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603b57973960e16ca28027211ccf46b2f13513c3
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <stdio.h>
25 #include <errno.h>
26 #include "pipe/p_defines.h"
27 #include "pipe/p_state.h"
28 #include "pipe/p_context.h"
29 #include "tgsi/tgsi_scan.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "tgsi/tgsi_util.h"
32 #include "util/u_blitter.h"
33 #include "util/u_double_list.h"
34 #include "util/u_transfer.h"
35 #include "util/u_surface.h"
36 #include "util/u_pack_color.h"
37 #include "util/u_memory.h"
38 #include "util/u_inlines.h"
39 #include "util/u_framebuffer.h"
40 #include "pipebuffer/pb_buffer.h"
41 #include "r600.h"
42 #include "evergreend.h"
43 #include "r600_resource.h"
44 #include "r600_shader.h"
45 #include "r600_pipe.h"
46 #include "r600_formats.h"
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(unsigned dim)
174 {
175 switch (dim) {
176 default:
177 case PIPE_TEXTURE_1D:
178 return V_030000_SQ_TEX_DIM_1D;
179 case PIPE_TEXTURE_1D_ARRAY:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY;
181 case PIPE_TEXTURE_2D:
182 case PIPE_TEXTURE_RECT:
183 return V_030000_SQ_TEX_DIM_2D;
184 case PIPE_TEXTURE_2D_ARRAY:
185 return V_030000_SQ_TEX_DIM_2D_ARRAY;
186 case PIPE_TEXTURE_3D:
187 return V_030000_SQ_TEX_DIM_3D;
188 case PIPE_TEXTURE_CUBE:
189 return V_030000_SQ_TEX_DIM_CUBEMAP;
190 }
191 }
192
193 static uint32_t r600_translate_dbformat(enum pipe_format format)
194 {
195 switch (format) {
196 case PIPE_FORMAT_Z16_UNORM:
197 return V_028040_Z_16;
198 case PIPE_FORMAT_Z24X8_UNORM:
199 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
200 return V_028040_Z_24;
201 case PIPE_FORMAT_Z32_FLOAT:
202 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
203 return V_028040_Z_32_FLOAT;
204 default:
205 return ~0U;
206 }
207 }
208
209 static uint32_t r600_translate_colorswap(enum pipe_format format)
210 {
211 switch (format) {
212 /* 8-bit buffers. */
213 case PIPE_FORMAT_L4A4_UNORM:
214 case PIPE_FORMAT_A4R4_UNORM:
215 return V_028C70_SWAP_ALT;
216
217 case PIPE_FORMAT_A8_UNORM:
218 case PIPE_FORMAT_A8_SNORM:
219 case PIPE_FORMAT_A8_UINT:
220 case PIPE_FORMAT_A8_SINT:
221 case PIPE_FORMAT_A16_UNORM:
222 case PIPE_FORMAT_A16_SNORM:
223 case PIPE_FORMAT_A16_UINT:
224 case PIPE_FORMAT_A16_SINT:
225 case PIPE_FORMAT_A16_FLOAT:
226 case PIPE_FORMAT_A32_UINT:
227 case PIPE_FORMAT_A32_SINT:
228 case PIPE_FORMAT_A32_FLOAT:
229 case PIPE_FORMAT_R4A4_UNORM:
230 return V_028C70_SWAP_ALT_REV;
231 case PIPE_FORMAT_I8_UNORM:
232 case PIPE_FORMAT_I8_SNORM:
233 case PIPE_FORMAT_I8_UINT:
234 case PIPE_FORMAT_I8_SINT:
235 case PIPE_FORMAT_I16_UNORM:
236 case PIPE_FORMAT_I16_SNORM:
237 case PIPE_FORMAT_I16_UINT:
238 case PIPE_FORMAT_I16_SINT:
239 case PIPE_FORMAT_I16_FLOAT:
240 case PIPE_FORMAT_I32_UINT:
241 case PIPE_FORMAT_I32_SINT:
242 case PIPE_FORMAT_I32_FLOAT:
243 case PIPE_FORMAT_L8_UNORM:
244 case PIPE_FORMAT_L8_SNORM:
245 case PIPE_FORMAT_L8_UINT:
246 case PIPE_FORMAT_L8_SINT:
247 case PIPE_FORMAT_L8_SRGB:
248 case PIPE_FORMAT_L16_UNORM:
249 case PIPE_FORMAT_L16_SNORM:
250 case PIPE_FORMAT_L16_UINT:
251 case PIPE_FORMAT_L16_SINT:
252 case PIPE_FORMAT_L16_FLOAT:
253 case PIPE_FORMAT_L32_UINT:
254 case PIPE_FORMAT_L32_SINT:
255 case PIPE_FORMAT_L32_FLOAT:
256 case PIPE_FORMAT_R8_UNORM:
257 case PIPE_FORMAT_R8_SNORM:
258 case PIPE_FORMAT_R8_UINT:
259 case PIPE_FORMAT_R8_SINT:
260 return V_028C70_SWAP_STD;
261
262 /* 16-bit buffers. */
263 case PIPE_FORMAT_B5G6R5_UNORM:
264 return V_028C70_SWAP_STD_REV;
265
266 case PIPE_FORMAT_B5G5R5A1_UNORM:
267 case PIPE_FORMAT_B5G5R5X1_UNORM:
268 return V_028C70_SWAP_ALT;
269
270 case PIPE_FORMAT_B4G4R4A4_UNORM:
271 case PIPE_FORMAT_B4G4R4X4_UNORM:
272 return V_028C70_SWAP_ALT;
273
274 case PIPE_FORMAT_Z16_UNORM:
275 return V_028C70_SWAP_STD;
276
277 case PIPE_FORMAT_L8A8_UNORM:
278 case PIPE_FORMAT_L8A8_SNORM:
279 case PIPE_FORMAT_L8A8_UINT:
280 case PIPE_FORMAT_L8A8_SINT:
281 case PIPE_FORMAT_L8A8_SRGB:
282 case PIPE_FORMAT_L16A16_UNORM:
283 case PIPE_FORMAT_L16A16_SNORM:
284 case PIPE_FORMAT_L16A16_UINT:
285 case PIPE_FORMAT_L16A16_SINT:
286 case PIPE_FORMAT_L16A16_FLOAT:
287 case PIPE_FORMAT_L32A32_UINT:
288 case PIPE_FORMAT_L32A32_SINT:
289 case PIPE_FORMAT_L32A32_FLOAT:
290 return V_028C70_SWAP_ALT;
291 case PIPE_FORMAT_R8G8_UNORM:
292 case PIPE_FORMAT_R8G8_SNORM:
293 case PIPE_FORMAT_R8G8_UINT:
294 case PIPE_FORMAT_R8G8_SINT:
295 return V_028C70_SWAP_STD;
296
297 case PIPE_FORMAT_R16_UNORM:
298 case PIPE_FORMAT_R16_SNORM:
299 case PIPE_FORMAT_R16_UINT:
300 case PIPE_FORMAT_R16_SINT:
301 case PIPE_FORMAT_R16_FLOAT:
302 return V_028C70_SWAP_STD;
303
304 /* 32-bit buffers. */
305 case PIPE_FORMAT_A8B8G8R8_SRGB:
306 return V_028C70_SWAP_STD_REV;
307 case PIPE_FORMAT_B8G8R8A8_SRGB:
308 return V_028C70_SWAP_ALT;
309
310 case PIPE_FORMAT_B8G8R8A8_UNORM:
311 case PIPE_FORMAT_B8G8R8X8_UNORM:
312 return V_028C70_SWAP_ALT;
313
314 case PIPE_FORMAT_A8R8G8B8_UNORM:
315 case PIPE_FORMAT_X8R8G8B8_UNORM:
316 return V_028C70_SWAP_ALT_REV;
317 case PIPE_FORMAT_R8G8B8A8_SNORM:
318 case PIPE_FORMAT_R8G8B8A8_UNORM:
319 case PIPE_FORMAT_R8G8B8A8_SINT:
320 case PIPE_FORMAT_R8G8B8A8_UINT:
321 case PIPE_FORMAT_R8G8B8X8_UNORM:
322 return V_028C70_SWAP_STD;
323
324 case PIPE_FORMAT_A8B8G8R8_UNORM:
325 case PIPE_FORMAT_X8B8G8R8_UNORM:
326 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
327 return V_028C70_SWAP_STD_REV;
328
329 case PIPE_FORMAT_Z24X8_UNORM:
330 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
331 return V_028C70_SWAP_STD;
332
333 case PIPE_FORMAT_X8Z24_UNORM:
334 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
335 return V_028C70_SWAP_STD;
336
337 case PIPE_FORMAT_R10G10B10A2_UNORM:
338 case PIPE_FORMAT_R10G10B10X2_SNORM:
339 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
340 return V_028C70_SWAP_STD;
341
342 case PIPE_FORMAT_B10G10R10A2_UNORM:
343 case PIPE_FORMAT_B10G10R10A2_UINT:
344 return V_028C70_SWAP_ALT;
345
346 case PIPE_FORMAT_R11G11B10_FLOAT:
347 case PIPE_FORMAT_R32_FLOAT:
348 case PIPE_FORMAT_R32_UINT:
349 case PIPE_FORMAT_R32_SINT:
350 case PIPE_FORMAT_Z32_FLOAT:
351 case PIPE_FORMAT_R16G16_FLOAT:
352 case PIPE_FORMAT_R16G16_UNORM:
353 case PIPE_FORMAT_R16G16_SNORM:
354 case PIPE_FORMAT_R16G16_UINT:
355 case PIPE_FORMAT_R16G16_SINT:
356 return V_028C70_SWAP_STD;
357
358 /* 64-bit buffers. */
359 case PIPE_FORMAT_R32G32_FLOAT:
360 case PIPE_FORMAT_R32G32_UINT:
361 case PIPE_FORMAT_R32G32_SINT:
362 case PIPE_FORMAT_R16G16B16A16_UNORM:
363 case PIPE_FORMAT_R16G16B16A16_SNORM:
364 case PIPE_FORMAT_R16G16B16A16_UINT:
365 case PIPE_FORMAT_R16G16B16A16_SINT:
366 case PIPE_FORMAT_R16G16B16A16_FLOAT:
367 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
368
369 /* 128-bit buffers. */
370 case PIPE_FORMAT_R32G32B32A32_FLOAT:
371 case PIPE_FORMAT_R32G32B32A32_SNORM:
372 case PIPE_FORMAT_R32G32B32A32_UNORM:
373 case PIPE_FORMAT_R32G32B32A32_SINT:
374 case PIPE_FORMAT_R32G32B32A32_UINT:
375 return V_028C70_SWAP_STD;
376 default:
377 R600_ERR("unsupported colorswap format %d\n", format);
378 return ~0U;
379 }
380 return ~0U;
381 }
382
383 static uint32_t r600_translate_colorformat(enum pipe_format format)
384 {
385 switch (format) {
386 /* 8-bit buffers. */
387 case PIPE_FORMAT_A8_UNORM:
388 case PIPE_FORMAT_A8_SNORM:
389 case PIPE_FORMAT_A8_UINT:
390 case PIPE_FORMAT_A8_SINT:
391 case PIPE_FORMAT_I8_UNORM:
392 case PIPE_FORMAT_I8_SNORM:
393 case PIPE_FORMAT_I8_UINT:
394 case PIPE_FORMAT_I8_SINT:
395 case PIPE_FORMAT_L8_UNORM:
396 case PIPE_FORMAT_L8_SNORM:
397 case PIPE_FORMAT_L8_UINT:
398 case PIPE_FORMAT_L8_SINT:
399 case PIPE_FORMAT_L8_SRGB:
400 case PIPE_FORMAT_R8_UNORM:
401 case PIPE_FORMAT_R8_SNORM:
402 case PIPE_FORMAT_R8_UINT:
403 case PIPE_FORMAT_R8_SINT:
404 return V_028C70_COLOR_8;
405
406 /* 16-bit buffers. */
407 case PIPE_FORMAT_B5G6R5_UNORM:
408 return V_028C70_COLOR_5_6_5;
409
410 case PIPE_FORMAT_B5G5R5A1_UNORM:
411 case PIPE_FORMAT_B5G5R5X1_UNORM:
412 return V_028C70_COLOR_1_5_5_5;
413
414 case PIPE_FORMAT_B4G4R4A4_UNORM:
415 case PIPE_FORMAT_B4G4R4X4_UNORM:
416 return V_028C70_COLOR_4_4_4_4;
417
418 case PIPE_FORMAT_Z16_UNORM:
419 return V_028C70_COLOR_16;
420
421 case PIPE_FORMAT_L8A8_UNORM:
422 case PIPE_FORMAT_L8A8_SNORM:
423 case PIPE_FORMAT_L8A8_UINT:
424 case PIPE_FORMAT_L8A8_SINT:
425 case PIPE_FORMAT_L8A8_SRGB:
426 case PIPE_FORMAT_R8G8_UNORM:
427 case PIPE_FORMAT_R8G8_SNORM:
428 case PIPE_FORMAT_R8G8_UINT:
429 case PIPE_FORMAT_R8G8_SINT:
430 return V_028C70_COLOR_8_8;
431
432 case PIPE_FORMAT_R16_UNORM:
433 case PIPE_FORMAT_R16_SNORM:
434 case PIPE_FORMAT_R16_UINT:
435 case PIPE_FORMAT_R16_SINT:
436 case PIPE_FORMAT_A16_UNORM:
437 case PIPE_FORMAT_A16_SNORM:
438 case PIPE_FORMAT_A16_UINT:
439 case PIPE_FORMAT_A16_SINT:
440 case PIPE_FORMAT_L16_UNORM:
441 case PIPE_FORMAT_L16_SNORM:
442 case PIPE_FORMAT_L16_UINT:
443 case PIPE_FORMAT_L16_SINT:
444 case PIPE_FORMAT_I16_UNORM:
445 case PIPE_FORMAT_I16_SNORM:
446 case PIPE_FORMAT_I16_UINT:
447 case PIPE_FORMAT_I16_SINT:
448 return V_028C70_COLOR_16;
449
450 case PIPE_FORMAT_R16_FLOAT:
451 case PIPE_FORMAT_A16_FLOAT:
452 case PIPE_FORMAT_L16_FLOAT:
453 case PIPE_FORMAT_I16_FLOAT:
454 return V_028C70_COLOR_16_FLOAT;
455
456 /* 32-bit buffers. */
457 case PIPE_FORMAT_A8B8G8R8_SRGB:
458 case PIPE_FORMAT_A8B8G8R8_UNORM:
459 case PIPE_FORMAT_A8R8G8B8_UNORM:
460 case PIPE_FORMAT_B8G8R8A8_SRGB:
461 case PIPE_FORMAT_B8G8R8A8_UNORM:
462 case PIPE_FORMAT_B8G8R8X8_UNORM:
463 case PIPE_FORMAT_R8G8B8A8_SNORM:
464 case PIPE_FORMAT_R8G8B8A8_UNORM:
465 case PIPE_FORMAT_R8G8B8X8_UNORM:
466 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
467 case PIPE_FORMAT_X8B8G8R8_UNORM:
468 case PIPE_FORMAT_X8R8G8B8_UNORM:
469 case PIPE_FORMAT_R8G8B8_UNORM:
470 case PIPE_FORMAT_R8G8B8A8_SINT:
471 case PIPE_FORMAT_R8G8B8A8_UINT:
472 return V_028C70_COLOR_8_8_8_8;
473
474 case PIPE_FORMAT_R10G10B10A2_UNORM:
475 case PIPE_FORMAT_R10G10B10X2_SNORM:
476 case PIPE_FORMAT_B10G10R10A2_UNORM:
477 case PIPE_FORMAT_B10G10R10A2_UINT:
478 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
479 return V_028C70_COLOR_2_10_10_10;
480
481 case PIPE_FORMAT_Z24X8_UNORM:
482 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
483 return V_028C70_COLOR_8_24;
484
485 case PIPE_FORMAT_X8Z24_UNORM:
486 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
487 return V_028C70_COLOR_24_8;
488
489 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
490 return V_028C70_COLOR_X24_8_32_FLOAT;
491
492 case PIPE_FORMAT_R32_UINT:
493 case PIPE_FORMAT_R32_SINT:
494 case PIPE_FORMAT_A32_UINT:
495 case PIPE_FORMAT_A32_SINT:
496 case PIPE_FORMAT_L32_UINT:
497 case PIPE_FORMAT_L32_SINT:
498 case PIPE_FORMAT_I32_UINT:
499 case PIPE_FORMAT_I32_SINT:
500 return V_028C70_COLOR_32;
501
502 case PIPE_FORMAT_R32_FLOAT:
503 case PIPE_FORMAT_A32_FLOAT:
504 case PIPE_FORMAT_L32_FLOAT:
505 case PIPE_FORMAT_I32_FLOAT:
506 case PIPE_FORMAT_Z32_FLOAT:
507 return V_028C70_COLOR_32_FLOAT;
508
509 case PIPE_FORMAT_R16G16_FLOAT:
510 case PIPE_FORMAT_L16A16_FLOAT:
511 return V_028C70_COLOR_16_16_FLOAT;
512
513 case PIPE_FORMAT_R16G16_UNORM:
514 case PIPE_FORMAT_R16G16_SNORM:
515 case PIPE_FORMAT_R16G16_UINT:
516 case PIPE_FORMAT_R16G16_SINT:
517 case PIPE_FORMAT_L16A16_UNORM:
518 case PIPE_FORMAT_L16A16_SNORM:
519 case PIPE_FORMAT_L16A16_UINT:
520 case PIPE_FORMAT_L16A16_SINT:
521 return V_028C70_COLOR_16_16;
522
523 case PIPE_FORMAT_R11G11B10_FLOAT:
524 return V_028C70_COLOR_10_11_11_FLOAT;
525
526 /* 64-bit buffers. */
527 case PIPE_FORMAT_R16G16B16A16_UINT:
528 case PIPE_FORMAT_R16G16B16A16_SINT:
529 case PIPE_FORMAT_R16G16B16A16_UNORM:
530 case PIPE_FORMAT_R16G16B16A16_SNORM:
531 return V_028C70_COLOR_16_16_16_16;
532
533 case PIPE_FORMAT_R16G16B16_FLOAT:
534 case PIPE_FORMAT_R16G16B16A16_FLOAT:
535 return V_028C70_COLOR_16_16_16_16_FLOAT;
536
537 case PIPE_FORMAT_R32G32_FLOAT:
538 case PIPE_FORMAT_L32A32_FLOAT:
539 return V_028C70_COLOR_32_32_FLOAT;
540
541 case PIPE_FORMAT_R32G32_SINT:
542 case PIPE_FORMAT_R32G32_UINT:
543 case PIPE_FORMAT_L32A32_UINT:
544 case PIPE_FORMAT_L32A32_SINT:
545 return V_028C70_COLOR_32_32;
546
547 /* 96-bit buffers. */
548 case PIPE_FORMAT_R32G32B32_FLOAT:
549 return V_028C70_COLOR_32_32_32_FLOAT;
550
551 /* 128-bit buffers. */
552 case PIPE_FORMAT_R32G32B32A32_SNORM:
553 case PIPE_FORMAT_R32G32B32A32_UNORM:
554 case PIPE_FORMAT_R32G32B32A32_SINT:
555 case PIPE_FORMAT_R32G32B32A32_UINT:
556 return V_028C70_COLOR_32_32_32_32;
557 case PIPE_FORMAT_R32G32B32A32_FLOAT:
558 return V_028C70_COLOR_32_32_32_32_FLOAT;
559
560 /* YUV buffers. */
561 case PIPE_FORMAT_UYVY:
562 case PIPE_FORMAT_YUYV:
563 default:
564 return ~0U; /* Unsupported. */
565 }
566 }
567
568 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
569 {
570 if (R600_BIG_ENDIAN) {
571 switch(colorformat) {
572
573 /* 8-bit buffers. */
574 case V_028C70_COLOR_8:
575 return ENDIAN_NONE;
576
577 /* 16-bit buffers. */
578 case V_028C70_COLOR_5_6_5:
579 case V_028C70_COLOR_1_5_5_5:
580 case V_028C70_COLOR_4_4_4_4:
581 case V_028C70_COLOR_16:
582 case V_028C70_COLOR_8_8:
583 return ENDIAN_8IN16;
584
585 /* 32-bit buffers. */
586 case V_028C70_COLOR_8_8_8_8:
587 case V_028C70_COLOR_2_10_10_10:
588 case V_028C70_COLOR_8_24:
589 case V_028C70_COLOR_24_8:
590 case V_028C70_COLOR_32_FLOAT:
591 case V_028C70_COLOR_16_16_FLOAT:
592 case V_028C70_COLOR_16_16:
593 return ENDIAN_8IN32;
594
595 /* 64-bit buffers. */
596 case V_028C70_COLOR_16_16_16_16:
597 case V_028C70_COLOR_16_16_16_16_FLOAT:
598 return ENDIAN_8IN16;
599
600 case V_028C70_COLOR_32_32_FLOAT:
601 case V_028C70_COLOR_32_32:
602 case V_028C70_COLOR_X24_8_32_FLOAT:
603 return ENDIAN_8IN32;
604
605 /* 96-bit buffers. */
606 case V_028C70_COLOR_32_32_32_FLOAT:
607 /* 128-bit buffers. */
608 case V_028C70_COLOR_32_32_32_32_FLOAT:
609 case V_028C70_COLOR_32_32_32_32:
610 return ENDIAN_8IN32;
611 default:
612 return ENDIAN_NONE; /* Unsupported. */
613 }
614 } else {
615 return ENDIAN_NONE;
616 }
617 }
618
619 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
620 {
621 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
622 }
623
624 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
625 {
626 return r600_translate_colorformat(format) != ~0U &&
627 r600_translate_colorswap(format) != ~0U;
628 }
629
630 static bool r600_is_zs_format_supported(enum pipe_format format)
631 {
632 return r600_translate_dbformat(format) != ~0U;
633 }
634
635 boolean evergreen_is_format_supported(struct pipe_screen *screen,
636 enum pipe_format format,
637 enum pipe_texture_target target,
638 unsigned sample_count,
639 unsigned usage)
640 {
641 unsigned retval = 0;
642
643 if (target >= PIPE_MAX_TEXTURE_TYPES) {
644 R600_ERR("r600: unsupported texture type %d\n", target);
645 return FALSE;
646 }
647
648 if (!util_format_is_supported(format, usage))
649 return FALSE;
650
651 /* Multisample */
652 if (sample_count > 1)
653 return FALSE;
654
655 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
656 r600_is_sampler_format_supported(screen, format)) {
657 retval |= PIPE_BIND_SAMPLER_VIEW;
658 }
659
660 if ((usage & (PIPE_BIND_RENDER_TARGET |
661 PIPE_BIND_DISPLAY_TARGET |
662 PIPE_BIND_SCANOUT |
663 PIPE_BIND_SHARED)) &&
664 r600_is_colorbuffer_format_supported(format)) {
665 retval |= usage &
666 (PIPE_BIND_RENDER_TARGET |
667 PIPE_BIND_DISPLAY_TARGET |
668 PIPE_BIND_SCANOUT |
669 PIPE_BIND_SHARED);
670 }
671
672 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
673 r600_is_zs_format_supported(format)) {
674 retval |= PIPE_BIND_DEPTH_STENCIL;
675 }
676
677 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
678 r600_is_vertex_format_supported(format)) {
679 retval |= PIPE_BIND_VERTEX_BUFFER;
680 }
681
682 if (usage & PIPE_BIND_TRANSFER_READ)
683 retval |= PIPE_BIND_TRANSFER_READ;
684 if (usage & PIPE_BIND_TRANSFER_WRITE)
685 retval |= PIPE_BIND_TRANSFER_WRITE;
686
687 return retval == usage;
688 }
689
690 static void *evergreen_create_blend_state(struct pipe_context *ctx,
691 const struct pipe_blend_state *state)
692 {
693 struct r600_context *rctx = (struct r600_context *)ctx;
694 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
695 struct r600_pipe_state *rstate;
696 uint32_t color_control, target_mask;
697 /* XXX there is more then 8 framebuffer */
698 unsigned blend_cntl[8];
699
700 if (blend == NULL) {
701 return NULL;
702 }
703
704 rstate = &blend->rstate;
705
706 rstate->id = R600_PIPE_STATE_BLEND;
707
708 target_mask = 0;
709 color_control = S_028808_MODE(1);
710 if (state->logicop_enable) {
711 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
712 } else {
713 color_control |= (0xcc << 16);
714 }
715 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
716 if (state->independent_blend_enable) {
717 for (int i = 0; i < 8; i++) {
718 target_mask |= (state->rt[i].colormask << (4 * i));
719 }
720 } else {
721 for (int i = 0; i < 8; i++) {
722 target_mask |= (state->rt[0].colormask << (4 * i));
723 }
724 }
725 blend->cb_target_mask = target_mask;
726
727 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
728 color_control, NULL, 0);
729
730 for (int i = 0; i < 8; i++) {
731 /* state->rt entries > 0 only written if independent blending */
732 const int j = state->independent_blend_enable ? i : 0;
733
734 unsigned eqRGB = state->rt[j].rgb_func;
735 unsigned srcRGB = state->rt[j].rgb_src_factor;
736 unsigned dstRGB = state->rt[j].rgb_dst_factor;
737 unsigned eqA = state->rt[j].alpha_func;
738 unsigned srcA = state->rt[j].alpha_src_factor;
739 unsigned dstA = state->rt[j].alpha_dst_factor;
740
741 blend_cntl[i] = 0;
742 if (!state->rt[j].blend_enable)
743 continue;
744
745 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
746 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
747 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
748 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
749
750 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
751 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
752 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
753 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
754 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
755 }
756 }
757 for (int i = 0; i < 8; i++) {
758 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], NULL, 0);
759 }
760
761 return rstate;
762 }
763
764 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
765 const struct pipe_depth_stencil_alpha_state *state)
766 {
767 struct r600_context *rctx = (struct r600_context *)ctx;
768 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
769 unsigned db_depth_control, alpha_test_control, alpha_ref;
770 unsigned db_render_control;
771 struct r600_pipe_state *rstate;
772
773 if (dsa == NULL) {
774 return NULL;
775 }
776
777 dsa->valuemask[0] = state->stencil[0].valuemask;
778 dsa->valuemask[1] = state->stencil[1].valuemask;
779 dsa->writemask[0] = state->stencil[0].writemask;
780 dsa->writemask[1] = state->stencil[1].writemask;
781
782 rstate = &dsa->rstate;
783
784 rstate->id = R600_PIPE_STATE_DSA;
785 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
786 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
787 S_028800_ZFUNC(state->depth.func);
788
789 /* stencil */
790 if (state->stencil[0].enabled) {
791 db_depth_control |= S_028800_STENCIL_ENABLE(1);
792 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
793 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
794 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
795 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
796
797 if (state->stencil[1].enabled) {
798 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
799 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
800 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
801 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
802 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
803 }
804 }
805
806 /* alpha */
807 alpha_test_control = 0;
808 alpha_ref = 0;
809 if (state->alpha.enabled) {
810 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
811 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
812 alpha_ref = fui(state->alpha.ref_value);
813 }
814 dsa->alpha_ref = alpha_ref;
815
816 /* misc */
817 db_render_control = 0;
818 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
819 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
820 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0);
821 return rstate;
822 }
823
824 static void *evergreen_create_rs_state(struct pipe_context *ctx,
825 const struct pipe_rasterizer_state *state)
826 {
827 struct r600_context *rctx = (struct r600_context *)ctx;
828 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
829 struct r600_pipe_state *rstate;
830 unsigned tmp;
831 unsigned prov_vtx = 1, polygon_dual_mode;
832 float psize_min, psize_max;
833
834 if (rs == NULL) {
835 return NULL;
836 }
837
838 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
839 state->fill_back != PIPE_POLYGON_MODE_FILL);
840
841 if (state->flatshade_first)
842 prov_vtx = 0;
843
844 rstate = &rs->rstate;
845 rs->rasterizer_discard = state->rasterizer_discard;
846 rs->flatshade = state->flatshade;
847 rs->sprite_coord_enable = state->sprite_coord_enable;
848 rs->two_side = state->light_twoside;
849 rs->clip_plane_enable = state->clip_plane_enable;
850 rs->pa_sc_line_stipple = state->line_stipple_enable ?
851 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
852 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
853 rs->pa_cl_clip_cntl =
854 S_028810_PS_UCP_MODE(3) |
855 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
856 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
857 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
858
859 /* offset */
860 rs->offset_units = state->offset_units;
861 rs->offset_scale = state->offset_scale * 12.0f;
862
863 rstate->id = R600_PIPE_STATE_RASTERIZER;
864 tmp = S_0286D4_FLAT_SHADE_ENA(1);
865 if (state->sprite_coord_enable) {
866 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
867 S_0286D4_PNT_SPRITE_OVRD_X(2) |
868 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
869 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
870 S_0286D4_PNT_SPRITE_OVRD_W(1);
871 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
872 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
873 }
874 }
875 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
876
877 /* point size 12.4 fixed point */
878 tmp = (unsigned)(state->point_size * 8.0);
879 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
880
881 if (state->point_size_per_vertex) {
882 psize_min = util_get_min_point_size(state);
883 psize_max = 8192;
884 } else {
885 /* Force the point size to be as if the vertex output was disabled. */
886 psize_min = state->point_size;
887 psize_max = state->point_size;
888 }
889 /* Divide by two, because 0.5 = 1 pixel. */
890 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
891 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
892 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
893 NULL, 0);
894
895 tmp = (unsigned)state->line_width * 8;
896 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
897 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
898 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
899 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
900 NULL, 0);
901
902 if (rctx->chip_class == CAYMAN) {
903 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
904 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
905 NULL, 0);
906 } else {
907 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
908 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
909 NULL, 0);
910 }
911 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
912 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
913 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
914 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
915 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
916 S_028814_FACE(!state->front_ccw) |
917 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
918 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
919 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
920 S_028814_POLY_MODE(polygon_dual_mode) |
921 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
922 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)),
923 NULL, 0);
924 return rstate;
925 }
926
927 void evergreen_set_rasterizer_discard(struct pipe_context *ctx, boolean discard)
928 {
929 struct r600_context *rctx = (struct r600_context*)ctx;
930
931 if (discard != rctx->atom_eg_strmout_config.rasterizer_discard) {
932 rctx->atom_eg_strmout_config.rasterizer_discard = discard;
933 r600_atom_dirty(rctx, &rctx->atom_eg_strmout_config.atom);
934 }
935 }
936
937 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
938 const struct pipe_sampler_state *state)
939 {
940 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
941 union util_color uc;
942 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
943
944 if (rstate == NULL) {
945 return NULL;
946 }
947
948 rstate->id = R600_PIPE_STATE_SAMPLER;
949 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
950 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
951 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
952 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
953 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
954 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
955 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
956 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
957 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
958 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
959 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
960 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
961 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
962 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
963 NULL, 0);
964 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
965 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
966 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
967 S_03C008_TYPE(1),
968 NULL, 0);
969
970 if (uc.ui) {
971 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
972 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
973 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
974 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
975 }
976 return rstate;
977 }
978
979 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
980 struct pipe_resource *texture,
981 const struct pipe_sampler_view *state)
982 {
983 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
984 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
985 struct r600_pipe_resource_state *rstate;
986 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
987 unsigned format, endian;
988 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
989 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
990 unsigned height, depth, width;
991 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
992
993 if (view == NULL)
994 return NULL;
995 rstate = &view->state;
996
997 /* initialize base object */
998 view->base = *state;
999 view->base.texture = NULL;
1000 pipe_reference(NULL, &texture->reference);
1001 view->base.texture = texture;
1002 view->base.reference.count = 1;
1003 view->base.context = ctx;
1004
1005 swizzle[0] = state->swizzle_r;
1006 swizzle[1] = state->swizzle_g;
1007 swizzle[2] = state->swizzle_b;
1008 swizzle[3] = state->swizzle_a;
1009
1010 format = r600_translate_texformat(ctx->screen, state->format,
1011 swizzle,
1012 &word4, &yuv_format);
1013 if (format == ~0) {
1014 format = 0;
1015 }
1016
1017 if (tmp->is_depth && !tmp->is_flushing_texture) {
1018 r600_texture_depth_flush(ctx, texture, TRUE);
1019 tmp = tmp->flushed_depth_texture;
1020 }
1021
1022 endian = r600_colorformat_endian_swap(format);
1023
1024 if (!rscreen->use_surface_alloc) {
1025 height = texture->height0;
1026 depth = texture->depth0;
1027 width = texture->width0;
1028 pitch = align(tmp->pitch_in_blocks[0] *
1029 util_format_get_blockwidth(state->format), 8);
1030 array_mode = tmp->array_mode[0];
1031 tile_type = tmp->tile_type;
1032 tile_split = 0;
1033 macro_aspect = 0;
1034 bankw = 0;
1035 bankh = 0;
1036 } else {
1037 width = tmp->surface.level[0].npix_x;
1038 height = tmp->surface.level[0].npix_y;
1039 depth = tmp->surface.level[0].npix_z;
1040 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1041 tile_type = tmp->tile_type;
1042
1043 switch (tmp->surface.level[0].mode) {
1044 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1045 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1046 break;
1047 case RADEON_SURF_MODE_2D:
1048 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1049 break;
1050 case RADEON_SURF_MODE_1D:
1051 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1052 break;
1053 case RADEON_SURF_MODE_LINEAR:
1054 default:
1055 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1056 break;
1057 }
1058 tile_split = tmp->surface.tile_split;
1059 macro_aspect = tmp->surface.mtilea;
1060 bankw = tmp->surface.bankw;
1061 bankh = tmp->surface.bankh;
1062 tile_split = eg_tile_split(tile_split);
1063 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1064 bankw = eg_bank_wh(bankw);
1065 bankh = eg_bank_wh(bankh);
1066 }
1067 /* 128 bit formats require tile type = 1 */
1068 if (rscreen->chip_class == CAYMAN) {
1069 if (util_format_get_blocksize(state->format) >= 16)
1070 tile_type = 1;
1071 }
1072 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1073
1074 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1075 height = 1;
1076 depth = texture->array_size;
1077 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1078 depth = texture->array_size;
1079 }
1080
1081 rstate->bo[0] = &tmp->resource;
1082 rstate->bo[1] = &tmp->resource;
1083 rstate->bo_usage[0] = RADEON_USAGE_READ;
1084 rstate->bo_usage[1] = RADEON_USAGE_READ;
1085
1086 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1087 S_030000_PITCH((pitch / 8) - 1) |
1088 S_030000_TEX_WIDTH(width - 1));
1089 if (rscreen->chip_class == CAYMAN)
1090 rstate->val[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1091 else
1092 rstate->val[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1093 rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1094 S_030004_TEX_DEPTH(depth - 1) |
1095 S_030004_ARRAY_MODE(array_mode));
1096 rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1097 if (state->u.tex.last_level) {
1098 rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1099 } else {
1100 rstate->val[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1101 }
1102 rstate->val[4] = (word4 |
1103 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1104 S_030010_ENDIAN_SWAP(endian) |
1105 S_030010_BASE_LEVEL(state->u.tex.first_level));
1106 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1107 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1108 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1109 /* aniso max 16 samples */
1110 rstate->val[6] = (S_030018_MAX_ANISO(4)) |
1111 (S_030018_TILE_SPLIT(tile_split));
1112 rstate->val[7] = S_03001C_DATA_FORMAT(format) |
1113 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1114 S_03001C_BANK_WIDTH(bankw) |
1115 S_03001C_BANK_HEIGHT(bankh) |
1116 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1117 S_03001C_NUM_BANKS(nbanks);
1118
1119 return &view->base;
1120 }
1121
1122 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1123 struct pipe_sampler_view **views)
1124 {
1125 struct r600_context *rctx = (struct r600_context *)ctx;
1126 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1127
1128 for (int i = 0; i < count; i++) {
1129 if (resource[i]) {
1130 r600_context_pipe_state_set_vs_resource(rctx, &resource[i]->state,
1131 i + R600_MAX_CONST_BUFFERS);
1132 }
1133 }
1134 }
1135
1136 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1137 struct pipe_sampler_view **views)
1138 {
1139 struct r600_context *rctx = (struct r600_context *)ctx;
1140 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1141 int i;
1142 int has_depth = 0;
1143
1144 for (i = 0; i < count; i++) {
1145 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1146 if (resource[i]) {
1147 if (((struct r600_resource_texture *)resource[i]->base.texture)->is_depth)
1148 has_depth = 1;
1149 r600_context_pipe_state_set_ps_resource(rctx, &resource[i]->state,
1150 i + R600_MAX_CONST_BUFFERS);
1151 } else
1152 r600_context_pipe_state_set_ps_resource(rctx, NULL,
1153 i + R600_MAX_CONST_BUFFERS);
1154
1155 pipe_sampler_view_reference(
1156 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1157 views[i]);
1158 } else {
1159 if (resource[i]) {
1160 if (((struct r600_resource_texture *)resource[i]->base.texture)->is_depth)
1161 has_depth = 1;
1162 }
1163 }
1164 }
1165 for (i = count; i < NUM_TEX_UNITS; i++) {
1166 if (rctx->ps_samplers.views[i]) {
1167 r600_context_pipe_state_set_ps_resource(rctx, NULL,
1168 i + R600_MAX_CONST_BUFFERS);
1169 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1170 }
1171 }
1172 rctx->have_depth_texture = has_depth;
1173 rctx->ps_samplers.n_views = count;
1174 }
1175
1176 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1177 {
1178 struct r600_context *rctx = (struct r600_context *)ctx;
1179 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1180
1181 if (count)
1182 r600_inval_texture_cache(rctx);
1183
1184 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1185 rctx->ps_samplers.n_samplers = count;
1186
1187 for (int i = 0; i < count; i++) {
1188 evergreen_context_pipe_state_set_ps_sampler(rctx, rstates[i], i);
1189 }
1190 }
1191
1192 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1193 {
1194 struct r600_context *rctx = (struct r600_context *)ctx;
1195 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1196
1197 if (count)
1198 r600_inval_texture_cache(rctx);
1199
1200 for (int i = 0; i < count; i++) {
1201 evergreen_context_pipe_state_set_vs_sampler(rctx, rstates[i], i);
1202 }
1203 }
1204
1205 static void evergreen_set_clip_state(struct pipe_context *ctx,
1206 const struct pipe_clip_state *state)
1207 {
1208 struct r600_context *rctx = (struct r600_context *)ctx;
1209 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1210 struct pipe_resource *cbuf;
1211
1212 if (rstate == NULL)
1213 return;
1214
1215 rctx->clip = *state;
1216 rstate->id = R600_PIPE_STATE_CLIP;
1217 for (int i = 0; i < 6; i++) {
1218 r600_pipe_state_add_reg(rstate,
1219 R_0285BC_PA_CL_UCP0_X + i * 16,
1220 fui(state->ucp[i][0]), NULL, 0);
1221 r600_pipe_state_add_reg(rstate,
1222 R_0285C0_PA_CL_UCP0_Y + i * 16,
1223 fui(state->ucp[i][1]) , NULL, 0);
1224 r600_pipe_state_add_reg(rstate,
1225 R_0285C4_PA_CL_UCP0_Z + i * 16,
1226 fui(state->ucp[i][2]), NULL, 0);
1227 r600_pipe_state_add_reg(rstate,
1228 R_0285C8_PA_CL_UCP0_W + i * 16,
1229 fui(state->ucp[i][3]), NULL, 0);
1230 }
1231
1232 free(rctx->states[R600_PIPE_STATE_CLIP]);
1233 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1234 r600_context_pipe_state_set(rctx, rstate);
1235
1236 cbuf = pipe_user_buffer_create(ctx->screen,
1237 state->ucp,
1238 4*4*8, /* 8*4 floats */
1239 PIPE_BIND_CONSTANT_BUFFER);
1240 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
1241 pipe_resource_reference(&cbuf, NULL);
1242 }
1243
1244 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1245 const struct pipe_poly_stipple *state)
1246 {
1247 }
1248
1249 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1250 {
1251 }
1252
1253 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1254 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1255 uint32_t *tl, uint32_t *br)
1256 {
1257 /* EG hw workaround */
1258 if (br_x == 0)
1259 tl_x = 1;
1260 if (br_y == 0)
1261 tl_y = 1;
1262
1263 /* cayman hw workaround */
1264 if (rctx->chip_class == CAYMAN) {
1265 if (br_x == 1 && br_y == 1)
1266 br_x = 2;
1267 }
1268
1269 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1270 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1271 }
1272
1273 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1274 const struct pipe_scissor_state *state)
1275 {
1276 struct r600_context *rctx = (struct r600_context *)ctx;
1277 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1278 uint32_t tl, br;
1279
1280 if (rstate == NULL)
1281 return;
1282
1283 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1284
1285 rstate->id = R600_PIPE_STATE_SCISSOR;
1286 r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl, NULL, 0);
1287 r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br, NULL, 0);
1288
1289 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1290 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1291 r600_context_pipe_state_set(rctx, rstate);
1292 }
1293
1294 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1295 const struct pipe_viewport_state *state)
1296 {
1297 struct r600_context *rctx = (struct r600_context *)ctx;
1298 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1299
1300 if (rstate == NULL)
1301 return;
1302
1303 rctx->viewport = *state;
1304 rstate->id = R600_PIPE_STATE_VIEWPORT;
1305 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
1306 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
1307 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
1308 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
1309 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
1310 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
1311
1312 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1313 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1314 r600_context_pipe_state_set(rctx, rstate);
1315 }
1316
1317 static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1318 const struct pipe_framebuffer_state *state, int cb)
1319 {
1320 struct r600_screen *rscreen = rctx->screen;
1321 struct r600_resource_texture *rtex;
1322 struct r600_surface *surf;
1323 unsigned level = state->cbufs[cb]->u.tex.level;
1324 unsigned pitch, slice;
1325 unsigned color_info, color_attrib;
1326 unsigned format, swap, ntype, endian;
1327 uint64_t offset;
1328 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1329 const struct util_format_description *desc;
1330 int i;
1331 unsigned blend_clamp = 0, blend_bypass = 0;
1332
1333 surf = (struct r600_surface *)state->cbufs[cb];
1334 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1335
1336 if (rtex->is_depth)
1337 rctx->have_depth_fb = TRUE;
1338
1339 if (rtex->is_depth && !rtex->is_flushing_texture) {
1340 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1341 rtex = rtex->flushed_depth_texture;
1342 }
1343
1344 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1345 if (!rscreen->use_surface_alloc) {
1346 offset = r600_texture_get_offset(rtex,
1347 level, state->cbufs[cb]->u.tex.first_layer);
1348 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1349 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1350 if (slice) {
1351 slice = slice - 1;
1352 }
1353 color_info = S_028C70_ARRAY_MODE(rtex->array_mode[level]);
1354 tile_split = 0;
1355 macro_aspect = 0;
1356 bankw = 0;
1357 bankh = 0;
1358 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1359 tile_type = rtex->tile_type;
1360 } else {
1361 /* workaround for linear buffers */
1362 tile_type = 1;
1363 }
1364 } else {
1365 offset = rtex->surface.level[level].offset;
1366 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1367 offset += rtex->surface.level[level].slice_size *
1368 state->cbufs[cb]->u.tex.first_layer;
1369 }
1370 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1371 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1372 if (slice) {
1373 slice = slice - 1;
1374 }
1375 color_info = 0;
1376 switch (rtex->surface.level[level].mode) {
1377 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1378 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1379 tile_type = 1;
1380 break;
1381 case RADEON_SURF_MODE_1D:
1382 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1383 tile_type = rtex->tile_type;
1384 break;
1385 case RADEON_SURF_MODE_2D:
1386 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1387 tile_type = rtex->tile_type;
1388 break;
1389 case RADEON_SURF_MODE_LINEAR:
1390 default:
1391 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1392 tile_type = 1;
1393 break;
1394 }
1395 tile_split = rtex->surface.tile_split;
1396 macro_aspect = rtex->surface.mtilea;
1397 bankw = rtex->surface.bankw;
1398 bankh = rtex->surface.bankh;
1399 tile_split = eg_tile_split(tile_split);
1400 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1401 bankw = eg_bank_wh(bankw);
1402 bankh = eg_bank_wh(bankh);
1403 }
1404 /* 128 bit formats require tile type = 1 */
1405 if (rscreen->chip_class == CAYMAN) {
1406 if (util_format_get_blocksize(surf->base.format) >= 16)
1407 tile_type = 1;
1408 }
1409 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1410 desc = util_format_description(surf->base.format);
1411 for (i = 0; i < 4; i++) {
1412 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1413 break;
1414 }
1415 }
1416
1417 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1418 S_028C74_NUM_BANKS(nbanks) |
1419 S_028C74_BANK_WIDTH(bankw) |
1420 S_028C74_BANK_HEIGHT(bankh) |
1421 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1422 S_028C74_NON_DISP_TILING_ORDER(tile_type);
1423
1424 ntype = V_028C70_NUMBER_UNORM;
1425 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1426 ntype = V_028C70_NUMBER_SRGB;
1427 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1428 if (desc->channel[i].normalized)
1429 ntype = V_028C70_NUMBER_SNORM;
1430 else if (desc->channel[i].pure_integer)
1431 ntype = V_028C70_NUMBER_SINT;
1432 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1433 if (desc->channel[i].normalized)
1434 ntype = V_028C70_NUMBER_UNORM;
1435 else if (desc->channel[i].pure_integer)
1436 ntype = V_028C70_NUMBER_UINT;
1437 }
1438
1439 format = r600_translate_colorformat(surf->base.format);
1440 swap = r600_translate_colorswap(surf->base.format);
1441 if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1442 endian = ENDIAN_NONE;
1443 } else {
1444 endian = r600_colorformat_endian_swap(format);
1445 }
1446
1447 /* blend clamp should be set for all NORM/SRGB types */
1448 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1449 ntype == V_028C70_NUMBER_SRGB)
1450 blend_clamp = 1;
1451
1452 /* set blend bypass according to docs if SINT/UINT or
1453 8/24 COLOR variants */
1454 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1455 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1456 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1457 blend_clamp = 0;
1458 blend_bypass = 1;
1459 }
1460
1461 color_info |= S_028C70_FORMAT(format) |
1462 S_028C70_COMP_SWAP(swap) |
1463 S_028C70_BLEND_CLAMP(blend_clamp) |
1464 S_028C70_BLEND_BYPASS(blend_bypass) |
1465 S_028C70_NUMBER_TYPE(ntype) |
1466 S_028C70_ENDIAN(endian);
1467
1468 /* EXPORT_NORM is an optimzation that can be enabled for better
1469 * performance in certain cases.
1470 * EXPORT_NORM can be enabled if:
1471 * - 11-bit or smaller UNORM/SNORM/SRGB
1472 * - 16-bit or smaller FLOAT
1473 */
1474 /* XXX: This should probably be the same for all CBs if we want
1475 * useful alpha tests. */
1476 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1477 ((desc->channel[i].size < 12 &&
1478 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1479 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1480 (desc->channel[i].size < 17 &&
1481 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1482 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1483 rctx->export_16bpc = true;
1484 } else {
1485 rctx->export_16bpc = false;
1486 }
1487 rctx->alpha_ref_dirty = true;
1488
1489
1490 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1491 offset >>= 8;
1492
1493 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1494 r600_pipe_state_add_reg(rstate,
1495 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1496 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1497 r600_pipe_state_add_reg(rstate,
1498 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1499 0x0, NULL, 0);
1500 r600_pipe_state_add_reg(rstate,
1501 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1502 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1503 r600_pipe_state_add_reg(rstate,
1504 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1505 S_028C64_PITCH_TILE_MAX(pitch),
1506 NULL, 0);
1507 r600_pipe_state_add_reg(rstate,
1508 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1509 S_028C68_SLICE_TILE_MAX(slice),
1510 NULL, 0);
1511 if (!rscreen->use_surface_alloc) {
1512 r600_pipe_state_add_reg(rstate,
1513 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1514 0x00000000, NULL, 0);
1515 } else {
1516 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1517 r600_pipe_state_add_reg(rstate,
1518 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1519 0x00000000, NULL, 0);
1520 } else {
1521 r600_pipe_state_add_reg(rstate,
1522 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1523 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1524 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
1525 NULL, 0);
1526 }
1527 }
1528 r600_pipe_state_add_reg(rstate,
1529 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1530 color_attrib,
1531 &rtex->resource, RADEON_USAGE_READWRITE);
1532 }
1533
1534 static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1535 const struct pipe_framebuffer_state *state)
1536 {
1537 struct r600_screen *rscreen = rctx->screen;
1538 struct r600_resource_texture *rtex;
1539 struct r600_surface *surf;
1540 uint64_t offset;
1541 unsigned level, first_layer, pitch, slice, format, array_mode;
1542 unsigned macro_aspect, tile_split, bankh, bankw, z_info, nbanks;
1543
1544 if (state->zsbuf == NULL)
1545 return;
1546
1547 surf = (struct r600_surface *)state->zsbuf;
1548 level = surf->base.u.tex.level;
1549 rtex = (struct r600_resource_texture*)surf->base.texture;
1550 first_layer = surf->base.u.tex.first_layer;
1551 format = r600_translate_dbformat(rtex->real_format);
1552
1553 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1554 /* XXX remove this once tiling is properly supported */
1555 if (!rscreen->use_surface_alloc) {
1556 /* XXX remove this once tiling is properly supported */
1557 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1558 V_028C70_ARRAY_1D_TILED_THIN1;
1559
1560 offset += r600_texture_get_offset(rtex, level, first_layer);
1561 pitch = (rtex->pitch_in_blocks[level] / 8) - 1;
1562 slice = ((rtex->pitch_in_blocks[level] * surf->aligned_height) / 64);
1563 if (slice) {
1564 slice = slice - 1;
1565 }
1566 tile_split = 0;
1567 macro_aspect = 0;
1568 bankw = 0;
1569 bankh = 0;
1570 } else {
1571 offset += rtex->surface.level[level].offset;
1572 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1573 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1574 if (slice) {
1575 slice = slice - 1;
1576 }
1577 switch (rtex->surface.level[level].mode) {
1578 case RADEON_SURF_MODE_2D:
1579 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1580 break;
1581 case RADEON_SURF_MODE_1D:
1582 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1583 case RADEON_SURF_MODE_LINEAR:
1584 default:
1585 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1586 break;
1587 }
1588 tile_split = rtex->surface.tile_split;
1589 macro_aspect = rtex->surface.mtilea;
1590 bankw = rtex->surface.bankw;
1591 bankh = rtex->surface.bankh;
1592 tile_split = eg_tile_split(tile_split);
1593 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1594 bankw = eg_bank_wh(bankw);
1595 bankh = eg_bank_wh(bankh);
1596 }
1597 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1598 offset >>= 8;
1599
1600 z_info = S_028040_ARRAY_MODE(array_mode) |
1601 S_028040_FORMAT(format) |
1602 S_028040_TILE_SPLIT(tile_split)|
1603 S_028040_NUM_BANKS(nbanks) |
1604 S_028040_BANK_WIDTH(bankw) |
1605 S_028040_BANK_HEIGHT(bankh) |
1606 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1607
1608 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1609 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1610 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1611 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1612 if (!rscreen->use_surface_alloc) {
1613 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1614 0x00000000, NULL, 0);
1615 } else {
1616 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1617 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1618 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer),
1619 NULL, 0);
1620 }
1621
1622 if (rtex->stencil) {
1623 uint64_t stencil_offset =
1624 r600_texture_get_offset(rtex->stencil, level, first_layer);
1625 unsigned stile_split;
1626
1627 stile_split = eg_tile_split(rtex->stencil->surface.tile_split);
1628 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1629 stencil_offset >>= 8;
1630
1631 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1632 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1633 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1634 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1635 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1636 1 | S_028044_TILE_SPLIT(stile_split),
1637 &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1638 } else {
1639 if (rscreen->use_surface_alloc && rtex->surface.flags & RADEON_SURF_SBUFFER) {
1640 uint64_t stencil_offset = rtex->surface.stencil_offset;
1641 unsigned stile_split = rtex->surface.stencil_tile_split;
1642
1643 stile_split = eg_tile_split(stile_split);
1644 stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1645 stencil_offset += rtex->surface.level[level].offset / 4;
1646 stencil_offset >>= 8;
1647
1648 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1649 stencil_offset, &rtex->resource,
1650 RADEON_USAGE_READWRITE);
1651 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1652 stencil_offset, &rtex->resource,
1653 RADEON_USAGE_READWRITE);
1654 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1655 1 | S_028044_TILE_SPLIT(stile_split),
1656 &rtex->resource,
1657 RADEON_USAGE_READWRITE);
1658 } else {
1659 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1660 offset, &rtex->resource,
1661 RADEON_USAGE_READWRITE);
1662 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1663 offset, &rtex->resource,
1664 RADEON_USAGE_READWRITE);
1665 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1666 0, NULL, RADEON_USAGE_READWRITE);
1667 }
1668 }
1669
1670 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, z_info,
1671 &rtex->resource, RADEON_USAGE_READWRITE);
1672 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1673 S_028058_PITCH_TILE_MAX(pitch),
1674 NULL, 0);
1675 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1676 S_02805C_SLICE_TILE_MAX(slice),
1677 NULL, 0);
1678 }
1679
1680 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1681 const struct pipe_framebuffer_state *state)
1682 {
1683 struct r600_context *rctx = (struct r600_context *)ctx;
1684 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1685 uint32_t shader_mask, tl, br;
1686
1687 if (rstate == NULL)
1688 return;
1689
1690 r600_flush_framebuffer(rctx, false);
1691
1692 /* unreference old buffer and reference new one */
1693 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1694
1695 util_copy_framebuffer_state(&rctx->framebuffer, state);
1696
1697 /* build states */
1698 rctx->have_depth_fb = 0;
1699 rctx->nr_cbufs = state->nr_cbufs;
1700 for (int i = 0; i < state->nr_cbufs; i++) {
1701 evergreen_cb(rctx, rstate, state, i);
1702 }
1703 if (state->zsbuf) {
1704 evergreen_db(rctx, rstate, state);
1705 }
1706
1707 shader_mask = 0;
1708 for (int i = 0; i < state->nr_cbufs; i++) {
1709 shader_mask |= 0xf << (i * 4);
1710 }
1711
1712 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1713
1714 r600_pipe_state_add_reg(rstate,
1715 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1716 NULL, 0);
1717 r600_pipe_state_add_reg(rstate,
1718 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1719 NULL, 0);
1720 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1721 shader_mask, NULL, 0);
1722
1723 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1724 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1725 r600_context_pipe_state_set(rctx, rstate);
1726
1727 if (state->zsbuf) {
1728 evergreen_polygon_offset_update(rctx);
1729 }
1730 }
1731
1732 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1733 {
1734 struct radeon_winsys_cs *cs = rctx->cs;
1735 struct r600_atom_db_misc_state *a = (struct r600_atom_db_misc_state*)atom;
1736 unsigned db_count_control = 0;
1737 unsigned db_render_override =
1738 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1739 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1740 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1741
1742 if (a->occlusion_query_enabled) {
1743 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1744 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1745 }
1746
1747 r600_write_context_reg(cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1748 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1749 }
1750
1751 static void evergreen_emit_streamout_config(struct r600_context *rctx, struct r600_atom *atom)
1752 {
1753 struct radeon_winsys_cs *cs = rctx->cs;
1754 struct r600_atom_eg_strmout_config *a = (struct r600_atom_eg_strmout_config*)atom;
1755
1756 r600_write_context_reg(cs, R_028B94_VGT_STRMOUT_CONFIG,
1757 S_028B94_STREAMOUT_0_EN(a->stream0_enable) |
1758 S_028B94_RAST_STREAM(a->rasterizer_discard ? 4 : 0));
1759 }
1760
1761 void evergreen_init_state_functions(struct r600_context *rctx)
1762 {
1763 r600_init_atom(&rctx->atom_db_misc_state.atom, evergreen_emit_db_misc_state, 6, 0);
1764 r600_atom_dirty(rctx, &rctx->atom_db_misc_state.atom);
1765 r600_init_atom(&rctx->atom_eg_strmout_config.atom, evergreen_emit_streamout_config, 6, 0);
1766 r600_atom_dirty(rctx, &rctx->atom_eg_strmout_config.atom);
1767
1768 rctx->context.create_blend_state = evergreen_create_blend_state;
1769 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1770 rctx->context.create_fs_state = r600_create_shader_state;
1771 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1772 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1773 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1774 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1775 rctx->context.create_vs_state = r600_create_shader_state;
1776 rctx->context.bind_blend_state = r600_bind_blend_state;
1777 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1778 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1779 rctx->context.bind_fs_state = r600_bind_ps_shader;
1780 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1781 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1782 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1783 rctx->context.bind_vs_state = r600_bind_vs_shader;
1784 rctx->context.delete_blend_state = r600_delete_state;
1785 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1786 rctx->context.delete_fs_state = r600_delete_ps_shader;
1787 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1788 rctx->context.delete_sampler_state = r600_delete_state;
1789 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1790 rctx->context.delete_vs_state = r600_delete_vs_shader;
1791 rctx->context.set_blend_color = r600_set_blend_color;
1792 rctx->context.set_clip_state = evergreen_set_clip_state;
1793 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1794 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1795 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1796 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1797 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1798 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1799 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1800 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1801 rctx->context.set_index_buffer = r600_set_index_buffer;
1802 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1803 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1804 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1805 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1806 rctx->context.texture_barrier = r600_texture_barrier;
1807 rctx->context.create_stream_output_target = r600_create_so_target;
1808 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1809 rctx->context.set_stream_output_targets = r600_set_so_targets;
1810 }
1811
1812 static void cayman_init_atom_start_cs(struct r600_context *rctx)
1813 {
1814 struct r600_command_buffer *cb = &rctx->atom_start_cs;
1815
1816 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1817
1818 /* This must be first. */
1819 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1820 r600_store_value(cb, 0x80000000);
1821 r600_store_value(cb, 0x80000000);
1822
1823 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
1824 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
1825 /* always set the temp clauses */
1826 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
1827
1828 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
1829 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
1830 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
1831
1832 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
1833
1834 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
1835
1836 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
1837 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
1838 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
1839 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
1840 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
1841 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
1842 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
1843 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
1844 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
1845 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
1846 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
1847 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
1848 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
1849 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
1850
1851 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
1852
1853 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
1854 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
1855 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
1856
1857 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
1858
1859 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
1860
1861 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1862 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
1863 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
1864
1865 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
1866 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
1867 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
1868
1869 r600_store_context_reg(cb, CM_R_028804_DB_EQAA, 0x110000);
1870
1871 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
1872 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
1873 r600_store_value(cb, 0);
1874 r600_store_value(cb, 0);
1875 r600_store_value(cb, 0);
1876 r600_store_value(cb, 0);
1877 r600_store_value(cb, 0);
1878 r600_store_value(cb, 0);
1879 r600_store_value(cb, 0);
1880 r600_store_value(cb, 0);
1881 r600_store_value(cb, 0);
1882 r600_store_value(cb, 0);
1883 r600_store_value(cb, 0);
1884 r600_store_value(cb, 0);
1885 r600_store_value(cb, 0);
1886 r600_store_value(cb, 0);
1887 r600_store_value(cb, 0);
1888 r600_store_value(cb, 0);
1889 r600_store_value(cb, 0);
1890 r600_store_value(cb, 0);
1891 r600_store_value(cb, 0);
1892 r600_store_value(cb, 0);
1893 r600_store_value(cb, 0);
1894 r600_store_value(cb, 0);
1895 r600_store_value(cb, 0);
1896 r600_store_value(cb, 0);
1897 r600_store_value(cb, 0);
1898 r600_store_value(cb, 0);
1899 r600_store_value(cb, 0);
1900 r600_store_value(cb, 0);
1901 r600_store_value(cb, 0);
1902 r600_store_value(cb, 0);
1903 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
1904 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
1905 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
1906
1907 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
1908
1909 r600_store_context_reg_seq(cb, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
1910 r600_store_value(cb, ~0); /* CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 */
1911 r600_store_value(cb, ~0); /* CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 */
1912
1913 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
1914 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
1915 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
1916
1917 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
1918
1919 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
1920 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
1921 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
1922 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
1923
1924 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
1925 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
1926
1927 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
1928 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
1929 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
1930
1931 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1932 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
1933 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
1934 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
1935
1936 r600_store_context_reg_seq(cb, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
1937 r600_store_value(cb, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1938 r600_store_value(cb, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1939
1940 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
1941 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
1942 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
1943 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
1944 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
1945
1946 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
1947 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
1948 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
1949
1950 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
1951 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
1952 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
1953
1954 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
1955 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
1956 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
1957
1958 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
1959
1960 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
1961 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
1962 }
1963
1964 void evergreen_init_atom_start_cs(struct r600_context *rctx)
1965 {
1966 struct r600_command_buffer *cb = &rctx->atom_start_cs;
1967 int ps_prio;
1968 int vs_prio;
1969 int gs_prio;
1970 int es_prio;
1971 int hs_prio, cs_prio, ls_prio;
1972 int num_ps_gprs;
1973 int num_vs_gprs;
1974 int num_gs_gprs;
1975 int num_es_gprs;
1976 int num_hs_gprs;
1977 int num_ls_gprs;
1978 int num_temp_gprs;
1979 int num_ps_threads;
1980 int num_vs_threads;
1981 int num_gs_threads;
1982 int num_es_threads;
1983 int num_hs_threads;
1984 int num_ls_threads;
1985 int num_ps_stack_entries;
1986 int num_vs_stack_entries;
1987 int num_gs_stack_entries;
1988 int num_es_stack_entries;
1989 int num_hs_stack_entries;
1990 int num_ls_stack_entries;
1991 enum radeon_family family;
1992 unsigned tmp;
1993
1994 if (rctx->chip_class == CAYMAN) {
1995 cayman_init_atom_start_cs(rctx);
1996 return;
1997 }
1998
1999 r600_init_command_buffer(cb, 256, EMIT_EARLY);
2000
2001 /* This must be first. */
2002 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2003 r600_store_value(cb, 0x80000000);
2004 r600_store_value(cb, 0x80000000);
2005
2006 family = rctx->family;
2007 ps_prio = 0;
2008 vs_prio = 1;
2009 gs_prio = 2;
2010 es_prio = 3;
2011 hs_prio = 0;
2012 ls_prio = 0;
2013 cs_prio = 0;
2014
2015 switch (family) {
2016 case CHIP_CEDAR:
2017 default:
2018 num_ps_gprs = 93;
2019 num_vs_gprs = 46;
2020 num_temp_gprs = 4;
2021 num_gs_gprs = 31;
2022 num_es_gprs = 31;
2023 num_hs_gprs = 23;
2024 num_ls_gprs = 23;
2025 num_ps_threads = 96;
2026 num_vs_threads = 16;
2027 num_gs_threads = 16;
2028 num_es_threads = 16;
2029 num_hs_threads = 16;
2030 num_ls_threads = 16;
2031 num_ps_stack_entries = 42;
2032 num_vs_stack_entries = 42;
2033 num_gs_stack_entries = 42;
2034 num_es_stack_entries = 42;
2035 num_hs_stack_entries = 42;
2036 num_ls_stack_entries = 42;
2037 break;
2038 case CHIP_REDWOOD:
2039 num_ps_gprs = 93;
2040 num_vs_gprs = 46;
2041 num_temp_gprs = 4;
2042 num_gs_gprs = 31;
2043 num_es_gprs = 31;
2044 num_hs_gprs = 23;
2045 num_ls_gprs = 23;
2046 num_ps_threads = 128;
2047 num_vs_threads = 20;
2048 num_gs_threads = 20;
2049 num_es_threads = 20;
2050 num_hs_threads = 20;
2051 num_ls_threads = 20;
2052 num_ps_stack_entries = 42;
2053 num_vs_stack_entries = 42;
2054 num_gs_stack_entries = 42;
2055 num_es_stack_entries = 42;
2056 num_hs_stack_entries = 42;
2057 num_ls_stack_entries = 42;
2058 break;
2059 case CHIP_JUNIPER:
2060 num_ps_gprs = 93;
2061 num_vs_gprs = 46;
2062 num_temp_gprs = 4;
2063 num_gs_gprs = 31;
2064 num_es_gprs = 31;
2065 num_hs_gprs = 23;
2066 num_ls_gprs = 23;
2067 num_ps_threads = 128;
2068 num_vs_threads = 20;
2069 num_gs_threads = 20;
2070 num_es_threads = 20;
2071 num_hs_threads = 20;
2072 num_ls_threads = 20;
2073 num_ps_stack_entries = 85;
2074 num_vs_stack_entries = 85;
2075 num_gs_stack_entries = 85;
2076 num_es_stack_entries = 85;
2077 num_hs_stack_entries = 85;
2078 num_ls_stack_entries = 85;
2079 break;
2080 case CHIP_CYPRESS:
2081 case CHIP_HEMLOCK:
2082 num_ps_gprs = 93;
2083 num_vs_gprs = 46;
2084 num_temp_gprs = 4;
2085 num_gs_gprs = 31;
2086 num_es_gprs = 31;
2087 num_hs_gprs = 23;
2088 num_ls_gprs = 23;
2089 num_ps_threads = 128;
2090 num_vs_threads = 20;
2091 num_gs_threads = 20;
2092 num_es_threads = 20;
2093 num_hs_threads = 20;
2094 num_ls_threads = 20;
2095 num_ps_stack_entries = 85;
2096 num_vs_stack_entries = 85;
2097 num_gs_stack_entries = 85;
2098 num_es_stack_entries = 85;
2099 num_hs_stack_entries = 85;
2100 num_ls_stack_entries = 85;
2101 break;
2102 case CHIP_PALM:
2103 num_ps_gprs = 93;
2104 num_vs_gprs = 46;
2105 num_temp_gprs = 4;
2106 num_gs_gprs = 31;
2107 num_es_gprs = 31;
2108 num_hs_gprs = 23;
2109 num_ls_gprs = 23;
2110 num_ps_threads = 96;
2111 num_vs_threads = 16;
2112 num_gs_threads = 16;
2113 num_es_threads = 16;
2114 num_hs_threads = 16;
2115 num_ls_threads = 16;
2116 num_ps_stack_entries = 42;
2117 num_vs_stack_entries = 42;
2118 num_gs_stack_entries = 42;
2119 num_es_stack_entries = 42;
2120 num_hs_stack_entries = 42;
2121 num_ls_stack_entries = 42;
2122 break;
2123 case CHIP_SUMO:
2124 num_ps_gprs = 93;
2125 num_vs_gprs = 46;
2126 num_temp_gprs = 4;
2127 num_gs_gprs = 31;
2128 num_es_gprs = 31;
2129 num_hs_gprs = 23;
2130 num_ls_gprs = 23;
2131 num_ps_threads = 96;
2132 num_vs_threads = 25;
2133 num_gs_threads = 25;
2134 num_es_threads = 25;
2135 num_hs_threads = 25;
2136 num_ls_threads = 25;
2137 num_ps_stack_entries = 42;
2138 num_vs_stack_entries = 42;
2139 num_gs_stack_entries = 42;
2140 num_es_stack_entries = 42;
2141 num_hs_stack_entries = 42;
2142 num_ls_stack_entries = 42;
2143 break;
2144 case CHIP_SUMO2:
2145 num_ps_gprs = 93;
2146 num_vs_gprs = 46;
2147 num_temp_gprs = 4;
2148 num_gs_gprs = 31;
2149 num_es_gprs = 31;
2150 num_hs_gprs = 23;
2151 num_ls_gprs = 23;
2152 num_ps_threads = 96;
2153 num_vs_threads = 25;
2154 num_gs_threads = 25;
2155 num_es_threads = 25;
2156 num_hs_threads = 25;
2157 num_ls_threads = 25;
2158 num_ps_stack_entries = 85;
2159 num_vs_stack_entries = 85;
2160 num_gs_stack_entries = 85;
2161 num_es_stack_entries = 85;
2162 num_hs_stack_entries = 85;
2163 num_ls_stack_entries = 85;
2164 break;
2165 case CHIP_BARTS:
2166 num_ps_gprs = 93;
2167 num_vs_gprs = 46;
2168 num_temp_gprs = 4;
2169 num_gs_gprs = 31;
2170 num_es_gprs = 31;
2171 num_hs_gprs = 23;
2172 num_ls_gprs = 23;
2173 num_ps_threads = 128;
2174 num_vs_threads = 20;
2175 num_gs_threads = 20;
2176 num_es_threads = 20;
2177 num_hs_threads = 20;
2178 num_ls_threads = 20;
2179 num_ps_stack_entries = 85;
2180 num_vs_stack_entries = 85;
2181 num_gs_stack_entries = 85;
2182 num_es_stack_entries = 85;
2183 num_hs_stack_entries = 85;
2184 num_ls_stack_entries = 85;
2185 break;
2186 case CHIP_TURKS:
2187 num_ps_gprs = 93;
2188 num_vs_gprs = 46;
2189 num_temp_gprs = 4;
2190 num_gs_gprs = 31;
2191 num_es_gprs = 31;
2192 num_hs_gprs = 23;
2193 num_ls_gprs = 23;
2194 num_ps_threads = 128;
2195 num_vs_threads = 20;
2196 num_gs_threads = 20;
2197 num_es_threads = 20;
2198 num_hs_threads = 20;
2199 num_ls_threads = 20;
2200 num_ps_stack_entries = 42;
2201 num_vs_stack_entries = 42;
2202 num_gs_stack_entries = 42;
2203 num_es_stack_entries = 42;
2204 num_hs_stack_entries = 42;
2205 num_ls_stack_entries = 42;
2206 break;
2207 case CHIP_CAICOS:
2208 num_ps_gprs = 93;
2209 num_vs_gprs = 46;
2210 num_temp_gprs = 4;
2211 num_gs_gprs = 31;
2212 num_es_gprs = 31;
2213 num_hs_gprs = 23;
2214 num_ls_gprs = 23;
2215 num_ps_threads = 128;
2216 num_vs_threads = 10;
2217 num_gs_threads = 10;
2218 num_es_threads = 10;
2219 num_hs_threads = 10;
2220 num_ls_threads = 10;
2221 num_ps_stack_entries = 42;
2222 num_vs_stack_entries = 42;
2223 num_gs_stack_entries = 42;
2224 num_es_stack_entries = 42;
2225 num_hs_stack_entries = 42;
2226 num_ls_stack_entries = 42;
2227 break;
2228 }
2229
2230 tmp = 0;
2231 switch (family) {
2232 case CHIP_CEDAR:
2233 case CHIP_PALM:
2234 case CHIP_SUMO:
2235 case CHIP_SUMO2:
2236 case CHIP_CAICOS:
2237 break;
2238 default:
2239 tmp |= S_008C00_VC_ENABLE(1);
2240 break;
2241 }
2242 tmp |= S_008C00_EXPORT_SRC_C(1);
2243 tmp |= S_008C00_CS_PRIO(cs_prio);
2244 tmp |= S_008C00_LS_PRIO(ls_prio);
2245 tmp |= S_008C00_HS_PRIO(hs_prio);
2246 tmp |= S_008C00_PS_PRIO(ps_prio);
2247 tmp |= S_008C00_VS_PRIO(vs_prio);
2248 tmp |= S_008C00_GS_PRIO(gs_prio);
2249 tmp |= S_008C00_ES_PRIO(es_prio);
2250
2251 /* enable dynamic GPR resource management */
2252 if (rctx->screen->info.drm_minor >= 7) {
2253 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2254 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2255 /* always set temp clauses */
2256 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2257 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2258 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2259 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2260 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2261 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2262 S_028838_PS_GPRS(0x1e) |
2263 S_028838_VS_GPRS(0x1e) |
2264 S_028838_GS_GPRS(0x1e) |
2265 S_028838_ES_GPRS(0x1e) |
2266 S_028838_HS_GPRS(0x1e) |
2267 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2268 } else {
2269 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2270 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2271
2272 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2273 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2274 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2275 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2276
2277 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2278 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2279 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2280
2281 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2282 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2283 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2284 }
2285
2286 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2287 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2288 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2289 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2290 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2291 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2292
2293 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2294 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2295 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2296
2297 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2298 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2299 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2300
2301 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2302 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2303 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2304
2305 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2306 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2307 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2308
2309 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2310 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2311
2312 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2313 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2314
2315 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2316
2317 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2318 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2319 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2320 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2321 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2322 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2323 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2324
2325 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2326 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2327 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2328 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2329 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2330
2331 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2332 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2333 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2334 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2335 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2336 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2337 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2338 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2339 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2340 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2341 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2342 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2343 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2344 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2345
2346 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2347
2348 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2349 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2350 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2351
2352 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2353
2354 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2355 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2356 r600_store_value(cb, 0);
2357 r600_store_value(cb, 0);
2358 r600_store_value(cb, 0);
2359 r600_store_value(cb, 0);
2360 r600_store_value(cb, 0);
2361 r600_store_value(cb, 0);
2362 r600_store_value(cb, 0);
2363 r600_store_value(cb, 0);
2364 r600_store_value(cb, 0);
2365 r600_store_value(cb, 0);
2366 r600_store_value(cb, 0);
2367 r600_store_value(cb, 0);
2368 r600_store_value(cb, 0);
2369 r600_store_value(cb, 0);
2370 r600_store_value(cb, 0);
2371 r600_store_value(cb, 0);
2372 r600_store_value(cb, 0);
2373 r600_store_value(cb, 0);
2374 r600_store_value(cb, 0);
2375 r600_store_value(cb, 0);
2376 r600_store_value(cb, 0);
2377 r600_store_value(cb, 0);
2378 r600_store_value(cb, 0);
2379 r600_store_value(cb, 0);
2380 r600_store_value(cb, 0);
2381 r600_store_value(cb, 0);
2382 r600_store_value(cb, 0);
2383 r600_store_value(cb, 0);
2384 r600_store_value(cb, 0);
2385 r600_store_value(cb, 0);
2386 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2387 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2388 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2389
2390 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2391
2392 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2393 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2394 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2395
2396 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2397 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2398 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2399
2400 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2401 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2402 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2403
2404 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2405 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2406 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2407
2408 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2409 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2410 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2411 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2412
2413 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2414
2415 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2416 r600_store_value(cb, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
2417 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2418
2419 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 5);
2420 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2421 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2422 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2423 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2424 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
2425
2426 r600_store_context_reg(cb, R_028C3C_PA_SC_AA_MASK, ~0);
2427
2428 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2429 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2430 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2431
2432 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2433 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2434 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2435
2436 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
2437 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
2438 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2439
2440 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2441
2442 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2443 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2444 }
2445
2446 void evergreen_polygon_offset_update(struct r600_context *rctx)
2447 {
2448 struct r600_pipe_state state;
2449
2450 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2451 state.nregs = 0;
2452 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2453 float offset_units = rctx->rasterizer->offset_units;
2454 unsigned offset_db_fmt_cntl = 0, depth;
2455
2456 switch (rctx->framebuffer.zsbuf->texture->format) {
2457 case PIPE_FORMAT_Z24X8_UNORM:
2458 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2459 depth = -24;
2460 offset_units *= 2.0f;
2461 break;
2462 case PIPE_FORMAT_Z32_FLOAT:
2463 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2464 depth = -23;
2465 offset_units *= 1.0f;
2466 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2467 break;
2468 case PIPE_FORMAT_Z16_UNORM:
2469 depth = -16;
2470 offset_units *= 4.0f;
2471 break;
2472 default:
2473 return;
2474 }
2475 /* XXX some of those reg can be computed with cso */
2476 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2477 r600_pipe_state_add_reg(&state,
2478 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2479 fui(rctx->rasterizer->offset_scale), NULL, 0);
2480 r600_pipe_state_add_reg(&state,
2481 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2482 fui(offset_units), NULL, 0);
2483 r600_pipe_state_add_reg(&state,
2484 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2485 fui(rctx->rasterizer->offset_scale), NULL, 0);
2486 r600_pipe_state_add_reg(&state,
2487 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2488 fui(offset_units), NULL, 0);
2489 r600_pipe_state_add_reg(&state,
2490 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2491 offset_db_fmt_cntl, NULL, 0);
2492 r600_context_pipe_state_set(rctx, &state);
2493 }
2494 }
2495
2496 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2497 {
2498 struct r600_context *rctx = (struct r600_context *)ctx;
2499 struct r600_pipe_state *rstate = &shader->rstate;
2500 struct r600_shader *rshader = &shader->shader;
2501 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2502 int pos_index = -1, face_index = -1;
2503 int ninterp = 0;
2504 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2505 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2506
2507 rstate->nregs = 0;
2508
2509 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2510 for (i = 0; i < rshader->ninput; i++) {
2511 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2512 POSITION goes via GPRs from the SC so isn't counted */
2513 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2514 pos_index = i;
2515 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2516 face_index = i;
2517 else {
2518 ninterp++;
2519 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2520 have_linear = TRUE;
2521 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2522 have_perspective = TRUE;
2523 if (rshader->input[i].centroid)
2524 have_centroid = TRUE;
2525 }
2526
2527 sid = rshader->input[i].spi_sid;
2528
2529 if (sid) {
2530
2531 tmp = S_028644_SEMANTIC(sid);
2532
2533 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2534 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2535 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2536 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2537 tmp |= S_028644_FLAT_SHADE(1);
2538 }
2539
2540 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2541 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2542 tmp |= S_028644_PT_SPRITE_TEX(1);
2543 }
2544
2545 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2546 tmp, NULL, 0);
2547
2548 idx++;
2549 }
2550 }
2551
2552 for (i = 0; i < rshader->noutput; i++) {
2553 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2554 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2555 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2556 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2557 }
2558 if (rshader->uses_kill)
2559 db_shader_control |= S_02880C_KILL_ENABLE(1);
2560
2561 exports_ps = 0;
2562 num_cout = 0;
2563 for (i = 0; i < rshader->noutput; i++) {
2564 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2565 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2566 exports_ps |= 1;
2567 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2568 if (rshader->fs_write_all)
2569 num_cout = rshader->nr_cbufs;
2570 else
2571 num_cout++;
2572 }
2573 }
2574 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2575 if (!exports_ps) {
2576 /* always at least export 1 component per pixel */
2577 exports_ps = 2;
2578 }
2579
2580 if (ninterp == 0) {
2581 ninterp = 1;
2582 have_perspective = TRUE;
2583 }
2584
2585 if (!have_perspective && !have_linear)
2586 have_perspective = TRUE;
2587
2588 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2589 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2590 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2591 spi_input_z = 0;
2592 if (pos_index != -1) {
2593 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2594 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2595 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2596 spi_input_z |= 1;
2597 }
2598
2599 spi_ps_in_control_1 = 0;
2600 if (face_index != -1) {
2601 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2602 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2603 }
2604
2605 spi_baryc_cntl = 0;
2606 if (have_perspective)
2607 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2608 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2609 if (have_linear)
2610 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2611 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2612
2613 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2614 spi_ps_in_control_0, NULL, 0);
2615 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2616 spi_ps_in_control_1, NULL, 0);
2617 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2618 0, NULL, 0);
2619 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0);
2620 r600_pipe_state_add_reg(rstate,
2621 R_0286E0_SPI_BARYC_CNTL,
2622 spi_baryc_cntl,
2623 NULL, 0);
2624
2625 r600_pipe_state_add_reg(rstate,
2626 R_028840_SQ_PGM_START_PS,
2627 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2628 shader->bo, RADEON_USAGE_READ);
2629 r600_pipe_state_add_reg(rstate,
2630 R_028844_SQ_PGM_RESOURCES_PS,
2631 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2632 S_028844_PRIME_CACHE_ON_DRAW(1) |
2633 S_028844_STACK_SIZE(rshader->bc.nstack),
2634 NULL, 0);
2635 r600_pipe_state_add_reg(rstate,
2636 R_02884C_SQ_PGM_EXPORTS_PS,
2637 exports_ps, NULL, 0);
2638 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2639 db_shader_control,
2640 NULL, 0);
2641
2642 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2643 if (rctx->rasterizer)
2644 shader->flatshade = rctx->rasterizer->flatshade;
2645 }
2646
2647 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2648 {
2649 struct r600_context *rctx = (struct r600_context *)ctx;
2650 struct r600_pipe_state *rstate = &shader->rstate;
2651 struct r600_shader *rshader = &shader->shader;
2652 unsigned spi_vs_out_id[10] = {};
2653 unsigned i, tmp, nparams = 0;
2654
2655 /* clear previous register */
2656 rstate->nregs = 0;
2657
2658 for (i = 0; i < rshader->noutput; i++) {
2659 if (rshader->output[i].spi_sid) {
2660 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2661 spi_vs_out_id[nparams / 4] |= tmp;
2662 nparams++;
2663 }
2664 }
2665
2666 for (i = 0; i < 10; i++) {
2667 r600_pipe_state_add_reg(rstate,
2668 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2669 spi_vs_out_id[i], NULL, 0);
2670 }
2671
2672 /* Certain attributes (position, psize, etc.) don't count as params.
2673 * VS is required to export at least one param and r600_shader_from_tgsi()
2674 * takes care of adding a dummy export.
2675 */
2676 if (nparams < 1)
2677 nparams = 1;
2678
2679 r600_pipe_state_add_reg(rstate,
2680 R_0286C4_SPI_VS_OUT_CONFIG,
2681 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2682 NULL, 0);
2683 r600_pipe_state_add_reg(rstate,
2684 R_028860_SQ_PGM_RESOURCES_VS,
2685 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2686 S_028860_STACK_SIZE(rshader->bc.nstack),
2687 NULL, 0);
2688 r600_pipe_state_add_reg(rstate,
2689 R_02885C_SQ_PGM_START_VS,
2690 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2691 shader->bo, RADEON_USAGE_READ);
2692
2693 shader->pa_cl_vs_out_cntl =
2694 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2695 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2696 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2697 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2698 }
2699
2700 void evergreen_fetch_shader(struct pipe_context *ctx,
2701 struct r600_vertex_element *ve)
2702 {
2703 struct r600_context *rctx = (struct r600_context *)ctx;
2704 struct r600_pipe_state *rstate = &ve->rstate;
2705 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2706 rstate->nregs = 0;
2707 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2708 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2709 ve->fetch_shader, RADEON_USAGE_READ);
2710 }
2711
2712 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2713 {
2714 struct pipe_depth_stencil_alpha_state dsa;
2715 struct r600_pipe_state *rstate;
2716
2717 memset(&dsa, 0, sizeof(dsa));
2718
2719 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2720 r600_pipe_state_add_reg(rstate,
2721 R_028000_DB_RENDER_CONTROL,
2722 S_028000_DEPTH_COPY_ENABLE(1) |
2723 S_028000_STENCIL_COPY_ENABLE(1) |
2724 S_028000_COPY_CENTROID(1),
2725 NULL, 0);
2726 /* Don't set the 'is_flush' flag in r600_pipe_dsa, evergreen doesn't need it. */
2727 return rstate;
2728 }
2729
2730 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
2731 struct r600_pipe_resource_state *rstate)
2732 {
2733 rstate->id = R600_PIPE_STATE_RESOURCE;
2734
2735 rstate->val[0] = 0;
2736 rstate->bo[0] = NULL;
2737 rstate->val[1] = 0;
2738 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2739 rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2740 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2741 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2742 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2743 rstate->val[4] = 0;
2744 rstate->val[5] = 0;
2745 rstate->val[6] = 0;
2746 rstate->val[7] = 0xc0000000;
2747 }
2748
2749
2750 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
2751 struct r600_pipe_resource_state *rstate,
2752 struct r600_resource *rbuffer,
2753 unsigned offset, unsigned stride,
2754 enum radeon_bo_usage usage)
2755 {
2756 uint64_t va;
2757
2758 va = r600_resource_va(ctx->screen, (void *)rbuffer);
2759 rstate->bo[0] = rbuffer;
2760 rstate->bo_usage[0] = usage;
2761 rstate->val[0] = (offset + va) & 0xFFFFFFFFUL;
2762 rstate->val[1] = rbuffer->buf->size - offset - 1;
2763 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2764 S_030008_STRIDE(stride) |
2765 (((va + offset) >> 32UL) & 0xFF);
2766 }