2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
35 static inline unsigned evergreen_array_mode(unsigned mode
)
39 case RADEON_SURF_MODE_LINEAR_ALIGNED
: return V_028C70_ARRAY_LINEAR_ALIGNED
;
41 case RADEON_SURF_MODE_1D
: return V_028C70_ARRAY_1D_TILED_THIN1
;
43 case RADEON_SURF_MODE_2D
: return V_028C70_ARRAY_2D_TILED_THIN1
;
47 static uint32_t eg_num_banks(uint32_t nbanks
)
63 static unsigned eg_tile_split(unsigned tile_split
)
66 case 64: tile_split
= 0; break;
67 case 128: tile_split
= 1; break;
68 case 256: tile_split
= 2; break;
69 case 512: tile_split
= 3; break;
71 case 1024: tile_split
= 4; break;
72 case 2048: tile_split
= 5; break;
73 case 4096: tile_split
= 6; break;
78 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect
)
80 switch (macro_tile_aspect
) {
82 case 1: macro_tile_aspect
= 0; break;
83 case 2: macro_tile_aspect
= 1; break;
84 case 4: macro_tile_aspect
= 2; break;
85 case 8: macro_tile_aspect
= 3; break;
87 return macro_tile_aspect
;
90 static unsigned eg_bank_wh(unsigned bankwh
)
94 case 1: bankwh
= 0; break;
95 case 2: bankwh
= 1; break;
96 case 4: bankwh
= 2; break;
97 case 8: bankwh
= 3; break;
102 static uint32_t r600_translate_blend_function(int blend_func
)
104 switch (blend_func
) {
106 return V_028780_COMB_DST_PLUS_SRC
;
107 case PIPE_BLEND_SUBTRACT
:
108 return V_028780_COMB_SRC_MINUS_DST
;
109 case PIPE_BLEND_REVERSE_SUBTRACT
:
110 return V_028780_COMB_DST_MINUS_SRC
;
112 return V_028780_COMB_MIN_DST_SRC
;
114 return V_028780_COMB_MAX_DST_SRC
;
116 R600_ERR("Unknown blend function %d\n", blend_func
);
123 static uint32_t r600_translate_blend_factor(int blend_fact
)
125 switch (blend_fact
) {
126 case PIPE_BLENDFACTOR_ONE
:
127 return V_028780_BLEND_ONE
;
128 case PIPE_BLENDFACTOR_SRC_COLOR
:
129 return V_028780_BLEND_SRC_COLOR
;
130 case PIPE_BLENDFACTOR_SRC_ALPHA
:
131 return V_028780_BLEND_SRC_ALPHA
;
132 case PIPE_BLENDFACTOR_DST_ALPHA
:
133 return V_028780_BLEND_DST_ALPHA
;
134 case PIPE_BLENDFACTOR_DST_COLOR
:
135 return V_028780_BLEND_DST_COLOR
;
136 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
137 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
138 case PIPE_BLENDFACTOR_CONST_COLOR
:
139 return V_028780_BLEND_CONST_COLOR
;
140 case PIPE_BLENDFACTOR_CONST_ALPHA
:
141 return V_028780_BLEND_CONST_ALPHA
;
142 case PIPE_BLENDFACTOR_ZERO
:
143 return V_028780_BLEND_ZERO
;
144 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
145 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
146 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
147 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
148 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
149 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
150 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
151 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
152 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
153 return V_028780_BLEND_ONE_MINUS_CONST_COLOR
;
154 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
155 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA
;
156 case PIPE_BLENDFACTOR_SRC1_COLOR
:
157 return V_028780_BLEND_SRC1_COLOR
;
158 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
159 return V_028780_BLEND_SRC1_ALPHA
;
160 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
161 return V_028780_BLEND_INV_SRC1_COLOR
;
162 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
163 return V_028780_BLEND_INV_SRC1_ALPHA
;
165 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
172 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
176 case PIPE_TEXTURE_1D
:
177 return V_030000_SQ_TEX_DIM_1D
;
178 case PIPE_TEXTURE_1D_ARRAY
:
179 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
180 case PIPE_TEXTURE_2D
:
181 case PIPE_TEXTURE_RECT
:
182 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_MSAA
:
183 V_030000_SQ_TEX_DIM_2D
;
184 case PIPE_TEXTURE_2D_ARRAY
:
185 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
186 V_030000_SQ_TEX_DIM_2D_ARRAY
;
187 case PIPE_TEXTURE_3D
:
188 return V_030000_SQ_TEX_DIM_3D
;
189 case PIPE_TEXTURE_CUBE
:
190 case PIPE_TEXTURE_CUBE_ARRAY
:
191 return V_030000_SQ_TEX_DIM_CUBEMAP
;
195 static uint32_t r600_translate_dbformat(enum pipe_format format
)
198 case PIPE_FORMAT_Z16_UNORM
:
199 return V_028040_Z_16
;
200 case PIPE_FORMAT_Z24X8_UNORM
:
201 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
202 case PIPE_FORMAT_X8Z24_UNORM
:
203 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
204 return V_028040_Z_24
;
205 case PIPE_FORMAT_Z32_FLOAT
:
206 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
207 return V_028040_Z_32_FLOAT
;
213 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
215 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
,
219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip
, enum pipe_format format
)
221 return r600_translate_colorformat(chip
, format
, FALSE
) != ~0U &&
222 r600_translate_colorswap(format
, FALSE
) != ~0U;
225 static bool r600_is_zs_format_supported(enum pipe_format format
)
227 return r600_translate_dbformat(format
) != ~0U;
230 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
231 enum pipe_format format
,
232 enum pipe_texture_target target
,
233 unsigned sample_count
,
236 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
239 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
240 R600_ERR("r600: unsupported texture type %d\n", target
);
244 if (!util_format_is_supported(format
, usage
))
247 if (sample_count
> 1) {
248 if (!rscreen
->has_msaa
)
251 switch (sample_count
) {
261 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
262 if (target
== PIPE_BUFFER
) {
263 if (r600_is_vertex_format_supported(format
))
264 retval
|= PIPE_BIND_SAMPLER_VIEW
;
266 if (r600_is_sampler_format_supported(screen
, format
))
267 retval
|= PIPE_BIND_SAMPLER_VIEW
;
271 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
272 PIPE_BIND_DISPLAY_TARGET
|
275 PIPE_BIND_BLENDABLE
)) &&
276 r600_is_colorbuffer_format_supported(rscreen
->b
.chip_class
, format
)) {
278 (PIPE_BIND_RENDER_TARGET
|
279 PIPE_BIND_DISPLAY_TARGET
|
282 if (!util_format_is_pure_integer(format
) &&
283 !util_format_is_depth_or_stencil(format
))
284 retval
|= usage
& PIPE_BIND_BLENDABLE
;
287 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
288 r600_is_zs_format_supported(format
)) {
289 retval
|= PIPE_BIND_DEPTH_STENCIL
;
292 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
293 r600_is_vertex_format_supported(format
)) {
294 retval
|= PIPE_BIND_VERTEX_BUFFER
;
297 if ((usage
& PIPE_BIND_LINEAR
) &&
298 !util_format_is_compressed(format
) &&
299 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
300 retval
|= PIPE_BIND_LINEAR
;
302 return retval
== usage
;
305 static void *evergreen_create_blend_state_mode(struct pipe_context
*ctx
,
306 const struct pipe_blend_state
*state
, int mode
)
308 uint32_t color_control
= 0, target_mask
= 0;
309 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
315 r600_init_command_buffer(&blend
->buffer
, 20);
316 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
318 if (state
->logicop_enable
) {
319 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
321 color_control
|= (0xcc << 16);
323 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
324 if (state
->independent_blend_enable
) {
325 for (int i
= 0; i
< 8; i
++) {
326 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
329 for (int i
= 0; i
< 8; i
++) {
330 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
334 /* only have dual source on MRT0 */
335 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
336 blend
->cb_target_mask
= target_mask
;
337 blend
->alpha_to_one
= state
->alpha_to_one
;
340 color_control
|= S_028808_MODE(mode
);
342 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
345 r600_store_context_reg(&blend
->buffer
, R_028808_CB_COLOR_CONTROL
, color_control
);
346 r600_store_context_reg(&blend
->buffer
, R_028B70_DB_ALPHA_TO_MASK
,
347 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
348 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
349 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
350 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
351 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
352 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
354 /* Copy over the dwords set so far into buffer_no_blend.
355 * Only the CB_BLENDi_CONTROL registers must be set after this. */
356 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
357 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
359 for (int i
= 0; i
< 8; i
++) {
360 /* state->rt entries > 0 only written if independent blending */
361 const int j
= state
->independent_blend_enable
? i
: 0;
363 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
364 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
365 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
366 unsigned eqA
= state
->rt
[j
].alpha_func
;
367 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
368 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
371 r600_store_value(&blend
->buffer_no_blend
, 0);
373 if (!state
->rt
[j
].blend_enable
) {
374 r600_store_value(&blend
->buffer
, 0);
378 bc
|= S_028780_BLEND_CONTROL_ENABLE(1);
379 bc
|= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
380 bc
|= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
381 bc
|= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
383 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
384 bc
|= S_028780_SEPARATE_ALPHA_BLEND(1);
385 bc
|= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
386 bc
|= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
387 bc
|= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
389 r600_store_value(&blend
->buffer
, bc
);
394 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
395 const struct pipe_blend_state
*state
)
398 return evergreen_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
401 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
402 const struct pipe_depth_stencil_alpha_state
*state
)
404 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
405 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
411 r600_init_command_buffer(&dsa
->buffer
, 3);
413 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
414 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
415 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
416 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
417 dsa
->zwritemask
= state
->depth
.writemask
;
419 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
420 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
421 S_028800_ZFUNC(state
->depth
.func
);
424 if (state
->stencil
[0].enabled
) {
425 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
426 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
427 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
428 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
429 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
431 if (state
->stencil
[1].enabled
) {
432 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
433 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
434 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
435 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
436 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
441 alpha_test_control
= 0;
443 if (state
->alpha
.enabled
) {
444 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
445 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
446 alpha_ref
= fui(state
->alpha
.ref_value
);
448 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
449 dsa
->alpha_ref
= alpha_ref
;
452 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
456 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
457 const struct pipe_rasterizer_state
*state
)
459 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
460 unsigned tmp
, spi_interp
;
461 float psize_min
, psize_max
;
462 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
468 r600_init_command_buffer(&rs
->buffer
, 30);
470 rs
->scissor_enable
= state
->scissor
;
471 rs
->clip_halfz
= state
->clip_halfz
;
472 rs
->flatshade
= state
->flatshade
;
473 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
474 rs
->rasterizer_discard
= state
->rasterizer_discard
;
475 rs
->two_side
= state
->light_twoside
;
476 rs
->clip_plane_enable
= state
->clip_plane_enable
;
477 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
478 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
479 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
480 rs
->pa_cl_clip_cntl
=
481 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
482 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
483 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
484 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
485 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
);
486 rs
->multisample_enable
= state
->multisample
;
489 rs
->offset_units
= state
->offset_units
;
490 rs
->offset_scale
= state
->offset_scale
* 16.0f
;
491 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
492 rs
->offset_units_unscaled
= state
->offset_units_unscaled
;
494 if (state
->point_size_per_vertex
) {
495 psize_min
= util_get_min_point_size(state
);
498 /* Force the point size to be as if the vertex output was disabled. */
499 psize_min
= state
->point_size
;
500 psize_max
= state
->point_size
;
503 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
504 if (state
->sprite_coord_enable
) {
505 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
506 S_0286D4_PNT_SPRITE_OVRD_X(2) |
507 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
508 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
509 S_0286D4_PNT_SPRITE_OVRD_W(1);
510 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
511 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
515 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
516 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
517 tmp
= r600_pack_float_12p4(state
->point_size
/2);
518 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
519 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
520 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
521 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
522 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
523 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
524 S_028A08_WIDTH((unsigned)(state
->line_width
* 8)));
526 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
527 r600_store_context_reg(&rs
->buffer
, R_028A48_PA_SC_MODE_CNTL_0
,
528 S_028A48_MSAA_ENABLE(state
->multisample
) |
529 S_028A48_VPORT_SCISSOR_ENABLE(1) |
530 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
));
532 if (rctx
->b
.chip_class
== CAYMAN
) {
533 r600_store_context_reg(&rs
->buffer
, CM_R_028BE4_PA_SU_VTX_CNTL
,
534 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
535 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
537 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
538 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
539 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
542 r600_store_context_reg(&rs
->buffer
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
543 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
,
544 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
545 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
546 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
547 S_028814_FACE(!state
->front_ccw
) |
548 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
549 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
550 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
551 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
552 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
553 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
554 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
558 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
559 const struct pipe_sampler_state
*state
)
561 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)ctx
->screen
;
562 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
563 unsigned max_aniso
= rscreen
->force_aniso
>= 0 ? rscreen
->force_aniso
564 : state
->max_anisotropy
;
565 unsigned max_aniso_ratio
= r600_tex_aniso_filter(max_aniso
);
571 ss
->border_color_use
= sampler_state_needs_border_color(state
);
573 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
574 ss
->tex_sampler_words
[0] =
575 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
576 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
577 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
578 S_03C000_XY_MAG_FILTER(eg_tex_filter(state
->mag_img_filter
, max_aniso
)) |
579 S_03C000_XY_MIN_FILTER(eg_tex_filter(state
->min_img_filter
, max_aniso
)) |
580 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
581 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio
) |
582 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
583 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
584 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
585 ss
->tex_sampler_words
[1] =
586 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
587 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8));
588 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
589 ss
->tex_sampler_words
[2] =
590 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
591 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
594 if (ss
->border_color_use
) {
595 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
600 struct eg_buf_res_params
{
601 enum pipe_format pipe_format
;
604 unsigned char swizzle
[4];
608 static void evergreen_fill_buffer_resource_words(struct r600_context
*rctx
,
609 struct pipe_resource
*buffer
,
610 struct eg_buf_res_params
*params
,
611 bool *skip_mip_address_reloc
,
612 unsigned tex_resource_words
[8])
614 struct r600_texture
*tmp
= (struct r600_texture
*)buffer
;
616 int stride
= util_format_get_blocksize(params
->pipe_format
);
617 unsigned format
, num_format
, format_comp
, endian
;
618 unsigned swizzle_res
;
619 const struct util_format_description
*desc
;
621 r600_vertex_data_type(params
->pipe_format
,
622 &format
, &num_format
, &format_comp
,
625 desc
= util_format_description(params
->pipe_format
);
627 swizzle_res
= r600_get_swizzle_combined(desc
->swizzle
, params
->swizzle
, TRUE
);
629 va
= tmp
->resource
.gpu_address
+ params
->offset
;
630 *skip_mip_address_reloc
= true;
631 tex_resource_words
[0] = va
;
632 tex_resource_words
[1] = params
->size
- 1;
633 tex_resource_words
[2] = S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
634 S_030008_STRIDE(stride
) |
635 S_030008_DATA_FORMAT(format
) |
636 S_030008_NUM_FORMAT_ALL(num_format
) |
637 S_030008_FORMAT_COMP_ALL(format_comp
) |
638 S_030008_ENDIAN_SWAP(endian
);
639 tex_resource_words
[3] = swizzle_res
| S_03000C_UNCACHED(params
->uncached
);
641 * in theory dword 4 is for number of elements, for use with resinfo,
642 * but it seems to utterly fail to work, the amd gpu shader analyser
643 * uses a const buffer to store the element sizes for buffer txq
645 tex_resource_words
[4] = 0;
646 tex_resource_words
[5] = tex_resource_words
[6] = 0;
647 tex_resource_words
[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
);
650 static struct pipe_sampler_view
*
651 texture_buffer_sampler_view(struct r600_context
*rctx
,
652 struct r600_pipe_sampler_view
*view
,
653 unsigned width0
, unsigned height0
)
655 struct r600_texture
*tmp
= (struct r600_texture
*)view
->base
.texture
;
656 struct eg_buf_res_params params
;
658 memset(¶ms
, 0, sizeof(params
));
660 params
.pipe_format
= view
->base
.format
;
661 params
.offset
= view
->base
.u
.buf
.offset
;
662 params
.size
= view
->base
.u
.buf
.size
;
663 params
.swizzle
[0] = view
->base
.swizzle_r
;
664 params
.swizzle
[1] = view
->base
.swizzle_g
;
665 params
.swizzle
[2] = view
->base
.swizzle_b
;
666 params
.swizzle
[3] = view
->base
.swizzle_a
;
668 evergreen_fill_buffer_resource_words(rctx
, view
->base
.texture
,
669 ¶ms
, &view
->skip_mip_address_reloc
,
670 view
->tex_resource_words
);
671 view
->tex_resource
= &tmp
->resource
;
673 if (tmp
->resource
.gpu_address
)
674 LIST_ADDTAIL(&view
->list
, &rctx
->texture_buffers
);
678 struct eg_tex_res_params
{
679 enum pipe_format pipe_format
;
683 unsigned first_level
;
685 unsigned first_layer
;
688 unsigned char swizzle
[4];
691 static int evergreen_fill_tex_resource_words(struct r600_context
*rctx
,
692 struct pipe_resource
*texture
,
693 struct eg_tex_res_params
*params
,
694 bool *skip_mip_address_reloc
,
695 unsigned tex_resource_words
[8])
697 struct r600_screen
*rscreen
= (struct r600_screen
*)rctx
->b
.b
.screen
;
698 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
699 unsigned format
, endian
;
700 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
701 unsigned char array_mode
= 0, non_disp_tiling
= 0;
702 unsigned height
, depth
, width
;
703 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
, fmask_bankh
;
704 struct legacy_surf_level
*surflevel
;
705 unsigned base_level
, first_level
, last_level
;
706 unsigned dim
, last_layer
;
708 bool do_endian_swap
= FALSE
;
710 tile_split
= tmp
->surface
.u
.legacy
.tile_split
;
711 surflevel
= tmp
->surface
.u
.legacy
.level
;
713 /* Texturing with separate depth and stencil. */
714 if (tmp
->db_compatible
) {
715 switch (params
->pipe_format
) {
716 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
717 params
->pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
719 case PIPE_FORMAT_X8Z24_UNORM
:
720 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
721 /* Z24 is always stored like this for DB
724 params
->pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
726 case PIPE_FORMAT_X24S8_UINT
:
727 case PIPE_FORMAT_S8X24_UINT
:
728 case PIPE_FORMAT_X32_S8X24_UINT
:
729 params
->pipe_format
= PIPE_FORMAT_S8_UINT
;
730 tile_split
= tmp
->surface
.u
.legacy
.stencil_tile_split
;
731 surflevel
= tmp
->surface
.u
.legacy
.stencil_level
;
738 do_endian_swap
= !tmp
->db_compatible
;
740 format
= r600_translate_texformat(rctx
->b
.b
.screen
, params
->pipe_format
,
742 &word4
, &yuv_format
, do_endian_swap
);
743 assert(format
!= ~0);
748 endian
= r600_colorformat_endian_swap(format
, do_endian_swap
);
751 first_level
= params
->first_level
;
752 last_level
= params
->last_level
;
753 width
= params
->width0
;
754 height
= params
->height0
;
755 depth
= texture
->depth0
;
757 if (params
->force_level
) {
758 base_level
= params
->force_level
;
761 width
= u_minify(width
, params
->force_level
);
762 height
= u_minify(height
, params
->force_level
);
763 depth
= u_minify(depth
, params
->force_level
);
766 pitch
= surflevel
[base_level
].nblk_x
* util_format_get_blockwidth(params
->pipe_format
);
767 non_disp_tiling
= tmp
->non_disp_tiling
;
769 switch (surflevel
[base_level
].mode
) {
771 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
772 array_mode
= V_028C70_ARRAY_LINEAR_ALIGNED
;
774 case RADEON_SURF_MODE_2D
:
775 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
777 case RADEON_SURF_MODE_1D
:
778 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
781 macro_aspect
= tmp
->surface
.u
.legacy
.mtilea
;
782 bankw
= tmp
->surface
.u
.legacy
.bankw
;
783 bankh
= tmp
->surface
.u
.legacy
.bankh
;
784 tile_split
= eg_tile_split(tile_split
);
785 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
786 bankw
= eg_bank_wh(bankw
);
787 bankh
= eg_bank_wh(bankh
);
788 fmask_bankh
= eg_bank_wh(tmp
->fmask
.bank_height
);
790 /* 128 bit formats require tile type = 1 */
791 if (rscreen
->b
.chip_class
== CAYMAN
) {
792 if (util_format_get_blocksize(params
->pipe_format
) >= 16)
795 nbanks
= eg_num_banks(rscreen
->b
.info
.r600_num_banks
);
797 if (params
->target
== PIPE_TEXTURE_1D_ARRAY
) {
799 depth
= texture
->array_size
;
800 } else if (params
->target
== PIPE_TEXTURE_2D_ARRAY
) {
801 depth
= texture
->array_size
;
802 } else if (params
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
803 depth
= texture
->array_size
/ 6;
805 va
= tmp
->resource
.gpu_address
;
807 /* array type views and views into array types need to use layer offset */
808 dim
= params
->target
;
809 if (params
->target
!= PIPE_TEXTURE_CUBE
)
810 dim
= MAX2(params
->target
, texture
->target
);
812 tex_resource_words
[0] = (S_030000_DIM(r600_tex_dim(dim
, texture
->nr_samples
)) |
813 S_030000_PITCH((pitch
/ 8) - 1) |
814 S_030000_TEX_WIDTH(width
- 1));
815 if (rscreen
->b
.chip_class
== CAYMAN
)
816 tex_resource_words
[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
818 tex_resource_words
[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
819 tex_resource_words
[1] = (S_030004_TEX_HEIGHT(height
- 1) |
820 S_030004_TEX_DEPTH(depth
- 1) |
821 S_030004_ARRAY_MODE(array_mode
));
822 tex_resource_words
[2] = (surflevel
[base_level
].offset
+ va
) >> 8;
824 *skip_mip_address_reloc
= false;
825 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
826 if (texture
->nr_samples
> 1 && rscreen
->has_compressed_msaa_texturing
) {
828 /* disable FMASK (0 = disabled) */
829 tex_resource_words
[3] = 0;
830 *skip_mip_address_reloc
= true;
832 /* FMASK should be in MIP_ADDRESS for multisample textures */
833 tex_resource_words
[3] = (tmp
->fmask
.offset
+ va
) >> 8;
835 } else if (last_level
&& texture
->nr_samples
<= 1) {
836 tex_resource_words
[3] = (surflevel
[1].offset
+ va
) >> 8;
838 tex_resource_words
[3] = (surflevel
[base_level
].offset
+ va
) >> 8;
841 last_layer
= params
->last_layer
;
842 if (params
->target
!= texture
->target
&& depth
== 1) {
843 last_layer
= params
->first_layer
;
845 tex_resource_words
[4] = (word4
|
846 S_030010_ENDIAN_SWAP(endian
));
847 tex_resource_words
[5] = S_030014_BASE_ARRAY(params
->first_layer
) |
848 S_030014_LAST_ARRAY(last_layer
);
849 tex_resource_words
[6] = S_030018_TILE_SPLIT(tile_split
);
851 if (texture
->nr_samples
> 1) {
852 unsigned log_samples
= util_logbase2(texture
->nr_samples
);
853 if (rscreen
->b
.chip_class
== CAYMAN
) {
854 tex_resource_words
[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples
);
856 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
857 tex_resource_words
[5] |= S_030014_LAST_LEVEL(log_samples
);
858 tex_resource_words
[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh
);
860 bool no_mip
= first_level
== last_level
;
862 tex_resource_words
[4] |= S_030010_BASE_LEVEL(first_level
);
863 tex_resource_words
[5] |= S_030014_LAST_LEVEL(last_level
);
864 /* aniso max 16 samples */
865 tex_resource_words
[6] |= S_030018_MAX_ANISO_RATIO(no_mip
? 0 : 4);
868 tex_resource_words
[7] = S_03001C_DATA_FORMAT(format
) |
869 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
) |
870 S_03001C_BANK_WIDTH(bankw
) |
871 S_03001C_BANK_HEIGHT(bankh
) |
872 S_03001C_MACRO_TILE_ASPECT(macro_aspect
) |
873 S_03001C_NUM_BANKS(nbanks
) |
874 S_03001C_DEPTH_SAMPLE_ORDER(tmp
->db_compatible
);
878 struct pipe_sampler_view
*
879 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
880 struct pipe_resource
*texture
,
881 const struct pipe_sampler_view
*state
,
882 unsigned width0
, unsigned height0
,
883 unsigned force_level
)
885 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
886 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
887 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
888 struct eg_tex_res_params params
;
894 /* initialize base object */
896 view
->base
.texture
= NULL
;
897 pipe_reference(NULL
, &texture
->reference
);
898 view
->base
.texture
= texture
;
899 view
->base
.reference
.count
= 1;
900 view
->base
.context
= ctx
;
902 if (state
->target
== PIPE_BUFFER
)
903 return texture_buffer_sampler_view(rctx
, view
, width0
, height0
);
905 memset(¶ms
, 0, sizeof(params
));
906 params
.pipe_format
= state
->format
;
907 params
.force_level
= force_level
;
908 params
.width0
= width0
;
909 params
.height0
= height0
;
910 params
.first_level
= state
->u
.tex
.first_level
;
911 params
.last_level
= state
->u
.tex
.last_level
;
912 params
.first_layer
= state
->u
.tex
.first_layer
;
913 params
.last_layer
= state
->u
.tex
.last_layer
;
914 params
.target
= state
->target
;
915 params
.swizzle
[0] = state
->swizzle_r
;
916 params
.swizzle
[1] = state
->swizzle_g
;
917 params
.swizzle
[2] = state
->swizzle_b
;
918 params
.swizzle
[3] = state
->swizzle_a
;
920 ret
= evergreen_fill_tex_resource_words(rctx
, texture
, ¶ms
,
921 &view
->skip_mip_address_reloc
,
922 view
->tex_resource_words
);
928 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
929 state
->format
== PIPE_FORMAT_S8X24_UINT
||
930 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
931 state
->format
== PIPE_FORMAT_S8_UINT
)
932 view
->is_stencil_sampler
= true;
934 view
->tex_resource
= &tmp
->resource
;
939 static struct pipe_sampler_view
*
940 evergreen_create_sampler_view(struct pipe_context
*ctx
,
941 struct pipe_resource
*tex
,
942 const struct pipe_sampler_view
*state
)
944 return evergreen_create_sampler_view_custom(ctx
, tex
, state
,
945 tex
->width0
, tex
->height0
, 0);
948 static void evergreen_emit_config_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
950 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
951 struct r600_config_state
*a
= (struct r600_config_state
*)atom
;
953 radeon_set_config_reg_seq(cs
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, 3);
954 if (a
->dyn_gpr_enabled
) {
955 radeon_emit(cs
, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx
->r6xx_num_clause_temp_gprs
));
959 radeon_emit(cs
, a
->sq_gpr_resource_mgmt_1
);
960 radeon_emit(cs
, a
->sq_gpr_resource_mgmt_2
);
961 radeon_emit(cs
, a
->sq_gpr_resource_mgmt_3
);
963 radeon_set_config_reg(cs
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (a
->dyn_gpr_enabled
<< 8));
964 if (a
->dyn_gpr_enabled
) {
965 radeon_set_context_reg(cs
, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
,
966 S_028838_PS_GPRS(0x1e) |
967 S_028838_VS_GPRS(0x1e) |
968 S_028838_GS_GPRS(0x1e) |
969 S_028838_ES_GPRS(0x1e) |
970 S_028838_HS_GPRS(0x1e) |
971 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
975 static void evergreen_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
977 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
978 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
980 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP0_X
, 6*4);
981 radeon_emit_array(cs
, (unsigned*)state
, 6*4);
984 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
985 const struct pipe_poly_stipple
*state
)
989 static void evergreen_get_scissor_rect(struct r600_context
*rctx
,
990 unsigned tl_x
, unsigned tl_y
, unsigned br_x
, unsigned br_y
,
991 uint32_t *tl
, uint32_t *br
)
993 struct pipe_scissor_state scissor
= {tl_x
, tl_y
, br_x
, br_y
};
995 evergreen_apply_scissor_bug_workaround(&rctx
->b
, &scissor
);
997 *tl
= S_028240_TL_X(scissor
.minx
) | S_028240_TL_Y(scissor
.miny
);
998 *br
= S_028244_BR_X(scissor
.maxx
) | S_028244_BR_Y(scissor
.maxy
);
1001 struct r600_tex_color_info
{
1010 unsigned fmask_slice
;
1012 boolean export_16bpc
;
1015 static void evergreen_set_color_surface_buffer(struct r600_context
*rctx
,
1016 struct r600_resource
*res
,
1017 enum pipe_format pformat
,
1018 unsigned first_element
,
1019 unsigned last_element
,
1020 struct r600_tex_color_info
*color
)
1022 unsigned format
, swap
, ntype
, endian
;
1023 const struct util_format_description
*desc
;
1024 unsigned block_size
= align(util_format_get_blocksize(res
->b
.b
.format
), 4);
1025 unsigned pitch_alignment
=
1026 MAX2(64, rctx
->screen
->b
.info
.pipe_interleave_bytes
/ block_size
);
1027 unsigned pitch
= align(res
->b
.b
.width0
, pitch_alignment
);
1029 unsigned width_elements
;
1031 width_elements
= last_element
- first_element
+ 1;
1033 format
= r600_translate_colorformat(rctx
->b
.chip_class
, pformat
, FALSE
);
1034 swap
= r600_translate_colorswap(pformat
, FALSE
);
1036 endian
= r600_colorformat_endian_swap(format
, FALSE
);
1038 desc
= util_format_description(pformat
);
1039 for (i
= 0; i
< 4; i
++) {
1040 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1044 ntype
= V_028C70_NUMBER_UNORM
;
1045 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1046 ntype
= V_028C70_NUMBER_SRGB
;
1047 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1048 if (desc
->channel
[i
].normalized
)
1049 ntype
= V_028C70_NUMBER_SNORM
;
1050 else if (desc
->channel
[i
].pure_integer
)
1051 ntype
= V_028C70_NUMBER_SINT
;
1052 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1053 if (desc
->channel
[i
].normalized
)
1054 ntype
= V_028C70_NUMBER_UNORM
;
1055 else if (desc
->channel
[i
].pure_integer
)
1056 ntype
= V_028C70_NUMBER_UINT
;
1058 pitch
= (pitch
/ 8) - 1;
1059 color
->pitch
= S_028C64_PITCH_TILE_MAX(pitch
);
1061 color
->info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1062 color
->info
|= S_028C70_FORMAT(format
) |
1063 S_028C70_COMP_SWAP(swap
) |
1064 S_028C70_BLEND_CLAMP(0) |
1065 S_028C70_BLEND_BYPASS(1) |
1066 S_028C70_NUMBER_TYPE(ntype
) |
1067 S_028C70_ENDIAN(endian
);
1068 color
->attrib
= S_028C74_NON_DISP_TILING_ORDER(1);
1069 color
->ntype
= ntype
;
1070 color
->export_16bpc
= false;
1071 color
->dim
= width_elements
- 1;
1072 color
->slice
= 0; /* (width_elements / 64) - 1;*/
1074 color
->offset
= res
->gpu_address
>> 8;
1076 color
->fmask
= color
->offset
;
1077 color
->fmask_slice
= 0;
1080 static void evergreen_set_color_surface_common(struct r600_context
*rctx
,
1081 struct r600_texture
*rtex
,
1083 unsigned first_layer
,
1084 unsigned last_layer
,
1085 enum pipe_format pformat
,
1086 struct r600_tex_color_info
*color
)
1088 struct r600_screen
*rscreen
= rctx
->screen
;
1089 unsigned pitch
, slice
;
1090 unsigned non_disp_tiling
, macro_aspect
, tile_split
, bankh
, bankw
, fmask_bankh
, nbanks
;
1091 unsigned format
, swap
, ntype
, endian
;
1092 const struct util_format_description
*desc
;
1093 bool blend_clamp
= 0, blend_bypass
= 0, do_endian_swap
= FALSE
;
1096 color
->offset
= rtex
->surface
.u
.legacy
.level
[level
].offset
;
1097 color
->view
= S_028C6C_SLICE_START(first_layer
) |
1098 S_028C6C_SLICE_MAX(last_layer
);
1100 color
->offset
+= rtex
->resource
.gpu_address
;
1101 color
->offset
>>= 8;
1104 pitch
= (rtex
->surface
.u
.legacy
.level
[level
].nblk_x
) / 8 - 1;
1105 slice
= (rtex
->surface
.u
.legacy
.level
[level
].nblk_x
* rtex
->surface
.u
.legacy
.level
[level
].nblk_y
) / 64;
1111 switch (rtex
->surface
.u
.legacy
.level
[level
].mode
) {
1113 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1114 color
->info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1115 non_disp_tiling
= 1;
1117 case RADEON_SURF_MODE_1D
:
1118 color
->info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1
);
1119 non_disp_tiling
= rtex
->non_disp_tiling
;
1121 case RADEON_SURF_MODE_2D
:
1122 color
->info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1
);
1123 non_disp_tiling
= rtex
->non_disp_tiling
;
1126 tile_split
= rtex
->surface
.u
.legacy
.tile_split
;
1127 macro_aspect
= rtex
->surface
.u
.legacy
.mtilea
;
1128 bankw
= rtex
->surface
.u
.legacy
.bankw
;
1129 bankh
= rtex
->surface
.u
.legacy
.bankh
;
1130 if (rtex
->fmask
.size
)
1131 fmask_bankh
= rtex
->fmask
.bank_height
;
1133 fmask_bankh
= rtex
->surface
.u
.legacy
.bankh
;
1134 tile_split
= eg_tile_split(tile_split
);
1135 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1136 bankw
= eg_bank_wh(bankw
);
1137 bankh
= eg_bank_wh(bankh
);
1138 fmask_bankh
= eg_bank_wh(fmask_bankh
);
1140 if (rscreen
->b
.chip_class
== CAYMAN
) {
1141 if (util_format_get_blocksize(pformat
) >= 16)
1142 non_disp_tiling
= 1;
1144 nbanks
= eg_num_banks(rscreen
->b
.info
.r600_num_banks
);
1145 desc
= util_format_description(pformat
);
1146 for (i
= 0; i
< 4; i
++) {
1147 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1151 color
->attrib
= S_028C74_TILE_SPLIT(tile_split
)|
1152 S_028C74_NUM_BANKS(nbanks
) |
1153 S_028C74_BANK_WIDTH(bankw
) |
1154 S_028C74_BANK_HEIGHT(bankh
) |
1155 S_028C74_MACRO_TILE_ASPECT(macro_aspect
) |
1156 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling
) |
1157 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
1159 if (rctx
->b
.chip_class
== CAYMAN
) {
1160 color
->attrib
|= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] ==
1163 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1164 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
1165 color
->attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1166 S_028C74_NUM_FRAGMENTS(log_samples
);
1170 ntype
= V_028C70_NUMBER_UNORM
;
1171 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1172 ntype
= V_028C70_NUMBER_SRGB
;
1173 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1174 if (desc
->channel
[i
].normalized
)
1175 ntype
= V_028C70_NUMBER_SNORM
;
1176 else if (desc
->channel
[i
].pure_integer
)
1177 ntype
= V_028C70_NUMBER_SINT
;
1178 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1179 if (desc
->channel
[i
].normalized
)
1180 ntype
= V_028C70_NUMBER_UNORM
;
1181 else if (desc
->channel
[i
].pure_integer
)
1182 ntype
= V_028C70_NUMBER_UINT
;
1185 if (R600_BIG_ENDIAN
)
1186 do_endian_swap
= !rtex
->db_compatible
;
1188 format
= r600_translate_colorformat(rctx
->b
.chip_class
, pformat
, do_endian_swap
);
1189 assert(format
!= ~0);
1190 swap
= r600_translate_colorswap(pformat
, do_endian_swap
);
1193 endian
= r600_colorformat_endian_swap(format
, do_endian_swap
);
1195 /* blend clamp should be set for all NORM/SRGB types */
1196 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
1197 ntype
== V_028C70_NUMBER_SRGB
)
1200 /* set blend bypass according to docs if SINT/UINT or
1201 8/24 COLOR variants */
1202 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1203 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1204 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1209 color
->ntype
= ntype
;
1210 color
->info
|= S_028C70_FORMAT(format
) |
1211 S_028C70_COMP_SWAP(swap
) |
1212 S_028C70_BLEND_CLAMP(blend_clamp
) |
1213 S_028C70_BLEND_BYPASS(blend_bypass
) |
1214 S_028C70_NUMBER_TYPE(ntype
) |
1215 S_028C70_ENDIAN(endian
);
1217 if (rtex
->fmask
.size
) {
1218 color
->info
|= S_028C70_COMPRESSION(1);
1221 /* EXPORT_NORM is an optimzation that can be enabled for better
1222 * performance in certain cases.
1223 * EXPORT_NORM can be enabled if:
1224 * - 11-bit or smaller UNORM/SNORM/SRGB
1225 * - 16-bit or smaller FLOAT
1227 color
->export_16bpc
= false;
1228 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1229 ((desc
->channel
[i
].size
< 12 &&
1230 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1231 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
1232 (desc
->channel
[i
].size
< 17 &&
1233 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1234 color
->info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
1235 color
->export_16bpc
= true;
1238 color
->pitch
= S_028C64_PITCH_TILE_MAX(pitch
);
1239 color
->slice
= S_028C68_SLICE_TILE_MAX(slice
);
1241 if (rtex
->fmask
.size
) {
1242 color
->fmask
= (rtex
->resource
.gpu_address
+ rtex
->fmask
.offset
) >> 8;
1243 color
->fmask_slice
= S_028C88_TILE_MAX(rtex
->fmask
.slice_tile_max
);
1245 color
->fmask
= color
->offset
;
1246 color
->fmask_slice
= S_028C88_TILE_MAX(slice
);
1251 * This function intializes the CB* register values for RATs. It is meant
1252 * to be used for 1D aligned buffers that do not have an associated
1255 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
1256 struct r600_surface
*surf
)
1258 struct pipe_resource
*pipe_buffer
= surf
->base
.texture
;
1259 struct r600_tex_color_info color
;
1261 evergreen_set_color_surface_buffer(rctx
, (struct r600_resource
*)surf
->base
.texture
,
1262 surf
->base
.format
, 0, pipe_buffer
->width0
,
1265 surf
->cb_color_base
= color
.offset
;
1266 surf
->cb_color_dim
= color
.dim
;
1267 surf
->cb_color_info
= color
.info
| S_028C70_RAT(1);
1268 surf
->cb_color_pitch
= color
.pitch
;
1269 surf
->cb_color_slice
= color
.slice
;
1270 surf
->cb_color_view
= color
.view
;
1271 surf
->cb_color_attrib
= color
.attrib
;
1272 surf
->cb_color_fmask
= color
.fmask
;
1273 surf
->cb_color_fmask_slice
= color
.fmask_slice
;
1275 surf
->cb_color_view
= 0;
1277 /* Set the buffer range the GPU will have access to: */
1278 util_range_add(&r600_resource(pipe_buffer
)->valid_buffer_range
,
1279 0, pipe_buffer
->width0
);
1283 void evergreen_init_color_surface(struct r600_context
*rctx
,
1284 struct r600_surface
*surf
)
1286 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1287 unsigned level
= surf
->base
.u
.tex
.level
;
1288 struct r600_tex_color_info color
;
1290 evergreen_set_color_surface_common(rctx
, rtex
, level
,
1291 surf
->base
.u
.tex
.first_layer
,
1292 surf
->base
.u
.tex
.last_layer
,
1296 surf
->alphatest_bypass
= color
.ntype
== V_028C70_NUMBER_UINT
||
1297 color
.ntype
== V_028C70_NUMBER_SINT
;
1298 surf
->export_16bpc
= color
.export_16bpc
;
1300 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1301 surf
->cb_color_base
= color
.offset
;
1302 surf
->cb_color_dim
= color
.dim
;
1303 surf
->cb_color_info
= color
.info
;
1304 surf
->cb_color_pitch
= color
.pitch
;
1305 surf
->cb_color_slice
= color
.slice
;
1306 surf
->cb_color_view
= color
.view
;
1307 surf
->cb_color_attrib
= color
.attrib
;
1308 surf
->cb_color_fmask
= color
.fmask
;
1309 surf
->cb_color_fmask_slice
= color
.fmask_slice
;
1311 surf
->color_initialized
= true;
1314 static void evergreen_init_depth_surface(struct r600_context
*rctx
,
1315 struct r600_surface
*surf
)
1317 struct r600_screen
*rscreen
= rctx
->screen
;
1318 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1319 unsigned level
= surf
->base
.u
.tex
.level
;
1320 struct legacy_surf_level
*levelinfo
= &rtex
->surface
.u
.legacy
.level
[level
];
1322 unsigned format
, array_mode
;
1323 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1326 format
= r600_translate_dbformat(surf
->base
.format
);
1327 assert(format
!= ~0);
1329 offset
= rtex
->resource
.gpu_address
;
1330 offset
+= rtex
->surface
.u
.legacy
.level
[level
].offset
;
1332 switch (rtex
->surface
.u
.legacy
.level
[level
].mode
) {
1333 case RADEON_SURF_MODE_2D
:
1334 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1336 case RADEON_SURF_MODE_1D
:
1337 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1339 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1342 tile_split
= rtex
->surface
.u
.legacy
.tile_split
;
1343 macro_aspect
= rtex
->surface
.u
.legacy
.mtilea
;
1344 bankw
= rtex
->surface
.u
.legacy
.bankw
;
1345 bankh
= rtex
->surface
.u
.legacy
.bankh
;
1346 tile_split
= eg_tile_split(tile_split
);
1347 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1348 bankw
= eg_bank_wh(bankw
);
1349 bankh
= eg_bank_wh(bankh
);
1350 nbanks
= eg_num_banks(rscreen
->b
.info
.r600_num_banks
);
1353 surf
->db_z_info
= S_028040_ARRAY_MODE(array_mode
) |
1354 S_028040_FORMAT(format
) |
1355 S_028040_TILE_SPLIT(tile_split
)|
1356 S_028040_NUM_BANKS(nbanks
) |
1357 S_028040_BANK_WIDTH(bankw
) |
1358 S_028040_BANK_HEIGHT(bankh
) |
1359 S_028040_MACRO_TILE_ASPECT(macro_aspect
);
1360 if (rscreen
->b
.chip_class
== CAYMAN
&& rtex
->resource
.b
.b
.nr_samples
> 1) {
1361 surf
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
1364 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
1366 surf
->db_depth_base
= offset
;
1367 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1368 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1369 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX(levelinfo
->nblk_x
/ 8 - 1) |
1370 S_028058_HEIGHT_TILE_MAX(levelinfo
->nblk_y
/ 8 - 1);
1371 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX(levelinfo
->nblk_x
*
1372 levelinfo
->nblk_y
/ 64 - 1);
1374 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1375 uint64_t stencil_offset
;
1376 unsigned stile_split
= rtex
->surface
.u
.legacy
.stencil_tile_split
;
1378 stile_split
= eg_tile_split(stile_split
);
1380 stencil_offset
= rtex
->surface
.u
.legacy
.stencil_level
[level
].offset
;
1381 stencil_offset
+= rtex
->resource
.gpu_address
;
1383 surf
->db_stencil_base
= stencil_offset
>> 8;
1384 surf
->db_stencil_info
= S_028044_FORMAT(V_028044_STENCIL_8
) |
1385 S_028044_TILE_SPLIT(stile_split
);
1387 surf
->db_stencil_base
= offset
;
1388 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1389 * Older kernels are out of luck. */
1390 surf
->db_stencil_info
= rctx
->screen
->b
.info
.drm_minor
>= 18 ?
1391 S_028044_FORMAT(V_028044_STENCIL_INVALID
) :
1392 S_028044_FORMAT(V_028044_STENCIL_8
);
1395 /* use htile only for first level */
1396 if (rtex
->htile_buffer
&& !level
) {
1397 uint64_t va
= rtex
->htile_buffer
->gpu_address
;
1398 surf
->db_htile_data_base
= va
>> 8;
1399 surf
->db_htile_surface
= S_028ABC_HTILE_WIDTH(1) |
1400 S_028ABC_HTILE_HEIGHT(1) |
1401 S_028ABC_FULL_CACHE(1);
1402 surf
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
1403 surf
->db_preload_control
= 0;
1406 surf
->depth_initialized
= true;
1409 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
1410 const struct pipe_framebuffer_state
*state
)
1412 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1413 struct r600_surface
*surf
;
1414 struct r600_texture
*rtex
;
1415 uint32_t i
, log_samples
;
1417 /* Flush TC when changing the framebuffer state, because the only
1418 * client not using TC that can change textures is the framebuffer.
1419 * Other places don't typically have to flush TC.
1421 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
|
1422 R600_CONTEXT_FLUSH_AND_INV
|
1423 R600_CONTEXT_FLUSH_AND_INV_CB
|
1424 R600_CONTEXT_FLUSH_AND_INV_CB_META
|
1425 R600_CONTEXT_FLUSH_AND_INV_DB
|
1426 R600_CONTEXT_FLUSH_AND_INV_DB_META
|
1427 R600_CONTEXT_INV_TEX_CACHE
;
1429 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1432 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1433 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&& state
->cbufs
[0] &&
1434 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1435 rctx
->framebuffer
.compressed_cb_mask
= 0;
1436 rctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
1438 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1439 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1443 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1445 r600_context_add_resource_size(ctx
, state
->cbufs
[i
]->texture
);
1447 if (!surf
->color_initialized
) {
1448 evergreen_init_color_surface(rctx
, surf
);
1451 if (!surf
->export_16bpc
) {
1452 rctx
->framebuffer
.export_16bpc
= false;
1455 if (rtex
->fmask
.size
) {
1456 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1460 /* Update alpha-test state dependencies.
1461 * Alpha-test is done on the first colorbuffer only. */
1462 if (state
->nr_cbufs
) {
1463 bool alphatest_bypass
= false;
1464 bool export_16bpc
= true;
1466 surf
= (struct r600_surface
*)state
->cbufs
[0];
1468 alphatest_bypass
= surf
->alphatest_bypass
;
1469 export_16bpc
= surf
->export_16bpc
;
1472 if (rctx
->alphatest_state
.bypass
!= alphatest_bypass
) {
1473 rctx
->alphatest_state
.bypass
= alphatest_bypass
;
1474 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1476 if (rctx
->alphatest_state
.cb0_export_16bpc
!= export_16bpc
) {
1477 rctx
->alphatest_state
.cb0_export_16bpc
= export_16bpc
;
1478 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1484 surf
= (struct r600_surface
*)state
->zsbuf
;
1486 r600_context_add_resource_size(ctx
, state
->zsbuf
->texture
);
1488 if (!surf
->depth_initialized
) {
1489 evergreen_init_depth_surface(rctx
, surf
);
1492 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1493 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1494 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
1497 if (rctx
->db_state
.rsurf
!= surf
) {
1498 rctx
->db_state
.rsurf
= surf
;
1499 r600_mark_atom_dirty(rctx
, &rctx
->db_state
.atom
);
1500 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1502 } else if (rctx
->db_state
.rsurf
) {
1503 rctx
->db_state
.rsurf
= NULL
;
1504 r600_mark_atom_dirty(rctx
, &rctx
->db_state
.atom
);
1505 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1508 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1509 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1510 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1513 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1514 rctx
->alphatest_state
.bypass
= false;
1515 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1518 log_samples
= util_logbase2(rctx
->framebuffer
.nr_samples
);
1519 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1520 if ((rctx
->b
.chip_class
== CAYMAN
||
1521 rctx
->b
.family
== CHIP_RV770
) &&
1522 rctx
->db_misc_state
.log_samples
!= log_samples
) {
1523 rctx
->db_misc_state
.log_samples
= log_samples
;
1524 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1528 /* Calculate the CS size. */
1529 rctx
->framebuffer
.atom
.num_dw
= 4; /* SCISSOR */
1532 if (rctx
->b
.chip_class
== EVERGREEN
)
1533 rctx
->framebuffer
.atom
.num_dw
+= 17; /* Evergreen */
1535 rctx
->framebuffer
.atom
.num_dw
+= 28; /* Cayman */
1538 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 23;
1539 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 2;
1540 rctx
->framebuffer
.atom
.num_dw
+= (12 - state
->nr_cbufs
) * 3;
1544 rctx
->framebuffer
.atom
.num_dw
+= 24;
1545 rctx
->framebuffer
.atom
.num_dw
+= 2;
1546 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1547 rctx
->framebuffer
.atom
.num_dw
+= 4;
1550 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1552 r600_set_sample_locations_constant_buffer(rctx
);
1553 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
1556 static void evergreen_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
1558 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1560 if (rctx
->ps_iter_samples
== min_samples
)
1563 rctx
->ps_iter_samples
= min_samples
;
1564 if (rctx
->framebuffer
.nr_samples
> 1) {
1565 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1570 static uint32_t sample_locs_8x
[] = {
1571 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1572 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1573 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1574 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1575 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1576 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1577 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1578 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1580 static unsigned max_dist_8x
= 7;
1582 static void evergreen_get_sample_position(struct pipe_context
*ctx
,
1583 unsigned sample_count
,
1584 unsigned sample_index
,
1591 switch (sample_count
) {
1594 out_value
[0] = out_value
[1] = 0.5;
1597 offset
= 4 * (sample_index
* 2);
1598 val
.idx
= (eg_sample_locs_2x
[0] >> offset
) & 0xf;
1599 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1600 val
.idx
= (eg_sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1601 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1604 offset
= 4 * (sample_index
* 2);
1605 val
.idx
= (eg_sample_locs_4x
[0] >> offset
) & 0xf;
1606 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1607 val
.idx
= (eg_sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1608 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1611 offset
= 4 * (sample_index
% 4 * 2);
1612 index
= (sample_index
/ 4);
1613 val
.idx
= (sample_locs_8x
[index
] >> offset
) & 0xf;
1614 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1615 val
.idx
= (sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1616 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1621 static void evergreen_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
, int ps_iter_samples
)
1624 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1625 unsigned max_dist
= 0;
1627 switch (nr_samples
) {
1632 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, ARRAY_SIZE(eg_sample_locs_2x
));
1633 radeon_emit_array(cs
, eg_sample_locs_2x
, ARRAY_SIZE(eg_sample_locs_2x
));
1634 max_dist
= eg_max_dist_2x
;
1637 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, ARRAY_SIZE(eg_sample_locs_4x
));
1638 radeon_emit_array(cs
, eg_sample_locs_4x
, ARRAY_SIZE(eg_sample_locs_4x
));
1639 max_dist
= eg_max_dist_4x
;
1642 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, ARRAY_SIZE(sample_locs_8x
));
1643 radeon_emit_array(cs
, sample_locs_8x
, ARRAY_SIZE(sample_locs_8x
));
1644 max_dist
= max_dist_8x
;
1648 if (nr_samples
> 1) {
1649 radeon_set_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1650 radeon_emit(cs
, S_028C00_LAST_PIXEL(1) |
1651 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1652 radeon_emit(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1653 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1654 radeon_set_context_reg(cs
, EG_R_028A4C_PA_SC_MODE_CNTL_1
,
1655 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1) |
1656 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1657 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1659 radeon_set_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1660 radeon_emit(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1661 radeon_emit(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1662 radeon_set_context_reg(cs
, EG_R_028A4C_PA_SC_MODE_CNTL_1
,
1663 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1664 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1668 static void evergreen_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1670 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1671 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1672 unsigned nr_cbufs
= state
->nr_cbufs
;
1674 struct r600_texture
*tex
= NULL
;
1675 struct r600_surface
*cb
= NULL
;
1677 /* XXX support more colorbuffers once we need them */
1678 assert(nr_cbufs
<= 8);
1683 for (i
= 0; i
< nr_cbufs
; i
++) {
1684 unsigned reloc
, cmask_reloc
;
1686 cb
= (struct r600_surface
*)state
->cbufs
[i
];
1688 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1689 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1693 tex
= (struct r600_texture
*)cb
->base
.texture
;
1694 reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1696 (struct r600_resource
*)cb
->base
.texture
,
1697 RADEON_USAGE_READWRITE
,
1698 tex
->resource
.b
.b
.nr_samples
> 1 ?
1699 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1700 RADEON_PRIO_COLOR_BUFFER
);
1702 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
1703 cmask_reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1704 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
1707 cmask_reloc
= reloc
;
1710 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 13);
1711 radeon_emit(cs
, cb
->cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
1712 radeon_emit(cs
, cb
->cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
1713 radeon_emit(cs
, cb
->cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
1714 radeon_emit(cs
, cb
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
1715 radeon_emit(cs
, cb
->cb_color_info
| tex
->cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
1716 radeon_emit(cs
, cb
->cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
1717 radeon_emit(cs
, cb
->cb_color_dim
); /* R_028C78_CB_COLOR0_DIM */
1718 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* R_028C7C_CB_COLOR0_CMASK */
1719 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1720 radeon_emit(cs
, cb
->cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
1721 radeon_emit(cs
, cb
->cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1722 radeon_emit(cs
, tex
->color_clear_value
[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1723 radeon_emit(cs
, tex
->color_clear_value
[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1725 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1726 radeon_emit(cs
, reloc
);
1728 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1729 radeon_emit(cs
, reloc
);
1731 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1732 radeon_emit(cs
, cmask_reloc
);
1734 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1735 radeon_emit(cs
, reloc
);
1737 /* set CB_COLOR1_INFO for possible dual-src blending */
1738 if (rctx
->framebuffer
.dual_src_blend
&& i
== 1 && state
->cbufs
[0]) {
1739 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C,
1740 cb
->cb_color_info
| tex
->cb_color_info
);
1744 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
1746 radeon_set_context_reg(cs
, R_028E50_CB_COLOR8_INFO
+ (i
- 8) * 0x1C, 0);
1750 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
1751 unsigned reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1753 (struct r600_resource
*)state
->zsbuf
->texture
,
1754 RADEON_USAGE_READWRITE
,
1755 zb
->base
.texture
->nr_samples
> 1 ?
1756 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
1757 RADEON_PRIO_DEPTH_BUFFER
);
1759 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
1761 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 8);
1762 radeon_emit(cs
, zb
->db_z_info
); /* R_028040_DB_Z_INFO */
1763 radeon_emit(cs
, zb
->db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1764 radeon_emit(cs
, zb
->db_depth_base
); /* R_028048_DB_Z_READ_BASE */
1765 radeon_emit(cs
, zb
->db_stencil_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1766 radeon_emit(cs
, zb
->db_depth_base
); /* R_028050_DB_Z_WRITE_BASE */
1767 radeon_emit(cs
, zb
->db_stencil_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1768 radeon_emit(cs
, zb
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1769 radeon_emit(cs
, zb
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1771 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1772 radeon_emit(cs
, reloc
);
1774 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1775 radeon_emit(cs
, reloc
);
1777 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1778 radeon_emit(cs
, reloc
);
1780 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1781 radeon_emit(cs
, reloc
);
1782 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1783 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1784 * Older kernels are out of luck. */
1785 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
1786 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
1787 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
1790 /* Framebuffer dimensions. */
1791 evergreen_get_scissor_rect(rctx
, 0, 0, state
->width
, state
->height
, &tl
, &br
);
1793 radeon_set_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
1794 radeon_emit(cs
, tl
); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1795 radeon_emit(cs
, br
); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1797 if (rctx
->b
.chip_class
== EVERGREEN
) {
1798 evergreen_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
, rctx
->ps_iter_samples
);
1800 unsigned sc_mode_cntl_1
=
1801 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1802 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1804 if (rctx
->framebuffer
.nr_samples
> 1)
1805 cayman_emit_msaa_sample_locs(cs
, rctx
->framebuffer
.nr_samples
);
1806 cayman_emit_msaa_config(cs
, rctx
->framebuffer
.nr_samples
,
1807 rctx
->ps_iter_samples
, 0, sc_mode_cntl_1
);
1811 static void evergreen_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
1813 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1814 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
1815 float offset_units
= state
->offset_units
;
1816 float offset_scale
= state
->offset_scale
;
1817 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
1819 if (!state
->offset_units_unscaled
) {
1820 switch (state
->zs_format
) {
1821 case PIPE_FORMAT_Z24X8_UNORM
:
1822 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1823 case PIPE_FORMAT_X8Z24_UNORM
:
1824 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1825 offset_units
*= 2.0f
;
1826 pa_su_poly_offset_db_fmt_cntl
=
1827 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1829 case PIPE_FORMAT_Z16_UNORM
:
1830 offset_units
*= 4.0f
;
1831 pa_su_poly_offset_db_fmt_cntl
=
1832 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1835 pa_su_poly_offset_db_fmt_cntl
=
1836 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1837 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1841 radeon_set_context_reg_seq(cs
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
1842 radeon_emit(cs
, fui(offset_scale
));
1843 radeon_emit(cs
, fui(offset_units
));
1844 radeon_emit(cs
, fui(offset_scale
));
1845 radeon_emit(cs
, fui(offset_units
));
1847 radeon_set_context_reg(cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1848 pa_su_poly_offset_db_fmt_cntl
);
1851 static void evergreen_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1853 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1854 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1855 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1856 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1858 radeon_set_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1859 radeon_emit(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
1860 /* This must match the used export instructions exactly.
1861 * Other values may lead to undefined behavior and hangs.
1863 radeon_emit(cs
, ps_colormask
); /* R_02823C_CB_SHADER_MASK */
1866 static void evergreen_emit_db_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1868 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1869 struct r600_db_state
*a
= (struct r600_db_state
*)atom
;
1871 if (a
->rsurf
&& a
->rsurf
->db_htile_surface
) {
1872 struct r600_texture
*rtex
= (struct r600_texture
*)a
->rsurf
->base
.texture
;
1875 radeon_set_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear_value
));
1876 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, a
->rsurf
->db_htile_surface
);
1877 radeon_set_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, a
->rsurf
->db_preload_control
);
1878 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, a
->rsurf
->db_htile_data_base
);
1879 reloc_idx
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rtex
->htile_buffer
,
1880 RADEON_USAGE_READWRITE
, RADEON_PRIO_HTILE
);
1881 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1882 radeon_emit(cs
, reloc_idx
);
1884 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, 0);
1885 radeon_set_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0);
1889 static void evergreen_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1891 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1892 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1893 unsigned db_render_control
= 0;
1894 unsigned db_count_control
= 0;
1895 unsigned db_render_override
=
1896 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
1897 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
1899 if (rctx
->b
.num_occlusion_queries
> 0 &&
1900 !a
->occlusion_queries_disabled
) {
1901 db_count_control
|= S_028004_PERFECT_ZPASS_COUNTS(1);
1902 if (rctx
->b
.chip_class
== CAYMAN
) {
1903 db_count_control
|= S_028004_SAMPLE_RATE(a
->log_samples
);
1905 db_render_override
|= S_02800C_NOOP_CULL_DISABLE(1);
1907 db_count_control
|= S_028004_ZPASS_INCREMENT_DISABLE(1);
1910 /* This is to fix a lockup when hyperz and alpha test are enabled at
1911 * the same time somehow GPU get confuse on which order to pick for
1914 if (rctx
->alphatest_state
.sx_alpha_test_control
)
1915 db_render_override
|= S_02800C_FORCE_SHADER_Z_ORDER(1);
1917 if (a
->flush_depthstencil_through_cb
) {
1918 assert(a
->copy_depth
|| a
->copy_stencil
);
1920 db_render_control
|= S_028000_DEPTH_COPY_ENABLE(a
->copy_depth
) |
1921 S_028000_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
1922 S_028000_COPY_CENTROID(1) |
1923 S_028000_COPY_SAMPLE(a
->copy_sample
);
1924 } else if (a
->flush_depth_inplace
|| a
->flush_stencil_inplace
) {
1925 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(a
->flush_depth_inplace
) |
1926 S_028000_STENCIL_COMPRESS_DISABLE(a
->flush_stencil_inplace
);
1927 db_render_override
|= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1929 if (a
->htile_clear
) {
1930 /* FIXME we might want to disable cliprect here */
1931 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(1);
1934 radeon_set_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1935 radeon_emit(cs
, db_render_control
); /* R_028000_DB_RENDER_CONTROL */
1936 radeon_emit(cs
, db_count_control
); /* R_028004_DB_COUNT_CONTROL */
1937 radeon_set_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
1938 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
1941 static void evergreen_emit_vertex_buffers(struct r600_context
*rctx
,
1942 struct r600_vertexbuf_state
*state
,
1943 unsigned resource_offset
,
1946 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1947 uint32_t dirty_mask
= state
->dirty_mask
;
1949 while (dirty_mask
) {
1950 struct pipe_vertex_buffer
*vb
;
1951 struct r600_resource
*rbuffer
;
1953 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
1955 vb
= &state
->vb
[buffer_index
];
1956 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
1959 va
= rbuffer
->gpu_address
+ vb
->buffer_offset
;
1961 /* fetch resources start at index 992 */
1962 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
1963 radeon_emit(cs
, (resource_offset
+ buffer_index
) * 8);
1964 radeon_emit(cs
, va
); /* RESOURCEi_WORD0 */
1965 radeon_emit(cs
, rbuffer
->b
.b
.width0
- vb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
1966 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1967 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1968 S_030008_STRIDE(vb
->stride
) |
1969 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
1970 radeon_emit(cs
, /* RESOURCEi_WORD3 */
1971 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
1972 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
1973 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
1974 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
1975 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1976 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1977 radeon_emit(cs
, 0); /* RESOURCEi_WORD6 */
1978 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
1980 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1981 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
1982 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
));
1984 state
->dirty_mask
= 0;
1987 static void evergreen_fs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
1989 evergreen_emit_vertex_buffers(rctx
, &rctx
->vertex_buffer_state
, EG_FETCH_CONSTANTS_OFFSET_FS
, 0);
1992 static void evergreen_cs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
1994 evergreen_emit_vertex_buffers(rctx
, &rctx
->cs_vertex_buffer_state
, EG_FETCH_CONSTANTS_OFFSET_CS
,
1995 RADEON_CP_PACKET3_COMPUTE_MODE
);
1998 static void evergreen_emit_constant_buffers(struct r600_context
*rctx
,
1999 struct r600_constbuf_state
*state
,
2000 unsigned buffer_id_base
,
2001 unsigned reg_alu_constbuf_size
,
2002 unsigned reg_alu_const_cache
,
2005 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2006 uint32_t dirty_mask
= state
->dirty_mask
;
2008 while (dirty_mask
) {
2009 struct pipe_constant_buffer
*cb
;
2010 struct r600_resource
*rbuffer
;
2012 unsigned buffer_index
= ffs(dirty_mask
) - 1;
2013 unsigned gs_ring_buffer
= (buffer_index
== R600_GS_RING_CONST_BUFFER
);
2015 cb
= &state
->cb
[buffer_index
];
2016 rbuffer
= (struct r600_resource
*)cb
->buffer
;
2019 va
= rbuffer
->gpu_address
+ cb
->buffer_offset
;
2021 if (!gs_ring_buffer
) {
2022 radeon_set_context_reg_flag(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
2023 DIV_ROUND_UP(cb
->buffer_size
, 256), pkt_flags
);
2024 radeon_set_context_reg_flag(cs
, reg_alu_const_cache
+ buffer_index
* 4, va
>> 8,
2028 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2029 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2030 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
));
2032 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
2033 radeon_emit(cs
, (buffer_id_base
+ buffer_index
) * 8);
2034 radeon_emit(cs
, va
); /* RESOURCEi_WORD0 */
2035 radeon_emit(cs
, rbuffer
->b
.b
.width0
- cb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
2036 radeon_emit(cs
, /* RESOURCEi_WORD2 */
2037 S_030008_ENDIAN_SWAP(gs_ring_buffer
? ENDIAN_NONE
: r600_endian_swap(32)) |
2038 S_030008_STRIDE(gs_ring_buffer
? 4 : 16) |
2039 S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
2040 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT
));
2041 radeon_emit(cs
, /* RESOURCEi_WORD3 */
2042 S_03000C_UNCACHED(gs_ring_buffer
? 1 : 0) |
2043 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
2044 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
2045 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
2046 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
2047 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
2048 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
2049 radeon_emit(cs
, 0); /* RESOURCEi_WORD6 */
2050 radeon_emit(cs
, /* RESOURCEi_WORD7 */
2051 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
));
2053 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2054 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2055 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
));
2057 dirty_mask
&= ~(1 << buffer_index
);
2059 state
->dirty_mask
= 0;
2062 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
2063 static void evergreen_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2065 if (rctx
->vs_shader
->current
->shader
.vs_as_ls
) {
2066 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
],
2067 EG_FETCH_CONSTANTS_OFFSET_LS
,
2068 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
,
2069 R_028F40_ALU_CONST_CACHE_LS_0
,
2070 0 /* PKT3 flags */);
2072 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
],
2073 EG_FETCH_CONSTANTS_OFFSET_VS
,
2074 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
2075 R_028980_ALU_CONST_CACHE_VS_0
,
2076 0 /* PKT3 flags */);
2080 static void evergreen_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2082 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
],
2083 EG_FETCH_CONSTANTS_OFFSET_GS
,
2084 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
2085 R_0289C0_ALU_CONST_CACHE_GS_0
,
2086 0 /* PKT3 flags */);
2089 static void evergreen_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2091 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
],
2092 EG_FETCH_CONSTANTS_OFFSET_PS
,
2093 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
2094 R_028940_ALU_CONST_CACHE_PS_0
,
2095 0 /* PKT3 flags */);
2098 static void evergreen_emit_cs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2100 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_COMPUTE
],
2101 EG_FETCH_CONSTANTS_OFFSET_CS
,
2102 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
,
2103 R_028F40_ALU_CONST_CACHE_LS_0
,
2104 RADEON_CP_PACKET3_COMPUTE_MODE
);
2107 /* tes constants can be emitted to VS or ES - which are common */
2108 static void evergreen_emit_tes_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2110 if (!rctx
->tes_shader
)
2112 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_TESS_EVAL
],
2113 EG_FETCH_CONSTANTS_OFFSET_VS
,
2114 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
2115 R_028980_ALU_CONST_CACHE_VS_0
,
2119 static void evergreen_emit_tcs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2121 if (!rctx
->tes_shader
)
2123 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_TESS_CTRL
],
2124 EG_FETCH_CONSTANTS_OFFSET_HS
,
2125 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0
,
2126 R_028F00_ALU_CONST_CACHE_HS_0
,
2130 static void evergreen_emit_sampler_views(struct r600_context
*rctx
,
2131 struct r600_samplerview_state
*state
,
2132 unsigned resource_id_base
, unsigned pkt_flags
)
2134 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2135 uint32_t dirty_mask
= state
->dirty_mask
;
2137 while (dirty_mask
) {
2138 struct r600_pipe_sampler_view
*rview
;
2139 unsigned resource_index
= u_bit_scan(&dirty_mask
);
2142 rview
= state
->views
[resource_index
];
2145 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
2146 radeon_emit(cs
, (resource_id_base
+ resource_index
) * 8);
2147 radeon_emit_array(cs
, rview
->tex_resource_words
, 8);
2149 reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rview
->tex_resource
,
2151 r600_get_sampler_view_priority(rview
->tex_resource
));
2152 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2153 radeon_emit(cs
, reloc
);
2155 if (!rview
->skip_mip_address_reloc
) {
2156 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2157 radeon_emit(cs
, reloc
);
2160 state
->dirty_mask
= 0;
2163 static void evergreen_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2165 if (rctx
->vs_shader
->current
->shader
.vs_as_ls
) {
2166 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
,
2167 EG_FETCH_CONSTANTS_OFFSET_LS
+ R600_MAX_CONST_BUFFERS
, 0);
2169 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
,
2170 EG_FETCH_CONSTANTS_OFFSET_VS
+ R600_MAX_CONST_BUFFERS
, 0);
2174 static void evergreen_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2176 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
,
2177 EG_FETCH_CONSTANTS_OFFSET_GS
+ R600_MAX_CONST_BUFFERS
, 0);
2180 static void evergreen_emit_tcs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2182 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_CTRL
].views
,
2183 EG_FETCH_CONSTANTS_OFFSET_HS
+ R600_MAX_CONST_BUFFERS
, 0);
2186 static void evergreen_emit_tes_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2188 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_EVAL
].views
,
2189 EG_FETCH_CONSTANTS_OFFSET_VS
+ R600_MAX_CONST_BUFFERS
, 0);
2192 static void evergreen_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2194 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
,
2195 EG_FETCH_CONSTANTS_OFFSET_PS
+ R600_MAX_CONST_BUFFERS
, 0);
2198 static void evergreen_emit_cs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2200 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
].views
,
2201 EG_FETCH_CONSTANTS_OFFSET_CS
+ 2, RADEON_CP_PACKET3_COMPUTE_MODE
);
2204 static void evergreen_emit_sampler_states(struct r600_context
*rctx
,
2205 struct r600_textures_info
*texinfo
,
2206 unsigned resource_id_base
,
2207 unsigned border_index_reg
,
2210 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2211 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
2213 while (dirty_mask
) {
2214 struct r600_pipe_sampler_state
*rstate
;
2215 unsigned i
= u_bit_scan(&dirty_mask
);
2217 rstate
= texinfo
->states
.states
[i
];
2220 radeon_emit(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0) | pkt_flags
);
2221 radeon_emit(cs
, (resource_id_base
+ i
) * 3);
2222 radeon_emit_array(cs
, rstate
->tex_sampler_words
, 3);
2224 if (rstate
->border_color_use
) {
2225 radeon_set_config_reg_seq(cs
, border_index_reg
, 5);
2227 radeon_emit_array(cs
, rstate
->border_color
.ui
, 4);
2230 texinfo
->states
.dirty_mask
= 0;
2233 static void evergreen_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2235 if (rctx
->vs_shader
->current
->shader
.vs_as_ls
) {
2236 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 72,
2237 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX
, 0);
2239 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18,
2240 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
, 0);
2244 static void evergreen_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2246 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36,
2247 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX
, 0);
2250 static void evergreen_emit_tcs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2252 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_CTRL
], 54,
2253 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX
, 0);
2256 static void evergreen_emit_tes_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2258 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_EVAL
], 18,
2259 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
, 0);
2262 static void evergreen_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2264 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0,
2265 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
, 0);
2268 static void evergreen_emit_cs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2270 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
], 90,
2271 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX
,
2272 RADEON_CP_PACKET3_COMPUTE_MODE
);
2275 static void evergreen_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2277 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2278 uint8_t mask
= s
->sample_mask
;
2280 radeon_set_context_reg(rctx
->b
.gfx
.cs
, R_028C3C_PA_SC_AA_MASK
,
2281 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2284 static void cayman_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2286 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2287 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2288 uint16_t mask
= s
->sample_mask
;
2290 radeon_set_context_reg_seq(cs
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2291 radeon_emit(cs
, mask
| (mask
<< 16)); /* X0Y0_X1Y0 */
2292 radeon_emit(cs
, mask
| (mask
<< 16)); /* X0Y1_X1Y1 */
2295 static void evergreen_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2297 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2298 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
2299 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
->cso
;
2301 radeon_set_context_reg(cs
, R_0288A4_SQ_PGM_START_FS
,
2302 (shader
->buffer
->gpu_address
+ shader
->offset
) >> 8);
2303 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2304 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->buffer
,
2306 RADEON_PRIO_SHADER_BINARY
));
2309 static void evergreen_emit_shader_stages(struct r600_context
*rctx
, struct r600_atom
*a
)
2311 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2312 struct r600_shader_stages_state
*state
= (struct r600_shader_stages_state
*)a
;
2314 uint32_t v
= 0, v2
= 0, primid
= 0, tf_param
= 0;
2316 if (rctx
->vs_shader
->current
->shader
.vs_as_gs_a
) {
2317 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
2321 if (state
->geom_enable
) {
2324 if (rctx
->gs_shader
->gs_max_out_vertices
<= 128)
2325 cut_val
= V_028A40_GS_CUT_128
;
2326 else if (rctx
->gs_shader
->gs_max_out_vertices
<= 256)
2327 cut_val
= V_028A40_GS_CUT_256
;
2328 else if (rctx
->gs_shader
->gs_max_out_vertices
<= 512)
2329 cut_val
= V_028A40_GS_CUT_512
;
2331 cut_val
= V_028A40_GS_CUT_1024
;
2333 v
= S_028B54_GS_EN(1) |
2334 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2335 if (!rctx
->tes_shader
)
2336 v
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
2338 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
2339 S_028A40_CUT_MODE(cut_val
);
2341 if (rctx
->gs_shader
->current
->shader
.gs_prim_id_input
)
2345 if (rctx
->tes_shader
) {
2346 uint32_t type
, partitioning
, topology
;
2347 struct tgsi_shader_info
*info
= &rctx
->tes_shader
->current
->selector
->info
;
2348 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
2349 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
2350 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
2351 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
2352 switch (tes_prim_mode
) {
2353 case PIPE_PRIM_LINES
:
2354 type
= V_028B6C_TESS_ISOLINE
;
2356 case PIPE_PRIM_TRIANGLES
:
2357 type
= V_028B6C_TESS_TRIANGLE
;
2359 case PIPE_PRIM_QUADS
:
2360 type
= V_028B6C_TESS_QUAD
;
2367 switch (tes_spacing
) {
2368 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
2369 partitioning
= V_028B6C_PART_FRAC_ODD
;
2371 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
2372 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2374 case PIPE_TESS_SPACING_EQUAL
:
2375 partitioning
= V_028B6C_PART_INTEGER
;
2383 topology
= V_028B6C_OUTPUT_POINT
;
2384 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
2385 topology
= V_028B6C_OUTPUT_LINE
;
2386 else if (tes_vertex_order_cw
)
2387 /* XXX follow radeonsi and invert */
2388 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2390 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2392 tf_param
= S_028B6C_TYPE(type
) |
2393 S_028B6C_PARTITIONING(partitioning
) |
2394 S_028B6C_TOPOLOGY(topology
);
2397 if (rctx
->tes_shader
) {
2398 v
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
2400 if (!state
->geom_enable
)
2401 v
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
2403 v
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
2406 radeon_set_context_reg(cs
, R_028AB8_VGT_VTX_CNT_EN
, v
? 1 : 0 );
2407 radeon_set_context_reg(cs
, R_028B54_VGT_SHADER_STAGES_EN
, v
);
2408 radeon_set_context_reg(cs
, R_028A40_VGT_GS_MODE
, v2
);
2409 radeon_set_context_reg(cs
, R_028A84_VGT_PRIMITIVEID_EN
, primid
);
2410 radeon_set_context_reg(cs
, R_028B6C_VGT_TF_PARAM
, tf_param
);
2413 static void evergreen_emit_gs_rings(struct r600_context
*rctx
, struct r600_atom
*a
)
2415 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2416 struct r600_gs_rings_state
*state
= (struct r600_gs_rings_state
*)a
;
2417 struct r600_resource
*rbuffer
;
2419 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2420 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2421 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
2423 if (state
->enable
) {
2424 rbuffer
=(struct r600_resource
*)state
->esgs_ring
.buffer
;
2425 radeon_set_config_reg(cs
, R_008C40_SQ_ESGS_RING_BASE
,
2426 rbuffer
->gpu_address
>> 8);
2427 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2428 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2429 RADEON_USAGE_READWRITE
,
2430 RADEON_PRIO_SHADER_RINGS
));
2431 radeon_set_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
,
2432 state
->esgs_ring
.buffer_size
>> 8);
2434 rbuffer
=(struct r600_resource
*)state
->gsvs_ring
.buffer
;
2435 radeon_set_config_reg(cs
, R_008C48_SQ_GSVS_RING_BASE
,
2436 rbuffer
->gpu_address
>> 8);
2437 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2438 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2439 RADEON_USAGE_READWRITE
,
2440 RADEON_PRIO_SHADER_RINGS
));
2441 radeon_set_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
,
2442 state
->gsvs_ring
.buffer_size
>> 8);
2444 radeon_set_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
, 0);
2445 radeon_set_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
, 0);
2448 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2449 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2450 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
2453 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
2454 enum chip_class ctx_chip_class
,
2455 enum radeon_family ctx_family
,
2458 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2459 r600_store_value(cb
, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2460 /* always set the temp clauses */
2461 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2463 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2464 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2465 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2467 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2469 r600_store_context_reg_seq(cb
, R_028350_SX_MISC
, 2);
2470 r600_store_value(cb
, 0);
2471 r600_store_value(cb
, S_028354_SURFACE_SYNC_MASK(0xf));
2473 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2476 static void cayman_init_atom_start_cs(struct r600_context
*rctx
)
2478 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2481 r600_init_command_buffer(cb
, 338);
2483 /* This must be first. */
2484 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2485 r600_store_value(cb
, 0x80000000);
2486 r600_store_value(cb
, 0x80000000);
2488 /* We're setting config registers here. */
2489 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2490 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2492 /* This enables pipeline stat & streamout queries.
2493 * They are only disabled by blits.
2495 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2496 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START
) | EVENT_INDEX(0));
2498 cayman_init_common_regs(cb
, rctx
->b
.chip_class
,
2499 rctx
->b
.family
, rctx
->screen
->b
.info
.drm_minor
);
2501 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2502 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2504 /* remove LS/HS from one SIMD for hw workaround */
2505 r600_store_config_reg_seq(cb
, R_008E20_SQ_STATIC_THREAD_MGMT1
, 3);
2506 r600_store_value(cb
, 0xffffffff);
2507 r600_store_value(cb
, 0xffffffff);
2508 r600_store_value(cb
, 0xfffffffe);
2510 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2511 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2512 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2513 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2514 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2515 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2516 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2518 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2519 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2520 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2521 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2522 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2524 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2525 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2526 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2527 r600_store_value(cb
, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2528 r600_store_value(cb
, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2529 r600_store_value(cb
, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2530 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2531 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2532 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2533 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2534 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2535 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2536 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2537 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2539 r600_store_context_reg(cb
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0);
2541 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2543 r600_store_context_reg_seq(cb
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
2544 r600_store_value(cb
, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2545 r600_store_value(cb
, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2547 r600_store_context_reg_seq(cb
, R_0288E8_SQ_LDS_ALLOC
, 2);
2548 r600_store_value(cb
, 0); /* R_0288E8_SQ_LDS_ALLOC */
2549 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2551 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2553 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2554 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2555 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2557 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2559 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2561 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2563 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2564 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2565 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2566 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2568 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2569 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2571 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2572 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2574 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2575 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2576 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2578 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2579 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2580 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2582 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2583 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2584 r600_store_context_reg(cb
, R_02887C_SQ_PGM_RESOURCES_2_GS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2585 r600_store_context_reg(cb
, R_028894_SQ_PGM_RESOURCES_2_ES
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2586 r600_store_context_reg(cb
, R_0288C0_SQ_PGM_RESOURCES_2_HS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2587 r600_store_context_reg(cb
, R_0288D8_SQ_PGM_RESOURCES_2_LS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2589 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2591 /* to avoid GPU doing any preloading of constant from random address */
2592 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2593 for (i
= 0; i
< 16; i
++)
2594 r600_store_value(cb
, 0);
2596 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2597 for (i
= 0; i
< 16; i
++)
2598 r600_store_value(cb
, 0);
2600 r600_store_context_reg_seq(cb
, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
, 16);
2601 for (i
= 0; i
< 16; i
++)
2602 r600_store_value(cb
, 0);
2604 r600_store_context_reg_seq(cb
, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
, 16);
2605 for (i
= 0; i
< 16; i
++)
2606 r600_store_value(cb
, 0);
2608 r600_store_context_reg_seq(cb
, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0
, 16);
2609 for (i
= 0; i
< 16; i
++)
2610 r600_store_value(cb
, 0);
2612 if (rctx
->screen
->b
.has_streamout
) {
2613 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2616 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
2617 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
2618 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2619 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
2620 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2621 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2623 r600_store_context_reg_seq(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 2);
2624 r600_store_value(cb
, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2625 r600_store_value(cb
, 0); /* R028B58_VGT_LS_HS_CONFIG */
2626 r600_store_context_reg(cb
, R_028B6C_VGT_TF_PARAM
, 0);
2627 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2628 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2629 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (64 * 4), 0x01000FFF);
2630 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (96 * 4), 0x01000FFF);
2631 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (128 * 4), 0x01000FFF);
2634 void evergreen_init_common_regs(struct r600_context
*rctx
, struct r600_command_buffer
*cb
,
2635 enum chip_class ctx_chip_class
,
2636 enum radeon_family ctx_family
,
2658 rctx
->default_gprs
[R600_HW_STAGE_PS
] = 93;
2659 rctx
->default_gprs
[R600_HW_STAGE_VS
] = 46;
2660 rctx
->r6xx_num_clause_temp_gprs
= 4;
2661 rctx
->default_gprs
[R600_HW_STAGE_GS
] = 31;
2662 rctx
->default_gprs
[R600_HW_STAGE_ES
] = 31;
2663 rctx
->default_gprs
[EG_HW_STAGE_HS
] = 23;
2664 rctx
->default_gprs
[EG_HW_STAGE_LS
] = 23;
2667 switch (ctx_family
) {
2675 tmp
|= S_008C00_VC_ENABLE(1);
2678 tmp
|= S_008C00_EXPORT_SRC_C(1);
2679 tmp
|= S_008C00_CS_PRIO(cs_prio
);
2680 tmp
|= S_008C00_LS_PRIO(ls_prio
);
2681 tmp
|= S_008C00_HS_PRIO(hs_prio
);
2682 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2683 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2684 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2685 tmp
|= S_008C00_ES_PRIO(es_prio
);
2687 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 1);
2688 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2690 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2691 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2692 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2694 /* The cs checker requires this register to be set. */
2695 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2697 r600_store_context_reg_seq(cb
, R_028350_SX_MISC
, 2);
2698 r600_store_value(cb
, 0);
2699 r600_store_value(cb
, S_028354_SURFACE_SYNC_MASK(0xf));
2704 void evergreen_init_atom_start_cs(struct r600_context
*rctx
)
2706 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2714 int num_ps_stack_entries
;
2715 int num_vs_stack_entries
;
2716 int num_gs_stack_entries
;
2717 int num_es_stack_entries
;
2718 int num_hs_stack_entries
;
2719 int num_ls_stack_entries
;
2720 enum radeon_family family
;
2723 if (rctx
->b
.chip_class
== CAYMAN
) {
2724 cayman_init_atom_start_cs(rctx
);
2728 r600_init_command_buffer(cb
, 338);
2730 /* This must be first. */
2731 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2732 r600_store_value(cb
, 0x80000000);
2733 r600_store_value(cb
, 0x80000000);
2735 /* We're setting config registers here. */
2736 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2737 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2739 /* This enables pipeline stat & streamout queries.
2740 * They are only disabled by blits.
2742 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2743 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START
) | EVENT_INDEX(0));
2745 evergreen_init_common_regs(rctx
, cb
, rctx
->b
.chip_class
,
2746 rctx
->b
.family
, rctx
->screen
->b
.info
.drm_minor
);
2748 family
= rctx
->b
.family
;
2752 num_ps_threads
= 96;
2753 num_vs_threads
= 16;
2754 num_gs_threads
= 16;
2755 num_es_threads
= 16;
2756 num_hs_threads
= 16;
2757 num_ls_threads
= 16;
2758 num_ps_stack_entries
= 42;
2759 num_vs_stack_entries
= 42;
2760 num_gs_stack_entries
= 42;
2761 num_es_stack_entries
= 42;
2762 num_hs_stack_entries
= 42;
2763 num_ls_stack_entries
= 42;
2766 num_ps_threads
= 128;
2767 num_vs_threads
= 20;
2768 num_gs_threads
= 20;
2769 num_es_threads
= 20;
2770 num_hs_threads
= 20;
2771 num_ls_threads
= 20;
2772 num_ps_stack_entries
= 42;
2773 num_vs_stack_entries
= 42;
2774 num_gs_stack_entries
= 42;
2775 num_es_stack_entries
= 42;
2776 num_hs_stack_entries
= 42;
2777 num_ls_stack_entries
= 42;
2780 num_ps_threads
= 128;
2781 num_vs_threads
= 20;
2782 num_gs_threads
= 20;
2783 num_es_threads
= 20;
2784 num_hs_threads
= 20;
2785 num_ls_threads
= 20;
2786 num_ps_stack_entries
= 85;
2787 num_vs_stack_entries
= 85;
2788 num_gs_stack_entries
= 85;
2789 num_es_stack_entries
= 85;
2790 num_hs_stack_entries
= 85;
2791 num_ls_stack_entries
= 85;
2795 num_ps_threads
= 128;
2796 num_vs_threads
= 20;
2797 num_gs_threads
= 20;
2798 num_es_threads
= 20;
2799 num_hs_threads
= 20;
2800 num_ls_threads
= 20;
2801 num_ps_stack_entries
= 85;
2802 num_vs_stack_entries
= 85;
2803 num_gs_stack_entries
= 85;
2804 num_es_stack_entries
= 85;
2805 num_hs_stack_entries
= 85;
2806 num_ls_stack_entries
= 85;
2809 num_ps_threads
= 96;
2810 num_vs_threads
= 16;
2811 num_gs_threads
= 16;
2812 num_es_threads
= 16;
2813 num_hs_threads
= 16;
2814 num_ls_threads
= 16;
2815 num_ps_stack_entries
= 42;
2816 num_vs_stack_entries
= 42;
2817 num_gs_stack_entries
= 42;
2818 num_es_stack_entries
= 42;
2819 num_hs_stack_entries
= 42;
2820 num_ls_stack_entries
= 42;
2823 num_ps_threads
= 96;
2824 num_vs_threads
= 25;
2825 num_gs_threads
= 25;
2826 num_es_threads
= 25;
2827 num_hs_threads
= 16;
2828 num_ls_threads
= 16;
2829 num_ps_stack_entries
= 42;
2830 num_vs_stack_entries
= 42;
2831 num_gs_stack_entries
= 42;
2832 num_es_stack_entries
= 42;
2833 num_hs_stack_entries
= 42;
2834 num_ls_stack_entries
= 42;
2837 num_ps_threads
= 96;
2838 num_vs_threads
= 25;
2839 num_gs_threads
= 25;
2840 num_es_threads
= 25;
2841 num_hs_threads
= 16;
2842 num_ls_threads
= 16;
2843 num_ps_stack_entries
= 85;
2844 num_vs_stack_entries
= 85;
2845 num_gs_stack_entries
= 85;
2846 num_es_stack_entries
= 85;
2847 num_hs_stack_entries
= 85;
2848 num_ls_stack_entries
= 85;
2851 num_ps_threads
= 128;
2852 num_vs_threads
= 20;
2853 num_gs_threads
= 20;
2854 num_es_threads
= 20;
2855 num_hs_threads
= 20;
2856 num_ls_threads
= 20;
2857 num_ps_stack_entries
= 85;
2858 num_vs_stack_entries
= 85;
2859 num_gs_stack_entries
= 85;
2860 num_es_stack_entries
= 85;
2861 num_hs_stack_entries
= 85;
2862 num_ls_stack_entries
= 85;
2865 num_ps_threads
= 128;
2866 num_vs_threads
= 20;
2867 num_gs_threads
= 20;
2868 num_es_threads
= 20;
2869 num_hs_threads
= 20;
2870 num_ls_threads
= 20;
2871 num_ps_stack_entries
= 42;
2872 num_vs_stack_entries
= 42;
2873 num_gs_stack_entries
= 42;
2874 num_es_stack_entries
= 42;
2875 num_hs_stack_entries
= 42;
2876 num_ls_stack_entries
= 42;
2879 num_ps_threads
= 96;
2880 num_vs_threads
= 10;
2881 num_gs_threads
= 10;
2882 num_es_threads
= 10;
2883 num_hs_threads
= 10;
2884 num_ls_threads
= 10;
2885 num_ps_stack_entries
= 42;
2886 num_vs_stack_entries
= 42;
2887 num_gs_stack_entries
= 42;
2888 num_es_stack_entries
= 42;
2889 num_hs_stack_entries
= 42;
2890 num_ls_stack_entries
= 42;
2894 tmp
= S_008C18_NUM_PS_THREADS(num_ps_threads
);
2895 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
2896 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
2897 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
2899 r600_store_config_reg_seq(cb
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, 5);
2900 r600_store_value(cb
, tmp
); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2902 tmp
= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
2903 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
2904 r600_store_value(cb
, tmp
); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2906 tmp
= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2907 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2908 r600_store_value(cb
, tmp
); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2910 tmp
= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2911 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2912 r600_store_value(cb
, tmp
); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2914 tmp
= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
2915 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
2916 r600_store_value(cb
, tmp
); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2918 r600_store_config_reg(cb
, R_008E2C_SQ_LDS_RESOURCE_MGMT
,
2919 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2921 /* remove LS/HS from one SIMD for hw workaround */
2922 r600_store_config_reg_seq(cb
, R_008E20_SQ_STATIC_THREAD_MGMT1
, 3);
2923 r600_store_value(cb
, 0xffffffff);
2924 r600_store_value(cb
, 0xffffffff);
2925 r600_store_value(cb
, 0xfffffffe);
2927 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2928 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2930 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2931 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2932 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2933 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2934 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2935 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2936 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2938 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2939 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2940 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2941 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2942 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2944 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2945 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2946 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2947 r600_store_value(cb
, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2948 r600_store_value(cb
, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2949 r600_store_value(cb
, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2950 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2951 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2952 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2953 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2954 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2955 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2956 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2957 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2959 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2961 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2963 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2964 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2965 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2967 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2969 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2971 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2972 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2973 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2975 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2976 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2978 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2979 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2980 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2981 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2983 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2984 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2985 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2987 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2988 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2989 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2991 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2992 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2993 r600_store_context_reg(cb
, R_02887C_SQ_PGM_RESOURCES_2_GS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2994 r600_store_context_reg(cb
, R_028894_SQ_PGM_RESOURCES_2_ES
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2995 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2996 r600_store_context_reg(cb
, R_0288C0_SQ_PGM_RESOURCES_2_HS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2997 r600_store_context_reg(cb
, R_0288D8_SQ_PGM_RESOURCES_2_LS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2999 /* to avoid GPU doing any preloading of constant from random address */
3000 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
3001 for (i
= 0; i
< 16; i
++)
3002 r600_store_value(cb
, 0);
3004 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
3005 for (i
= 0; i
< 16; i
++)
3006 r600_store_value(cb
, 0);
3008 r600_store_context_reg_seq(cb
, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
, 16);
3009 for (i
= 0; i
< 16; i
++)
3010 r600_store_value(cb
, 0);
3012 r600_store_context_reg_seq(cb
, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
, 16);
3013 for (i
= 0; i
< 16; i
++)
3014 r600_store_value(cb
, 0);
3016 r600_store_context_reg_seq(cb
, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0
, 16);
3017 for (i
= 0; i
< 16; i
++)
3018 r600_store_value(cb
, 0);
3020 r600_store_context_reg(cb
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0);
3022 if (rctx
->screen
->b
.has_streamout
) {
3023 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
3026 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
3027 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
3028 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
3029 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
3030 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3031 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3033 r600_store_context_reg_seq(cb
, R_0288E8_SQ_LDS_ALLOC
, 2);
3034 r600_store_value(cb
, 0); /* R_0288E8_SQ_LDS_ALLOC */
3035 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
3037 if (rctx
->b
.family
== CHIP_CAICOS
) {
3038 r600_store_context_reg_seq(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 2);
3039 r600_store_value(cb
, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3040 r600_store_value(cb
, 0); /* R028B58_VGT_LS_HS_CONFIG */
3041 r600_store_context_reg(cb
, R_028B6C_VGT_TF_PARAM
, 0);
3043 r600_store_context_reg_seq(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 7);
3044 r600_store_value(cb
, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3045 r600_store_value(cb
, 0); /* R028B58_VGT_LS_HS_CONFIG */
3046 r600_store_value(cb
, 0); /* R028B5C_VGT_LS_SIZE */
3047 r600_store_value(cb
, 0); /* R028B60_VGT_HS_SIZE */
3048 r600_store_value(cb
, 0); /* R028B64_VGT_LS_HS_ALLOC */
3049 r600_store_value(cb
, 0); /* R028B68_VGT_HS_PATCH_CONST */
3050 r600_store_value(cb
, 0); /* R028B68_VGT_TF_PARAM */
3053 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
3054 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
3055 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (64 * 4), 0x01000FFF);
3056 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (96 * 4), 0x01000FFF);
3057 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (128 * 4), 0x01000FFF);
3060 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3062 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3063 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3064 struct r600_shader
*rshader
= &shader
->shader
;
3065 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
= 0;
3066 int pos_index
= -1, face_index
= -1, fixed_pt_position_index
= -1;
3068 boolean have_perspective
= FALSE
, have_linear
= FALSE
;
3069 static const unsigned spi_baryc_enable_bit
[6] = {
3070 S_0286E0_PERSP_SAMPLE_ENA(1),
3071 S_0286E0_PERSP_CENTER_ENA(1),
3072 S_0286E0_PERSP_CENTROID_ENA(1),
3073 S_0286E0_LINEAR_SAMPLE_ENA(1),
3074 S_0286E0_LINEAR_CENTER_ENA(1),
3075 S_0286E0_LINEAR_CENTROID_ENA(1)
3077 unsigned spi_baryc_cntl
= 0, sid
, tmp
, num
= 0;
3078 unsigned z_export
= 0, stencil_export
= 0, mask_export
= 0;
3079 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
3080 uint32_t spi_ps_input_cntl
[32];
3083 r600_init_command_buffer(cb
, 64);
3088 for (i
= 0; i
< rshader
->ninput
; i
++) {
3089 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3090 POSITION goes via GPRs from the SC so isn't counted */
3091 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
3093 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
) {
3094 if (face_index
== -1)
3097 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
) {
3098 if (face_index
== -1)
3099 face_index
= i
; /* lives in same register, same enable bit */
3101 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_SAMPLEID
) {
3102 fixed_pt_position_index
= i
;
3106 int k
= eg_get_interpolator_index(
3107 rshader
->input
[i
].interpolate
,
3108 rshader
->input
[i
].interpolate_location
);
3110 spi_baryc_cntl
|= spi_baryc_enable_bit
[k
];
3111 have_perspective
|= k
< 3;
3112 have_linear
|= !(k
< 3);
3116 sid
= rshader
->input
[i
].spi_sid
;
3119 tmp
= S_028644_SEMANTIC(sid
);
3121 /* D3D 9 behaviour. GL is undefined */
3122 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
&& rshader
->input
[i
].sid
== 0)
3123 tmp
|= S_028644_DEFAULT_VAL(3);
3125 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
3126 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3127 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
3128 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
)) {
3129 tmp
|= S_028644_FLAT_SHADE(1);
3132 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
3133 (sprite_coord_enable
& (1 << rshader
->input
[i
].sid
))) {
3134 tmp
|= S_028644_PT_SPRITE_TEX(1);
3137 spi_ps_input_cntl
[num
++] = tmp
;
3141 r600_store_context_reg_seq(cb
, R_028644_SPI_PS_INPUT_CNTL_0
, num
);
3142 r600_store_array(cb
, num
, spi_ps_input_cntl
);
3144 for (i
= 0; i
< rshader
->noutput
; i
++) {
3145 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
3147 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
3149 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
&&
3150 rctx
->framebuffer
.nr_samples
> 1 && rctx
->ps_iter_samples
> 0)
3153 if (rshader
->uses_kill
)
3154 db_shader_control
|= S_02880C_KILL_ENABLE(1);
3156 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
3157 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export
);
3158 db_shader_control
|= S_02880C_MASK_EXPORT_ENABLE(mask_export
);
3160 switch (rshader
->ps_conservative_z
) {
3161 default: /* fall through */
3162 case TGSI_FS_DEPTH_LAYOUT_ANY
:
3163 db_shader_control
|= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z
);
3165 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
3166 db_shader_control
|= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
3168 case TGSI_FS_DEPTH_LAYOUT_LESS
:
3169 db_shader_control
|= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
3174 for (i
= 0; i
< rshader
->noutput
; i
++) {
3175 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
3176 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
||
3177 rshader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
)
3181 num_cout
= rshader
->nr_ps_color_exports
;
3183 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
3185 /* always at least export 1 component per pixel */
3188 shader
->nr_ps_color_outputs
= num_cout
;
3191 have_perspective
= TRUE
;
3193 if (!spi_baryc_cntl
)
3194 spi_baryc_cntl
|= spi_baryc_enable_bit
[0];
3196 if (!have_perspective
&& !have_linear
)
3197 have_perspective
= TRUE
;
3199 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
3200 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
3201 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
3203 if (pos_index
!= -1) {
3204 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
3205 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].interpolate_location
== TGSI_INTERPOLATE_LOC_CENTROID
) |
3206 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
3207 spi_input_z
|= S_0286D8_PROVIDE_Z_TO_SPI(1);
3210 spi_ps_in_control_1
= 0;
3211 if (face_index
!= -1) {
3212 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
3213 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
3215 if (fixed_pt_position_index
!= -1) {
3216 spi_ps_in_control_1
|= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3217 S_0286D0_FIXED_PT_POSITION_ADDR(rshader
->input
[fixed_pt_position_index
].gpr
);
3220 r600_store_context_reg_seq(cb
, R_0286CC_SPI_PS_IN_CONTROL_0
, 2);
3221 r600_store_value(cb
, spi_ps_in_control_0
); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3222 r600_store_value(cb
, spi_ps_in_control_1
); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3224 r600_store_context_reg(cb
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
3225 r600_store_context_reg(cb
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
3226 r600_store_context_reg(cb
, R_02884C_SQ_PGM_EXPORTS_PS
, exports_ps
);
3228 r600_store_context_reg_seq(cb
, R_028840_SQ_PGM_START_PS
, 2);
3229 r600_store_value(cb
, shader
->bo
->gpu_address
>> 8);
3230 r600_store_value(cb
, /* R_028844_SQ_PGM_RESOURCES_PS */
3231 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
3232 S_028844_PRIME_CACHE_ON_DRAW(1) |
3233 S_028844_STACK_SIZE(rshader
->bc
.nstack
));
3234 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3236 shader
->db_shader_control
= db_shader_control
;
3237 shader
->ps_depth_export
= z_export
| stencil_export
| mask_export
;
3239 shader
->sprite_coord_enable
= sprite_coord_enable
;
3240 if (rctx
->rasterizer
)
3241 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
3244 void evergreen_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3246 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3247 struct r600_shader
*rshader
= &shader
->shader
;
3249 r600_init_command_buffer(cb
, 32);
3251 r600_store_context_reg(cb
, R_028890_SQ_PGM_RESOURCES_ES
,
3252 S_028890_NUM_GPRS(rshader
->bc
.ngpr
) |
3253 S_028890_STACK_SIZE(rshader
->bc
.nstack
));
3254 r600_store_context_reg(cb
, R_02888C_SQ_PGM_START_ES
,
3255 shader
->bo
->gpu_address
>> 8);
3256 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3259 void evergreen_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3261 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3262 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3263 struct r600_shader
*rshader
= &shader
->shader
;
3264 struct r600_shader
*cp_shader
= &shader
->gs_copy_shader
->shader
;
3265 unsigned gsvs_itemsizes
[4] = {
3266 (cp_shader
->ring_item_sizes
[0] * shader
->selector
->gs_max_out_vertices
) >> 2,
3267 (cp_shader
->ring_item_sizes
[1] * shader
->selector
->gs_max_out_vertices
) >> 2,
3268 (cp_shader
->ring_item_sizes
[2] * shader
->selector
->gs_max_out_vertices
) >> 2,
3269 (cp_shader
->ring_item_sizes
[3] * shader
->selector
->gs_max_out_vertices
) >> 2
3272 r600_init_command_buffer(cb
, 64);
3274 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3277 r600_store_context_reg(cb
, R_028B38_VGT_GS_MAX_VERT_OUT
,
3278 S_028B38_MAX_VERT_OUT(shader
->selector
->gs_max_out_vertices
));
3279 r600_store_context_reg(cb
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
3280 r600_conv_prim_to_gs_out(shader
->selector
->gs_output_prim
));
3282 if (rctx
->screen
->b
.info
.drm_minor
>= 35) {
3283 r600_store_context_reg(cb
, R_028B90_VGT_GS_INSTANCE_CNT
,
3284 S_028B90_CNT(MIN2(shader
->selector
->gs_num_invocations
, 127)) |
3285 S_028B90_ENABLE(shader
->selector
->gs_num_invocations
> 0));
3287 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
3288 r600_store_value(cb
, cp_shader
->ring_item_sizes
[0] >> 2);
3289 r600_store_value(cb
, cp_shader
->ring_item_sizes
[1] >> 2);
3290 r600_store_value(cb
, cp_shader
->ring_item_sizes
[2] >> 2);
3291 r600_store_value(cb
, cp_shader
->ring_item_sizes
[3] >> 2);
3293 r600_store_context_reg(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
,
3294 (rshader
->ring_item_sizes
[0]) >> 2);
3296 r600_store_context_reg(cb
, R_028904_SQ_GSVS_RING_ITEMSIZE
,
3302 r600_store_context_reg_seq(cb
, R_02892C_SQ_GSVS_RING_OFFSET_1
, 3);
3303 r600_store_value(cb
, gsvs_itemsizes
[0]);
3304 r600_store_value(cb
, gsvs_itemsizes
[0] + gsvs_itemsizes
[1]);
3305 r600_store_value(cb
, gsvs_itemsizes
[0] + gsvs_itemsizes
[1] + gsvs_itemsizes
[2]);
3307 /* FIXME calculate these values somehow ??? */
3308 r600_store_context_reg_seq(cb
, R_028A54_GS_PER_ES
, 3);
3309 r600_store_value(cb
, 0x80); /* GS_PER_ES */
3310 r600_store_value(cb
, 0x100); /* ES_PER_GS */
3311 r600_store_value(cb
, 0x2); /* GS_PER_VS */
3313 r600_store_context_reg(cb
, R_028878_SQ_PGM_RESOURCES_GS
,
3314 S_028878_NUM_GPRS(rshader
->bc
.ngpr
) |
3315 S_028878_STACK_SIZE(rshader
->bc
.nstack
));
3316 r600_store_context_reg(cb
, R_028874_SQ_PGM_START_GS
,
3317 shader
->bo
->gpu_address
>> 8);
3318 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3322 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3324 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3325 struct r600_shader
*rshader
= &shader
->shader
;
3326 unsigned spi_vs_out_id
[10] = {};
3327 unsigned i
, tmp
, nparams
= 0;
3329 for (i
= 0; i
< rshader
->noutput
; i
++) {
3330 if (rshader
->output
[i
].spi_sid
) {
3331 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
3332 spi_vs_out_id
[nparams
/ 4] |= tmp
;
3337 r600_init_command_buffer(cb
, 32);
3339 r600_store_context_reg_seq(cb
, R_02861C_SPI_VS_OUT_ID_0
, 10);
3340 for (i
= 0; i
< 10; i
++) {
3341 r600_store_value(cb
, spi_vs_out_id
[i
]);
3344 /* Certain attributes (position, psize, etc.) don't count as params.
3345 * VS is required to export at least one param and r600_shader_from_tgsi()
3346 * takes care of adding a dummy export.
3351 r600_store_context_reg(cb
, R_0286C4_SPI_VS_OUT_CONFIG
,
3352 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
3353 r600_store_context_reg(cb
, R_028860_SQ_PGM_RESOURCES_VS
,
3354 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
3355 S_028860_STACK_SIZE(rshader
->bc
.nstack
));
3356 if (rshader
->vs_position_window_space
) {
3357 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
3358 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3360 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
3361 S_028818_VTX_W0_FMT(1) |
3362 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3363 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3364 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3367 r600_store_context_reg(cb
, R_02885C_SQ_PGM_START_VS
,
3368 shader
->bo
->gpu_address
>> 8);
3369 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3371 shader
->pa_cl_vs_out_cntl
=
3372 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
3373 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
3374 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
3375 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
) |
3376 S_02881C_USE_VTX_EDGE_FLAG(rshader
->vs_out_edgeflag
) |
3377 S_02881C_USE_VTX_VIEWPORT_INDX(rshader
->vs_out_viewport
) |
3378 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader
->vs_out_layer
);
3381 void evergreen_update_hs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3383 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3384 struct r600_shader
*rshader
= &shader
->shader
;
3386 r600_init_command_buffer(cb
, 32);
3387 r600_store_context_reg(cb
, R_0288BC_SQ_PGM_RESOURCES_HS
,
3388 S_0288BC_NUM_GPRS(rshader
->bc
.ngpr
) |
3389 S_0288BC_STACK_SIZE(rshader
->bc
.nstack
));
3390 r600_store_context_reg(cb
, R_0288B8_SQ_PGM_START_HS
,
3391 shader
->bo
->gpu_address
>> 8);
3394 void evergreen_update_ls_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3396 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3397 struct r600_shader
*rshader
= &shader
->shader
;
3399 r600_init_command_buffer(cb
, 32);
3400 r600_store_context_reg(cb
, R_0288D4_SQ_PGM_RESOURCES_LS
,
3401 S_0288D4_NUM_GPRS(rshader
->bc
.ngpr
) |
3402 S_0288D4_STACK_SIZE(rshader
->bc
.nstack
));
3403 r600_store_context_reg(cb
, R_0288D0_SQ_PGM_START_LS
,
3404 shader
->bo
->gpu_address
>> 8);
3406 void *evergreen_create_resolve_blend(struct r600_context
*rctx
)
3408 struct pipe_blend_state blend
;
3410 memset(&blend
, 0, sizeof(blend
));
3411 blend
.independent_blend_enable
= true;
3412 blend
.rt
[0].colormask
= 0xf;
3413 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_CB_RESOLVE
);
3416 void *evergreen_create_decompress_blend(struct r600_context
*rctx
)
3418 struct pipe_blend_state blend
;
3419 unsigned mode
= rctx
->screen
->has_compressed_msaa_texturing
?
3420 V_028808_CB_FMASK_DECOMPRESS
: V_028808_CB_DECOMPRESS
;
3422 memset(&blend
, 0, sizeof(blend
));
3423 blend
.independent_blend_enable
= true;
3424 blend
.rt
[0].colormask
= 0xf;
3425 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3428 void *evergreen_create_fastclear_blend(struct r600_context
*rctx
)
3430 struct pipe_blend_state blend
;
3431 unsigned mode
= V_028808_CB_ELIMINATE_FAST_CLEAR
;
3433 memset(&blend
, 0, sizeof(blend
));
3434 blend
.independent_blend_enable
= true;
3435 blend
.rt
[0].colormask
= 0xf;
3436 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3439 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
)
3441 struct pipe_depth_stencil_alpha_state dsa
= {{0}};
3443 return rctx
->b
.b
.create_depth_stencil_alpha_state(&rctx
->b
.b
, &dsa
);
3446 void evergreen_update_db_shader_control(struct r600_context
* rctx
)
3449 unsigned db_shader_control
;
3451 if (!rctx
->ps_shader
) {
3455 dual_export
= rctx
->framebuffer
.export_16bpc
&&
3456 !rctx
->ps_shader
->current
->ps_depth_export
;
3458 db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
3459 S_02880C_DUAL_EXPORT_ENABLE(dual_export
) |
3460 S_02880C_DB_SOURCE_FORMAT(dual_export
? V_02880C_EXPORT_DB_TWO
:
3461 V_02880C_EXPORT_DB_FULL
) |
3462 S_02880C_ALPHA_TO_MASK_DISABLE(rctx
->framebuffer
.cb0_is_integer
);
3464 /* When alpha test is enabled we can't trust the hw to make the proper
3465 * decision on the order in which ztest should be run related to fragment
3468 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3469 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3470 * execution and thus after alpha test so if discarded by the alpha test
3471 * the z value is not written.
3472 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3473 * get a hang unless you flush the DB in between. For now just use
3476 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
3477 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
3479 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
3482 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
) {
3483 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
3484 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
3488 static void evergreen_dma_copy_tile(struct r600_context
*rctx
,
3489 struct pipe_resource
*dst
,
3494 struct pipe_resource
*src
,
3499 unsigned copy_height
,
3503 struct radeon_winsys_cs
*cs
= rctx
->b
.dma
.cs
;
3504 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3505 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3506 unsigned array_mode
, lbpp
, pitch_tile_max
, slice_tile_max
, size
;
3507 unsigned ncopy
, height
, cheight
, detile
, i
, x
, y
, z
, src_mode
, dst_mode
;
3508 unsigned sub_cmd
, bank_h
, bank_w
, mt_aspect
, nbanks
, tile_split
, non_disp_tiling
= 0;
3509 uint64_t base
, addr
;
3511 dst_mode
= rdst
->surface
.u
.legacy
.level
[dst_level
].mode
;
3512 src_mode
= rsrc
->surface
.u
.legacy
.level
[src_level
].mode
;
3513 assert(dst_mode
!= src_mode
);
3515 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3516 if (util_format_has_depth(util_format_description(src
->format
)))
3517 non_disp_tiling
= 1;
3520 sub_cmd
= EG_DMA_COPY_TILED
;
3521 lbpp
= util_logbase2(bpp
);
3522 pitch_tile_max
= ((pitch
/ bpp
) / 8) - 1;
3523 nbanks
= eg_num_banks(rctx
->screen
->b
.info
.r600_num_banks
);
3525 if (dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
) {
3527 array_mode
= evergreen_array_mode(src_mode
);
3528 slice_tile_max
= (rsrc
->surface
.u
.legacy
.level
[src_level
].nblk_x
* rsrc
->surface
.u
.legacy
.level
[src_level
].nblk_y
) / (8*8);
3529 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3530 /* linear height must be the same as the slice tile max height, it's ok even
3531 * if the linear destination/source have smaller heigh as the size of the
3532 * dma packet will be using the copy_height which is always smaller or equal
3533 * to the linear height
3535 height
= u_minify(rsrc
->resource
.b
.b
.height0
, src_level
);
3540 base
= rsrc
->surface
.u
.legacy
.level
[src_level
].offset
;
3541 addr
= rdst
->surface
.u
.legacy
.level
[dst_level
].offset
;
3542 addr
+= rdst
->surface
.u
.legacy
.level
[dst_level
].slice_size
* dst_z
;
3543 addr
+= dst_y
* pitch
+ dst_x
* bpp
;
3544 bank_h
= eg_bank_wh(rsrc
->surface
.u
.legacy
.bankh
);
3545 bank_w
= eg_bank_wh(rsrc
->surface
.u
.legacy
.bankw
);
3546 mt_aspect
= eg_macro_tile_aspect(rsrc
->surface
.u
.legacy
.mtilea
);
3547 tile_split
= eg_tile_split(rsrc
->surface
.u
.legacy
.tile_split
);
3548 base
+= rsrc
->resource
.gpu_address
;
3549 addr
+= rdst
->resource
.gpu_address
;
3552 array_mode
= evergreen_array_mode(dst_mode
);
3553 slice_tile_max
= (rdst
->surface
.u
.legacy
.level
[dst_level
].nblk_x
* rdst
->surface
.u
.legacy
.level
[dst_level
].nblk_y
) / (8*8);
3554 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3555 /* linear height must be the same as the slice tile max height, it's ok even
3556 * if the linear destination/source have smaller heigh as the size of the
3557 * dma packet will be using the copy_height which is always smaller or equal
3558 * to the linear height
3560 height
= u_minify(rdst
->resource
.b
.b
.height0
, dst_level
);
3565 base
= rdst
->surface
.u
.legacy
.level
[dst_level
].offset
;
3566 addr
= rsrc
->surface
.u
.legacy
.level
[src_level
].offset
;
3567 addr
+= rsrc
->surface
.u
.legacy
.level
[src_level
].slice_size
* src_z
;
3568 addr
+= src_y
* pitch
+ src_x
* bpp
;
3569 bank_h
= eg_bank_wh(rdst
->surface
.u
.legacy
.bankh
);
3570 bank_w
= eg_bank_wh(rdst
->surface
.u
.legacy
.bankw
);
3571 mt_aspect
= eg_macro_tile_aspect(rdst
->surface
.u
.legacy
.mtilea
);
3572 tile_split
= eg_tile_split(rdst
->surface
.u
.legacy
.tile_split
);
3573 base
+= rdst
->resource
.gpu_address
;
3574 addr
+= rsrc
->resource
.gpu_address
;
3577 size
= (copy_height
* pitch
) / 4;
3578 ncopy
= (size
/ EG_DMA_COPY_MAX_SIZE
) + !!(size
% EG_DMA_COPY_MAX_SIZE
);
3579 r600_need_dma_space(&rctx
->b
, ncopy
* 9, &rdst
->resource
, &rsrc
->resource
);
3581 for (i
= 0; i
< ncopy
; i
++) {
3582 cheight
= copy_height
;
3583 if (((cheight
* pitch
) / 4) > EG_DMA_COPY_MAX_SIZE
) {
3584 cheight
= (EG_DMA_COPY_MAX_SIZE
* 4) / pitch
;
3586 size
= (cheight
* pitch
) / 4;
3587 /* emit reloc before writing cs so that cs is always in consistent state */
3588 radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.dma
, &rsrc
->resource
,
3589 RADEON_USAGE_READ
, RADEON_PRIO_SDMA_TEXTURE
);
3590 radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.dma
, &rdst
->resource
,
3591 RADEON_USAGE_WRITE
, RADEON_PRIO_SDMA_TEXTURE
);
3592 radeon_emit(cs
, DMA_PACKET(DMA_PACKET_COPY
, sub_cmd
, size
));
3593 radeon_emit(cs
, base
>> 8);
3594 radeon_emit(cs
, (detile
<< 31) | (array_mode
<< 27) |
3595 (lbpp
<< 24) | (bank_h
<< 21) |
3596 (bank_w
<< 18) | (mt_aspect
<< 16));
3597 radeon_emit(cs
, (pitch_tile_max
<< 0) | ((height
- 1) << 16));
3598 radeon_emit(cs
, (slice_tile_max
<< 0));
3599 radeon_emit(cs
, (x
<< 0) | (z
<< 18));
3600 radeon_emit(cs
, (y
<< 0) | (tile_split
<< 21) | (nbanks
<< 25) | (non_disp_tiling
<< 28));
3601 radeon_emit(cs
, addr
& 0xfffffffc);
3602 radeon_emit(cs
, (addr
>> 32UL) & 0xff);
3603 copy_height
-= cheight
;
3604 addr
+= cheight
* pitch
;
3609 static void evergreen_dma_copy(struct pipe_context
*ctx
,
3610 struct pipe_resource
*dst
,
3612 unsigned dstx
, unsigned dsty
, unsigned dstz
,
3613 struct pipe_resource
*src
,
3615 const struct pipe_box
*src_box
)
3617 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3618 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3619 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3620 unsigned dst_pitch
, src_pitch
, bpp
, dst_mode
, src_mode
, copy_height
;
3621 unsigned src_w
, dst_w
;
3622 unsigned src_x
, src_y
;
3623 unsigned dst_x
= dstx
, dst_y
= dsty
, dst_z
= dstz
;
3625 if (rctx
->b
.dma
.cs
== NULL
) {
3629 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
3630 evergreen_dma_copy_buffer(rctx
, dst
, src
, dst_x
, src_box
->x
, src_box
->width
);
3634 if (src_box
->depth
> 1 ||
3635 !r600_prepare_for_dma_blit(&rctx
->b
, rdst
, dst_level
, dstx
, dsty
,
3636 dstz
, rsrc
, src_level
, src_box
))
3639 src_x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
3640 dst_x
= util_format_get_nblocksx(src
->format
, dst_x
);
3641 src_y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
3642 dst_y
= util_format_get_nblocksy(src
->format
, dst_y
);
3644 bpp
= rdst
->surface
.bpe
;
3645 dst_pitch
= rdst
->surface
.u
.legacy
.level
[dst_level
].nblk_x
* rdst
->surface
.bpe
;
3646 src_pitch
= rsrc
->surface
.u
.legacy
.level
[src_level
].nblk_x
* rsrc
->surface
.bpe
;
3647 src_w
= u_minify(rsrc
->resource
.b
.b
.width0
, src_level
);
3648 dst_w
= u_minify(rdst
->resource
.b
.b
.width0
, dst_level
);
3649 copy_height
= src_box
->height
/ rsrc
->surface
.blk_h
;
3651 dst_mode
= rdst
->surface
.u
.legacy
.level
[dst_level
].mode
;
3652 src_mode
= rsrc
->surface
.u
.legacy
.level
[src_level
].mode
;
3654 if (src_pitch
!= dst_pitch
|| src_box
->x
|| dst_x
|| src_w
!= dst_w
) {
3655 /* FIXME evergreen can do partial blit */
3658 /* the x test here are currently useless (because we don't support partial blit)
3659 * but keep them around so we don't forget about those
3661 if (src_pitch
% 8 || src_box
->x
% 8 || dst_x
% 8 || src_box
->y
% 8 || dst_y
% 8) {
3665 /* 128 bpp surfaces require non_disp_tiling for both
3666 * tiled and linear buffers on cayman. However, async
3667 * DMA only supports it on the tiled side. As such
3668 * the tile order is backwards after a L2T/T2L packet.
3670 if ((rctx
->b
.chip_class
== CAYMAN
) &&
3671 (src_mode
!= dst_mode
) &&
3672 (util_format_get_blocksize(src
->format
) >= 16)) {
3676 if (src_mode
== dst_mode
) {
3677 uint64_t dst_offset
, src_offset
;
3678 /* simple dma blit would do NOTE code here assume :
3681 * dst_pitch == src_pitch
3683 src_offset
= rsrc
->surface
.u
.legacy
.level
[src_level
].offset
;
3684 src_offset
+= rsrc
->surface
.u
.legacy
.level
[src_level
].slice_size
* src_box
->z
;
3685 src_offset
+= src_y
* src_pitch
+ src_x
* bpp
;
3686 dst_offset
= rdst
->surface
.u
.legacy
.level
[dst_level
].offset
;
3687 dst_offset
+= rdst
->surface
.u
.legacy
.level
[dst_level
].slice_size
* dst_z
;
3688 dst_offset
+= dst_y
* dst_pitch
+ dst_x
* bpp
;
3689 evergreen_dma_copy_buffer(rctx
, dst
, src
, dst_offset
, src_offset
,
3690 src_box
->height
* src_pitch
);
3692 evergreen_dma_copy_tile(rctx
, dst
, dst_level
, dst_x
, dst_y
, dst_z
,
3693 src
, src_level
, src_x
, src_y
, src_box
->z
,
3694 copy_height
, dst_pitch
, bpp
);
3699 r600_resource_copy_region(ctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
3700 src
, src_level
, src_box
);
3703 static void evergreen_set_tess_state(struct pipe_context
*ctx
,
3704 const float default_outer_level
[4],
3705 const float default_inner_level
[2])
3707 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3709 memcpy(rctx
->tess_state
, default_outer_level
, sizeof(float) * 4);
3710 memcpy(rctx
->tess_state
+4, default_inner_level
, sizeof(float) * 2);
3711 rctx
->tess_state_dirty
= true;
3714 void evergreen_init_state_functions(struct r600_context
*rctx
)
3719 * To avoid GPU lockup registers must be emitted in a specific order
3720 * (no kidding ...). The order below is important and have been
3721 * partially inferred from analyzing fglrx command stream.
3723 * Don't reorder atom without carefully checking the effect (GPU lockup
3724 * or piglit regression).
3727 if (rctx
->b
.chip_class
== EVERGREEN
) {
3728 r600_init_atom(rctx
, &rctx
->config_state
.atom
, id
++, evergreen_emit_config_state
, 11);
3729 rctx
->config_state
.dyn_gpr_enabled
= true;
3731 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, evergreen_emit_framebuffer_state
, 0);
3733 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, evergreen_emit_vs_constant_buffers
, 0);
3734 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, evergreen_emit_gs_constant_buffers
, 0);
3735 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, evergreen_emit_ps_constant_buffers
, 0);
3736 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_TESS_CTRL
].atom
, id
++, evergreen_emit_tcs_constant_buffers
, 0);
3737 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_TESS_EVAL
].atom
, id
++, evergreen_emit_tes_constant_buffers
, 0);
3738 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_COMPUTE
].atom
, id
++, evergreen_emit_cs_constant_buffers
, 0);
3739 /* shader program */
3740 r600_init_atom(rctx
, &rctx
->cs_shader_state
.atom
, id
++, evergreen_emit_cs_shader
, 0);
3742 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, evergreen_emit_vs_sampler_states
, 0);
3743 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, evergreen_emit_gs_sampler_states
, 0);
3744 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_CTRL
].states
.atom
, id
++, evergreen_emit_tcs_sampler_states
, 0);
3745 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_EVAL
].states
.atom
, id
++, evergreen_emit_tes_sampler_states
, 0);
3746 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, evergreen_emit_ps_sampler_states
, 0);
3747 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
].states
.atom
, id
++, evergreen_emit_cs_sampler_states
, 0);
3749 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, evergreen_fs_emit_vertex_buffers
, 0);
3750 r600_init_atom(rctx
, &rctx
->cs_vertex_buffer_state
.atom
, id
++, evergreen_cs_emit_vertex_buffers
, 0);
3751 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, evergreen_emit_vs_sampler_views
, 0);
3752 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, evergreen_emit_gs_sampler_views
, 0);
3753 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_CTRL
].views
.atom
, id
++, evergreen_emit_tcs_sampler_views
, 0);
3754 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_EVAL
].views
.atom
, id
++, evergreen_emit_tes_sampler_views
, 0);
3755 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, evergreen_emit_ps_sampler_views
, 0);
3756 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
].views
.atom
, id
++, evergreen_emit_cs_sampler_views
, 0);
3758 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 10);
3760 if (rctx
->b
.chip_class
== EVERGREEN
) {
3761 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, evergreen_emit_sample_mask
, 3);
3763 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, cayman_emit_sample_mask
, 4);
3765 rctx
->sample_mask
.sample_mask
= ~0;
3767 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
3768 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
3769 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
3770 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, evergreen_emit_cb_misc_state
, 4);
3771 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 9);
3772 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, evergreen_emit_clip_state
, 26);
3773 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, evergreen_emit_db_misc_state
, 10);
3774 r600_init_atom(rctx
, &rctx
->db_state
.atom
, id
++, evergreen_emit_db_state
, 14);
3775 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
3776 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, evergreen_emit_polygon_offset
, 9);
3777 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
3778 r600_add_atom(rctx
, &rctx
->b
.scissors
.atom
, id
++);
3779 r600_add_atom(rctx
, &rctx
->b
.viewports
.atom
, id
++);
3780 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
3781 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, evergreen_emit_vertex_fetch_shader
, 5);
3782 r600_add_atom(rctx
, &rctx
->b
.render_cond_atom
, id
++);
3783 r600_add_atom(rctx
, &rctx
->b
.streamout
.begin_atom
, id
++);
3784 r600_add_atom(rctx
, &rctx
->b
.streamout
.enable_atom
, id
++);
3785 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++)
3786 r600_init_atom(rctx
, &rctx
->hw_shader_stages
[i
].atom
, id
++, r600_emit_shader
, 0);
3787 r600_init_atom(rctx
, &rctx
->shader_stages
.atom
, id
++, evergreen_emit_shader_stages
, 15);
3788 r600_init_atom(rctx
, &rctx
->gs_rings
.atom
, id
++, evergreen_emit_gs_rings
, 26);
3790 rctx
->b
.b
.create_blend_state
= evergreen_create_blend_state
;
3791 rctx
->b
.b
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
3792 rctx
->b
.b
.create_rasterizer_state
= evergreen_create_rs_state
;
3793 rctx
->b
.b
.create_sampler_state
= evergreen_create_sampler_state
;
3794 rctx
->b
.b
.create_sampler_view
= evergreen_create_sampler_view
;
3795 rctx
->b
.b
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
3796 rctx
->b
.b
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
3797 rctx
->b
.b
.set_min_samples
= evergreen_set_min_samples
;
3798 rctx
->b
.b
.set_tess_state
= evergreen_set_tess_state
;
3799 if (rctx
->b
.chip_class
== EVERGREEN
)
3800 rctx
->b
.b
.get_sample_position
= evergreen_get_sample_position
;
3802 rctx
->b
.b
.get_sample_position
= cayman_get_sample_position
;
3803 rctx
->b
.dma_copy
= evergreen_dma_copy
;
3805 evergreen_init_compute_state_functions(rctx
);
3809 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
3811 * The information about LDS and other non-compile-time parameters is then
3812 * written to the const buffer.
3814 * const buffer contains -
3815 * uint32_t input_patch_size
3816 * uint32_t input_vertex_size
3817 * uint32_t num_tcs_input_cp
3818 * uint32_t num_tcs_output_cp;
3819 * uint32_t output_patch_size
3820 * uint32_t output_vertex_size
3821 * uint32_t output_patch0_offset
3822 * uint32_t perpatch_output_offset
3823 * and the same constbuf is bound to LS/HS/VS(ES).
3825 void evergreen_setup_tess_constants(struct r600_context
*rctx
, const struct pipe_draw_info
*info
, unsigned *num_patches
)
3827 struct pipe_constant_buffer constbuf
= {0};
3828 struct r600_pipe_shader_selector
*tcs
= rctx
->tcs_shader
? rctx
->tcs_shader
: rctx
->tes_shader
;
3829 struct r600_pipe_shader_selector
*ls
= rctx
->vs_shader
;
3830 unsigned num_tcs_input_cp
= info
->vertices_per_patch
;
3831 unsigned num_tcs_outputs
;
3832 unsigned num_tcs_output_cp
;
3833 unsigned num_tcs_patch_outputs
;
3834 unsigned num_tcs_inputs
;
3835 unsigned input_vertex_size
, output_vertex_size
;
3836 unsigned input_patch_size
, pervertex_output_patch_size
, output_patch_size
;
3837 unsigned output_patch0_offset
, perpatch_output_offset
, lds_size
;
3838 uint32_t values
[16];
3840 unsigned num_pipes
= rctx
->screen
->b
.info
.r600_max_quad_pipes
;
3841 unsigned wave_divisor
= (16 * num_pipes
);
3845 if (!rctx
->tes_shader
) {
3846 rctx
->lds_alloc
= 0;
3847 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
3848 R600_LDS_INFO_CONST_BUFFER
, NULL
);
3849 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_CTRL
,
3850 R600_LDS_INFO_CONST_BUFFER
, NULL
);
3851 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
3852 R600_LDS_INFO_CONST_BUFFER
, NULL
);
3856 if (rctx
->lds_alloc
!= 0 &&
3857 rctx
->last_ls
== ls
&&
3858 !rctx
->tess_state_dirty
&&
3859 rctx
->last_num_tcs_input_cp
== num_tcs_input_cp
&&
3860 rctx
->last_tcs
== tcs
)
3863 num_tcs_inputs
= util_last_bit64(ls
->lds_outputs_written_mask
);
3865 if (rctx
->tcs_shader
) {
3866 num_tcs_outputs
= util_last_bit64(tcs
->lds_outputs_written_mask
);
3867 num_tcs_output_cp
= tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
3868 num_tcs_patch_outputs
= util_last_bit64(tcs
->lds_patch_outputs_written_mask
);
3870 num_tcs_outputs
= num_tcs_inputs
;
3871 num_tcs_output_cp
= num_tcs_input_cp
;
3872 num_tcs_patch_outputs
= 2; /* TESSINNER + TESSOUTER */
3876 input_vertex_size
= num_tcs_inputs
* 16;
3877 output_vertex_size
= num_tcs_outputs
* 16;
3879 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
3881 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
3882 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3884 output_patch0_offset
= rctx
->tcs_shader
? input_patch_size
* *num_patches
: 0;
3885 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
3887 lds_size
= output_patch0_offset
+ output_patch_size
* *num_patches
;
3889 values
[0] = input_patch_size
;
3890 values
[1] = input_vertex_size
;
3891 values
[2] = num_tcs_input_cp
;
3892 values
[3] = num_tcs_output_cp
;
3894 values
[4] = output_patch_size
;
3895 values
[5] = output_vertex_size
;
3896 values
[6] = output_patch0_offset
;
3897 values
[7] = perpatch_output_offset
;
3899 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
3900 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
3901 num_waves
= ceilf((float)(*num_patches
* num_tcs_output_cp
) / (float)wave_divisor
);
3903 rctx
->lds_alloc
= (lds_size
| (num_waves
<< 14));
3905 memcpy(&values
[8], rctx
->tess_state
, 6 * sizeof(float));
3909 rctx
->tess_state_dirty
= false;
3911 rctx
->last_tcs
= tcs
;
3912 rctx
->last_num_tcs_input_cp
= num_tcs_input_cp
;
3914 constbuf
.user_buffer
= values
;
3915 constbuf
.buffer_size
= 16 * 4;
3917 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
3918 R600_LDS_INFO_CONST_BUFFER
, &constbuf
);
3919 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_CTRL
,
3920 R600_LDS_INFO_CONST_BUFFER
, &constbuf
);
3921 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
3922 R600_LDS_INFO_CONST_BUFFER
, &constbuf
);
3923 pipe_resource_reference(&constbuf
.buffer
, NULL
);
3926 uint32_t evergreen_get_ls_hs_config(struct r600_context
*rctx
,
3927 const struct pipe_draw_info
*info
,
3928 unsigned num_patches
)
3930 unsigned num_output_cp
;
3932 if (!rctx
->tes_shader
)
3935 num_output_cp
= rctx
->tcs_shader
?
3936 rctx
->tcs_shader
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] :
3937 info
->vertices_per_patch
;
3939 return S_028B58_NUM_PATCHES(num_patches
) |
3940 S_028B58_HS_NUM_INPUT_CP(info
->vertices_per_patch
) |
3941 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp
);
3944 void evergreen_set_ls_hs_config(struct r600_context
*rctx
,
3945 struct radeon_winsys_cs
*cs
,
3946 uint32_t ls_hs_config
)
3948 radeon_set_context_reg(cs
, R_028B58_VGT_LS_HS_CONFIG
, ls_hs_config
);
3951 void evergreen_set_lds_alloc(struct r600_context
*rctx
,
3952 struct radeon_winsys_cs
*cs
,
3955 radeon_set_context_reg(cs
, R_0288E8_SQ_LDS_ALLOC
, lds_alloc
);
3958 /* on evergreen if you are running tessellation you need to disable dynamic
3959 GPRs to workaround a hardware bug.*/
3960 bool evergreen_adjust_gprs(struct r600_context
*rctx
)
3962 unsigned num_gprs
[EG_NUM_HW_STAGES
];
3963 unsigned def_gprs
[EG_NUM_HW_STAGES
];
3964 unsigned cur_gprs
[EG_NUM_HW_STAGES
];
3965 unsigned new_gprs
[EG_NUM_HW_STAGES
];
3966 unsigned def_num_clause_temp_gprs
= rctx
->r6xx_num_clause_temp_gprs
;
3969 unsigned total_gprs
;
3971 bool rework
= false, set_default
= false, set_dirty
= false;
3973 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
3974 def_gprs
[i
] = rctx
->default_gprs
[i
];
3975 max_gprs
+= def_gprs
[i
];
3977 max_gprs
+= def_num_clause_temp_gprs
* 2;
3979 /* if we have no TESS and dyn gpr is enabled then do nothing. */
3980 if (!rctx
->hw_shader_stages
[EG_HW_STAGE_HS
].shader
) {
3981 if (rctx
->config_state
.dyn_gpr_enabled
)
3984 /* transition back to dyn gpr enabled state */
3985 rctx
->config_state
.dyn_gpr_enabled
= true;
3986 r600_mark_atom_dirty(rctx
, &rctx
->config_state
.atom
);
3987 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
3992 /* gather required shader gprs */
3993 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
3994 if (rctx
->hw_shader_stages
[i
].shader
)
3995 num_gprs
[i
] = rctx
->hw_shader_stages
[i
].shader
->shader
.bc
.ngpr
;
4000 cur_gprs
[R600_HW_STAGE_PS
] = G_008C04_NUM_PS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
4001 cur_gprs
[R600_HW_STAGE_VS
] = G_008C04_NUM_VS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
4002 cur_gprs
[R600_HW_STAGE_GS
] = G_008C08_NUM_GS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_2
);
4003 cur_gprs
[R600_HW_STAGE_ES
] = G_008C08_NUM_ES_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_2
);
4004 cur_gprs
[EG_HW_STAGE_LS
] = G_008C0C_NUM_LS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_3
);
4005 cur_gprs
[EG_HW_STAGE_HS
] = G_008C0C_NUM_HS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_3
);
4008 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4009 new_gprs
[i
] = num_gprs
[i
];
4010 total_gprs
+= num_gprs
[i
];
4013 if (total_gprs
> (max_gprs
- (2 * def_num_clause_temp_gprs
)))
4016 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4017 if (new_gprs
[i
] > cur_gprs
[i
]) {
4023 if (rctx
->config_state
.dyn_gpr_enabled
) {
4025 rctx
->config_state
.dyn_gpr_enabled
= false;
4030 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4031 if (new_gprs
[i
] > def_gprs
[i
])
4032 set_default
= false;
4036 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4037 new_gprs
[i
] = def_gprs
[i
];
4040 unsigned ps_value
= max_gprs
;
4042 ps_value
-= (def_num_clause_temp_gprs
* 2);
4043 for (i
= R600_HW_STAGE_VS
; i
< EG_NUM_HW_STAGES
; i
++)
4044 ps_value
-= new_gprs
[i
];
4046 new_gprs
[R600_HW_STAGE_PS
] = ps_value
;
4049 tmp
[0] = S_008C04_NUM_PS_GPRS(new_gprs
[R600_HW_STAGE_PS
]) |
4050 S_008C04_NUM_VS_GPRS(new_gprs
[R600_HW_STAGE_VS
]) |
4051 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs
);
4053 tmp
[1] = S_008C08_NUM_ES_GPRS(new_gprs
[R600_HW_STAGE_ES
]) |
4054 S_008C08_NUM_GS_GPRS(new_gprs
[R600_HW_STAGE_GS
]);
4056 tmp
[2] = S_008C0C_NUM_HS_GPRS(new_gprs
[EG_HW_STAGE_HS
]) |
4057 S_008C0C_NUM_LS_GPRS(new_gprs
[EG_HW_STAGE_LS
]);
4059 if (rctx
->config_state
.sq_gpr_resource_mgmt_1
!= tmp
[0] ||
4060 rctx
->config_state
.sq_gpr_resource_mgmt_2
!= tmp
[1] ||
4061 rctx
->config_state
.sq_gpr_resource_mgmt_3
!= tmp
[2]) {
4062 rctx
->config_state
.sq_gpr_resource_mgmt_1
= tmp
[0];
4063 rctx
->config_state
.sq_gpr_resource_mgmt_2
= tmp
[1];
4064 rctx
->config_state
.sq_gpr_resource_mgmt_3
= tmp
[2];
4071 r600_mark_atom_dirty(rctx
, &rctx
->config_state
.atom
);
4072 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;