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radeon/llvm: Use correct opcocde for BREAK_LOGICALNZ_i32
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "evergreend.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31 #include "evergreen_compute.h"
32
33 static uint32_t eg_num_banks(uint32_t nbanks)
34 {
35 switch (nbanks) {
36 case 2:
37 return 0;
38 case 4:
39 return 1;
40 case 8:
41 default:
42 return 2;
43 case 16:
44 return 3;
45 }
46 }
47
48
49 static unsigned eg_tile_split(unsigned tile_split)
50 {
51 switch (tile_split) {
52 case 64: tile_split = 0; break;
53 case 128: tile_split = 1; break;
54 case 256: tile_split = 2; break;
55 case 512: tile_split = 3; break;
56 default:
57 case 1024: tile_split = 4; break;
58 case 2048: tile_split = 5; break;
59 case 4096: tile_split = 6; break;
60 }
61 return tile_split;
62 }
63
64 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65 {
66 switch (macro_tile_aspect) {
67 default:
68 case 1: macro_tile_aspect = 0; break;
69 case 2: macro_tile_aspect = 1; break;
70 case 4: macro_tile_aspect = 2; break;
71 case 8: macro_tile_aspect = 3; break;
72 }
73 return macro_tile_aspect;
74 }
75
76 static unsigned eg_bank_wh(unsigned bankwh)
77 {
78 switch (bankwh) {
79 default:
80 case 1: bankwh = 0; break;
81 case 2: bankwh = 1; break;
82 case 4: bankwh = 2; break;
83 case 8: bankwh = 3; break;
84 }
85 return bankwh;
86 }
87
88 static uint32_t r600_translate_blend_function(int blend_func)
89 {
90 switch (blend_func) {
91 case PIPE_BLEND_ADD:
92 return V_028780_COMB_DST_PLUS_SRC;
93 case PIPE_BLEND_SUBTRACT:
94 return V_028780_COMB_SRC_MINUS_DST;
95 case PIPE_BLEND_REVERSE_SUBTRACT:
96 return V_028780_COMB_DST_MINUS_SRC;
97 case PIPE_BLEND_MIN:
98 return V_028780_COMB_MIN_DST_SRC;
99 case PIPE_BLEND_MAX:
100 return V_028780_COMB_MAX_DST_SRC;
101 default:
102 R600_ERR("Unknown blend function %d\n", blend_func);
103 assert(0);
104 break;
105 }
106 return 0;
107 }
108
109 static uint32_t r600_translate_blend_factor(int blend_fact)
110 {
111 switch (blend_fact) {
112 case PIPE_BLENDFACTOR_ONE:
113 return V_028780_BLEND_ONE;
114 case PIPE_BLENDFACTOR_SRC_COLOR:
115 return V_028780_BLEND_SRC_COLOR;
116 case PIPE_BLENDFACTOR_SRC_ALPHA:
117 return V_028780_BLEND_SRC_ALPHA;
118 case PIPE_BLENDFACTOR_DST_ALPHA:
119 return V_028780_BLEND_DST_ALPHA;
120 case PIPE_BLENDFACTOR_DST_COLOR:
121 return V_028780_BLEND_DST_COLOR;
122 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123 return V_028780_BLEND_SRC_ALPHA_SATURATE;
124 case PIPE_BLENDFACTOR_CONST_COLOR:
125 return V_028780_BLEND_CONST_COLOR;
126 case PIPE_BLENDFACTOR_CONST_ALPHA:
127 return V_028780_BLEND_CONST_ALPHA;
128 case PIPE_BLENDFACTOR_ZERO:
129 return V_028780_BLEND_ZERO;
130 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136 case PIPE_BLENDFACTOR_INV_DST_COLOR:
137 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_SRC1_COLOR:
143 return V_028780_BLEND_SRC1_COLOR;
144 case PIPE_BLENDFACTOR_SRC1_ALPHA:
145 return V_028780_BLEND_SRC1_ALPHA;
146 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147 return V_028780_BLEND_INV_SRC1_COLOR;
148 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149 return V_028780_BLEND_INV_SRC1_ALPHA;
150 default:
151 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152 assert(0);
153 break;
154 }
155 return 0;
156 }
157
158 static unsigned r600_tex_dim(unsigned dim)
159 {
160 switch (dim) {
161 default:
162 case PIPE_TEXTURE_1D:
163 return V_030000_SQ_TEX_DIM_1D;
164 case PIPE_TEXTURE_1D_ARRAY:
165 return V_030000_SQ_TEX_DIM_1D_ARRAY;
166 case PIPE_TEXTURE_2D:
167 case PIPE_TEXTURE_RECT:
168 return V_030000_SQ_TEX_DIM_2D;
169 case PIPE_TEXTURE_2D_ARRAY:
170 return V_030000_SQ_TEX_DIM_2D_ARRAY;
171 case PIPE_TEXTURE_3D:
172 return V_030000_SQ_TEX_DIM_3D;
173 case PIPE_TEXTURE_CUBE:
174 return V_030000_SQ_TEX_DIM_CUBEMAP;
175 }
176 }
177
178 static uint32_t r600_translate_dbformat(enum pipe_format format)
179 {
180 switch (format) {
181 case PIPE_FORMAT_Z16_UNORM:
182 return V_028040_Z_16;
183 case PIPE_FORMAT_Z24X8_UNORM:
184 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
185 return V_028040_Z_24;
186 case PIPE_FORMAT_Z32_FLOAT:
187 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
188 return V_028040_Z_32_FLOAT;
189 default:
190 return ~0U;
191 }
192 }
193
194 static uint32_t r600_translate_colorswap(enum pipe_format format)
195 {
196 switch (format) {
197 /* 8-bit buffers. */
198 case PIPE_FORMAT_L4A4_UNORM:
199 case PIPE_FORMAT_A4R4_UNORM:
200 return V_028C70_SWAP_ALT;
201
202 case PIPE_FORMAT_A8_UNORM:
203 case PIPE_FORMAT_A8_SNORM:
204 case PIPE_FORMAT_A8_UINT:
205 case PIPE_FORMAT_A8_SINT:
206 case PIPE_FORMAT_A16_UNORM:
207 case PIPE_FORMAT_A16_SNORM:
208 case PIPE_FORMAT_A16_UINT:
209 case PIPE_FORMAT_A16_SINT:
210 case PIPE_FORMAT_A16_FLOAT:
211 case PIPE_FORMAT_A32_UINT:
212 case PIPE_FORMAT_A32_SINT:
213 case PIPE_FORMAT_A32_FLOAT:
214 case PIPE_FORMAT_R4A4_UNORM:
215 return V_028C70_SWAP_ALT_REV;
216 case PIPE_FORMAT_I8_UNORM:
217 case PIPE_FORMAT_I8_SNORM:
218 case PIPE_FORMAT_I8_UINT:
219 case PIPE_FORMAT_I8_SINT:
220 case PIPE_FORMAT_I16_UNORM:
221 case PIPE_FORMAT_I16_SNORM:
222 case PIPE_FORMAT_I16_UINT:
223 case PIPE_FORMAT_I16_SINT:
224 case PIPE_FORMAT_I16_FLOAT:
225 case PIPE_FORMAT_I32_UINT:
226 case PIPE_FORMAT_I32_SINT:
227 case PIPE_FORMAT_I32_FLOAT:
228 case PIPE_FORMAT_L8_UNORM:
229 case PIPE_FORMAT_L8_SNORM:
230 case PIPE_FORMAT_L8_UINT:
231 case PIPE_FORMAT_L8_SINT:
232 case PIPE_FORMAT_L8_SRGB:
233 case PIPE_FORMAT_L16_UNORM:
234 case PIPE_FORMAT_L16_SNORM:
235 case PIPE_FORMAT_L16_UINT:
236 case PIPE_FORMAT_L16_SINT:
237 case PIPE_FORMAT_L16_FLOAT:
238 case PIPE_FORMAT_L32_UINT:
239 case PIPE_FORMAT_L32_SINT:
240 case PIPE_FORMAT_L32_FLOAT:
241 case PIPE_FORMAT_R8_UNORM:
242 case PIPE_FORMAT_R8_SNORM:
243 case PIPE_FORMAT_R8_UINT:
244 case PIPE_FORMAT_R8_SINT:
245 return V_028C70_SWAP_STD;
246
247 /* 16-bit buffers. */
248 case PIPE_FORMAT_B5G6R5_UNORM:
249 return V_028C70_SWAP_STD_REV;
250
251 case PIPE_FORMAT_B5G5R5A1_UNORM:
252 case PIPE_FORMAT_B5G5R5X1_UNORM:
253 return V_028C70_SWAP_ALT;
254
255 case PIPE_FORMAT_B4G4R4A4_UNORM:
256 case PIPE_FORMAT_B4G4R4X4_UNORM:
257 return V_028C70_SWAP_ALT;
258
259 case PIPE_FORMAT_Z16_UNORM:
260 return V_028C70_SWAP_STD;
261
262 case PIPE_FORMAT_L8A8_UNORM:
263 case PIPE_FORMAT_L8A8_SNORM:
264 case PIPE_FORMAT_L8A8_UINT:
265 case PIPE_FORMAT_L8A8_SINT:
266 case PIPE_FORMAT_L8A8_SRGB:
267 case PIPE_FORMAT_L16A16_UNORM:
268 case PIPE_FORMAT_L16A16_SNORM:
269 case PIPE_FORMAT_L16A16_UINT:
270 case PIPE_FORMAT_L16A16_SINT:
271 case PIPE_FORMAT_L16A16_FLOAT:
272 case PIPE_FORMAT_L32A32_UINT:
273 case PIPE_FORMAT_L32A32_SINT:
274 case PIPE_FORMAT_L32A32_FLOAT:
275 return V_028C70_SWAP_ALT;
276 case PIPE_FORMAT_R8G8_UNORM:
277 case PIPE_FORMAT_R8G8_SNORM:
278 case PIPE_FORMAT_R8G8_UINT:
279 case PIPE_FORMAT_R8G8_SINT:
280 return V_028C70_SWAP_STD;
281
282 case PIPE_FORMAT_R16_UNORM:
283 case PIPE_FORMAT_R16_SNORM:
284 case PIPE_FORMAT_R16_UINT:
285 case PIPE_FORMAT_R16_SINT:
286 case PIPE_FORMAT_R16_FLOAT:
287 return V_028C70_SWAP_STD;
288
289 /* 32-bit buffers. */
290 case PIPE_FORMAT_A8B8G8R8_SRGB:
291 return V_028C70_SWAP_STD_REV;
292 case PIPE_FORMAT_B8G8R8A8_SRGB:
293 return V_028C70_SWAP_ALT;
294
295 case PIPE_FORMAT_B8G8R8A8_UNORM:
296 case PIPE_FORMAT_B8G8R8X8_UNORM:
297 return V_028C70_SWAP_ALT;
298
299 case PIPE_FORMAT_A8R8G8B8_UNORM:
300 case PIPE_FORMAT_X8R8G8B8_UNORM:
301 return V_028C70_SWAP_ALT_REV;
302 case PIPE_FORMAT_R8G8B8A8_SNORM:
303 case PIPE_FORMAT_R8G8B8A8_UNORM:
304 case PIPE_FORMAT_R8G8B8A8_SINT:
305 case PIPE_FORMAT_R8G8B8A8_UINT:
306 case PIPE_FORMAT_R8G8B8X8_UNORM:
307 return V_028C70_SWAP_STD;
308
309 case PIPE_FORMAT_A8B8G8R8_UNORM:
310 case PIPE_FORMAT_X8B8G8R8_UNORM:
311 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
312 return V_028C70_SWAP_STD_REV;
313
314 case PIPE_FORMAT_Z24X8_UNORM:
315 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
316 return V_028C70_SWAP_STD;
317
318 case PIPE_FORMAT_X8Z24_UNORM:
319 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
320 return V_028C70_SWAP_STD;
321
322 case PIPE_FORMAT_R10G10B10A2_UNORM:
323 case PIPE_FORMAT_R10G10B10X2_SNORM:
324 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
325 return V_028C70_SWAP_STD;
326
327 case PIPE_FORMAT_B10G10R10A2_UNORM:
328 case PIPE_FORMAT_B10G10R10A2_UINT:
329 return V_028C70_SWAP_ALT;
330
331 case PIPE_FORMAT_R11G11B10_FLOAT:
332 case PIPE_FORMAT_R32_FLOAT:
333 case PIPE_FORMAT_R32_UINT:
334 case PIPE_FORMAT_R32_SINT:
335 case PIPE_FORMAT_Z32_FLOAT:
336 case PIPE_FORMAT_R16G16_FLOAT:
337 case PIPE_FORMAT_R16G16_UNORM:
338 case PIPE_FORMAT_R16G16_SNORM:
339 case PIPE_FORMAT_R16G16_UINT:
340 case PIPE_FORMAT_R16G16_SINT:
341 case PIPE_FORMAT_R16G16B16_FLOAT:
342 case PIPE_FORMAT_R32G32B32_FLOAT:
343 return V_028C70_SWAP_STD;
344
345 /* 64-bit buffers. */
346 case PIPE_FORMAT_R32G32_FLOAT:
347 case PIPE_FORMAT_R32G32_UINT:
348 case PIPE_FORMAT_R32G32_SINT:
349 case PIPE_FORMAT_R16G16B16A16_UNORM:
350 case PIPE_FORMAT_R16G16B16A16_SNORM:
351 case PIPE_FORMAT_R16G16B16A16_UINT:
352 case PIPE_FORMAT_R16G16B16A16_SINT:
353 case PIPE_FORMAT_R16G16B16A16_FLOAT:
354 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
355
356 /* 128-bit buffers. */
357 case PIPE_FORMAT_R32G32B32A32_FLOAT:
358 case PIPE_FORMAT_R32G32B32A32_SNORM:
359 case PIPE_FORMAT_R32G32B32A32_UNORM:
360 case PIPE_FORMAT_R32G32B32A32_SINT:
361 case PIPE_FORMAT_R32G32B32A32_UINT:
362 return V_028C70_SWAP_STD;
363 default:
364 R600_ERR("unsupported colorswap format %d\n", format);
365 return ~0U;
366 }
367 return ~0U;
368 }
369
370 static uint32_t r600_translate_colorformat(enum pipe_format format)
371 {
372 switch (format) {
373 /* 8-bit buffers. */
374 case PIPE_FORMAT_A8_UNORM:
375 case PIPE_FORMAT_A8_SNORM:
376 case PIPE_FORMAT_A8_UINT:
377 case PIPE_FORMAT_A8_SINT:
378 case PIPE_FORMAT_I8_UNORM:
379 case PIPE_FORMAT_I8_SNORM:
380 case PIPE_FORMAT_I8_UINT:
381 case PIPE_FORMAT_I8_SINT:
382 case PIPE_FORMAT_L8_UNORM:
383 case PIPE_FORMAT_L8_SNORM:
384 case PIPE_FORMAT_L8_UINT:
385 case PIPE_FORMAT_L8_SINT:
386 case PIPE_FORMAT_L8_SRGB:
387 case PIPE_FORMAT_R8_UNORM:
388 case PIPE_FORMAT_R8_SNORM:
389 case PIPE_FORMAT_R8_UINT:
390 case PIPE_FORMAT_R8_SINT:
391 return V_028C70_COLOR_8;
392
393 /* 16-bit buffers. */
394 case PIPE_FORMAT_B5G6R5_UNORM:
395 return V_028C70_COLOR_5_6_5;
396
397 case PIPE_FORMAT_B5G5R5A1_UNORM:
398 case PIPE_FORMAT_B5G5R5X1_UNORM:
399 return V_028C70_COLOR_1_5_5_5;
400
401 case PIPE_FORMAT_B4G4R4A4_UNORM:
402 case PIPE_FORMAT_B4G4R4X4_UNORM:
403 return V_028C70_COLOR_4_4_4_4;
404
405 case PIPE_FORMAT_Z16_UNORM:
406 return V_028C70_COLOR_16;
407
408 case PIPE_FORMAT_L8A8_UNORM:
409 case PIPE_FORMAT_L8A8_SNORM:
410 case PIPE_FORMAT_L8A8_UINT:
411 case PIPE_FORMAT_L8A8_SINT:
412 case PIPE_FORMAT_L8A8_SRGB:
413 case PIPE_FORMAT_R8G8_UNORM:
414 case PIPE_FORMAT_R8G8_SNORM:
415 case PIPE_FORMAT_R8G8_UINT:
416 case PIPE_FORMAT_R8G8_SINT:
417 return V_028C70_COLOR_8_8;
418
419 case PIPE_FORMAT_R16_UNORM:
420 case PIPE_FORMAT_R16_SNORM:
421 case PIPE_FORMAT_R16_UINT:
422 case PIPE_FORMAT_R16_SINT:
423 case PIPE_FORMAT_A16_UNORM:
424 case PIPE_FORMAT_A16_SNORM:
425 case PIPE_FORMAT_A16_UINT:
426 case PIPE_FORMAT_A16_SINT:
427 case PIPE_FORMAT_L16_UNORM:
428 case PIPE_FORMAT_L16_SNORM:
429 case PIPE_FORMAT_L16_UINT:
430 case PIPE_FORMAT_L16_SINT:
431 case PIPE_FORMAT_I16_UNORM:
432 case PIPE_FORMAT_I16_SNORM:
433 case PIPE_FORMAT_I16_UINT:
434 case PIPE_FORMAT_I16_SINT:
435 return V_028C70_COLOR_16;
436
437 case PIPE_FORMAT_R16_FLOAT:
438 case PIPE_FORMAT_A16_FLOAT:
439 case PIPE_FORMAT_L16_FLOAT:
440 case PIPE_FORMAT_I16_FLOAT:
441 return V_028C70_COLOR_16_FLOAT;
442
443 /* 32-bit buffers. */
444 case PIPE_FORMAT_A8B8G8R8_SRGB:
445 case PIPE_FORMAT_A8B8G8R8_UNORM:
446 case PIPE_FORMAT_A8R8G8B8_UNORM:
447 case PIPE_FORMAT_B8G8R8A8_SRGB:
448 case PIPE_FORMAT_B8G8R8A8_UNORM:
449 case PIPE_FORMAT_B8G8R8X8_UNORM:
450 case PIPE_FORMAT_R8G8B8A8_SNORM:
451 case PIPE_FORMAT_R8G8B8A8_UNORM:
452 case PIPE_FORMAT_R8G8B8X8_UNORM:
453 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
454 case PIPE_FORMAT_X8B8G8R8_UNORM:
455 case PIPE_FORMAT_X8R8G8B8_UNORM:
456 case PIPE_FORMAT_R8G8B8_UNORM:
457 case PIPE_FORMAT_R8G8B8A8_SINT:
458 case PIPE_FORMAT_R8G8B8A8_UINT:
459 return V_028C70_COLOR_8_8_8_8;
460
461 case PIPE_FORMAT_R10G10B10A2_UNORM:
462 case PIPE_FORMAT_R10G10B10X2_SNORM:
463 case PIPE_FORMAT_B10G10R10A2_UNORM:
464 case PIPE_FORMAT_B10G10R10A2_UINT:
465 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
466 return V_028C70_COLOR_2_10_10_10;
467
468 case PIPE_FORMAT_Z24X8_UNORM:
469 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
470 return V_028C70_COLOR_8_24;
471
472 case PIPE_FORMAT_X8Z24_UNORM:
473 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
474 return V_028C70_COLOR_24_8;
475
476 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
477 return V_028C70_COLOR_X24_8_32_FLOAT;
478
479 case PIPE_FORMAT_R32_UINT:
480 case PIPE_FORMAT_R32_SINT:
481 case PIPE_FORMAT_A32_UINT:
482 case PIPE_FORMAT_A32_SINT:
483 case PIPE_FORMAT_L32_UINT:
484 case PIPE_FORMAT_L32_SINT:
485 case PIPE_FORMAT_I32_UINT:
486 case PIPE_FORMAT_I32_SINT:
487 return V_028C70_COLOR_32;
488
489 case PIPE_FORMAT_R32_FLOAT:
490 case PIPE_FORMAT_A32_FLOAT:
491 case PIPE_FORMAT_L32_FLOAT:
492 case PIPE_FORMAT_I32_FLOAT:
493 case PIPE_FORMAT_Z32_FLOAT:
494 return V_028C70_COLOR_32_FLOAT;
495
496 case PIPE_FORMAT_R16G16_FLOAT:
497 case PIPE_FORMAT_L16A16_FLOAT:
498 return V_028C70_COLOR_16_16_FLOAT;
499
500 case PIPE_FORMAT_R16G16_UNORM:
501 case PIPE_FORMAT_R16G16_SNORM:
502 case PIPE_FORMAT_R16G16_UINT:
503 case PIPE_FORMAT_R16G16_SINT:
504 case PIPE_FORMAT_L16A16_UNORM:
505 case PIPE_FORMAT_L16A16_SNORM:
506 case PIPE_FORMAT_L16A16_UINT:
507 case PIPE_FORMAT_L16A16_SINT:
508 return V_028C70_COLOR_16_16;
509
510 case PIPE_FORMAT_R11G11B10_FLOAT:
511 return V_028C70_COLOR_10_11_11_FLOAT;
512
513 /* 64-bit buffers. */
514 case PIPE_FORMAT_R16G16B16A16_UINT:
515 case PIPE_FORMAT_R16G16B16A16_SINT:
516 case PIPE_FORMAT_R16G16B16A16_UNORM:
517 case PIPE_FORMAT_R16G16B16A16_SNORM:
518 return V_028C70_COLOR_16_16_16_16;
519
520 case PIPE_FORMAT_R16G16B16_FLOAT:
521 case PIPE_FORMAT_R16G16B16A16_FLOAT:
522 return V_028C70_COLOR_16_16_16_16_FLOAT;
523
524 case PIPE_FORMAT_R32G32_FLOAT:
525 case PIPE_FORMAT_L32A32_FLOAT:
526 return V_028C70_COLOR_32_32_FLOAT;
527
528 case PIPE_FORMAT_R32G32_SINT:
529 case PIPE_FORMAT_R32G32_UINT:
530 case PIPE_FORMAT_L32A32_UINT:
531 case PIPE_FORMAT_L32A32_SINT:
532 return V_028C70_COLOR_32_32;
533
534 /* 96-bit buffers. */
535 case PIPE_FORMAT_R32G32B32_FLOAT:
536 return V_028C70_COLOR_32_32_32_FLOAT;
537
538 /* 128-bit buffers. */
539 case PIPE_FORMAT_R32G32B32A32_SNORM:
540 case PIPE_FORMAT_R32G32B32A32_UNORM:
541 case PIPE_FORMAT_R32G32B32A32_SINT:
542 case PIPE_FORMAT_R32G32B32A32_UINT:
543 return V_028C70_COLOR_32_32_32_32;
544 case PIPE_FORMAT_R32G32B32A32_FLOAT:
545 return V_028C70_COLOR_32_32_32_32_FLOAT;
546
547 /* YUV buffers. */
548 case PIPE_FORMAT_UYVY:
549 case PIPE_FORMAT_YUYV:
550 default:
551 return ~0U; /* Unsupported. */
552 }
553 }
554
555 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
556 {
557 if (R600_BIG_ENDIAN) {
558 switch(colorformat) {
559
560 /* 8-bit buffers. */
561 case V_028C70_COLOR_8:
562 return ENDIAN_NONE;
563
564 /* 16-bit buffers. */
565 case V_028C70_COLOR_5_6_5:
566 case V_028C70_COLOR_1_5_5_5:
567 case V_028C70_COLOR_4_4_4_4:
568 case V_028C70_COLOR_16:
569 case V_028C70_COLOR_8_8:
570 return ENDIAN_8IN16;
571
572 /* 32-bit buffers. */
573 case V_028C70_COLOR_8_8_8_8:
574 case V_028C70_COLOR_2_10_10_10:
575 case V_028C70_COLOR_8_24:
576 case V_028C70_COLOR_24_8:
577 case V_028C70_COLOR_32_FLOAT:
578 case V_028C70_COLOR_16_16_FLOAT:
579 case V_028C70_COLOR_16_16:
580 return ENDIAN_8IN32;
581
582 /* 64-bit buffers. */
583 case V_028C70_COLOR_16_16_16_16:
584 case V_028C70_COLOR_16_16_16_16_FLOAT:
585 return ENDIAN_8IN16;
586
587 case V_028C70_COLOR_32_32_FLOAT:
588 case V_028C70_COLOR_32_32:
589 case V_028C70_COLOR_X24_8_32_FLOAT:
590 return ENDIAN_8IN32;
591
592 /* 96-bit buffers. */
593 case V_028C70_COLOR_32_32_32_FLOAT:
594 /* 128-bit buffers. */
595 case V_028C70_COLOR_32_32_32_32_FLOAT:
596 case V_028C70_COLOR_32_32_32_32:
597 return ENDIAN_8IN32;
598 default:
599 return ENDIAN_NONE; /* Unsupported. */
600 }
601 } else {
602 return ENDIAN_NONE;
603 }
604 }
605
606 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
607 {
608 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
609 }
610
611 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
612 {
613 return r600_translate_colorformat(format) != ~0U &&
614 r600_translate_colorswap(format) != ~0U;
615 }
616
617 static bool r600_is_zs_format_supported(enum pipe_format format)
618 {
619 return r600_translate_dbformat(format) != ~0U;
620 }
621
622 boolean evergreen_is_format_supported(struct pipe_screen *screen,
623 enum pipe_format format,
624 enum pipe_texture_target target,
625 unsigned sample_count,
626 unsigned usage)
627 {
628 unsigned retval = 0;
629
630 if (target >= PIPE_MAX_TEXTURE_TYPES) {
631 R600_ERR("r600: unsupported texture type %d\n", target);
632 return FALSE;
633 }
634
635 if (!util_format_is_supported(format, usage))
636 return FALSE;
637
638 /* Multisample */
639 if (sample_count > 1)
640 return FALSE;
641
642 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
643 r600_is_sampler_format_supported(screen, format)) {
644 retval |= PIPE_BIND_SAMPLER_VIEW;
645 }
646
647 if ((usage & (PIPE_BIND_RENDER_TARGET |
648 PIPE_BIND_DISPLAY_TARGET |
649 PIPE_BIND_SCANOUT |
650 PIPE_BIND_SHARED)) &&
651 r600_is_colorbuffer_format_supported(format)) {
652 retval |= usage &
653 (PIPE_BIND_RENDER_TARGET |
654 PIPE_BIND_DISPLAY_TARGET |
655 PIPE_BIND_SCANOUT |
656 PIPE_BIND_SHARED);
657 }
658
659 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
660 r600_is_zs_format_supported(format)) {
661 retval |= PIPE_BIND_DEPTH_STENCIL;
662 }
663
664 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
665 r600_is_vertex_format_supported(format)) {
666 retval |= PIPE_BIND_VERTEX_BUFFER;
667 }
668
669 if (usage & PIPE_BIND_TRANSFER_READ)
670 retval |= PIPE_BIND_TRANSFER_READ;
671 if (usage & PIPE_BIND_TRANSFER_WRITE)
672 retval |= PIPE_BIND_TRANSFER_WRITE;
673
674 return retval == usage;
675 }
676
677 static void *evergreen_create_blend_state(struct pipe_context *ctx,
678 const struct pipe_blend_state *state)
679 {
680 struct r600_context *rctx = (struct r600_context *)ctx;
681 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
682 struct r600_pipe_state *rstate;
683 uint32_t color_control = 0, target_mask;
684 /* XXX there is more then 8 framebuffer */
685 unsigned blend_cntl[8];
686
687 if (blend == NULL) {
688 return NULL;
689 }
690
691 rstate = &blend->rstate;
692
693 rstate->id = R600_PIPE_STATE_BLEND;
694
695 target_mask = 0;
696 if (state->logicop_enable) {
697 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
698 } else {
699 color_control |= (0xcc << 16);
700 }
701 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
702 if (state->independent_blend_enable) {
703 for (int i = 0; i < 8; i++) {
704 target_mask |= (state->rt[i].colormask << (4 * i));
705 }
706 } else {
707 for (int i = 0; i < 8; i++) {
708 target_mask |= (state->rt[0].colormask << (4 * i));
709 }
710 }
711 blend->cb_target_mask = target_mask;
712
713 if (target_mask)
714 color_control |= S_028808_MODE(V_028808_CB_NORMAL);
715 else
716 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
717
718 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
719 color_control);
720 /* only have dual source on MRT0 */
721 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
722 for (int i = 0; i < 8; i++) {
723 /* state->rt entries > 0 only written if independent blending */
724 const int j = state->independent_blend_enable ? i : 0;
725
726 unsigned eqRGB = state->rt[j].rgb_func;
727 unsigned srcRGB = state->rt[j].rgb_src_factor;
728 unsigned dstRGB = state->rt[j].rgb_dst_factor;
729 unsigned eqA = state->rt[j].alpha_func;
730 unsigned srcA = state->rt[j].alpha_src_factor;
731 unsigned dstA = state->rt[j].alpha_dst_factor;
732
733 blend_cntl[i] = 0;
734 if (!state->rt[j].blend_enable)
735 continue;
736
737 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
738 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
739 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
740 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
741
742 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
743 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
744 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
745 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
746 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
747 }
748 }
749 for (int i = 0; i < 8; i++) {
750 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
751 }
752
753 return rstate;
754 }
755
756 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
757 const struct pipe_depth_stencil_alpha_state *state)
758 {
759 struct r600_context *rctx = (struct r600_context *)ctx;
760 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
761 unsigned db_depth_control, alpha_test_control, alpha_ref;
762 struct r600_pipe_state *rstate;
763
764 if (dsa == NULL) {
765 return NULL;
766 }
767
768 dsa->valuemask[0] = state->stencil[0].valuemask;
769 dsa->valuemask[1] = state->stencil[1].valuemask;
770 dsa->writemask[0] = state->stencil[0].writemask;
771 dsa->writemask[1] = state->stencil[1].writemask;
772
773 rstate = &dsa->rstate;
774
775 rstate->id = R600_PIPE_STATE_DSA;
776 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
777 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
778 S_028800_ZFUNC(state->depth.func);
779
780 /* stencil */
781 if (state->stencil[0].enabled) {
782 db_depth_control |= S_028800_STENCIL_ENABLE(1);
783 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
784 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
785 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
786 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
787
788 if (state->stencil[1].enabled) {
789 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
790 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
791 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
792 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
793 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
794 }
795 }
796
797 /* alpha */
798 alpha_test_control = 0;
799 alpha_ref = 0;
800 if (state->alpha.enabled) {
801 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
802 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
803 alpha_ref = fui(state->alpha.ref_value);
804 }
805 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
806 dsa->alpha_ref = alpha_ref;
807
808 /* misc */
809 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
810 return rstate;
811 }
812
813 static void *evergreen_create_rs_state(struct pipe_context *ctx,
814 const struct pipe_rasterizer_state *state)
815 {
816 struct r600_context *rctx = (struct r600_context *)ctx;
817 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
818 struct r600_pipe_state *rstate;
819 unsigned tmp;
820 unsigned prov_vtx = 1, polygon_dual_mode;
821 float psize_min, psize_max;
822
823 if (rs == NULL) {
824 return NULL;
825 }
826
827 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
828 state->fill_back != PIPE_POLYGON_MODE_FILL);
829
830 if (state->flatshade_first)
831 prov_vtx = 0;
832
833 rstate = &rs->rstate;
834 rs->flatshade = state->flatshade;
835 rs->sprite_coord_enable = state->sprite_coord_enable;
836 rs->two_side = state->light_twoside;
837 rs->clip_plane_enable = state->clip_plane_enable;
838 rs->pa_sc_line_stipple = state->line_stipple_enable ?
839 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
840 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
841 rs->pa_cl_clip_cntl =
842 S_028810_PS_UCP_MODE(3) |
843 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
844 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
845 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
846
847 /* offset */
848 rs->offset_units = state->offset_units;
849 rs->offset_scale = state->offset_scale * 12.0f;
850
851 rstate->id = R600_PIPE_STATE_RASTERIZER;
852 tmp = S_0286D4_FLAT_SHADE_ENA(1);
853 if (state->sprite_coord_enable) {
854 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
855 S_0286D4_PNT_SPRITE_OVRD_X(2) |
856 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
857 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
858 S_0286D4_PNT_SPRITE_OVRD_W(1);
859 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
860 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
861 }
862 }
863 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
864
865 /* point size 12.4 fixed point */
866 tmp = (unsigned)(state->point_size * 8.0);
867 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
868
869 if (state->point_size_per_vertex) {
870 psize_min = util_get_min_point_size(state);
871 psize_max = 8192;
872 } else {
873 /* Force the point size to be as if the vertex output was disabled. */
874 psize_min = state->point_size;
875 psize_max = state->point_size;
876 }
877 /* Divide by two, because 0.5 = 1 pixel. */
878 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
879 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
880 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
881
882 tmp = (unsigned)state->line_width * 8;
883 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
884 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
885 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
886 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
887
888 if (rctx->chip_class == CAYMAN) {
889 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
890 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
891 } else {
892 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
893 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
894 }
895 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
896 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
897 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
898 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
899 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
900 S_028814_FACE(!state->front_ccw) |
901 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
902 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
903 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
904 S_028814_POLY_MODE(polygon_dual_mode) |
905 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
906 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
907 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
908 return rstate;
909 }
910
911 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
912 const struct pipe_sampler_state *state)
913 {
914 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
915 union util_color uc;
916 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
917
918 if (ss == NULL) {
919 return NULL;
920 }
921
922 /* directly into sampler avoid r6xx code to emit useless reg */
923 ss->seamless_cube_map = false;
924 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
925 ss->border_color_use = false;
926 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
927 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
928 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
929 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
930 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
931 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
932 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
933 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
934 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
935 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
936 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
937 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
938 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
939 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
940 ss->tex_sampler_words[2] = S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
941 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
942 S_03C008_TYPE(1);
943 if (uc.ui) {
944 ss->border_color_use = true;
945 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
946 ss->border_color[0] = fui(state->border_color.f[0]);
947 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
948 ss->border_color[1] = fui(state->border_color.f[1]);
949 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
950 ss->border_color[2] = fui(state->border_color.f[2]);
951 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
952 ss->border_color[3] = fui(state->border_color.f[3]);
953 }
954 return ss;
955 }
956
957 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
958 struct pipe_resource *texture,
959 const struct pipe_sampler_view *state)
960 {
961 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
962 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
963 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
964 unsigned format, endian;
965 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
966 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
967 unsigned height, depth, width;
968 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
969
970 if (view == NULL)
971 return NULL;
972
973 /* initialize base object */
974 view->base = *state;
975 view->base.texture = NULL;
976 pipe_reference(NULL, &texture->reference);
977 view->base.texture = texture;
978 view->base.reference.count = 1;
979 view->base.context = ctx;
980
981 swizzle[0] = state->swizzle_r;
982 swizzle[1] = state->swizzle_g;
983 swizzle[2] = state->swizzle_b;
984 swizzle[3] = state->swizzle_a;
985
986 format = r600_translate_texformat(ctx->screen, state->format,
987 swizzle,
988 &word4, &yuv_format);
989 assert(format != ~0);
990 if (format == ~0) {
991 FREE(view);
992 return NULL;
993 }
994
995 if (tmp->is_depth && !tmp->is_flushing_texture) {
996 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
997 FREE(view);
998 return NULL;
999 }
1000 tmp = tmp->flushed_depth_texture;
1001 }
1002
1003 endian = r600_colorformat_endian_swap(format);
1004
1005 width = tmp->surface.level[0].npix_x;
1006 height = tmp->surface.level[0].npix_y;
1007 depth = tmp->surface.level[0].npix_z;
1008 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1009 tile_type = tmp->tile_type;
1010
1011 switch (tmp->surface.level[0].mode) {
1012 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1013 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1014 break;
1015 case RADEON_SURF_MODE_2D:
1016 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1017 break;
1018 case RADEON_SURF_MODE_1D:
1019 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1020 break;
1021 case RADEON_SURF_MODE_LINEAR:
1022 default:
1023 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1024 break;
1025 }
1026 tile_split = tmp->surface.tile_split;
1027 macro_aspect = tmp->surface.mtilea;
1028 bankw = tmp->surface.bankw;
1029 bankh = tmp->surface.bankh;
1030 tile_split = eg_tile_split(tile_split);
1031 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1032 bankw = eg_bank_wh(bankw);
1033 bankh = eg_bank_wh(bankh);
1034
1035 /* 128 bit formats require tile type = 1 */
1036 if (rscreen->chip_class == CAYMAN) {
1037 if (util_format_get_blocksize(state->format) >= 16)
1038 tile_type = 1;
1039 }
1040 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1041
1042 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1043 height = 1;
1044 depth = texture->array_size;
1045 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1046 depth = texture->array_size;
1047 }
1048
1049 view->tex_resource = &tmp->resource;
1050 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1051 S_030000_PITCH((pitch / 8) - 1) |
1052 S_030000_TEX_WIDTH(width - 1));
1053 if (rscreen->chip_class == CAYMAN)
1054 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1055 else
1056 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1057 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1058 S_030004_TEX_DEPTH(depth - 1) |
1059 S_030004_ARRAY_MODE(array_mode));
1060 view->tex_resource_words[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1061 if (state->u.tex.last_level) {
1062 view->tex_resource_words[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1063 } else {
1064 view->tex_resource_words[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1065 }
1066 view->tex_resource_words[4] = (word4 |
1067 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1068 S_030010_ENDIAN_SWAP(endian) |
1069 S_030010_BASE_LEVEL(state->u.tex.first_level));
1070 view->tex_resource_words[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1071 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1072 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1073 /* aniso max 16 samples */
1074 view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
1075 (S_030018_TILE_SPLIT(tile_split));
1076 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1077 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1078 S_03001C_BANK_WIDTH(bankw) |
1079 S_03001C_BANK_HEIGHT(bankh) |
1080 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1081 S_03001C_NUM_BANKS(nbanks);
1082 return &view->base;
1083 }
1084
1085 static void evergreen_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1086 struct pipe_sampler_view **views)
1087 {
1088 struct r600_context *rctx = (struct r600_context *)ctx;
1089 r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views);
1090 }
1091
1092 static void evergreen_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1093 struct pipe_sampler_view **views)
1094 {
1095 struct r600_context *rctx = (struct r600_context *)ctx;
1096 r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views);
1097 }
1098
1099 static void evergreen_set_clip_state(struct pipe_context *ctx,
1100 const struct pipe_clip_state *state)
1101 {
1102 struct r600_context *rctx = (struct r600_context *)ctx;
1103 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1104 struct pipe_constant_buffer cb;
1105
1106 if (rstate == NULL)
1107 return;
1108
1109 rctx->clip = *state;
1110 rstate->id = R600_PIPE_STATE_CLIP;
1111 for (int i = 0; i < 6; i++) {
1112 r600_pipe_state_add_reg(rstate,
1113 R_0285BC_PA_CL_UCP0_X + i * 16,
1114 fui(state->ucp[i][0]));
1115 r600_pipe_state_add_reg(rstate,
1116 R_0285C0_PA_CL_UCP0_Y + i * 16,
1117 fui(state->ucp[i][1]) );
1118 r600_pipe_state_add_reg(rstate,
1119 R_0285C4_PA_CL_UCP0_Z + i * 16,
1120 fui(state->ucp[i][2]));
1121 r600_pipe_state_add_reg(rstate,
1122 R_0285C8_PA_CL_UCP0_W + i * 16,
1123 fui(state->ucp[i][3]));
1124 }
1125
1126 free(rctx->states[R600_PIPE_STATE_CLIP]);
1127 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1128 r600_context_pipe_state_set(rctx, rstate);
1129
1130 cb.buffer = NULL;
1131 cb.user_buffer = state->ucp;
1132 cb.buffer_offset = 0;
1133 cb.buffer_size = 4*4*8;
1134 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1135 pipe_resource_reference(&cb.buffer, NULL);
1136 }
1137
1138 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1139 const struct pipe_poly_stipple *state)
1140 {
1141 }
1142
1143 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1144 {
1145 }
1146
1147 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1148 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1149 uint32_t *tl, uint32_t *br)
1150 {
1151 /* EG hw workaround */
1152 if (br_x == 0)
1153 tl_x = 1;
1154 if (br_y == 0)
1155 tl_y = 1;
1156
1157 /* cayman hw workaround */
1158 if (rctx->chip_class == CAYMAN) {
1159 if (br_x == 1 && br_y == 1)
1160 br_x = 2;
1161 }
1162
1163 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1164 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1165 }
1166
1167 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1168 const struct pipe_scissor_state *state)
1169 {
1170 struct r600_context *rctx = (struct r600_context *)ctx;
1171 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1172 uint32_t tl, br;
1173
1174 if (rstate == NULL)
1175 return;
1176
1177 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1178
1179 rstate->id = R600_PIPE_STATE_SCISSOR;
1180 r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1181 r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1182
1183 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1184 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1185 r600_context_pipe_state_set(rctx, rstate);
1186 }
1187
1188 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1189 const struct pipe_viewport_state *state)
1190 {
1191 struct r600_context *rctx = (struct r600_context *)ctx;
1192 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1193
1194 if (rstate == NULL)
1195 return;
1196
1197 rctx->viewport = *state;
1198 rstate->id = R600_PIPE_STATE_VIEWPORT;
1199 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1200 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1201 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1202 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1203 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1204 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1205
1206 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1207 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1208 r600_context_pipe_state_set(rctx, rstate);
1209 }
1210
1211 void evergreen_init_color_surface(struct r600_context *rctx,
1212 struct r600_surface *surf)
1213 {
1214 struct r600_screen *rscreen = rctx->screen;
1215 struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
1216 struct pipe_resource *pipe_tex = surf->base.texture;
1217 unsigned level = surf->base.u.tex.level;
1218 unsigned pitch, slice;
1219 unsigned color_info, color_attrib, color_dim = 0;
1220 unsigned format, swap, ntype, endian;
1221 uint64_t offset;
1222 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1223 const struct util_format_description *desc;
1224 int i;
1225 bool blend_clamp = 0, blend_bypass = 0;
1226
1227 if (rtex->is_depth && !rtex->is_flushing_texture) {
1228 r600_init_flushed_depth_texture(&rctx->context, pipe_tex, NULL);
1229 rtex = rtex->flushed_depth_texture;
1230 assert(rtex);
1231 }
1232
1233 offset = rtex->surface.level[level].offset;
1234 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1235 offset += rtex->surface.level[level].slice_size *
1236 surf->base.u.tex.first_layer;
1237 }
1238 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1239 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1240 if (slice) {
1241 slice = slice - 1;
1242 }
1243 color_info = 0;
1244 switch (rtex->surface.level[level].mode) {
1245 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1246 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1247 tile_type = 1;
1248 break;
1249 case RADEON_SURF_MODE_1D:
1250 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1251 tile_type = rtex->tile_type;
1252 break;
1253 case RADEON_SURF_MODE_2D:
1254 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1255 tile_type = rtex->tile_type;
1256 break;
1257 case RADEON_SURF_MODE_LINEAR:
1258 default:
1259 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1260 tile_type = 1;
1261 break;
1262 }
1263 tile_split = rtex->surface.tile_split;
1264 macro_aspect = rtex->surface.mtilea;
1265 bankw = rtex->surface.bankw;
1266 bankh = rtex->surface.bankh;
1267 tile_split = eg_tile_split(tile_split);
1268 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1269 bankw = eg_bank_wh(bankw);
1270 bankh = eg_bank_wh(bankh);
1271
1272 /* 128 bit formats require tile type = 1 */
1273 if (rscreen->chip_class == CAYMAN) {
1274 if (util_format_get_blocksize(surf->base.format) >= 16)
1275 tile_type = 1;
1276 }
1277 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1278 desc = util_format_description(surf->base.format);
1279 for (i = 0; i < 4; i++) {
1280 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1281 break;
1282 }
1283 }
1284
1285 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1286 S_028C74_NUM_BANKS(nbanks) |
1287 S_028C74_BANK_WIDTH(bankw) |
1288 S_028C74_BANK_HEIGHT(bankh) |
1289 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1290 S_028C74_NON_DISP_TILING_ORDER(tile_type);
1291
1292 ntype = V_028C70_NUMBER_UNORM;
1293 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1294 ntype = V_028C70_NUMBER_SRGB;
1295 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1296 if (desc->channel[i].normalized)
1297 ntype = V_028C70_NUMBER_SNORM;
1298 else if (desc->channel[i].pure_integer)
1299 ntype = V_028C70_NUMBER_SINT;
1300 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1301 if (desc->channel[i].normalized)
1302 ntype = V_028C70_NUMBER_UNORM;
1303 else if (desc->channel[i].pure_integer)
1304 ntype = V_028C70_NUMBER_UINT;
1305 }
1306
1307 format = r600_translate_colorformat(surf->base.format);
1308 assert(format != ~0);
1309
1310 swap = r600_translate_colorswap(surf->base.format);
1311 assert(swap != ~0);
1312
1313 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1314 endian = ENDIAN_NONE;
1315 } else {
1316 endian = r600_colorformat_endian_swap(format);
1317 }
1318
1319 /* blend clamp should be set for all NORM/SRGB types */
1320 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1321 ntype == V_028C70_NUMBER_SRGB)
1322 blend_clamp = 1;
1323
1324 /* set blend bypass according to docs if SINT/UINT or
1325 8/24 COLOR variants */
1326 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1327 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1328 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1329 blend_clamp = 0;
1330 blend_bypass = 1;
1331 }
1332
1333 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1334
1335 color_info |= S_028C70_FORMAT(format) |
1336 S_028C70_COMP_SWAP(swap) |
1337 S_028C70_BLEND_CLAMP(blend_clamp) |
1338 S_028C70_BLEND_BYPASS(blend_bypass) |
1339 S_028C70_NUMBER_TYPE(ntype) |
1340 S_028C70_ENDIAN(endian);
1341
1342 if (rtex->is_rat) {
1343 color_info |= S_028C70_RAT(1);
1344 color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0)
1345 | S_028C78_HEIGHT_MAX(pipe_tex->height0);
1346 }
1347
1348 /* EXPORT_NORM is an optimzation that can be enabled for better
1349 * performance in certain cases.
1350 * EXPORT_NORM can be enabled if:
1351 * - 11-bit or smaller UNORM/SNORM/SRGB
1352 * - 16-bit or smaller FLOAT
1353 */
1354 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1355 ((desc->channel[i].size < 12 &&
1356 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1357 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1358 (desc->channel[i].size < 17 &&
1359 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1360 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1361 surf->export_16bpc = true;
1362 }
1363
1364 offset += r600_resource_va(rctx->context.screen, pipe_tex);
1365 offset >>= 8;
1366
1367 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1368 surf->cb_color_base = offset;
1369 surf->cb_color_dim = color_dim;
1370 surf->cb_color_info = color_info;
1371 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1372 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1373 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1374 surf->cb_color_view = 0;
1375 } else {
1376 surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1377 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1378 }
1379 surf->cb_color_attrib = color_attrib;
1380
1381 surf->color_initialized = true;
1382 }
1383
1384 static void evergreen_init_depth_surface(struct r600_context *rctx,
1385 struct r600_surface *surf)
1386 {
1387 struct r600_screen *rscreen = rctx->screen;
1388 struct pipe_screen *screen = &rscreen->screen;
1389 struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
1390 uint64_t offset;
1391 unsigned level, pitch, slice, format, array_mode;
1392 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1393
1394 level = surf->base.u.tex.level;
1395 format = r600_translate_dbformat(surf->base.format);
1396 assert(format != ~0);
1397
1398 offset = r600_resource_va(screen, surf->base.texture);
1399 offset += rtex->surface.level[level].offset;
1400 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1401 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1402 if (slice) {
1403 slice = slice - 1;
1404 }
1405 switch (rtex->surface.level[level].mode) {
1406 case RADEON_SURF_MODE_2D:
1407 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1408 break;
1409 case RADEON_SURF_MODE_1D:
1410 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1411 case RADEON_SURF_MODE_LINEAR:
1412 default:
1413 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1414 break;
1415 }
1416 tile_split = rtex->surface.tile_split;
1417 macro_aspect = rtex->surface.mtilea;
1418 bankw = rtex->surface.bankw;
1419 bankh = rtex->surface.bankh;
1420 tile_split = eg_tile_split(tile_split);
1421 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1422 bankw = eg_bank_wh(bankw);
1423 bankh = eg_bank_wh(bankh);
1424 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1425 offset >>= 8;
1426
1427 surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1428 S_028040_FORMAT(format) |
1429 S_028040_TILE_SPLIT(tile_split)|
1430 S_028040_NUM_BANKS(nbanks) |
1431 S_028040_BANK_WIDTH(bankw) |
1432 S_028040_BANK_HEIGHT(bankh) |
1433 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1434 surf->db_depth_base = offset;
1435 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1436 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1437 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1438 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1439
1440 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1441 uint64_t stencil_offset = rtex->surface.stencil_offset;
1442 unsigned stile_split = rtex->surface.stencil_tile_split;
1443
1444 stile_split = eg_tile_split(stile_split);
1445 stencil_offset += r600_resource_va(screen, surf->base.texture);
1446 stencil_offset += rtex->surface.level[level].offset / 4;
1447 stencil_offset >>= 8;
1448
1449 surf->db_stencil_base = stencil_offset;
1450 surf->db_stencil_info = 1 | S_028044_TILE_SPLIT(stile_split);
1451 } else {
1452 surf->db_stencil_base = offset;
1453 surf->db_stencil_info = 1;
1454 }
1455
1456 surf->depth_initialized = true;
1457 }
1458
1459 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1460 const struct pipe_framebuffer_state *state)
1461 {
1462 struct r600_context *rctx = (struct r600_context *)ctx;
1463 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1464 struct r600_surface *surf;
1465 struct r600_resource *res;
1466 uint32_t tl, br;
1467 int i;
1468
1469 if (rstate == NULL)
1470 return;
1471
1472 r600_flush_framebuffer(rctx, false);
1473
1474 /* unreference old buffer and reference new one */
1475 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1476
1477 util_copy_framebuffer_state(&rctx->framebuffer, state);
1478
1479 /* build states */
1480 rctx->export_16bpc = true;
1481 rctx->nr_cbufs = state->nr_cbufs;
1482
1483 for (i = 0; i < state->nr_cbufs; i++) {
1484 surf = (struct r600_surface*)state->cbufs[i];
1485 res = (struct r600_resource*)surf->base.texture;
1486
1487 if (!surf->color_initialized) {
1488 evergreen_init_color_surface(rctx, surf);
1489 }
1490
1491 if (!surf->export_16bpc) {
1492 rctx->export_16bpc = false;
1493 }
1494
1495 r600_pipe_state_add_reg_bo(rstate, R_028C60_CB_COLOR0_BASE + i * 0x3C,
1496 surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1497 r600_pipe_state_add_reg(rstate, R_028C78_CB_COLOR0_DIM + i * 0x3C,
1498 surf->cb_color_dim);
1499 r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1500 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1501 r600_pipe_state_add_reg(rstate, R_028C64_CB_COLOR0_PITCH + i * 0x3C,
1502 surf->cb_color_pitch);
1503 r600_pipe_state_add_reg(rstate, R_028C68_CB_COLOR0_SLICE + i * 0x3C,
1504 surf->cb_color_slice);
1505 r600_pipe_state_add_reg(rstate, R_028C6C_CB_COLOR0_VIEW + i * 0x3C,
1506 surf->cb_color_view);
1507 r600_pipe_state_add_reg_bo(rstate, R_028C74_CB_COLOR0_ATTRIB + i * 0x3C,
1508 surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
1509 }
1510 /* set CB_COLOR1_INFO for possible dual-src blending */
1511 if (i == 1 && !((struct r600_resource_texture*)res)->is_rat) {
1512 r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1513 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1514 i++;
1515 }
1516 for (; i < 8 ; i++) {
1517 r600_pipe_state_add_reg(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1518 }
1519
1520 /* Update alpha-test state dependencies.
1521 * Alpha-test is done on the first colorbuffer only. */
1522 if (state->nr_cbufs) {
1523 surf = (struct r600_surface*)state->cbufs[0];
1524 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1525 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1526 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1527 }
1528 if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
1529 rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
1530 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1531 }
1532 }
1533
1534 if (state->zsbuf) {
1535 surf = (struct r600_surface*)state->zsbuf;
1536 res = (struct r600_resource*)surf->base.texture;
1537
1538 if (!surf->depth_initialized) {
1539 evergreen_init_depth_surface(rctx, surf);
1540 }
1541
1542 r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE, surf->db_depth_base,
1543 res, RADEON_USAGE_READWRITE);
1544 r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base,
1545 res, RADEON_USAGE_READWRITE);
1546 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, surf->db_depth_view);
1547
1548 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base,
1549 res, RADEON_USAGE_READWRITE);
1550 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE, surf->db_stencil_base,
1551 res, RADEON_USAGE_READWRITE);
1552 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO, surf->db_stencil_info,
1553 res, RADEON_USAGE_READWRITE);
1554
1555 r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, surf->db_depth_info,
1556 res, RADEON_USAGE_READWRITE);
1557 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE, surf->db_depth_size);
1558 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, surf->db_depth_slice);
1559 }
1560
1561 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1562
1563 r600_pipe_state_add_reg(rstate,
1564 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1565 r600_pipe_state_add_reg(rstate,
1566 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1567
1568 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1569 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1570 r600_context_pipe_state_set(rctx, rstate);
1571
1572 if (state->zsbuf) {
1573 evergreen_polygon_offset_update(rctx);
1574 }
1575
1576 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1577 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1578 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1579 }
1580
1581 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1582 rctx->alphatest_state.bypass = false;
1583 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1584 }
1585 }
1586
1587 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1588 {
1589 struct radeon_winsys_cs *cs = rctx->cs;
1590 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1591 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1592 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1593
1594 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1595 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1596 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
1597 * will assure that the alpha-test will work even if there is
1598 * no colorbuffer bound. */
1599 r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1600 }
1601
1602 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1603 {
1604 struct radeon_winsys_cs *cs = rctx->cs;
1605 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1606 unsigned db_render_control = 0;
1607 unsigned db_count_control = 0;
1608 unsigned db_render_override =
1609 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1610 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1611 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1612
1613 if (a->occlusion_query_enabled) {
1614 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1615 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1616 }
1617
1618 if (a->flush_depthstencil_through_cb) {
1619 assert(a->copy_depth || a->copy_stencil);
1620
1621 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1622 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1623 S_028000_COPY_CENTROID(1);
1624 }
1625
1626 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1627 r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1628 r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1629 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1630 }
1631
1632 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1633 struct r600_vertexbuf_state *state,
1634 unsigned resource_offset,
1635 unsigned pkt_flags)
1636 {
1637 struct radeon_winsys_cs *cs = rctx->cs;
1638 uint32_t dirty_mask = state->dirty_mask;
1639
1640 while (dirty_mask) {
1641 struct pipe_vertex_buffer *vb;
1642 struct r600_resource *rbuffer;
1643 uint64_t va;
1644 unsigned buffer_index = u_bit_scan(&dirty_mask);
1645
1646 vb = &state->vb[buffer_index];
1647 rbuffer = (struct r600_resource*)vb->buffer;
1648 assert(rbuffer);
1649
1650 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1651 va += vb->buffer_offset;
1652
1653 /* fetch resources start at index 992 */
1654 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1655 r600_write_value(cs, (resource_offset + buffer_index) * 8);
1656 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1657 r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1658 r600_write_value(cs, /* RESOURCEi_WORD2 */
1659 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1660 S_030008_STRIDE(vb->stride) |
1661 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1662 r600_write_value(cs, /* RESOURCEi_WORD3 */
1663 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1664 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1665 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1666 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1667 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1668 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1669 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1670 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1671
1672 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1673 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1674 }
1675 state->dirty_mask = 0;
1676 }
1677
1678 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1679 {
1680 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
1681 }
1682
1683 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1684 {
1685 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
1686 RADEON_CP_PACKET3_COMPUTE_MODE);
1687 }
1688
1689 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1690 struct r600_constbuf_state *state,
1691 unsigned buffer_id_base,
1692 unsigned reg_alu_constbuf_size,
1693 unsigned reg_alu_const_cache)
1694 {
1695 struct radeon_winsys_cs *cs = rctx->cs;
1696 uint32_t dirty_mask = state->dirty_mask;
1697
1698 while (dirty_mask) {
1699 struct pipe_constant_buffer *cb;
1700 struct r600_resource *rbuffer;
1701 uint64_t va;
1702 unsigned buffer_index = ffs(dirty_mask) - 1;
1703
1704 cb = &state->cb[buffer_index];
1705 rbuffer = (struct r600_resource*)cb->buffer;
1706 assert(rbuffer);
1707
1708 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1709 va += cb->buffer_offset;
1710
1711 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1712 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1713 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
1714
1715 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1716 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1717
1718 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1719 r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
1720 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1721 r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1722 r600_write_value(cs, /* RESOURCEi_WORD2 */
1723 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1724 S_030008_STRIDE(16) |
1725 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1726 r600_write_value(cs, /* RESOURCEi_WORD3 */
1727 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1728 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1729 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1730 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1731 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1732 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1733 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1734 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1735
1736 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1737 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1738
1739 dirty_mask &= ~(1 << buffer_index);
1740 }
1741 state->dirty_mask = 0;
1742 }
1743
1744 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1745 {
1746 evergreen_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 176,
1747 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1748 R_028980_ALU_CONST_CACHE_VS_0);
1749 }
1750
1751 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1752 {
1753 evergreen_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1754 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1755 R_028940_ALU_CONST_CACHE_PS_0);
1756 }
1757
1758 static void evergreen_emit_sampler_views(struct r600_context *rctx,
1759 struct r600_samplerview_state *state,
1760 unsigned resource_id_base)
1761 {
1762 struct radeon_winsys_cs *cs = rctx->cs;
1763 uint32_t dirty_mask = state->dirty_mask;
1764
1765 while (dirty_mask) {
1766 struct r600_pipe_sampler_view *rview;
1767 unsigned resource_index = u_bit_scan(&dirty_mask);
1768 unsigned reloc;
1769
1770 rview = state->views[resource_index];
1771 assert(rview);
1772
1773 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1774 r600_write_value(cs, (resource_id_base + resource_index) * 8);
1775 r600_write_array(cs, 8, rview->tex_resource_words);
1776
1777 /* XXX The kernel needs two relocations. This is stupid. */
1778 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1779 RADEON_USAGE_READ);
1780 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1781 r600_write_value(cs, reloc);
1782 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1783 r600_write_value(cs, reloc);
1784 }
1785 state->dirty_mask = 0;
1786 }
1787
1788 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1789 {
1790 evergreen_emit_sampler_views(rctx, &rctx->vs_samplers.views, 176 + R600_MAX_CONST_BUFFERS);
1791 }
1792
1793 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1794 {
1795 evergreen_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
1796 }
1797
1798 static void evergreen_emit_sampler(struct r600_context *rctx,
1799 struct r600_textures_info *texinfo,
1800 unsigned resource_id_base,
1801 unsigned border_index_reg)
1802 {
1803 struct radeon_winsys_cs *cs = rctx->cs;
1804 unsigned i;
1805
1806 for (i = 0; i < texinfo->n_samplers; i++) {
1807
1808 if (texinfo->samplers[i] == NULL) {
1809 continue;
1810 }
1811 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1812 r600_write_value(cs, (resource_id_base + i) * 3);
1813 r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words);
1814
1815 if (texinfo->samplers[i]->border_color_use) {
1816 r600_write_config_reg_seq(cs, border_index_reg, 5);
1817 r600_write_value(cs, i);
1818 r600_write_array(cs, 4, texinfo->samplers[i]->border_color);
1819 }
1820 }
1821 }
1822
1823 static void evergreen_emit_vs_sampler(struct r600_context *rctx, struct r600_atom *atom)
1824 {
1825 evergreen_emit_sampler(rctx, &rctx->vs_samplers, 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
1826 }
1827
1828 static void evergreen_emit_ps_sampler(struct r600_context *rctx, struct r600_atom *atom)
1829 {
1830 evergreen_emit_sampler(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
1831 }
1832
1833 void evergreen_init_state_functions(struct r600_context *rctx)
1834 {
1835 r600_init_atom(&rctx->cb_misc_state.atom, evergreen_emit_cb_misc_state, 0, 0);
1836 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1837 r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 7, 0);
1838 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1839 r600_init_atom(&rctx->vertex_buffer_state.atom, evergreen_fs_emit_vertex_buffers, 0, 0);
1840 r600_init_atom(&rctx->cs_vertex_buffer_state.atom, evergreen_cs_emit_vertex_buffers, 0, 0);
1841 r600_init_atom(&rctx->vs_constbuf_state.atom, evergreen_emit_vs_constant_buffers, 0, 0);
1842 r600_init_atom(&rctx->ps_constbuf_state.atom, evergreen_emit_ps_constant_buffers, 0, 0);
1843 r600_init_atom(&rctx->vs_samplers.views.atom, evergreen_emit_vs_sampler_views, 0, 0);
1844 r600_init_atom(&rctx->ps_samplers.views.atom, evergreen_emit_ps_sampler_views, 0, 0);
1845 r600_init_atom(&rctx->cs_shader_state.atom, evergreen_emit_cs_shader, 0, 0);
1846 r600_init_atom(&rctx->vs_samplers.atom_sampler, evergreen_emit_vs_sampler, 0, 0);
1847 r600_init_atom(&rctx->ps_samplers.atom_sampler, evergreen_emit_ps_sampler, 0, 0);
1848
1849 rctx->context.create_blend_state = evergreen_create_blend_state;
1850 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1851 rctx->context.create_fs_state = r600_create_shader_state_ps;
1852 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1853 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1854 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1855 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1856 rctx->context.create_vs_state = r600_create_shader_state_vs;
1857 rctx->context.bind_blend_state = r600_bind_blend_state;
1858 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1859 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1860 rctx->context.bind_fs_state = r600_bind_ps_shader;
1861 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1862 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1863 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1864 rctx->context.bind_vs_state = r600_bind_vs_shader;
1865 rctx->context.delete_blend_state = r600_delete_state;
1866 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1867 rctx->context.delete_fs_state = r600_delete_ps_shader;
1868 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1869 rctx->context.delete_sampler_state = r600_delete_sampler;
1870 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1871 rctx->context.delete_vs_state = r600_delete_vs_shader;
1872 rctx->context.set_blend_color = r600_set_blend_color;
1873 rctx->context.set_clip_state = evergreen_set_clip_state;
1874 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1875 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_views;
1876 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1877 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1878 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1879 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1880 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1881 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1882 rctx->context.set_index_buffer = r600_set_index_buffer;
1883 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_views;
1884 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1885 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1886 rctx->context.texture_barrier = r600_texture_barrier;
1887 rctx->context.create_stream_output_target = r600_create_so_target;
1888 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1889 rctx->context.set_stream_output_targets = r600_set_so_targets;
1890 evergreen_init_compute_state_functions(rctx);
1891 }
1892
1893 static void cayman_init_atom_start_cs(struct r600_context *rctx)
1894 {
1895 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1896
1897 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1898
1899 /* This must be first. */
1900 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1901 r600_store_value(cb, 0x80000000);
1902 r600_store_value(cb, 0x80000000);
1903
1904 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
1905 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
1906 /* always set the temp clauses */
1907 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
1908
1909 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
1910 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
1911 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
1912
1913 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
1914
1915 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
1916
1917 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
1918 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
1919 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
1920 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
1921 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
1922 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
1923 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
1924 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
1925 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
1926 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
1927 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
1928 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
1929 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
1930 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
1931
1932 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
1933 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
1934 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
1935
1936 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
1937 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
1938 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
1939
1940 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
1941
1942 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
1943
1944 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1945 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
1946 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
1947
1948 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
1949 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
1950 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
1951
1952 r600_store_context_reg(cb, CM_R_028804_DB_EQAA, 0x110000);
1953
1954 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
1955 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
1956 r600_store_value(cb, 0);
1957 r600_store_value(cb, 0);
1958 r600_store_value(cb, 0);
1959 r600_store_value(cb, 0);
1960 r600_store_value(cb, 0);
1961 r600_store_value(cb, 0);
1962 r600_store_value(cb, 0);
1963 r600_store_value(cb, 0);
1964 r600_store_value(cb, 0);
1965 r600_store_value(cb, 0);
1966 r600_store_value(cb, 0);
1967 r600_store_value(cb, 0);
1968 r600_store_value(cb, 0);
1969 r600_store_value(cb, 0);
1970 r600_store_value(cb, 0);
1971 r600_store_value(cb, 0);
1972 r600_store_value(cb, 0);
1973 r600_store_value(cb, 0);
1974 r600_store_value(cb, 0);
1975 r600_store_value(cb, 0);
1976 r600_store_value(cb, 0);
1977 r600_store_value(cb, 0);
1978 r600_store_value(cb, 0);
1979 r600_store_value(cb, 0);
1980 r600_store_value(cb, 0);
1981 r600_store_value(cb, 0);
1982 r600_store_value(cb, 0);
1983 r600_store_value(cb, 0);
1984 r600_store_value(cb, 0);
1985 r600_store_value(cb, 0);
1986 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
1987 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
1988 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
1989
1990 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
1991
1992 r600_store_context_reg_seq(cb, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
1993 r600_store_value(cb, ~0); /* CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 */
1994 r600_store_value(cb, ~0); /* CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 */
1995
1996 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
1997 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
1998 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
1999
2000 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2001
2002 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2003 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2004 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2005 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2006
2007 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2008 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2009
2010 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2011 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2012 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2013
2014 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2015 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2016 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2017 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2018
2019 r600_store_context_reg_seq(cb, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
2020 r600_store_value(cb, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2021 r600_store_value(cb, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2022
2023 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2024 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2025 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2026 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2027 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2028
2029 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2030 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2031 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2032
2033 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2034 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2035 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2036
2037 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2038 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2039 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2040
2041 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2042 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2043 if (rctx->screen->has_streamout) {
2044 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2045 }
2046
2047 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2048 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2049 }
2050
2051 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2052 {
2053 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2054 int ps_prio;
2055 int vs_prio;
2056 int gs_prio;
2057 int es_prio;
2058 int hs_prio, cs_prio, ls_prio;
2059 int num_ps_gprs;
2060 int num_vs_gprs;
2061 int num_gs_gprs;
2062 int num_es_gprs;
2063 int num_hs_gprs;
2064 int num_ls_gprs;
2065 int num_temp_gprs;
2066 int num_ps_threads;
2067 int num_vs_threads;
2068 int num_gs_threads;
2069 int num_es_threads;
2070 int num_hs_threads;
2071 int num_ls_threads;
2072 int num_ps_stack_entries;
2073 int num_vs_stack_entries;
2074 int num_gs_stack_entries;
2075 int num_es_stack_entries;
2076 int num_hs_stack_entries;
2077 int num_ls_stack_entries;
2078 enum radeon_family family;
2079 unsigned tmp;
2080
2081 if (rctx->chip_class == CAYMAN) {
2082 cayman_init_atom_start_cs(rctx);
2083 return;
2084 }
2085
2086 r600_init_command_buffer(cb, 256, EMIT_EARLY);
2087
2088 /* This must be first. */
2089 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2090 r600_store_value(cb, 0x80000000);
2091 r600_store_value(cb, 0x80000000);
2092
2093 family = rctx->family;
2094 ps_prio = 0;
2095 vs_prio = 1;
2096 gs_prio = 2;
2097 es_prio = 3;
2098 hs_prio = 0;
2099 ls_prio = 0;
2100 cs_prio = 0;
2101
2102 switch (family) {
2103 case CHIP_CEDAR:
2104 default:
2105 num_ps_gprs = 93;
2106 num_vs_gprs = 46;
2107 num_temp_gprs = 4;
2108 num_gs_gprs = 31;
2109 num_es_gprs = 31;
2110 num_hs_gprs = 23;
2111 num_ls_gprs = 23;
2112 num_ps_threads = 96;
2113 num_vs_threads = 16;
2114 num_gs_threads = 16;
2115 num_es_threads = 16;
2116 num_hs_threads = 16;
2117 num_ls_threads = 16;
2118 num_ps_stack_entries = 42;
2119 num_vs_stack_entries = 42;
2120 num_gs_stack_entries = 42;
2121 num_es_stack_entries = 42;
2122 num_hs_stack_entries = 42;
2123 num_ls_stack_entries = 42;
2124 break;
2125 case CHIP_REDWOOD:
2126 num_ps_gprs = 93;
2127 num_vs_gprs = 46;
2128 num_temp_gprs = 4;
2129 num_gs_gprs = 31;
2130 num_es_gprs = 31;
2131 num_hs_gprs = 23;
2132 num_ls_gprs = 23;
2133 num_ps_threads = 128;
2134 num_vs_threads = 20;
2135 num_gs_threads = 20;
2136 num_es_threads = 20;
2137 num_hs_threads = 20;
2138 num_ls_threads = 20;
2139 num_ps_stack_entries = 42;
2140 num_vs_stack_entries = 42;
2141 num_gs_stack_entries = 42;
2142 num_es_stack_entries = 42;
2143 num_hs_stack_entries = 42;
2144 num_ls_stack_entries = 42;
2145 break;
2146 case CHIP_JUNIPER:
2147 num_ps_gprs = 93;
2148 num_vs_gprs = 46;
2149 num_temp_gprs = 4;
2150 num_gs_gprs = 31;
2151 num_es_gprs = 31;
2152 num_hs_gprs = 23;
2153 num_ls_gprs = 23;
2154 num_ps_threads = 128;
2155 num_vs_threads = 20;
2156 num_gs_threads = 20;
2157 num_es_threads = 20;
2158 num_hs_threads = 20;
2159 num_ls_threads = 20;
2160 num_ps_stack_entries = 85;
2161 num_vs_stack_entries = 85;
2162 num_gs_stack_entries = 85;
2163 num_es_stack_entries = 85;
2164 num_hs_stack_entries = 85;
2165 num_ls_stack_entries = 85;
2166 break;
2167 case CHIP_CYPRESS:
2168 case CHIP_HEMLOCK:
2169 num_ps_gprs = 93;
2170 num_vs_gprs = 46;
2171 num_temp_gprs = 4;
2172 num_gs_gprs = 31;
2173 num_es_gprs = 31;
2174 num_hs_gprs = 23;
2175 num_ls_gprs = 23;
2176 num_ps_threads = 128;
2177 num_vs_threads = 20;
2178 num_gs_threads = 20;
2179 num_es_threads = 20;
2180 num_hs_threads = 20;
2181 num_ls_threads = 20;
2182 num_ps_stack_entries = 85;
2183 num_vs_stack_entries = 85;
2184 num_gs_stack_entries = 85;
2185 num_es_stack_entries = 85;
2186 num_hs_stack_entries = 85;
2187 num_ls_stack_entries = 85;
2188 break;
2189 case CHIP_PALM:
2190 num_ps_gprs = 93;
2191 num_vs_gprs = 46;
2192 num_temp_gprs = 4;
2193 num_gs_gprs = 31;
2194 num_es_gprs = 31;
2195 num_hs_gprs = 23;
2196 num_ls_gprs = 23;
2197 num_ps_threads = 96;
2198 num_vs_threads = 16;
2199 num_gs_threads = 16;
2200 num_es_threads = 16;
2201 num_hs_threads = 16;
2202 num_ls_threads = 16;
2203 num_ps_stack_entries = 42;
2204 num_vs_stack_entries = 42;
2205 num_gs_stack_entries = 42;
2206 num_es_stack_entries = 42;
2207 num_hs_stack_entries = 42;
2208 num_ls_stack_entries = 42;
2209 break;
2210 case CHIP_SUMO:
2211 num_ps_gprs = 93;
2212 num_vs_gprs = 46;
2213 num_temp_gprs = 4;
2214 num_gs_gprs = 31;
2215 num_es_gprs = 31;
2216 num_hs_gprs = 23;
2217 num_ls_gprs = 23;
2218 num_ps_threads = 96;
2219 num_vs_threads = 25;
2220 num_gs_threads = 25;
2221 num_es_threads = 25;
2222 num_hs_threads = 25;
2223 num_ls_threads = 25;
2224 num_ps_stack_entries = 42;
2225 num_vs_stack_entries = 42;
2226 num_gs_stack_entries = 42;
2227 num_es_stack_entries = 42;
2228 num_hs_stack_entries = 42;
2229 num_ls_stack_entries = 42;
2230 break;
2231 case CHIP_SUMO2:
2232 num_ps_gprs = 93;
2233 num_vs_gprs = 46;
2234 num_temp_gprs = 4;
2235 num_gs_gprs = 31;
2236 num_es_gprs = 31;
2237 num_hs_gprs = 23;
2238 num_ls_gprs = 23;
2239 num_ps_threads = 96;
2240 num_vs_threads = 25;
2241 num_gs_threads = 25;
2242 num_es_threads = 25;
2243 num_hs_threads = 25;
2244 num_ls_threads = 25;
2245 num_ps_stack_entries = 85;
2246 num_vs_stack_entries = 85;
2247 num_gs_stack_entries = 85;
2248 num_es_stack_entries = 85;
2249 num_hs_stack_entries = 85;
2250 num_ls_stack_entries = 85;
2251 break;
2252 case CHIP_BARTS:
2253 num_ps_gprs = 93;
2254 num_vs_gprs = 46;
2255 num_temp_gprs = 4;
2256 num_gs_gprs = 31;
2257 num_es_gprs = 31;
2258 num_hs_gprs = 23;
2259 num_ls_gprs = 23;
2260 num_ps_threads = 128;
2261 num_vs_threads = 20;
2262 num_gs_threads = 20;
2263 num_es_threads = 20;
2264 num_hs_threads = 20;
2265 num_ls_threads = 20;
2266 num_ps_stack_entries = 85;
2267 num_vs_stack_entries = 85;
2268 num_gs_stack_entries = 85;
2269 num_es_stack_entries = 85;
2270 num_hs_stack_entries = 85;
2271 num_ls_stack_entries = 85;
2272 break;
2273 case CHIP_TURKS:
2274 num_ps_gprs = 93;
2275 num_vs_gprs = 46;
2276 num_temp_gprs = 4;
2277 num_gs_gprs = 31;
2278 num_es_gprs = 31;
2279 num_hs_gprs = 23;
2280 num_ls_gprs = 23;
2281 num_ps_threads = 128;
2282 num_vs_threads = 20;
2283 num_gs_threads = 20;
2284 num_es_threads = 20;
2285 num_hs_threads = 20;
2286 num_ls_threads = 20;
2287 num_ps_stack_entries = 42;
2288 num_vs_stack_entries = 42;
2289 num_gs_stack_entries = 42;
2290 num_es_stack_entries = 42;
2291 num_hs_stack_entries = 42;
2292 num_ls_stack_entries = 42;
2293 break;
2294 case CHIP_CAICOS:
2295 num_ps_gprs = 93;
2296 num_vs_gprs = 46;
2297 num_temp_gprs = 4;
2298 num_gs_gprs = 31;
2299 num_es_gprs = 31;
2300 num_hs_gprs = 23;
2301 num_ls_gprs = 23;
2302 num_ps_threads = 128;
2303 num_vs_threads = 10;
2304 num_gs_threads = 10;
2305 num_es_threads = 10;
2306 num_hs_threads = 10;
2307 num_ls_threads = 10;
2308 num_ps_stack_entries = 42;
2309 num_vs_stack_entries = 42;
2310 num_gs_stack_entries = 42;
2311 num_es_stack_entries = 42;
2312 num_hs_stack_entries = 42;
2313 num_ls_stack_entries = 42;
2314 break;
2315 }
2316
2317 tmp = 0;
2318 switch (family) {
2319 case CHIP_CEDAR:
2320 case CHIP_PALM:
2321 case CHIP_SUMO:
2322 case CHIP_SUMO2:
2323 case CHIP_CAICOS:
2324 break;
2325 default:
2326 tmp |= S_008C00_VC_ENABLE(1);
2327 break;
2328 }
2329 tmp |= S_008C00_EXPORT_SRC_C(1);
2330 tmp |= S_008C00_CS_PRIO(cs_prio);
2331 tmp |= S_008C00_LS_PRIO(ls_prio);
2332 tmp |= S_008C00_HS_PRIO(hs_prio);
2333 tmp |= S_008C00_PS_PRIO(ps_prio);
2334 tmp |= S_008C00_VS_PRIO(vs_prio);
2335 tmp |= S_008C00_GS_PRIO(gs_prio);
2336 tmp |= S_008C00_ES_PRIO(es_prio);
2337
2338 /* enable dynamic GPR resource management */
2339 if (rctx->screen->info.drm_minor >= 7) {
2340 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2341 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2342 /* always set temp clauses */
2343 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2344 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2345 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2346 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2347 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2348 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2349 S_028838_PS_GPRS(0x1e) |
2350 S_028838_VS_GPRS(0x1e) |
2351 S_028838_GS_GPRS(0x1e) |
2352 S_028838_ES_GPRS(0x1e) |
2353 S_028838_HS_GPRS(0x1e) |
2354 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2355 } else {
2356 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2357 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2358
2359 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2360 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2361 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2362 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2363
2364 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2365 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2366 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2367
2368 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2369 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2370 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2371 }
2372
2373 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2374 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2375 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2376 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2377 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2378 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2379
2380 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2381 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2382 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2383
2384 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2385 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2386 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2387
2388 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2389 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2390 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2391
2392 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2393 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2394 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2395
2396 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2397 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2398
2399 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2400 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2401
2402 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2403
2404 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2405 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2406 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2407 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2408 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2409 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2410 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2411
2412 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2413 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2414 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2415 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2416 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2417
2418 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2419 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2420 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2421 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2422 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2423 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2424 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2425 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2426 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2427 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2428 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2429 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2430 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2431 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2432
2433 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2434 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2435 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2436
2437 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2438 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2439 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2440
2441 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2442
2443 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2444 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2445 r600_store_value(cb, 0);
2446 r600_store_value(cb, 0);
2447 r600_store_value(cb, 0);
2448 r600_store_value(cb, 0);
2449 r600_store_value(cb, 0);
2450 r600_store_value(cb, 0);
2451 r600_store_value(cb, 0);
2452 r600_store_value(cb, 0);
2453 r600_store_value(cb, 0);
2454 r600_store_value(cb, 0);
2455 r600_store_value(cb, 0);
2456 r600_store_value(cb, 0);
2457 r600_store_value(cb, 0);
2458 r600_store_value(cb, 0);
2459 r600_store_value(cb, 0);
2460 r600_store_value(cb, 0);
2461 r600_store_value(cb, 0);
2462 r600_store_value(cb, 0);
2463 r600_store_value(cb, 0);
2464 r600_store_value(cb, 0);
2465 r600_store_value(cb, 0);
2466 r600_store_value(cb, 0);
2467 r600_store_value(cb, 0);
2468 r600_store_value(cb, 0);
2469 r600_store_value(cb, 0);
2470 r600_store_value(cb, 0);
2471 r600_store_value(cb, 0);
2472 r600_store_value(cb, 0);
2473 r600_store_value(cb, 0);
2474 r600_store_value(cb, 0);
2475 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2476 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2477 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2478
2479 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2480
2481 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2482 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2483 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2484
2485 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2486 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2487 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2488
2489 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2490 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2491 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2492
2493 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2494 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2495 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2496
2497 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2498 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2499 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2500 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2501
2502 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2503
2504 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2505 r600_store_value(cb, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
2506 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2507
2508 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 5);
2509 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2510 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2511 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2512 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2513 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
2514
2515 r600_store_context_reg(cb, R_028C3C_PA_SC_AA_MASK, ~0);
2516
2517 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2518 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2519 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2520
2521 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2522 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2523 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2524
2525 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2526 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2527 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2528
2529 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2530 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2531 if (rctx->screen->has_streamout) {
2532 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2533 }
2534
2535 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2536 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2537 }
2538
2539 void evergreen_polygon_offset_update(struct r600_context *rctx)
2540 {
2541 struct r600_pipe_state state;
2542
2543 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2544 state.nregs = 0;
2545 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2546 float offset_units = rctx->rasterizer->offset_units;
2547 unsigned offset_db_fmt_cntl = 0, depth;
2548
2549 switch (rctx->framebuffer.zsbuf->format) {
2550 case PIPE_FORMAT_Z24X8_UNORM:
2551 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2552 depth = -24;
2553 offset_units *= 2.0f;
2554 break;
2555 case PIPE_FORMAT_Z32_FLOAT:
2556 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2557 depth = -23;
2558 offset_units *= 1.0f;
2559 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2560 break;
2561 case PIPE_FORMAT_Z16_UNORM:
2562 depth = -16;
2563 offset_units *= 4.0f;
2564 break;
2565 default:
2566 return;
2567 }
2568 /* XXX some of those reg can be computed with cso */
2569 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2570 r600_pipe_state_add_reg(&state,
2571 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2572 fui(rctx->rasterizer->offset_scale));
2573 r600_pipe_state_add_reg(&state,
2574 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2575 fui(offset_units));
2576 r600_pipe_state_add_reg(&state,
2577 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2578 fui(rctx->rasterizer->offset_scale));
2579 r600_pipe_state_add_reg(&state,
2580 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2581 fui(offset_units));
2582 r600_pipe_state_add_reg(&state,
2583 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2584 offset_db_fmt_cntl);
2585 r600_context_pipe_state_set(rctx, &state);
2586 }
2587 }
2588
2589 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2590 {
2591 struct r600_context *rctx = (struct r600_context *)ctx;
2592 struct r600_pipe_state *rstate = &shader->rstate;
2593 struct r600_shader *rshader = &shader->shader;
2594 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2595 int pos_index = -1, face_index = -1;
2596 int ninterp = 0;
2597 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2598 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2599 unsigned z_export = 0, stencil_export = 0;
2600
2601 rstate->nregs = 0;
2602
2603 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2604 for (i = 0; i < rshader->ninput; i++) {
2605 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2606 POSITION goes via GPRs from the SC so isn't counted */
2607 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2608 pos_index = i;
2609 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2610 face_index = i;
2611 else {
2612 ninterp++;
2613 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2614 have_linear = TRUE;
2615 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2616 have_perspective = TRUE;
2617 if (rshader->input[i].centroid)
2618 have_centroid = TRUE;
2619 }
2620
2621 sid = rshader->input[i].spi_sid;
2622
2623 if (sid) {
2624
2625 tmp = S_028644_SEMANTIC(sid);
2626
2627 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2628 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2629 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2630 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2631 tmp |= S_028644_FLAT_SHADE(1);
2632 }
2633
2634 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2635 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2636 tmp |= S_028644_PT_SPRITE_TEX(1);
2637 }
2638
2639 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2640 tmp);
2641
2642 idx++;
2643 }
2644 }
2645
2646 for (i = 0; i < rshader->noutput; i++) {
2647 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2648 z_export = 1;
2649 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2650 stencil_export = 1;
2651 }
2652 if (rshader->uses_kill)
2653 db_shader_control |= S_02880C_KILL_ENABLE(1);
2654
2655 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2656 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
2657
2658 exports_ps = 0;
2659 for (i = 0; i < rshader->noutput; i++) {
2660 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2661 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2662 exports_ps |= 1;
2663 }
2664
2665 num_cout = rshader->nr_ps_color_exports;
2666
2667 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2668 if (!exports_ps) {
2669 /* always at least export 1 component per pixel */
2670 exports_ps = 2;
2671 }
2672 shader->nr_ps_color_outputs = num_cout;
2673 if (ninterp == 0) {
2674 ninterp = 1;
2675 have_perspective = TRUE;
2676 }
2677
2678 if (!have_perspective && !have_linear)
2679 have_perspective = TRUE;
2680
2681 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2682 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2683 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2684 spi_input_z = 0;
2685 if (pos_index != -1) {
2686 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2687 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2688 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2689 spi_input_z |= 1;
2690 }
2691
2692 spi_ps_in_control_1 = 0;
2693 if (face_index != -1) {
2694 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2695 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2696 }
2697
2698 spi_baryc_cntl = 0;
2699 if (have_perspective)
2700 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2701 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2702 if (have_linear)
2703 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2704 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2705
2706 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2707 spi_ps_in_control_0);
2708 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2709 spi_ps_in_control_1);
2710 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2711 0);
2712 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2713 r600_pipe_state_add_reg(rstate,
2714 R_0286E0_SPI_BARYC_CNTL,
2715 spi_baryc_cntl);
2716
2717 r600_pipe_state_add_reg_bo(rstate,
2718 R_028840_SQ_PGM_START_PS,
2719 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2720 shader->bo, RADEON_USAGE_READ);
2721 r600_pipe_state_add_reg(rstate,
2722 R_028844_SQ_PGM_RESOURCES_PS,
2723 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2724 S_028844_PRIME_CACHE_ON_DRAW(1) |
2725 S_028844_STACK_SIZE(rshader->bc.nstack));
2726 r600_pipe_state_add_reg(rstate,
2727 R_02884C_SQ_PGM_EXPORTS_PS,
2728 exports_ps);
2729
2730 shader->db_shader_control = db_shader_control;
2731 shader->ps_depth_export = z_export | stencil_export;
2732
2733 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2734 if (rctx->rasterizer)
2735 shader->flatshade = rctx->rasterizer->flatshade;
2736 }
2737
2738 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2739 {
2740 struct r600_context *rctx = (struct r600_context *)ctx;
2741 struct r600_pipe_state *rstate = &shader->rstate;
2742 struct r600_shader *rshader = &shader->shader;
2743 unsigned spi_vs_out_id[10] = {};
2744 unsigned i, tmp, nparams = 0;
2745
2746 /* clear previous register */
2747 rstate->nregs = 0;
2748
2749 for (i = 0; i < rshader->noutput; i++) {
2750 if (rshader->output[i].spi_sid) {
2751 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2752 spi_vs_out_id[nparams / 4] |= tmp;
2753 nparams++;
2754 }
2755 }
2756
2757 for (i = 0; i < 10; i++) {
2758 r600_pipe_state_add_reg(rstate,
2759 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2760 spi_vs_out_id[i]);
2761 }
2762
2763 /* Certain attributes (position, psize, etc.) don't count as params.
2764 * VS is required to export at least one param and r600_shader_from_tgsi()
2765 * takes care of adding a dummy export.
2766 */
2767 if (nparams < 1)
2768 nparams = 1;
2769
2770 r600_pipe_state_add_reg(rstate,
2771 R_0286C4_SPI_VS_OUT_CONFIG,
2772 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2773 r600_pipe_state_add_reg(rstate,
2774 R_028860_SQ_PGM_RESOURCES_VS,
2775 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2776 S_028860_STACK_SIZE(rshader->bc.nstack));
2777 r600_pipe_state_add_reg_bo(rstate,
2778 R_02885C_SQ_PGM_START_VS,
2779 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2780 shader->bo, RADEON_USAGE_READ);
2781
2782 shader->pa_cl_vs_out_cntl =
2783 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2784 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2785 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2786 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2787 }
2788
2789 void evergreen_fetch_shader(struct pipe_context *ctx,
2790 struct r600_vertex_element *ve)
2791 {
2792 struct r600_context *rctx = (struct r600_context *)ctx;
2793 struct r600_pipe_state *rstate = &ve->rstate;
2794 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2795 rstate->nregs = 0;
2796 r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
2797 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2798 ve->fetch_shader, RADEON_USAGE_READ);
2799 }
2800
2801 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2802 {
2803 struct pipe_depth_stencil_alpha_state dsa = {{0}};
2804
2805 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2806 }
2807
2808 void evergreen_update_dual_export_state(struct r600_context * rctx)
2809 {
2810 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2811 !rctx->ps_shader->current->ps_depth_export;
2812
2813 unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
2814 V_02880C_EXPORT_DB_FULL;
2815
2816 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2817 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
2818 S_02880C_DB_SOURCE_FORMAT(db_source_format);
2819
2820 if (db_shader_control != rctx->db_shader_control) {
2821 struct r600_pipe_state rstate;
2822
2823 rctx->db_shader_control = db_shader_control;
2824
2825 rstate.nregs = 0;
2826 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2827 r600_context_pipe_state_set(rctx, &rstate);
2828 }
2829 }