2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
35 static inline unsigned evergreen_array_mode(unsigned mode
)
38 case RADEON_SURF_MODE_LINEAR_ALIGNED
: return V_028C70_ARRAY_LINEAR_ALIGNED
;
40 case RADEON_SURF_MODE_1D
: return V_028C70_ARRAY_1D_TILED_THIN1
;
42 case RADEON_SURF_MODE_2D
: return V_028C70_ARRAY_2D_TILED_THIN1
;
44 case RADEON_SURF_MODE_LINEAR
: return V_028C70_ARRAY_LINEAR_GENERAL
;
48 static uint32_t eg_num_banks(uint32_t nbanks
)
64 static unsigned eg_tile_split(unsigned tile_split
)
67 case 64: tile_split
= 0; break;
68 case 128: tile_split
= 1; break;
69 case 256: tile_split
= 2; break;
70 case 512: tile_split
= 3; break;
72 case 1024: tile_split
= 4; break;
73 case 2048: tile_split
= 5; break;
74 case 4096: tile_split
= 6; break;
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect
)
81 switch (macro_tile_aspect
) {
83 case 1: macro_tile_aspect
= 0; break;
84 case 2: macro_tile_aspect
= 1; break;
85 case 4: macro_tile_aspect
= 2; break;
86 case 8: macro_tile_aspect
= 3; break;
88 return macro_tile_aspect
;
91 static unsigned eg_bank_wh(unsigned bankwh
)
95 case 1: bankwh
= 0; break;
96 case 2: bankwh
= 1; break;
97 case 4: bankwh
= 2; break;
98 case 8: bankwh
= 3; break;
103 static uint32_t r600_translate_blend_function(int blend_func
)
105 switch (blend_func
) {
107 return V_028780_COMB_DST_PLUS_SRC
;
108 case PIPE_BLEND_SUBTRACT
:
109 return V_028780_COMB_SRC_MINUS_DST
;
110 case PIPE_BLEND_REVERSE_SUBTRACT
:
111 return V_028780_COMB_DST_MINUS_SRC
;
113 return V_028780_COMB_MIN_DST_SRC
;
115 return V_028780_COMB_MAX_DST_SRC
;
117 R600_ERR("Unknown blend function %d\n", blend_func
);
124 static uint32_t r600_translate_blend_factor(int blend_fact
)
126 switch (blend_fact
) {
127 case PIPE_BLENDFACTOR_ONE
:
128 return V_028780_BLEND_ONE
;
129 case PIPE_BLENDFACTOR_SRC_COLOR
:
130 return V_028780_BLEND_SRC_COLOR
;
131 case PIPE_BLENDFACTOR_SRC_ALPHA
:
132 return V_028780_BLEND_SRC_ALPHA
;
133 case PIPE_BLENDFACTOR_DST_ALPHA
:
134 return V_028780_BLEND_DST_ALPHA
;
135 case PIPE_BLENDFACTOR_DST_COLOR
:
136 return V_028780_BLEND_DST_COLOR
;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
139 case PIPE_BLENDFACTOR_CONST_COLOR
:
140 return V_028780_BLEND_CONST_COLOR
;
141 case PIPE_BLENDFACTOR_CONST_ALPHA
:
142 return V_028780_BLEND_CONST_ALPHA
;
143 case PIPE_BLENDFACTOR_ZERO
:
144 return V_028780_BLEND_ZERO
;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR
;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA
;
157 case PIPE_BLENDFACTOR_SRC1_COLOR
:
158 return V_028780_BLEND_SRC1_COLOR
;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
160 return V_028780_BLEND_SRC1_ALPHA
;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
162 return V_028780_BLEND_INV_SRC1_COLOR
;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
164 return V_028780_BLEND_INV_SRC1_ALPHA
;
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
173 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
177 case PIPE_TEXTURE_1D
:
178 return V_030000_SQ_TEX_DIM_1D
;
179 case PIPE_TEXTURE_1D_ARRAY
:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
181 case PIPE_TEXTURE_2D
:
182 case PIPE_TEXTURE_RECT
:
183 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_MSAA
:
184 V_030000_SQ_TEX_DIM_2D
;
185 case PIPE_TEXTURE_2D_ARRAY
:
186 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
187 V_030000_SQ_TEX_DIM_2D_ARRAY
;
188 case PIPE_TEXTURE_3D
:
189 return V_030000_SQ_TEX_DIM_3D
;
190 case PIPE_TEXTURE_CUBE
:
191 case PIPE_TEXTURE_CUBE_ARRAY
:
192 return V_030000_SQ_TEX_DIM_CUBEMAP
;
196 static uint32_t r600_translate_dbformat(enum pipe_format format
)
199 case PIPE_FORMAT_Z16_UNORM
:
200 return V_028040_Z_16
;
201 case PIPE_FORMAT_Z24X8_UNORM
:
202 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
203 case PIPE_FORMAT_X8Z24_UNORM
:
204 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
205 return V_028040_Z_24
;
206 case PIPE_FORMAT_Z32_FLOAT
:
207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
208 return V_028040_Z_32_FLOAT
;
214 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
216 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip
, enum pipe_format format
)
221 return r600_translate_colorformat(chip
, format
) != ~0U &&
222 r600_translate_colorswap(format
) != ~0U;
225 static bool r600_is_zs_format_supported(enum pipe_format format
)
227 return r600_translate_dbformat(format
) != ~0U;
230 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
231 enum pipe_format format
,
232 enum pipe_texture_target target
,
233 unsigned sample_count
,
236 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
239 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
240 R600_ERR("r600: unsupported texture type %d\n", target
);
244 if (!util_format_is_supported(format
, usage
))
247 if (sample_count
> 1) {
248 if (!rscreen
->has_msaa
)
251 switch (sample_count
) {
261 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
262 if (target
== PIPE_BUFFER
) {
263 if (r600_is_vertex_format_supported(format
))
264 retval
|= PIPE_BIND_SAMPLER_VIEW
;
266 if (r600_is_sampler_format_supported(screen
, format
))
267 retval
|= PIPE_BIND_SAMPLER_VIEW
;
271 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
272 PIPE_BIND_DISPLAY_TARGET
|
275 PIPE_BIND_BLENDABLE
)) &&
276 r600_is_colorbuffer_format_supported(rscreen
->b
.chip_class
, format
)) {
278 (PIPE_BIND_RENDER_TARGET
|
279 PIPE_BIND_DISPLAY_TARGET
|
282 if (!util_format_is_pure_integer(format
) &&
283 !util_format_is_depth_or_stencil(format
))
284 retval
|= usage
& PIPE_BIND_BLENDABLE
;
287 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
288 r600_is_zs_format_supported(format
)) {
289 retval
|= PIPE_BIND_DEPTH_STENCIL
;
292 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
293 r600_is_vertex_format_supported(format
)) {
294 retval
|= PIPE_BIND_VERTEX_BUFFER
;
297 if (usage
& PIPE_BIND_TRANSFER_READ
)
298 retval
|= PIPE_BIND_TRANSFER_READ
;
299 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
300 retval
|= PIPE_BIND_TRANSFER_WRITE
;
302 return retval
== usage
;
305 static void *evergreen_create_blend_state_mode(struct pipe_context
*ctx
,
306 const struct pipe_blend_state
*state
, int mode
)
308 uint32_t color_control
= 0, target_mask
= 0;
309 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
315 r600_init_command_buffer(&blend
->buffer
, 20);
316 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
318 if (state
->logicop_enable
) {
319 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
321 color_control
|= (0xcc << 16);
323 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
324 if (state
->independent_blend_enable
) {
325 for (int i
= 0; i
< 8; i
++) {
326 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
329 for (int i
= 0; i
< 8; i
++) {
330 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
334 /* only have dual source on MRT0 */
335 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
336 blend
->cb_target_mask
= target_mask
;
337 blend
->alpha_to_one
= state
->alpha_to_one
;
340 color_control
|= S_028808_MODE(mode
);
342 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
345 r600_store_context_reg(&blend
->buffer
, R_028808_CB_COLOR_CONTROL
, color_control
);
346 r600_store_context_reg(&blend
->buffer
, R_028B70_DB_ALPHA_TO_MASK
,
347 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
348 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
349 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
350 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
351 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
352 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
354 /* Copy over the dwords set so far into buffer_no_blend.
355 * Only the CB_BLENDi_CONTROL registers must be set after this. */
356 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
357 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
359 for (int i
= 0; i
< 8; i
++) {
360 /* state->rt entries > 0 only written if independent blending */
361 const int j
= state
->independent_blend_enable
? i
: 0;
363 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
364 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
365 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
366 unsigned eqA
= state
->rt
[j
].alpha_func
;
367 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
368 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
371 r600_store_value(&blend
->buffer_no_blend
, 0);
373 if (!state
->rt
[j
].blend_enable
) {
374 r600_store_value(&blend
->buffer
, 0);
378 bc
|= S_028780_BLEND_CONTROL_ENABLE(1);
379 bc
|= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
380 bc
|= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
381 bc
|= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
383 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
384 bc
|= S_028780_SEPARATE_ALPHA_BLEND(1);
385 bc
|= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
386 bc
|= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
387 bc
|= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
389 r600_store_value(&blend
->buffer
, bc
);
394 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
395 const struct pipe_blend_state
*state
)
398 return evergreen_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
401 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
402 const struct pipe_depth_stencil_alpha_state
*state
)
404 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
405 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
411 r600_init_command_buffer(&dsa
->buffer
, 3);
413 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
414 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
415 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
416 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
417 dsa
->zwritemask
= state
->depth
.writemask
;
419 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
420 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
421 S_028800_ZFUNC(state
->depth
.func
);
424 if (state
->stencil
[0].enabled
) {
425 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
426 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
427 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
428 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
429 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
431 if (state
->stencil
[1].enabled
) {
432 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
433 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
434 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
435 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
436 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
441 alpha_test_control
= 0;
443 if (state
->alpha
.enabled
) {
444 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
445 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
446 alpha_ref
= fui(state
->alpha
.ref_value
);
448 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
449 dsa
->alpha_ref
= alpha_ref
;
452 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
456 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
457 const struct pipe_rasterizer_state
*state
)
459 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
460 unsigned tmp
, spi_interp
;
461 float psize_min
, psize_max
;
462 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
468 r600_init_command_buffer(&rs
->buffer
, 30);
470 rs
->flatshade
= state
->flatshade
;
471 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
472 rs
->two_side
= state
->light_twoside
;
473 rs
->clip_plane_enable
= state
->clip_plane_enable
;
474 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
475 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
476 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
477 rs
->pa_cl_clip_cntl
=
478 S_028810_PS_UCP_MODE(3) |
479 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
480 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
481 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
482 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
483 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
);
484 rs
->multisample_enable
= state
->multisample
;
487 rs
->offset_units
= state
->offset_units
;
488 rs
->offset_scale
= state
->offset_scale
* 16.0f
;
489 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
491 if (state
->point_size_per_vertex
) {
492 psize_min
= util_get_min_point_size(state
);
495 /* Force the point size to be as if the vertex output was disabled. */
496 psize_min
= state
->point_size
;
497 psize_max
= state
->point_size
;
500 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
501 if (state
->sprite_coord_enable
) {
502 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
503 S_0286D4_PNT_SPRITE_OVRD_X(2) |
504 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
505 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
506 S_0286D4_PNT_SPRITE_OVRD_W(1);
507 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
508 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
512 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
513 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
514 tmp
= r600_pack_float_12p4(state
->point_size
/2);
515 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
516 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
517 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
518 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
519 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
520 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
521 S_028A08_WIDTH((unsigned)(state
->line_width
* 8)));
523 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
524 r600_store_context_reg(&rs
->buffer
, R_028A48_PA_SC_MODE_CNTL_0
,
525 S_028A48_MSAA_ENABLE(state
->multisample
) |
526 S_028A48_VPORT_SCISSOR_ENABLE(state
->scissor
) |
527 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
));
529 if (rctx
->b
.chip_class
== CAYMAN
) {
530 r600_store_context_reg(&rs
->buffer
, CM_R_028BE4_PA_SU_VTX_CNTL
,
531 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
532 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
534 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
535 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
536 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
539 r600_store_context_reg(&rs
->buffer
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
540 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
,
541 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
542 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
543 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
544 S_028814_FACE(!state
->front_ccw
) |
545 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
546 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
547 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
548 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
549 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
550 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
551 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
555 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
556 const struct pipe_sampler_state
*state
)
558 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
559 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
565 ss
->border_color_use
= sampler_state_needs_border_color(state
);
567 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
568 ss
->tex_sampler_words
[0] =
569 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
570 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
571 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
572 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
573 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
574 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
575 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
576 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
577 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
578 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
579 ss
->tex_sampler_words
[1] =
580 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
581 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8));
582 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
583 ss
->tex_sampler_words
[2] =
584 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
585 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
588 if (ss
->border_color_use
) {
589 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
594 static struct pipe_sampler_view
*
595 texture_buffer_sampler_view(struct r600_context
*rctx
,
596 struct r600_pipe_sampler_view
*view
,
597 unsigned width0
, unsigned height0
)
600 struct r600_texture
*tmp
= (struct r600_texture
*)view
->base
.texture
;
602 int stride
= util_format_get_blocksize(view
->base
.format
);
603 unsigned format
, num_format
, format_comp
, endian
;
604 unsigned swizzle_res
;
605 unsigned char swizzle
[4];
606 const struct util_format_description
*desc
;
607 unsigned offset
= view
->base
.u
.buf
.first_element
* stride
;
608 unsigned size
= (view
->base
.u
.buf
.last_element
- view
->base
.u
.buf
.first_element
+ 1) * stride
;
610 swizzle
[0] = view
->base
.swizzle_r
;
611 swizzle
[1] = view
->base
.swizzle_g
;
612 swizzle
[2] = view
->base
.swizzle_b
;
613 swizzle
[3] = view
->base
.swizzle_a
;
615 r600_vertex_data_type(view
->base
.format
,
616 &format
, &num_format
, &format_comp
,
619 desc
= util_format_description(view
->base
.format
);
621 swizzle_res
= r600_get_swizzle_combined(desc
->swizzle
, swizzle
, TRUE
);
623 va
= tmp
->resource
.gpu_address
+ offset
;
624 view
->tex_resource
= &tmp
->resource
;
626 view
->skip_mip_address_reloc
= true;
627 view
->tex_resource_words
[0] = va
;
628 view
->tex_resource_words
[1] = size
- 1;
629 view
->tex_resource_words
[2] = S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
630 S_030008_STRIDE(stride
) |
631 S_030008_DATA_FORMAT(format
) |
632 S_030008_NUM_FORMAT_ALL(num_format
) |
633 S_030008_FORMAT_COMP_ALL(format_comp
) |
634 S_030008_ENDIAN_SWAP(endian
);
635 view
->tex_resource_words
[3] = swizzle_res
;
637 * in theory dword 4 is for number of elements, for use with resinfo,
638 * but it seems to utterly fail to work, the amd gpu shader analyser
639 * uses a const buffer to store the element sizes for buffer txq
641 view
->tex_resource_words
[4] = 0;
642 view
->tex_resource_words
[5] = view
->tex_resource_words
[6] = 0;
643 view
->tex_resource_words
[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
);
645 if (tmp
->resource
.gpu_address
)
646 LIST_ADDTAIL(&view
->list
, &rctx
->b
.texture_buffers
);
650 struct pipe_sampler_view
*
651 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
652 struct pipe_resource
*texture
,
653 const struct pipe_sampler_view
*state
,
654 unsigned width0
, unsigned height0
,
655 unsigned force_level
)
657 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
658 struct r600_screen
*rscreen
= (struct r600_screen
*)ctx
->screen
;
659 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
660 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
661 unsigned format
, endian
;
662 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
663 unsigned char swizzle
[4], array_mode
= 0, non_disp_tiling
= 0;
664 unsigned height
, depth
, width
;
665 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
, fmask_bankh
;
666 enum pipe_format pipe_format
= state
->format
;
667 struct radeon_surf_level
*surflevel
;
668 unsigned base_level
, first_level
, last_level
;
674 /* initialize base object */
676 view
->base
.texture
= NULL
;
677 pipe_reference(NULL
, &texture
->reference
);
678 view
->base
.texture
= texture
;
679 view
->base
.reference
.count
= 1;
680 view
->base
.context
= ctx
;
682 if (texture
->target
== PIPE_BUFFER
)
683 return texture_buffer_sampler_view(rctx
, view
, width0
, height0
);
685 swizzle
[0] = state
->swizzle_r
;
686 swizzle
[1] = state
->swizzle_g
;
687 swizzle
[2] = state
->swizzle_b
;
688 swizzle
[3] = state
->swizzle_a
;
690 tile_split
= tmp
->surface
.tile_split
;
691 surflevel
= tmp
->surface
.level
;
693 /* Texturing with separate depth and stencil. */
694 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
695 switch (pipe_format
) {
696 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
697 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
699 case PIPE_FORMAT_X8Z24_UNORM
:
700 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
701 /* Z24 is always stored like this. */
702 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
704 case PIPE_FORMAT_X24S8_UINT
:
705 case PIPE_FORMAT_S8X24_UINT
:
706 case PIPE_FORMAT_X32_S8X24_UINT
:
707 pipe_format
= PIPE_FORMAT_S8_UINT
;
708 tile_split
= tmp
->surface
.stencil_tile_split
;
709 surflevel
= tmp
->surface
.stencil_level
;
715 format
= r600_translate_texformat(ctx
->screen
, pipe_format
,
717 &word4
, &yuv_format
);
718 assert(format
!= ~0);
724 endian
= r600_colorformat_endian_swap(format
);
727 first_level
= state
->u
.tex
.first_level
;
728 last_level
= state
->u
.tex
.last_level
;
731 depth
= texture
->depth0
;
734 base_level
= force_level
;
737 width
= u_minify(width
, force_level
);
738 height
= u_minify(height
, force_level
);
739 depth
= u_minify(depth
, force_level
);
742 pitch
= surflevel
[base_level
].nblk_x
* util_format_get_blockwidth(pipe_format
);
743 non_disp_tiling
= tmp
->non_disp_tiling
;
745 switch (surflevel
[base_level
].mode
) {
746 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
747 array_mode
= V_028C70_ARRAY_LINEAR_ALIGNED
;
749 case RADEON_SURF_MODE_2D
:
750 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
752 case RADEON_SURF_MODE_1D
:
753 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
755 case RADEON_SURF_MODE_LINEAR
:
757 array_mode
= V_028C70_ARRAY_LINEAR_GENERAL
;
760 macro_aspect
= tmp
->surface
.mtilea
;
761 bankw
= tmp
->surface
.bankw
;
762 bankh
= tmp
->surface
.bankh
;
763 tile_split
= eg_tile_split(tile_split
);
764 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
765 bankw
= eg_bank_wh(bankw
);
766 bankh
= eg_bank_wh(bankh
);
767 fmask_bankh
= eg_bank_wh(tmp
->fmask
.bank_height
);
769 /* 128 bit formats require tile type = 1 */
770 if (rscreen
->b
.chip_class
== CAYMAN
) {
771 if (util_format_get_blocksize(pipe_format
) >= 16)
774 nbanks
= eg_num_banks(rscreen
->b
.tiling_info
.num_banks
);
776 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
778 depth
= texture
->array_size
;
779 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
780 depth
= texture
->array_size
;
781 } else if (texture
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
782 depth
= texture
->array_size
/ 6;
784 va
= tmp
->resource
.gpu_address
;
786 view
->tex_resource
= &tmp
->resource
;
787 view
->tex_resource_words
[0] = (S_030000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
788 S_030000_PITCH((pitch
/ 8) - 1) |
789 S_030000_TEX_WIDTH(width
- 1));
790 if (rscreen
->b
.chip_class
== CAYMAN
)
791 view
->tex_resource_words
[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
793 view
->tex_resource_words
[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
794 view
->tex_resource_words
[1] = (S_030004_TEX_HEIGHT(height
- 1) |
795 S_030004_TEX_DEPTH(depth
- 1) |
796 S_030004_ARRAY_MODE(array_mode
));
797 view
->tex_resource_words
[2] = (surflevel
[base_level
].offset
+ va
) >> 8;
799 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
800 if (texture
->nr_samples
> 1 && rscreen
->has_compressed_msaa_texturing
) {
802 /* disable FMASK (0 = disabled) */
803 view
->tex_resource_words
[3] = 0;
804 view
->skip_mip_address_reloc
= true;
806 /* FMASK should be in MIP_ADDRESS for multisample textures */
807 view
->tex_resource_words
[3] = (tmp
->fmask
.offset
+ va
) >> 8;
809 } else if (last_level
&& texture
->nr_samples
<= 1) {
810 view
->tex_resource_words
[3] = (surflevel
[1].offset
+ va
) >> 8;
812 view
->tex_resource_words
[3] = (surflevel
[base_level
].offset
+ va
) >> 8;
815 view
->tex_resource_words
[4] = (word4
|
816 S_030010_ENDIAN_SWAP(endian
));
817 view
->tex_resource_words
[5] = S_030014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
818 S_030014_LAST_ARRAY(state
->u
.tex
.last_layer
);
819 view
->tex_resource_words
[6] = S_030018_TILE_SPLIT(tile_split
);
821 if (texture
->nr_samples
> 1) {
822 unsigned log_samples
= util_logbase2(texture
->nr_samples
);
823 if (rscreen
->b
.chip_class
== CAYMAN
) {
824 view
->tex_resource_words
[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples
);
826 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
827 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(log_samples
);
828 view
->tex_resource_words
[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh
);
830 view
->tex_resource_words
[4] |= S_030010_BASE_LEVEL(first_level
);
831 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(last_level
);
832 /* aniso max 16 samples */
833 view
->tex_resource_words
[6] |= S_030018_MAX_ANISO(4);
836 view
->tex_resource_words
[7] = S_03001C_DATA_FORMAT(format
) |
837 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
) |
838 S_03001C_BANK_WIDTH(bankw
) |
839 S_03001C_BANK_HEIGHT(bankh
) |
840 S_03001C_MACRO_TILE_ASPECT(macro_aspect
) |
841 S_03001C_NUM_BANKS(nbanks
) |
842 S_03001C_DEPTH_SAMPLE_ORDER(tmp
->is_depth
&& !tmp
->is_flushing_texture
);
846 static struct pipe_sampler_view
*
847 evergreen_create_sampler_view(struct pipe_context
*ctx
,
848 struct pipe_resource
*tex
,
849 const struct pipe_sampler_view
*state
)
851 return evergreen_create_sampler_view_custom(ctx
, tex
, state
,
852 tex
->width0
, tex
->height0
, 0);
855 static void evergreen_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
857 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
858 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
860 r600_write_context_reg_seq(cs
, R_0285BC_PA_CL_UCP0_X
, 6*4);
861 radeon_emit_array(cs
, (unsigned*)state
, 6*4);
864 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
865 const struct pipe_poly_stipple
*state
)
869 static void evergreen_get_scissor_rect(struct r600_context
*rctx
,
870 unsigned tl_x
, unsigned tl_y
, unsigned br_x
, unsigned br_y
,
871 uint32_t *tl
, uint32_t *br
)
873 /* EG hw workaround */
879 /* cayman hw workaround */
880 if (rctx
->b
.chip_class
== CAYMAN
) {
881 if (br_x
== 1 && br_y
== 1)
885 *tl
= S_028240_TL_X(tl_x
) | S_028240_TL_Y(tl_y
);
886 *br
= S_028244_BR_X(br_x
) | S_028244_BR_Y(br_y
);
889 static void evergreen_set_scissor_states(struct pipe_context
*ctx
,
891 unsigned num_scissors
,
892 const struct pipe_scissor_state
*state
)
894 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
897 for (i
= start_slot
; i
< start_slot
+ num_scissors
; i
++) {
898 rctx
->scissor
[i
].scissor
= state
[i
- start_slot
];
899 r600_mark_atom_dirty(rctx
, &rctx
->scissor
[i
].atom
);
903 static void evergreen_emit_scissor_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
905 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
906 struct r600_scissor_state
*rstate
= (struct r600_scissor_state
*)atom
;
907 struct pipe_scissor_state
*state
= &rstate
->scissor
;
908 unsigned offset
= rstate
->idx
* 4 * 2;
911 evergreen_get_scissor_rect(rctx
, state
->minx
, state
->miny
, state
->maxx
, state
->maxy
, &tl
, &br
);
913 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+ offset
, 2);
919 * This function intializes the CB* register values for RATs. It is meant
920 * to be used for 1D aligned buffers that do not have an associated
923 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
924 struct r600_surface
*surf
)
926 struct pipe_resource
*pipe_buffer
= surf
->base
.texture
;
927 unsigned format
= r600_translate_colorformat(rctx
->b
.chip_class
,
929 unsigned endian
= r600_colorformat_endian_swap(format
);
930 unsigned swap
= r600_translate_colorswap(surf
->base
.format
);
931 unsigned block_size
=
932 align(util_format_get_blocksize(pipe_buffer
->format
), 4);
933 unsigned pitch_alignment
=
934 MAX2(64, rctx
->screen
->b
.tiling_info
.group_bytes
/ block_size
);
935 unsigned pitch
= align(pipe_buffer
->width0
, pitch_alignment
);
937 /* XXX: This is copied from evergreen_init_color_surface(). I don't
938 * know why this is necessary.
940 if (pipe_buffer
->usage
== PIPE_USAGE_STAGING
) {
941 endian
= ENDIAN_NONE
;
944 surf
->cb_color_base
= r600_resource(pipe_buffer
)->gpu_address
>> 8;
946 surf
->cb_color_pitch
= (pitch
/ 8) - 1;
948 surf
->cb_color_slice
= 0;
950 surf
->cb_color_view
= 0;
952 surf
->cb_color_info
=
953 S_028C70_ENDIAN(endian
)
954 | S_028C70_FORMAT(format
)
955 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
)
956 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT
)
957 | S_028C70_COMP_SWAP(swap
)
958 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
959 * are using NUMBER_UINT */
963 surf
->cb_color_attrib
= S_028C74_NON_DISP_TILING_ORDER(1);
965 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
967 surf
->cb_color_dim
= pipe_buffer
->width0
;
969 /* Set the buffer range the GPU will have access to: */
970 util_range_add(&r600_resource(pipe_buffer
)->valid_buffer_range
,
971 0, pipe_buffer
->width0
);
973 surf
->cb_color_fmask
= surf
->cb_color_base
;
974 surf
->cb_color_fmask_slice
= 0;
977 void evergreen_init_color_surface(struct r600_context
*rctx
,
978 struct r600_surface
*surf
)
980 struct r600_screen
*rscreen
= rctx
->screen
;
981 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
982 unsigned level
= surf
->base
.u
.tex
.level
;
983 unsigned pitch
, slice
;
984 unsigned color_info
, color_attrib
, color_dim
= 0, color_view
;
985 unsigned format
, swap
, ntype
, endian
;
986 uint64_t offset
, base_offset
;
987 unsigned non_disp_tiling
, macro_aspect
, tile_split
, bankh
, bankw
, fmask_bankh
, nbanks
;
988 const struct util_format_description
*desc
;
990 bool blend_clamp
= 0, blend_bypass
= 0;
992 offset
= rtex
->surface
.level
[level
].offset
;
993 if (rtex
->surface
.level
[level
].mode
== RADEON_SURF_MODE_LINEAR
) {
994 assert(surf
->base
.u
.tex
.first_layer
== surf
->base
.u
.tex
.last_layer
);
995 offset
+= rtex
->surface
.level
[level
].slice_size
*
996 surf
->base
.u
.tex
.first_layer
;
999 color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1000 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1002 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1003 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1008 switch (rtex
->surface
.level
[level
].mode
) {
1009 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1010 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1011 non_disp_tiling
= 1;
1013 case RADEON_SURF_MODE_1D
:
1014 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1
);
1015 non_disp_tiling
= rtex
->non_disp_tiling
;
1017 case RADEON_SURF_MODE_2D
:
1018 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1
);
1019 non_disp_tiling
= rtex
->non_disp_tiling
;
1021 case RADEON_SURF_MODE_LINEAR
:
1023 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL
);
1024 non_disp_tiling
= 1;
1027 tile_split
= rtex
->surface
.tile_split
;
1028 macro_aspect
= rtex
->surface
.mtilea
;
1029 bankw
= rtex
->surface
.bankw
;
1030 bankh
= rtex
->surface
.bankh
;
1031 if (rtex
->fmask
.size
)
1032 fmask_bankh
= rtex
->fmask
.bank_height
;
1034 fmask_bankh
= rtex
->surface
.bankh
;
1035 tile_split
= eg_tile_split(tile_split
);
1036 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1037 bankw
= eg_bank_wh(bankw
);
1038 bankh
= eg_bank_wh(bankh
);
1039 fmask_bankh
= eg_bank_wh(fmask_bankh
);
1041 /* 128 bit formats require tile type = 1 */
1042 if (rscreen
->b
.chip_class
== CAYMAN
) {
1043 if (util_format_get_blocksize(surf
->base
.format
) >= 16)
1044 non_disp_tiling
= 1;
1046 nbanks
= eg_num_banks(rscreen
->b
.tiling_info
.num_banks
);
1047 desc
= util_format_description(surf
->base
.format
);
1048 for (i
= 0; i
< 4; i
++) {
1049 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1054 color_attrib
= S_028C74_TILE_SPLIT(tile_split
)|
1055 S_028C74_NUM_BANKS(nbanks
) |
1056 S_028C74_BANK_WIDTH(bankw
) |
1057 S_028C74_BANK_HEIGHT(bankh
) |
1058 S_028C74_MACRO_TILE_ASPECT(macro_aspect
) |
1059 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling
) |
1060 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
1062 if (rctx
->b
.chip_class
== CAYMAN
) {
1063 color_attrib
|= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] ==
1064 UTIL_FORMAT_SWIZZLE_1
);
1066 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1067 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
1068 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1069 S_028C74_NUM_FRAGMENTS(log_samples
);
1073 ntype
= V_028C70_NUMBER_UNORM
;
1074 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1075 ntype
= V_028C70_NUMBER_SRGB
;
1076 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1077 if (desc
->channel
[i
].normalized
)
1078 ntype
= V_028C70_NUMBER_SNORM
;
1079 else if (desc
->channel
[i
].pure_integer
)
1080 ntype
= V_028C70_NUMBER_SINT
;
1081 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1082 if (desc
->channel
[i
].normalized
)
1083 ntype
= V_028C70_NUMBER_UNORM
;
1084 else if (desc
->channel
[i
].pure_integer
)
1085 ntype
= V_028C70_NUMBER_UINT
;
1088 format
= r600_translate_colorformat(rctx
->b
.chip_class
, surf
->base
.format
);
1089 assert(format
!= ~0);
1091 swap
= r600_translate_colorswap(surf
->base
.format
);
1094 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1095 endian
= ENDIAN_NONE
;
1097 endian
= r600_colorformat_endian_swap(format
);
1100 /* blend clamp should be set for all NORM/SRGB types */
1101 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
1102 ntype
== V_028C70_NUMBER_SRGB
)
1105 /* set blend bypass according to docs if SINT/UINT or
1106 8/24 COLOR variants */
1107 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1108 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1109 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1114 surf
->alphatest_bypass
= ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
;
1116 color_info
|= S_028C70_FORMAT(format
) |
1117 S_028C70_COMP_SWAP(swap
) |
1118 S_028C70_BLEND_CLAMP(blend_clamp
) |
1119 S_028C70_BLEND_BYPASS(blend_bypass
) |
1120 S_028C70_NUMBER_TYPE(ntype
) |
1121 S_028C70_ENDIAN(endian
);
1123 /* EXPORT_NORM is an optimzation that can be enabled for better
1124 * performance in certain cases.
1125 * EXPORT_NORM can be enabled if:
1126 * - 11-bit or smaller UNORM/SNORM/SRGB
1127 * - 16-bit or smaller FLOAT
1129 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1130 ((desc
->channel
[i
].size
< 12 &&
1131 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1132 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
1133 (desc
->channel
[i
].size
< 17 &&
1134 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1135 color_info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
1136 surf
->export_16bpc
= true;
1139 if (rtex
->fmask
.size
) {
1140 color_info
|= S_028C70_COMPRESSION(1);
1143 base_offset
= rtex
->resource
.gpu_address
;
1145 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1146 surf
->cb_color_base
= (base_offset
+ offset
) >> 8;
1147 surf
->cb_color_dim
= color_dim
;
1148 surf
->cb_color_info
= color_info
;
1149 surf
->cb_color_pitch
= S_028C64_PITCH_TILE_MAX(pitch
);
1150 surf
->cb_color_slice
= S_028C68_SLICE_TILE_MAX(slice
);
1151 surf
->cb_color_view
= color_view
;
1152 surf
->cb_color_attrib
= color_attrib
;
1153 if (rtex
->fmask
.size
) {
1154 surf
->cb_color_fmask
= (base_offset
+ rtex
->fmask
.offset
) >> 8;
1155 surf
->cb_color_fmask_slice
= S_028C88_TILE_MAX(rtex
->fmask
.slice_tile_max
);
1157 surf
->cb_color_fmask
= surf
->cb_color_base
;
1158 surf
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice
);
1161 surf
->color_initialized
= true;
1164 static void evergreen_init_depth_surface(struct r600_context
*rctx
,
1165 struct r600_surface
*surf
)
1167 struct r600_screen
*rscreen
= rctx
->screen
;
1168 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1169 unsigned level
= surf
->base
.u
.tex
.level
;
1170 struct radeon_surf_level
*levelinfo
= &rtex
->surface
.level
[level
];
1172 unsigned format
, array_mode
;
1173 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1176 format
= r600_translate_dbformat(surf
->base
.format
);
1177 assert(format
!= ~0);
1179 offset
= rtex
->resource
.gpu_address
;
1180 offset
+= rtex
->surface
.level
[level
].offset
;
1182 switch (rtex
->surface
.level
[level
].mode
) {
1183 case RADEON_SURF_MODE_2D
:
1184 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1186 case RADEON_SURF_MODE_1D
:
1187 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1188 case RADEON_SURF_MODE_LINEAR
:
1190 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1193 tile_split
= rtex
->surface
.tile_split
;
1194 macro_aspect
= rtex
->surface
.mtilea
;
1195 bankw
= rtex
->surface
.bankw
;
1196 bankh
= rtex
->surface
.bankh
;
1197 tile_split
= eg_tile_split(tile_split
);
1198 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1199 bankw
= eg_bank_wh(bankw
);
1200 bankh
= eg_bank_wh(bankh
);
1201 nbanks
= eg_num_banks(rscreen
->b
.tiling_info
.num_banks
);
1204 surf
->db_z_info
= S_028040_ARRAY_MODE(array_mode
) |
1205 S_028040_FORMAT(format
) |
1206 S_028040_TILE_SPLIT(tile_split
)|
1207 S_028040_NUM_BANKS(nbanks
) |
1208 S_028040_BANK_WIDTH(bankw
) |
1209 S_028040_BANK_HEIGHT(bankh
) |
1210 S_028040_MACRO_TILE_ASPECT(macro_aspect
);
1211 if (rscreen
->b
.chip_class
== CAYMAN
&& rtex
->resource
.b
.b
.nr_samples
> 1) {
1212 surf
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
1215 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
1217 surf
->db_depth_base
= offset
;
1218 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1219 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1220 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX(levelinfo
->nblk_x
/ 8 - 1) |
1221 S_028058_HEIGHT_TILE_MAX(levelinfo
->nblk_y
/ 8 - 1);
1222 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX(levelinfo
->nblk_x
*
1223 levelinfo
->nblk_y
/ 64 - 1);
1225 switch (surf
->base
.format
) {
1226 case PIPE_FORMAT_Z24X8_UNORM
:
1227 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1228 case PIPE_FORMAT_X8Z24_UNORM
:
1229 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1230 surf
->pa_su_poly_offset_db_fmt_cntl
=
1231 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1233 case PIPE_FORMAT_Z32_FLOAT
:
1234 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1235 surf
->pa_su_poly_offset_db_fmt_cntl
=
1236 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1237 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1239 case PIPE_FORMAT_Z16_UNORM
:
1240 surf
->pa_su_poly_offset_db_fmt_cntl
=
1241 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1246 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1247 uint64_t stencil_offset
;
1248 unsigned stile_split
= rtex
->surface
.stencil_tile_split
;
1250 stile_split
= eg_tile_split(stile_split
);
1252 stencil_offset
= rtex
->surface
.stencil_level
[level
].offset
;
1253 stencil_offset
+= rtex
->resource
.gpu_address
;
1255 surf
->db_stencil_base
= stencil_offset
>> 8;
1256 surf
->db_stencil_info
= S_028044_FORMAT(V_028044_STENCIL_8
) |
1257 S_028044_TILE_SPLIT(stile_split
);
1259 surf
->db_stencil_base
= offset
;
1260 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1261 * Older kernels are out of luck. */
1262 surf
->db_stencil_info
= rctx
->screen
->b
.info
.drm_minor
>= 18 ?
1263 S_028044_FORMAT(V_028044_STENCIL_INVALID
) :
1264 S_028044_FORMAT(V_028044_STENCIL_8
);
1267 /* use htile only for first level */
1268 if (rtex
->htile_buffer
&& !level
) {
1269 uint64_t va
= rtex
->htile_buffer
->gpu_address
;
1270 surf
->db_htile_data_base
= va
>> 8;
1271 surf
->db_htile_surface
= S_028ABC_HTILE_WIDTH(1) |
1272 S_028ABC_HTILE_HEIGHT(1) |
1273 S_028ABC_FULL_CACHE(1);
1274 surf
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
1275 surf
->db_preload_control
= 0;
1278 surf
->depth_initialized
= true;
1281 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
1282 const struct pipe_framebuffer_state
*state
)
1284 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1285 struct r600_surface
*surf
;
1286 struct r600_texture
*rtex
;
1287 uint32_t i
, log_samples
;
1289 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1290 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1291 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_CB
|
1292 R600_CONTEXT_FLUSH_AND_INV_CB_META
;
1294 if (rctx
->framebuffer
.state
.zsbuf
) {
1295 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1296 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB
;
1298 rtex
= (struct r600_texture
*)rctx
->framebuffer
.state
.zsbuf
->texture
;
1299 if (rtex
->htile_buffer
) {
1300 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB_META
;
1304 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1307 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1308 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&& state
->cbufs
[0] &&
1309 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1310 rctx
->framebuffer
.compressed_cb_mask
= 0;
1311 rctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
1313 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1314 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1318 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1320 r600_context_add_resource_size(ctx
, state
->cbufs
[i
]->texture
);
1322 if (!surf
->color_initialized
) {
1323 evergreen_init_color_surface(rctx
, surf
);
1326 if (!surf
->export_16bpc
) {
1327 rctx
->framebuffer
.export_16bpc
= false;
1330 if (rtex
->fmask
.size
&& rtex
->cmask
.size
) {
1331 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1335 /* Update alpha-test state dependencies.
1336 * Alpha-test is done on the first colorbuffer only. */
1337 if (state
->nr_cbufs
) {
1338 bool alphatest_bypass
= false;
1339 bool export_16bpc
= true;
1341 surf
= (struct r600_surface
*)state
->cbufs
[0];
1343 alphatest_bypass
= surf
->alphatest_bypass
;
1344 export_16bpc
= surf
->export_16bpc
;
1347 if (rctx
->alphatest_state
.bypass
!= alphatest_bypass
) {
1348 rctx
->alphatest_state
.bypass
= alphatest_bypass
;
1349 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1351 if (rctx
->alphatest_state
.cb0_export_16bpc
!= export_16bpc
) {
1352 rctx
->alphatest_state
.cb0_export_16bpc
= export_16bpc
;
1353 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1359 surf
= (struct r600_surface
*)state
->zsbuf
;
1361 r600_context_add_resource_size(ctx
, state
->zsbuf
->texture
);
1363 if (!surf
->depth_initialized
) {
1364 evergreen_init_depth_surface(rctx
, surf
);
1367 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1368 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1369 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
1372 if (rctx
->db_state
.rsurf
!= surf
) {
1373 rctx
->db_state
.rsurf
= surf
;
1374 r600_mark_atom_dirty(rctx
, &rctx
->db_state
.atom
);
1375 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1377 } else if (rctx
->db_state
.rsurf
) {
1378 rctx
->db_state
.rsurf
= NULL
;
1379 r600_mark_atom_dirty(rctx
, &rctx
->db_state
.atom
);
1380 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1383 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1384 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1385 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1388 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1389 rctx
->alphatest_state
.bypass
= false;
1390 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1393 log_samples
= util_logbase2(rctx
->framebuffer
.nr_samples
);
1394 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1395 if ((rctx
->b
.chip_class
== CAYMAN
||
1396 rctx
->b
.family
== CHIP_RV770
) &&
1397 rctx
->db_misc_state
.log_samples
!= log_samples
) {
1398 rctx
->db_misc_state
.log_samples
= log_samples
;
1399 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1403 /* Calculate the CS size. */
1404 rctx
->framebuffer
.atom
.num_dw
= 4; /* SCISSOR */
1407 if (rctx
->b
.chip_class
== EVERGREEN
)
1408 rctx
->framebuffer
.atom
.num_dw
+= 17; /* Evergreen */
1410 rctx
->framebuffer
.atom
.num_dw
+= 28; /* Cayman */
1413 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 23;
1414 if (rctx
->keep_tiling_flags
)
1415 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 2;
1416 rctx
->framebuffer
.atom
.num_dw
+= (12 - state
->nr_cbufs
) * 3;
1420 rctx
->framebuffer
.atom
.num_dw
+= 24;
1421 if (rctx
->keep_tiling_flags
)
1422 rctx
->framebuffer
.atom
.num_dw
+= 2;
1423 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1424 rctx
->framebuffer
.atom
.num_dw
+= 4;
1427 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1429 r600_set_sample_locations_constant_buffer(rctx
);
1432 static void evergreen_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
1434 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1436 if (rctx
->ps_iter_samples
== min_samples
)
1439 rctx
->ps_iter_samples
= min_samples
;
1440 if (rctx
->framebuffer
.nr_samples
> 1) {
1441 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1446 static uint32_t sample_locs_8x
[] = {
1447 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1448 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1449 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1450 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1451 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1452 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1453 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1454 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1456 static unsigned max_dist_8x
= 7;
1458 static void evergreen_get_sample_position(struct pipe_context
*ctx
,
1459 unsigned sample_count
,
1460 unsigned sample_index
,
1467 switch (sample_count
) {
1470 out_value
[0] = out_value
[1] = 0.5;
1473 offset
= 4 * (sample_index
* 2);
1474 val
.idx
= (eg_sample_locs_2x
[0] >> offset
) & 0xf;
1475 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1476 val
.idx
= (eg_sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1477 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1480 offset
= 4 * (sample_index
* 2);
1481 val
.idx
= (eg_sample_locs_4x
[0] >> offset
) & 0xf;
1482 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1483 val
.idx
= (eg_sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1484 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1487 offset
= 4 * (sample_index
% 4 * 2);
1488 index
= (sample_index
/ 4);
1489 val
.idx
= (sample_locs_8x
[index
] >> offset
) & 0xf;
1490 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1491 val
.idx
= (sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1492 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1497 static void evergreen_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
, int ps_iter_samples
)
1500 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1501 unsigned max_dist
= 0;
1503 switch (nr_samples
) {
1508 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(eg_sample_locs_2x
));
1509 radeon_emit_array(cs
, eg_sample_locs_2x
, Elements(eg_sample_locs_2x
));
1510 max_dist
= eg_max_dist_2x
;
1513 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(eg_sample_locs_4x
));
1514 radeon_emit_array(cs
, eg_sample_locs_4x
, Elements(eg_sample_locs_4x
));
1515 max_dist
= eg_max_dist_4x
;
1518 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(sample_locs_8x
));
1519 radeon_emit_array(cs
, sample_locs_8x
, Elements(sample_locs_8x
));
1520 max_dist
= max_dist_8x
;
1524 if (nr_samples
> 1) {
1525 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1526 radeon_emit(cs
, S_028C00_LAST_PIXEL(1) |
1527 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1528 radeon_emit(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1529 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1530 r600_write_context_reg(cs
, EG_R_028A4C_PA_SC_MODE_CNTL_1
, EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1));
1532 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1533 radeon_emit(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1534 radeon_emit(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1535 r600_write_context_reg(cs
, EG_R_028A4C_PA_SC_MODE_CNTL_1
, 0);
1539 static void evergreen_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1541 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1542 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1543 unsigned nr_cbufs
= state
->nr_cbufs
;
1545 struct r600_texture
*tex
= NULL
;
1546 struct r600_surface
*cb
= NULL
;
1548 /* XXX support more colorbuffers once we need them */
1549 assert(nr_cbufs
<= 8);
1554 for (i
= 0; i
< nr_cbufs
; i
++) {
1555 unsigned reloc
, cmask_reloc
;
1557 cb
= (struct r600_surface
*)state
->cbufs
[i
];
1559 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1560 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1564 tex
= (struct r600_texture
*)cb
->base
.texture
;
1565 reloc
= r600_context_bo_reloc(&rctx
->b
,
1567 (struct r600_resource
*)cb
->base
.texture
,
1568 RADEON_USAGE_READWRITE
,
1569 tex
->surface
.nsamples
> 1 ?
1570 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1571 RADEON_PRIO_COLOR_BUFFER
);
1573 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
1574 cmask_reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
,
1575 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
1576 RADEON_PRIO_COLOR_META
);
1578 cmask_reloc
= reloc
;
1581 r600_write_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 13);
1582 radeon_emit(cs
, cb
->cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
1583 radeon_emit(cs
, cb
->cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
1584 radeon_emit(cs
, cb
->cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
1585 radeon_emit(cs
, cb
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
1586 radeon_emit(cs
, cb
->cb_color_info
| tex
->cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
1587 radeon_emit(cs
, cb
->cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
1588 radeon_emit(cs
, cb
->cb_color_dim
); /* R_028C78_CB_COLOR0_DIM */
1589 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* R_028C7C_CB_COLOR0_CMASK */
1590 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1591 radeon_emit(cs
, cb
->cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
1592 radeon_emit(cs
, cb
->cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1593 radeon_emit(cs
, tex
->color_clear_value
[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1594 radeon_emit(cs
, tex
->color_clear_value
[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1596 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1597 radeon_emit(cs
, reloc
);
1599 if (!rctx
->keep_tiling_flags
) {
1600 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1601 radeon_emit(cs
, reloc
);
1604 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1605 radeon_emit(cs
, reloc
);
1607 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1608 radeon_emit(cs
, cmask_reloc
);
1610 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1611 radeon_emit(cs
, reloc
);
1613 /* set CB_COLOR1_INFO for possible dual-src blending */
1614 if (i
== 1 && state
->cbufs
[0]) {
1615 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C,
1616 cb
->cb_color_info
| tex
->cb_color_info
);
1618 if (!rctx
->keep_tiling_flags
) {
1619 unsigned reloc
= r600_context_bo_reloc(&rctx
->b
,
1621 (struct r600_resource
*)state
->cbufs
[0]->texture
,
1622 RADEON_USAGE_READWRITE
,
1623 RADEON_PRIO_COLOR_BUFFER
);
1625 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1626 radeon_emit(cs
, reloc
);
1630 if (rctx
->keep_tiling_flags
) {
1631 for (; i
< 8 ; i
++) {
1632 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
1634 for (; i
< 12; i
++) {
1635 r600_write_context_reg(cs
, R_028E50_CB_COLOR8_INFO
+ (i
- 8) * 0x1C, 0);
1641 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
1642 unsigned reloc
= r600_context_bo_reloc(&rctx
->b
,
1644 (struct r600_resource
*)state
->zsbuf
->texture
,
1645 RADEON_USAGE_READWRITE
,
1646 zb
->base
.texture
->nr_samples
> 1 ?
1647 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
1648 RADEON_PRIO_DEPTH_BUFFER
);
1650 r600_write_context_reg(cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1651 zb
->pa_su_poly_offset_db_fmt_cntl
);
1652 r600_write_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
1654 r600_write_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 8);
1655 radeon_emit(cs
, zb
->db_z_info
); /* R_028040_DB_Z_INFO */
1656 radeon_emit(cs
, zb
->db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1657 radeon_emit(cs
, zb
->db_depth_base
); /* R_028048_DB_Z_READ_BASE */
1658 radeon_emit(cs
, zb
->db_stencil_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1659 radeon_emit(cs
, zb
->db_depth_base
); /* R_028050_DB_Z_WRITE_BASE */
1660 radeon_emit(cs
, zb
->db_stencil_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1661 radeon_emit(cs
, zb
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1662 radeon_emit(cs
, zb
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1664 if (!rctx
->keep_tiling_flags
) {
1665 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028040_DB_Z_INFO */
1666 radeon_emit(cs
, reloc
);
1669 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1670 radeon_emit(cs
, reloc
);
1672 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1673 radeon_emit(cs
, reloc
);
1675 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1676 radeon_emit(cs
, reloc
);
1678 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1679 radeon_emit(cs
, reloc
);
1680 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1681 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1682 * Older kernels are out of luck. */
1683 r600_write_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
1684 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
1685 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
1688 /* Framebuffer dimensions. */
1689 evergreen_get_scissor_rect(rctx
, 0, 0, state
->width
, state
->height
, &tl
, &br
);
1691 r600_write_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
1692 radeon_emit(cs
, tl
); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1693 radeon_emit(cs
, br
); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1695 if (rctx
->b
.chip_class
== EVERGREEN
) {
1696 evergreen_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
, rctx
->ps_iter_samples
);
1698 cayman_emit_msaa_sample_locs(cs
, rctx
->framebuffer
.nr_samples
);
1699 cayman_emit_msaa_config(cs
, rctx
->framebuffer
.nr_samples
, rctx
->ps_iter_samples
, 0);
1703 static void evergreen_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
1705 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1706 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
1707 float offset_units
= state
->offset_units
;
1708 float offset_scale
= state
->offset_scale
;
1710 switch (state
->zs_format
) {
1711 case PIPE_FORMAT_Z24X8_UNORM
:
1712 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1713 case PIPE_FORMAT_X8Z24_UNORM
:
1714 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1715 offset_units
*= 2.0f
;
1717 case PIPE_FORMAT_Z16_UNORM
:
1718 offset_units
*= 4.0f
;
1723 r600_write_context_reg_seq(cs
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
1724 radeon_emit(cs
, fui(offset_scale
));
1725 radeon_emit(cs
, fui(offset_units
));
1726 radeon_emit(cs
, fui(offset_scale
));
1727 radeon_emit(cs
, fui(offset_units
));
1730 static void evergreen_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1732 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1733 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1734 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1735 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1737 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1738 radeon_emit(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
1739 /* This must match the used export instructions exactly.
1740 * Other values may lead to undefined behavior and hangs.
1742 radeon_emit(cs
, ps_colormask
); /* R_02823C_CB_SHADER_MASK */
1745 static void evergreen_emit_db_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1747 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1748 struct r600_db_state
*a
= (struct r600_db_state
*)atom
;
1750 if (a
->rsurf
&& a
->rsurf
->db_htile_surface
) {
1751 struct r600_texture
*rtex
= (struct r600_texture
*)a
->rsurf
->base
.texture
;
1754 r600_write_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear_value
));
1755 r600_write_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, a
->rsurf
->db_htile_surface
);
1756 r600_write_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, a
->rsurf
->db_preload_control
);
1757 r600_write_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, a
->rsurf
->db_htile_data_base
);
1758 reloc_idx
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rtex
->htile_buffer
,
1759 RADEON_USAGE_READWRITE
, RADEON_PRIO_DEPTH_META
);
1760 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1761 cs
->buf
[cs
->cdw
++] = reloc_idx
;
1763 r600_write_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, 0);
1764 r600_write_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0);
1768 static void evergreen_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1770 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1771 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1772 unsigned db_render_control
= 0;
1773 unsigned db_count_control
= 0;
1774 unsigned db_render_override
=
1775 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
1776 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
) |
1777 /* There is a hang with HTILE if stencil is used and
1778 * fast stencil is enabled. */
1779 S_02800C_FAST_STENCIL_DISABLE(1);
1781 if (a
->occlusion_query_enabled
) {
1782 db_count_control
|= S_028004_PERFECT_ZPASS_COUNTS(1);
1783 if (rctx
->b
.chip_class
== CAYMAN
) {
1784 db_count_control
|= S_028004_SAMPLE_RATE(a
->log_samples
);
1786 db_render_override
|= S_02800C_NOOP_CULL_DISABLE(1);
1788 /* FIXME we should be able to use hyperz even if we are not writing to
1789 * zbuffer but somehow this trigger GPU lockup. See :
1791 * https://bugs.freedesktop.org/show_bug.cgi?id=60848
1793 * Disable hyperz for now if not writing to zbuffer.
1795 if (rctx
->db_state
.rsurf
&& rctx
->db_state
.rsurf
->db_htile_surface
&& rctx
->zwritemask
) {
1796 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1797 db_render_override
|= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF
);
1798 /* This is to fix a lockup when hyperz and alpha test are enabled at
1799 * the same time somehow GPU get confuse on which order to pick for
1802 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
1803 db_render_override
|= S_02800C_FORCE_SHADER_Z_ORDER(1);
1806 db_render_override
|= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
);
1808 if (a
->flush_depthstencil_through_cb
) {
1809 assert(a
->copy_depth
|| a
->copy_stencil
);
1811 db_render_control
|= S_028000_DEPTH_COPY_ENABLE(a
->copy_depth
) |
1812 S_028000_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
1813 S_028000_COPY_CENTROID(1) |
1814 S_028000_COPY_SAMPLE(a
->copy_sample
);
1815 } else if (a
->flush_depthstencil_in_place
) {
1816 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(1) |
1817 S_028000_STENCIL_COMPRESS_DISABLE(1);
1818 db_render_override
|= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1820 if (a
->htile_clear
) {
1821 /* FIXME we might want to disable cliprect here */
1822 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(1);
1825 r600_write_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1826 radeon_emit(cs
, db_render_control
); /* R_028000_DB_RENDER_CONTROL */
1827 radeon_emit(cs
, db_count_control
); /* R_028004_DB_COUNT_CONTROL */
1828 r600_write_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
1829 r600_write_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
1832 static void evergreen_emit_vertex_buffers(struct r600_context
*rctx
,
1833 struct r600_vertexbuf_state
*state
,
1834 unsigned resource_offset
,
1837 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1838 uint32_t dirty_mask
= state
->dirty_mask
;
1840 while (dirty_mask
) {
1841 struct pipe_vertex_buffer
*vb
;
1842 struct r600_resource
*rbuffer
;
1844 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
1846 vb
= &state
->vb
[buffer_index
];
1847 rbuffer
= (struct r600_resource
*)vb
->buffer
;
1850 va
= rbuffer
->gpu_address
+ vb
->buffer_offset
;
1852 /* fetch resources start at index 992 */
1853 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
1854 radeon_emit(cs
, (resource_offset
+ buffer_index
) * 8);
1855 radeon_emit(cs
, va
); /* RESOURCEi_WORD0 */
1856 radeon_emit(cs
, rbuffer
->buf
->size
- vb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
1857 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1858 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1859 S_030008_STRIDE(vb
->stride
) |
1860 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
1861 radeon_emit(cs
, /* RESOURCEi_WORD3 */
1862 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
1863 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
1864 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
1865 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
1866 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1867 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1868 radeon_emit(cs
, 0); /* RESOURCEi_WORD6 */
1869 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
1871 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1872 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1873 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BUFFER_RO
));
1875 state
->dirty_mask
= 0;
1878 static void evergreen_fs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
1880 evergreen_emit_vertex_buffers(rctx
, &rctx
->vertex_buffer_state
, 992, 0);
1883 static void evergreen_cs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
1885 evergreen_emit_vertex_buffers(rctx
, &rctx
->cs_vertex_buffer_state
, 816,
1886 RADEON_CP_PACKET3_COMPUTE_MODE
);
1889 static void evergreen_emit_constant_buffers(struct r600_context
*rctx
,
1890 struct r600_constbuf_state
*state
,
1891 unsigned buffer_id_base
,
1892 unsigned reg_alu_constbuf_size
,
1893 unsigned reg_alu_const_cache
,
1896 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1897 uint32_t dirty_mask
= state
->dirty_mask
;
1899 while (dirty_mask
) {
1900 struct pipe_constant_buffer
*cb
;
1901 struct r600_resource
*rbuffer
;
1903 unsigned buffer_index
= ffs(dirty_mask
) - 1;
1904 unsigned gs_ring_buffer
= (buffer_index
== R600_GS_RING_CONST_BUFFER
);
1906 cb
= &state
->cb
[buffer_index
];
1907 rbuffer
= (struct r600_resource
*)cb
->buffer
;
1910 va
= rbuffer
->gpu_address
+ cb
->buffer_offset
;
1912 if (!gs_ring_buffer
) {
1913 r600_write_context_reg_flag(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
1914 ALIGN_DIVUP(cb
->buffer_size
>> 4, 16), pkt_flags
);
1915 r600_write_context_reg_flag(cs
, reg_alu_const_cache
+ buffer_index
* 4, va
>> 8,
1919 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1920 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1921 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BUFFER_RO
));
1923 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
1924 radeon_emit(cs
, (buffer_id_base
+ buffer_index
) * 8);
1925 radeon_emit(cs
, va
); /* RESOURCEi_WORD0 */
1926 radeon_emit(cs
, rbuffer
->buf
->size
- cb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
1927 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1928 S_030008_ENDIAN_SWAP(gs_ring_buffer
? ENDIAN_NONE
: r600_endian_swap(32)) |
1929 S_030008_STRIDE(gs_ring_buffer
? 4 : 16) |
1930 S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
1931 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT
));
1932 radeon_emit(cs
, /* RESOURCEi_WORD3 */
1933 S_03000C_UNCACHED(gs_ring_buffer
? 1 : 0) |
1934 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
1935 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
1936 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
1937 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
1938 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1939 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1940 radeon_emit(cs
, 0); /* RESOURCEi_WORD6 */
1941 radeon_emit(cs
, /* RESOURCEi_WORD7 */
1942 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
));
1944 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1945 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1946 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BUFFER_RO
));
1948 dirty_mask
&= ~(1 << buffer_index
);
1950 state
->dirty_mask
= 0;
1953 static void evergreen_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1955 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
], 176,
1956 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
1957 R_028980_ALU_CONST_CACHE_VS_0
,
1958 0 /* PKT3 flags */);
1961 static void evergreen_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1963 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
], 336,
1964 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
1965 R_0289C0_ALU_CONST_CACHE_GS_0
,
1966 0 /* PKT3 flags */);
1969 static void evergreen_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1971 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
], 0,
1972 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
1973 R_028940_ALU_CONST_CACHE_PS_0
,
1974 0 /* PKT3 flags */);
1977 static void evergreen_emit_cs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1979 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_COMPUTE
], 816,
1980 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
,
1981 R_028F40_ALU_CONST_CACHE_LS_0
,
1982 RADEON_CP_PACKET3_COMPUTE_MODE
);
1985 static void evergreen_emit_sampler_views(struct r600_context
*rctx
,
1986 struct r600_samplerview_state
*state
,
1987 unsigned resource_id_base
, unsigned pkt_flags
)
1989 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1990 uint32_t dirty_mask
= state
->dirty_mask
;
1992 while (dirty_mask
) {
1993 struct r600_pipe_sampler_view
*rview
;
1994 unsigned resource_index
= u_bit_scan(&dirty_mask
);
1997 rview
= state
->views
[resource_index
];
2000 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
2001 radeon_emit(cs
, (resource_id_base
+ resource_index
) * 8);
2002 radeon_emit_array(cs
, rview
->tex_resource_words
, 8);
2004 reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rview
->tex_resource
,
2006 rview
->tex_resource
->b
.b
.nr_samples
> 1 ?
2007 RADEON_PRIO_SHADER_TEXTURE_MSAA
:
2008 RADEON_PRIO_SHADER_TEXTURE_RO
);
2009 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2010 radeon_emit(cs
, reloc
);
2012 if (!rview
->skip_mip_address_reloc
) {
2013 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2014 radeon_emit(cs
, reloc
);
2017 state
->dirty_mask
= 0;
2020 static void evergreen_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2022 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
,
2023 176 + R600_MAX_CONST_BUFFERS
, 0);
2026 static void evergreen_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2028 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
,
2029 336 + R600_MAX_CONST_BUFFERS
, 0);
2032 static void evergreen_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2034 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
,
2035 R600_MAX_CONST_BUFFERS
, 0);
2038 static void evergreen_emit_cs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2040 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
].views
,
2041 816 + 2, RADEON_CP_PACKET3_COMPUTE_MODE
);
2044 static void evergreen_emit_sampler_states(struct r600_context
*rctx
,
2045 struct r600_textures_info
*texinfo
,
2046 unsigned resource_id_base
,
2047 unsigned border_index_reg
,
2050 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2051 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
2053 while (dirty_mask
) {
2054 struct r600_pipe_sampler_state
*rstate
;
2055 unsigned i
= u_bit_scan(&dirty_mask
);
2057 rstate
= texinfo
->states
.states
[i
];
2060 radeon_emit(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0) | pkt_flags
);
2061 radeon_emit(cs
, (resource_id_base
+ i
) * 3);
2062 radeon_emit_array(cs
, rstate
->tex_sampler_words
, 3);
2064 if (rstate
->border_color_use
) {
2065 r600_write_config_reg_seq(cs
, border_index_reg
, 5);
2067 radeon_emit_array(cs
, rstate
->border_color
.ui
, 4);
2070 texinfo
->states
.dirty_mask
= 0;
2073 static void evergreen_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2075 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18,
2076 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
, 0);
2079 static void evergreen_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2081 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36,
2082 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX
, 0);
2085 static void evergreen_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2087 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0,
2088 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
, 0);
2091 static void evergreen_emit_cs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2093 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
], 90,
2094 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX
,
2095 RADEON_CP_PACKET3_COMPUTE_MODE
);
2098 static void evergreen_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2100 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2101 uint8_t mask
= s
->sample_mask
;
2103 r600_write_context_reg(rctx
->b
.rings
.gfx
.cs
, R_028C3C_PA_SC_AA_MASK
,
2104 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2107 static void cayman_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2109 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2110 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2111 uint16_t mask
= s
->sample_mask
;
2113 r600_write_context_reg_seq(cs
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2114 radeon_emit(cs
, mask
| (mask
<< 16)); /* X0Y0_X1Y0 */
2115 radeon_emit(cs
, mask
| (mask
<< 16)); /* X0Y1_X1Y1 */
2118 static void evergreen_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2120 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2121 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
2122 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
->cso
;
2124 r600_write_context_reg(cs
, R_0288A4_SQ_PGM_START_FS
,
2125 (shader
->buffer
->gpu_address
+ shader
->offset
) >> 8);
2126 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2127 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, shader
->buffer
,
2128 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
));
2131 static void evergreen_emit_shader_stages(struct r600_context
*rctx
, struct r600_atom
*a
)
2133 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2134 struct r600_shader_stages_state
*state
= (struct r600_shader_stages_state
*)a
;
2136 uint32_t v
= 0, v2
= 0, primid
= 0;
2138 if (rctx
->vs_shader
->current
->shader
.vs_as_gs_a
) {
2139 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
2143 if (state
->geom_enable
) {
2146 if (rctx
->gs_shader
->current
->shader
.gs_max_out_vertices
<= 128)
2147 cut_val
= V_028A40_GS_CUT_128
;
2148 else if (rctx
->gs_shader
->current
->shader
.gs_max_out_vertices
<= 256)
2149 cut_val
= V_028A40_GS_CUT_256
;
2150 else if (rctx
->gs_shader
->current
->shader
.gs_max_out_vertices
<= 512)
2151 cut_val
= V_028A40_GS_CUT_512
;
2153 cut_val
= V_028A40_GS_CUT_1024
;
2154 v
= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
2156 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2158 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
2159 S_028A40_CUT_MODE(cut_val
);
2161 if (rctx
->gs_shader
->current
->shader
.gs_prim_id_input
)
2165 r600_write_context_reg(cs
, R_028B54_VGT_SHADER_STAGES_EN
, v
);
2166 r600_write_context_reg(cs
, R_028A40_VGT_GS_MODE
, v2
);
2167 r600_write_context_reg(cs
, R_028A84_VGT_PRIMITIVEID_EN
, primid
);
2170 static void evergreen_emit_gs_rings(struct r600_context
*rctx
, struct r600_atom
*a
)
2172 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2173 struct r600_gs_rings_state
*state
= (struct r600_gs_rings_state
*)a
;
2174 struct r600_resource
*rbuffer
;
2176 r600_write_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2177 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2178 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
2180 if (state
->enable
) {
2181 rbuffer
=(struct r600_resource
*)state
->esgs_ring
.buffer
;
2182 r600_write_config_reg(cs
, R_008C40_SQ_ESGS_RING_BASE
,
2183 rbuffer
->gpu_address
>> 8);
2184 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2185 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
2186 RADEON_USAGE_READWRITE
,
2187 RADEON_PRIO_SHADER_RESOURCE_RW
));
2188 r600_write_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
,
2189 state
->esgs_ring
.buffer_size
>> 8);
2191 rbuffer
=(struct r600_resource
*)state
->gsvs_ring
.buffer
;
2192 r600_write_config_reg(cs
, R_008C48_SQ_GSVS_RING_BASE
,
2193 rbuffer
->gpu_address
>> 8);
2194 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2195 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
2196 RADEON_USAGE_READWRITE
,
2197 RADEON_PRIO_SHADER_RESOURCE_RW
));
2198 r600_write_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
,
2199 state
->gsvs_ring
.buffer_size
>> 8);
2201 r600_write_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
, 0);
2202 r600_write_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
, 0);
2205 r600_write_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2206 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2207 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
2210 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
2211 enum chip_class ctx_chip_class
,
2212 enum radeon_family ctx_family
,
2215 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2216 r600_store_value(cb
, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2217 /* always set the temp clauses */
2218 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2220 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2221 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2222 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2224 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2226 r600_store_context_reg_seq(cb
, R_028350_SX_MISC
, 2);
2227 r600_store_value(cb
, 0);
2228 r600_store_value(cb
, S_028354_SURFACE_SYNC_MASK(0xf));
2230 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2233 static void cayman_init_atom_start_cs(struct r600_context
*rctx
)
2235 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2238 r600_init_command_buffer(cb
, 320);
2240 /* This must be first. */
2241 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2242 r600_store_value(cb
, 0x80000000);
2243 r600_store_value(cb
, 0x80000000);
2245 /* We're setting config registers here. */
2246 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2247 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2249 cayman_init_common_regs(cb
, rctx
->b
.chip_class
,
2250 rctx
->b
.family
, rctx
->screen
->b
.info
.drm_minor
);
2252 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2253 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2255 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2256 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2257 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2258 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2259 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2260 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2261 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2263 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2264 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2265 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2266 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2267 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2269 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2270 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2271 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2272 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2273 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2274 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2275 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2276 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2277 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2278 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2279 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2280 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2281 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2282 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2284 r600_store_context_reg(cb
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0);
2286 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2287 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
2288 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2290 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2292 r600_store_context_reg_seq(cb
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
2293 r600_store_value(cb
, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2294 r600_store_value(cb
, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2296 r600_store_context_reg_seq(cb
, CM_R_0288E8_SQ_LDS_ALLOC
, 2);
2297 r600_store_value(cb
, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2298 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2300 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2302 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2303 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2304 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2306 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2308 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2310 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2312 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2313 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2314 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2315 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2317 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2318 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2320 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2 * R600_MAX_VIEWPORTS
);
2321 for (tmp
= 0; tmp
< R600_MAX_VIEWPORTS
; tmp
++) {
2322 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2323 r600_store_value(cb
, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2326 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2327 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2329 r600_store_context_reg_seq(cb
, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2330 r600_store_value(cb
, fui(1.0)); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2331 r600_store_value(cb
, fui(1.0)); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2332 r600_store_value(cb
, fui(1.0)); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2333 r600_store_value(cb
, fui(1.0)); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2335 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2336 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2337 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2339 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2340 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2341 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2343 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2344 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2345 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2347 /* to avoid GPU doing any preloading of constant from random address */
2348 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2349 for (i
= 0; i
< 16; i
++)
2350 r600_store_value(cb
, 0);
2352 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2353 for (i
= 0; i
< 16; i
++)
2354 r600_store_value(cb
, 0);
2356 r600_store_context_reg_seq(cb
, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
, 16);
2357 for (i
= 0; i
< 16; i
++)
2358 r600_store_value(cb
, 0);
2360 r600_store_context_reg_seq(cb
, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
, 16);
2361 for (i
= 0; i
< 16; i
++)
2362 r600_store_value(cb
, 0);
2364 r600_store_context_reg_seq(cb
, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0
, 16);
2365 for (i
= 0; i
< 16; i
++)
2366 r600_store_value(cb
, 0);
2368 if (rctx
->screen
->b
.has_streamout
) {
2369 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2372 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
2373 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
2374 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2375 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
2376 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2377 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2378 r600_store_context_reg(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 0);
2380 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2381 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2382 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (64 * 4), 0x01000FFF);
2385 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
2386 enum chip_class ctx_chip_class
,
2387 enum radeon_family ctx_family
,
2426 switch (ctx_family
) {
2434 tmp
|= S_008C00_VC_ENABLE(1);
2437 tmp
|= S_008C00_EXPORT_SRC_C(1);
2438 tmp
|= S_008C00_CS_PRIO(cs_prio
);
2439 tmp
|= S_008C00_LS_PRIO(ls_prio
);
2440 tmp
|= S_008C00_HS_PRIO(hs_prio
);
2441 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2442 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2443 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2444 tmp
|= S_008C00_ES_PRIO(es_prio
);
2446 /* enable dynamic GPR resource management */
2447 if (ctx_drm_minor
>= 7) {
2448 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2449 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2450 /* always set temp clauses */
2451 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2452 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2453 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2454 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2455 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2456 r600_store_context_reg(cb
, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
,
2457 S_028838_PS_GPRS(0x1e) |
2458 S_028838_VS_GPRS(0x1e) |
2459 S_028838_GS_GPRS(0x1e) |
2460 S_028838_ES_GPRS(0x1e) |
2461 S_028838_HS_GPRS(0x1e) |
2462 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2464 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 4);
2465 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2467 tmp
= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
2468 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
2469 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
2470 r600_store_value(cb
, tmp
); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2472 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2473 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2474 r600_store_value(cb
, tmp
); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2476 tmp
= S_008C0C_NUM_HS_GPRS(num_hs_gprs
);
2477 tmp
|= S_008C0C_NUM_HS_GPRS(num_ls_gprs
);
2478 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2481 /* The cs checker requires this register to be set. */
2482 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2484 r600_store_context_reg_seq(cb
, R_028350_SX_MISC
, 2);
2485 r600_store_value(cb
, 0);
2486 r600_store_value(cb
, S_028354_SURFACE_SYNC_MASK(0xf));
2491 void evergreen_init_atom_start_cs(struct r600_context
*rctx
)
2493 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2501 int num_ps_stack_entries
;
2502 int num_vs_stack_entries
;
2503 int num_gs_stack_entries
;
2504 int num_es_stack_entries
;
2505 int num_hs_stack_entries
;
2506 int num_ls_stack_entries
;
2507 enum radeon_family family
;
2510 if (rctx
->b
.chip_class
== CAYMAN
) {
2511 cayman_init_atom_start_cs(rctx
);
2515 r600_init_command_buffer(cb
, 320);
2517 /* This must be first. */
2518 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2519 r600_store_value(cb
, 0x80000000);
2520 r600_store_value(cb
, 0x80000000);
2522 /* We're setting config registers here. */
2523 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2524 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2526 evergreen_init_common_regs(cb
, rctx
->b
.chip_class
,
2527 rctx
->b
.family
, rctx
->screen
->b
.info
.drm_minor
);
2529 family
= rctx
->b
.family
;
2533 num_ps_threads
= 96;
2534 num_vs_threads
= 16;
2535 num_gs_threads
= 16;
2536 num_es_threads
= 16;
2537 num_hs_threads
= 16;
2538 num_ls_threads
= 16;
2539 num_ps_stack_entries
= 42;
2540 num_vs_stack_entries
= 42;
2541 num_gs_stack_entries
= 42;
2542 num_es_stack_entries
= 42;
2543 num_hs_stack_entries
= 42;
2544 num_ls_stack_entries
= 42;
2547 num_ps_threads
= 128;
2548 num_vs_threads
= 20;
2549 num_gs_threads
= 20;
2550 num_es_threads
= 20;
2551 num_hs_threads
= 20;
2552 num_ls_threads
= 20;
2553 num_ps_stack_entries
= 42;
2554 num_vs_stack_entries
= 42;
2555 num_gs_stack_entries
= 42;
2556 num_es_stack_entries
= 42;
2557 num_hs_stack_entries
= 42;
2558 num_ls_stack_entries
= 42;
2561 num_ps_threads
= 128;
2562 num_vs_threads
= 20;
2563 num_gs_threads
= 20;
2564 num_es_threads
= 20;
2565 num_hs_threads
= 20;
2566 num_ls_threads
= 20;
2567 num_ps_stack_entries
= 85;
2568 num_vs_stack_entries
= 85;
2569 num_gs_stack_entries
= 85;
2570 num_es_stack_entries
= 85;
2571 num_hs_stack_entries
= 85;
2572 num_ls_stack_entries
= 85;
2576 num_ps_threads
= 128;
2577 num_vs_threads
= 20;
2578 num_gs_threads
= 20;
2579 num_es_threads
= 20;
2580 num_hs_threads
= 20;
2581 num_ls_threads
= 20;
2582 num_ps_stack_entries
= 85;
2583 num_vs_stack_entries
= 85;
2584 num_gs_stack_entries
= 85;
2585 num_es_stack_entries
= 85;
2586 num_hs_stack_entries
= 85;
2587 num_ls_stack_entries
= 85;
2590 num_ps_threads
= 96;
2591 num_vs_threads
= 16;
2592 num_gs_threads
= 16;
2593 num_es_threads
= 16;
2594 num_hs_threads
= 16;
2595 num_ls_threads
= 16;
2596 num_ps_stack_entries
= 42;
2597 num_vs_stack_entries
= 42;
2598 num_gs_stack_entries
= 42;
2599 num_es_stack_entries
= 42;
2600 num_hs_stack_entries
= 42;
2601 num_ls_stack_entries
= 42;
2604 num_ps_threads
= 96;
2605 num_vs_threads
= 25;
2606 num_gs_threads
= 25;
2607 num_es_threads
= 25;
2608 num_hs_threads
= 25;
2609 num_ls_threads
= 25;
2610 num_ps_stack_entries
= 42;
2611 num_vs_stack_entries
= 42;
2612 num_gs_stack_entries
= 42;
2613 num_es_stack_entries
= 42;
2614 num_hs_stack_entries
= 42;
2615 num_ls_stack_entries
= 42;
2618 num_ps_threads
= 96;
2619 num_vs_threads
= 25;
2620 num_gs_threads
= 25;
2621 num_es_threads
= 25;
2622 num_hs_threads
= 25;
2623 num_ls_threads
= 25;
2624 num_ps_stack_entries
= 85;
2625 num_vs_stack_entries
= 85;
2626 num_gs_stack_entries
= 85;
2627 num_es_stack_entries
= 85;
2628 num_hs_stack_entries
= 85;
2629 num_ls_stack_entries
= 85;
2632 num_ps_threads
= 128;
2633 num_vs_threads
= 20;
2634 num_gs_threads
= 20;
2635 num_es_threads
= 20;
2636 num_hs_threads
= 20;
2637 num_ls_threads
= 20;
2638 num_ps_stack_entries
= 85;
2639 num_vs_stack_entries
= 85;
2640 num_gs_stack_entries
= 85;
2641 num_es_stack_entries
= 85;
2642 num_hs_stack_entries
= 85;
2643 num_ls_stack_entries
= 85;
2646 num_ps_threads
= 128;
2647 num_vs_threads
= 20;
2648 num_gs_threads
= 20;
2649 num_es_threads
= 20;
2650 num_hs_threads
= 20;
2651 num_ls_threads
= 20;
2652 num_ps_stack_entries
= 42;
2653 num_vs_stack_entries
= 42;
2654 num_gs_stack_entries
= 42;
2655 num_es_stack_entries
= 42;
2656 num_hs_stack_entries
= 42;
2657 num_ls_stack_entries
= 42;
2660 num_ps_threads
= 128;
2661 num_vs_threads
= 10;
2662 num_gs_threads
= 10;
2663 num_es_threads
= 10;
2664 num_hs_threads
= 10;
2665 num_ls_threads
= 10;
2666 num_ps_stack_entries
= 42;
2667 num_vs_stack_entries
= 42;
2668 num_gs_stack_entries
= 42;
2669 num_es_stack_entries
= 42;
2670 num_hs_stack_entries
= 42;
2671 num_ls_stack_entries
= 42;
2675 tmp
= S_008C18_NUM_PS_THREADS(num_ps_threads
);
2676 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
2677 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
2678 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
2680 r600_store_config_reg_seq(cb
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, 5);
2681 r600_store_value(cb
, tmp
); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2683 tmp
= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
2684 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
2685 r600_store_value(cb
, tmp
); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2687 tmp
= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2688 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2689 r600_store_value(cb
, tmp
); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2691 tmp
= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2692 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2693 r600_store_value(cb
, tmp
); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2695 tmp
= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
2696 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
2697 r600_store_value(cb
, tmp
); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2699 r600_store_config_reg(cb
, R_008E2C_SQ_LDS_RESOURCE_MGMT
,
2700 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2702 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2703 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2705 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2706 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2707 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2708 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2709 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2710 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2711 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2713 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2714 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2715 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2716 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2717 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2719 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2720 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2721 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2722 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2723 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2724 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2725 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2726 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2727 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2728 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2729 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2730 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2731 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2732 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2734 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2735 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
2736 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2738 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2740 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2742 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2743 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2744 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2746 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2748 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2750 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2751 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2752 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2754 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2 * R600_MAX_VIEWPORTS
);
2755 for (tmp
= 0; tmp
< R600_MAX_VIEWPORTS
; tmp
++) {
2756 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2757 r600_store_value(cb
, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2760 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2761 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2763 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2764 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2765 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2766 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2768 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2769 r600_store_value(cb
, fui(1.0)); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2770 r600_store_value(cb
, fui(1.0)); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2771 r600_store_value(cb
, fui(1.0)); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2772 r600_store_value(cb
, fui(1.0)); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2774 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2775 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2776 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2778 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2779 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2780 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2782 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2783 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2784 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2786 /* to avoid GPU doing any preloading of constant from random address */
2787 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2788 for (i
= 0; i
< 16; i
++)
2789 r600_store_value(cb
, 0);
2791 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2792 for (i
= 0; i
< 16; i
++)
2793 r600_store_value(cb
, 0);
2795 r600_store_context_reg_seq(cb
, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
, 16);
2796 for (i
= 0; i
< 16; i
++)
2797 r600_store_value(cb
, 0);
2799 r600_store_context_reg_seq(cb
, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
, 16);
2800 for (i
= 0; i
< 16; i
++)
2801 r600_store_value(cb
, 0);
2803 r600_store_context_reg_seq(cb
, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0
, 16);
2804 for (i
= 0; i
< 16; i
++)
2805 r600_store_value(cb
, 0);
2807 r600_store_context_reg(cb
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0);
2809 if (rctx
->screen
->b
.has_streamout
) {
2810 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2813 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
2814 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
2815 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2816 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
2817 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2818 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2819 r600_store_context_reg(cb
, R_0288EC_SQ_LDS_ALLOC_PS
, 0);
2820 r600_store_context_reg(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 0);
2822 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2823 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2824 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (64 * 4), 0x01000FFF);
2827 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2829 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2830 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2831 struct r600_shader
*rshader
= &shader
->shader
;
2832 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
= 0;
2833 int pos_index
= -1, face_index
= -1, fixed_pt_position_index
= -1;
2835 boolean have_perspective
= FALSE
, have_linear
= FALSE
;
2836 static const unsigned spi_baryc_enable_bit
[6] = {
2837 S_0286E0_PERSP_SAMPLE_ENA(1),
2838 S_0286E0_PERSP_CENTER_ENA(1),
2839 S_0286E0_PERSP_CENTROID_ENA(1),
2840 S_0286E0_LINEAR_SAMPLE_ENA(1),
2841 S_0286E0_LINEAR_CENTER_ENA(1),
2842 S_0286E0_LINEAR_CENTROID_ENA(1)
2844 unsigned spi_baryc_cntl
= 0, sid
, tmp
, num
= 0;
2845 unsigned z_export
= 0, stencil_export
= 0, mask_export
= 0;
2846 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
2847 uint32_t spi_ps_input_cntl
[32];
2850 r600_init_command_buffer(cb
, 64);
2855 for (i
= 0; i
< rshader
->ninput
; i
++) {
2856 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2857 POSITION goes via GPRs from the SC so isn't counted */
2858 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2860 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
) {
2861 if (face_index
== -1)
2864 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
) {
2865 if (face_index
== -1)
2866 face_index
= i
; /* lives in same register, same enable bit */
2868 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_SAMPLEID
) {
2869 fixed_pt_position_index
= i
;
2873 int k
= eg_get_interpolator_index(
2874 rshader
->input
[i
].interpolate
,
2875 rshader
->input
[i
].interpolate_location
);
2877 spi_baryc_cntl
|= spi_baryc_enable_bit
[k
];
2878 have_perspective
|= k
< 3;
2879 have_linear
|= !(k
< 3);
2883 sid
= rshader
->input
[i
].spi_sid
;
2886 tmp
= S_028644_SEMANTIC(sid
);
2888 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2889 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2890 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2891 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
)) {
2892 tmp
|= S_028644_FLAT_SHADE(1);
2895 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2896 (sprite_coord_enable
& (1 << rshader
->input
[i
].sid
))) {
2897 tmp
|= S_028644_PT_SPRITE_TEX(1);
2900 spi_ps_input_cntl
[num
++] = tmp
;
2904 r600_store_context_reg_seq(cb
, R_028644_SPI_PS_INPUT_CNTL_0
, num
);
2905 r600_store_array(cb
, num
, spi_ps_input_cntl
);
2907 for (i
= 0; i
< rshader
->noutput
; i
++) {
2908 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2910 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2912 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
&&
2913 rctx
->framebuffer
.nr_samples
> 1 && rctx
->ps_iter_samples
> 0)
2916 if (rshader
->uses_kill
)
2917 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2919 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
2920 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export
);
2921 db_shader_control
|= S_02880C_MASK_EXPORT_ENABLE(mask_export
);
2924 for (i
= 0; i
< rshader
->noutput
; i
++) {
2925 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2926 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
||
2927 rshader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
)
2931 num_cout
= rshader
->nr_ps_color_exports
;
2933 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
2935 /* always at least export 1 component per pixel */
2938 shader
->nr_ps_color_outputs
= num_cout
;
2941 have_perspective
= TRUE
;
2943 if (!spi_baryc_cntl
)
2944 spi_baryc_cntl
|= spi_baryc_enable_bit
[0];
2946 if (!have_perspective
&& !have_linear
)
2947 have_perspective
= TRUE
;
2949 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
2950 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
2951 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
2953 if (pos_index
!= -1) {
2954 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
2955 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].interpolate_location
== TGSI_INTERPOLATE_LOC_CENTROID
) |
2956 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
2957 spi_input_z
|= S_0286D8_PROVIDE_Z_TO_SPI(1);
2960 spi_ps_in_control_1
= 0;
2961 if (face_index
!= -1) {
2962 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2963 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2965 if (fixed_pt_position_index
!= -1) {
2966 spi_ps_in_control_1
|= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2967 S_0286D0_FIXED_PT_POSITION_ADDR(rshader
->input
[fixed_pt_position_index
].gpr
);
2970 r600_store_context_reg_seq(cb
, R_0286CC_SPI_PS_IN_CONTROL_0
, 2);
2971 r600_store_value(cb
, spi_ps_in_control_0
); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2972 r600_store_value(cb
, spi_ps_in_control_1
); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2974 r600_store_context_reg(cb
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
2975 r600_store_context_reg(cb
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
2976 r600_store_context_reg(cb
, R_02884C_SQ_PGM_EXPORTS_PS
, exports_ps
);
2978 r600_store_context_reg_seq(cb
, R_028840_SQ_PGM_START_PS
, 2);
2979 r600_store_value(cb
, shader
->bo
->gpu_address
>> 8);
2980 r600_store_value(cb
, /* R_028844_SQ_PGM_RESOURCES_PS */
2981 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
2982 S_028844_PRIME_CACHE_ON_DRAW(1) |
2983 S_028844_STACK_SIZE(rshader
->bc
.nstack
));
2984 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2986 shader
->db_shader_control
= db_shader_control
;
2987 shader
->ps_depth_export
= z_export
| stencil_export
| mask_export
;
2989 shader
->sprite_coord_enable
= sprite_coord_enable
;
2990 if (rctx
->rasterizer
)
2991 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
2994 void evergreen_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2996 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2997 struct r600_shader
*rshader
= &shader
->shader
;
2999 r600_init_command_buffer(cb
, 32);
3001 r600_store_context_reg(cb
, R_028890_SQ_PGM_RESOURCES_ES
,
3002 S_028890_NUM_GPRS(rshader
->bc
.ngpr
) |
3003 S_028890_STACK_SIZE(rshader
->bc
.nstack
));
3004 r600_store_context_reg(cb
, R_02888C_SQ_PGM_START_ES
,
3005 shader
->bo
->gpu_address
>> 8);
3006 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3009 void evergreen_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3011 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3012 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3013 struct r600_shader
*rshader
= &shader
->shader
;
3014 struct r600_shader
*cp_shader
= &shader
->gs_copy_shader
->shader
;
3015 unsigned gsvs_itemsize
=
3016 (cp_shader
->ring_item_size
* rshader
->gs_max_out_vertices
) >> 2;
3018 r600_init_command_buffer(cb
, 64);
3020 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3022 r600_store_context_reg(cb
, R_028AB8_VGT_VTX_CNT_EN
, 1);
3024 r600_store_context_reg(cb
, R_028B38_VGT_GS_MAX_VERT_OUT
,
3025 S_028B38_MAX_VERT_OUT(rshader
->gs_max_out_vertices
));
3026 r600_store_context_reg(cb
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
3027 r600_conv_prim_to_gs_out(rshader
->gs_output_prim
));
3029 if (rctx
->screen
->b
.info
.drm_minor
>= 35) {
3030 r600_store_context_reg(cb
, R_028B90_VGT_GS_INSTANCE_CNT
,
3031 S_028B90_CNT(MIN2(rshader
->gs_num_invocations
, 127)) |
3032 S_028B90_ENABLE(rshader
->gs_num_invocations
> 0));
3034 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
3035 r600_store_value(cb
, cp_shader
->ring_item_size
>> 2);
3036 r600_store_value(cb
, 0);
3037 r600_store_value(cb
, 0);
3038 r600_store_value(cb
, 0);
3040 r600_store_context_reg(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
,
3041 (rshader
->ring_item_size
) >> 2);
3043 r600_store_context_reg(cb
, R_028904_SQ_GSVS_RING_ITEMSIZE
,
3046 r600_store_context_reg_seq(cb
, R_02892C_SQ_GSVS_RING_OFFSET_1
, 3);
3047 r600_store_value(cb
, gsvs_itemsize
);
3048 r600_store_value(cb
, gsvs_itemsize
);
3049 r600_store_value(cb
, gsvs_itemsize
);
3051 /* FIXME calculate these values somehow ??? */
3052 r600_store_context_reg_seq(cb
, R_028A54_GS_PER_ES
, 3);
3053 r600_store_value(cb
, 0x80); /* GS_PER_ES */
3054 r600_store_value(cb
, 0x100); /* ES_PER_GS */
3055 r600_store_value(cb
, 0x2); /* GS_PER_VS */
3057 r600_store_context_reg(cb
, R_028878_SQ_PGM_RESOURCES_GS
,
3058 S_028878_NUM_GPRS(rshader
->bc
.ngpr
) |
3059 S_028878_STACK_SIZE(rshader
->bc
.nstack
));
3060 r600_store_context_reg(cb
, R_028874_SQ_PGM_START_GS
,
3061 shader
->bo
->gpu_address
>> 8);
3062 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3066 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3068 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3069 struct r600_shader
*rshader
= &shader
->shader
;
3070 unsigned spi_vs_out_id
[10] = {};
3071 unsigned i
, tmp
, nparams
= 0;
3073 for (i
= 0; i
< rshader
->noutput
; i
++) {
3074 if (rshader
->output
[i
].spi_sid
) {
3075 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
3076 spi_vs_out_id
[nparams
/ 4] |= tmp
;
3081 r600_init_command_buffer(cb
, 32);
3083 r600_store_context_reg_seq(cb
, R_02861C_SPI_VS_OUT_ID_0
, 10);
3084 for (i
= 0; i
< 10; i
++) {
3085 r600_store_value(cb
, spi_vs_out_id
[i
]);
3088 /* Certain attributes (position, psize, etc.) don't count as params.
3089 * VS is required to export at least one param and r600_shader_from_tgsi()
3090 * takes care of adding a dummy export.
3095 r600_store_context_reg(cb
, R_0286C4_SPI_VS_OUT_CONFIG
,
3096 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
3097 r600_store_context_reg(cb
, R_028860_SQ_PGM_RESOURCES_VS
,
3098 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
3099 S_028860_STACK_SIZE(rshader
->bc
.nstack
));
3100 if (rshader
->vs_position_window_space
) {
3101 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
3102 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3104 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
3105 S_028818_VTX_W0_FMT(1) |
3106 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3107 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3108 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3111 r600_store_context_reg(cb
, R_02885C_SQ_PGM_START_VS
,
3112 shader
->bo
->gpu_address
>> 8);
3113 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3115 shader
->pa_cl_vs_out_cntl
=
3116 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
3117 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
3118 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
3119 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
) |
3120 S_02881C_USE_VTX_EDGE_FLAG(rshader
->vs_out_edgeflag
) |
3121 S_02881C_USE_VTX_VIEWPORT_INDX(rshader
->vs_out_viewport
) |
3122 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader
->vs_out_layer
);
3125 void *evergreen_create_resolve_blend(struct r600_context
*rctx
)
3127 struct pipe_blend_state blend
;
3129 memset(&blend
, 0, sizeof(blend
));
3130 blend
.independent_blend_enable
= true;
3131 blend
.rt
[0].colormask
= 0xf;
3132 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_CB_RESOLVE
);
3135 void *evergreen_create_decompress_blend(struct r600_context
*rctx
)
3137 struct pipe_blend_state blend
;
3138 unsigned mode
= rctx
->screen
->has_compressed_msaa_texturing
?
3139 V_028808_CB_FMASK_DECOMPRESS
: V_028808_CB_DECOMPRESS
;
3141 memset(&blend
, 0, sizeof(blend
));
3142 blend
.independent_blend_enable
= true;
3143 blend
.rt
[0].colormask
= 0xf;
3144 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3147 void *evergreen_create_fastclear_blend(struct r600_context
*rctx
)
3149 struct pipe_blend_state blend
;
3150 unsigned mode
= V_028808_CB_ELIMINATE_FAST_CLEAR
;
3152 memset(&blend
, 0, sizeof(blend
));
3153 blend
.independent_blend_enable
= true;
3154 blend
.rt
[0].colormask
= 0xf;
3155 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3158 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
)
3160 struct pipe_depth_stencil_alpha_state dsa
= {{0}};
3162 return rctx
->b
.b
.create_depth_stencil_alpha_state(&rctx
->b
.b
, &dsa
);
3165 void evergreen_update_db_shader_control(struct r600_context
* rctx
)
3168 unsigned db_shader_control
;
3170 if (!rctx
->ps_shader
) {
3174 dual_export
= rctx
->framebuffer
.export_16bpc
&&
3175 !rctx
->ps_shader
->current
->ps_depth_export
;
3177 db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
3178 S_02880C_DUAL_EXPORT_ENABLE(dual_export
) |
3179 S_02880C_DB_SOURCE_FORMAT(dual_export
? V_02880C_EXPORT_DB_TWO
:
3180 V_02880C_EXPORT_DB_FULL
) |
3181 S_02880C_ALPHA_TO_MASK_DISABLE(rctx
->framebuffer
.cb0_is_integer
);
3183 /* When alpha test is enabled we can't trust the hw to make the proper
3184 * decision on the order in which ztest should be run related to fragment
3187 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3188 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3189 * execution and thus after alpha test so if discarded by the alpha test
3190 * the z value is not written.
3191 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3192 * get a hang unless you flush the DB in between. For now just use
3195 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
3196 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
3198 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
3201 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
) {
3202 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
3203 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
3207 static void evergreen_dma_copy_tile(struct r600_context
*rctx
,
3208 struct pipe_resource
*dst
,
3213 struct pipe_resource
*src
,
3218 unsigned copy_height
,
3222 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.dma
.cs
;
3223 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3224 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3225 unsigned array_mode
, lbpp
, pitch_tile_max
, slice_tile_max
, size
;
3226 unsigned ncopy
, height
, cheight
, detile
, i
, x
, y
, z
, src_mode
, dst_mode
;
3227 unsigned sub_cmd
, bank_h
, bank_w
, mt_aspect
, nbanks
, tile_split
, non_disp_tiling
= 0;
3228 uint64_t base
, addr
;
3230 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
3231 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
3232 /* downcast linear aligned to linear to simplify test */
3233 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
3234 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
3235 assert(dst_mode
!= src_mode
);
3237 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3238 if (util_format_has_depth(util_format_description(src
->format
)))
3239 non_disp_tiling
= 1;
3242 sub_cmd
= EG_DMA_COPY_TILED
;
3243 lbpp
= util_logbase2(bpp
);
3244 pitch_tile_max
= ((pitch
/ bpp
) / 8) - 1;
3245 nbanks
= eg_num_banks(rctx
->screen
->b
.tiling_info
.num_banks
);
3247 if (dst_mode
== RADEON_SURF_MODE_LINEAR
) {
3249 array_mode
= evergreen_array_mode(src_mode
);
3250 slice_tile_max
= (rsrc
->surface
.level
[src_level
].nblk_x
* rsrc
->surface
.level
[src_level
].nblk_y
) / (8*8);
3251 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3252 /* linear height must be the same as the slice tile max height, it's ok even
3253 * if the linear destination/source have smaller heigh as the size of the
3254 * dma packet will be using the copy_height which is always smaller or equal
3255 * to the linear height
3257 height
= rsrc
->surface
.level
[src_level
].npix_y
;
3262 base
= rsrc
->surface
.level
[src_level
].offset
;
3263 addr
= rdst
->surface
.level
[dst_level
].offset
;
3264 addr
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
3265 addr
+= dst_y
* pitch
+ dst_x
* bpp
;
3266 bank_h
= eg_bank_wh(rsrc
->surface
.bankh
);
3267 bank_w
= eg_bank_wh(rsrc
->surface
.bankw
);
3268 mt_aspect
= eg_macro_tile_aspect(rsrc
->surface
.mtilea
);
3269 tile_split
= eg_tile_split(rsrc
->surface
.tile_split
);
3270 base
+= rsrc
->resource
.gpu_address
;
3271 addr
+= rdst
->resource
.gpu_address
;
3274 array_mode
= evergreen_array_mode(dst_mode
);
3275 slice_tile_max
= (rdst
->surface
.level
[dst_level
].nblk_x
* rdst
->surface
.level
[dst_level
].nblk_y
) / (8*8);
3276 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3277 /* linear height must be the same as the slice tile max height, it's ok even
3278 * if the linear destination/source have smaller heigh as the size of the
3279 * dma packet will be using the copy_height which is always smaller or equal
3280 * to the linear height
3282 height
= rdst
->surface
.level
[dst_level
].npix_y
;
3287 base
= rdst
->surface
.level
[dst_level
].offset
;
3288 addr
= rsrc
->surface
.level
[src_level
].offset
;
3289 addr
+= rsrc
->surface
.level
[src_level
].slice_size
* src_z
;
3290 addr
+= src_y
* pitch
+ src_x
* bpp
;
3291 bank_h
= eg_bank_wh(rdst
->surface
.bankh
);
3292 bank_w
= eg_bank_wh(rdst
->surface
.bankw
);
3293 mt_aspect
= eg_macro_tile_aspect(rdst
->surface
.mtilea
);
3294 tile_split
= eg_tile_split(rdst
->surface
.tile_split
);
3295 base
+= rdst
->resource
.gpu_address
;
3296 addr
+= rsrc
->resource
.gpu_address
;
3299 size
= (copy_height
* pitch
) / 4;
3300 ncopy
= (size
/ EG_DMA_COPY_MAX_SIZE
) + !!(size
% EG_DMA_COPY_MAX_SIZE
);
3301 r600_need_dma_space(&rctx
->b
, ncopy
* 9);
3303 for (i
= 0; i
< ncopy
; i
++) {
3304 cheight
= copy_height
;
3305 if (((cheight
* pitch
) / 4) > EG_DMA_COPY_MAX_SIZE
) {
3306 cheight
= (EG_DMA_COPY_MAX_SIZE
* 4) / pitch
;
3308 size
= (cheight
* pitch
) / 4;
3309 /* emit reloc before writing cs so that cs is always in consistent state */
3310 r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.dma
, &rsrc
->resource
,
3311 RADEON_USAGE_READ
, RADEON_PRIO_MIN
);
3312 r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.dma
, &rdst
->resource
,
3313 RADEON_USAGE_WRITE
, RADEON_PRIO_MIN
);
3314 cs
->buf
[cs
->cdw
++] = DMA_PACKET(DMA_PACKET_COPY
, sub_cmd
, size
);
3315 cs
->buf
[cs
->cdw
++] = base
>> 8;
3316 cs
->buf
[cs
->cdw
++] = (detile
<< 31) | (array_mode
<< 27) |
3317 (lbpp
<< 24) | (bank_h
<< 21) |
3318 (bank_w
<< 18) | (mt_aspect
<< 16);
3319 cs
->buf
[cs
->cdw
++] = (pitch_tile_max
<< 0) | ((height
- 1) << 16);
3320 cs
->buf
[cs
->cdw
++] = (slice_tile_max
<< 0);
3321 cs
->buf
[cs
->cdw
++] = (x
<< 0) | (z
<< 18);
3322 cs
->buf
[cs
->cdw
++] = (y
<< 0) | (tile_split
<< 21) | (nbanks
<< 25) | (non_disp_tiling
<< 28);
3323 cs
->buf
[cs
->cdw
++] = addr
& 0xfffffffc;
3324 cs
->buf
[cs
->cdw
++] = (addr
>> 32UL) & 0xff;
3325 copy_height
-= cheight
;
3326 addr
+= cheight
* pitch
;
3331 static void evergreen_dma_copy(struct pipe_context
*ctx
,
3332 struct pipe_resource
*dst
,
3334 unsigned dstx
, unsigned dsty
, unsigned dstz
,
3335 struct pipe_resource
*src
,
3337 const struct pipe_box
*src_box
)
3339 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3340 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3341 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3342 unsigned dst_pitch
, src_pitch
, bpp
, dst_mode
, src_mode
, copy_height
;
3343 unsigned src_w
, dst_w
;
3344 unsigned src_x
, src_y
;
3345 unsigned dst_x
= dstx
, dst_y
= dsty
, dst_z
= dstz
;
3347 if (rctx
->b
.rings
.dma
.cs
== NULL
) {
3351 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
3352 evergreen_dma_copy_buffer(rctx
, dst
, src
, dst_x
, src_box
->x
, src_box
->width
);
3356 if (src
->format
!= dst
->format
|| src_box
->depth
> 1 ||
3357 rdst
->dirty_level_mask
!= 0) {
3361 if (rsrc
->dirty_level_mask
) {
3362 ctx
->flush_resource(ctx
, src
);
3365 src_x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
3366 dst_x
= util_format_get_nblocksx(src
->format
, dst_x
);
3367 src_y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
3368 dst_y
= util_format_get_nblocksy(src
->format
, dst_y
);
3370 bpp
= rdst
->surface
.bpe
;
3371 dst_pitch
= rdst
->surface
.level
[dst_level
].pitch_bytes
;
3372 src_pitch
= rsrc
->surface
.level
[src_level
].pitch_bytes
;
3373 src_w
= rsrc
->surface
.level
[src_level
].npix_x
;
3374 dst_w
= rdst
->surface
.level
[dst_level
].npix_x
;
3375 copy_height
= src_box
->height
/ rsrc
->surface
.blk_h
;
3377 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
3378 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
3379 /* downcast linear aligned to linear to simplify test */
3380 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
3381 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
3383 if (src_pitch
!= dst_pitch
|| src_box
->x
|| dst_x
|| src_w
!= dst_w
) {
3384 /* FIXME evergreen can do partial blit */
3387 /* the x test here are currently useless (because we don't support partial blit)
3388 * but keep them around so we don't forget about those
3390 if (src_pitch
% 8 || src_box
->x
% 8 || dst_x
% 8 || src_box
->y
% 8 || dst_y
% 8) {
3394 /* 128 bpp surfaces require non_disp_tiling for both
3395 * tiled and linear buffers on cayman. However, async
3396 * DMA only supports it on the tiled side. As such
3397 * the tile order is backwards after a L2T/T2L packet.
3399 if ((rctx
->b
.chip_class
== CAYMAN
) &&
3400 (src_mode
!= dst_mode
) &&
3401 (util_format_get_blocksize(src
->format
) >= 16)) {
3405 if (src_mode
== dst_mode
) {
3406 uint64_t dst_offset
, src_offset
;
3407 /* simple dma blit would do NOTE code here assume :
3410 * dst_pitch == src_pitch
3412 src_offset
= rsrc
->surface
.level
[src_level
].offset
;
3413 src_offset
+= rsrc
->surface
.level
[src_level
].slice_size
* src_box
->z
;
3414 src_offset
+= src_y
* src_pitch
+ src_x
* bpp
;
3415 dst_offset
= rdst
->surface
.level
[dst_level
].offset
;
3416 dst_offset
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
3417 dst_offset
+= dst_y
* dst_pitch
+ dst_x
* bpp
;
3418 evergreen_dma_copy_buffer(rctx
, dst
, src
, dst_offset
, src_offset
,
3419 src_box
->height
* src_pitch
);
3421 evergreen_dma_copy_tile(rctx
, dst
, dst_level
, dst_x
, dst_y
, dst_z
,
3422 src
, src_level
, src_x
, src_y
, src_box
->z
,
3423 copy_height
, dst_pitch
, bpp
);
3428 r600_resource_copy_region(ctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
3429 src
, src_level
, src_box
);
3432 void evergreen_init_state_functions(struct r600_context
*rctx
)
3437 * To avoid GPU lockup registers must be emited in a specific order
3438 * (no kidding ...). The order below is important and have been
3439 * partialy infered from analyzing fglrx command stream.
3441 * Don't reorder atom without carefully checking the effect (GPU lockup
3442 * or piglit regression).
3446 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, evergreen_emit_framebuffer_state
, 0);
3448 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, evergreen_emit_vs_constant_buffers
, 0);
3449 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, evergreen_emit_gs_constant_buffers
, 0);
3450 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, evergreen_emit_ps_constant_buffers
, 0);
3451 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_COMPUTE
].atom
, id
++, evergreen_emit_cs_constant_buffers
, 0);
3452 /* shader program */
3453 r600_init_atom(rctx
, &rctx
->cs_shader_state
.atom
, id
++, evergreen_emit_cs_shader
, 0);
3455 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, evergreen_emit_vs_sampler_states
, 0);
3456 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, evergreen_emit_gs_sampler_states
, 0);
3457 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, evergreen_emit_ps_sampler_states
, 0);
3458 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
].states
.atom
, id
++, evergreen_emit_cs_sampler_states
, 0);
3460 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, evergreen_fs_emit_vertex_buffers
, 0);
3461 r600_init_atom(rctx
, &rctx
->cs_vertex_buffer_state
.atom
, id
++, evergreen_cs_emit_vertex_buffers
, 0);
3462 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, evergreen_emit_vs_sampler_views
, 0);
3463 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, evergreen_emit_gs_sampler_views
, 0);
3464 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, evergreen_emit_ps_sampler_views
, 0);
3465 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
].views
.atom
, id
++, evergreen_emit_cs_sampler_views
, 0);
3467 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 10);
3469 if (rctx
->b
.chip_class
== EVERGREEN
) {
3470 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, evergreen_emit_sample_mask
, 3);
3472 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, cayman_emit_sample_mask
, 4);
3474 rctx
->sample_mask
.sample_mask
= ~0;
3476 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
3477 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
3478 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
3479 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, evergreen_emit_cb_misc_state
, 4);
3480 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 6);
3481 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, evergreen_emit_clip_state
, 26);
3482 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, evergreen_emit_db_misc_state
, 10);
3483 r600_init_atom(rctx
, &rctx
->db_state
.atom
, id
++, evergreen_emit_db_state
, 14);
3484 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
3485 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, evergreen_emit_polygon_offset
, 6);
3486 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
3487 for (i
= 0; i
< R600_MAX_VIEWPORTS
; i
++) {
3488 r600_init_atom(rctx
, &rctx
->viewport
[i
].atom
, id
++, r600_emit_viewport_state
, 8);
3489 r600_init_atom(rctx
, &rctx
->scissor
[i
].atom
, id
++, evergreen_emit_scissor_state
, 4);
3490 rctx
->viewport
[i
].idx
= i
;
3491 rctx
->scissor
[i
].idx
= i
;
3493 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
3494 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, evergreen_emit_vertex_fetch_shader
, 5);
3495 r600_add_atom(rctx
, &rctx
->b
.streamout
.begin_atom
, id
++);
3496 r600_add_atom(rctx
, &rctx
->b
.streamout
.enable_atom
, id
++);
3497 r600_init_atom(rctx
, &rctx
->vertex_shader
.atom
, id
++, r600_emit_shader
, 23);
3498 r600_init_atom(rctx
, &rctx
->pixel_shader
.atom
, id
++, r600_emit_shader
, 0);
3499 r600_init_atom(rctx
, &rctx
->geometry_shader
.atom
, id
++, r600_emit_shader
, 0);
3500 r600_init_atom(rctx
, &rctx
->export_shader
.atom
, id
++, r600_emit_shader
, 0);
3501 r600_init_atom(rctx
, &rctx
->shader_stages
.atom
, id
++, evergreen_emit_shader_stages
, 6);
3502 r600_init_atom(rctx
, &rctx
->gs_rings
.atom
, id
++, evergreen_emit_gs_rings
, 26);
3504 rctx
->b
.b
.create_blend_state
= evergreen_create_blend_state
;
3505 rctx
->b
.b
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
3506 rctx
->b
.b
.create_rasterizer_state
= evergreen_create_rs_state
;
3507 rctx
->b
.b
.create_sampler_state
= evergreen_create_sampler_state
;
3508 rctx
->b
.b
.create_sampler_view
= evergreen_create_sampler_view
;
3509 rctx
->b
.b
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
3510 rctx
->b
.b
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
3511 rctx
->b
.b
.set_min_samples
= evergreen_set_min_samples
;
3512 rctx
->b
.b
.set_scissor_states
= evergreen_set_scissor_states
;
3514 if (rctx
->b
.chip_class
== EVERGREEN
)
3515 rctx
->b
.b
.get_sample_position
= evergreen_get_sample_position
;
3517 rctx
->b
.b
.get_sample_position
= cayman_get_sample_position
;
3518 rctx
->b
.dma_copy
= evergreen_dma_copy
;
3520 evergreen_init_compute_state_functions(rctx
);