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anv/pipeline: Get rid of the no kernel input parameters hack
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static inline unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
39 break;
40 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
41 break;
42 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
43 default:
44 case RADEON_SURF_MODE_LINEAR: return V_028C70_ARRAY_LINEAR_GENERAL;
45 }
46 }
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
174 {
175 switch (dim) {
176 default:
177 case PIPE_TEXTURE_1D:
178 return V_030000_SQ_TEX_DIM_1D;
179 case PIPE_TEXTURE_1D_ARRAY:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY;
181 case PIPE_TEXTURE_2D:
182 case PIPE_TEXTURE_RECT:
183 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
184 V_030000_SQ_TEX_DIM_2D;
185 case PIPE_TEXTURE_2D_ARRAY:
186 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
187 V_030000_SQ_TEX_DIM_2D_ARRAY;
188 case PIPE_TEXTURE_3D:
189 return V_030000_SQ_TEX_DIM_3D;
190 case PIPE_TEXTURE_CUBE:
191 case PIPE_TEXTURE_CUBE_ARRAY:
192 return V_030000_SQ_TEX_DIM_CUBEMAP;
193 }
194 }
195
196 static uint32_t r600_translate_dbformat(enum pipe_format format)
197 {
198 switch (format) {
199 case PIPE_FORMAT_Z16_UNORM:
200 return V_028040_Z_16;
201 case PIPE_FORMAT_Z24X8_UNORM:
202 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
203 case PIPE_FORMAT_X8Z24_UNORM:
204 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
205 return V_028040_Z_24;
206 case PIPE_FORMAT_Z32_FLOAT:
207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
208 return V_028040_Z_32_FLOAT;
209 default:
210 return ~0U;
211 }
212 }
213
214 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
215 {
216 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
217 }
218
219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
220 {
221 return r600_translate_colorformat(chip, format) != ~0U &&
222 r600_translate_colorswap(format) != ~0U;
223 }
224
225 static bool r600_is_zs_format_supported(enum pipe_format format)
226 {
227 return r600_translate_dbformat(format) != ~0U;
228 }
229
230 boolean evergreen_is_format_supported(struct pipe_screen *screen,
231 enum pipe_format format,
232 enum pipe_texture_target target,
233 unsigned sample_count,
234 unsigned usage)
235 {
236 struct r600_screen *rscreen = (struct r600_screen*)screen;
237 unsigned retval = 0;
238
239 if (target >= PIPE_MAX_TEXTURE_TYPES) {
240 R600_ERR("r600: unsupported texture type %d\n", target);
241 return FALSE;
242 }
243
244 if (!util_format_is_supported(format, usage))
245 return FALSE;
246
247 if (sample_count > 1) {
248 if (!rscreen->has_msaa)
249 return FALSE;
250
251 switch (sample_count) {
252 case 2:
253 case 4:
254 case 8:
255 break;
256 default:
257 return FALSE;
258 }
259 }
260
261 if (usage & PIPE_BIND_SAMPLER_VIEW) {
262 if (target == PIPE_BUFFER) {
263 if (r600_is_vertex_format_supported(format))
264 retval |= PIPE_BIND_SAMPLER_VIEW;
265 } else {
266 if (r600_is_sampler_format_supported(screen, format))
267 retval |= PIPE_BIND_SAMPLER_VIEW;
268 }
269 }
270
271 if ((usage & (PIPE_BIND_RENDER_TARGET |
272 PIPE_BIND_DISPLAY_TARGET |
273 PIPE_BIND_SCANOUT |
274 PIPE_BIND_SHARED |
275 PIPE_BIND_BLENDABLE)) &&
276 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
277 retval |= usage &
278 (PIPE_BIND_RENDER_TARGET |
279 PIPE_BIND_DISPLAY_TARGET |
280 PIPE_BIND_SCANOUT |
281 PIPE_BIND_SHARED);
282 if (!util_format_is_pure_integer(format) &&
283 !util_format_is_depth_or_stencil(format))
284 retval |= usage & PIPE_BIND_BLENDABLE;
285 }
286
287 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
288 r600_is_zs_format_supported(format)) {
289 retval |= PIPE_BIND_DEPTH_STENCIL;
290 }
291
292 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
293 r600_is_vertex_format_supported(format)) {
294 retval |= PIPE_BIND_VERTEX_BUFFER;
295 }
296
297 if (usage & PIPE_BIND_TRANSFER_READ)
298 retval |= PIPE_BIND_TRANSFER_READ;
299 if (usage & PIPE_BIND_TRANSFER_WRITE)
300 retval |= PIPE_BIND_TRANSFER_WRITE;
301
302 return retval == usage;
303 }
304
305 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
306 const struct pipe_blend_state *state, int mode)
307 {
308 uint32_t color_control = 0, target_mask = 0;
309 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
310
311 if (!blend) {
312 return NULL;
313 }
314
315 r600_init_command_buffer(&blend->buffer, 20);
316 r600_init_command_buffer(&blend->buffer_no_blend, 20);
317
318 if (state->logicop_enable) {
319 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
320 } else {
321 color_control |= (0xcc << 16);
322 }
323 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
324 if (state->independent_blend_enable) {
325 for (int i = 0; i < 8; i++) {
326 target_mask |= (state->rt[i].colormask << (4 * i));
327 }
328 } else {
329 for (int i = 0; i < 8; i++) {
330 target_mask |= (state->rt[0].colormask << (4 * i));
331 }
332 }
333
334 /* only have dual source on MRT0 */
335 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
336 blend->cb_target_mask = target_mask;
337 blend->alpha_to_one = state->alpha_to_one;
338
339 if (target_mask)
340 color_control |= S_028808_MODE(mode);
341 else
342 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
343
344
345 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
346 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
347 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
348 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
349 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
350 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
351 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
352 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
353
354 /* Copy over the dwords set so far into buffer_no_blend.
355 * Only the CB_BLENDi_CONTROL registers must be set after this. */
356 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
357 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
358
359 for (int i = 0; i < 8; i++) {
360 /* state->rt entries > 0 only written if independent blending */
361 const int j = state->independent_blend_enable ? i : 0;
362
363 unsigned eqRGB = state->rt[j].rgb_func;
364 unsigned srcRGB = state->rt[j].rgb_src_factor;
365 unsigned dstRGB = state->rt[j].rgb_dst_factor;
366 unsigned eqA = state->rt[j].alpha_func;
367 unsigned srcA = state->rt[j].alpha_src_factor;
368 unsigned dstA = state->rt[j].alpha_dst_factor;
369 uint32_t bc = 0;
370
371 r600_store_value(&blend->buffer_no_blend, 0);
372
373 if (!state->rt[j].blend_enable) {
374 r600_store_value(&blend->buffer, 0);
375 continue;
376 }
377
378 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
379 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
380 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
381 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
382
383 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
384 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
385 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
386 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
387 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
388 }
389 r600_store_value(&blend->buffer, bc);
390 }
391 return blend;
392 }
393
394 static void *evergreen_create_blend_state(struct pipe_context *ctx,
395 const struct pipe_blend_state *state)
396 {
397
398 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
399 }
400
401 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
402 const struct pipe_depth_stencil_alpha_state *state)
403 {
404 unsigned db_depth_control, alpha_test_control, alpha_ref;
405 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
406
407 if (!dsa) {
408 return NULL;
409 }
410
411 r600_init_command_buffer(&dsa->buffer, 3);
412
413 dsa->valuemask[0] = state->stencil[0].valuemask;
414 dsa->valuemask[1] = state->stencil[1].valuemask;
415 dsa->writemask[0] = state->stencil[0].writemask;
416 dsa->writemask[1] = state->stencil[1].writemask;
417 dsa->zwritemask = state->depth.writemask;
418
419 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
420 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
421 S_028800_ZFUNC(state->depth.func);
422
423 /* stencil */
424 if (state->stencil[0].enabled) {
425 db_depth_control |= S_028800_STENCIL_ENABLE(1);
426 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
427 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
428 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
429 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
430
431 if (state->stencil[1].enabled) {
432 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
433 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
434 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
435 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
436 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
437 }
438 }
439
440 /* alpha */
441 alpha_test_control = 0;
442 alpha_ref = 0;
443 if (state->alpha.enabled) {
444 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
445 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
446 alpha_ref = fui(state->alpha.ref_value);
447 }
448 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
449 dsa->alpha_ref = alpha_ref;
450
451 /* misc */
452 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
453 return dsa;
454 }
455
456 static void *evergreen_create_rs_state(struct pipe_context *ctx,
457 const struct pipe_rasterizer_state *state)
458 {
459 struct r600_context *rctx = (struct r600_context *)ctx;
460 unsigned tmp, spi_interp;
461 float psize_min, psize_max;
462 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
463
464 if (!rs) {
465 return NULL;
466 }
467
468 r600_init_command_buffer(&rs->buffer, 30);
469
470 rs->flatshade = state->flatshade;
471 rs->sprite_coord_enable = state->sprite_coord_enable;
472 rs->two_side = state->light_twoside;
473 rs->clip_plane_enable = state->clip_plane_enable;
474 rs->pa_sc_line_stipple = state->line_stipple_enable ?
475 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
476 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
477 rs->pa_cl_clip_cntl =
478 S_028810_PS_UCP_MODE(3) |
479 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
480 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
481 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
482 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
483 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
484 rs->multisample_enable = state->multisample;
485
486 /* offset */
487 rs->offset_units = state->offset_units;
488 rs->offset_scale = state->offset_scale * 16.0f;
489 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
490
491 if (state->point_size_per_vertex) {
492 psize_min = util_get_min_point_size(state);
493 psize_max = 8192;
494 } else {
495 /* Force the point size to be as if the vertex output was disabled. */
496 psize_min = state->point_size;
497 psize_max = state->point_size;
498 }
499
500 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
501 if (state->sprite_coord_enable) {
502 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
503 S_0286D4_PNT_SPRITE_OVRD_X(2) |
504 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
505 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
506 S_0286D4_PNT_SPRITE_OVRD_W(1);
507 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
508 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
509 }
510 }
511
512 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
513 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
514 tmp = r600_pack_float_12p4(state->point_size/2);
515 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
516 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
517 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
518 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
519 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
520 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
521 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
522
523 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
524 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
525 S_028A48_MSAA_ENABLE(state->multisample) |
526 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
527 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
528
529 if (rctx->b.chip_class == CAYMAN) {
530 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
531 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
532 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
533 } else {
534 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
535 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
536 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
537 }
538
539 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
540 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
541 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
542 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
543 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
544 S_028814_FACE(!state->front_ccw) |
545 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
546 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
547 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
548 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
549 state->fill_back != PIPE_POLYGON_MODE_FILL) |
550 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
551 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
552 return rs;
553 }
554
555 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
556 const struct pipe_sampler_state *state)
557 {
558 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
559 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
560
561 if (!ss) {
562 return NULL;
563 }
564
565 ss->border_color_use = sampler_state_needs_border_color(state);
566
567 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
568 ss->tex_sampler_words[0] =
569 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
570 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
571 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
572 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
573 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
574 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
575 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
576 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
577 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
578 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
579 ss->tex_sampler_words[1] =
580 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
581 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
582 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
583 ss->tex_sampler_words[2] =
584 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
585 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
586 S_03C008_TYPE(1);
587
588 if (ss->border_color_use) {
589 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
590 }
591 return ss;
592 }
593
594 static struct pipe_sampler_view *
595 texture_buffer_sampler_view(struct r600_context *rctx,
596 struct r600_pipe_sampler_view *view,
597 unsigned width0, unsigned height0)
598
599 {
600 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
601 uint64_t va;
602 int stride = util_format_get_blocksize(view->base.format);
603 unsigned format, num_format, format_comp, endian;
604 unsigned swizzle_res;
605 unsigned char swizzle[4];
606 const struct util_format_description *desc;
607 unsigned offset = view->base.u.buf.first_element * stride;
608 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
609
610 swizzle[0] = view->base.swizzle_r;
611 swizzle[1] = view->base.swizzle_g;
612 swizzle[2] = view->base.swizzle_b;
613 swizzle[3] = view->base.swizzle_a;
614
615 r600_vertex_data_type(view->base.format,
616 &format, &num_format, &format_comp,
617 &endian);
618
619 desc = util_format_description(view->base.format);
620
621 swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
622
623 va = tmp->resource.gpu_address + offset;
624 view->tex_resource = &tmp->resource;
625
626 view->skip_mip_address_reloc = true;
627 view->tex_resource_words[0] = va;
628 view->tex_resource_words[1] = size - 1;
629 view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
630 S_030008_STRIDE(stride) |
631 S_030008_DATA_FORMAT(format) |
632 S_030008_NUM_FORMAT_ALL(num_format) |
633 S_030008_FORMAT_COMP_ALL(format_comp) |
634 S_030008_ENDIAN_SWAP(endian);
635 view->tex_resource_words[3] = swizzle_res;
636 /*
637 * in theory dword 4 is for number of elements, for use with resinfo,
638 * but it seems to utterly fail to work, the amd gpu shader analyser
639 * uses a const buffer to store the element sizes for buffer txq
640 */
641 view->tex_resource_words[4] = 0;
642 view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
643 view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
644
645 if (tmp->resource.gpu_address)
646 LIST_ADDTAIL(&view->list, &rctx->b.texture_buffers);
647 return &view->base;
648 }
649
650 struct pipe_sampler_view *
651 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
652 struct pipe_resource *texture,
653 const struct pipe_sampler_view *state,
654 unsigned width0, unsigned height0,
655 unsigned force_level)
656 {
657 struct r600_context *rctx = (struct r600_context*)ctx;
658 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
659 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
660 struct r600_texture *tmp = (struct r600_texture*)texture;
661 unsigned format, endian;
662 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
663 unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
664 unsigned height, depth, width;
665 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
666 enum pipe_format pipe_format = state->format;
667 struct radeon_surf_level *surflevel;
668 unsigned base_level, first_level, last_level;
669 unsigned dim, last_layer;
670 uint64_t va;
671
672 if (!view)
673 return NULL;
674
675 /* initialize base object */
676 view->base = *state;
677 view->base.texture = NULL;
678 pipe_reference(NULL, &texture->reference);
679 view->base.texture = texture;
680 view->base.reference.count = 1;
681 view->base.context = ctx;
682
683 if (state->target == PIPE_BUFFER)
684 return texture_buffer_sampler_view(rctx, view, width0, height0);
685
686 swizzle[0] = state->swizzle_r;
687 swizzle[1] = state->swizzle_g;
688 swizzle[2] = state->swizzle_b;
689 swizzle[3] = state->swizzle_a;
690
691 tile_split = tmp->surface.tile_split;
692 surflevel = tmp->surface.level;
693
694 /* Texturing with separate depth and stencil. */
695 if (tmp->is_depth && !tmp->is_flushing_texture) {
696 switch (pipe_format) {
697 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
698 pipe_format = PIPE_FORMAT_Z32_FLOAT;
699 break;
700 case PIPE_FORMAT_X8Z24_UNORM:
701 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
702 /* Z24 is always stored like this. */
703 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
704 break;
705 case PIPE_FORMAT_X24S8_UINT:
706 case PIPE_FORMAT_S8X24_UINT:
707 case PIPE_FORMAT_X32_S8X24_UINT:
708 pipe_format = PIPE_FORMAT_S8_UINT;
709 tile_split = tmp->surface.stencil_tile_split;
710 surflevel = tmp->surface.stencil_level;
711 break;
712 default:;
713 }
714 }
715
716 format = r600_translate_texformat(ctx->screen, pipe_format,
717 swizzle,
718 &word4, &yuv_format);
719 assert(format != ~0);
720 if (format == ~0) {
721 FREE(view);
722 return NULL;
723 }
724
725 endian = r600_colorformat_endian_swap(format);
726
727 base_level = 0;
728 first_level = state->u.tex.first_level;
729 last_level = state->u.tex.last_level;
730 width = width0;
731 height = height0;
732 depth = texture->depth0;
733
734 if (force_level) {
735 base_level = force_level;
736 first_level = 0;
737 last_level = 0;
738 width = u_minify(width, force_level);
739 height = u_minify(height, force_level);
740 depth = u_minify(depth, force_level);
741 }
742
743 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
744 non_disp_tiling = tmp->non_disp_tiling;
745
746 switch (surflevel[base_level].mode) {
747 case RADEON_SURF_MODE_LINEAR_ALIGNED:
748 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
749 break;
750 case RADEON_SURF_MODE_2D:
751 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
752 break;
753 case RADEON_SURF_MODE_1D:
754 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
755 break;
756 case RADEON_SURF_MODE_LINEAR:
757 default:
758 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
759 break;
760 }
761 macro_aspect = tmp->surface.mtilea;
762 bankw = tmp->surface.bankw;
763 bankh = tmp->surface.bankh;
764 tile_split = eg_tile_split(tile_split);
765 macro_aspect = eg_macro_tile_aspect(macro_aspect);
766 bankw = eg_bank_wh(bankw);
767 bankh = eg_bank_wh(bankh);
768 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
769
770 /* 128 bit formats require tile type = 1 */
771 if (rscreen->b.chip_class == CAYMAN) {
772 if (util_format_get_blocksize(pipe_format) >= 16)
773 non_disp_tiling = 1;
774 }
775 nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
776
777 if (state->target == PIPE_TEXTURE_1D_ARRAY) {
778 height = 1;
779 depth = texture->array_size;
780 } else if (state->target == PIPE_TEXTURE_2D_ARRAY) {
781 depth = texture->array_size;
782 } else if (state->target == PIPE_TEXTURE_CUBE_ARRAY)
783 depth = texture->array_size / 6;
784
785 va = tmp->resource.gpu_address;
786
787 if (state->format == PIPE_FORMAT_X24S8_UINT ||
788 state->format == PIPE_FORMAT_S8X24_UINT ||
789 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
790 state->format == PIPE_FORMAT_S8_UINT)
791 view->is_stencil_sampler = true;
792
793 view->tex_resource = &tmp->resource;
794
795 /* array type views and views into array types need to use layer offset */
796 dim = state->target;
797 if (state->target != PIPE_TEXTURE_CUBE)
798 dim = MAX2(state->target, texture->target);
799
800 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(dim, texture->nr_samples)) |
801 S_030000_PITCH((pitch / 8) - 1) |
802 S_030000_TEX_WIDTH(width - 1));
803 if (rscreen->b.chip_class == CAYMAN)
804 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
805 else
806 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
807 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
808 S_030004_TEX_DEPTH(depth - 1) |
809 S_030004_ARRAY_MODE(array_mode));
810 view->tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
811
812 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
813 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
814 if (tmp->is_depth) {
815 /* disable FMASK (0 = disabled) */
816 view->tex_resource_words[3] = 0;
817 view->skip_mip_address_reloc = true;
818 } else {
819 /* FMASK should be in MIP_ADDRESS for multisample textures */
820 view->tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
821 }
822 } else if (last_level && texture->nr_samples <= 1) {
823 view->tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
824 } else {
825 view->tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
826 }
827
828 last_layer = state->u.tex.last_layer;
829 if (state->target != texture->target && depth == 1) {
830 last_layer = state->u.tex.first_layer;
831 }
832 view->tex_resource_words[4] = (word4 |
833 S_030010_ENDIAN_SWAP(endian));
834 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
835 S_030014_LAST_ARRAY(last_layer);
836 view->tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
837
838 if (texture->nr_samples > 1) {
839 unsigned log_samples = util_logbase2(texture->nr_samples);
840 if (rscreen->b.chip_class == CAYMAN) {
841 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
842 }
843 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
844 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
845 view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
846 } else {
847 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
848 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
849 /* aniso max 16 samples */
850 view->tex_resource_words[6] |= S_030018_MAX_ANISO(4);
851 }
852
853 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
854 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
855 S_03001C_BANK_WIDTH(bankw) |
856 S_03001C_BANK_HEIGHT(bankh) |
857 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
858 S_03001C_NUM_BANKS(nbanks) |
859 S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
860 return &view->base;
861 }
862
863 static struct pipe_sampler_view *
864 evergreen_create_sampler_view(struct pipe_context *ctx,
865 struct pipe_resource *tex,
866 const struct pipe_sampler_view *state)
867 {
868 return evergreen_create_sampler_view_custom(ctx, tex, state,
869 tex->width0, tex->height0, 0);
870 }
871
872 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
873 {
874 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
875 struct r600_config_state *a = (struct r600_config_state*)atom;
876
877 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
878 if (a->dyn_gpr_enabled) {
879 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
880 radeon_emit(cs, 0);
881 radeon_emit(cs, 0);
882 } else {
883 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
884 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
885 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
886 }
887 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
888 if (a->dyn_gpr_enabled) {
889 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
890 S_028838_PS_GPRS(0x1e) |
891 S_028838_VS_GPRS(0x1e) |
892 S_028838_GS_GPRS(0x1e) |
893 S_028838_ES_GPRS(0x1e) |
894 S_028838_HS_GPRS(0x1e) |
895 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
896 }
897 }
898
899 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
900 {
901 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
902 struct pipe_clip_state *state = &rctx->clip_state.state;
903
904 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
905 radeon_emit_array(cs, (unsigned*)state, 6*4);
906 }
907
908 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
909 const struct pipe_poly_stipple *state)
910 {
911 }
912
913 static void evergreen_get_scissor_rect(struct r600_context *rctx,
914 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
915 uint32_t *tl, uint32_t *br)
916 {
917 /* EG hw workaround */
918 if (br_x == 0)
919 tl_x = 1;
920 if (br_y == 0)
921 tl_y = 1;
922
923 /* cayman hw workaround */
924 if (rctx->b.chip_class == CAYMAN) {
925 if (br_x == 1 && br_y == 1)
926 br_x = 2;
927 }
928
929 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
930 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
931 }
932
933 static void evergreen_set_scissor_states(struct pipe_context *ctx,
934 unsigned start_slot,
935 unsigned num_scissors,
936 const struct pipe_scissor_state *state)
937 {
938 struct r600_context *rctx = (struct r600_context *)ctx;
939 struct r600_scissor_state *rstate = &rctx->scissor;
940 int i;
941
942 for (i = start_slot; i < start_slot + num_scissors; i++)
943 rstate->scissor[i] = state[i - start_slot];
944 rstate->dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
945 rstate->atom.num_dw = util_bitcount(rstate->dirty_mask) * 4;
946 r600_mark_atom_dirty(rctx, &rstate->atom);
947 }
948
949 static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
950 {
951 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
952 struct r600_scissor_state *rstate = &rctx->scissor;
953 struct pipe_scissor_state *state;
954 uint32_t dirty_mask;
955 unsigned i, offset;
956 uint32_t tl, br;
957
958 dirty_mask = rstate->dirty_mask;
959 while (dirty_mask != 0) {
960 i = u_bit_scan(&dirty_mask);
961 state = &rstate->scissor[i];
962 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
963
964 offset = i * 4 * 2;
965 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
966 radeon_emit(cs, tl);
967 radeon_emit(cs, br);
968 }
969 rstate->dirty_mask = 0;
970 rstate->atom.num_dw = 0;
971 }
972
973 /**
974 * This function intializes the CB* register values for RATs. It is meant
975 * to be used for 1D aligned buffers that do not have an associated
976 * radeon_surf.
977 */
978 void evergreen_init_color_surface_rat(struct r600_context *rctx,
979 struct r600_surface *surf)
980 {
981 struct pipe_resource *pipe_buffer = surf->base.texture;
982 unsigned format = r600_translate_colorformat(rctx->b.chip_class,
983 surf->base.format);
984 unsigned endian = r600_colorformat_endian_swap(format);
985 unsigned swap = r600_translate_colorswap(surf->base.format);
986 unsigned block_size =
987 align(util_format_get_blocksize(pipe_buffer->format), 4);
988 unsigned pitch_alignment =
989 MAX2(64, rctx->screen->b.tiling_info.group_bytes / block_size);
990 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
991
992 /* XXX: This is copied from evergreen_init_color_surface(). I don't
993 * know why this is necessary.
994 */
995 if (pipe_buffer->usage == PIPE_USAGE_STAGING) {
996 endian = ENDIAN_NONE;
997 }
998
999 surf->cb_color_base = r600_resource(pipe_buffer)->gpu_address >> 8;
1000
1001 surf->cb_color_pitch = (pitch / 8) - 1;
1002
1003 surf->cb_color_slice = 0;
1004
1005 surf->cb_color_view = 0;
1006
1007 surf->cb_color_info =
1008 S_028C70_ENDIAN(endian)
1009 | S_028C70_FORMAT(format)
1010 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
1011 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
1012 | S_028C70_COMP_SWAP(swap)
1013 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
1014 * are using NUMBER_UINT */
1015 | S_028C70_RAT(1)
1016 ;
1017
1018 surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1019
1020 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
1021 * elements. */
1022 surf->cb_color_dim = pipe_buffer->width0;
1023
1024 /* Set the buffer range the GPU will have access to: */
1025 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
1026 0, pipe_buffer->width0);
1027
1028 surf->cb_color_fmask = surf->cb_color_base;
1029 surf->cb_color_fmask_slice = 0;
1030 }
1031
1032 void evergreen_init_color_surface(struct r600_context *rctx,
1033 struct r600_surface *surf)
1034 {
1035 struct r600_screen *rscreen = rctx->screen;
1036 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1037 unsigned level = surf->base.u.tex.level;
1038 unsigned pitch, slice;
1039 unsigned color_info, color_attrib, color_dim = 0, color_view;
1040 unsigned format, swap, ntype, endian;
1041 uint64_t offset, base_offset;
1042 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1043 const struct util_format_description *desc;
1044 int i;
1045 bool blend_clamp = 0, blend_bypass = 0;
1046
1047 offset = rtex->surface.level[level].offset;
1048 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1049 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1050 offset += rtex->surface.level[level].slice_size *
1051 surf->base.u.tex.first_layer;
1052 color_view = 0;
1053 } else
1054 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1055 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1056
1057 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1058 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1059 if (slice) {
1060 slice = slice - 1;
1061 }
1062 color_info = 0;
1063 switch (rtex->surface.level[level].mode) {
1064 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1065 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1066 non_disp_tiling = 1;
1067 break;
1068 case RADEON_SURF_MODE_1D:
1069 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1070 non_disp_tiling = rtex->non_disp_tiling;
1071 break;
1072 case RADEON_SURF_MODE_2D:
1073 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1074 non_disp_tiling = rtex->non_disp_tiling;
1075 break;
1076 case RADEON_SURF_MODE_LINEAR:
1077 default:
1078 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1079 non_disp_tiling = 1;
1080 break;
1081 }
1082 tile_split = rtex->surface.tile_split;
1083 macro_aspect = rtex->surface.mtilea;
1084 bankw = rtex->surface.bankw;
1085 bankh = rtex->surface.bankh;
1086 if (rtex->fmask.size)
1087 fmask_bankh = rtex->fmask.bank_height;
1088 else
1089 fmask_bankh = rtex->surface.bankh;
1090 tile_split = eg_tile_split(tile_split);
1091 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1092 bankw = eg_bank_wh(bankw);
1093 bankh = eg_bank_wh(bankh);
1094 fmask_bankh = eg_bank_wh(fmask_bankh);
1095
1096 /* 128 bit formats require tile type = 1 */
1097 if (rscreen->b.chip_class == CAYMAN) {
1098 if (util_format_get_blocksize(surf->base.format) >= 16)
1099 non_disp_tiling = 1;
1100 }
1101 nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
1102 desc = util_format_description(surf->base.format);
1103 for (i = 0; i < 4; i++) {
1104 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1105 break;
1106 }
1107 }
1108
1109 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1110 S_028C74_NUM_BANKS(nbanks) |
1111 S_028C74_BANK_WIDTH(bankw) |
1112 S_028C74_BANK_HEIGHT(bankh) |
1113 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1114 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1115 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1116
1117 if (rctx->b.chip_class == CAYMAN) {
1118 color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1119 UTIL_FORMAT_SWIZZLE_1);
1120
1121 if (rtex->resource.b.b.nr_samples > 1) {
1122 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1123 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1124 S_028C74_NUM_FRAGMENTS(log_samples);
1125 }
1126 }
1127
1128 ntype = V_028C70_NUMBER_UNORM;
1129 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1130 ntype = V_028C70_NUMBER_SRGB;
1131 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1132 if (desc->channel[i].normalized)
1133 ntype = V_028C70_NUMBER_SNORM;
1134 else if (desc->channel[i].pure_integer)
1135 ntype = V_028C70_NUMBER_SINT;
1136 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1137 if (desc->channel[i].normalized)
1138 ntype = V_028C70_NUMBER_UNORM;
1139 else if (desc->channel[i].pure_integer)
1140 ntype = V_028C70_NUMBER_UINT;
1141 }
1142
1143 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
1144 assert(format != ~0);
1145
1146 swap = r600_translate_colorswap(surf->base.format);
1147 assert(swap != ~0);
1148
1149 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1150 endian = ENDIAN_NONE;
1151 } else {
1152 endian = r600_colorformat_endian_swap(format);
1153 }
1154
1155 /* blend clamp should be set for all NORM/SRGB types */
1156 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1157 ntype == V_028C70_NUMBER_SRGB)
1158 blend_clamp = 1;
1159
1160 /* set blend bypass according to docs if SINT/UINT or
1161 8/24 COLOR variants */
1162 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1163 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1164 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1165 blend_clamp = 0;
1166 blend_bypass = 1;
1167 }
1168
1169 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1170
1171 color_info |= S_028C70_FORMAT(format) |
1172 S_028C70_COMP_SWAP(swap) |
1173 S_028C70_BLEND_CLAMP(blend_clamp) |
1174 S_028C70_BLEND_BYPASS(blend_bypass) |
1175 S_028C70_NUMBER_TYPE(ntype) |
1176 S_028C70_ENDIAN(endian);
1177
1178 /* EXPORT_NORM is an optimzation that can be enabled for better
1179 * performance in certain cases.
1180 * EXPORT_NORM can be enabled if:
1181 * - 11-bit or smaller UNORM/SNORM/SRGB
1182 * - 16-bit or smaller FLOAT
1183 */
1184 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1185 ((desc->channel[i].size < 12 &&
1186 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1187 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1188 (desc->channel[i].size < 17 &&
1189 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1190 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1191 surf->export_16bpc = true;
1192 }
1193
1194 if (rtex->fmask.size) {
1195 color_info |= S_028C70_COMPRESSION(1);
1196 }
1197
1198 base_offset = rtex->resource.gpu_address;
1199
1200 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1201 surf->cb_color_base = (base_offset + offset) >> 8;
1202 surf->cb_color_dim = color_dim;
1203 surf->cb_color_info = color_info;
1204 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1205 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1206 surf->cb_color_view = color_view;
1207 surf->cb_color_attrib = color_attrib;
1208 if (rtex->fmask.size) {
1209 surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8;
1210 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1211 } else {
1212 surf->cb_color_fmask = surf->cb_color_base;
1213 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1214 }
1215
1216 surf->color_initialized = true;
1217 }
1218
1219 static void evergreen_init_depth_surface(struct r600_context *rctx,
1220 struct r600_surface *surf)
1221 {
1222 struct r600_screen *rscreen = rctx->screen;
1223 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1224 unsigned level = surf->base.u.tex.level;
1225 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1226 uint64_t offset;
1227 unsigned format, array_mode;
1228 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1229
1230
1231 format = r600_translate_dbformat(surf->base.format);
1232 assert(format != ~0);
1233
1234 offset = rtex->resource.gpu_address;
1235 offset += rtex->surface.level[level].offset;
1236
1237 switch (rtex->surface.level[level].mode) {
1238 case RADEON_SURF_MODE_2D:
1239 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1240 break;
1241 case RADEON_SURF_MODE_1D:
1242 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1243 case RADEON_SURF_MODE_LINEAR:
1244 default:
1245 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1246 break;
1247 }
1248 tile_split = rtex->surface.tile_split;
1249 macro_aspect = rtex->surface.mtilea;
1250 bankw = rtex->surface.bankw;
1251 bankh = rtex->surface.bankh;
1252 tile_split = eg_tile_split(tile_split);
1253 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1254 bankw = eg_bank_wh(bankw);
1255 bankh = eg_bank_wh(bankh);
1256 nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
1257 offset >>= 8;
1258
1259 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1260 S_028040_FORMAT(format) |
1261 S_028040_TILE_SPLIT(tile_split)|
1262 S_028040_NUM_BANKS(nbanks) |
1263 S_028040_BANK_WIDTH(bankw) |
1264 S_028040_BANK_HEIGHT(bankh) |
1265 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1266 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1267 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1268 }
1269
1270 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1271
1272 surf->db_depth_base = offset;
1273 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1274 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1275 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1276 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1277 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1278 levelinfo->nblk_y / 64 - 1);
1279
1280 switch (surf->base.format) {
1281 case PIPE_FORMAT_Z24X8_UNORM:
1282 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1283 case PIPE_FORMAT_X8Z24_UNORM:
1284 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1285 surf->pa_su_poly_offset_db_fmt_cntl =
1286 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1287 break;
1288 case PIPE_FORMAT_Z32_FLOAT:
1289 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1290 surf->pa_su_poly_offset_db_fmt_cntl =
1291 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1292 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1293 break;
1294 case PIPE_FORMAT_Z16_UNORM:
1295 surf->pa_su_poly_offset_db_fmt_cntl =
1296 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1297 break;
1298 default:;
1299 }
1300
1301 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1302 uint64_t stencil_offset;
1303 unsigned stile_split = rtex->surface.stencil_tile_split;
1304
1305 stile_split = eg_tile_split(stile_split);
1306
1307 stencil_offset = rtex->surface.stencil_level[level].offset;
1308 stencil_offset += rtex->resource.gpu_address;
1309
1310 surf->db_stencil_base = stencil_offset >> 8;
1311 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1312 S_028044_TILE_SPLIT(stile_split);
1313 } else {
1314 surf->db_stencil_base = offset;
1315 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1316 * Older kernels are out of luck. */
1317 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1318 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1319 S_028044_FORMAT(V_028044_STENCIL_8);
1320 }
1321
1322 /* use htile only for first level */
1323 if (rtex->htile_buffer && !level) {
1324 uint64_t va = rtex->htile_buffer->gpu_address;
1325 surf->db_htile_data_base = va >> 8;
1326 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1327 S_028ABC_HTILE_HEIGHT(1) |
1328 S_028ABC_FULL_CACHE(1);
1329 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1330 surf->db_preload_control = 0;
1331 }
1332
1333 surf->depth_initialized = true;
1334 }
1335
1336 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1337 const struct pipe_framebuffer_state *state)
1338 {
1339 struct r600_context *rctx = (struct r600_context *)ctx;
1340 struct r600_surface *surf;
1341 struct r600_texture *rtex;
1342 uint32_t i, log_samples;
1343
1344 if (rctx->framebuffer.state.nr_cbufs) {
1345 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1346 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1347 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1348 }
1349 if (rctx->framebuffer.state.zsbuf) {
1350 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1351 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1352
1353 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1354 if (rtex->htile_buffer) {
1355 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1356 }
1357 }
1358
1359 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1360
1361 /* Colorbuffers. */
1362 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1363 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1364 util_format_is_pure_integer(state->cbufs[0]->format);
1365 rctx->framebuffer.compressed_cb_mask = 0;
1366 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1367
1368 for (i = 0; i < state->nr_cbufs; i++) {
1369 surf = (struct r600_surface*)state->cbufs[i];
1370 if (!surf)
1371 continue;
1372
1373 rtex = (struct r600_texture*)surf->base.texture;
1374
1375 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1376
1377 if (!surf->color_initialized) {
1378 evergreen_init_color_surface(rctx, surf);
1379 }
1380
1381 if (!surf->export_16bpc) {
1382 rctx->framebuffer.export_16bpc = false;
1383 }
1384
1385 if (rtex->fmask.size && rtex->cmask.size) {
1386 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1387 }
1388 }
1389
1390 /* Update alpha-test state dependencies.
1391 * Alpha-test is done on the first colorbuffer only. */
1392 if (state->nr_cbufs) {
1393 bool alphatest_bypass = false;
1394 bool export_16bpc = true;
1395
1396 surf = (struct r600_surface*)state->cbufs[0];
1397 if (surf) {
1398 alphatest_bypass = surf->alphatest_bypass;
1399 export_16bpc = surf->export_16bpc;
1400 }
1401
1402 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1403 rctx->alphatest_state.bypass = alphatest_bypass;
1404 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1405 }
1406 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1407 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1408 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1409 }
1410 }
1411
1412 /* ZS buffer. */
1413 if (state->zsbuf) {
1414 surf = (struct r600_surface*)state->zsbuf;
1415
1416 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1417
1418 if (!surf->depth_initialized) {
1419 evergreen_init_depth_surface(rctx, surf);
1420 }
1421
1422 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1423 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1424 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1425 }
1426
1427 if (rctx->db_state.rsurf != surf) {
1428 rctx->db_state.rsurf = surf;
1429 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1430 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1431 }
1432 } else if (rctx->db_state.rsurf) {
1433 rctx->db_state.rsurf = NULL;
1434 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1435 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1436 }
1437
1438 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1439 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1440 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1441 }
1442
1443 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1444 rctx->alphatest_state.bypass = false;
1445 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1446 }
1447
1448 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1449 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1450 if ((rctx->b.chip_class == CAYMAN ||
1451 rctx->b.family == CHIP_RV770) &&
1452 rctx->db_misc_state.log_samples != log_samples) {
1453 rctx->db_misc_state.log_samples = log_samples;
1454 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1455 }
1456
1457
1458 /* Calculate the CS size. */
1459 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1460
1461 /* MSAA. */
1462 if (rctx->b.chip_class == EVERGREEN)
1463 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1464 else
1465 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1466
1467 /* Colorbuffers. */
1468 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1469 if (rctx->keep_tiling_flags)
1470 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1471 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1472
1473 /* ZS buffer. */
1474 if (state->zsbuf) {
1475 rctx->framebuffer.atom.num_dw += 24;
1476 if (rctx->keep_tiling_flags)
1477 rctx->framebuffer.atom.num_dw += 2;
1478 } else if (rctx->screen->b.info.drm_minor >= 18) {
1479 rctx->framebuffer.atom.num_dw += 4;
1480 }
1481
1482 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1483
1484 r600_set_sample_locations_constant_buffer(rctx);
1485 }
1486
1487 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1488 {
1489 struct r600_context *rctx = (struct r600_context *)ctx;
1490
1491 if (rctx->ps_iter_samples == min_samples)
1492 return;
1493
1494 rctx->ps_iter_samples = min_samples;
1495 if (rctx->framebuffer.nr_samples > 1) {
1496 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1497 }
1498 }
1499
1500 /* 8xMSAA */
1501 static uint32_t sample_locs_8x[] = {
1502 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1503 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1504 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1505 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1506 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1507 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1508 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1509 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1510 };
1511 static unsigned max_dist_8x = 7;
1512
1513 static void evergreen_get_sample_position(struct pipe_context *ctx,
1514 unsigned sample_count,
1515 unsigned sample_index,
1516 float *out_value)
1517 {
1518 int offset, index;
1519 struct {
1520 int idx:4;
1521 } val;
1522 switch (sample_count) {
1523 case 1:
1524 default:
1525 out_value[0] = out_value[1] = 0.5;
1526 break;
1527 case 2:
1528 offset = 4 * (sample_index * 2);
1529 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1530 out_value[0] = (float)(val.idx + 8) / 16.0f;
1531 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1532 out_value[1] = (float)(val.idx + 8) / 16.0f;
1533 break;
1534 case 4:
1535 offset = 4 * (sample_index * 2);
1536 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1537 out_value[0] = (float)(val.idx + 8) / 16.0f;
1538 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1539 out_value[1] = (float)(val.idx + 8) / 16.0f;
1540 break;
1541 case 8:
1542 offset = 4 * (sample_index % 4 * 2);
1543 index = (sample_index / 4);
1544 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1545 out_value[0] = (float)(val.idx + 8) / 16.0f;
1546 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1547 out_value[1] = (float)(val.idx + 8) / 16.0f;
1548 break;
1549 }
1550 }
1551
1552 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1553 {
1554
1555 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1556 unsigned max_dist = 0;
1557
1558 switch (nr_samples) {
1559 default:
1560 nr_samples = 0;
1561 break;
1562 case 2:
1563 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_2x));
1564 radeon_emit_array(cs, eg_sample_locs_2x, Elements(eg_sample_locs_2x));
1565 max_dist = eg_max_dist_2x;
1566 break;
1567 case 4:
1568 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_4x));
1569 radeon_emit_array(cs, eg_sample_locs_4x, Elements(eg_sample_locs_4x));
1570 max_dist = eg_max_dist_4x;
1571 break;
1572 case 8:
1573 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1574 radeon_emit_array(cs, sample_locs_8x, Elements(sample_locs_8x));
1575 max_dist = max_dist_8x;
1576 break;
1577 }
1578
1579 if (nr_samples > 1) {
1580 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1581 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1582 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1583 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1584 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1585 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1));
1586 } else {
1587 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1588 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1589 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1590 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, 0);
1591 }
1592 }
1593
1594 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1595 {
1596 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1597 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1598 unsigned nr_cbufs = state->nr_cbufs;
1599 unsigned i, tl, br;
1600 struct r600_texture *tex = NULL;
1601 struct r600_surface *cb = NULL;
1602
1603 /* XXX support more colorbuffers once we need them */
1604 assert(nr_cbufs <= 8);
1605 if (nr_cbufs > 8)
1606 nr_cbufs = 8;
1607
1608 /* Colorbuffers. */
1609 for (i = 0; i < nr_cbufs; i++) {
1610 unsigned reloc, cmask_reloc;
1611
1612 cb = (struct r600_surface*)state->cbufs[i];
1613 if (!cb) {
1614 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1615 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1616 continue;
1617 }
1618
1619 tex = (struct r600_texture *)cb->base.texture;
1620 reloc = radeon_add_to_buffer_list(&rctx->b,
1621 &rctx->b.gfx,
1622 (struct r600_resource*)cb->base.texture,
1623 RADEON_USAGE_READWRITE,
1624 tex->surface.nsamples > 1 ?
1625 RADEON_PRIO_COLOR_BUFFER_MSAA :
1626 RADEON_PRIO_COLOR_BUFFER);
1627
1628 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1629 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1630 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1631 RADEON_PRIO_CMASK);
1632 } else {
1633 cmask_reloc = reloc;
1634 }
1635
1636 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1637 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1638 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1639 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1640 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1641 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1642 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1643 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1644 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1645 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1646 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1647 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1648 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1649 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1650
1651 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1652 radeon_emit(cs, reloc);
1653
1654 if (!rctx->keep_tiling_flags) {
1655 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1656 radeon_emit(cs, reloc);
1657 }
1658
1659 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1660 radeon_emit(cs, reloc);
1661
1662 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1663 radeon_emit(cs, cmask_reloc);
1664
1665 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1666 radeon_emit(cs, reloc);
1667 }
1668 /* set CB_COLOR1_INFO for possible dual-src blending */
1669 if (i == 1 && state->cbufs[0]) {
1670 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1671 cb->cb_color_info | tex->cb_color_info);
1672
1673 if (!rctx->keep_tiling_flags) {
1674 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1675 &rctx->b.gfx,
1676 (struct r600_resource*)state->cbufs[0]->texture,
1677 RADEON_USAGE_READWRITE,
1678 RADEON_PRIO_COLOR_BUFFER);
1679
1680 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1681 radeon_emit(cs, reloc);
1682 }
1683 i++;
1684 }
1685 if (rctx->keep_tiling_flags) {
1686 for (; i < 8 ; i++) {
1687 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1688 }
1689 for (; i < 12; i++) {
1690 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1691 }
1692 }
1693
1694 /* ZS buffer. */
1695 if (state->zsbuf) {
1696 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1697 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1698 &rctx->b.gfx,
1699 (struct r600_resource*)state->zsbuf->texture,
1700 RADEON_USAGE_READWRITE,
1701 zb->base.texture->nr_samples > 1 ?
1702 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1703 RADEON_PRIO_DEPTH_BUFFER);
1704
1705 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1706 zb->pa_su_poly_offset_db_fmt_cntl);
1707 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1708
1709 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1710 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1711 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1712 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1713 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1714 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1715 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1716 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1717 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1718
1719 if (!rctx->keep_tiling_flags) {
1720 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
1721 radeon_emit(cs, reloc);
1722 }
1723
1724 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1725 radeon_emit(cs, reloc);
1726
1727 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1728 radeon_emit(cs, reloc);
1729
1730 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1731 radeon_emit(cs, reloc);
1732
1733 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1734 radeon_emit(cs, reloc);
1735 } else if (rctx->screen->b.info.drm_minor >= 18) {
1736 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1737 * Older kernels are out of luck. */
1738 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1739 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1740 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1741 }
1742
1743 /* Framebuffer dimensions. */
1744 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1745
1746 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1747 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1748 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1749
1750 if (rctx->b.chip_class == EVERGREEN) {
1751 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1752 } else {
1753 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1754 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples, rctx->ps_iter_samples, 0);
1755 }
1756 }
1757
1758 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1759 {
1760 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1761 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1762 float offset_units = state->offset_units;
1763 float offset_scale = state->offset_scale;
1764
1765 switch (state->zs_format) {
1766 case PIPE_FORMAT_Z24X8_UNORM:
1767 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1768 case PIPE_FORMAT_X8Z24_UNORM:
1769 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1770 offset_units *= 2.0f;
1771 break;
1772 case PIPE_FORMAT_Z16_UNORM:
1773 offset_units *= 4.0f;
1774 break;
1775 default:;
1776 }
1777
1778 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1779 radeon_emit(cs, fui(offset_scale));
1780 radeon_emit(cs, fui(offset_units));
1781 radeon_emit(cs, fui(offset_scale));
1782 radeon_emit(cs, fui(offset_units));
1783 }
1784
1785 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1786 {
1787 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1788 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1789 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1790 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1791
1792 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1793 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1794 /* This must match the used export instructions exactly.
1795 * Other values may lead to undefined behavior and hangs.
1796 */
1797 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
1798 }
1799
1800 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1801 {
1802 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1803 struct r600_db_state *a = (struct r600_db_state*)atom;
1804
1805 if (a->rsurf && a->rsurf->db_htile_surface) {
1806 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1807 unsigned reloc_idx;
1808
1809 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1810 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1811 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
1812 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1813 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1814 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1815 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1816 cs->buf[cs->cdw++] = reloc_idx;
1817 } else {
1818 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
1819 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
1820 }
1821 }
1822
1823 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1824 {
1825 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1826 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1827 unsigned db_render_control = 0;
1828 unsigned db_count_control = 0;
1829 unsigned db_render_override =
1830 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1831 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
1832 /* There is a hang with HTILE if stencil is used and
1833 * fast stencil is enabled. */
1834 S_02800C_FAST_STENCIL_DISABLE(1);
1835
1836 if (a->occlusion_query_enabled) {
1837 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1838 if (rctx->b.chip_class == CAYMAN) {
1839 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1840 }
1841 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1842 }
1843 /* FIXME we should be able to use hyperz even if we are not writing to
1844 * zbuffer but somehow this trigger GPU lockup. See :
1845 *
1846 * https://bugs.freedesktop.org/show_bug.cgi?id=60848
1847 *
1848 * Disable hyperz for now if not writing to zbuffer.
1849 */
1850 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface && rctx->zwritemask) {
1851 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1852 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
1853 /* This is to fix a lockup when hyperz and alpha test are enabled at
1854 * the same time somehow GPU get confuse on which order to pick for
1855 * z test
1856 */
1857 if (rctx->alphatest_state.sx_alpha_test_control) {
1858 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
1859 }
1860 } else {
1861 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
1862 }
1863 if (a->flush_depthstencil_through_cb) {
1864 assert(a->copy_depth || a->copy_stencil);
1865
1866 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1867 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1868 S_028000_COPY_CENTROID(1) |
1869 S_028000_COPY_SAMPLE(a->copy_sample);
1870 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1871 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1872 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1873 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1874 }
1875 if (a->htile_clear) {
1876 /* FIXME we might want to disable cliprect here */
1877 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
1878 }
1879
1880 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1881 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1882 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1883 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1884 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1885 }
1886
1887 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1888 struct r600_vertexbuf_state *state,
1889 unsigned resource_offset,
1890 unsigned pkt_flags)
1891 {
1892 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1893 uint32_t dirty_mask = state->dirty_mask;
1894
1895 while (dirty_mask) {
1896 struct pipe_vertex_buffer *vb;
1897 struct r600_resource *rbuffer;
1898 uint64_t va;
1899 unsigned buffer_index = u_bit_scan(&dirty_mask);
1900
1901 vb = &state->vb[buffer_index];
1902 rbuffer = (struct r600_resource*)vb->buffer;
1903 assert(rbuffer);
1904
1905 va = rbuffer->gpu_address + vb->buffer_offset;
1906
1907 /* fetch resources start at index 992 */
1908 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1909 radeon_emit(cs, (resource_offset + buffer_index) * 8);
1910 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1911 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1912 radeon_emit(cs, /* RESOURCEi_WORD2 */
1913 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1914 S_030008_STRIDE(vb->stride) |
1915 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1916 radeon_emit(cs, /* RESOURCEi_WORD3 */
1917 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1918 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1919 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1920 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1921 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1922 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1923 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1924 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1925
1926 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1927 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1928 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1929 }
1930 state->dirty_mask = 0;
1931 }
1932
1933 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1934 {
1935 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
1936 }
1937
1938 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1939 {
1940 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
1941 RADEON_CP_PACKET3_COMPUTE_MODE);
1942 }
1943
1944 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1945 struct r600_constbuf_state *state,
1946 unsigned buffer_id_base,
1947 unsigned reg_alu_constbuf_size,
1948 unsigned reg_alu_const_cache,
1949 unsigned pkt_flags)
1950 {
1951 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1952 uint32_t dirty_mask = state->dirty_mask;
1953
1954 while (dirty_mask) {
1955 struct pipe_constant_buffer *cb;
1956 struct r600_resource *rbuffer;
1957 uint64_t va;
1958 unsigned buffer_index = ffs(dirty_mask) - 1;
1959 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1960
1961 cb = &state->cb[buffer_index];
1962 rbuffer = (struct r600_resource*)cb->buffer;
1963 assert(rbuffer);
1964
1965 va = rbuffer->gpu_address + cb->buffer_offset;
1966
1967 if (!gs_ring_buffer) {
1968 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
1969 ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags);
1970 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
1971 pkt_flags);
1972 }
1973
1974 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1975 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1976 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1977
1978 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1979 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
1980 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1981 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1982 radeon_emit(cs, /* RESOURCEi_WORD2 */
1983 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1984 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
1985 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
1986 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
1987 radeon_emit(cs, /* RESOURCEi_WORD3 */
1988 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
1989 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1990 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1991 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1992 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1993 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1994 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1995 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1996 radeon_emit(cs, /* RESOURCEi_WORD7 */
1997 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
1998
1999 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2000 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2001 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2002
2003 dirty_mask &= ~(1 << buffer_index);
2004 }
2005 state->dirty_mask = 0;
2006 }
2007
2008 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
2009 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2010 {
2011 if (rctx->vs_shader->current->shader.vs_as_ls) {
2012 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2013 EG_FETCH_CONSTANTS_OFFSET_LS,
2014 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2015 R_028F40_ALU_CONST_CACHE_LS_0,
2016 0 /* PKT3 flags */);
2017 } else {
2018 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2019 EG_FETCH_CONSTANTS_OFFSET_VS,
2020 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2021 R_028980_ALU_CONST_CACHE_VS_0,
2022 0 /* PKT3 flags */);
2023 }
2024 }
2025
2026 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2027 {
2028 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
2029 EG_FETCH_CONSTANTS_OFFSET_GS,
2030 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2031 R_0289C0_ALU_CONST_CACHE_GS_0,
2032 0 /* PKT3 flags */);
2033 }
2034
2035 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2036 {
2037 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
2038 EG_FETCH_CONSTANTS_OFFSET_PS,
2039 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2040 R_028940_ALU_CONST_CACHE_PS_0,
2041 0 /* PKT3 flags */);
2042 }
2043
2044 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2045 {
2046 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
2047 EG_FETCH_CONSTANTS_OFFSET_CS,
2048 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2049 R_028F40_ALU_CONST_CACHE_LS_0,
2050 RADEON_CP_PACKET3_COMPUTE_MODE);
2051 }
2052
2053 /* tes constants can be emitted to VS or ES - which are common */
2054 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2055 {
2056 if (!rctx->tes_shader)
2057 return;
2058 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2059 EG_FETCH_CONSTANTS_OFFSET_VS,
2060 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2061 R_028980_ALU_CONST_CACHE_VS_0,
2062 0);
2063 }
2064
2065 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2066 {
2067 if (!rctx->tes_shader)
2068 return;
2069 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2070 EG_FETCH_CONSTANTS_OFFSET_HS,
2071 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
2072 R_028F00_ALU_CONST_CACHE_HS_0,
2073 0);
2074 }
2075
2076 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2077 struct r600_samplerview_state *state,
2078 unsigned resource_id_base, unsigned pkt_flags)
2079 {
2080 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2081 uint32_t dirty_mask = state->dirty_mask;
2082
2083 while (dirty_mask) {
2084 struct r600_pipe_sampler_view *rview;
2085 unsigned resource_index = u_bit_scan(&dirty_mask);
2086 unsigned reloc;
2087
2088 rview = state->views[resource_index];
2089 assert(rview);
2090
2091 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2092 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2093 radeon_emit_array(cs, rview->tex_resource_words, 8);
2094
2095 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2096 RADEON_USAGE_READ,
2097 r600_get_sampler_view_priority(rview->tex_resource));
2098 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2099 radeon_emit(cs, reloc);
2100
2101 if (!rview->skip_mip_address_reloc) {
2102 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2103 radeon_emit(cs, reloc);
2104 }
2105 }
2106 state->dirty_mask = 0;
2107 }
2108
2109 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2110 {
2111 if (rctx->vs_shader->current->shader.vs_as_ls) {
2112 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2113 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2114 } else {
2115 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2116 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2117 }
2118 }
2119
2120 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2121 {
2122 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2123 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2124 }
2125
2126 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2127 {
2128 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2129 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2130 }
2131
2132 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2133 {
2134 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2135 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2136 }
2137
2138 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2139 {
2140 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2141 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2142 }
2143
2144 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2145 {
2146 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2147 EG_FETCH_CONSTANTS_OFFSET_CS + 2, RADEON_CP_PACKET3_COMPUTE_MODE);
2148 }
2149
2150 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2151 struct r600_textures_info *texinfo,
2152 unsigned resource_id_base,
2153 unsigned border_index_reg,
2154 unsigned pkt_flags)
2155 {
2156 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2157 uint32_t dirty_mask = texinfo->states.dirty_mask;
2158
2159 while (dirty_mask) {
2160 struct r600_pipe_sampler_state *rstate;
2161 unsigned i = u_bit_scan(&dirty_mask);
2162
2163 rstate = texinfo->states.states[i];
2164 assert(rstate);
2165
2166 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2167 radeon_emit(cs, (resource_id_base + i) * 3);
2168 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2169
2170 if (rstate->border_color_use) {
2171 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2172 radeon_emit(cs, i);
2173 radeon_emit_array(cs, rstate->border_color.ui, 4);
2174 }
2175 }
2176 texinfo->states.dirty_mask = 0;
2177 }
2178
2179 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2180 {
2181 if (rctx->vs_shader->current->shader.vs_as_ls) {
2182 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2183 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2184 } else {
2185 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2186 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2187 }
2188 }
2189
2190 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2191 {
2192 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2193 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2194 }
2195
2196 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2197 {
2198 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2199 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2200 }
2201
2202 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2203 {
2204 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2205 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2206 }
2207
2208 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2209 {
2210 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2211 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2212 }
2213
2214 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2215 {
2216 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2217 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2218 RADEON_CP_PACKET3_COMPUTE_MODE);
2219 }
2220
2221 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2222 {
2223 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2224 uint8_t mask = s->sample_mask;
2225
2226 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2227 mask | (mask << 8) | (mask << 16) | (mask << 24));
2228 }
2229
2230 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2231 {
2232 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2233 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2234 uint16_t mask = s->sample_mask;
2235
2236 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2237 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2238 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2239 }
2240
2241 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2242 {
2243 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2244 struct r600_cso_state *state = (struct r600_cso_state*)a;
2245 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2246
2247 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2248 (shader->buffer->gpu_address + shader->offset) >> 8);
2249 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2250 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2251 RADEON_USAGE_READ,
2252 RADEON_PRIO_INTERNAL_SHADER));
2253 }
2254
2255 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2256 {
2257 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2258 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2259
2260 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2261
2262 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2263 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2264 primid = 1;
2265 }
2266
2267 if (state->geom_enable) {
2268 uint32_t cut_val;
2269
2270 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2271 cut_val = V_028A40_GS_CUT_128;
2272 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2273 cut_val = V_028A40_GS_CUT_256;
2274 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2275 cut_val = V_028A40_GS_CUT_512;
2276 else
2277 cut_val = V_028A40_GS_CUT_1024;
2278
2279 v = S_028B54_GS_EN(1) |
2280 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2281 if (!rctx->tes_shader)
2282 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2283
2284 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2285 S_028A40_CUT_MODE(cut_val);
2286
2287 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2288 primid = 1;
2289 }
2290
2291 if (rctx->tes_shader) {
2292 uint32_t type, partitioning, topology;
2293 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2294 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2295 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2296 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2297 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2298 switch (tes_prim_mode) {
2299 case PIPE_PRIM_LINES:
2300 type = V_028B6C_TESS_ISOLINE;
2301 break;
2302 case PIPE_PRIM_TRIANGLES:
2303 type = V_028B6C_TESS_TRIANGLE;
2304 break;
2305 case PIPE_PRIM_QUADS:
2306 type = V_028B6C_TESS_QUAD;
2307 break;
2308 default:
2309 assert(0);
2310 return;
2311 }
2312
2313 switch (tes_spacing) {
2314 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2315 partitioning = V_028B6C_PART_FRAC_ODD;
2316 break;
2317 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2318 partitioning = V_028B6C_PART_FRAC_EVEN;
2319 break;
2320 case PIPE_TESS_SPACING_EQUAL:
2321 partitioning = V_028B6C_PART_INTEGER;
2322 break;
2323 default:
2324 assert(0);
2325 return;
2326 }
2327
2328 if (tes_point_mode)
2329 topology = V_028B6C_OUTPUT_POINT;
2330 else if (tes_prim_mode == PIPE_PRIM_LINES)
2331 topology = V_028B6C_OUTPUT_LINE;
2332 else if (tes_vertex_order_cw)
2333 /* XXX follow radeonsi and invert */
2334 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2335 else
2336 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2337
2338 tf_param = S_028B6C_TYPE(type) |
2339 S_028B6C_PARTITIONING(partitioning) |
2340 S_028B6C_TOPOLOGY(topology);
2341 }
2342
2343 if (rctx->tes_shader) {
2344 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2345 S_028B54_HS_EN(1);
2346 if (!state->geom_enable)
2347 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2348 else
2349 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2350 }
2351
2352 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2353 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2354 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2355 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2356 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2357 }
2358
2359 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2360 {
2361 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2362 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2363 struct r600_resource *rbuffer;
2364
2365 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2366 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2367 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2368
2369 if (state->enable) {
2370 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2371 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2372 rbuffer->gpu_address >> 8);
2373 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2374 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2375 RADEON_USAGE_READWRITE,
2376 RADEON_PRIO_RINGS_STREAMOUT));
2377 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2378 state->esgs_ring.buffer_size >> 8);
2379
2380 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2381 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2382 rbuffer->gpu_address >> 8);
2383 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2384 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2385 RADEON_USAGE_READWRITE,
2386 RADEON_PRIO_RINGS_STREAMOUT));
2387 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2388 state->gsvs_ring.buffer_size >> 8);
2389 } else {
2390 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2391 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2392 }
2393
2394 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2395 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2396 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2397 }
2398
2399 void cayman_init_common_regs(struct r600_command_buffer *cb,
2400 enum chip_class ctx_chip_class,
2401 enum radeon_family ctx_family,
2402 int ctx_drm_minor)
2403 {
2404 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2405 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2406 /* always set the temp clauses */
2407 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2408
2409 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2410 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2411 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2412
2413 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2414
2415 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2416 r600_store_value(cb, 0);
2417 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2418
2419 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2420 }
2421
2422 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2423 {
2424 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2425 int tmp, i;
2426
2427 r600_init_command_buffer(cb, 342);
2428
2429 /* This must be first. */
2430 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2431 r600_store_value(cb, 0x80000000);
2432 r600_store_value(cb, 0x80000000);
2433
2434 /* We're setting config registers here. */
2435 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2436 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2437
2438 cayman_init_common_regs(cb, rctx->b.chip_class,
2439 rctx->b.family, rctx->screen->b.info.drm_minor);
2440
2441 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2442 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2443
2444 /* remove LS/HS from one SIMD for hw workaround */
2445 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2446 r600_store_value(cb, 0xffffffff);
2447 r600_store_value(cb, 0xffffffff);
2448 r600_store_value(cb, 0xfffffffe);
2449
2450 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2451 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2452 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2453 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2454 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2455 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2456 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2457
2458 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2459 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2460 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2461 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2462 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2463
2464 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2465 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2466 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2467 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2468 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2469 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2470 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2471 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2472 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2473 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2474 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2475 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2476 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2477 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2478
2479 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2480
2481 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2482 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2483 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2484
2485 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2486
2487 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2488 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2489 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2490
2491 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2492 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2493 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2494
2495 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2496
2497 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2498 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2499 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2500
2501 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2502
2503 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2504
2505 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2506
2507 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2508 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2509 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2510 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2511
2512 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2513 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2514
2515 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2516 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2517 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2518 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2519 }
2520
2521 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2522 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2523
2524 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2525 r600_store_value(cb, fui(1.0)); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2526 r600_store_value(cb, fui(1.0)); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2527 r600_store_value(cb, fui(1.0)); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2528 r600_store_value(cb, fui(1.0)); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2529
2530 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2531 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2532 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2533
2534 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2535 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2536 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2537
2538 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2539 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2540 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2541 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2542 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2543 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2544
2545 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2546
2547 /* to avoid GPU doing any preloading of constant from random address */
2548 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2549 for (i = 0; i < 16; i++)
2550 r600_store_value(cb, 0);
2551
2552 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2553 for (i = 0; i < 16; i++)
2554 r600_store_value(cb, 0);
2555
2556 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2557 for (i = 0; i < 16; i++)
2558 r600_store_value(cb, 0);
2559
2560 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2561 for (i = 0; i < 16; i++)
2562 r600_store_value(cb, 0);
2563
2564 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2565 for (i = 0; i < 16; i++)
2566 r600_store_value(cb, 0);
2567
2568 if (rctx->screen->b.has_streamout) {
2569 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2570 }
2571
2572 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2573 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2574 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2575 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2576 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2577 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2578
2579 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2580 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2581 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2582 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2583 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2584 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2585 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2586 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2587 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2588 }
2589
2590 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2591 enum chip_class ctx_chip_class,
2592 enum radeon_family ctx_family,
2593 int ctx_drm_minor)
2594 {
2595 int ps_prio;
2596 int vs_prio;
2597 int gs_prio;
2598 int es_prio;
2599
2600 int hs_prio;
2601 int cs_prio;
2602 int ls_prio;
2603
2604 unsigned tmp;
2605
2606 ps_prio = 0;
2607 vs_prio = 1;
2608 gs_prio = 2;
2609 es_prio = 3;
2610 hs_prio = 3;
2611 ls_prio = 3;
2612 cs_prio = 0;
2613
2614 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2615 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2616 rctx->r6xx_num_clause_temp_gprs = 4;
2617 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2618 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2619 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2620 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2621
2622 tmp = 0;
2623 switch (ctx_family) {
2624 case CHIP_CEDAR:
2625 case CHIP_PALM:
2626 case CHIP_SUMO:
2627 case CHIP_SUMO2:
2628 case CHIP_CAICOS:
2629 break;
2630 default:
2631 tmp |= S_008C00_VC_ENABLE(1);
2632 break;
2633 }
2634 tmp |= S_008C00_EXPORT_SRC_C(1);
2635 tmp |= S_008C00_CS_PRIO(cs_prio);
2636 tmp |= S_008C00_LS_PRIO(ls_prio);
2637 tmp |= S_008C00_HS_PRIO(hs_prio);
2638 tmp |= S_008C00_PS_PRIO(ps_prio);
2639 tmp |= S_008C00_VS_PRIO(vs_prio);
2640 tmp |= S_008C00_GS_PRIO(gs_prio);
2641 tmp |= S_008C00_ES_PRIO(es_prio);
2642
2643 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2644 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2645
2646 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2647 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2648 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2649
2650 /* The cs checker requires this register to be set. */
2651 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2652
2653 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2654 r600_store_value(cb, 0);
2655 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2656
2657 return;
2658 }
2659
2660 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2661 {
2662 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2663 int num_ps_threads;
2664 int num_vs_threads;
2665 int num_gs_threads;
2666 int num_es_threads;
2667 int num_hs_threads;
2668 int num_ls_threads;
2669
2670 int num_ps_stack_entries;
2671 int num_vs_stack_entries;
2672 int num_gs_stack_entries;
2673 int num_es_stack_entries;
2674 int num_hs_stack_entries;
2675 int num_ls_stack_entries;
2676 enum radeon_family family;
2677 unsigned tmp, i;
2678
2679 if (rctx->b.chip_class == CAYMAN) {
2680 cayman_init_atom_start_cs(rctx);
2681 return;
2682 }
2683
2684 r600_init_command_buffer(cb, 342);
2685
2686 /* This must be first. */
2687 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2688 r600_store_value(cb, 0x80000000);
2689 r600_store_value(cb, 0x80000000);
2690
2691 /* We're setting config registers here. */
2692 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2693 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2694
2695 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2696 rctx->b.family, rctx->screen->b.info.drm_minor);
2697
2698 family = rctx->b.family;
2699 switch (family) {
2700 case CHIP_CEDAR:
2701 default:
2702 num_ps_threads = 96;
2703 num_vs_threads = 16;
2704 num_gs_threads = 16;
2705 num_es_threads = 16;
2706 num_hs_threads = 16;
2707 num_ls_threads = 16;
2708 num_ps_stack_entries = 42;
2709 num_vs_stack_entries = 42;
2710 num_gs_stack_entries = 42;
2711 num_es_stack_entries = 42;
2712 num_hs_stack_entries = 42;
2713 num_ls_stack_entries = 42;
2714 break;
2715 case CHIP_REDWOOD:
2716 num_ps_threads = 128;
2717 num_vs_threads = 20;
2718 num_gs_threads = 20;
2719 num_es_threads = 20;
2720 num_hs_threads = 20;
2721 num_ls_threads = 20;
2722 num_ps_stack_entries = 42;
2723 num_vs_stack_entries = 42;
2724 num_gs_stack_entries = 42;
2725 num_es_stack_entries = 42;
2726 num_hs_stack_entries = 42;
2727 num_ls_stack_entries = 42;
2728 break;
2729 case CHIP_JUNIPER:
2730 num_ps_threads = 128;
2731 num_vs_threads = 20;
2732 num_gs_threads = 20;
2733 num_es_threads = 20;
2734 num_hs_threads = 20;
2735 num_ls_threads = 20;
2736 num_ps_stack_entries = 85;
2737 num_vs_stack_entries = 85;
2738 num_gs_stack_entries = 85;
2739 num_es_stack_entries = 85;
2740 num_hs_stack_entries = 85;
2741 num_ls_stack_entries = 85;
2742 break;
2743 case CHIP_CYPRESS:
2744 case CHIP_HEMLOCK:
2745 num_ps_threads = 128;
2746 num_vs_threads = 20;
2747 num_gs_threads = 20;
2748 num_es_threads = 20;
2749 num_hs_threads = 20;
2750 num_ls_threads = 20;
2751 num_ps_stack_entries = 85;
2752 num_vs_stack_entries = 85;
2753 num_gs_stack_entries = 85;
2754 num_es_stack_entries = 85;
2755 num_hs_stack_entries = 85;
2756 num_ls_stack_entries = 85;
2757 break;
2758 case CHIP_PALM:
2759 num_ps_threads = 96;
2760 num_vs_threads = 16;
2761 num_gs_threads = 16;
2762 num_es_threads = 16;
2763 num_hs_threads = 16;
2764 num_ls_threads = 16;
2765 num_ps_stack_entries = 42;
2766 num_vs_stack_entries = 42;
2767 num_gs_stack_entries = 42;
2768 num_es_stack_entries = 42;
2769 num_hs_stack_entries = 42;
2770 num_ls_stack_entries = 42;
2771 break;
2772 case CHIP_SUMO:
2773 num_ps_threads = 96;
2774 num_vs_threads = 25;
2775 num_gs_threads = 25;
2776 num_es_threads = 25;
2777 num_hs_threads = 16;
2778 num_ls_threads = 16;
2779 num_ps_stack_entries = 42;
2780 num_vs_stack_entries = 42;
2781 num_gs_stack_entries = 42;
2782 num_es_stack_entries = 42;
2783 num_hs_stack_entries = 42;
2784 num_ls_stack_entries = 42;
2785 break;
2786 case CHIP_SUMO2:
2787 num_ps_threads = 96;
2788 num_vs_threads = 25;
2789 num_gs_threads = 25;
2790 num_es_threads = 25;
2791 num_hs_threads = 16;
2792 num_ls_threads = 16;
2793 num_ps_stack_entries = 85;
2794 num_vs_stack_entries = 85;
2795 num_gs_stack_entries = 85;
2796 num_es_stack_entries = 85;
2797 num_hs_stack_entries = 85;
2798 num_ls_stack_entries = 85;
2799 break;
2800 case CHIP_BARTS:
2801 num_ps_threads = 128;
2802 num_vs_threads = 20;
2803 num_gs_threads = 20;
2804 num_es_threads = 20;
2805 num_hs_threads = 20;
2806 num_ls_threads = 20;
2807 num_ps_stack_entries = 85;
2808 num_vs_stack_entries = 85;
2809 num_gs_stack_entries = 85;
2810 num_es_stack_entries = 85;
2811 num_hs_stack_entries = 85;
2812 num_ls_stack_entries = 85;
2813 break;
2814 case CHIP_TURKS:
2815 num_ps_threads = 128;
2816 num_vs_threads = 20;
2817 num_gs_threads = 20;
2818 num_es_threads = 20;
2819 num_hs_threads = 20;
2820 num_ls_threads = 20;
2821 num_ps_stack_entries = 42;
2822 num_vs_stack_entries = 42;
2823 num_gs_stack_entries = 42;
2824 num_es_stack_entries = 42;
2825 num_hs_stack_entries = 42;
2826 num_ls_stack_entries = 42;
2827 break;
2828 case CHIP_CAICOS:
2829 num_ps_threads = 96;
2830 num_vs_threads = 10;
2831 num_gs_threads = 10;
2832 num_es_threads = 10;
2833 num_hs_threads = 10;
2834 num_ls_threads = 10;
2835 num_ps_stack_entries = 42;
2836 num_vs_stack_entries = 42;
2837 num_gs_stack_entries = 42;
2838 num_es_stack_entries = 42;
2839 num_hs_stack_entries = 42;
2840 num_ls_stack_entries = 42;
2841 break;
2842 }
2843
2844 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2845 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2846 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2847 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2848
2849 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2850 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2851
2852 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2853 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2854 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2855
2856 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2857 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2858 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2859
2860 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2861 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2862 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2863
2864 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2865 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2866 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2867
2868 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2869 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2870
2871 /* remove LS/HS from one SIMD for hw workaround */
2872 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2873 r600_store_value(cb, 0xffffffff);
2874 r600_store_value(cb, 0xffffffff);
2875 r600_store_value(cb, 0xfffffffe);
2876
2877 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2878 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2879
2880 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2881 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2882 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2883 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2884 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2885 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2886 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2887
2888 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2889 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2890 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2891 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2892 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2893
2894 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2895 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2896 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2897 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2898 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2899 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2900 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2901 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2902 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2903 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2904 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2905 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2906 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2907 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2908
2909 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2910 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2911 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2912
2913 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2914
2915 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2916
2917 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2918 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2919 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2920
2921 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2922
2923 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2924
2925 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2926 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2927 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2928
2929 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2930 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2931 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2932 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2933 }
2934
2935 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2936 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2937
2938 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2939 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2940 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2941 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2942
2943 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2944 r600_store_value(cb, fui(1.0)); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2945 r600_store_value(cb, fui(1.0)); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2946 r600_store_value(cb, fui(1.0)); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2947 r600_store_value(cb, fui(1.0)); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2948
2949 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2950 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2951 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2952
2953 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2954 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2955 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2956
2957 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2958 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2959 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2960 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2961 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2962 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2963 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2964
2965 /* to avoid GPU doing any preloading of constant from random address */
2966 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2967 for (i = 0; i < 16; i++)
2968 r600_store_value(cb, 0);
2969
2970 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2971 for (i = 0; i < 16; i++)
2972 r600_store_value(cb, 0);
2973
2974 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2975 for (i = 0; i < 16; i++)
2976 r600_store_value(cb, 0);
2977
2978 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2979 for (i = 0; i < 16; i++)
2980 r600_store_value(cb, 0);
2981
2982 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2983 for (i = 0; i < 16; i++)
2984 r600_store_value(cb, 0);
2985
2986 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2987
2988 if (rctx->screen->b.has_streamout) {
2989 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2990 }
2991
2992 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2993 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2994 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2995 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2996 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2997 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2998
2999 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
3000 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
3001 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
3002
3003 if (rctx->b.family == CHIP_CAICOS) {
3004 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
3005 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3006 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3007 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
3008 } else {
3009 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
3010 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3011 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3012 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
3013 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
3014 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
3015 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
3016 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
3017 }
3018
3019 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3020 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3021 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
3022 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
3023 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
3024 }
3025
3026 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3027 {
3028 struct r600_context *rctx = (struct r600_context *)ctx;
3029 struct r600_command_buffer *cb = &shader->command_buffer;
3030 struct r600_shader *rshader = &shader->shader;
3031 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
3032 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
3033 int ninterp = 0;
3034 boolean have_perspective = FALSE, have_linear = FALSE;
3035 static const unsigned spi_baryc_enable_bit[6] = {
3036 S_0286E0_PERSP_SAMPLE_ENA(1),
3037 S_0286E0_PERSP_CENTER_ENA(1),
3038 S_0286E0_PERSP_CENTROID_ENA(1),
3039 S_0286E0_LINEAR_SAMPLE_ENA(1),
3040 S_0286E0_LINEAR_CENTER_ENA(1),
3041 S_0286E0_LINEAR_CENTROID_ENA(1)
3042 };
3043 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
3044 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
3045 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3046 uint32_t spi_ps_input_cntl[32];
3047
3048 if (!cb->buf) {
3049 r600_init_command_buffer(cb, 64);
3050 } else {
3051 cb->num_dw = 0;
3052 }
3053
3054 for (i = 0; i < rshader->ninput; i++) {
3055 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3056 POSITION goes via GPRs from the SC so isn't counted */
3057 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3058 pos_index = i;
3059 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
3060 if (face_index == -1)
3061 face_index = i;
3062 }
3063 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3064 if (face_index == -1)
3065 face_index = i; /* lives in same register, same enable bit */
3066 }
3067 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
3068 fixed_pt_position_index = i;
3069 }
3070 else {
3071 ninterp++;
3072 int k = eg_get_interpolator_index(
3073 rshader->input[i].interpolate,
3074 rshader->input[i].interpolate_location);
3075 if (k >= 0) {
3076 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3077 have_perspective |= k < 3;
3078 have_linear |= !(k < 3);
3079 }
3080 }
3081
3082 sid = rshader->input[i].spi_sid;
3083
3084 if (sid) {
3085 tmp = S_028644_SEMANTIC(sid);
3086
3087 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3088 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3089 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3090 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3091 tmp |= S_028644_FLAT_SHADE(1);
3092 }
3093
3094 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3095 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3096 tmp |= S_028644_PT_SPRITE_TEX(1);
3097 }
3098
3099 spi_ps_input_cntl[num++] = tmp;
3100 }
3101 }
3102
3103 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3104 r600_store_array(cb, num, spi_ps_input_cntl);
3105
3106 for (i = 0; i < rshader->noutput; i++) {
3107 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3108 z_export = 1;
3109 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3110 stencil_export = 1;
3111 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3112 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3113 mask_export = 1;
3114 }
3115 if (rshader->uses_kill)
3116 db_shader_control |= S_02880C_KILL_ENABLE(1);
3117
3118 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3119 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3120 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3121
3122 switch (rshader->ps_conservative_z) {
3123 default: /* fall through */
3124 case TGSI_FS_DEPTH_LAYOUT_ANY:
3125 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3126 break;
3127 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3128 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3129 break;
3130 case TGSI_FS_DEPTH_LAYOUT_LESS:
3131 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3132 break;
3133 }
3134
3135 exports_ps = 0;
3136 for (i = 0; i < rshader->noutput; i++) {
3137 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3138 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3139 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3140 exports_ps |= 1;
3141 }
3142
3143 num_cout = rshader->nr_ps_color_exports;
3144
3145 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3146 if (!exports_ps) {
3147 /* always at least export 1 component per pixel */
3148 exports_ps = 2;
3149 }
3150 shader->nr_ps_color_outputs = num_cout;
3151 if (ninterp == 0) {
3152 ninterp = 1;
3153 have_perspective = TRUE;
3154 }
3155 if (!spi_baryc_cntl)
3156 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3157
3158 if (!have_perspective && !have_linear)
3159 have_perspective = TRUE;
3160
3161 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3162 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3163 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3164 spi_input_z = 0;
3165 if (pos_index != -1) {
3166 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3167 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3168 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3169 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3170 }
3171
3172 spi_ps_in_control_1 = 0;
3173 if (face_index != -1) {
3174 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3175 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3176 }
3177 if (fixed_pt_position_index != -1) {
3178 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3179 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3180 }
3181
3182 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3183 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3184 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3185
3186 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3187 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3188 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3189
3190 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3191 r600_store_value(cb, shader->bo->gpu_address >> 8);
3192 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3193 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3194 S_028844_PRIME_CACHE_ON_DRAW(1) |
3195 S_028844_STACK_SIZE(rshader->bc.nstack));
3196 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3197
3198 shader->db_shader_control = db_shader_control;
3199 shader->ps_depth_export = z_export | stencil_export | mask_export;
3200
3201 shader->sprite_coord_enable = sprite_coord_enable;
3202 if (rctx->rasterizer)
3203 shader->flatshade = rctx->rasterizer->flatshade;
3204 }
3205
3206 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3207 {
3208 struct r600_command_buffer *cb = &shader->command_buffer;
3209 struct r600_shader *rshader = &shader->shader;
3210
3211 r600_init_command_buffer(cb, 32);
3212
3213 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3214 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3215 S_028890_STACK_SIZE(rshader->bc.nstack));
3216 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3217 shader->bo->gpu_address >> 8);
3218 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3219 }
3220
3221 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3222 {
3223 struct r600_context *rctx = (struct r600_context *)ctx;
3224 struct r600_command_buffer *cb = &shader->command_buffer;
3225 struct r600_shader *rshader = &shader->shader;
3226 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3227 unsigned gsvs_itemsizes[4] = {
3228 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3229 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3230 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3231 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3232 };
3233
3234 r600_init_command_buffer(cb, 64);
3235
3236 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3237
3238
3239 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3240 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3241 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3242 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3243
3244 if (rctx->screen->b.info.drm_minor >= 35) {
3245 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3246 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3247 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3248 }
3249 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3250 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3251 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3252 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3253 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3254
3255 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3256 (rshader->ring_item_sizes[0]) >> 2);
3257
3258 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3259 gsvs_itemsizes[0] +
3260 gsvs_itemsizes[1] +
3261 gsvs_itemsizes[2] +
3262 gsvs_itemsizes[3]);
3263
3264 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3265 r600_store_value(cb, gsvs_itemsizes[0]);
3266 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3267 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3268
3269 /* FIXME calculate these values somehow ??? */
3270 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3271 r600_store_value(cb, 0x80); /* GS_PER_ES */
3272 r600_store_value(cb, 0x100); /* ES_PER_GS */
3273 r600_store_value(cb, 0x2); /* GS_PER_VS */
3274
3275 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3276 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3277 S_028878_STACK_SIZE(rshader->bc.nstack));
3278 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3279 shader->bo->gpu_address >> 8);
3280 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3281 }
3282
3283
3284 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3285 {
3286 struct r600_command_buffer *cb = &shader->command_buffer;
3287 struct r600_shader *rshader = &shader->shader;
3288 unsigned spi_vs_out_id[10] = {};
3289 unsigned i, tmp, nparams = 0;
3290
3291 for (i = 0; i < rshader->noutput; i++) {
3292 if (rshader->output[i].spi_sid) {
3293 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3294 spi_vs_out_id[nparams / 4] |= tmp;
3295 nparams++;
3296 }
3297 }
3298
3299 r600_init_command_buffer(cb, 32);
3300
3301 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3302 for (i = 0; i < 10; i++) {
3303 r600_store_value(cb, spi_vs_out_id[i]);
3304 }
3305
3306 /* Certain attributes (position, psize, etc.) don't count as params.
3307 * VS is required to export at least one param and r600_shader_from_tgsi()
3308 * takes care of adding a dummy export.
3309 */
3310 if (nparams < 1)
3311 nparams = 1;
3312
3313 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3314 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3315 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3316 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3317 S_028860_STACK_SIZE(rshader->bc.nstack));
3318 if (rshader->vs_position_window_space) {
3319 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3320 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3321 } else {
3322 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3323 S_028818_VTX_W0_FMT(1) |
3324 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3325 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3326 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3327
3328 }
3329 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3330 shader->bo->gpu_address >> 8);
3331 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3332
3333 shader->pa_cl_vs_out_cntl =
3334 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3335 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3336 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3337 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3338 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3339 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3340 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3341 }
3342
3343 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3344 {
3345 struct r600_command_buffer *cb = &shader->command_buffer;
3346 struct r600_shader *rshader = &shader->shader;
3347
3348 r600_init_command_buffer(cb, 32);
3349 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3350 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3351 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3352 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3353 shader->bo->gpu_address >> 8);
3354 }
3355
3356 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3357 {
3358 struct r600_command_buffer *cb = &shader->command_buffer;
3359 struct r600_shader *rshader = &shader->shader;
3360
3361 r600_init_command_buffer(cb, 32);
3362 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3363 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3364 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3365 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3366 shader->bo->gpu_address >> 8);
3367 }
3368 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3369 {
3370 struct pipe_blend_state blend;
3371
3372 memset(&blend, 0, sizeof(blend));
3373 blend.independent_blend_enable = true;
3374 blend.rt[0].colormask = 0xf;
3375 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3376 }
3377
3378 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3379 {
3380 struct pipe_blend_state blend;
3381 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3382 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3383
3384 memset(&blend, 0, sizeof(blend));
3385 blend.independent_blend_enable = true;
3386 blend.rt[0].colormask = 0xf;
3387 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3388 }
3389
3390 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3391 {
3392 struct pipe_blend_state blend;
3393 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3394
3395 memset(&blend, 0, sizeof(blend));
3396 blend.independent_blend_enable = true;
3397 blend.rt[0].colormask = 0xf;
3398 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3399 }
3400
3401 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3402 {
3403 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3404
3405 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3406 }
3407
3408 void evergreen_update_db_shader_control(struct r600_context * rctx)
3409 {
3410 bool dual_export;
3411 unsigned db_shader_control;
3412
3413 if (!rctx->ps_shader) {
3414 return;
3415 }
3416
3417 dual_export = rctx->framebuffer.export_16bpc &&
3418 !rctx->ps_shader->current->ps_depth_export;
3419
3420 db_shader_control = rctx->ps_shader->current->db_shader_control |
3421 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3422 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3423 V_02880C_EXPORT_DB_FULL) |
3424 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3425
3426 /* When alpha test is enabled we can't trust the hw to make the proper
3427 * decision on the order in which ztest should be run related to fragment
3428 * shader execution.
3429 *
3430 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3431 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3432 * execution and thus after alpha test so if discarded by the alpha test
3433 * the z value is not written.
3434 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3435 * get a hang unless you flush the DB in between. For now just use
3436 * LATE_Z.
3437 */
3438 if (rctx->alphatest_state.sx_alpha_test_control) {
3439 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3440 } else {
3441 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3442 }
3443
3444 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3445 rctx->db_misc_state.db_shader_control = db_shader_control;
3446 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3447 }
3448 }
3449
3450 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3451 struct pipe_resource *dst,
3452 unsigned dst_level,
3453 unsigned dst_x,
3454 unsigned dst_y,
3455 unsigned dst_z,
3456 struct pipe_resource *src,
3457 unsigned src_level,
3458 unsigned src_x,
3459 unsigned src_y,
3460 unsigned src_z,
3461 unsigned copy_height,
3462 unsigned pitch,
3463 unsigned bpp)
3464 {
3465 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3466 struct r600_texture *rsrc = (struct r600_texture*)src;
3467 struct r600_texture *rdst = (struct r600_texture*)dst;
3468 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3469 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3470 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3471 uint64_t base, addr;
3472
3473 dst_mode = rdst->surface.level[dst_level].mode;
3474 src_mode = rsrc->surface.level[src_level].mode;
3475 /* downcast linear aligned to linear to simplify test */
3476 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3477 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3478 assert(dst_mode != src_mode);
3479
3480 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3481 if (util_format_has_depth(util_format_description(src->format)))
3482 non_disp_tiling = 1;
3483
3484 y = 0;
3485 sub_cmd = EG_DMA_COPY_TILED;
3486 lbpp = util_logbase2(bpp);
3487 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3488 nbanks = eg_num_banks(rctx->screen->b.tiling_info.num_banks);
3489
3490 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
3491 /* T2L */
3492 array_mode = evergreen_array_mode(src_mode);
3493 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
3494 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3495 /* linear height must be the same as the slice tile max height, it's ok even
3496 * if the linear destination/source have smaller heigh as the size of the
3497 * dma packet will be using the copy_height which is always smaller or equal
3498 * to the linear height
3499 */
3500 height = rsrc->surface.level[src_level].npix_y;
3501 detile = 1;
3502 x = src_x;
3503 y = src_y;
3504 z = src_z;
3505 base = rsrc->surface.level[src_level].offset;
3506 addr = rdst->surface.level[dst_level].offset;
3507 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3508 addr += dst_y * pitch + dst_x * bpp;
3509 bank_h = eg_bank_wh(rsrc->surface.bankh);
3510 bank_w = eg_bank_wh(rsrc->surface.bankw);
3511 mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
3512 tile_split = eg_tile_split(rsrc->surface.tile_split);
3513 base += rsrc->resource.gpu_address;
3514 addr += rdst->resource.gpu_address;
3515 } else {
3516 /* L2T */
3517 array_mode = evergreen_array_mode(dst_mode);
3518 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
3519 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3520 /* linear height must be the same as the slice tile max height, it's ok even
3521 * if the linear destination/source have smaller heigh as the size of the
3522 * dma packet will be using the copy_height which is always smaller or equal
3523 * to the linear height
3524 */
3525 height = rdst->surface.level[dst_level].npix_y;
3526 detile = 0;
3527 x = dst_x;
3528 y = dst_y;
3529 z = dst_z;
3530 base = rdst->surface.level[dst_level].offset;
3531 addr = rsrc->surface.level[src_level].offset;
3532 addr += rsrc->surface.level[src_level].slice_size * src_z;
3533 addr += src_y * pitch + src_x * bpp;
3534 bank_h = eg_bank_wh(rdst->surface.bankh);
3535 bank_w = eg_bank_wh(rdst->surface.bankw);
3536 mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
3537 tile_split = eg_tile_split(rdst->surface.tile_split);
3538 base += rdst->resource.gpu_address;
3539 addr += rsrc->resource.gpu_address;
3540 }
3541
3542 size = (copy_height * pitch) / 4;
3543 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3544 r600_need_dma_space(&rctx->b, ncopy * 9);
3545
3546 for (i = 0; i < ncopy; i++) {
3547 cheight = copy_height;
3548 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3549 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3550 }
3551 size = (cheight * pitch) / 4;
3552 /* emit reloc before writing cs so that cs is always in consistent state */
3553 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3554 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3555 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3556 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3557 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
3558 cs->buf[cs->cdw++] = base >> 8;
3559 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3560 (lbpp << 24) | (bank_h << 21) |
3561 (bank_w << 18) | (mt_aspect << 16);
3562 cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
3563 cs->buf[cs->cdw++] = (slice_tile_max << 0);
3564 cs->buf[cs->cdw++] = (x << 0) | (z << 18);
3565 cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28);
3566 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3567 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3568 copy_height -= cheight;
3569 addr += cheight * pitch;
3570 y += cheight;
3571 }
3572 }
3573
3574 static void evergreen_dma_copy(struct pipe_context *ctx,
3575 struct pipe_resource *dst,
3576 unsigned dst_level,
3577 unsigned dstx, unsigned dsty, unsigned dstz,
3578 struct pipe_resource *src,
3579 unsigned src_level,
3580 const struct pipe_box *src_box)
3581 {
3582 struct r600_context *rctx = (struct r600_context *)ctx;
3583 struct r600_texture *rsrc = (struct r600_texture*)src;
3584 struct r600_texture *rdst = (struct r600_texture*)dst;
3585 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3586 unsigned src_w, dst_w;
3587 unsigned src_x, src_y;
3588 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3589
3590 if (rctx->b.dma.cs == NULL) {
3591 goto fallback;
3592 }
3593
3594 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3595 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3596 return;
3597 }
3598
3599 if (src->format != dst->format || src_box->depth > 1 ||
3600 (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level)) {
3601 goto fallback;
3602 }
3603
3604 if (rsrc->dirty_level_mask & (1 << src_level)) {
3605 ctx->flush_resource(ctx, src);
3606 }
3607
3608 src_x = util_format_get_nblocksx(src->format, src_box->x);
3609 dst_x = util_format_get_nblocksx(src->format, dst_x);
3610 src_y = util_format_get_nblocksy(src->format, src_box->y);
3611 dst_y = util_format_get_nblocksy(src->format, dst_y);
3612
3613 bpp = rdst->surface.bpe;
3614 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3615 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3616 src_w = rsrc->surface.level[src_level].npix_x;
3617 dst_w = rdst->surface.level[dst_level].npix_x;
3618 copy_height = src_box->height / rsrc->surface.blk_h;
3619
3620 dst_mode = rdst->surface.level[dst_level].mode;
3621 src_mode = rsrc->surface.level[src_level].mode;
3622 /* downcast linear aligned to linear to simplify test */
3623 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3624 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3625
3626 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3627 /* FIXME evergreen can do partial blit */
3628 goto fallback;
3629 }
3630 /* the x test here are currently useless (because we don't support partial blit)
3631 * but keep them around so we don't forget about those
3632 */
3633 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3634 goto fallback;
3635 }
3636
3637 /* 128 bpp surfaces require non_disp_tiling for both
3638 * tiled and linear buffers on cayman. However, async
3639 * DMA only supports it on the tiled side. As such
3640 * the tile order is backwards after a L2T/T2L packet.
3641 */
3642 if ((rctx->b.chip_class == CAYMAN) &&
3643 (src_mode != dst_mode) &&
3644 (util_format_get_blocksize(src->format) >= 16)) {
3645 goto fallback;
3646 }
3647
3648 if (src_mode == dst_mode) {
3649 uint64_t dst_offset, src_offset;
3650 /* simple dma blit would do NOTE code here assume :
3651 * src_box.x/y == 0
3652 * dst_x/y == 0
3653 * dst_pitch == src_pitch
3654 */
3655 src_offset= rsrc->surface.level[src_level].offset;
3656 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3657 src_offset += src_y * src_pitch + src_x * bpp;
3658 dst_offset = rdst->surface.level[dst_level].offset;
3659 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3660 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3661 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3662 src_box->height * src_pitch);
3663 } else {
3664 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3665 src, src_level, src_x, src_y, src_box->z,
3666 copy_height, dst_pitch, bpp);
3667 }
3668 return;
3669
3670 fallback:
3671 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3672 src, src_level, src_box);
3673 }
3674
3675 static void evergreen_set_tess_state(struct pipe_context *ctx,
3676 const float default_outer_level[4],
3677 const float default_inner_level[2])
3678 {
3679 struct r600_context *rctx = (struct r600_context *)ctx;
3680
3681 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3682 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3683 rctx->tess_state_dirty = true;
3684 }
3685
3686 void evergreen_init_state_functions(struct r600_context *rctx)
3687 {
3688 unsigned id = 1;
3689 unsigned i;
3690 /* !!!
3691 * To avoid GPU lockup registers must be emited in a specific order
3692 * (no kidding ...). The order below is important and have been
3693 * partialy infered from analyzing fglrx command stream.
3694 *
3695 * Don't reorder atom without carefully checking the effect (GPU lockup
3696 * or piglit regression).
3697 * !!!
3698 */
3699 if (rctx->b.chip_class == EVERGREEN) {
3700 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
3701 if (rctx->screen->b.info.drm_minor >= 7)
3702 rctx->config_state.dyn_gpr_enabled = true;
3703 }
3704 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
3705 /* shader const */
3706 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
3707 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
3708 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
3709 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
3710 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
3711 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
3712 /* shader program */
3713 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
3714 /* sampler */
3715 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
3716 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
3717 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
3718 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
3719 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
3720 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
3721 /* resources */
3722 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
3723 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
3724 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
3725 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
3726 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
3727 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
3728 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
3729 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
3730
3731 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3732
3733 if (rctx->b.chip_class == EVERGREEN) {
3734 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
3735 } else {
3736 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
3737 }
3738 rctx->sample_mask.sample_mask = ~0;
3739
3740 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3741 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3742 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3743 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
3744 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3745 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
3746 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
3747 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
3748 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3749 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
3750 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3751 r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 0);
3752 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 0);
3753 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3754 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
3755 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3756 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3757 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3758 for (i = 0; i < EG_NUM_HW_STAGES; i++)
3759 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3760 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
3761 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
3762
3763 rctx->b.b.create_blend_state = evergreen_create_blend_state;
3764 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
3765 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
3766 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
3767 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
3768 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
3769 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
3770 rctx->b.b.set_min_samples = evergreen_set_min_samples;
3771 rctx->b.b.set_scissor_states = evergreen_set_scissor_states;
3772 rctx->b.b.set_tess_state = evergreen_set_tess_state;
3773 if (rctx->b.chip_class == EVERGREEN)
3774 rctx->b.b.get_sample_position = evergreen_get_sample_position;
3775 else
3776 rctx->b.b.get_sample_position = cayman_get_sample_position;
3777 rctx->b.dma_copy = evergreen_dma_copy;
3778
3779 evergreen_init_compute_state_functions(rctx);
3780 }
3781
3782 /**
3783 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
3784 *
3785 * The information about LDS and other non-compile-time parameters is then
3786 * written to the const buffer.
3787
3788 * const buffer contains -
3789 * uint32_t input_patch_size
3790 * uint32_t input_vertex_size
3791 * uint32_t num_tcs_input_cp
3792 * uint32_t num_tcs_output_cp;
3793 * uint32_t output_patch_size
3794 * uint32_t output_vertex_size
3795 * uint32_t output_patch0_offset
3796 * uint32_t perpatch_output_offset
3797 * and the same constbuf is bound to LS/HS/VS(ES).
3798 */
3799 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
3800 {
3801 struct pipe_constant_buffer constbuf = {0};
3802 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
3803 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
3804 unsigned num_tcs_input_cp = info->vertices_per_patch;
3805 unsigned num_tcs_outputs;
3806 unsigned num_tcs_output_cp;
3807 unsigned num_tcs_patch_outputs;
3808 unsigned num_tcs_inputs;
3809 unsigned input_vertex_size, output_vertex_size;
3810 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
3811 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
3812 uint32_t values[16];
3813 unsigned num_waves;
3814 unsigned num_pipes = rctx->screen->b.info.r600_max_pipes;
3815 unsigned wave_divisor = (16 * num_pipes);
3816
3817 *num_patches = 1;
3818
3819 if (!rctx->tes_shader) {
3820 rctx->lds_alloc = 0;
3821 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3822 R600_LDS_INFO_CONST_BUFFER, NULL);
3823 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3824 R600_LDS_INFO_CONST_BUFFER, NULL);
3825 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3826 R600_LDS_INFO_CONST_BUFFER, NULL);
3827 return;
3828 }
3829
3830 if (rctx->lds_alloc != 0 &&
3831 rctx->last_ls == ls &&
3832 !rctx->tess_state_dirty &&
3833 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
3834 rctx->last_tcs == tcs)
3835 return;
3836
3837 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
3838
3839 if (rctx->tcs_shader) {
3840 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
3841 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
3842 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
3843 } else {
3844 num_tcs_outputs = num_tcs_inputs;
3845 num_tcs_output_cp = num_tcs_input_cp;
3846 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
3847 }
3848
3849 /* size in bytes */
3850 input_vertex_size = num_tcs_inputs * 16;
3851 output_vertex_size = num_tcs_outputs * 16;
3852
3853 input_patch_size = num_tcs_input_cp * input_vertex_size;
3854
3855 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
3856 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3857
3858 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
3859 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
3860
3861 lds_size = output_patch0_offset + output_patch_size * *num_patches;
3862
3863 values[0] = input_patch_size;
3864 values[1] = input_vertex_size;
3865 values[2] = num_tcs_input_cp;
3866 values[3] = num_tcs_output_cp;
3867
3868 values[4] = output_patch_size;
3869 values[5] = output_vertex_size;
3870 values[6] = output_patch0_offset;
3871 values[7] = perpatch_output_offset;
3872
3873 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
3874 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
3875 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
3876
3877 rctx->lds_alloc = (lds_size | (num_waves << 14));
3878
3879 memcpy(&values[8], rctx->tess_state, 6 * sizeof(float));
3880 values[14] = 0;
3881 values[15] = 0;
3882
3883 rctx->tess_state_dirty = false;
3884 rctx->last_ls = ls;
3885 rctx->last_tcs = tcs;
3886 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
3887
3888 constbuf.user_buffer = values;
3889 constbuf.buffer_size = 16 * 4;
3890
3891 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3892 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3893 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3894 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3895 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3896 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3897 pipe_resource_reference(&constbuf.buffer, NULL);
3898 }
3899
3900 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
3901 const struct pipe_draw_info *info,
3902 unsigned num_patches)
3903 {
3904 unsigned num_output_cp;
3905
3906 if (!rctx->tes_shader)
3907 return 0;
3908
3909 num_output_cp = rctx->tcs_shader ?
3910 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
3911 info->vertices_per_patch;
3912
3913 return S_028B58_NUM_PATCHES(num_patches) |
3914 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
3915 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
3916 }
3917
3918 void evergreen_set_ls_hs_config(struct r600_context *rctx,
3919 struct radeon_winsys_cs *cs,
3920 uint32_t ls_hs_config)
3921 {
3922 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
3923 }
3924
3925 void evergreen_set_lds_alloc(struct r600_context *rctx,
3926 struct radeon_winsys_cs *cs,
3927 uint32_t lds_alloc)
3928 {
3929 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
3930 }
3931
3932 /* on evergreen if you are running tessellation you need to disable dynamic
3933 GPRs to workaround a hardware bug.*/
3934 bool evergreen_adjust_gprs(struct r600_context *rctx)
3935 {
3936 unsigned num_gprs[EG_NUM_HW_STAGES];
3937 unsigned def_gprs[EG_NUM_HW_STAGES];
3938 unsigned cur_gprs[EG_NUM_HW_STAGES];
3939 unsigned new_gprs[EG_NUM_HW_STAGES];
3940 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
3941 unsigned max_gprs;
3942 unsigned i;
3943 unsigned total_gprs;
3944 unsigned tmp[3];
3945 bool rework = false, set_default = false, set_dirty = false;
3946 max_gprs = 0;
3947 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3948 def_gprs[i] = rctx->default_gprs[i];
3949 max_gprs += def_gprs[i];
3950 }
3951 max_gprs += def_num_clause_temp_gprs * 2;
3952
3953 /* if we have no TESS and dyn gpr is enabled then do nothing. */
3954 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader || rctx->screen->b.info.drm_minor < 7) {
3955 if (rctx->config_state.dyn_gpr_enabled)
3956 return true;
3957
3958 /* transition back to dyn gpr enabled state */
3959 rctx->config_state.dyn_gpr_enabled = true;
3960 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3961 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3962 return true;
3963 }
3964
3965
3966 /* gather required shader gprs */
3967 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3968 if (rctx->hw_shader_stages[i].shader)
3969 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
3970 else
3971 num_gprs[i] = 0;
3972 }
3973
3974 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3975 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3976 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3977 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3978 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3979 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3980
3981 total_gprs = 0;
3982 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3983 new_gprs[i] = num_gprs[i];
3984 total_gprs += num_gprs[i];
3985 }
3986
3987 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
3988 return false;
3989
3990 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3991 if (new_gprs[i] > cur_gprs[i]) {
3992 rework = true;
3993 break;
3994 }
3995 }
3996
3997 if (rctx->config_state.dyn_gpr_enabled) {
3998 set_dirty = true;
3999 rctx->config_state.dyn_gpr_enabled = false;
4000 }
4001
4002 if (rework) {
4003 set_default = true;
4004 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4005 if (new_gprs[i] > def_gprs[i])
4006 set_default = false;
4007 }
4008
4009 if (set_default) {
4010 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4011 new_gprs[i] = def_gprs[i];
4012 }
4013 } else {
4014 unsigned ps_value = max_gprs;
4015
4016 ps_value -= (def_num_clause_temp_gprs * 2);
4017 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
4018 ps_value -= new_gprs[i];
4019
4020 new_gprs[R600_HW_STAGE_PS] = ps_value;
4021 }
4022
4023 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
4024 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
4025 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
4026
4027 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
4028 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
4029
4030 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
4031 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
4032
4033 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
4034 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
4035 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
4036 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
4037 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
4038 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
4039 set_dirty = true;
4040 }
4041 }
4042
4043
4044 if (set_dirty) {
4045 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4046 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4047 }
4048 return true;
4049 }