2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
35 static INLINE
unsigned evergreen_array_mode(unsigned mode
)
38 case RADEON_SURF_MODE_LINEAR_ALIGNED
: return V_028C70_ARRAY_LINEAR_ALIGNED
;
40 case RADEON_SURF_MODE_1D
: return V_028C70_ARRAY_1D_TILED_THIN1
;
42 case RADEON_SURF_MODE_2D
: return V_028C70_ARRAY_2D_TILED_THIN1
;
44 case RADEON_SURF_MODE_LINEAR
: return V_028C70_ARRAY_LINEAR_GENERAL
;
48 static uint32_t eg_num_banks(uint32_t nbanks
)
64 static unsigned eg_tile_split(unsigned tile_split
)
67 case 64: tile_split
= 0; break;
68 case 128: tile_split
= 1; break;
69 case 256: tile_split
= 2; break;
70 case 512: tile_split
= 3; break;
72 case 1024: tile_split
= 4; break;
73 case 2048: tile_split
= 5; break;
74 case 4096: tile_split
= 6; break;
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect
)
81 switch (macro_tile_aspect
) {
83 case 1: macro_tile_aspect
= 0; break;
84 case 2: macro_tile_aspect
= 1; break;
85 case 4: macro_tile_aspect
= 2; break;
86 case 8: macro_tile_aspect
= 3; break;
88 return macro_tile_aspect
;
91 static unsigned eg_bank_wh(unsigned bankwh
)
95 case 1: bankwh
= 0; break;
96 case 2: bankwh
= 1; break;
97 case 4: bankwh
= 2; break;
98 case 8: bankwh
= 3; break;
103 static uint32_t r600_translate_blend_function(int blend_func
)
105 switch (blend_func
) {
107 return V_028780_COMB_DST_PLUS_SRC
;
108 case PIPE_BLEND_SUBTRACT
:
109 return V_028780_COMB_SRC_MINUS_DST
;
110 case PIPE_BLEND_REVERSE_SUBTRACT
:
111 return V_028780_COMB_DST_MINUS_SRC
;
113 return V_028780_COMB_MIN_DST_SRC
;
115 return V_028780_COMB_MAX_DST_SRC
;
117 R600_ERR("Unknown blend function %d\n", blend_func
);
124 static uint32_t r600_translate_blend_factor(int blend_fact
)
126 switch (blend_fact
) {
127 case PIPE_BLENDFACTOR_ONE
:
128 return V_028780_BLEND_ONE
;
129 case PIPE_BLENDFACTOR_SRC_COLOR
:
130 return V_028780_BLEND_SRC_COLOR
;
131 case PIPE_BLENDFACTOR_SRC_ALPHA
:
132 return V_028780_BLEND_SRC_ALPHA
;
133 case PIPE_BLENDFACTOR_DST_ALPHA
:
134 return V_028780_BLEND_DST_ALPHA
;
135 case PIPE_BLENDFACTOR_DST_COLOR
:
136 return V_028780_BLEND_DST_COLOR
;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
139 case PIPE_BLENDFACTOR_CONST_COLOR
:
140 return V_028780_BLEND_CONST_COLOR
;
141 case PIPE_BLENDFACTOR_CONST_ALPHA
:
142 return V_028780_BLEND_CONST_ALPHA
;
143 case PIPE_BLENDFACTOR_ZERO
:
144 return V_028780_BLEND_ZERO
;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR
;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA
;
157 case PIPE_BLENDFACTOR_SRC1_COLOR
:
158 return V_028780_BLEND_SRC1_COLOR
;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
160 return V_028780_BLEND_SRC1_ALPHA
;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
162 return V_028780_BLEND_INV_SRC1_COLOR
;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
164 return V_028780_BLEND_INV_SRC1_ALPHA
;
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
173 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
177 case PIPE_TEXTURE_1D
:
178 return V_030000_SQ_TEX_DIM_1D
;
179 case PIPE_TEXTURE_1D_ARRAY
:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
181 case PIPE_TEXTURE_2D
:
182 case PIPE_TEXTURE_RECT
:
183 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_MSAA
:
184 V_030000_SQ_TEX_DIM_2D
;
185 case PIPE_TEXTURE_2D_ARRAY
:
186 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
187 V_030000_SQ_TEX_DIM_2D_ARRAY
;
188 case PIPE_TEXTURE_3D
:
189 return V_030000_SQ_TEX_DIM_3D
;
190 case PIPE_TEXTURE_CUBE
:
191 case PIPE_TEXTURE_CUBE_ARRAY
:
192 return V_030000_SQ_TEX_DIM_CUBEMAP
;
196 static uint32_t r600_translate_dbformat(enum pipe_format format
)
199 case PIPE_FORMAT_Z16_UNORM
:
200 return V_028040_Z_16
;
201 case PIPE_FORMAT_Z24X8_UNORM
:
202 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
203 case PIPE_FORMAT_X8Z24_UNORM
:
204 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
205 return V_028040_Z_24
;
206 case PIPE_FORMAT_Z32_FLOAT
:
207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
208 return V_028040_Z_32_FLOAT
;
214 static uint32_t r600_translate_colorswap(enum pipe_format format
)
218 case PIPE_FORMAT_L4A4_UNORM
:
219 case PIPE_FORMAT_A4R4_UNORM
:
220 return V_028C70_SWAP_ALT
;
222 case PIPE_FORMAT_A8_UNORM
:
223 case PIPE_FORMAT_A8_SNORM
:
224 case PIPE_FORMAT_A8_UINT
:
225 case PIPE_FORMAT_A8_SINT
:
226 case PIPE_FORMAT_A16_UNORM
:
227 case PIPE_FORMAT_A16_SNORM
:
228 case PIPE_FORMAT_A16_UINT
:
229 case PIPE_FORMAT_A16_SINT
:
230 case PIPE_FORMAT_A16_FLOAT
:
231 case PIPE_FORMAT_A32_UINT
:
232 case PIPE_FORMAT_A32_SINT
:
233 case PIPE_FORMAT_A32_FLOAT
:
234 case PIPE_FORMAT_R4A4_UNORM
:
235 return V_028C70_SWAP_ALT_REV
;
236 case PIPE_FORMAT_I8_UNORM
:
237 case PIPE_FORMAT_I8_SNORM
:
238 case PIPE_FORMAT_I8_UINT
:
239 case PIPE_FORMAT_I8_SINT
:
240 case PIPE_FORMAT_I16_UNORM
:
241 case PIPE_FORMAT_I16_SNORM
:
242 case PIPE_FORMAT_I16_UINT
:
243 case PIPE_FORMAT_I16_SINT
:
244 case PIPE_FORMAT_I16_FLOAT
:
245 case PIPE_FORMAT_I32_UINT
:
246 case PIPE_FORMAT_I32_SINT
:
247 case PIPE_FORMAT_I32_FLOAT
:
248 case PIPE_FORMAT_L8_UNORM
:
249 case PIPE_FORMAT_L8_SNORM
:
250 case PIPE_FORMAT_L8_UINT
:
251 case PIPE_FORMAT_L8_SINT
:
252 case PIPE_FORMAT_L8_SRGB
:
253 case PIPE_FORMAT_L16_UNORM
:
254 case PIPE_FORMAT_L16_SNORM
:
255 case PIPE_FORMAT_L16_UINT
:
256 case PIPE_FORMAT_L16_SINT
:
257 case PIPE_FORMAT_L16_FLOAT
:
258 case PIPE_FORMAT_L32_UINT
:
259 case PIPE_FORMAT_L32_SINT
:
260 case PIPE_FORMAT_L32_FLOAT
:
261 case PIPE_FORMAT_R8_UNORM
:
262 case PIPE_FORMAT_R8_SNORM
:
263 case PIPE_FORMAT_R8_UINT
:
264 case PIPE_FORMAT_R8_SINT
:
265 return V_028C70_SWAP_STD
;
267 /* 16-bit buffers. */
268 case PIPE_FORMAT_B5G6R5_UNORM
:
269 return V_028C70_SWAP_STD_REV
;
271 case PIPE_FORMAT_B5G5R5A1_UNORM
:
272 case PIPE_FORMAT_B5G5R5X1_UNORM
:
273 return V_028C70_SWAP_ALT
;
275 case PIPE_FORMAT_B4G4R4A4_UNORM
:
276 case PIPE_FORMAT_B4G4R4X4_UNORM
:
277 return V_028C70_SWAP_ALT
;
279 case PIPE_FORMAT_Z16_UNORM
:
280 return V_028C70_SWAP_STD
;
282 case PIPE_FORMAT_L8A8_UNORM
:
283 case PIPE_FORMAT_L8A8_SNORM
:
284 case PIPE_FORMAT_L8A8_UINT
:
285 case PIPE_FORMAT_L8A8_SINT
:
286 case PIPE_FORMAT_L8A8_SRGB
:
287 case PIPE_FORMAT_L16A16_UNORM
:
288 case PIPE_FORMAT_L16A16_SNORM
:
289 case PIPE_FORMAT_L16A16_UINT
:
290 case PIPE_FORMAT_L16A16_SINT
:
291 case PIPE_FORMAT_L16A16_FLOAT
:
292 case PIPE_FORMAT_L32A32_UINT
:
293 case PIPE_FORMAT_L32A32_SINT
:
294 case PIPE_FORMAT_L32A32_FLOAT
:
295 case PIPE_FORMAT_R8A8_UNORM
:
296 case PIPE_FORMAT_R8A8_SNORM
:
297 case PIPE_FORMAT_R8A8_UINT
:
298 case PIPE_FORMAT_R8A8_SINT
:
299 case PIPE_FORMAT_R16A16_UNORM
:
300 case PIPE_FORMAT_R16A16_SNORM
:
301 case PIPE_FORMAT_R16A16_UINT
:
302 case PIPE_FORMAT_R16A16_SINT
:
303 case PIPE_FORMAT_R16A16_FLOAT
:
304 case PIPE_FORMAT_R32A32_UINT
:
305 case PIPE_FORMAT_R32A32_SINT
:
306 case PIPE_FORMAT_R32A32_FLOAT
:
307 return V_028C70_SWAP_ALT
;
308 case PIPE_FORMAT_R8G8_UNORM
:
309 case PIPE_FORMAT_R8G8_SNORM
:
310 case PIPE_FORMAT_R8G8_UINT
:
311 case PIPE_FORMAT_R8G8_SINT
:
312 return V_028C70_SWAP_STD
;
314 case PIPE_FORMAT_R16_UNORM
:
315 case PIPE_FORMAT_R16_SNORM
:
316 case PIPE_FORMAT_R16_UINT
:
317 case PIPE_FORMAT_R16_SINT
:
318 case PIPE_FORMAT_R16_FLOAT
:
319 return V_028C70_SWAP_STD
;
321 /* 32-bit buffers. */
322 case PIPE_FORMAT_A8B8G8R8_SRGB
:
323 return V_028C70_SWAP_STD_REV
;
324 case PIPE_FORMAT_B8G8R8A8_SRGB
:
325 return V_028C70_SWAP_ALT
;
327 case PIPE_FORMAT_B8G8R8A8_UNORM
:
328 case PIPE_FORMAT_B8G8R8X8_UNORM
:
329 return V_028C70_SWAP_ALT
;
331 case PIPE_FORMAT_A8R8G8B8_UNORM
:
332 case PIPE_FORMAT_X8R8G8B8_UNORM
:
333 return V_028C70_SWAP_ALT_REV
;
334 case PIPE_FORMAT_R8G8B8A8_SNORM
:
335 case PIPE_FORMAT_R8G8B8A8_UNORM
:
336 case PIPE_FORMAT_R8G8B8A8_SINT
:
337 case PIPE_FORMAT_R8G8B8A8_UINT
:
338 case PIPE_FORMAT_R8G8B8X8_UNORM
:
339 case PIPE_FORMAT_R8G8B8X8_SNORM
:
340 case PIPE_FORMAT_R8G8B8X8_SRGB
:
341 case PIPE_FORMAT_R8G8B8X8_UINT
:
342 case PIPE_FORMAT_R8G8B8X8_SINT
:
343 return V_028C70_SWAP_STD
;
345 case PIPE_FORMAT_A8B8G8R8_UNORM
:
346 case PIPE_FORMAT_X8B8G8R8_UNORM
:
347 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
348 return V_028C70_SWAP_STD_REV
;
350 case PIPE_FORMAT_Z24X8_UNORM
:
351 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
352 return V_028C70_SWAP_STD
;
354 case PIPE_FORMAT_X8Z24_UNORM
:
355 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
356 return V_028C70_SWAP_STD_REV
;
358 case PIPE_FORMAT_R10G10B10A2_UNORM
:
359 case PIPE_FORMAT_R10G10B10X2_SNORM
:
360 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
361 return V_028C70_SWAP_STD
;
363 case PIPE_FORMAT_B10G10R10A2_UNORM
:
364 case PIPE_FORMAT_B10G10R10A2_UINT
:
365 case PIPE_FORMAT_B10G10R10X2_UNORM
:
366 return V_028C70_SWAP_ALT
;
368 case PIPE_FORMAT_R11G11B10_FLOAT
:
369 case PIPE_FORMAT_R32_FLOAT
:
370 case PIPE_FORMAT_R32_UINT
:
371 case PIPE_FORMAT_R32_SINT
:
372 case PIPE_FORMAT_Z32_FLOAT
:
373 case PIPE_FORMAT_R16G16_FLOAT
:
374 case PIPE_FORMAT_R16G16_UNORM
:
375 case PIPE_FORMAT_R16G16_SNORM
:
376 case PIPE_FORMAT_R16G16_UINT
:
377 case PIPE_FORMAT_R16G16_SINT
:
378 return V_028C70_SWAP_STD
;
380 /* 64-bit buffers. */
381 case PIPE_FORMAT_R32G32_FLOAT
:
382 case PIPE_FORMAT_R32G32_UINT
:
383 case PIPE_FORMAT_R32G32_SINT
:
384 case PIPE_FORMAT_R16G16B16A16_UNORM
:
385 case PIPE_FORMAT_R16G16B16A16_SNORM
:
386 case PIPE_FORMAT_R16G16B16A16_UINT
:
387 case PIPE_FORMAT_R16G16B16A16_SINT
:
388 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
389 case PIPE_FORMAT_R16G16B16X16_UNORM
:
390 case PIPE_FORMAT_R16G16B16X16_SNORM
:
391 case PIPE_FORMAT_R16G16B16X16_FLOAT
:
392 case PIPE_FORMAT_R16G16B16X16_UINT
:
393 case PIPE_FORMAT_R16G16B16X16_SINT
:
394 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
396 /* 128-bit buffers. */
397 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
398 case PIPE_FORMAT_R32G32B32A32_SNORM
:
399 case PIPE_FORMAT_R32G32B32A32_UNORM
:
400 case PIPE_FORMAT_R32G32B32A32_SINT
:
401 case PIPE_FORMAT_R32G32B32A32_UINT
:
402 case PIPE_FORMAT_R32G32B32X32_FLOAT
:
403 case PIPE_FORMAT_R32G32B32X32_UINT
:
404 case PIPE_FORMAT_R32G32B32X32_SINT
:
405 return V_028C70_SWAP_STD
;
407 R600_ERR("unsupported colorswap format %d\n", format
);
413 static uint32_t r600_translate_colorformat(enum pipe_format format
)
417 case PIPE_FORMAT_A8_UNORM
:
418 case PIPE_FORMAT_A8_SNORM
:
419 case PIPE_FORMAT_A8_UINT
:
420 case PIPE_FORMAT_A8_SINT
:
421 case PIPE_FORMAT_I8_UNORM
:
422 case PIPE_FORMAT_I8_SNORM
:
423 case PIPE_FORMAT_I8_UINT
:
424 case PIPE_FORMAT_I8_SINT
:
425 case PIPE_FORMAT_L8_UNORM
:
426 case PIPE_FORMAT_L8_SNORM
:
427 case PIPE_FORMAT_L8_UINT
:
428 case PIPE_FORMAT_L8_SINT
:
429 case PIPE_FORMAT_L8_SRGB
:
430 case PIPE_FORMAT_R8_UNORM
:
431 case PIPE_FORMAT_R8_SNORM
:
432 case PIPE_FORMAT_R8_UINT
:
433 case PIPE_FORMAT_R8_SINT
:
434 return V_028C70_COLOR_8
;
436 /* 16-bit buffers. */
437 case PIPE_FORMAT_B5G6R5_UNORM
:
438 return V_028C70_COLOR_5_6_5
;
440 case PIPE_FORMAT_B5G5R5A1_UNORM
:
441 case PIPE_FORMAT_B5G5R5X1_UNORM
:
442 return V_028C70_COLOR_1_5_5_5
;
444 case PIPE_FORMAT_B4G4R4A4_UNORM
:
445 case PIPE_FORMAT_B4G4R4X4_UNORM
:
446 return V_028C70_COLOR_4_4_4_4
;
448 case PIPE_FORMAT_Z16_UNORM
:
449 return V_028C70_COLOR_16
;
451 case PIPE_FORMAT_L8A8_UNORM
:
452 case PIPE_FORMAT_L8A8_SNORM
:
453 case PIPE_FORMAT_L8A8_UINT
:
454 case PIPE_FORMAT_L8A8_SINT
:
455 case PIPE_FORMAT_L8A8_SRGB
:
456 case PIPE_FORMAT_R8G8_UNORM
:
457 case PIPE_FORMAT_R8G8_SNORM
:
458 case PIPE_FORMAT_R8G8_UINT
:
459 case PIPE_FORMAT_R8G8_SINT
:
460 case PIPE_FORMAT_R8A8_UNORM
:
461 case PIPE_FORMAT_R8A8_SNORM
:
462 case PIPE_FORMAT_R8A8_UINT
:
463 case PIPE_FORMAT_R8A8_SINT
:
464 return V_028C70_COLOR_8_8
;
466 case PIPE_FORMAT_R16_UNORM
:
467 case PIPE_FORMAT_R16_SNORM
:
468 case PIPE_FORMAT_R16_UINT
:
469 case PIPE_FORMAT_R16_SINT
:
470 case PIPE_FORMAT_A16_UNORM
:
471 case PIPE_FORMAT_A16_SNORM
:
472 case PIPE_FORMAT_A16_UINT
:
473 case PIPE_FORMAT_A16_SINT
:
474 case PIPE_FORMAT_L16_UNORM
:
475 case PIPE_FORMAT_L16_SNORM
:
476 case PIPE_FORMAT_L16_UINT
:
477 case PIPE_FORMAT_L16_SINT
:
478 case PIPE_FORMAT_I16_UNORM
:
479 case PIPE_FORMAT_I16_SNORM
:
480 case PIPE_FORMAT_I16_UINT
:
481 case PIPE_FORMAT_I16_SINT
:
482 return V_028C70_COLOR_16
;
484 case PIPE_FORMAT_R16_FLOAT
:
485 case PIPE_FORMAT_A16_FLOAT
:
486 case PIPE_FORMAT_L16_FLOAT
:
487 case PIPE_FORMAT_I16_FLOAT
:
488 return V_028C70_COLOR_16_FLOAT
;
490 /* 32-bit buffers. */
491 case PIPE_FORMAT_A8B8G8R8_SRGB
:
492 case PIPE_FORMAT_A8B8G8R8_UNORM
:
493 case PIPE_FORMAT_A8R8G8B8_UNORM
:
494 case PIPE_FORMAT_B8G8R8A8_SRGB
:
495 case PIPE_FORMAT_B8G8R8A8_UNORM
:
496 case PIPE_FORMAT_B8G8R8X8_UNORM
:
497 case PIPE_FORMAT_R8G8B8A8_SNORM
:
498 case PIPE_FORMAT_R8G8B8A8_UNORM
:
499 case PIPE_FORMAT_R8G8B8X8_UNORM
:
500 case PIPE_FORMAT_R8G8B8X8_SNORM
:
501 case PIPE_FORMAT_R8G8B8X8_SRGB
:
502 case PIPE_FORMAT_R8G8B8X8_UINT
:
503 case PIPE_FORMAT_R8G8B8X8_SINT
:
504 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
505 case PIPE_FORMAT_X8B8G8R8_UNORM
:
506 case PIPE_FORMAT_X8R8G8B8_UNORM
:
507 case PIPE_FORMAT_R8G8B8_UNORM
:
508 case PIPE_FORMAT_R8G8B8A8_SINT
:
509 case PIPE_FORMAT_R8G8B8A8_UINT
:
510 return V_028C70_COLOR_8_8_8_8
;
512 case PIPE_FORMAT_R10G10B10A2_UNORM
:
513 case PIPE_FORMAT_R10G10B10X2_SNORM
:
514 case PIPE_FORMAT_B10G10R10A2_UNORM
:
515 case PIPE_FORMAT_B10G10R10A2_UINT
:
516 case PIPE_FORMAT_B10G10R10X2_UNORM
:
517 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
518 return V_028C70_COLOR_2_10_10_10
;
520 case PIPE_FORMAT_Z24X8_UNORM
:
521 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
522 return V_028C70_COLOR_8_24
;
524 case PIPE_FORMAT_X8Z24_UNORM
:
525 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
526 return V_028C70_COLOR_24_8
;
528 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
529 return V_028C70_COLOR_X24_8_32_FLOAT
;
531 case PIPE_FORMAT_R32_UINT
:
532 case PIPE_FORMAT_R32_SINT
:
533 case PIPE_FORMAT_A32_UINT
:
534 case PIPE_FORMAT_A32_SINT
:
535 case PIPE_FORMAT_L32_UINT
:
536 case PIPE_FORMAT_L32_SINT
:
537 case PIPE_FORMAT_I32_UINT
:
538 case PIPE_FORMAT_I32_SINT
:
539 return V_028C70_COLOR_32
;
541 case PIPE_FORMAT_R32_FLOAT
:
542 case PIPE_FORMAT_A32_FLOAT
:
543 case PIPE_FORMAT_L32_FLOAT
:
544 case PIPE_FORMAT_I32_FLOAT
:
545 case PIPE_FORMAT_Z32_FLOAT
:
546 return V_028C70_COLOR_32_FLOAT
;
548 case PIPE_FORMAT_R16G16_FLOAT
:
549 case PIPE_FORMAT_L16A16_FLOAT
:
550 case PIPE_FORMAT_R16A16_FLOAT
:
551 return V_028C70_COLOR_16_16_FLOAT
;
553 case PIPE_FORMAT_R16G16_UNORM
:
554 case PIPE_FORMAT_R16G16_SNORM
:
555 case PIPE_FORMAT_R16G16_UINT
:
556 case PIPE_FORMAT_R16G16_SINT
:
557 case PIPE_FORMAT_L16A16_UNORM
:
558 case PIPE_FORMAT_L16A16_SNORM
:
559 case PIPE_FORMAT_L16A16_UINT
:
560 case PIPE_FORMAT_L16A16_SINT
:
561 case PIPE_FORMAT_R16A16_UNORM
:
562 case PIPE_FORMAT_R16A16_SNORM
:
563 case PIPE_FORMAT_R16A16_UINT
:
564 case PIPE_FORMAT_R16A16_SINT
:
565 return V_028C70_COLOR_16_16
;
567 case PIPE_FORMAT_R11G11B10_FLOAT
:
568 return V_028C70_COLOR_10_11_11_FLOAT
;
570 /* 64-bit buffers. */
571 case PIPE_FORMAT_R16G16B16A16_UINT
:
572 case PIPE_FORMAT_R16G16B16A16_SINT
:
573 case PIPE_FORMAT_R16G16B16A16_UNORM
:
574 case PIPE_FORMAT_R16G16B16A16_SNORM
:
575 case PIPE_FORMAT_R16G16B16X16_UNORM
:
576 case PIPE_FORMAT_R16G16B16X16_SNORM
:
577 case PIPE_FORMAT_R16G16B16X16_UINT
:
578 case PIPE_FORMAT_R16G16B16X16_SINT
:
579 return V_028C70_COLOR_16_16_16_16
;
581 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
582 case PIPE_FORMAT_R16G16B16X16_FLOAT
:
583 return V_028C70_COLOR_16_16_16_16_FLOAT
;
585 case PIPE_FORMAT_R32G32_FLOAT
:
586 case PIPE_FORMAT_L32A32_FLOAT
:
587 case PIPE_FORMAT_R32A32_FLOAT
:
588 return V_028C70_COLOR_32_32_FLOAT
;
590 case PIPE_FORMAT_R32G32_SINT
:
591 case PIPE_FORMAT_R32G32_UINT
:
592 case PIPE_FORMAT_L32A32_UINT
:
593 case PIPE_FORMAT_L32A32_SINT
:
594 return V_028C70_COLOR_32_32
;
596 /* 128-bit buffers. */
597 case PIPE_FORMAT_R32G32B32A32_SNORM
:
598 case PIPE_FORMAT_R32G32B32A32_UNORM
:
599 case PIPE_FORMAT_R32G32B32A32_SINT
:
600 case PIPE_FORMAT_R32G32B32A32_UINT
:
601 case PIPE_FORMAT_R32G32B32X32_UINT
:
602 case PIPE_FORMAT_R32G32B32X32_SINT
:
603 return V_028C70_COLOR_32_32_32_32
;
604 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
605 case PIPE_FORMAT_R32G32B32X32_FLOAT
:
606 return V_028C70_COLOR_32_32_32_32_FLOAT
;
609 case PIPE_FORMAT_UYVY
:
610 case PIPE_FORMAT_YUYV
:
612 return ~0U; /* Unsupported. */
616 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
618 if (R600_BIG_ENDIAN
) {
619 switch(colorformat
) {
622 case V_028C70_COLOR_8
:
625 /* 16-bit buffers. */
626 case V_028C70_COLOR_5_6_5
:
627 case V_028C70_COLOR_1_5_5_5
:
628 case V_028C70_COLOR_4_4_4_4
:
629 case V_028C70_COLOR_16
:
630 case V_028C70_COLOR_8_8
:
633 /* 32-bit buffers. */
634 case V_028C70_COLOR_8_8_8_8
:
635 case V_028C70_COLOR_2_10_10_10
:
636 case V_028C70_COLOR_8_24
:
637 case V_028C70_COLOR_24_8
:
638 case V_028C70_COLOR_32_FLOAT
:
639 case V_028C70_COLOR_16_16_FLOAT
:
640 case V_028C70_COLOR_16_16
:
643 /* 64-bit buffers. */
644 case V_028C70_COLOR_16_16_16_16
:
645 case V_028C70_COLOR_16_16_16_16_FLOAT
:
648 case V_028C70_COLOR_32_32_FLOAT
:
649 case V_028C70_COLOR_32_32
:
650 case V_028C70_COLOR_X24_8_32_FLOAT
:
653 /* 96-bit buffers. */
654 case V_028C70_COLOR_32_32_32_FLOAT
:
655 /* 128-bit buffers. */
656 case V_028C70_COLOR_32_32_32_32_FLOAT
:
657 case V_028C70_COLOR_32_32_32_32
:
660 return ENDIAN_NONE
; /* Unsupported. */
667 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
669 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
672 static bool r600_is_colorbuffer_format_supported(enum pipe_format format
)
674 return r600_translate_colorformat(format
) != ~0U &&
675 r600_translate_colorswap(format
) != ~0U;
678 static bool r600_is_zs_format_supported(enum pipe_format format
)
680 return r600_translate_dbformat(format
) != ~0U;
683 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
684 enum pipe_format format
,
685 enum pipe_texture_target target
,
686 unsigned sample_count
,
689 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
692 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
693 R600_ERR("r600: unsupported texture type %d\n", target
);
697 if (!util_format_is_supported(format
, usage
))
700 if (sample_count
> 1) {
701 if (!rscreen
->has_msaa
)
704 switch (sample_count
) {
714 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
715 r600_is_sampler_format_supported(screen
, format
)) {
716 retval
|= PIPE_BIND_SAMPLER_VIEW
;
719 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
720 PIPE_BIND_DISPLAY_TARGET
|
722 PIPE_BIND_SHARED
)) &&
723 r600_is_colorbuffer_format_supported(format
)) {
725 (PIPE_BIND_RENDER_TARGET
|
726 PIPE_BIND_DISPLAY_TARGET
|
731 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
732 r600_is_zs_format_supported(format
)) {
733 retval
|= PIPE_BIND_DEPTH_STENCIL
;
736 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
737 r600_is_vertex_format_supported(format
)) {
738 retval
|= PIPE_BIND_VERTEX_BUFFER
;
741 if (usage
& PIPE_BIND_TRANSFER_READ
)
742 retval
|= PIPE_BIND_TRANSFER_READ
;
743 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
744 retval
|= PIPE_BIND_TRANSFER_WRITE
;
746 return retval
== usage
;
749 static void *evergreen_create_blend_state_mode(struct pipe_context
*ctx
,
750 const struct pipe_blend_state
*state
, int mode
)
752 uint32_t color_control
= 0, target_mask
= 0;
753 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
759 r600_init_command_buffer(&blend
->buffer
, 20);
760 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
762 if (state
->logicop_enable
) {
763 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
765 color_control
|= (0xcc << 16);
767 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
768 if (state
->independent_blend_enable
) {
769 for (int i
= 0; i
< 8; i
++) {
770 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
773 for (int i
= 0; i
< 8; i
++) {
774 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
778 /* only have dual source on MRT0 */
779 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
780 blend
->cb_target_mask
= target_mask
;
781 blend
->alpha_to_one
= state
->alpha_to_one
;
784 color_control
|= S_028808_MODE(mode
);
786 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
789 r600_store_context_reg(&blend
->buffer
, R_028808_CB_COLOR_CONTROL
, color_control
);
790 r600_store_context_reg(&blend
->buffer
, R_028B70_DB_ALPHA_TO_MASK
,
791 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
792 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
793 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
794 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
795 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
796 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
798 /* Copy over the dwords set so far into buffer_no_blend.
799 * Only the CB_BLENDi_CONTROL registers must be set after this. */
800 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
801 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
803 for (int i
= 0; i
< 8; i
++) {
804 /* state->rt entries > 0 only written if independent blending */
805 const int j
= state
->independent_blend_enable
? i
: 0;
807 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
808 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
809 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
810 unsigned eqA
= state
->rt
[j
].alpha_func
;
811 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
812 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
815 r600_store_value(&blend
->buffer_no_blend
, 0);
817 if (!state
->rt
[j
].blend_enable
) {
818 r600_store_value(&blend
->buffer
, 0);
822 bc
|= S_028780_BLEND_CONTROL_ENABLE(1);
823 bc
|= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
824 bc
|= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
825 bc
|= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
827 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
828 bc
|= S_028780_SEPARATE_ALPHA_BLEND(1);
829 bc
|= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
830 bc
|= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
831 bc
|= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
833 r600_store_value(&blend
->buffer
, bc
);
838 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
839 const struct pipe_blend_state
*state
)
842 return evergreen_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
845 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
846 const struct pipe_depth_stencil_alpha_state
*state
)
848 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
849 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
855 r600_init_command_buffer(&dsa
->buffer
, 3);
857 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
858 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
859 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
860 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
861 dsa
->zwritemask
= state
->depth
.writemask
;
863 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
864 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
865 S_028800_ZFUNC(state
->depth
.func
);
868 if (state
->stencil
[0].enabled
) {
869 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
870 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
871 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
872 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
873 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
875 if (state
->stencil
[1].enabled
) {
876 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
877 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
878 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
879 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
880 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
885 alpha_test_control
= 0;
887 if (state
->alpha
.enabled
) {
888 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
889 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
890 alpha_ref
= fui(state
->alpha
.ref_value
);
892 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
893 dsa
->alpha_ref
= alpha_ref
;
896 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
900 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
901 const struct pipe_rasterizer_state
*state
)
903 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
904 unsigned tmp
, spi_interp
;
905 float psize_min
, psize_max
;
906 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
912 r600_init_command_buffer(&rs
->buffer
, 30);
914 rs
->flatshade
= state
->flatshade
;
915 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
916 rs
->two_side
= state
->light_twoside
;
917 rs
->clip_plane_enable
= state
->clip_plane_enable
;
918 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
919 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
920 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
921 rs
->pa_cl_clip_cntl
=
922 S_028810_PS_UCP_MODE(3) |
923 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
924 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
925 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
926 rs
->multisample_enable
= state
->multisample
;
929 rs
->offset_units
= state
->offset_units
;
930 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
931 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
933 if (state
->point_size_per_vertex
) {
934 psize_min
= util_get_min_point_size(state
);
937 /* Force the point size to be as if the vertex output was disabled. */
938 psize_min
= state
->point_size
;
939 psize_max
= state
->point_size
;
942 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
943 if (state
->sprite_coord_enable
) {
944 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
945 S_0286D4_PNT_SPRITE_OVRD_X(2) |
946 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
947 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
948 S_0286D4_PNT_SPRITE_OVRD_W(1);
949 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
950 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
954 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
955 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
956 tmp
= r600_pack_float_12p4(state
->point_size
/2);
957 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
958 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
959 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
960 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
961 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
962 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
963 S_028A08_WIDTH((unsigned)(state
->line_width
* 8)));
965 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
966 r600_store_context_reg(&rs
->buffer
, R_028A48_PA_SC_MODE_CNTL_0
,
967 S_028A48_MSAA_ENABLE(state
->multisample
) |
968 S_028A48_VPORT_SCISSOR_ENABLE(state
->scissor
) |
969 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
));
971 if (rctx
->chip_class
== CAYMAN
) {
972 r600_store_context_reg(&rs
->buffer
, CM_R_028BE4_PA_SU_VTX_CNTL
,
973 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
) |
974 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
976 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
977 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
) |
978 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
981 r600_store_context_reg(&rs
->buffer
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
982 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
,
983 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
984 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
985 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
986 S_028814_FACE(!state
->front_ccw
) |
987 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
988 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
989 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
990 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
991 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
992 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
993 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
994 r600_store_context_reg(&rs
->buffer
, R_028350_SX_MISC
, S_028350_MULTIPASS(state
->rasterizer_discard
));
998 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
999 const struct pipe_sampler_state
*state
)
1001 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
1002 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
1008 ss
->border_color_use
= sampler_state_needs_border_color(state
);
1010 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
1011 ss
->tex_sampler_words
[0] =
1012 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
1013 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
1014 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
1015 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
1016 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
1017 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
1018 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
1019 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
1020 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
1021 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
1022 ss
->tex_sampler_words
[1] =
1023 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
1024 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8));
1025 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
1026 ss
->tex_sampler_words
[2] =
1027 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
1028 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
1031 if (ss
->border_color_use
) {
1032 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
1037 static struct pipe_sampler_view
*
1038 texture_buffer_sampler_view(struct r600_pipe_sampler_view
*view
,
1039 unsigned width0
, unsigned height0
)
1042 struct pipe_context
*ctx
= view
->base
.context
;
1043 struct r600_texture
*tmp
= (struct r600_texture
*)view
->base
.texture
;
1045 int stride
= util_format_get_blocksize(view
->base
.format
);
1046 unsigned format
, num_format
, format_comp
, endian
;
1047 unsigned swizzle_res
;
1048 unsigned char swizzle
[4];
1049 const struct util_format_description
*desc
;
1051 swizzle
[0] = view
->base
.swizzle_r
;
1052 swizzle
[1] = view
->base
.swizzle_g
;
1053 swizzle
[2] = view
->base
.swizzle_b
;
1054 swizzle
[3] = view
->base
.swizzle_a
;
1056 r600_vertex_data_type(view
->base
.format
,
1057 &format
, &num_format
, &format_comp
,
1060 desc
= util_format_description(view
->base
.format
);
1062 swizzle_res
= r600_get_swizzle_combined(desc
->swizzle
, swizzle
, TRUE
);
1064 va
= r600_resource_va(ctx
->screen
, view
->base
.texture
);
1065 view
->tex_resource
= &tmp
->resource
;
1067 view
->skip_mip_address_reloc
= true;
1068 view
->tex_resource_words
[0] = va
;
1069 view
->tex_resource_words
[1] = width0
- 1;
1070 view
->tex_resource_words
[2] = S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
1071 S_030008_STRIDE(stride
) |
1072 S_030008_DATA_FORMAT(format
) |
1073 S_030008_NUM_FORMAT_ALL(num_format
) |
1074 S_030008_FORMAT_COMP_ALL(format_comp
) |
1075 S_030008_SRF_MODE_ALL(1) |
1076 S_030008_ENDIAN_SWAP(endian
);
1077 view
->tex_resource_words
[3] = swizzle_res
;
1079 * in theory dword 4 is for number of elements, for use with resinfo,
1080 * but it seems to utterly fail to work, the amd gpu shader analyser
1081 * uses a const buffer to store the element sizes for buffer txq
1083 view
->tex_resource_words
[4] = 0;
1084 view
->tex_resource_words
[5] = view
->tex_resource_words
[6] = 0;
1085 view
->tex_resource_words
[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
);
1089 struct pipe_sampler_view
*
1090 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
1091 struct pipe_resource
*texture
,
1092 const struct pipe_sampler_view
*state
,
1093 unsigned width0
, unsigned height0
)
1095 struct r600_screen
*rscreen
= (struct r600_screen
*)ctx
->screen
;
1096 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
1097 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
1098 unsigned format
, endian
;
1099 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
1100 unsigned char swizzle
[4], array_mode
= 0, non_disp_tiling
= 0;
1101 unsigned height
, depth
, width
;
1102 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1103 enum pipe_format pipe_format
= state
->format
;
1104 struct radeon_surface_level
*surflevel
;
1109 /* initialize base object */
1110 view
->base
= *state
;
1111 view
->base
.texture
= NULL
;
1112 pipe_reference(NULL
, &texture
->reference
);
1113 view
->base
.texture
= texture
;
1114 view
->base
.reference
.count
= 1;
1115 view
->base
.context
= ctx
;
1117 if (texture
->target
== PIPE_BUFFER
)
1118 return texture_buffer_sampler_view(view
, width0
, height0
);
1120 swizzle
[0] = state
->swizzle_r
;
1121 swizzle
[1] = state
->swizzle_g
;
1122 swizzle
[2] = state
->swizzle_b
;
1123 swizzle
[3] = state
->swizzle_a
;
1125 tile_split
= tmp
->surface
.tile_split
;
1126 surflevel
= tmp
->surface
.level
;
1128 /* Texturing with separate depth and stencil. */
1129 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
1130 switch (pipe_format
) {
1131 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1132 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1134 case PIPE_FORMAT_X8Z24_UNORM
:
1135 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1136 /* Z24 is always stored like this. */
1137 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1139 case PIPE_FORMAT_X24S8_UINT
:
1140 case PIPE_FORMAT_S8X24_UINT
:
1141 case PIPE_FORMAT_X32_S8X24_UINT
:
1142 pipe_format
= PIPE_FORMAT_S8_UINT
;
1143 tile_split
= tmp
->surface
.stencil_tile_split
;
1144 surflevel
= tmp
->surface
.stencil_level
;
1150 format
= r600_translate_texformat(ctx
->screen
, pipe_format
,
1152 &word4
, &yuv_format
);
1153 assert(format
!= ~0);
1159 endian
= r600_colorformat_endian_swap(format
);
1163 depth
= texture
->depth0
;
1164 pitch
= surflevel
[0].nblk_x
* util_format_get_blockwidth(pipe_format
);
1165 non_disp_tiling
= tmp
->non_disp_tiling
;
1167 switch (surflevel
[0].mode
) {
1168 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1169 array_mode
= V_028C70_ARRAY_LINEAR_ALIGNED
;
1171 case RADEON_SURF_MODE_2D
:
1172 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1174 case RADEON_SURF_MODE_1D
:
1175 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1177 case RADEON_SURF_MODE_LINEAR
:
1179 array_mode
= V_028C70_ARRAY_LINEAR_GENERAL
;
1182 macro_aspect
= tmp
->surface
.mtilea
;
1183 bankw
= tmp
->surface
.bankw
;
1184 bankh
= tmp
->surface
.bankh
;
1185 tile_split
= eg_tile_split(tile_split
);
1186 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1187 bankw
= eg_bank_wh(bankw
);
1188 bankh
= eg_bank_wh(bankh
);
1190 /* 128 bit formats require tile type = 1 */
1191 if (rscreen
->chip_class
== CAYMAN
) {
1192 if (util_format_get_blocksize(pipe_format
) >= 16)
1193 non_disp_tiling
= 1;
1195 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1197 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
1199 depth
= texture
->array_size
;
1200 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
1201 depth
= texture
->array_size
;
1202 } else if (texture
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
1203 depth
= texture
->array_size
/ 6;
1205 view
->tex_resource
= &tmp
->resource
;
1206 view
->tex_resource_words
[0] = (S_030000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
1207 S_030000_PITCH((pitch
/ 8) - 1) |
1208 S_030000_TEX_WIDTH(width
- 1));
1209 if (rscreen
->chip_class
== CAYMAN
)
1210 view
->tex_resource_words
[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
1212 view
->tex_resource_words
[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
1213 view
->tex_resource_words
[1] = (S_030004_TEX_HEIGHT(height
- 1) |
1214 S_030004_TEX_DEPTH(depth
- 1) |
1215 S_030004_ARRAY_MODE(array_mode
));
1216 view
->tex_resource_words
[2] = (surflevel
[0].offset
+ r600_resource_va(ctx
->screen
, texture
)) >> 8;
1218 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
1219 if (texture
->nr_samples
> 1 && rscreen
->msaa_texture_support
== MSAA_TEXTURE_COMPRESSED
) {
1220 /* XXX the 2x and 4x cases are broken. */
1221 if (tmp
->is_depth
|| tmp
->resource
.b
.b
.nr_samples
!= 8) {
1222 /* disable FMASK (0 = disabled) */
1223 view
->tex_resource_words
[3] = 0;
1224 view
->skip_mip_address_reloc
= true;
1226 /* FMASK should be in MIP_ADDRESS for multisample textures */
1227 view
->tex_resource_words
[3] = (tmp
->fmask_offset
+ r600_resource_va(ctx
->screen
, texture
)) >> 8;
1229 } else if (state
->u
.tex
.last_level
&& texture
->nr_samples
<= 1) {
1230 view
->tex_resource_words
[3] = (surflevel
[1].offset
+ r600_resource_va(ctx
->screen
, texture
)) >> 8;
1232 view
->tex_resource_words
[3] = (surflevel
[0].offset
+ r600_resource_va(ctx
->screen
, texture
)) >> 8;
1235 view
->tex_resource_words
[4] = (word4
|
1236 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
1237 S_030010_ENDIAN_SWAP(endian
));
1238 view
->tex_resource_words
[5] = S_030014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
1239 S_030014_LAST_ARRAY(state
->u
.tex
.last_layer
);
1240 if (texture
->nr_samples
> 1) {
1241 unsigned log_samples
= util_logbase2(texture
->nr_samples
);
1242 if (rscreen
->chip_class
== CAYMAN
) {
1243 view
->tex_resource_words
[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples
);
1245 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1246 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(log_samples
);
1248 view
->tex_resource_words
[4] |= S_030010_BASE_LEVEL(state
->u
.tex
.first_level
);
1249 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(state
->u
.tex
.last_level
);
1251 /* aniso max 16 samples */
1252 view
->tex_resource_words
[6] = (S_030018_MAX_ANISO(4)) |
1253 (S_030018_TILE_SPLIT(tile_split
));
1254 view
->tex_resource_words
[7] = S_03001C_DATA_FORMAT(format
) |
1255 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
) |
1256 S_03001C_BANK_WIDTH(bankw
) |
1257 S_03001C_BANK_HEIGHT(bankh
) |
1258 S_03001C_MACRO_TILE_ASPECT(macro_aspect
) |
1259 S_03001C_NUM_BANKS(nbanks
) |
1260 S_03001C_DEPTH_SAMPLE_ORDER(tmp
->is_depth
&& !tmp
->is_flushing_texture
);
1264 static struct pipe_sampler_view
*
1265 evergreen_create_sampler_view(struct pipe_context
*ctx
,
1266 struct pipe_resource
*tex
,
1267 const struct pipe_sampler_view
*state
)
1269 return evergreen_create_sampler_view_custom(ctx
, tex
, state
,
1270 tex
->width0
, tex
->height0
);
1273 static void evergreen_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1275 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1276 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
1278 r600_write_context_reg_seq(cs
, R_0285BC_PA_CL_UCP0_X
, 6*4);
1279 r600_write_array(cs
, 6*4, (unsigned*)state
);
1282 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
1283 const struct pipe_poly_stipple
*state
)
1287 static void evergreen_get_scissor_rect(struct r600_context
*rctx
,
1288 unsigned tl_x
, unsigned tl_y
, unsigned br_x
, unsigned br_y
,
1289 uint32_t *tl
, uint32_t *br
)
1291 /* EG hw workaround */
1297 /* cayman hw workaround */
1298 if (rctx
->chip_class
== CAYMAN
) {
1299 if (br_x
== 1 && br_y
== 1)
1303 *tl
= S_028240_TL_X(tl_x
) | S_028240_TL_Y(tl_y
);
1304 *br
= S_028244_BR_X(br_x
) | S_028244_BR_Y(br_y
);
1307 static void evergreen_set_scissor_state(struct pipe_context
*ctx
,
1308 const struct pipe_scissor_state
*state
)
1310 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1312 rctx
->scissor
.scissor
= *state
;
1313 rctx
->scissor
.atom
.dirty
= true;
1316 static void evergreen_emit_scissor_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1318 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1319 struct pipe_scissor_state
*state
= &rctx
->scissor
.scissor
;
1322 evergreen_get_scissor_rect(rctx
, state
->minx
, state
->miny
, state
->maxx
, state
->maxy
, &tl
, &br
);
1324 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
1325 r600_write_value(cs
, tl
);
1326 r600_write_value(cs
, br
);
1330 * This function intializes the CB* register values for RATs. It is meant
1331 * to be used for 1D aligned buffers that do not have an associated
1334 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
1335 struct r600_surface
*surf
)
1337 struct pipe_resource
*pipe_buffer
= surf
->base
.texture
;
1338 unsigned format
= r600_translate_colorformat(surf
->base
.format
);
1339 unsigned endian
= r600_colorformat_endian_swap(format
);
1340 unsigned swap
= r600_translate_colorswap(surf
->base
.format
);
1341 unsigned block_size
=
1342 align(util_format_get_blocksize(pipe_buffer
->format
), 4);
1343 unsigned pitch_alignment
=
1344 MAX2(64, rctx
->screen
->tiling_info
.group_bytes
/ block_size
);
1345 unsigned pitch
= align(pipe_buffer
->width0
, pitch_alignment
);
1347 /* XXX: This is copied from evergreen_init_color_surface(). I don't
1348 * know why this is necessary.
1350 if (pipe_buffer
->usage
== PIPE_USAGE_STAGING
) {
1351 endian
= ENDIAN_NONE
;
1354 surf
->cb_color_base
=
1355 r600_resource_va(rctx
->context
.screen
, pipe_buffer
) >> 8;
1357 surf
->cb_color_pitch
= (pitch
/ 8) - 1;
1359 surf
->cb_color_slice
= 0;
1361 surf
->cb_color_view
= 0;
1363 surf
->cb_color_info
=
1364 S_028C70_ENDIAN(endian
)
1365 | S_028C70_FORMAT(format
)
1366 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
)
1367 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT
)
1368 | S_028C70_COMP_SWAP(swap
)
1369 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
1370 * are using NUMBER_UINT */
1374 surf
->cb_color_attrib
= S_028C74_NON_DISP_TILING_ORDER(1);
1376 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
1378 surf
->cb_color_dim
= pipe_buffer
->width0
;
1380 /* Set the buffer range the GPU will have access to: */
1381 util_range_add(&r600_resource(pipe_buffer
)->valid_buffer_range
,
1382 0, pipe_buffer
->width0
);
1384 surf
->cb_color_cmask
= surf
->cb_color_base
;
1385 surf
->cb_color_cmask_slice
= 0;
1386 surf
->cb_color_fmask
= surf
->cb_color_base
;
1387 surf
->cb_color_fmask_slice
= 0;
1390 void evergreen_init_color_surface(struct r600_context
*rctx
,
1391 struct r600_surface
*surf
)
1393 struct r600_screen
*rscreen
= rctx
->screen
;
1394 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1395 struct pipe_resource
*pipe_tex
= surf
->base
.texture
;
1396 unsigned level
= surf
->base
.u
.tex
.level
;
1397 unsigned pitch
, slice
;
1398 unsigned color_info
, color_attrib
, color_dim
= 0;
1399 unsigned format
, swap
, ntype
, endian
;
1400 uint64_t offset
, base_offset
;
1401 unsigned non_disp_tiling
, macro_aspect
, tile_split
, bankh
, bankw
, fmask_bankh
, nbanks
;
1402 const struct util_format_description
*desc
;
1404 bool blend_clamp
= 0, blend_bypass
= 0;
1406 offset
= rtex
->surface
.level
[level
].offset
;
1407 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1408 offset
+= rtex
->surface
.level
[level
].slice_size
*
1409 surf
->base
.u
.tex
.first_layer
;
1411 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1412 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1417 switch (rtex
->surface
.level
[level
].mode
) {
1418 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1419 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1420 non_disp_tiling
= 1;
1422 case RADEON_SURF_MODE_1D
:
1423 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1
);
1424 non_disp_tiling
= rtex
->non_disp_tiling
;
1426 case RADEON_SURF_MODE_2D
:
1427 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1
);
1428 non_disp_tiling
= rtex
->non_disp_tiling
;
1430 case RADEON_SURF_MODE_LINEAR
:
1432 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL
);
1433 non_disp_tiling
= 1;
1436 tile_split
= rtex
->surface
.tile_split
;
1437 macro_aspect
= rtex
->surface
.mtilea
;
1438 bankw
= rtex
->surface
.bankw
;
1439 bankh
= rtex
->surface
.bankh
;
1440 fmask_bankh
= rtex
->fmask_bank_height
;
1441 tile_split
= eg_tile_split(tile_split
);
1442 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1443 bankw
= eg_bank_wh(bankw
);
1444 bankh
= eg_bank_wh(bankh
);
1445 fmask_bankh
= eg_bank_wh(fmask_bankh
);
1447 /* 128 bit formats require tile type = 1 */
1448 if (rscreen
->chip_class
== CAYMAN
) {
1449 if (util_format_get_blocksize(surf
->base
.format
) >= 16)
1450 non_disp_tiling
= 1;
1452 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1453 desc
= util_format_description(surf
->base
.format
);
1454 for (i
= 0; i
< 4; i
++) {
1455 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1460 color_attrib
= S_028C74_TILE_SPLIT(tile_split
)|
1461 S_028C74_NUM_BANKS(nbanks
) |
1462 S_028C74_BANK_WIDTH(bankw
) |
1463 S_028C74_BANK_HEIGHT(bankh
) |
1464 S_028C74_MACRO_TILE_ASPECT(macro_aspect
) |
1465 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling
) |
1466 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
1468 if (rctx
->chip_class
== CAYMAN
) {
1469 color_attrib
|= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] ==
1470 UTIL_FORMAT_SWIZZLE_1
);
1472 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1473 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
1474 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1475 S_028C74_NUM_FRAGMENTS(log_samples
);
1479 ntype
= V_028C70_NUMBER_UNORM
;
1480 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1481 ntype
= V_028C70_NUMBER_SRGB
;
1482 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1483 if (desc
->channel
[i
].normalized
)
1484 ntype
= V_028C70_NUMBER_SNORM
;
1485 else if (desc
->channel
[i
].pure_integer
)
1486 ntype
= V_028C70_NUMBER_SINT
;
1487 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1488 if (desc
->channel
[i
].normalized
)
1489 ntype
= V_028C70_NUMBER_UNORM
;
1490 else if (desc
->channel
[i
].pure_integer
)
1491 ntype
= V_028C70_NUMBER_UINT
;
1494 format
= r600_translate_colorformat(surf
->base
.format
);
1495 assert(format
!= ~0);
1497 swap
= r600_translate_colorswap(surf
->base
.format
);
1500 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1501 endian
= ENDIAN_NONE
;
1503 endian
= r600_colorformat_endian_swap(format
);
1506 /* blend clamp should be set for all NORM/SRGB types */
1507 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
1508 ntype
== V_028C70_NUMBER_SRGB
)
1511 /* set blend bypass according to docs if SINT/UINT or
1512 8/24 COLOR variants */
1513 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1514 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1515 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1520 surf
->alphatest_bypass
= ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
;
1522 color_info
|= S_028C70_FORMAT(format
) |
1523 S_028C70_COMP_SWAP(swap
) |
1524 S_028C70_BLEND_CLAMP(blend_clamp
) |
1525 S_028C70_BLEND_BYPASS(blend_bypass
) |
1526 S_028C70_NUMBER_TYPE(ntype
) |
1527 S_028C70_ENDIAN(endian
);
1530 color_info
|= S_028C70_RAT(1);
1531 color_dim
= S_028C78_WIDTH_MAX(pipe_tex
->width0
& 0xffff)
1532 | S_028C78_HEIGHT_MAX((pipe_tex
->width0
>> 16) & 0xffff);
1535 /* EXPORT_NORM is an optimzation that can be enabled for better
1536 * performance in certain cases.
1537 * EXPORT_NORM can be enabled if:
1538 * - 11-bit or smaller UNORM/SNORM/SRGB
1539 * - 16-bit or smaller FLOAT
1541 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1542 ((desc
->channel
[i
].size
< 12 &&
1543 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1544 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
1545 (desc
->channel
[i
].size
< 17 &&
1546 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1547 color_info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
1548 surf
->export_16bpc
= true;
1551 if (rtex
->fmask_size
&& rtex
->cmask_size
) {
1552 color_info
|= S_028C70_COMPRESSION(1) | S_028C70_FAST_CLEAR(1);
1555 base_offset
= r600_resource_va(rctx
->context
.screen
, pipe_tex
);
1557 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1558 surf
->cb_color_base
= (base_offset
+ offset
) >> 8;
1559 surf
->cb_color_dim
= color_dim
;
1560 surf
->cb_color_info
= color_info
;
1561 surf
->cb_color_pitch
= S_028C64_PITCH_TILE_MAX(pitch
);
1562 surf
->cb_color_slice
= S_028C68_SLICE_TILE_MAX(slice
);
1563 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1564 surf
->cb_color_view
= 0;
1566 surf
->cb_color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1567 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1569 surf
->cb_color_attrib
= color_attrib
;
1570 if (rtex
->fmask_size
&& rtex
->cmask_size
) {
1571 surf
->cb_color_fmask
= (base_offset
+ rtex
->fmask_offset
) >> 8;
1572 surf
->cb_color_cmask
= (base_offset
+ rtex
->cmask_offset
) >> 8;
1574 surf
->cb_color_fmask
= surf
->cb_color_base
;
1575 surf
->cb_color_cmask
= surf
->cb_color_base
;
1577 surf
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice
);
1578 surf
->cb_color_cmask_slice
= S_028C80_TILE_MAX(rtex
->cmask_slice_tile_max
);
1580 surf
->color_initialized
= true;
1583 static void evergreen_init_depth_surface(struct r600_context
*rctx
,
1584 struct r600_surface
*surf
)
1586 struct r600_screen
*rscreen
= rctx
->screen
;
1587 struct pipe_screen
*screen
= &rscreen
->screen
;
1588 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1590 unsigned level
, pitch
, slice
, format
, array_mode
;
1591 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1593 level
= surf
->base
.u
.tex
.level
;
1594 format
= r600_translate_dbformat(surf
->base
.format
);
1595 assert(format
!= ~0);
1597 offset
= r600_resource_va(screen
, surf
->base
.texture
);
1598 offset
+= rtex
->surface
.level
[level
].offset
;
1599 pitch
= (rtex
->surface
.level
[level
].nblk_x
/ 8) - 1;
1600 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1604 switch (rtex
->surface
.level
[level
].mode
) {
1605 case RADEON_SURF_MODE_2D
:
1606 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1608 case RADEON_SURF_MODE_1D
:
1609 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1610 case RADEON_SURF_MODE_LINEAR
:
1612 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1615 tile_split
= rtex
->surface
.tile_split
;
1616 macro_aspect
= rtex
->surface
.mtilea
;
1617 bankw
= rtex
->surface
.bankw
;
1618 bankh
= rtex
->surface
.bankh
;
1619 tile_split
= eg_tile_split(tile_split
);
1620 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1621 bankw
= eg_bank_wh(bankw
);
1622 bankh
= eg_bank_wh(bankh
);
1623 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1626 surf
->db_depth_info
= S_028040_ARRAY_MODE(array_mode
) |
1627 S_028040_FORMAT(format
) |
1628 S_028040_TILE_SPLIT(tile_split
)|
1629 S_028040_NUM_BANKS(nbanks
) |
1630 S_028040_BANK_WIDTH(bankw
) |
1631 S_028040_BANK_HEIGHT(bankh
) |
1632 S_028040_MACRO_TILE_ASPECT(macro_aspect
);
1633 if (rscreen
->chip_class
== CAYMAN
&& rtex
->resource
.b
.b
.nr_samples
> 1) {
1634 surf
->db_depth_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
1636 surf
->db_depth_base
= offset
;
1637 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1638 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1639 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX(pitch
);
1640 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX(slice
);
1642 switch (surf
->base
.format
) {
1643 case PIPE_FORMAT_Z24X8_UNORM
:
1644 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1645 case PIPE_FORMAT_X8Z24_UNORM
:
1646 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1647 surf
->pa_su_poly_offset_db_fmt_cntl
=
1648 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1650 case PIPE_FORMAT_Z32_FLOAT
:
1651 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1652 surf
->pa_su_poly_offset_db_fmt_cntl
=
1653 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1654 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1656 case PIPE_FORMAT_Z16_UNORM
:
1657 surf
->pa_su_poly_offset_db_fmt_cntl
=
1658 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1663 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1664 uint64_t stencil_offset
;
1665 unsigned stile_split
= rtex
->surface
.stencil_tile_split
;
1667 stile_split
= eg_tile_split(stile_split
);
1669 stencil_offset
= rtex
->surface
.stencil_level
[level
].offset
;
1670 stencil_offset
+= r600_resource_va(screen
, surf
->base
.texture
);
1672 surf
->db_stencil_base
= stencil_offset
>> 8;
1673 surf
->db_stencil_info
= S_028044_FORMAT(V_028044_STENCIL_8
) |
1674 S_028044_TILE_SPLIT(stile_split
);
1676 surf
->db_stencil_base
= offset
;
1677 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1678 * Older kernels are out of luck. */
1679 surf
->db_stencil_info
= rctx
->screen
->info
.drm_minor
>= 18 ?
1680 S_028044_FORMAT(V_028044_STENCIL_INVALID
) :
1681 S_028044_FORMAT(V_028044_STENCIL_8
);
1684 surf
->htile_enabled
= 0;
1685 /* use htile only for first level */
1686 if (rtex
->htile
&& !level
) {
1687 uint64_t va
= r600_resource_va(&rctx
->screen
->screen
, &rtex
->htile
->b
.b
);
1688 surf
->htile_enabled
= 1;
1689 surf
->db_htile_data_base
= va
>> 8;
1690 surf
->db_htile_surface
= S_028ABC_HTILE_WIDTH(1) |
1691 S_028ABC_HTILE_HEIGHT(1) |
1693 surf
->db_depth_info
|= S_028040_TILE_SURFACE_ENABLE(1);
1694 surf
->db_preload_control
= 0;
1697 surf
->depth_initialized
= true;
1700 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
1701 const struct pipe_framebuffer_state
*state
)
1703 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1704 struct r600_surface
*surf
;
1705 struct r600_texture
*rtex
;
1706 uint32_t i
, log_samples
;
1708 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1709 rctx
->flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1711 if (rctx
->framebuffer
.state
.cbufs
[0]->texture
->nr_samples
> 1) {
1712 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV_CB_META
;
1715 if (rctx
->framebuffer
.state
.zsbuf
) {
1716 rctx
->flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1718 rtex
= (struct r600_texture
*)rctx
->framebuffer
.state
.zsbuf
->texture
;
1720 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV_DB_META
;
1724 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1727 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1728 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&&
1729 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1730 rctx
->framebuffer
.compressed_cb_mask
= 0;
1732 if (state
->nr_cbufs
)
1733 rctx
->framebuffer
.nr_samples
= state
->cbufs
[0]->texture
->nr_samples
;
1734 else if (state
->zsbuf
)
1735 rctx
->framebuffer
.nr_samples
= state
->zsbuf
->texture
->nr_samples
;
1737 rctx
->framebuffer
.nr_samples
= 0;
1739 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1740 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1741 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1743 r600_context_add_resource_size(ctx
, state
->cbufs
[i
]->texture
);
1745 if (!surf
->color_initialized
) {
1746 evergreen_init_color_surface(rctx
, surf
);
1749 if (!surf
->export_16bpc
) {
1750 rctx
->framebuffer
.export_16bpc
= false;
1753 if (rtex
->fmask_size
&& rtex
->cmask_size
) {
1754 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1758 /* Update alpha-test state dependencies.
1759 * Alpha-test is done on the first colorbuffer only. */
1760 if (state
->nr_cbufs
) {
1761 surf
= (struct r600_surface
*)state
->cbufs
[0];
1762 if (rctx
->alphatest_state
.bypass
!= surf
->alphatest_bypass
) {
1763 rctx
->alphatest_state
.bypass
= surf
->alphatest_bypass
;
1764 rctx
->alphatest_state
.atom
.dirty
= true;
1766 if (rctx
->alphatest_state
.cb0_export_16bpc
!= surf
->export_16bpc
) {
1767 rctx
->alphatest_state
.cb0_export_16bpc
= surf
->export_16bpc
;
1768 rctx
->alphatest_state
.atom
.dirty
= true;
1774 surf
= (struct r600_surface
*)state
->zsbuf
;
1776 r600_context_add_resource_size(ctx
, state
->zsbuf
->texture
);
1778 if (!surf
->depth_initialized
) {
1779 evergreen_init_depth_surface(rctx
, surf
);
1782 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1783 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1784 rctx
->poly_offset_state
.atom
.dirty
= true;
1787 if (rctx
->db_state
.rsurf
!= surf
) {
1788 rctx
->db_state
.rsurf
= surf
;
1789 rctx
->db_state
.atom
.dirty
= true;
1790 rctx
->db_misc_state
.atom
.dirty
= true;
1792 } else if (rctx
->db_state
.rsurf
) {
1793 rctx
->db_state
.rsurf
= NULL
;
1794 rctx
->db_state
.atom
.dirty
= true;
1795 rctx
->db_misc_state
.atom
.dirty
= true;
1798 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1799 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1800 rctx
->cb_misc_state
.atom
.dirty
= true;
1803 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1804 rctx
->alphatest_state
.bypass
= false;
1805 rctx
->alphatest_state
.atom
.dirty
= true;
1808 log_samples
= util_logbase2(rctx
->framebuffer
.nr_samples
);
1809 if (rctx
->chip_class
== CAYMAN
&& rctx
->db_misc_state
.log_samples
!= log_samples
) {
1810 rctx
->db_misc_state
.log_samples
= log_samples
;
1811 rctx
->db_misc_state
.atom
.dirty
= true;
1814 evergreen_update_db_shader_control(rctx
);
1816 /* Calculate the CS size. */
1817 rctx
->framebuffer
.atom
.num_dw
= 4; /* SCISSOR */
1820 if (rctx
->chip_class
== EVERGREEN
) {
1821 switch (rctx
->framebuffer
.nr_samples
) {
1824 rctx
->framebuffer
.atom
.num_dw
+= 6;
1827 rctx
->framebuffer
.atom
.num_dw
+= 10;
1830 rctx
->framebuffer
.atom
.num_dw
+= 4;
1832 switch (rctx
->framebuffer
.nr_samples
) {
1835 rctx
->framebuffer
.atom
.num_dw
+= 12;
1838 rctx
->framebuffer
.atom
.num_dw
+= 16;
1841 rctx
->framebuffer
.atom
.num_dw
+= 18;
1844 rctx
->framebuffer
.atom
.num_dw
+= 7;
1848 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 21;
1849 if (rctx
->keep_tiling_flags
)
1850 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 2;
1851 rctx
->framebuffer
.atom
.num_dw
+= (12 - state
->nr_cbufs
) * 3;
1855 rctx
->framebuffer
.atom
.num_dw
+= 24;
1856 if (rctx
->keep_tiling_flags
)
1857 rctx
->framebuffer
.atom
.num_dw
+= 2;
1858 } else if (rctx
->screen
->info
.drm_minor
>= 18) {
1859 rctx
->framebuffer
.atom
.num_dw
+= 4;
1862 rctx
->framebuffer
.atom
.dirty
= true;
1865 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1866 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1867 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1868 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1869 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1871 static void evergreen_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
1874 * There are two locations (-4, 4), (4, -4). */
1875 static uint32_t sample_locs_2x
[] = {
1876 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1877 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1878 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1879 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1881 static unsigned max_dist_2x
= 4;
1883 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1884 static uint32_t sample_locs_4x
[] = {
1885 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1886 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1887 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1888 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1890 static unsigned max_dist_4x
= 6;
1892 static uint32_t sample_locs_8x
[] = {
1893 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1894 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1895 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1896 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1897 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1898 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1899 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1900 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1902 static unsigned max_dist_8x
= 7;
1904 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1905 unsigned max_dist
= 0;
1907 switch (nr_samples
) {
1912 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(sample_locs_2x
));
1913 r600_write_array(cs
, Elements(sample_locs_2x
), sample_locs_2x
);
1914 max_dist
= max_dist_2x
;
1917 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(sample_locs_4x
));
1918 r600_write_array(cs
, Elements(sample_locs_4x
), sample_locs_4x
);
1919 max_dist
= max_dist_4x
;
1922 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(sample_locs_8x
));
1923 r600_write_array(cs
, Elements(sample_locs_8x
), sample_locs_8x
);
1924 max_dist
= max_dist_8x
;
1928 if (nr_samples
> 1) {
1929 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1930 r600_write_value(cs
, S_028C00_LAST_PIXEL(1) |
1931 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1932 r600_write_value(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1933 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1935 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1936 r600_write_value(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1937 r600_write_value(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1941 static void cayman_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
1944 * There are two locations (-4, 4), (4, -4). */
1945 static uint32_t sample_locs_2x
[] = {
1946 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1947 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1948 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1949 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1951 static unsigned max_dist_2x
= 4;
1953 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1954 static uint32_t sample_locs_4x
[] = {
1955 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1956 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1957 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1958 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1960 static unsigned max_dist_4x
= 6;
1962 static uint32_t sample_locs_8x
[] = {
1963 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1964 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1965 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1966 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1967 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1968 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1969 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1970 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1972 static unsigned max_dist_8x
= 8;
1974 static uint32_t sample_locs_16x
[] = {
1975 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1976 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1977 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1978 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1979 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1980 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1981 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1982 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1983 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1984 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1985 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1986 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1987 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1988 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1989 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1990 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1992 static unsigned max_dist_16x
= 8;
1994 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1995 unsigned max_dist
= 0;
1997 switch (nr_samples
) {
2002 r600_write_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_2x
[0]);
2003 r600_write_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_2x
[1]);
2004 r600_write_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_2x
[2]);
2005 r600_write_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_2x
[3]);
2006 max_dist
= max_dist_2x
;
2009 r600_write_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_4x
[0]);
2010 r600_write_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_4x
[1]);
2011 r600_write_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_4x
[2]);
2012 r600_write_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_4x
[3]);
2013 max_dist
= max_dist_4x
;
2016 r600_write_context_reg_seq(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 14);
2017 r600_write_value(cs
, sample_locs_8x
[0]);
2018 r600_write_value(cs
, sample_locs_8x
[4]);
2019 r600_write_value(cs
, 0);
2020 r600_write_value(cs
, 0);
2021 r600_write_value(cs
, sample_locs_8x
[1]);
2022 r600_write_value(cs
, sample_locs_8x
[5]);
2023 r600_write_value(cs
, 0);
2024 r600_write_value(cs
, 0);
2025 r600_write_value(cs
, sample_locs_8x
[2]);
2026 r600_write_value(cs
, sample_locs_8x
[6]);
2027 r600_write_value(cs
, 0);
2028 r600_write_value(cs
, 0);
2029 r600_write_value(cs
, sample_locs_8x
[3]);
2030 r600_write_value(cs
, sample_locs_8x
[7]);
2031 max_dist
= max_dist_8x
;
2034 r600_write_context_reg_seq(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 16);
2035 r600_write_value(cs
, sample_locs_16x
[0]);
2036 r600_write_value(cs
, sample_locs_16x
[4]);
2037 r600_write_value(cs
, sample_locs_16x
[8]);
2038 r600_write_value(cs
, sample_locs_16x
[12]);
2039 r600_write_value(cs
, sample_locs_16x
[1]);
2040 r600_write_value(cs
, sample_locs_16x
[5]);
2041 r600_write_value(cs
, sample_locs_16x
[9]);
2042 r600_write_value(cs
, sample_locs_16x
[13]);
2043 r600_write_value(cs
, sample_locs_16x
[2]);
2044 r600_write_value(cs
, sample_locs_16x
[6]);
2045 r600_write_value(cs
, sample_locs_16x
[10]);
2046 r600_write_value(cs
, sample_locs_16x
[14]);
2047 r600_write_value(cs
, sample_locs_16x
[3]);
2048 r600_write_value(cs
, sample_locs_16x
[7]);
2049 r600_write_value(cs
, sample_locs_16x
[11]);
2050 r600_write_value(cs
, sample_locs_16x
[15]);
2051 max_dist
= max_dist_16x
;
2055 if (nr_samples
> 1) {
2056 unsigned log_samples
= util_logbase2(nr_samples
);
2058 r600_write_context_reg_seq(cs
, CM_R_028BDC_PA_SC_LINE_CNTL
, 2);
2059 r600_write_value(cs
, S_028C00_LAST_PIXEL(1) |
2060 S_028C00_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2061 r600_write_value(cs
, S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
2062 S_028BE0_MAX_SAMPLE_DIST(max_dist
) |
2063 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2065 r600_write_context_reg(cs
, CM_R_028804_DB_EQAA
,
2066 S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
2067 S_028804_PS_ITER_SAMPLES(log_samples
) |
2068 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
2069 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
) |
2070 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2071 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2073 r600_write_context_reg_seq(cs
, CM_R_028BDC_PA_SC_LINE_CNTL
, 2);
2074 r600_write_value(cs
, S_028C00_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2075 r600_write_value(cs
, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2077 r600_write_context_reg(cs
, CM_R_028804_DB_EQAA
,
2078 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2079 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2083 static void evergreen_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2085 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2086 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
2087 unsigned nr_cbufs
= state
->nr_cbufs
;
2090 /* XXX support more colorbuffers once we need them */
2091 assert(nr_cbufs
<= 8);
2096 for (i
= 0; i
< nr_cbufs
; i
++) {
2097 struct r600_surface
*cb
= (struct r600_surface
*)state
->cbufs
[i
];
2098 unsigned reloc
= r600_context_bo_reloc(rctx
,
2100 (struct r600_resource
*)cb
->base
.texture
,
2101 RADEON_USAGE_READWRITE
);
2103 r600_write_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 11);
2104 r600_write_value(cs
, cb
->cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
2105 r600_write_value(cs
, cb
->cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
2106 r600_write_value(cs
, cb
->cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
2107 r600_write_value(cs
, cb
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
2108 r600_write_value(cs
, cb
->cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
2109 r600_write_value(cs
, cb
->cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
2110 r600_write_value(cs
, cb
->cb_color_dim
); /* R_028C78_CB_COLOR0_DIM */
2111 r600_write_value(cs
, cb
->cb_color_cmask
); /* R_028C7C_CB_COLOR0_CMASK */
2112 r600_write_value(cs
, cb
->cb_color_cmask_slice
); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2113 r600_write_value(cs
, cb
->cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
2114 r600_write_value(cs
, cb
->cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2116 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
2117 r600_write_value(cs
, reloc
);
2119 if (!rctx
->keep_tiling_flags
) {
2120 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
2121 r600_write_value(cs
, reloc
);
2124 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
2125 r600_write_value(cs
, reloc
);
2127 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
2128 r600_write_value(cs
, reloc
);
2130 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
2131 r600_write_value(cs
, reloc
);
2133 /* set CB_COLOR1_INFO for possible dual-src blending */
2134 if (i
== 1 && !((struct r600_texture
*)state
->cbufs
[0]->texture
)->is_rat
) {
2135 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C,
2136 ((struct r600_surface
*)state
->cbufs
[0])->cb_color_info
);
2138 if (!rctx
->keep_tiling_flags
) {
2139 unsigned reloc
= r600_context_bo_reloc(rctx
,
2141 (struct r600_resource
*)state
->cbufs
[0]->texture
,
2142 RADEON_USAGE_READWRITE
);
2144 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
2145 r600_write_value(cs
, reloc
);
2149 if (rctx
->keep_tiling_flags
) {
2150 for (; i
< 8 ; i
++) {
2151 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
2153 for (; i
< 12; i
++) {
2154 r600_write_context_reg(cs
, R_028E50_CB_COLOR8_INFO
+ (i
- 8) * 0x1C, 0);
2160 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
2161 unsigned reloc
= r600_context_bo_reloc(rctx
,
2163 (struct r600_resource
*)state
->zsbuf
->texture
,
2164 RADEON_USAGE_READWRITE
);
2166 r600_write_context_reg(cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
2167 zb
->pa_su_poly_offset_db_fmt_cntl
);
2168 r600_write_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
2170 r600_write_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 8);
2171 r600_write_value(cs
, zb
->db_depth_info
); /* R_028040_DB_Z_INFO */
2172 r600_write_value(cs
, zb
->db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
2173 r600_write_value(cs
, zb
->db_depth_base
); /* R_028048_DB_Z_READ_BASE */
2174 r600_write_value(cs
, zb
->db_stencil_base
); /* R_02804C_DB_STENCIL_READ_BASE */
2175 r600_write_value(cs
, zb
->db_depth_base
); /* R_028050_DB_Z_WRITE_BASE */
2176 r600_write_value(cs
, zb
->db_stencil_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
2177 r600_write_value(cs
, zb
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
2178 r600_write_value(cs
, zb
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
2180 if (!rctx
->keep_tiling_flags
) {
2181 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028040_DB_Z_INFO */
2182 r600_write_value(cs
, reloc
);
2185 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028048_DB_Z_READ_BASE */
2186 r600_write_value(cs
, reloc
);
2188 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
2189 r600_write_value(cs
, reloc
);
2191 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
2192 r600_write_value(cs
, reloc
);
2194 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
2195 r600_write_value(cs
, reloc
);
2196 } else if (rctx
->screen
->info
.drm_minor
>= 18) {
2197 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
2198 * Older kernels are out of luck. */
2199 r600_write_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
2200 r600_write_value(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
2201 r600_write_value(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
2204 /* Framebuffer dimensions. */
2205 evergreen_get_scissor_rect(rctx
, 0, 0, state
->width
, state
->height
, &tl
, &br
);
2207 r600_write_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
2208 r600_write_value(cs
, tl
); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
2209 r600_write_value(cs
, br
); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
2211 if (rctx
->chip_class
== EVERGREEN
) {
2212 evergreen_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
2214 cayman_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
2218 static void evergreen_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
2220 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2221 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
2222 float offset_units
= state
->offset_units
;
2223 float offset_scale
= state
->offset_scale
;
2225 switch (state
->zs_format
) {
2226 case PIPE_FORMAT_Z24X8_UNORM
:
2227 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2228 case PIPE_FORMAT_X8Z24_UNORM
:
2229 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2230 offset_units
*= 2.0f
;
2232 case PIPE_FORMAT_Z16_UNORM
:
2233 offset_units
*= 4.0f
;
2238 r600_write_context_reg_seq(cs
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
2239 r600_write_value(cs
, fui(offset_scale
));
2240 r600_write_value(cs
, fui(offset_units
));
2241 r600_write_value(cs
, fui(offset_scale
));
2242 r600_write_value(cs
, fui(offset_units
));
2245 static void evergreen_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2247 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2248 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
2249 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
2250 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
2252 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
2253 r600_write_value(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
2254 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
2255 * will assure that the alpha-test will work even if there is
2256 * no colorbuffer bound. */
2257 r600_write_value(cs
, 0xf | (a
->dual_src_blend
? ps_colormask
: 0) | fb_colormask
); /* R_02823C_CB_SHADER_MASK */
2260 static void evergreen_emit_db_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2262 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2263 struct r600_db_state
*a
= (struct r600_db_state
*)atom
;
2265 if (a
->rsurf
&& a
->rsurf
->htile_enabled
) {
2266 struct r600_texture
*rtex
= (struct r600_texture
*)a
->rsurf
->base
.texture
;
2269 r600_write_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear
));
2270 r600_write_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, a
->rsurf
->db_htile_surface
);
2271 r600_write_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, a
->rsurf
->db_preload_control
);
2272 r600_write_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, a
->rsurf
->db_htile_data_base
);
2273 reloc_idx
= r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, rtex
->htile
, RADEON_USAGE_READWRITE
);
2274 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
2275 cs
->buf
[cs
->cdw
++] = reloc_idx
;
2277 r600_write_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, 0);
2278 r600_write_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0);
2282 static void evergreen_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2284 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2285 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
2286 unsigned db_render_control
= 0;
2287 unsigned db_count_control
= 0;
2288 unsigned db_render_override
=
2289 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
2290 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
2292 if (a
->occlusion_query_enabled
) {
2293 db_count_control
|= S_028004_PERFECT_ZPASS_COUNTS(1);
2294 if (rctx
->chip_class
== CAYMAN
) {
2295 db_count_control
|= S_028004_SAMPLE_RATE(a
->log_samples
);
2297 db_render_override
|= S_02800C_NOOP_CULL_DISABLE(1);
2299 /* FIXME we should be able to use hyperz even if we are not writing to
2300 * zbuffer but somehow this trigger GPU lockup. See :
2302 * https://bugs.freedesktop.org/show_bug.cgi?id=60848
2304 * Disable hyperz for now if not writing to zbuffer.
2306 if (rctx
->db_state
.rsurf
&& rctx
->db_state
.rsurf
->htile_enabled
&& rctx
->zwritemask
) {
2307 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
2308 db_render_override
|= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF
);
2309 /* This is to fix a lockup when hyperz and alpha test are enabled at
2310 * the same time somehow GPU get confuse on which order to pick for
2313 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
2314 db_render_override
|= S_02800C_FORCE_SHADER_Z_ORDER(1);
2317 db_render_override
|= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
);
2319 if (a
->flush_depthstencil_through_cb
) {
2320 assert(a
->copy_depth
|| a
->copy_stencil
);
2322 db_render_control
|= S_028000_DEPTH_COPY_ENABLE(a
->copy_depth
) |
2323 S_028000_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
2324 S_028000_COPY_CENTROID(1) |
2325 S_028000_COPY_SAMPLE(a
->copy_sample
);
2326 } else if (a
->flush_depthstencil_in_place
) {
2327 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(1) |
2328 S_028000_STENCIL_COMPRESS_DISABLE(1);
2329 db_render_override
|= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2331 if (a
->htile_clear
) {
2332 /* FIXME we might want to disable cliprect here */
2333 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(1);
2336 r600_write_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
2337 r600_write_value(cs
, db_render_control
); /* R_028000_DB_RENDER_CONTROL */
2338 r600_write_value(cs
, db_count_control
); /* R_028004_DB_COUNT_CONTROL */
2339 r600_write_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
2340 r600_write_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
2343 static void evergreen_emit_vertex_buffers(struct r600_context
*rctx
,
2344 struct r600_vertexbuf_state
*state
,
2345 unsigned resource_offset
,
2348 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2349 uint32_t dirty_mask
= state
->dirty_mask
;
2351 while (dirty_mask
) {
2352 struct pipe_vertex_buffer
*vb
;
2353 struct r600_resource
*rbuffer
;
2355 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
2357 vb
= &state
->vb
[buffer_index
];
2358 rbuffer
= (struct r600_resource
*)vb
->buffer
;
2361 va
= r600_resource_va(&rctx
->screen
->screen
, &rbuffer
->b
.b
);
2362 va
+= vb
->buffer_offset
;
2364 /* fetch resources start at index 992 */
2365 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
2366 r600_write_value(cs
, (resource_offset
+ buffer_index
) * 8);
2367 r600_write_value(cs
, va
); /* RESOURCEi_WORD0 */
2368 r600_write_value(cs
, rbuffer
->buf
->size
- vb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
2369 r600_write_value(cs
, /* RESOURCEi_WORD2 */
2370 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2371 S_030008_STRIDE(vb
->stride
) |
2372 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
2373 r600_write_value(cs
, /* RESOURCEi_WORD3 */
2374 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
2375 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
2376 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
2377 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
2378 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
2379 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
2380 r600_write_value(cs
, 0); /* RESOURCEi_WORD6 */
2381 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
2383 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2384 r600_write_value(cs
, r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, rbuffer
, RADEON_USAGE_READ
));
2386 state
->dirty_mask
= 0;
2389 static void evergreen_fs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
2391 evergreen_emit_vertex_buffers(rctx
, &rctx
->vertex_buffer_state
, 992, 0);
2394 static void evergreen_cs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
2396 evergreen_emit_vertex_buffers(rctx
, &rctx
->cs_vertex_buffer_state
, 816,
2397 RADEON_CP_PACKET3_COMPUTE_MODE
);
2400 static void evergreen_emit_constant_buffers(struct r600_context
*rctx
,
2401 struct r600_constbuf_state
*state
,
2402 unsigned buffer_id_base
,
2403 unsigned reg_alu_constbuf_size
,
2404 unsigned reg_alu_const_cache
)
2406 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2407 uint32_t dirty_mask
= state
->dirty_mask
;
2409 while (dirty_mask
) {
2410 struct pipe_constant_buffer
*cb
;
2411 struct r600_resource
*rbuffer
;
2413 unsigned buffer_index
= ffs(dirty_mask
) - 1;
2415 cb
= &state
->cb
[buffer_index
];
2416 rbuffer
= (struct r600_resource
*)cb
->buffer
;
2419 va
= r600_resource_va(&rctx
->screen
->screen
, &rbuffer
->b
.b
);
2420 va
+= cb
->buffer_offset
;
2422 r600_write_context_reg(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
2423 ALIGN_DIVUP(cb
->buffer_size
>> 4, 16));
2424 r600_write_context_reg(cs
, reg_alu_const_cache
+ buffer_index
* 4, va
>> 8);
2426 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2427 r600_write_value(cs
, r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, rbuffer
, RADEON_USAGE_READ
));
2429 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0));
2430 r600_write_value(cs
, (buffer_id_base
+ buffer_index
) * 8);
2431 r600_write_value(cs
, va
); /* RESOURCEi_WORD0 */
2432 r600_write_value(cs
, rbuffer
->buf
->size
- cb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
2433 r600_write_value(cs
, /* RESOURCEi_WORD2 */
2434 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2435 S_030008_STRIDE(16) |
2436 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
2437 r600_write_value(cs
, /* RESOURCEi_WORD3 */
2438 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
2439 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
2440 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
2441 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
2442 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
2443 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
2444 r600_write_value(cs
, 0); /* RESOURCEi_WORD6 */
2445 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
2447 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2448 r600_write_value(cs
, r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, rbuffer
, RADEON_USAGE_READ
));
2450 dirty_mask
&= ~(1 << buffer_index
);
2452 state
->dirty_mask
= 0;
2455 static void evergreen_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2457 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
], 176,
2458 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
2459 R_028980_ALU_CONST_CACHE_VS_0
);
2462 static void evergreen_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2464 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
], 336,
2465 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
2466 R_0289C0_ALU_CONST_CACHE_GS_0
);
2469 static void evergreen_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2471 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
], 0,
2472 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
2473 R_028940_ALU_CONST_CACHE_PS_0
);
2476 static void evergreen_emit_sampler_views(struct r600_context
*rctx
,
2477 struct r600_samplerview_state
*state
,
2478 unsigned resource_id_base
)
2480 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2481 uint32_t dirty_mask
= state
->dirty_mask
;
2483 while (dirty_mask
) {
2484 struct r600_pipe_sampler_view
*rview
;
2485 unsigned resource_index
= u_bit_scan(&dirty_mask
);
2488 rview
= state
->views
[resource_index
];
2491 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0));
2492 r600_write_value(cs
, (resource_id_base
+ resource_index
) * 8);
2493 r600_write_array(cs
, 8, rview
->tex_resource_words
);
2495 reloc
= r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, rview
->tex_resource
,
2497 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2498 r600_write_value(cs
, reloc
);
2500 if (!rview
->skip_mip_address_reloc
) {
2501 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2502 r600_write_value(cs
, reloc
);
2505 state
->dirty_mask
= 0;
2508 static void evergreen_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2510 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
, 176 + R600_MAX_CONST_BUFFERS
);
2513 static void evergreen_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2515 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
, 336 + R600_MAX_CONST_BUFFERS
);
2518 static void evergreen_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2520 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
, R600_MAX_CONST_BUFFERS
);
2523 static void evergreen_emit_sampler_states(struct r600_context
*rctx
,
2524 struct r600_textures_info
*texinfo
,
2525 unsigned resource_id_base
,
2526 unsigned border_index_reg
)
2528 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2529 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
2531 while (dirty_mask
) {
2532 struct r600_pipe_sampler_state
*rstate
;
2533 unsigned i
= u_bit_scan(&dirty_mask
);
2535 rstate
= texinfo
->states
.states
[i
];
2538 r600_write_value(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0));
2539 r600_write_value(cs
, (resource_id_base
+ i
) * 3);
2540 r600_write_array(cs
, 3, rstate
->tex_sampler_words
);
2542 if (rstate
->border_color_use
) {
2543 r600_write_config_reg_seq(cs
, border_index_reg
, 5);
2544 r600_write_value(cs
, i
);
2545 r600_write_array(cs
, 4, rstate
->border_color
.ui
);
2548 texinfo
->states
.dirty_mask
= 0;
2551 static void evergreen_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2553 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
);
2556 static void evergreen_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2558 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX
);
2561 static void evergreen_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2563 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
);
2566 static void evergreen_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2568 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2569 uint8_t mask
= s
->sample_mask
;
2571 r600_write_context_reg(rctx
->rings
.gfx
.cs
, R_028C3C_PA_SC_AA_MASK
,
2572 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2575 static void cayman_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2577 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2578 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2579 uint16_t mask
= s
->sample_mask
;
2581 r600_write_context_reg_seq(cs
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2582 r600_write_value(cs
, mask
| (mask
<< 16)); /* X0Y0_X1Y0 */
2583 r600_write_value(cs
, mask
| (mask
<< 16)); /* X0Y1_X1Y1 */
2586 static void evergreen_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2588 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2589 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
2590 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
->cso
;
2592 r600_write_context_reg(cs
, R_0288A4_SQ_PGM_START_FS
,
2593 (r600_resource_va(rctx
->context
.screen
, &shader
->buffer
->b
.b
) + shader
->offset
) >> 8);
2594 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2595 r600_write_value(cs
, r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, shader
->buffer
, RADEON_USAGE_READ
));
2598 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
2599 enum chip_class ctx_chip_class
,
2600 enum radeon_family ctx_family
,
2603 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2604 r600_store_value(cb
, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2605 /* always set the temp clauses */
2606 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2608 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2609 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2610 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2612 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2614 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
2616 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2618 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2621 static void cayman_init_atom_start_cs(struct r600_context
*rctx
)
2623 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2625 r600_init_command_buffer(cb
, 256);
2627 /* This must be first. */
2628 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2629 r600_store_value(cb
, 0x80000000);
2630 r600_store_value(cb
, 0x80000000);
2632 /* We're setting config registers here. */
2633 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2634 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2636 cayman_init_common_regs(cb
, rctx
->chip_class
,
2637 rctx
->family
, rctx
->screen
->info
.drm_minor
);
2639 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2640 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2642 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2643 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2644 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2645 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2646 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2647 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2648 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2650 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2651 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2652 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2653 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2654 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2656 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2657 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2658 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2659 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2660 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2661 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2662 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2663 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2664 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2665 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2666 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2667 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2668 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2669 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2671 r600_store_context_reg_seq(cb
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
2672 r600_store_value(cb
, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2673 r600_store_value(cb
, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2675 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2676 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
2677 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2679 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2681 r600_store_context_reg(cb
, CM_R_028AA8_IA_MULTI_VGT_PARAM
, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2683 r600_store_context_reg_seq(cb
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
2684 r600_store_value(cb
, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2685 r600_store_value(cb
, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2687 r600_store_context_reg_seq(cb
, CM_R_0288E8_SQ_LDS_ALLOC
, 2);
2688 r600_store_value(cb
, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2689 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2691 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2693 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2694 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2695 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2697 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2699 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2701 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2703 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2704 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2705 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2706 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2708 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2709 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2711 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
2712 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2713 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2715 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2716 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
2717 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2719 r600_store_context_reg_seq(cb
, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2720 r600_store_value(cb
, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2721 r600_store_value(cb
, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2722 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2723 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2725 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2726 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2727 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2729 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2730 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2731 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2733 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2734 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2735 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2737 /* to avoid GPU doing any preloading of constant from random address */
2738 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2739 r600_store_value(cb
, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2740 r600_store_value(cb
, 0);
2741 r600_store_value(cb
, 0);
2742 r600_store_value(cb
, 0);
2743 r600_store_value(cb
, 0);
2744 r600_store_value(cb
, 0);
2745 r600_store_value(cb
, 0);
2746 r600_store_value(cb
, 0);
2747 r600_store_value(cb
, 0);
2748 r600_store_value(cb
, 0);
2749 r600_store_value(cb
, 0);
2750 r600_store_value(cb
, 0);
2751 r600_store_value(cb
, 0);
2752 r600_store_value(cb
, 0);
2753 r600_store_value(cb
, 0);
2754 r600_store_value(cb
, 0);
2756 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2757 r600_store_value(cb
, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2758 r600_store_value(cb
, 0);
2759 r600_store_value(cb
, 0);
2760 r600_store_value(cb
, 0);
2761 r600_store_value(cb
, 0);
2762 r600_store_value(cb
, 0);
2763 r600_store_value(cb
, 0);
2764 r600_store_value(cb
, 0);
2765 r600_store_value(cb
, 0);
2766 r600_store_value(cb
, 0);
2767 r600_store_value(cb
, 0);
2768 r600_store_value(cb
, 0);
2769 r600_store_value(cb
, 0);
2770 r600_store_value(cb
, 0);
2771 r600_store_value(cb
, 0);
2772 r600_store_value(cb
, 0);
2774 if (rctx
->screen
->has_streamout
) {
2775 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2778 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
2779 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
2780 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2781 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
2782 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2783 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2784 r600_store_context_reg(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 0);
2786 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2787 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2790 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
2791 enum chip_class ctx_chip_class
,
2792 enum radeon_family ctx_family
,
2831 switch (ctx_family
) {
2839 tmp
|= S_008C00_VC_ENABLE(1);
2842 tmp
|= S_008C00_EXPORT_SRC_C(1);
2843 tmp
|= S_008C00_CS_PRIO(cs_prio
);
2844 tmp
|= S_008C00_LS_PRIO(ls_prio
);
2845 tmp
|= S_008C00_HS_PRIO(hs_prio
);
2846 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2847 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2848 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2849 tmp
|= S_008C00_ES_PRIO(es_prio
);
2851 /* enable dynamic GPR resource management */
2852 if (ctx_drm_minor
>= 7) {
2853 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2854 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2855 /* always set temp clauses */
2856 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2857 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2858 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2859 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2860 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2861 r600_store_context_reg(cb
, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
,
2862 S_028838_PS_GPRS(0x1e) |
2863 S_028838_VS_GPRS(0x1e) |
2864 S_028838_GS_GPRS(0x1e) |
2865 S_028838_ES_GPRS(0x1e) |
2866 S_028838_HS_GPRS(0x1e) |
2867 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2869 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 4);
2870 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2872 tmp
= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
2873 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
2874 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
2875 r600_store_value(cb
, tmp
); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2877 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2878 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2879 r600_store_value(cb
, tmp
); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2881 tmp
= S_008C0C_NUM_HS_GPRS(num_hs_gprs
);
2882 tmp
|= S_008C0C_NUM_HS_GPRS(num_ls_gprs
);
2883 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2886 r600_store_config_reg(cb
, R_008E2C_SQ_LDS_RESOURCE_MGMT
,
2887 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2889 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
2891 /* The cs checker requires this register to be set. */
2892 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2894 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2899 void evergreen_init_atom_start_cs(struct r600_context
*rctx
)
2901 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2909 int num_ps_stack_entries
;
2910 int num_vs_stack_entries
;
2911 int num_gs_stack_entries
;
2912 int num_es_stack_entries
;
2913 int num_hs_stack_entries
;
2914 int num_ls_stack_entries
;
2915 enum radeon_family family
;
2918 if (rctx
->chip_class
== CAYMAN
) {
2919 cayman_init_atom_start_cs(rctx
);
2923 r600_init_command_buffer(cb
, 256);
2925 /* This must be first. */
2926 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2927 r600_store_value(cb
, 0x80000000);
2928 r600_store_value(cb
, 0x80000000);
2930 /* We're setting config registers here. */
2931 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2932 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2934 evergreen_init_common_regs(cb
, rctx
->chip_class
,
2935 rctx
->family
, rctx
->screen
->info
.drm_minor
);
2937 family
= rctx
->family
;
2941 num_ps_threads
= 96;
2942 num_vs_threads
= 16;
2943 num_gs_threads
= 16;
2944 num_es_threads
= 16;
2945 num_hs_threads
= 16;
2946 num_ls_threads
= 16;
2947 num_ps_stack_entries
= 42;
2948 num_vs_stack_entries
= 42;
2949 num_gs_stack_entries
= 42;
2950 num_es_stack_entries
= 42;
2951 num_hs_stack_entries
= 42;
2952 num_ls_stack_entries
= 42;
2955 num_ps_threads
= 128;
2956 num_vs_threads
= 20;
2957 num_gs_threads
= 20;
2958 num_es_threads
= 20;
2959 num_hs_threads
= 20;
2960 num_ls_threads
= 20;
2961 num_ps_stack_entries
= 42;
2962 num_vs_stack_entries
= 42;
2963 num_gs_stack_entries
= 42;
2964 num_es_stack_entries
= 42;
2965 num_hs_stack_entries
= 42;
2966 num_ls_stack_entries
= 42;
2969 num_ps_threads
= 128;
2970 num_vs_threads
= 20;
2971 num_gs_threads
= 20;
2972 num_es_threads
= 20;
2973 num_hs_threads
= 20;
2974 num_ls_threads
= 20;
2975 num_ps_stack_entries
= 85;
2976 num_vs_stack_entries
= 85;
2977 num_gs_stack_entries
= 85;
2978 num_es_stack_entries
= 85;
2979 num_hs_stack_entries
= 85;
2980 num_ls_stack_entries
= 85;
2984 num_ps_threads
= 128;
2985 num_vs_threads
= 20;
2986 num_gs_threads
= 20;
2987 num_es_threads
= 20;
2988 num_hs_threads
= 20;
2989 num_ls_threads
= 20;
2990 num_ps_stack_entries
= 85;
2991 num_vs_stack_entries
= 85;
2992 num_gs_stack_entries
= 85;
2993 num_es_stack_entries
= 85;
2994 num_hs_stack_entries
= 85;
2995 num_ls_stack_entries
= 85;
2998 num_ps_threads
= 96;
2999 num_vs_threads
= 16;
3000 num_gs_threads
= 16;
3001 num_es_threads
= 16;
3002 num_hs_threads
= 16;
3003 num_ls_threads
= 16;
3004 num_ps_stack_entries
= 42;
3005 num_vs_stack_entries
= 42;
3006 num_gs_stack_entries
= 42;
3007 num_es_stack_entries
= 42;
3008 num_hs_stack_entries
= 42;
3009 num_ls_stack_entries
= 42;
3012 num_ps_threads
= 96;
3013 num_vs_threads
= 25;
3014 num_gs_threads
= 25;
3015 num_es_threads
= 25;
3016 num_hs_threads
= 25;
3017 num_ls_threads
= 25;
3018 num_ps_stack_entries
= 42;
3019 num_vs_stack_entries
= 42;
3020 num_gs_stack_entries
= 42;
3021 num_es_stack_entries
= 42;
3022 num_hs_stack_entries
= 42;
3023 num_ls_stack_entries
= 42;
3026 num_ps_threads
= 96;
3027 num_vs_threads
= 25;
3028 num_gs_threads
= 25;
3029 num_es_threads
= 25;
3030 num_hs_threads
= 25;
3031 num_ls_threads
= 25;
3032 num_ps_stack_entries
= 85;
3033 num_vs_stack_entries
= 85;
3034 num_gs_stack_entries
= 85;
3035 num_es_stack_entries
= 85;
3036 num_hs_stack_entries
= 85;
3037 num_ls_stack_entries
= 85;
3040 num_ps_threads
= 128;
3041 num_vs_threads
= 20;
3042 num_gs_threads
= 20;
3043 num_es_threads
= 20;
3044 num_hs_threads
= 20;
3045 num_ls_threads
= 20;
3046 num_ps_stack_entries
= 85;
3047 num_vs_stack_entries
= 85;
3048 num_gs_stack_entries
= 85;
3049 num_es_stack_entries
= 85;
3050 num_hs_stack_entries
= 85;
3051 num_ls_stack_entries
= 85;
3054 num_ps_threads
= 128;
3055 num_vs_threads
= 20;
3056 num_gs_threads
= 20;
3057 num_es_threads
= 20;
3058 num_hs_threads
= 20;
3059 num_ls_threads
= 20;
3060 num_ps_stack_entries
= 42;
3061 num_vs_stack_entries
= 42;
3062 num_gs_stack_entries
= 42;
3063 num_es_stack_entries
= 42;
3064 num_hs_stack_entries
= 42;
3065 num_ls_stack_entries
= 42;
3068 num_ps_threads
= 128;
3069 num_vs_threads
= 10;
3070 num_gs_threads
= 10;
3071 num_es_threads
= 10;
3072 num_hs_threads
= 10;
3073 num_ls_threads
= 10;
3074 num_ps_stack_entries
= 42;
3075 num_vs_stack_entries
= 42;
3076 num_gs_stack_entries
= 42;
3077 num_es_stack_entries
= 42;
3078 num_hs_stack_entries
= 42;
3079 num_ls_stack_entries
= 42;
3083 tmp
= S_008C18_NUM_PS_THREADS(num_ps_threads
);
3084 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
3085 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
3086 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
3088 r600_store_config_reg_seq(cb
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, 5);
3089 r600_store_value(cb
, tmp
); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3091 tmp
= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
3092 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
3093 r600_store_value(cb
, tmp
); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3095 tmp
= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
3096 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
3097 r600_store_value(cb
, tmp
); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3099 tmp
= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
3100 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
3101 r600_store_value(cb
, tmp
); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3103 tmp
= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
3104 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
3105 r600_store_value(cb
, tmp
); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3107 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
3108 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
3110 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
3111 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3112 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3113 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3114 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3115 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3116 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3118 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
3119 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3120 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3121 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3122 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3124 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
3125 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3126 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
3127 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3128 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3129 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3130 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3131 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3132 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
3133 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3134 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3135 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3136 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3137 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
3139 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
3140 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
3141 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
3143 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
3145 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
3147 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
3148 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3149 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
3151 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
3153 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
3155 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
3156 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
3157 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
3159 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
3160 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
3161 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
3163 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
3164 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
3165 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
3167 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
3168 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3169 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3170 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3172 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
3173 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
3174 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
3175 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
3176 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
3178 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
3179 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3180 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3182 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
3183 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3184 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3186 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3187 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3188 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
3190 /* to avoid GPU doing any preloading of constant from random address */
3191 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
3192 r600_store_value(cb
, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
3193 r600_store_value(cb
, 0);
3194 r600_store_value(cb
, 0);
3195 r600_store_value(cb
, 0);
3196 r600_store_value(cb
, 0);
3197 r600_store_value(cb
, 0);
3198 r600_store_value(cb
, 0);
3199 r600_store_value(cb
, 0);
3200 r600_store_value(cb
, 0);
3201 r600_store_value(cb
, 0);
3202 r600_store_value(cb
, 0);
3203 r600_store_value(cb
, 0);
3204 r600_store_value(cb
, 0);
3205 r600_store_value(cb
, 0);
3206 r600_store_value(cb
, 0);
3207 r600_store_value(cb
, 0);
3209 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
3210 r600_store_value(cb
, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
3211 r600_store_value(cb
, 0);
3212 r600_store_value(cb
, 0);
3213 r600_store_value(cb
, 0);
3214 r600_store_value(cb
, 0);
3215 r600_store_value(cb
, 0);
3216 r600_store_value(cb
, 0);
3217 r600_store_value(cb
, 0);
3218 r600_store_value(cb
, 0);
3219 r600_store_value(cb
, 0);
3220 r600_store_value(cb
, 0);
3221 r600_store_value(cb
, 0);
3222 r600_store_value(cb
, 0);
3223 r600_store_value(cb
, 0);
3224 r600_store_value(cb
, 0);
3225 r600_store_value(cb
, 0);
3227 r600_store_context_reg_seq(cb
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
3228 r600_store_value(cb
, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
3229 r600_store_value(cb
, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
3231 if (rctx
->screen
->has_streamout
) {
3232 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
3235 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
3236 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
3237 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
3238 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
3239 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3240 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3241 r600_store_context_reg(cb
, R_0288EC_SQ_LDS_ALLOC_PS
, 0);
3242 r600_store_context_reg(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 0);
3244 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
3245 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
3248 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3250 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3251 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3252 struct r600_shader
*rshader
= &shader
->shader
;
3253 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
= 0;
3254 int pos_index
= -1, face_index
= -1;
3256 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
3257 unsigned spi_baryc_cntl
, sid
, tmp
, num
= 0;
3258 unsigned z_export
= 0, stencil_export
= 0;
3259 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
3260 uint32_t spi_ps_input_cntl
[32];
3263 r600_init_command_buffer(cb
, 64);
3268 for (i
= 0; i
< rshader
->ninput
; i
++) {
3269 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3270 POSITION goes via GPRs from the SC so isn't counted */
3271 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
3273 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
3277 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
3279 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
3280 have_perspective
= TRUE
;
3281 if (rshader
->input
[i
].centroid
)
3282 have_centroid
= TRUE
;
3285 sid
= rshader
->input
[i
].spi_sid
;
3288 tmp
= S_028644_SEMANTIC(sid
);
3290 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
3291 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3292 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
3293 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
)) {
3294 tmp
|= S_028644_FLAT_SHADE(1);
3297 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
3298 (sprite_coord_enable
& (1 << rshader
->input
[i
].sid
))) {
3299 tmp
|= S_028644_PT_SPRITE_TEX(1);
3302 spi_ps_input_cntl
[num
++] = tmp
;
3306 r600_store_context_reg_seq(cb
, R_028644_SPI_PS_INPUT_CNTL_0
, num
);
3307 r600_store_array(cb
, num
, spi_ps_input_cntl
);
3309 for (i
= 0; i
< rshader
->noutput
; i
++) {
3310 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
3312 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
3315 if (rshader
->uses_kill
)
3316 db_shader_control
|= S_02880C_KILL_ENABLE(1);
3318 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
3319 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export
);
3322 for (i
= 0; i
< rshader
->noutput
; i
++) {
3323 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
3324 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
3328 num_cout
= rshader
->nr_ps_color_exports
;
3330 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
3332 /* always at least export 1 component per pixel */
3335 shader
->nr_ps_color_outputs
= num_cout
;
3338 have_perspective
= TRUE
;
3341 if (!have_perspective
&& !have_linear
)
3342 have_perspective
= TRUE
;
3344 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
3345 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
3346 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
3348 if (pos_index
!= -1) {
3349 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
3350 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
3351 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
3352 spi_input_z
|= S_0286D8_PROVIDE_Z_TO_SPI(1);
3355 spi_ps_in_control_1
= 0;
3356 if (face_index
!= -1) {
3357 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
3358 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
3362 if (have_perspective
)
3363 spi_baryc_cntl
|= S_0286E0_PERSP_CENTER_ENA(1) |
3364 S_0286E0_PERSP_CENTROID_ENA(have_centroid
);
3366 spi_baryc_cntl
|= S_0286E0_LINEAR_CENTER_ENA(1) |
3367 S_0286E0_LINEAR_CENTROID_ENA(have_centroid
);
3369 r600_store_context_reg_seq(cb
, R_0286CC_SPI_PS_IN_CONTROL_0
, 2);
3370 r600_store_value(cb
, spi_ps_in_control_0
); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3371 r600_store_value(cb
, spi_ps_in_control_1
); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3373 r600_store_context_reg(cb
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
3374 r600_store_context_reg(cb
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
3375 r600_store_context_reg(cb
, R_02884C_SQ_PGM_EXPORTS_PS
, exports_ps
);
3377 r600_store_context_reg_seq(cb
, R_028840_SQ_PGM_START_PS
, 2);
3378 r600_store_value(cb
, r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8);
3379 r600_store_value(cb
, /* R_028844_SQ_PGM_RESOURCES_PS */
3380 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
3381 S_028844_PRIME_CACHE_ON_DRAW(1) |
3382 S_028844_STACK_SIZE(rshader
->bc
.nstack
));
3383 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3385 shader
->db_shader_control
= db_shader_control
;
3386 shader
->ps_depth_export
= z_export
| stencil_export
;
3388 shader
->sprite_coord_enable
= sprite_coord_enable
;
3389 if (rctx
->rasterizer
)
3390 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
3393 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3395 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3396 struct r600_shader
*rshader
= &shader
->shader
;
3397 unsigned spi_vs_out_id
[10] = {};
3398 unsigned i
, tmp
, nparams
= 0;
3400 for (i
= 0; i
< rshader
->noutput
; i
++) {
3401 if (rshader
->output
[i
].spi_sid
) {
3402 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
3403 spi_vs_out_id
[nparams
/ 4] |= tmp
;
3408 r600_init_command_buffer(cb
, 32);
3410 r600_store_context_reg_seq(cb
, R_02861C_SPI_VS_OUT_ID_0
, 10);
3411 for (i
= 0; i
< 10; i
++) {
3412 r600_store_value(cb
, spi_vs_out_id
[i
]);
3415 /* Certain attributes (position, psize, etc.) don't count as params.
3416 * VS is required to export at least one param and r600_shader_from_tgsi()
3417 * takes care of adding a dummy export.
3422 r600_store_context_reg(cb
, R_0286C4_SPI_VS_OUT_CONFIG
,
3423 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
3424 r600_store_context_reg(cb
, R_028860_SQ_PGM_RESOURCES_VS
,
3425 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
3426 S_028860_STACK_SIZE(rshader
->bc
.nstack
));
3427 r600_store_context_reg(cb
, R_02885C_SQ_PGM_START_VS
,
3428 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8);
3429 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3431 shader
->pa_cl_vs_out_cntl
=
3432 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
3433 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
3434 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
3435 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
);
3438 void *evergreen_create_resolve_blend(struct r600_context
*rctx
)
3440 struct pipe_blend_state blend
;
3442 memset(&blend
, 0, sizeof(blend
));
3443 blend
.independent_blend_enable
= true;
3444 blend
.rt
[0].colormask
= 0xf;
3445 return evergreen_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_CB_RESOLVE
);
3448 void *evergreen_create_decompress_blend(struct r600_context
*rctx
)
3450 struct pipe_blend_state blend
;
3452 memset(&blend
, 0, sizeof(blend
));
3453 blend
.independent_blend_enable
= true;
3454 blend
.rt
[0].colormask
= 0xf;
3455 return evergreen_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_CB_DECOMPRESS
);
3458 void *evergreen_create_fmask_decompress_blend(struct r600_context
*rctx
)
3460 struct pipe_blend_state blend
;
3462 memset(&blend
, 0, sizeof(blend
));
3463 blend
.independent_blend_enable
= true;
3464 blend
.rt
[0].colormask
= 0xf;
3465 return evergreen_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_CB_FMASK_DECOMPRESS
);
3468 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
)
3470 struct pipe_depth_stencil_alpha_state dsa
= {{0}};
3472 return rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
3475 void evergreen_update_db_shader_control(struct r600_context
* rctx
)
3477 bool dual_export
= rctx
->framebuffer
.export_16bpc
&&
3478 !rctx
->ps_shader
->current
->ps_depth_export
;
3480 unsigned db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
3481 S_02880C_DUAL_EXPORT_ENABLE(dual_export
) |
3482 S_02880C_DB_SOURCE_FORMAT(dual_export
? V_02880C_EXPORT_DB_TWO
:
3483 V_02880C_EXPORT_DB_FULL
) |
3484 S_02880C_ALPHA_TO_MASK_DISABLE(rctx
->framebuffer
.cb0_is_integer
);
3486 /* When alpha test is enabled we can't trust the hw to make the proper
3487 * decision on the order in which ztest should be run related to fragment
3490 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3491 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3492 * execution and thus after alpha test so if discarded by the alpha test
3493 * the z value is not written.
3494 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3495 * get a hang unless you flush the DB in between. For now just use
3498 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
3499 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
3501 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
3504 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
) {
3505 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
3506 rctx
->db_misc_state
.atom
.dirty
= true;
3510 static void evergreen_dma_copy_tile(struct r600_context
*rctx
,
3511 struct pipe_resource
*dst
,
3516 struct pipe_resource
*src
,
3521 unsigned copy_height
,
3525 struct radeon_winsys_cs
*cs
= rctx
->rings
.dma
.cs
;
3526 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3527 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3528 unsigned array_mode
, lbpp
, pitch_tile_max
, slice_tile_max
, size
;
3529 unsigned ncopy
, height
, cheight
, detile
, i
, x
, y
, z
, src_mode
, dst_mode
;
3530 unsigned sub_cmd
, bank_h
, bank_w
, mt_aspect
, nbanks
, tile_split
, non_disp_tiling
= 0;
3531 uint64_t base
, addr
;
3533 /* make sure that the dma ring is only one active */
3534 rctx
->rings
.gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
);
3536 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
3537 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
3538 /* downcast linear aligned to linear to simplify test */
3539 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
3540 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
3541 assert(dst_mode
!= src_mode
);
3543 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3544 if (util_format_has_depth(util_format_description(src
->format
)))
3545 non_disp_tiling
= 1;
3549 lbpp
= util_logbase2(bpp
);
3550 pitch_tile_max
= ((pitch
/ bpp
) >> 3) - 1;
3551 nbanks
= eg_num_banks(rctx
->screen
->tiling_info
.num_banks
);
3553 if (dst_mode
== RADEON_SURF_MODE_LINEAR
) {
3555 array_mode
= evergreen_array_mode(src_mode
);
3556 slice_tile_max
= (rsrc
->surface
.level
[src_level
].nblk_x
* rsrc
->surface
.level
[src_level
].nblk_y
) >> 6;
3557 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3558 /* linear height must be the same as the slice tile max height, it's ok even
3559 * if the linear destination/source have smaller heigh as the size of the
3560 * dma packet will be using the copy_height which is always smaller or equal
3561 * to the linear height
3563 height
= rsrc
->surface
.level
[src_level
].npix_y
;
3568 base
= rsrc
->surface
.level
[src_level
].offset
;
3569 addr
= rdst
->surface
.level
[dst_level
].offset
;
3570 addr
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
3571 addr
+= dst_y
* pitch
+ dst_x
* bpp
;
3572 bank_h
= eg_bank_wh(rsrc
->surface
.bankh
);
3573 bank_w
= eg_bank_wh(rsrc
->surface
.bankw
);
3574 mt_aspect
= eg_macro_tile_aspect(rsrc
->surface
.mtilea
);
3575 tile_split
= eg_tile_split(rsrc
->surface
.tile_split
);
3576 base
+= r600_resource_va(&rctx
->screen
->screen
, src
);
3577 addr
+= r600_resource_va(&rctx
->screen
->screen
, dst
);
3580 array_mode
= evergreen_array_mode(dst_mode
);
3581 slice_tile_max
= (rdst
->surface
.level
[dst_level
].nblk_x
* rdst
->surface
.level
[dst_level
].nblk_y
) >> 6;
3582 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3583 /* linear height must be the same as the slice tile max height, it's ok even
3584 * if the linear destination/source have smaller heigh as the size of the
3585 * dma packet will be using the copy_height which is always smaller or equal
3586 * to the linear height
3588 height
= rdst
->surface
.level
[dst_level
].npix_y
;
3593 base
= rdst
->surface
.level
[dst_level
].offset
;
3594 addr
= rsrc
->surface
.level
[src_level
].offset
;
3595 addr
+= rsrc
->surface
.level
[src_level
].slice_size
* src_z
;
3596 addr
+= src_y
* pitch
+ src_x
* bpp
;
3597 bank_h
= eg_bank_wh(rdst
->surface
.bankh
);
3598 bank_w
= eg_bank_wh(rdst
->surface
.bankw
);
3599 mt_aspect
= eg_macro_tile_aspect(rdst
->surface
.mtilea
);
3600 tile_split
= eg_tile_split(rdst
->surface
.tile_split
);
3601 base
+= r600_resource_va(&rctx
->screen
->screen
, dst
);
3602 addr
+= r600_resource_va(&rctx
->screen
->screen
, src
);
3605 size
= (copy_height
* pitch
) >> 2;
3606 ncopy
= (size
/ 0x000fffff) + !!(size
% 0x000fffff);
3607 r600_need_dma_space(rctx
, ncopy
* 9);
3609 for (i
= 0; i
< ncopy
; i
++) {
3610 cheight
= copy_height
;
3611 if (((cheight
* pitch
) >> 2) > 0x000fffff) {
3612 cheight
= (0x000fffff << 2) / pitch
;
3614 size
= (cheight
* pitch
) >> 2;
3615 /* emit reloc before writting cs so that cs is always in consistent state */
3616 r600_context_bo_reloc(rctx
, &rctx
->rings
.dma
, &rsrc
->resource
, RADEON_USAGE_READ
);
3617 r600_context_bo_reloc(rctx
, &rctx
->rings
.dma
, &rdst
->resource
, RADEON_USAGE_WRITE
);
3618 cs
->buf
[cs
->cdw
++] = DMA_PACKET(DMA_PACKET_COPY
, sub_cmd
, size
);
3619 cs
->buf
[cs
->cdw
++] = base
>> 8;
3620 cs
->buf
[cs
->cdw
++] = (detile
<< 31) | (array_mode
<< 27) |
3621 (lbpp
<< 24) | (bank_h
<< 21) |
3622 (bank_w
<< 18) | (mt_aspect
<< 16);
3623 cs
->buf
[cs
->cdw
++] = (pitch_tile_max
<< 0) | ((height
- 1) << 16);
3624 cs
->buf
[cs
->cdw
++] = (slice_tile_max
<< 0);
3625 cs
->buf
[cs
->cdw
++] = (x
<< 0) | (z
<< 18);
3626 cs
->buf
[cs
->cdw
++] = (y
<< 0) | (tile_split
<< 21) | (nbanks
<< 25) | (non_disp_tiling
<< 28);
3627 cs
->buf
[cs
->cdw
++] = addr
& 0xfffffffc;
3628 cs
->buf
[cs
->cdw
++] = (addr
>> 32UL) & 0xff;
3629 copy_height
-= cheight
;
3630 addr
+= cheight
* pitch
;
3635 boolean
evergreen_dma_blit(struct pipe_context
*ctx
,
3636 struct pipe_resource
*dst
,
3638 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
3639 struct pipe_resource
*src
,
3641 const struct pipe_box
*src_box
)
3643 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3644 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3645 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3646 unsigned dst_pitch
, src_pitch
, bpp
, dst_mode
, src_mode
, copy_height
;
3647 unsigned src_w
, dst_w
;
3649 if (rctx
->rings
.dma
.cs
== NULL
) {
3652 if (src
->format
!= dst
->format
) {
3656 bpp
= rdst
->surface
.bpe
;
3657 dst_pitch
= rdst
->surface
.level
[dst_level
].pitch_bytes
;
3658 src_pitch
= rsrc
->surface
.level
[src_level
].pitch_bytes
;
3659 src_w
= rsrc
->surface
.level
[src_level
].npix_x
;
3660 dst_w
= rdst
->surface
.level
[dst_level
].npix_x
;
3661 copy_height
= src_box
->height
/ rsrc
->surface
.blk_h
;
3663 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
3664 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
3665 /* downcast linear aligned to linear to simplify test */
3666 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
3667 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
3669 if (src_pitch
!= dst_pitch
|| src_box
->x
|| dst_x
|| src_w
!= dst_w
) {
3670 /* FIXME evergreen can do partial blit */
3673 /* the x test here are currently useless (because we don't support partial blit)
3674 * but keep them around so we don't forget about those
3676 if ((src_pitch
& 0x7) || (src_box
->x
& 0x7) || (dst_x
& 0x7) || (src_box
->y
& 0x7) || (dst_y
& 0x7)) {
3680 /* 128 bpp surfaces require non_disp_tiling for both
3681 * tiled and linear buffers on cayman. However, async
3682 * DMA only supports it on the tiled side. As such
3683 * the tile order is backwards after a L2T/T2L packet.
3685 if ((rctx
->chip_class
== CAYMAN
) &&
3686 (src_mode
!= dst_mode
) &&
3687 (util_format_get_blocksize(src
->format
) >= 16)) {
3691 if (src_mode
== dst_mode
) {
3692 uint64_t dst_offset
, src_offset
;
3693 /* simple dma blit would do NOTE code here assume :
3696 * dst_pitch == src_pitch
3698 src_offset
= rsrc
->surface
.level
[src_level
].offset
;
3699 src_offset
+= rsrc
->surface
.level
[src_level
].slice_size
* src_box
->z
;
3700 src_offset
+= src_box
->y
* src_pitch
+ src_box
->x
* bpp
;
3701 dst_offset
= rdst
->surface
.level
[dst_level
].offset
;
3702 dst_offset
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
3703 dst_offset
+= dst_y
* dst_pitch
+ dst_x
* bpp
;
3704 evergreen_dma_copy(rctx
, dst
, src
, dst_offset
, src_offset
,
3705 src_box
->height
* src_pitch
);
3707 evergreen_dma_copy_tile(rctx
, dst
, dst_level
, dst_x
, dst_y
, dst_z
,
3708 src
, src_level
, src_box
->x
, src_box
->y
, src_box
->z
,
3709 copy_height
, dst_pitch
, bpp
);
3714 void evergreen_init_state_functions(struct r600_context
*rctx
)
3719 * To avoid GPU lockup registers must be emited in a specific order
3720 * (no kidding ...). The order below is important and have been
3721 * partialy infered from analyzing fglrx command stream.
3723 * Don't reorder atom without carefully checking the effect (GPU lockup
3724 * or piglit regression).
3728 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, evergreen_emit_framebuffer_state
, 0);
3730 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, evergreen_emit_vs_constant_buffers
, 0);
3731 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, evergreen_emit_gs_constant_buffers
, 0);
3732 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, evergreen_emit_ps_constant_buffers
, 0);
3733 /* shader program */
3734 r600_init_atom(rctx
, &rctx
->cs_shader_state
.atom
, id
++, evergreen_emit_cs_shader
, 0);
3736 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, evergreen_emit_vs_sampler_states
, 0);
3737 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, evergreen_emit_gs_sampler_states
, 0);
3738 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, evergreen_emit_ps_sampler_states
, 0);
3740 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, evergreen_fs_emit_vertex_buffers
, 0);
3741 r600_init_atom(rctx
, &rctx
->cs_vertex_buffer_state
.atom
, id
++, evergreen_cs_emit_vertex_buffers
, 0);
3742 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, evergreen_emit_vs_sampler_views
, 0);
3743 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, evergreen_emit_gs_sampler_views
, 0);
3744 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, evergreen_emit_ps_sampler_views
, 0);
3746 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 7);
3748 if (rctx
->chip_class
== EVERGREEN
) {
3749 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, evergreen_emit_sample_mask
, 3);
3751 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, cayman_emit_sample_mask
, 4);
3753 rctx
->sample_mask
.sample_mask
= ~0;
3755 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
3756 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
3757 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
3758 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, evergreen_emit_cb_misc_state
, 4);
3759 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 6);
3760 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, evergreen_emit_clip_state
, 26);
3761 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, evergreen_emit_db_misc_state
, 10);
3762 r600_init_atom(rctx
, &rctx
->db_state
.atom
, id
++, evergreen_emit_db_state
, 14);
3763 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
3764 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, evergreen_emit_polygon_offset
, 6);
3765 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
3766 r600_init_atom(rctx
, &rctx
->scissor
.atom
, id
++, evergreen_emit_scissor_state
, 4);
3767 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
3768 r600_init_atom(rctx
, &rctx
->viewport
.atom
, id
++, r600_emit_viewport_state
, 8);
3769 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, evergreen_emit_vertex_fetch_shader
, 5);
3770 r600_init_atom(rctx
, &rctx
->streamout
.begin_atom
, id
++, r600_emit_streamout_begin
, 0);
3771 r600_init_atom(rctx
, &rctx
->vertex_shader
.atom
, id
++, r600_emit_shader
, 23);
3772 r600_init_atom(rctx
, &rctx
->pixel_shader
.atom
, id
++, r600_emit_shader
, 0);
3774 rctx
->context
.create_blend_state
= evergreen_create_blend_state
;
3775 rctx
->context
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
3776 rctx
->context
.create_rasterizer_state
= evergreen_create_rs_state
;
3777 rctx
->context
.create_sampler_state
= evergreen_create_sampler_state
;
3778 rctx
->context
.create_sampler_view
= evergreen_create_sampler_view
;
3779 rctx
->context
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
3780 rctx
->context
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
3781 rctx
->context
.set_scissor_state
= evergreen_set_scissor_state
;
3782 evergreen_init_compute_state_functions(rctx
);