projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: use a hash table instead of group
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <pipebuffer/pb_buffer.h>
43 #include "r600.h"
44 #include "evergreend.h"
45 struct radeon_state {
46 unsigned dummy;
47 };
48 #include "r600_resource.h"
49 #include "r600_shader.h"
50 #include "r600_pipe.h"
51 #include "eg_state_inlines.h"
52
53 static void evergreen_set_blend_color(struct pipe_context *ctx,
54 const struct pipe_blend_color *state)
55 {
56 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
57 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
58
59 if (rstate == NULL)
60 return;
61
62 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
63 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
65 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
66 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
67
68 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
69 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
70 r600_context_pipe_state_set(&rctx->ctx, rstate);
71 }
72
73 static void *evergreen_create_blend_state(struct pipe_context *ctx,
74 const struct pipe_blend_state *state)
75 {
76 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
77 struct r600_pipe_state *rstate;
78 u32 color_control, target_mask;
79 /* FIXME there is more then 8 framebuffer */
80 unsigned blend_cntl[8];
81
82 if (blend == NULL) {
83 return NULL;
84 }
85 rstate = &blend->rstate;
86
87 rstate->id = R600_PIPE_STATE_BLEND;
88
89 target_mask = 0;
90 color_control = S_028808_MODE(1);
91 if (state->logicop_enable) {
92 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
93 } else {
94 color_control |= (0xcc << 16);
95 }
96 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
97 if (state->independent_blend_enable) {
98 for (int i = 0; i < 8; i++) {
99 target_mask |= (state->rt[i].colormask << (4 * i));
100 }
101 } else {
102 for (int i = 0; i < 8; i++) {
103 target_mask |= (state->rt[0].colormask << (4 * i));
104 }
105 }
106 blend->cb_target_mask = target_mask;
107 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
108 color_control, 0xFFFFFFFF, NULL);
109 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
110
111 for (int i = 0; i < 8; i++) {
112 unsigned eqRGB = state->rt[i].rgb_func;
113 unsigned srcRGB = state->rt[i].rgb_src_factor;
114 unsigned dstRGB = state->rt[i].rgb_dst_factor;
115 unsigned eqA = state->rt[i].alpha_func;
116 unsigned srcA = state->rt[i].alpha_src_factor;
117 unsigned dstA = state->rt[i].alpha_dst_factor;
118
119 blend_cntl[i] = 0;
120 if (!state->rt[i].blend_enable)
121 continue;
122
123 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
124 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
125 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
126 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
127
128 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
129 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
130 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
131 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
132 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
133 }
134 }
135 for (int i = 0; i < 8; i++) {
136 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
137 }
138
139 return rstate;
140 }
141
142 static void evergreen_bind_blend_state(struct pipe_context *ctx, void *state)
143 {
144 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
145 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
146 struct r600_pipe_state *rstate;
147
148 if (state == NULL)
149 return;
150 rstate = &blend->rstate;
151 rctx->states[rstate->id] = rstate;
152 rctx->cb_target_mask = blend->cb_target_mask;
153 r600_context_pipe_state_set(&rctx->ctx, rstate);
154 }
155
156 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
157 const struct pipe_depth_stencil_alpha_state *state)
158 {
159 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
160 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
161 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
162
163 if (rstate == NULL) {
164 return NULL;
165 }
166
167 rstate->id = R600_PIPE_STATE_DSA;
168 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
169 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
170 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
171 * be set if shader use texkill instruction
172 */
173 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
174 stencil_ref_mask = 0;
175 stencil_ref_mask_bf = 0;
176 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
177 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
178 S_028800_ZFUNC(state->depth.func);
179
180 /* stencil */
181 if (state->stencil[0].enabled) {
182 db_depth_control |= S_028800_STENCIL_ENABLE(1);
183 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
184 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
185 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
186 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
187
188
189 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
190 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
191 if (state->stencil[1].enabled) {
192 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
193 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
194 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
195 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
196 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
197 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
198 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
199 }
200 }
201
202 /* alpha */
203 alpha_test_control = 0;
204 alpha_ref = 0;
205 if (state->alpha.enabled) {
206 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
207 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
208 alpha_ref = fui(state->alpha.ref_value);
209 }
210
211 /* misc */
212 db_render_control = 0;
213 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
214 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
215 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
216 /* TODO db_render_override depends on query */
217 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
218 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
219 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
220 r600_pipe_state_add_reg(rstate,
221 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
222 0xFFFFFFFF & C_028430_STENCILREF, NULL);
223 r600_pipe_state_add_reg(rstate,
224 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
225 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
226 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
227 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
228 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
229 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
230 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
231 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
232 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
233 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
234 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
235 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
236
237 return rstate;
238 }
239
240 static void *evergreen_create_rs_state(struct pipe_context *ctx,
241 const struct pipe_rasterizer_state *state)
242 {
243 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
244 struct r600_pipe_state *rstate;
245 unsigned tmp;
246 unsigned prov_vtx = 1, polygon_dual_mode;
247
248 if (rs == NULL) {
249 return NULL;
250 }
251
252 rstate = &rs->rstate;
253 rs->flatshade = state->flatshade;
254 rs->sprite_coord_enable = state->sprite_coord_enable;
255
256 /* offset */
257 rs->offset_units = state->offset_units;
258 rs->offset_scale = state->offset_scale * 12.0f;
259
260 rstate->id = R600_PIPE_STATE_RASTERIZER;
261 if (state->flatshade_first)
262 prov_vtx = 0;
263 tmp = 0x00000001;
264 if (state->sprite_coord_enable) {
265 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
266 S_0286D4_PNT_SPRITE_OVRD_X(2) |
267 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
268 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
269 S_0286D4_PNT_SPRITE_OVRD_W(1);
270 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
271 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
272 }
273 }
274 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
275
276 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
277 state->fill_back != PIPE_POLYGON_MODE_FILL);
278 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
279 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
280 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
281 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
282 S_028814_FACE(!state->front_ccw) |
283 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
284 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
285 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
286 S_028814_POLY_MODE(polygon_dual_mode) |
287 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
288 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
289 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
290 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
291 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
292 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
293 /* point size 12.4 fixed point */
294 tmp = (unsigned)(state->point_size * 8.0);
295 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
296 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
297 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
298 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
299 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
300 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
301 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
302 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
303 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
304 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 0x00000005, 0xFFFFFFFF, NULL);
305 return rstate;
306 }
307
308 static void evergreen_bind_rs_state(struct pipe_context *ctx, void *state)
309 {
310 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
311 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
312
313 if (state == NULL)
314 return;
315
316 rctx->flatshade = rs->flatshade;
317 rctx->sprite_coord_enable = rs->sprite_coord_enable;
318 rctx->rasterizer = rs;
319
320 rctx->states[rs->rstate.id] = &rs->rstate;
321 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
322 }
323
324 static void evergreen_delete_rs_state(struct pipe_context *ctx, void *state)
325 {
326 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
327 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
328
329 if (rctx->rasterizer == rs) {
330 rctx->rasterizer = NULL;
331 }
332 if (rctx->states[rs->rstate.id] == &rs->rstate) {
333 rctx->states[rs->rstate.id] = NULL;
334 }
335 free(rs);
336 }
337
338 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
339 const struct pipe_sampler_state *state)
340 {
341 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
342 union util_color uc;
343
344 if (rstate == NULL) {
345 return NULL;
346 }
347
348 rstate->id = R600_PIPE_STATE_SAMPLER;
349 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
350 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
351 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
352 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
353 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
354 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
355 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
356 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
357 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
358 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
359 /* FIXME LOD it depends on texture base level ... */
360 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
361 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
362 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)),
363 0xFFFFFFFF, NULL);
364 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
365 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
366 S_03C008_TYPE(1),
367 0xFFFFFFFF, NULL);
368
369 if (uc.ui) {
370 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
371 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
372 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
373 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
374 }
375 return rstate;
376 }
377
378 static void *evergreen_create_vertex_elements(struct pipe_context *ctx,
379 unsigned count,
380 const struct pipe_vertex_element *elements)
381 {
382 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
383
384 assert(count < 32);
385 v->count = count;
386 v->refcount = 1;
387 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
388 return v;
389 }
390
391 static void evergreen_sampler_view_destroy(struct pipe_context *ctx,
392 struct pipe_sampler_view *state)
393 {
394 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
395
396 pipe_resource_reference(&state->texture, NULL);
397 FREE(resource);
398 }
399
400 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
401 struct pipe_resource *texture,
402 const struct pipe_sampler_view *state)
403 {
404 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
405 struct r600_pipe_state *rstate;
406 const struct util_format_description *desc;
407 struct r600_resource_texture *tmp;
408 struct r600_resource *rbuffer;
409 unsigned format;
410 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
411 unsigned char swizzle[4];
412 struct radeon_ws_bo *bo[2];
413
414 if (resource == NULL)
415 return NULL;
416 rstate = &resource->state;
417
418 /* initialize base object */
419 resource->base = *state;
420 resource->base.texture = NULL;
421 pipe_reference(NULL, &texture->reference);
422 resource->base.texture = texture;
423 resource->base.reference.count = 1;
424 resource->base.context = ctx;
425
426 swizzle[0] = state->swizzle_r;
427 swizzle[1] = state->swizzle_g;
428 swizzle[2] = state->swizzle_b;
429 swizzle[3] = state->swizzle_a;
430 format = r600_translate_texformat(texture->format,
431 swizzle,
432 &word4, &yuv_format);
433 if (format == ~0) {
434 format = 0;
435 }
436 desc = util_format_description(texture->format);
437 if (desc == NULL) {
438 R600_ERR("unknow format %d\n", texture->format);
439 }
440 tmp = (struct r600_resource_texture*)texture;
441 rbuffer = &tmp->resource;
442 bo[0] = rbuffer->bo;
443 bo[1] = rbuffer->bo;
444 /* FIXME depth texture decompression */
445 if (tmp->depth) {
446 #if 0
447 r = evergreen_texture_from_depth(ctx, tmp, view->first_level);
448 if (r) {
449 return;
450 }
451 bo[0] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
452 bo[1] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
453 #endif
454 }
455 pitch = align(tmp->pitch[0] / tmp->bpt, 8);
456
457 /* FIXME properly handle first level != 0 */
458 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
459 S_030000_DIM(r600_tex_dim(texture->target)) |
460 S_030000_PITCH((pitch / 8) - 1) |
461 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
462 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
463 S_030004_TEX_HEIGHT(texture->height0 - 1) |
464 S_030004_TEX_DEPTH(texture->depth0 - 1),
465 0xFFFFFFFF, NULL);
466 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
467 tmp->offset[0] >> 8, 0xFFFFFFFF, bo[0]);
468 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
469 tmp->offset[1] >> 8, 0xFFFFFFFF, bo[1]);
470 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
471 word4 | S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
472 S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
473 S_030010_REQUEST_SIZE(1) |
474 S_030010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
475 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
476 S_030014_LAST_LEVEL(state->last_level) |
477 S_030014_BASE_ARRAY(0) |
478 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
479 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
480 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
481 S_03001C_DATA_FORMAT(format) |
482 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
483
484 return &resource->base;
485 }
486
487 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
488 struct pipe_sampler_view **views)
489 {
490 /* TODO */
491 assert(1);
492 }
493
494 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
495 struct pipe_sampler_view **views)
496 {
497 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
498 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
499
500 for (int i = 0; i < count; i++) {
501 if (resource[i]) {
502 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
503 }
504 }
505 }
506
507 static void evergreen_bind_state(struct pipe_context *ctx, void *state)
508 {
509 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
510 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
511
512 if (state == NULL)
513 return;
514 rctx->states[rstate->id] = rstate;
515 r600_context_pipe_state_set(&rctx->ctx, rstate);
516 }
517
518 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
519 {
520 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
521 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
522
523 for (int i = 0; i < count; i++) {
524 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
525 }
526 }
527
528 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
529 {
530 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
531 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
532
533 /* TODO implement */
534 for (int i = 0; i < count; i++) {
535 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
536 }
537 }
538
539 static void evergreen_delete_state(struct pipe_context *ctx, void *state)
540 {
541 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
542 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
543
544 if (rctx->states[rstate->id] == rstate) {
545 rctx->states[rstate->id] = NULL;
546 }
547 for (int i = 0; i < rstate->nregs; i++) {
548 radeon_ws_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
549 }
550 free(rstate);
551 }
552
553 static void evergreen_delete_vertex_element(struct pipe_context *ctx, void *state)
554 {
555 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
556
557 if (v == NULL)
558 return;
559 if (--v->refcount)
560 return;
561 free(v);
562 }
563
564 static void evergreen_set_clip_state(struct pipe_context *ctx,
565 const struct pipe_clip_state *state)
566 {
567 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
568 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
569
570 if (rstate == NULL)
571 return;
572
573 rctx->clip = *state;
574 rstate->id = R600_PIPE_STATE_CLIP;
575 for (int i = 0; i < state->nr; i++) {
576 r600_pipe_state_add_reg(rstate,
577 R_0285BC_PA_CL_UCP0_X + i * 4,
578 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
579 r600_pipe_state_add_reg(rstate,
580 R_0285C0_PA_CL_UCP0_Y + i * 4,
581 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
582 r600_pipe_state_add_reg(rstate,
583 R_0285C4_PA_CL_UCP0_Z + i * 4,
584 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
585 r600_pipe_state_add_reg(rstate,
586 R_0285C8_PA_CL_UCP0_W + i * 4,
587 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
588 }
589 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
590 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
591 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
592 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
593
594 free(rctx->states[R600_PIPE_STATE_CLIP]);
595 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
596 r600_context_pipe_state_set(&rctx->ctx, rstate);
597 }
598
599 static void evergreen_bind_vertex_elements(struct pipe_context *ctx, void *state)
600 {
601 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
602 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
603
604 evergreen_delete_vertex_element(ctx, rctx->vertex_elements);
605 rctx->vertex_elements = v;
606 if (v) {
607 v->refcount++;
608 // rctx->vs_rebuild = TRUE;
609 }
610 }
611
612 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
613 const struct pipe_poly_stipple *state)
614 {
615 }
616
617 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
618 {
619 }
620
621 static void evergreen_set_scissor_state(struct pipe_context *ctx,
622 const struct pipe_scissor_state *state)
623 {
624 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
625 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
626 u32 tl, br;
627
628 if (rstate == NULL)
629 return;
630
631 rstate->id = R600_PIPE_STATE_SCISSOR;
632 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
633 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
634 r600_pipe_state_add_reg(rstate,
635 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
636 0xFFFFFFFF, NULL);
637 r600_pipe_state_add_reg(rstate,
638 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
639 0xFFFFFFFF, NULL);
640 r600_pipe_state_add_reg(rstate,
641 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
642 0xFFFFFFFF, NULL);
643 r600_pipe_state_add_reg(rstate,
644 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
645 0xFFFFFFFF, NULL);
646 r600_pipe_state_add_reg(rstate,
647 R_028210_PA_SC_CLIPRECT_0_TL, tl,
648 0xFFFFFFFF, NULL);
649 r600_pipe_state_add_reg(rstate,
650 R_028214_PA_SC_CLIPRECT_0_BR, br,
651 0xFFFFFFFF, NULL);
652 r600_pipe_state_add_reg(rstate,
653 R_028218_PA_SC_CLIPRECT_1_TL, tl,
654 0xFFFFFFFF, NULL);
655 r600_pipe_state_add_reg(rstate,
656 R_02821C_PA_SC_CLIPRECT_1_BR, br,
657 0xFFFFFFFF, NULL);
658 r600_pipe_state_add_reg(rstate,
659 R_028220_PA_SC_CLIPRECT_2_TL, tl,
660 0xFFFFFFFF, NULL);
661 r600_pipe_state_add_reg(rstate,
662 R_028224_PA_SC_CLIPRECT_2_BR, br,
663 0xFFFFFFFF, NULL);
664 r600_pipe_state_add_reg(rstate,
665 R_028228_PA_SC_CLIPRECT_3_TL, tl,
666 0xFFFFFFFF, NULL);
667 r600_pipe_state_add_reg(rstate,
668 R_02822C_PA_SC_CLIPRECT_3_BR, br,
669 0xFFFFFFFF, NULL);
670 r600_pipe_state_add_reg(rstate,
671 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
672 0xFFFFFFFF, NULL);
673 r600_pipe_state_add_reg(rstate,
674 R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
675 0xFFFFFFFF, NULL);
676 r600_pipe_state_add_reg(rstate,
677 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
678 0xFFFFFFFF, NULL);
679
680 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
681 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
682 r600_context_pipe_state_set(&rctx->ctx, rstate);
683 }
684
685 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
686 const struct pipe_stencil_ref *state)
687 {
688 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
689 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
690 u32 tmp;
691
692 if (rstate == NULL)
693 return;
694
695 rctx->stencil_ref = *state;
696 rstate->id = R600_PIPE_STATE_STENCIL_REF;
697 tmp = S_028430_STENCILREF(state->ref_value[0]);
698 r600_pipe_state_add_reg(rstate,
699 R_028430_DB_STENCILREFMASK, tmp,
700 ~C_028430_STENCILREF, NULL);
701 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
702 r600_pipe_state_add_reg(rstate,
703 R_028434_DB_STENCILREFMASK_BF, tmp,
704 ~C_028434_STENCILREF_BF, NULL);
705
706 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
707 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
708 r600_context_pipe_state_set(&rctx->ctx, rstate);
709 }
710
711 static void evergreen_set_viewport_state(struct pipe_context *ctx,
712 const struct pipe_viewport_state *state)
713 {
714 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
715 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
716
717 if (rstate == NULL)
718 return;
719
720 rctx->viewport = *state;
721 rstate->id = R600_PIPE_STATE_VIEWPORT;
722 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
723 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
724 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
725 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
726 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
727 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
728 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
729 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
730 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
731
732 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
733 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
734 r600_context_pipe_state_set(&rctx->ctx, rstate);
735 }
736
737 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
738 const struct pipe_framebuffer_state *state, int cb)
739 {
740 struct r600_resource_texture *rtex;
741 struct r600_resource *rbuffer;
742 unsigned level = state->cbufs[cb]->level;
743 unsigned pitch, slice;
744 unsigned color_info;
745 unsigned format, swap, ntype;
746 const struct util_format_description *desc;
747 struct radeon_ws_bo *bo[3];
748
749 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
750 rbuffer = &rtex->resource;
751 bo[0] = rbuffer->bo;
752 bo[1] = rbuffer->bo;
753 bo[2] = rbuffer->bo;
754
755 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
756 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
757 ntype = 0;
758 desc = util_format_description(rtex->resource.base.b.format);
759 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
760 ntype = V_028C70_NUMBER_SRGB;
761
762 format = r600_translate_colorformat(rtex->resource.base.b.format);
763 swap = r600_translate_colorswap(rtex->resource.base.b.format);
764 color_info = S_028C70_FORMAT(format) |
765 S_028C70_COMP_SWAP(swap) |
766 S_028C70_BLEND_CLAMP(1) |
767 S_028C70_NUMBER_TYPE(ntype);
768 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
769 color_info |= S_028C70_SOURCE_FORMAT(1);
770
771 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
772 r600_pipe_state_add_reg(rstate,
773 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
774 state->cbufs[cb]->offset >> 8, 0xFFFFFFFF, bo[0]);
775 r600_pipe_state_add_reg(rstate,
776 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
777 0x0, 0xFFFFFFFF, NULL);
778 r600_pipe_state_add_reg(rstate,
779 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
780 color_info, 0xFFFFFFFF, bo[0]);
781 r600_pipe_state_add_reg(rstate,
782 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
783 S_028C64_PITCH_TILE_MAX(pitch),
784 0xFFFFFFFF, NULL);
785 r600_pipe_state_add_reg(rstate,
786 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
787 S_028C68_SLICE_TILE_MAX(slice),
788 0xFFFFFFFF, NULL);
789 r600_pipe_state_add_reg(rstate,
790 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
791 0x00000000, 0xFFFFFFFF, NULL);
792 r600_pipe_state_add_reg(rstate,
793 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
794 S_028C74_NON_DISP_TILING_ORDER(1),
795 0xFFFFFFFF, NULL);
796 }
797
798 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
799 const struct pipe_framebuffer_state *state)
800 {
801 struct r600_resource_texture *rtex;
802 struct r600_resource *rbuffer;
803 unsigned level;
804 unsigned pitch, slice, format;
805
806 if (state->zsbuf == NULL)
807 return;
808
809 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
810 rtex->tiled = 1;
811 rtex->array_mode = 2;
812 rtex->tile_type = 1;
813 rtex->depth = 1;
814 rbuffer = &rtex->resource;
815
816 level = state->zsbuf->level;
817 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
818 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
819 format = r600_translate_dbformat(state->zsbuf->texture->format);
820
821 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
822 state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
823 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
824 state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
825 // r600_pipe_state_add_reg(rstate, R_028014_DB_HTILE_DATA_BASE, state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
826 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
827 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
828 S_028040_ARRAY_MODE(rtex->array_mode) | S_028040_FORMAT(format),
829 0xFFFFFFFF, rbuffer->bo);
830 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
831 S_028058_PITCH_TILE_MAX(pitch),
832 0xFFFFFFFF, NULL);
833 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
834 S_02805C_SLICE_TILE_MAX(slice),
835 0xFFFFFFFF, NULL);
836 }
837
838 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
839 const struct pipe_framebuffer_state *state)
840 {
841 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
842 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
843 u32 shader_mask, tl, br, target_mask;
844
845 if (rstate == NULL)
846 return;
847
848 /* unreference old buffer and reference new one */
849 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
850 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
851 pipe_surface_reference(&rctx->framebuffer.cbufs[i], NULL);
852 }
853 for (int i = 0; i < state->nr_cbufs; i++) {
854 pipe_surface_reference(&rctx->framebuffer.cbufs[i], state->cbufs[i]);
855 }
856 pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
857 rctx->framebuffer = *state;
858
859 /* build states */
860 for (int i = 0; i < state->nr_cbufs; i++) {
861 evergreen_cb(rctx, rstate, state, i);
862 }
863 if (state->zsbuf) {
864 evergreen_db(rctx, rstate, state);
865 }
866
867 target_mask = 0x00000000;
868 target_mask = 0xFFFFFFFF;
869 shader_mask = 0;
870 for (int i = 0; i < state->nr_cbufs; i++) {
871 target_mask ^= 0xf << (i * 4);
872 shader_mask |= 0xf << (i * 4);
873 }
874 tl = S_028240_TL_X(0) | S_028240_TL_Y(0);
875 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
876
877 r600_pipe_state_add_reg(rstate,
878 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
879 0xFFFFFFFF, NULL);
880 r600_pipe_state_add_reg(rstate,
881 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
882 0xFFFFFFFF, NULL);
883 r600_pipe_state_add_reg(rstate,
884 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
885 0xFFFFFFFF, NULL);
886 r600_pipe_state_add_reg(rstate,
887 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
888 0xFFFFFFFF, NULL);
889
890 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
891 0x00000000, target_mask, NULL);
892 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
893 shader_mask, 0xFFFFFFFF, NULL);
894 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
895 0x00000000, 0xFFFFFFFF, NULL);
896 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
897 0x00000000, 0xFFFFFFFF, NULL);
898
899 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
900 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
901 r600_context_pipe_state_set(&rctx->ctx, rstate);
902 }
903
904 static void evergreen_set_index_buffer(struct pipe_context *ctx,
905 const struct pipe_index_buffer *ib)
906 {
907 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
908
909 if (ib) {
910 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
911 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
912 } else {
913 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
914 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
915 }
916
917 /* TODO make this more like a state */
918 }
919
920 static void evergreen_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
921 const struct pipe_vertex_buffer *buffers)
922 {
923 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
924
925 for (int i = 0; i < rctx->nvertex_buffer; i++) {
926 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
927 }
928 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
929 for (int i = 0; i < count; i++) {
930 rctx->vertex_buffer[i].buffer = NULL;
931 if (r600_buffer_is_user_buffer(buffers[i].buffer))
932 rctx->any_user_vbs = TRUE;
933 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
934 }
935 rctx->nvertex_buffer = count;
936 }
937
938 static void evergreen_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
939 struct pipe_resource *buffer)
940 {
941 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
942 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
943
944 switch (shader) {
945 case PIPE_SHADER_VERTEX:
946 rctx->vs_const_buffer.nregs = 0;
947 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
948 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
949 ALIGN_DIVUP(buffer->width0 >> 4, 16),
950 0xFFFFFFFF, NULL);
951 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
952 R_028980_ALU_CONST_CACHE_VS_0,
953 0, 0xFFFFFFFF, rbuffer->bo);
954 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
955 break;
956 case PIPE_SHADER_FRAGMENT:
957 rctx->ps_const_buffer.nregs = 0;
958 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
959 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
960 ALIGN_DIVUP(buffer->width0 >> 4, 16),
961 0xFFFFFFFF, NULL);
962 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
963 R_028940_ALU_CONST_CACHE_PS_0,
964 0, 0xFFFFFFFF, rbuffer->bo);
965 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
966 break;
967 default:
968 R600_ERR("unsupported %d\n", shader);
969 return;
970 }
971 }
972
973 static void *evergreen_create_shader_state(struct pipe_context *ctx,
974 const struct pipe_shader_state *state)
975 {
976 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
977 int r;
978
979 shader->shader.use_mem_constant = TRUE;
980 r = r600_pipe_shader_create2(ctx, shader, state->tokens);
981 if (r) {
982 return NULL;
983 }
984 return shader;
985 }
986
987 static void evergreen_bind_ps_shader(struct pipe_context *ctx, void *state)
988 {
989 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
990
991 /* TODO delete old shader */
992 rctx->ps_shader = (struct r600_pipe_shader *)state;
993 }
994
995 static void evergreen_bind_vs_shader(struct pipe_context *ctx, void *state)
996 {
997 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
998
999 /* TODO delete old shader */
1000 rctx->vs_shader = (struct r600_pipe_shader *)state;
1001 }
1002
1003 static void evergreen_delete_ps_shader(struct pipe_context *ctx, void *state)
1004 {
1005 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1006 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1007
1008 if (rctx->ps_shader == shader) {
1009 rctx->ps_shader = NULL;
1010 }
1011 /* TODO proper delete */
1012 free(shader);
1013 }
1014
1015 static void evergreen_delete_vs_shader(struct pipe_context *ctx, void *state)
1016 {
1017 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1018 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1019
1020 if (rctx->vs_shader == shader) {
1021 rctx->vs_shader = NULL;
1022 }
1023 /* TODO proper delete */
1024 free(shader);
1025 }
1026
1027 void evergreen_init_state_functions2(struct r600_pipe_context *rctx)
1028 {
1029 rctx->context.create_blend_state = evergreen_create_blend_state;
1030 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1031 rctx->context.create_fs_state = evergreen_create_shader_state;
1032 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1033 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1034 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1035 rctx->context.create_vertex_elements_state = evergreen_create_vertex_elements;
1036 rctx->context.create_vs_state = evergreen_create_shader_state;
1037 rctx->context.bind_blend_state = evergreen_bind_blend_state;
1038 rctx->context.bind_depth_stencil_alpha_state = evergreen_bind_state;
1039 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1040 rctx->context.bind_fs_state = evergreen_bind_ps_shader;
1041 rctx->context.bind_rasterizer_state = evergreen_bind_rs_state;
1042 rctx->context.bind_vertex_elements_state = evergreen_bind_vertex_elements;
1043 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1044 rctx->context.bind_vs_state = evergreen_bind_vs_shader;
1045 rctx->context.delete_blend_state = evergreen_delete_state;
1046 rctx->context.delete_depth_stencil_alpha_state = evergreen_delete_state;
1047 rctx->context.delete_fs_state = evergreen_delete_ps_shader;
1048 rctx->context.delete_rasterizer_state = evergreen_delete_rs_state;
1049 rctx->context.delete_sampler_state = evergreen_delete_state;
1050 rctx->context.delete_vertex_elements_state = evergreen_delete_vertex_element;
1051 rctx->context.delete_vs_state = evergreen_delete_vs_shader;
1052 rctx->context.set_blend_color = evergreen_set_blend_color;
1053 rctx->context.set_clip_state = evergreen_set_clip_state;
1054 rctx->context.set_constant_buffer = evergreen_set_constant_buffer;
1055 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1056 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1057 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1058 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1059 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1060 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1061 rctx->context.set_vertex_buffers = evergreen_set_vertex_buffers;
1062 rctx->context.set_index_buffer = evergreen_set_index_buffer;
1063 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1064 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1065 rctx->context.sampler_view_destroy = evergreen_sampler_view_destroy;
1066 }
1067
1068 void evergreen_init_config2(struct r600_pipe_context *rctx)
1069 {
1070 struct r600_pipe_state *rstate = &rctx->config;
1071 int ps_prio;
1072 int vs_prio;
1073 int gs_prio;
1074 int es_prio;
1075 int hs_prio, cs_prio, ls_prio;
1076 int num_ps_gprs;
1077 int num_vs_gprs;
1078 int num_gs_gprs;
1079 int num_es_gprs;
1080 int num_hs_gprs;
1081 int num_ls_gprs;
1082 int num_temp_gprs;
1083 int num_ps_threads;
1084 int num_vs_threads;
1085 int num_gs_threads;
1086 int num_es_threads;
1087 int num_hs_threads;
1088 int num_ls_threads;
1089 int num_ps_stack_entries;
1090 int num_vs_stack_entries;
1091 int num_gs_stack_entries;
1092 int num_es_stack_entries;
1093 int num_hs_stack_entries;
1094 int num_ls_stack_entries;
1095 enum radeon_family family;
1096 unsigned tmp;
1097
1098 family = r600_get_family(rctx->radeon);
1099 ps_prio = 0;
1100 vs_prio = 1;
1101 gs_prio = 2;
1102 es_prio = 3;
1103 hs_prio = 0;
1104 ls_prio = 0;
1105 cs_prio = 0;
1106
1107 switch (family) {
1108 case CHIP_CEDAR:
1109 default:
1110 num_ps_gprs = 93;
1111 num_vs_gprs = 46;
1112 num_temp_gprs = 4;
1113 num_gs_gprs = 31;
1114 num_es_gprs = 31;
1115 num_hs_gprs = 23;
1116 num_ls_gprs = 23;
1117 num_ps_threads = 96;
1118 num_vs_threads = 16;
1119 num_gs_threads = 16;
1120 num_es_threads = 16;
1121 num_hs_threads = 16;
1122 num_ls_threads = 16;
1123 num_ps_stack_entries = 42;
1124 num_vs_stack_entries = 42;
1125 num_gs_stack_entries = 42;
1126 num_es_stack_entries = 42;
1127 num_hs_stack_entries = 42;
1128 num_ls_stack_entries = 42;
1129 break;
1130 case CHIP_REDWOOD:
1131 num_ps_gprs = 93;
1132 num_vs_gprs = 46;
1133 num_temp_gprs = 4;
1134 num_gs_gprs = 31;
1135 num_es_gprs = 31;
1136 num_hs_gprs = 23;
1137 num_ls_gprs = 23;
1138 num_ps_threads = 128;
1139 num_vs_threads = 20;
1140 num_gs_threads = 20;
1141 num_es_threads = 20;
1142 num_hs_threads = 20;
1143 num_ls_threads = 20;
1144 num_ps_stack_entries = 42;
1145 num_vs_stack_entries = 42;
1146 num_gs_stack_entries = 42;
1147 num_es_stack_entries = 42;
1148 num_hs_stack_entries = 42;
1149 num_ls_stack_entries = 42;
1150 break;
1151 case CHIP_JUNIPER:
1152 num_ps_gprs = 93;
1153 num_vs_gprs = 46;
1154 num_temp_gprs = 4;
1155 num_gs_gprs = 31;
1156 num_es_gprs = 31;
1157 num_hs_gprs = 23;
1158 num_ls_gprs = 23;
1159 num_ps_threads = 128;
1160 num_vs_threads = 20;
1161 num_gs_threads = 20;
1162 num_es_threads = 20;
1163 num_hs_threads = 20;
1164 num_ls_threads = 20;
1165 num_ps_stack_entries = 85;
1166 num_vs_stack_entries = 85;
1167 num_gs_stack_entries = 85;
1168 num_es_stack_entries = 85;
1169 num_hs_stack_entries = 85;
1170 num_ls_stack_entries = 85;
1171 break;
1172 case CHIP_CYPRESS:
1173 case CHIP_HEMLOCK:
1174 num_ps_gprs = 93;
1175 num_vs_gprs = 46;
1176 num_temp_gprs = 4;
1177 num_gs_gprs = 31;
1178 num_es_gprs = 31;
1179 num_hs_gprs = 23;
1180 num_ls_gprs = 23;
1181 num_ps_threads = 128;
1182 num_vs_threads = 20;
1183 num_gs_threads = 20;
1184 num_es_threads = 20;
1185 num_hs_threads = 20;
1186 num_ls_threads = 20;
1187 num_ps_stack_entries = 85;
1188 num_vs_stack_entries = 85;
1189 num_gs_stack_entries = 85;
1190 num_es_stack_entries = 85;
1191 num_hs_stack_entries = 85;
1192 num_ls_stack_entries = 85;
1193 break;
1194 }
1195
1196 tmp = 0x00000000;
1197 switch (family) {
1198 case CHIP_CEDAR:
1199 break;
1200 default:
1201 tmp |= S_008C00_VC_ENABLE(1);
1202 break;
1203 }
1204 tmp |= S_008C00_EXPORT_SRC_C(1);
1205 tmp |= S_008C00_CS_PRIO(cs_prio);
1206 tmp |= S_008C00_LS_PRIO(ls_prio);
1207 tmp |= S_008C00_HS_PRIO(hs_prio);
1208 tmp |= S_008C00_PS_PRIO(ps_prio);
1209 tmp |= S_008C00_VS_PRIO(vs_prio);
1210 tmp |= S_008C00_GS_PRIO(gs_prio);
1211 tmp |= S_008C00_ES_PRIO(es_prio);
1212 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1213
1214 tmp = 0;
1215 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1216 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1217 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1218 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1219
1220 tmp = 0;
1221 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1222 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1223 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1224
1225 tmp = 0;
1226 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1227 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1228 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1229
1230 tmp = 0;
1231 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1232 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1233 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1234 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1235 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1236
1237 tmp = 0;
1238 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1239 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1240 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1241
1242 tmp = 0;
1243 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1244 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1245 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1246
1247 tmp = 0;
1248 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1249 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1250 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1251
1252 tmp = 0;
1253 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1254 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1255 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1256
1257 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1258 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1259
1260 // r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1261
1262 // r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1263 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1264 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1265
1266 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1267 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1268 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1269 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1270 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1271 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1272
1273 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1274 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1275 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1276 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1277
1278 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1279 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1280 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1281 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1282 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1283 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1284 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1285 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1286 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1287 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1288 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1289 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1290 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1291 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1292 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1293 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1294 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1295 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1296
1297 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1298 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1299 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1300 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1301 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1302 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1303 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1304 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1305 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1306 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1307 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1308 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1309 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1310 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1311 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1312 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1313 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1314 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1315 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1316 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1317 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1318 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1319 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1320 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1321 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1322 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1323 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1324 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1325 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1326 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1327 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1328 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1329
1330 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1331 0x0, 0xFFFFFFFF, NULL);
1332
1333 r600_context_pipe_state_set(&rctx->ctx, rstate);
1334 }
1335
1336 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
1337 void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
1338 {
1339 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1340 struct r600_pipe_state *rstate;
1341 struct r600_resource *rbuffer;
1342 unsigned i, j, offset, format, prim;
1343 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
1344 struct pipe_vertex_buffer *vertex_buffer;
1345 struct r600_draw rdraw;
1346 struct r600_pipe_state vgt;
1347 struct r600_drawl draw;
1348
1349 assert(info->index_bias == 0);
1350
1351 if (rctx->any_user_vbs) {
1352 r600_upload_user_buffers2(rctx);
1353 rctx->any_user_vbs = FALSE;
1354 }
1355
1356 memset(&draw, 0, sizeof(struct r600_drawl));
1357 draw.mode = info->mode;
1358 draw.start = info->start;
1359 draw.count = info->count;
1360 if (info->indexed && rctx->index_buffer.buffer) {
1361 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
1362 draw.min_index = info->min_index;
1363 draw.max_index = info->max_index;
1364 draw.index_bias = info->index_bias;
1365
1366 r600_translate_index_buffer2(rctx, &rctx->index_buffer.buffer,
1367 &rctx->index_buffer.index_size,
1368 &draw.start,
1369 info->count);
1370
1371 draw.index_size = rctx->index_buffer.index_size;
1372 draw.index_buffer = rctx->index_buffer.buffer;
1373 draw.index_buffer_offset = draw.start * draw.index_size;
1374 draw.start = 0;
1375 r600_upload_index_buffer2(rctx, &draw);
1376 } else {
1377 draw.index_size = 0;
1378 draw.index_buffer = NULL;
1379 draw.min_index = info->min_index;
1380 draw.max_index = info->max_index;
1381 draw.index_bias = info->start;
1382 }
1383
1384 switch (draw.index_size) {
1385 case 2:
1386 vgt_draw_initiator = 0;
1387 vgt_dma_index_type = 0;
1388 break;
1389 case 4:
1390 vgt_draw_initiator = 0;
1391 vgt_dma_index_type = 1;
1392 break;
1393 case 0:
1394 vgt_draw_initiator = 2;
1395 vgt_dma_index_type = 0;
1396 break;
1397 default:
1398 R600_ERR("unsupported index size %d\n", draw.index_size);
1399 return;
1400 }
1401 if (r600_conv_pipe_prim(draw.mode, &prim))
1402 return;
1403
1404 /* rebuild vertex shader if input format changed */
1405 if (r600_pipe_shader_update2(&rctx->context, rctx->vs_shader))
1406 return;
1407 if (r600_pipe_shader_update2(&rctx->context, rctx->ps_shader))
1408 return;
1409
1410 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
1411 unsigned num_format = 0, format_comp = 0;
1412
1413 rstate = &rctx->vs_resource[i];
1414 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
1415 vertex_buffer = &rctx->vertex_buffer[j];
1416 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
1417 offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
1418 format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
1419 rstate->id = R600_PIPE_STATE_RESOURCE;
1420 rstate->nregs = 0;
1421
1422 r600_translate_vertex_num_format(rctx->vertex_elements->elements[i].src_format, &num_format, &format_comp);
1423 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
1424 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
1425 r600_pipe_state_add_reg(rstate,
1426 R_030008_RESOURCE0_WORD2,
1427 S_030008_STRIDE(vertex_buffer->stride) |
1428 S_030008_DATA_FORMAT(format) |
1429 S_030008_NUM_FORMAT_ALL(num_format) |
1430 S_030008_FORMAT_COMP_ALL(format_comp),
1431 0xFFFFFFFF, NULL);
1432 r600_pipe_state_add_reg(rstate,
1433 R_03000C_RESOURCE0_WORD3,
1434 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1435 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1436 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1437 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W),
1438 0xFFFFFFFF, NULL);
1439 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
1440 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
1441 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x00000000, 0xFFFFFFFF, NULL);
1442 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7, 0xC0000000, 0xFFFFFFFF, NULL);
1443 evergreen_vs_resource_set(&rctx->ctx, rstate, i);
1444 }
1445
1446 mask = 0;
1447 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
1448 mask |= (0xF << (i * 4));
1449 }
1450
1451 vgt.id = R600_PIPE_STATE_VGT;
1452 vgt.nregs = 0;
1453 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
1454 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw.index_bias, 0xFFFFFFFF, NULL);
1455 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
1456 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw.max_index, 0xFFFFFFFF, NULL);
1457 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw.min_index, 0xFFFFFFFF, NULL);
1458
1459 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1460 float offset_units = rctx->rasterizer->offset_units;
1461 unsigned offset_db_fmt_cntl = 0, depth;
1462
1463 switch (rctx->framebuffer.zsbuf->texture->format) {
1464 case PIPE_FORMAT_Z24X8_UNORM:
1465 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1466 depth = -24;
1467 offset_units *= 2.0f;
1468 break;
1469 case PIPE_FORMAT_Z32_FLOAT:
1470 depth = -23;
1471 offset_units *= 1.0f;
1472 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1473 break;
1474 case PIPE_FORMAT_Z16_UNORM:
1475 depth = -16;
1476 offset_units *= 4.0f;
1477 break;
1478 default:
1479 return;
1480 }
1481 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1482 r600_pipe_state_add_reg(&vgt,
1483 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1484 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1485 r600_pipe_state_add_reg(&vgt,
1486 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1487 fui(offset_units), 0xFFFFFFFF, NULL);
1488 r600_pipe_state_add_reg(&vgt,
1489 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1490 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1491 r600_pipe_state_add_reg(&vgt,
1492 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1493 fui(offset_units), 0xFFFFFFFF, NULL);
1494 r600_pipe_state_add_reg(&vgt,
1495 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1496 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1497 }
1498 r600_context_pipe_state_set(&rctx->ctx, &vgt);
1499
1500 rdraw.vgt_num_indices = draw.count;
1501 rdraw.vgt_num_instances = 1;
1502 rdraw.vgt_index_type = vgt_dma_index_type;
1503 rdraw.vgt_draw_initiator = vgt_draw_initiator;
1504 rdraw.indices = NULL;
1505 if (draw.index_buffer) {
1506 rbuffer = (struct r600_resource*)draw.index_buffer;
1507 rdraw.indices = rbuffer->bo;
1508 rdraw.indices_bo_offset = draw.index_buffer_offset;
1509 }
1510 evergreen_context_draw(&rctx->ctx, &rdraw);
1511 }
1512
1513 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1514 {
1515 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1516 struct r600_pipe_state *rstate = &shader->rstate;
1517 struct r600_shader *rshader = &shader->shader;
1518 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
1519 boolean have_pos = FALSE, have_face = FALSE;
1520
1521 /* clear previous register */
1522 rstate->nregs = 0;
1523
1524 for (i = 0; i < rshader->ninput; i++) {
1525 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index2(&rctx->vs_shader->shader, rshader, i));
1526 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1527 have_pos = TRUE;
1528 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
1529 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
1530 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
1531 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
1532 }
1533 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1534 have_face = TRUE;
1535 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
1536 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
1537 tmp |= S_028644_PT_SPRITE_TEX(1);
1538 }
1539 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
1540 }
1541 for (i = 0; i < rshader->noutput; i++) {
1542 r600_pipe_state_add_reg(rstate,
1543 R_02880C_DB_SHADER_CONTROL,
1544 S_02880C_Z_EXPORT_ENABLE(1),
1545 S_02880C_Z_EXPORT_ENABLE(1), NULL);
1546 }
1547
1548 exports_ps = 0;
1549 num_cout = 0;
1550 for (i = 0; i < rshader->noutput; i++) {
1551 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1552 exports_ps |= 1;
1553 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1554 num_cout++;
1555 }
1556 }
1557 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1558 if (!exports_ps) {
1559 /* always at least export 1 component per pixel */
1560 exports_ps = 2;
1561 }
1562
1563 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
1564 S_0286CC_PERSP_GRADIENT_ENA(1);
1565 spi_input_z = 0;
1566 if (have_pos) {
1567 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1);
1568 spi_input_z |= 1;
1569 }
1570 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1571 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1572 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1573 S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
1574 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1575 r600_pipe_state_add_reg(rstate,
1576 R_028840_SQ_PGM_START_PS,
1577 0x00000000, 0xFFFFFFFF, shader->bo);
1578 r600_pipe_state_add_reg(rstate,
1579 R_028844_SQ_PGM_RESOURCES_PS,
1580 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1581 S_028844_PRIME_CACHE_ON_DRAW(1) |
1582 S_028844_STACK_SIZE(rshader->bc.nstack),
1583 0xFFFFFFFF, NULL);
1584 r600_pipe_state_add_reg(rstate,
1585 R_028848_SQ_PGM_RESOURCES_2_PS,
1586 0x0, 0xFFFFFFFF, NULL);
1587 r600_pipe_state_add_reg(rstate,
1588 R_02884C_SQ_PGM_EXPORTS_PS,
1589 exports_ps, 0xFFFFFFFF, NULL);
1590 r600_pipe_state_add_reg(rstate,
1591 R_0286E0_SPI_BARYC_CNTL,
1592 S_0286E0_PERSP_CENTROID_ENA(1) |
1593 S_0286E0_LINEAR_CENTROID_ENA(1),
1594 0xFFFFFFFF, NULL);
1595
1596 if (rshader->uses_kill) {
1597 /* only set some bits here, the other bits are set in the dsa state */
1598 r600_pipe_state_add_reg(rstate,
1599 R_02880C_DB_SHADER_CONTROL,
1600 S_02880C_KILL_ENABLE(1),
1601 S_02880C_KILL_ENABLE(1), NULL);
1602 }
1603 }
1604
1605 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1606 {
1607 struct r600_pipe_state *rstate = &shader->rstate;
1608 struct r600_shader *rshader = &shader->shader;
1609 unsigned spi_vs_out_id[10];
1610 unsigned i, tmp;
1611
1612 /* clear previous register */
1613 rstate->nregs = 0;
1614
1615 /* so far never got proper semantic id from tgsi */
1616 for (i = 0; i < 10; i++) {
1617 spi_vs_out_id[i] = 0;
1618 }
1619 for (i = 0; i < 32; i++) {
1620 tmp = i << ((i & 3) * 8);
1621 spi_vs_out_id[i / 4] |= tmp;
1622 }
1623 for (i = 0; i < 10; i++) {
1624 r600_pipe_state_add_reg(rstate,
1625 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1626 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1627 }
1628
1629 r600_pipe_state_add_reg(rstate,
1630 R_0286C4_SPI_VS_OUT_CONFIG,
1631 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1632 0xFFFFFFFF, NULL);
1633 r600_pipe_state_add_reg(rstate,
1634 R_028860_SQ_PGM_RESOURCES_VS,
1635 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1636 S_028860_STACK_SIZE(rshader->bc.nstack),
1637 0xFFFFFFFF, NULL);
1638 r600_pipe_state_add_reg(rstate,
1639 R_028864_SQ_PGM_RESOURCES_2_VS,
1640 0x0, 0xFFFFFFFF, NULL);
1641 r600_pipe_state_add_reg(rstate,
1642 R_0288A8_SQ_PGM_RESOURCES_FS,
1643 0x00000000, 0xFFFFFFFF, NULL);
1644 r600_pipe_state_add_reg(rstate,
1645 R_02885C_SQ_PGM_START_VS,
1646 0x00000000, 0xFFFFFFFF, shader->bo);
1647 r600_pipe_state_add_reg(rstate,
1648 R_0288A4_SQ_PGM_START_FS,
1649 0x00000000, 0xFFFFFFFF, shader->bo);
1650 }