2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
35 static INLINE
unsigned evergreen_array_mode(unsigned mode
)
38 case RADEON_SURF_MODE_LINEAR_ALIGNED
: return V_028C70_ARRAY_LINEAR_ALIGNED
;
40 case RADEON_SURF_MODE_1D
: return V_028C70_ARRAY_1D_TILED_THIN1
;
42 case RADEON_SURF_MODE_2D
: return V_028C70_ARRAY_2D_TILED_THIN1
;
44 case RADEON_SURF_MODE_LINEAR
: return V_028C70_ARRAY_LINEAR_GENERAL
;
48 static uint32_t eg_num_banks(uint32_t nbanks
)
64 static unsigned eg_tile_split(unsigned tile_split
)
67 case 64: tile_split
= 0; break;
68 case 128: tile_split
= 1; break;
69 case 256: tile_split
= 2; break;
70 case 512: tile_split
= 3; break;
72 case 1024: tile_split
= 4; break;
73 case 2048: tile_split
= 5; break;
74 case 4096: tile_split
= 6; break;
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect
)
81 switch (macro_tile_aspect
) {
83 case 1: macro_tile_aspect
= 0; break;
84 case 2: macro_tile_aspect
= 1; break;
85 case 4: macro_tile_aspect
= 2; break;
86 case 8: macro_tile_aspect
= 3; break;
88 return macro_tile_aspect
;
91 static unsigned eg_bank_wh(unsigned bankwh
)
95 case 1: bankwh
= 0; break;
96 case 2: bankwh
= 1; break;
97 case 4: bankwh
= 2; break;
98 case 8: bankwh
= 3; break;
103 static uint32_t r600_translate_blend_function(int blend_func
)
105 switch (blend_func
) {
107 return V_028780_COMB_DST_PLUS_SRC
;
108 case PIPE_BLEND_SUBTRACT
:
109 return V_028780_COMB_SRC_MINUS_DST
;
110 case PIPE_BLEND_REVERSE_SUBTRACT
:
111 return V_028780_COMB_DST_MINUS_SRC
;
113 return V_028780_COMB_MIN_DST_SRC
;
115 return V_028780_COMB_MAX_DST_SRC
;
117 R600_ERR("Unknown blend function %d\n", blend_func
);
124 static uint32_t r600_translate_blend_factor(int blend_fact
)
126 switch (blend_fact
) {
127 case PIPE_BLENDFACTOR_ONE
:
128 return V_028780_BLEND_ONE
;
129 case PIPE_BLENDFACTOR_SRC_COLOR
:
130 return V_028780_BLEND_SRC_COLOR
;
131 case PIPE_BLENDFACTOR_SRC_ALPHA
:
132 return V_028780_BLEND_SRC_ALPHA
;
133 case PIPE_BLENDFACTOR_DST_ALPHA
:
134 return V_028780_BLEND_DST_ALPHA
;
135 case PIPE_BLENDFACTOR_DST_COLOR
:
136 return V_028780_BLEND_DST_COLOR
;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
139 case PIPE_BLENDFACTOR_CONST_COLOR
:
140 return V_028780_BLEND_CONST_COLOR
;
141 case PIPE_BLENDFACTOR_CONST_ALPHA
:
142 return V_028780_BLEND_CONST_ALPHA
;
143 case PIPE_BLENDFACTOR_ZERO
:
144 return V_028780_BLEND_ZERO
;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR
;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA
;
157 case PIPE_BLENDFACTOR_SRC1_COLOR
:
158 return V_028780_BLEND_SRC1_COLOR
;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
160 return V_028780_BLEND_SRC1_ALPHA
;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
162 return V_028780_BLEND_INV_SRC1_COLOR
;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
164 return V_028780_BLEND_INV_SRC1_ALPHA
;
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
173 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
177 case PIPE_TEXTURE_1D
:
178 return V_030000_SQ_TEX_DIM_1D
;
179 case PIPE_TEXTURE_1D_ARRAY
:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
181 case PIPE_TEXTURE_2D
:
182 case PIPE_TEXTURE_RECT
:
183 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_MSAA
:
184 V_030000_SQ_TEX_DIM_2D
;
185 case PIPE_TEXTURE_2D_ARRAY
:
186 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
187 V_030000_SQ_TEX_DIM_2D_ARRAY
;
188 case PIPE_TEXTURE_3D
:
189 return V_030000_SQ_TEX_DIM_3D
;
190 case PIPE_TEXTURE_CUBE
:
191 case PIPE_TEXTURE_CUBE_ARRAY
:
192 return V_030000_SQ_TEX_DIM_CUBEMAP
;
196 static uint32_t r600_translate_dbformat(enum pipe_format format
)
199 case PIPE_FORMAT_Z16_UNORM
:
200 return V_028040_Z_16
;
201 case PIPE_FORMAT_Z24X8_UNORM
:
202 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
203 case PIPE_FORMAT_X8Z24_UNORM
:
204 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
205 return V_028040_Z_24
;
206 case PIPE_FORMAT_Z32_FLOAT
:
207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
208 return V_028040_Z_32_FLOAT
;
214 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
216 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip
, enum pipe_format format
)
221 return r600_translate_colorformat(chip
, format
) != ~0U &&
222 r600_translate_colorswap(format
) != ~0U;
225 static bool r600_is_zs_format_supported(enum pipe_format format
)
227 return r600_translate_dbformat(format
) != ~0U;
230 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
231 enum pipe_format format
,
232 enum pipe_texture_target target
,
233 unsigned sample_count
,
236 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
239 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
240 R600_ERR("r600: unsupported texture type %d\n", target
);
244 if (!util_format_is_supported(format
, usage
))
247 if (sample_count
> 1) {
248 if (!rscreen
->has_msaa
)
251 switch (sample_count
) {
261 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
262 if (target
== PIPE_BUFFER
) {
263 if (r600_is_vertex_format_supported(format
))
264 retval
|= PIPE_BIND_SAMPLER_VIEW
;
266 if (r600_is_sampler_format_supported(screen
, format
))
267 retval
|= PIPE_BIND_SAMPLER_VIEW
;
271 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
272 PIPE_BIND_DISPLAY_TARGET
|
274 PIPE_BIND_SHARED
)) &&
275 r600_is_colorbuffer_format_supported(rscreen
->b
.chip_class
, format
)) {
277 (PIPE_BIND_RENDER_TARGET
|
278 PIPE_BIND_DISPLAY_TARGET
|
283 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
284 r600_is_zs_format_supported(format
)) {
285 retval
|= PIPE_BIND_DEPTH_STENCIL
;
288 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
289 r600_is_vertex_format_supported(format
)) {
290 retval
|= PIPE_BIND_VERTEX_BUFFER
;
293 if (usage
& PIPE_BIND_TRANSFER_READ
)
294 retval
|= PIPE_BIND_TRANSFER_READ
;
295 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
296 retval
|= PIPE_BIND_TRANSFER_WRITE
;
298 return retval
== usage
;
301 static void *evergreen_create_blend_state_mode(struct pipe_context
*ctx
,
302 const struct pipe_blend_state
*state
, int mode
)
304 uint32_t color_control
= 0, target_mask
= 0;
305 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
311 r600_init_command_buffer(&blend
->buffer
, 20);
312 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
314 if (state
->logicop_enable
) {
315 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
317 color_control
|= (0xcc << 16);
319 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
320 if (state
->independent_blend_enable
) {
321 for (int i
= 0; i
< 8; i
++) {
322 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
325 for (int i
= 0; i
< 8; i
++) {
326 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
330 /* only have dual source on MRT0 */
331 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
332 blend
->cb_target_mask
= target_mask
;
333 blend
->alpha_to_one
= state
->alpha_to_one
;
336 color_control
|= S_028808_MODE(mode
);
338 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
341 r600_store_context_reg(&blend
->buffer
, R_028808_CB_COLOR_CONTROL
, color_control
);
342 r600_store_context_reg(&blend
->buffer
, R_028B70_DB_ALPHA_TO_MASK
,
343 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
344 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
345 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
346 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
347 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
348 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
350 /* Copy over the dwords set so far into buffer_no_blend.
351 * Only the CB_BLENDi_CONTROL registers must be set after this. */
352 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
353 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
355 for (int i
= 0; i
< 8; i
++) {
356 /* state->rt entries > 0 only written if independent blending */
357 const int j
= state
->independent_blend_enable
? i
: 0;
359 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
360 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
361 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
362 unsigned eqA
= state
->rt
[j
].alpha_func
;
363 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
364 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
367 r600_store_value(&blend
->buffer_no_blend
, 0);
369 if (!state
->rt
[j
].blend_enable
) {
370 r600_store_value(&blend
->buffer
, 0);
374 bc
|= S_028780_BLEND_CONTROL_ENABLE(1);
375 bc
|= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
376 bc
|= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
377 bc
|= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
379 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
380 bc
|= S_028780_SEPARATE_ALPHA_BLEND(1);
381 bc
|= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
382 bc
|= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
383 bc
|= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
385 r600_store_value(&blend
->buffer
, bc
);
390 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
391 const struct pipe_blend_state
*state
)
394 return evergreen_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
397 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
398 const struct pipe_depth_stencil_alpha_state
*state
)
400 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
401 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
407 r600_init_command_buffer(&dsa
->buffer
, 3);
409 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
410 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
411 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
412 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
413 dsa
->zwritemask
= state
->depth
.writemask
;
415 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
416 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
417 S_028800_ZFUNC(state
->depth
.func
);
420 if (state
->stencil
[0].enabled
) {
421 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
422 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
423 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
424 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
425 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
427 if (state
->stencil
[1].enabled
) {
428 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
429 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
430 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
431 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
432 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
437 alpha_test_control
= 0;
439 if (state
->alpha
.enabled
) {
440 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
441 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
442 alpha_ref
= fui(state
->alpha
.ref_value
);
444 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
445 dsa
->alpha_ref
= alpha_ref
;
448 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
452 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
453 const struct pipe_rasterizer_state
*state
)
455 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
456 unsigned tmp
, spi_interp
;
457 float psize_min
, psize_max
;
458 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
464 r600_init_command_buffer(&rs
->buffer
, 30);
466 rs
->flatshade
= state
->flatshade
;
467 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
468 rs
->two_side
= state
->light_twoside
;
469 rs
->clip_plane_enable
= state
->clip_plane_enable
;
470 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
471 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
472 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
473 rs
->pa_cl_clip_cntl
=
474 S_028810_PS_UCP_MODE(3) |
475 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
476 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
477 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
478 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
);
479 rs
->multisample_enable
= state
->multisample
;
482 rs
->offset_units
= state
->offset_units
;
483 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
484 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
486 if (state
->point_size_per_vertex
) {
487 psize_min
= util_get_min_point_size(state
);
490 /* Force the point size to be as if the vertex output was disabled. */
491 psize_min
= state
->point_size
;
492 psize_max
= state
->point_size
;
495 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
496 if (state
->sprite_coord_enable
) {
497 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
498 S_0286D4_PNT_SPRITE_OVRD_X(2) |
499 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
500 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
501 S_0286D4_PNT_SPRITE_OVRD_W(1);
502 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
503 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
507 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
508 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
509 tmp
= r600_pack_float_12p4(state
->point_size
/2);
510 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
511 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
512 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
513 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
514 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
515 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
516 S_028A08_WIDTH((unsigned)(state
->line_width
* 8)));
518 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
519 r600_store_context_reg(&rs
->buffer
, R_028A48_PA_SC_MODE_CNTL_0
,
520 S_028A48_MSAA_ENABLE(state
->multisample
) |
521 S_028A48_VPORT_SCISSOR_ENABLE(state
->scissor
) |
522 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
));
524 if (rctx
->b
.chip_class
== CAYMAN
) {
525 r600_store_context_reg(&rs
->buffer
, CM_R_028BE4_PA_SU_VTX_CNTL
,
526 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
527 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
529 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
530 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
531 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
534 r600_store_context_reg(&rs
->buffer
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
535 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
,
536 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
537 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
538 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
539 S_028814_FACE(!state
->front_ccw
) |
540 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
541 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
542 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
543 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
544 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
545 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
546 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
550 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
551 const struct pipe_sampler_state
*state
)
553 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
554 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
560 ss
->border_color_use
= sampler_state_needs_border_color(state
);
562 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
563 ss
->tex_sampler_words
[0] =
564 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
565 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
566 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
567 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
568 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
569 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
570 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
571 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
572 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
573 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
574 ss
->tex_sampler_words
[1] =
575 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
576 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8));
577 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
578 ss
->tex_sampler_words
[2] =
579 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
580 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
583 if (ss
->border_color_use
) {
584 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
589 static struct pipe_sampler_view
*
590 texture_buffer_sampler_view(struct r600_pipe_sampler_view
*view
,
591 unsigned width0
, unsigned height0
)
594 struct pipe_context
*ctx
= view
->base
.context
;
595 struct r600_texture
*tmp
= (struct r600_texture
*)view
->base
.texture
;
597 int stride
= util_format_get_blocksize(view
->base
.format
);
598 unsigned format
, num_format
, format_comp
, endian
;
599 unsigned swizzle_res
;
600 unsigned char swizzle
[4];
601 const struct util_format_description
*desc
;
602 unsigned offset
= view
->base
.u
.buf
.first_element
* stride
;
603 unsigned size
= (view
->base
.u
.buf
.last_element
- view
->base
.u
.buf
.first_element
+ 1) * stride
;
605 swizzle
[0] = view
->base
.swizzle_r
;
606 swizzle
[1] = view
->base
.swizzle_g
;
607 swizzle
[2] = view
->base
.swizzle_b
;
608 swizzle
[3] = view
->base
.swizzle_a
;
610 r600_vertex_data_type(view
->base
.format
,
611 &format
, &num_format
, &format_comp
,
614 desc
= util_format_description(view
->base
.format
);
616 swizzle_res
= r600_get_swizzle_combined(desc
->swizzle
, swizzle
, TRUE
);
618 va
= r600_resource_va(ctx
->screen
, view
->base
.texture
) + offset
;
619 view
->tex_resource
= &tmp
->resource
;
621 view
->skip_mip_address_reloc
= true;
622 view
->tex_resource_words
[0] = va
;
623 view
->tex_resource_words
[1] = size
- 1;
624 view
->tex_resource_words
[2] = S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
625 S_030008_STRIDE(stride
) |
626 S_030008_DATA_FORMAT(format
) |
627 S_030008_NUM_FORMAT_ALL(num_format
) |
628 S_030008_FORMAT_COMP_ALL(format_comp
) |
629 S_030008_SRF_MODE_ALL(1) |
630 S_030008_ENDIAN_SWAP(endian
);
631 view
->tex_resource_words
[3] = swizzle_res
;
633 * in theory dword 4 is for number of elements, for use with resinfo,
634 * but it seems to utterly fail to work, the amd gpu shader analyser
635 * uses a const buffer to store the element sizes for buffer txq
637 view
->tex_resource_words
[4] = 0;
638 view
->tex_resource_words
[5] = view
->tex_resource_words
[6] = 0;
639 view
->tex_resource_words
[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
);
643 struct pipe_sampler_view
*
644 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
645 struct pipe_resource
*texture
,
646 const struct pipe_sampler_view
*state
,
647 unsigned width0
, unsigned height0
,
648 unsigned force_level
)
650 struct r600_screen
*rscreen
= (struct r600_screen
*)ctx
->screen
;
651 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
652 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
653 unsigned format
, endian
;
654 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
655 unsigned char swizzle
[4], array_mode
= 0, non_disp_tiling
= 0;
656 unsigned height
, depth
, width
;
657 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
, fmask_bankh
;
658 enum pipe_format pipe_format
= state
->format
;
659 struct radeon_surface_level
*surflevel
;
660 unsigned base_level
, first_level
, last_level
;
666 /* initialize base object */
668 view
->base
.texture
= NULL
;
669 pipe_reference(NULL
, &texture
->reference
);
670 view
->base
.texture
= texture
;
671 view
->base
.reference
.count
= 1;
672 view
->base
.context
= ctx
;
674 if (texture
->target
== PIPE_BUFFER
)
675 return texture_buffer_sampler_view(view
, width0
, height0
);
677 swizzle
[0] = state
->swizzle_r
;
678 swizzle
[1] = state
->swizzle_g
;
679 swizzle
[2] = state
->swizzle_b
;
680 swizzle
[3] = state
->swizzle_a
;
682 tile_split
= tmp
->surface
.tile_split
;
683 surflevel
= tmp
->surface
.level
;
685 /* Texturing with separate depth and stencil. */
686 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
687 switch (pipe_format
) {
688 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
689 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
691 case PIPE_FORMAT_X8Z24_UNORM
:
692 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
693 /* Z24 is always stored like this. */
694 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
696 case PIPE_FORMAT_X24S8_UINT
:
697 case PIPE_FORMAT_S8X24_UINT
:
698 case PIPE_FORMAT_X32_S8X24_UINT
:
699 pipe_format
= PIPE_FORMAT_S8_UINT
;
700 tile_split
= tmp
->surface
.stencil_tile_split
;
701 surflevel
= tmp
->surface
.stencil_level
;
707 format
= r600_translate_texformat(ctx
->screen
, pipe_format
,
709 &word4
, &yuv_format
);
710 assert(format
!= ~0);
716 endian
= r600_colorformat_endian_swap(format
);
719 first_level
= state
->u
.tex
.first_level
;
720 last_level
= state
->u
.tex
.last_level
;
723 depth
= texture
->depth0
;
726 base_level
= force_level
;
729 width
= u_minify(width
, force_level
);
730 height
= u_minify(height
, force_level
);
731 depth
= u_minify(depth
, force_level
);
734 pitch
= surflevel
[base_level
].nblk_x
* util_format_get_blockwidth(pipe_format
);
735 non_disp_tiling
= tmp
->non_disp_tiling
;
737 switch (surflevel
[base_level
].mode
) {
738 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
739 array_mode
= V_028C70_ARRAY_LINEAR_ALIGNED
;
741 case RADEON_SURF_MODE_2D
:
742 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
744 case RADEON_SURF_MODE_1D
:
745 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
747 case RADEON_SURF_MODE_LINEAR
:
749 array_mode
= V_028C70_ARRAY_LINEAR_GENERAL
;
752 macro_aspect
= tmp
->surface
.mtilea
;
753 bankw
= tmp
->surface
.bankw
;
754 bankh
= tmp
->surface
.bankh
;
755 tile_split
= eg_tile_split(tile_split
);
756 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
757 bankw
= eg_bank_wh(bankw
);
758 bankh
= eg_bank_wh(bankh
);
759 fmask_bankh
= eg_bank_wh(tmp
->fmask
.bank_height
);
761 /* 128 bit formats require tile type = 1 */
762 if (rscreen
->b
.chip_class
== CAYMAN
) {
763 if (util_format_get_blocksize(pipe_format
) >= 16)
766 nbanks
= eg_num_banks(rscreen
->b
.tiling_info
.num_banks
);
768 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
770 depth
= texture
->array_size
;
771 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
772 depth
= texture
->array_size
;
773 } else if (texture
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
774 depth
= texture
->array_size
/ 6;
776 va
= r600_resource_va(ctx
->screen
, texture
);
778 view
->tex_resource
= &tmp
->resource
;
779 view
->tex_resource_words
[0] = (S_030000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
780 S_030000_PITCH((pitch
/ 8) - 1) |
781 S_030000_TEX_WIDTH(width
- 1));
782 if (rscreen
->b
.chip_class
== CAYMAN
)
783 view
->tex_resource_words
[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
785 view
->tex_resource_words
[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
786 view
->tex_resource_words
[1] = (S_030004_TEX_HEIGHT(height
- 1) |
787 S_030004_TEX_DEPTH(depth
- 1) |
788 S_030004_ARRAY_MODE(array_mode
));
789 view
->tex_resource_words
[2] = (surflevel
[base_level
].offset
+ va
) >> 8;
791 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
792 if (texture
->nr_samples
> 1 && rscreen
->has_compressed_msaa_texturing
) {
794 /* disable FMASK (0 = disabled) */
795 view
->tex_resource_words
[3] = 0;
796 view
->skip_mip_address_reloc
= true;
798 /* FMASK should be in MIP_ADDRESS for multisample textures */
799 view
->tex_resource_words
[3] = (tmp
->fmask
.offset
+ va
) >> 8;
801 } else if (last_level
&& texture
->nr_samples
<= 1) {
802 view
->tex_resource_words
[3] = (surflevel
[1].offset
+ va
) >> 8;
804 view
->tex_resource_words
[3] = (surflevel
[base_level
].offset
+ va
) >> 8;
807 view
->tex_resource_words
[4] = (word4
|
808 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
809 S_030010_ENDIAN_SWAP(endian
));
810 view
->tex_resource_words
[5] = S_030014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
811 S_030014_LAST_ARRAY(state
->u
.tex
.last_layer
);
812 view
->tex_resource_words
[6] = S_030018_TILE_SPLIT(tile_split
);
814 if (texture
->nr_samples
> 1) {
815 unsigned log_samples
= util_logbase2(texture
->nr_samples
);
816 if (rscreen
->b
.chip_class
== CAYMAN
) {
817 view
->tex_resource_words
[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples
);
819 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
820 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(log_samples
);
821 view
->tex_resource_words
[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh
);
823 view
->tex_resource_words
[4] |= S_030010_BASE_LEVEL(first_level
);
824 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(last_level
);
825 /* aniso max 16 samples */
826 view
->tex_resource_words
[6] |= S_030018_MAX_ANISO(4);
829 view
->tex_resource_words
[7] = S_03001C_DATA_FORMAT(format
) |
830 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
) |
831 S_03001C_BANK_WIDTH(bankw
) |
832 S_03001C_BANK_HEIGHT(bankh
) |
833 S_03001C_MACRO_TILE_ASPECT(macro_aspect
) |
834 S_03001C_NUM_BANKS(nbanks
) |
835 S_03001C_DEPTH_SAMPLE_ORDER(tmp
->is_depth
&& !tmp
->is_flushing_texture
);
839 static struct pipe_sampler_view
*
840 evergreen_create_sampler_view(struct pipe_context
*ctx
,
841 struct pipe_resource
*tex
,
842 const struct pipe_sampler_view
*state
)
844 return evergreen_create_sampler_view_custom(ctx
, tex
, state
,
845 tex
->width0
, tex
->height0
, 0);
848 static void evergreen_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
850 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
851 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
853 r600_write_context_reg_seq(cs
, R_0285BC_PA_CL_UCP0_X
, 6*4);
854 radeon_emit_array(cs
, (unsigned*)state
, 6*4);
857 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
858 const struct pipe_poly_stipple
*state
)
862 static void evergreen_get_scissor_rect(struct r600_context
*rctx
,
863 unsigned tl_x
, unsigned tl_y
, unsigned br_x
, unsigned br_y
,
864 uint32_t *tl
, uint32_t *br
)
866 /* EG hw workaround */
872 /* cayman hw workaround */
873 if (rctx
->b
.chip_class
== CAYMAN
) {
874 if (br_x
== 1 && br_y
== 1)
878 *tl
= S_028240_TL_X(tl_x
) | S_028240_TL_Y(tl_y
);
879 *br
= S_028244_BR_X(br_x
) | S_028244_BR_Y(br_y
);
882 static void evergreen_set_scissor_states(struct pipe_context
*ctx
,
884 unsigned num_scissors
,
885 const struct pipe_scissor_state
*state
)
887 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
890 for (i
= start_slot
; i
< start_slot
+ num_scissors
; i
++) {
891 rctx
->scissor
[i
].scissor
= state
[i
- start_slot
];
892 rctx
->scissor
[i
].atom
.dirty
= true;
896 static void evergreen_emit_scissor_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
898 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
899 struct r600_scissor_state
*rstate
= (struct r600_scissor_state
*)atom
;
900 struct pipe_scissor_state
*state
= &rstate
->scissor
;
901 unsigned offset
= rstate
->idx
* 4 * 2;
904 evergreen_get_scissor_rect(rctx
, state
->minx
, state
->miny
, state
->maxx
, state
->maxy
, &tl
, &br
);
906 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+ offset
, 2);
912 * This function intializes the CB* register values for RATs. It is meant
913 * to be used for 1D aligned buffers that do not have an associated
916 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
917 struct r600_surface
*surf
)
919 struct pipe_resource
*pipe_buffer
= surf
->base
.texture
;
920 unsigned format
= r600_translate_colorformat(rctx
->b
.chip_class
,
922 unsigned endian
= r600_colorformat_endian_swap(format
);
923 unsigned swap
= r600_translate_colorswap(surf
->base
.format
);
924 unsigned block_size
=
925 align(util_format_get_blocksize(pipe_buffer
->format
), 4);
926 unsigned pitch_alignment
=
927 MAX2(64, rctx
->screen
->b
.tiling_info
.group_bytes
/ block_size
);
928 unsigned pitch
= align(pipe_buffer
->width0
, pitch_alignment
);
930 /* XXX: This is copied from evergreen_init_color_surface(). I don't
931 * know why this is necessary.
933 if (pipe_buffer
->usage
== PIPE_USAGE_STAGING
) {
934 endian
= ENDIAN_NONE
;
937 surf
->cb_color_base
=
938 r600_resource_va(rctx
->b
.b
.screen
, pipe_buffer
) >> 8;
940 surf
->cb_color_pitch
= (pitch
/ 8) - 1;
942 surf
->cb_color_slice
= 0;
944 surf
->cb_color_view
= 0;
946 surf
->cb_color_info
=
947 S_028C70_ENDIAN(endian
)
948 | S_028C70_FORMAT(format
)
949 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
)
950 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT
)
951 | S_028C70_COMP_SWAP(swap
)
952 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
953 * are using NUMBER_UINT */
957 surf
->cb_color_attrib
= S_028C74_NON_DISP_TILING_ORDER(1);
959 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
961 surf
->cb_color_dim
= pipe_buffer
->width0
;
963 /* Set the buffer range the GPU will have access to: */
964 util_range_add(&r600_resource(pipe_buffer
)->valid_buffer_range
,
965 0, pipe_buffer
->width0
);
967 surf
->cb_color_fmask
= surf
->cb_color_base
;
968 surf
->cb_color_fmask_slice
= 0;
971 void evergreen_init_color_surface(struct r600_context
*rctx
,
972 struct r600_surface
*surf
)
974 struct r600_screen
*rscreen
= rctx
->screen
;
975 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
976 struct pipe_resource
*pipe_tex
= surf
->base
.texture
;
977 unsigned level
= surf
->base
.u
.tex
.level
;
978 unsigned pitch
, slice
;
979 unsigned color_info
, color_attrib
, color_dim
= 0, color_view
;
980 unsigned format
, swap
, ntype
, endian
;
981 uint64_t offset
, base_offset
;
982 unsigned non_disp_tiling
, macro_aspect
, tile_split
, bankh
, bankw
, fmask_bankh
, nbanks
;
983 const struct util_format_description
*desc
;
985 bool blend_clamp
= 0, blend_bypass
= 0;
987 offset
= rtex
->surface
.level
[level
].offset
;
988 if (rtex
->surface
.level
[level
].mode
== RADEON_SURF_MODE_LINEAR
) {
989 assert(surf
->base
.u
.tex
.first_layer
== surf
->base
.u
.tex
.last_layer
);
990 offset
+= rtex
->surface
.level
[level
].slice_size
*
991 surf
->base
.u
.tex
.first_layer
;
994 color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
995 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
997 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
998 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1003 switch (rtex
->surface
.level
[level
].mode
) {
1004 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1005 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1006 non_disp_tiling
= 1;
1008 case RADEON_SURF_MODE_1D
:
1009 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1
);
1010 non_disp_tiling
= rtex
->non_disp_tiling
;
1012 case RADEON_SURF_MODE_2D
:
1013 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1
);
1014 non_disp_tiling
= rtex
->non_disp_tiling
;
1016 case RADEON_SURF_MODE_LINEAR
:
1018 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL
);
1019 non_disp_tiling
= 1;
1022 tile_split
= rtex
->surface
.tile_split
;
1023 macro_aspect
= rtex
->surface
.mtilea
;
1024 bankw
= rtex
->surface
.bankw
;
1025 bankh
= rtex
->surface
.bankh
;
1026 fmask_bankh
= rtex
->fmask
.bank_height
;
1027 tile_split
= eg_tile_split(tile_split
);
1028 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1029 bankw
= eg_bank_wh(bankw
);
1030 bankh
= eg_bank_wh(bankh
);
1031 fmask_bankh
= eg_bank_wh(fmask_bankh
);
1033 /* 128 bit formats require tile type = 1 */
1034 if (rscreen
->b
.chip_class
== CAYMAN
) {
1035 if (util_format_get_blocksize(surf
->base
.format
) >= 16)
1036 non_disp_tiling
= 1;
1038 nbanks
= eg_num_banks(rscreen
->b
.tiling_info
.num_banks
);
1039 desc
= util_format_description(surf
->base
.format
);
1040 for (i
= 0; i
< 4; i
++) {
1041 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1046 color_attrib
= S_028C74_TILE_SPLIT(tile_split
)|
1047 S_028C74_NUM_BANKS(nbanks
) |
1048 S_028C74_BANK_WIDTH(bankw
) |
1049 S_028C74_BANK_HEIGHT(bankh
) |
1050 S_028C74_MACRO_TILE_ASPECT(macro_aspect
) |
1051 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling
) |
1052 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
1054 if (rctx
->b
.chip_class
== CAYMAN
) {
1055 color_attrib
|= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] ==
1056 UTIL_FORMAT_SWIZZLE_1
);
1058 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1059 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
1060 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1061 S_028C74_NUM_FRAGMENTS(log_samples
);
1065 ntype
= V_028C70_NUMBER_UNORM
;
1066 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1067 ntype
= V_028C70_NUMBER_SRGB
;
1068 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1069 if (desc
->channel
[i
].normalized
)
1070 ntype
= V_028C70_NUMBER_SNORM
;
1071 else if (desc
->channel
[i
].pure_integer
)
1072 ntype
= V_028C70_NUMBER_SINT
;
1073 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1074 if (desc
->channel
[i
].normalized
)
1075 ntype
= V_028C70_NUMBER_UNORM
;
1076 else if (desc
->channel
[i
].pure_integer
)
1077 ntype
= V_028C70_NUMBER_UINT
;
1080 format
= r600_translate_colorformat(rctx
->b
.chip_class
, surf
->base
.format
);
1081 assert(format
!= ~0);
1083 swap
= r600_translate_colorswap(surf
->base
.format
);
1086 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1087 endian
= ENDIAN_NONE
;
1089 endian
= r600_colorformat_endian_swap(format
);
1092 /* blend clamp should be set for all NORM/SRGB types */
1093 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
1094 ntype
== V_028C70_NUMBER_SRGB
)
1097 /* set blend bypass according to docs if SINT/UINT or
1098 8/24 COLOR variants */
1099 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1100 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1101 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1106 surf
->alphatest_bypass
= ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
;
1108 color_info
|= S_028C70_FORMAT(format
) |
1109 S_028C70_COMP_SWAP(swap
) |
1110 S_028C70_BLEND_CLAMP(blend_clamp
) |
1111 S_028C70_BLEND_BYPASS(blend_bypass
) |
1112 S_028C70_NUMBER_TYPE(ntype
) |
1113 S_028C70_ENDIAN(endian
);
1115 /* EXPORT_NORM is an optimzation that can be enabled for better
1116 * performance in certain cases.
1117 * EXPORT_NORM can be enabled if:
1118 * - 11-bit or smaller UNORM/SNORM/SRGB
1119 * - 16-bit or smaller FLOAT
1121 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1122 ((desc
->channel
[i
].size
< 12 &&
1123 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1124 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
1125 (desc
->channel
[i
].size
< 17 &&
1126 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1127 color_info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
1128 surf
->export_16bpc
= true;
1131 if (rtex
->fmask
.size
) {
1132 color_info
|= S_028C70_COMPRESSION(1);
1135 base_offset
= r600_resource_va(rctx
->b
.b
.screen
, pipe_tex
);
1137 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1138 surf
->cb_color_base
= (base_offset
+ offset
) >> 8;
1139 surf
->cb_color_dim
= color_dim
;
1140 surf
->cb_color_info
= color_info
;
1141 surf
->cb_color_pitch
= S_028C64_PITCH_TILE_MAX(pitch
);
1142 surf
->cb_color_slice
= S_028C68_SLICE_TILE_MAX(slice
);
1143 surf
->cb_color_view
= color_view
;
1144 surf
->cb_color_attrib
= color_attrib
;
1145 if (rtex
->fmask
.size
) {
1146 surf
->cb_color_fmask
= (base_offset
+ rtex
->fmask
.offset
) >> 8;
1148 surf
->cb_color_fmask
= surf
->cb_color_base
;
1150 surf
->cb_color_fmask_slice
= S_028C88_TILE_MAX(rtex
->fmask
.slice_tile_max
);
1152 surf
->color_initialized
= true;
1155 static void evergreen_init_depth_surface(struct r600_context
*rctx
,
1156 struct r600_surface
*surf
)
1158 struct r600_screen
*rscreen
= rctx
->screen
;
1159 struct pipe_screen
*screen
= &rscreen
->b
.b
;
1160 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1162 unsigned level
, pitch
, slice
, format
, array_mode
;
1163 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1165 level
= surf
->base
.u
.tex
.level
;
1166 format
= r600_translate_dbformat(surf
->base
.format
);
1167 assert(format
!= ~0);
1169 offset
= r600_resource_va(screen
, surf
->base
.texture
);
1170 offset
+= rtex
->surface
.level
[level
].offset
;
1171 pitch
= (rtex
->surface
.level
[level
].nblk_x
/ 8) - 1;
1172 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1176 switch (rtex
->surface
.level
[level
].mode
) {
1177 case RADEON_SURF_MODE_2D
:
1178 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1180 case RADEON_SURF_MODE_1D
:
1181 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1182 case RADEON_SURF_MODE_LINEAR
:
1184 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1187 tile_split
= rtex
->surface
.tile_split
;
1188 macro_aspect
= rtex
->surface
.mtilea
;
1189 bankw
= rtex
->surface
.bankw
;
1190 bankh
= rtex
->surface
.bankh
;
1191 tile_split
= eg_tile_split(tile_split
);
1192 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1193 bankw
= eg_bank_wh(bankw
);
1194 bankh
= eg_bank_wh(bankh
);
1195 nbanks
= eg_num_banks(rscreen
->b
.tiling_info
.num_banks
);
1198 surf
->db_z_info
= S_028040_ARRAY_MODE(array_mode
) |
1199 S_028040_FORMAT(format
) |
1200 S_028040_TILE_SPLIT(tile_split
)|
1201 S_028040_NUM_BANKS(nbanks
) |
1202 S_028040_BANK_WIDTH(bankw
) |
1203 S_028040_BANK_HEIGHT(bankh
) |
1204 S_028040_MACRO_TILE_ASPECT(macro_aspect
);
1205 if (rscreen
->b
.chip_class
== CAYMAN
&& rtex
->resource
.b
.b
.nr_samples
> 1) {
1206 surf
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
1208 surf
->db_depth_base
= offset
;
1209 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1210 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1211 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX(pitch
);
1212 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX(slice
);
1214 switch (surf
->base
.format
) {
1215 case PIPE_FORMAT_Z24X8_UNORM
:
1216 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1217 case PIPE_FORMAT_X8Z24_UNORM
:
1218 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1219 surf
->pa_su_poly_offset_db_fmt_cntl
=
1220 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1222 case PIPE_FORMAT_Z32_FLOAT
:
1223 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1224 surf
->pa_su_poly_offset_db_fmt_cntl
=
1225 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1226 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1228 case PIPE_FORMAT_Z16_UNORM
:
1229 surf
->pa_su_poly_offset_db_fmt_cntl
=
1230 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1235 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1236 uint64_t stencil_offset
;
1237 unsigned stile_split
= rtex
->surface
.stencil_tile_split
;
1239 stile_split
= eg_tile_split(stile_split
);
1241 stencil_offset
= rtex
->surface
.stencil_level
[level
].offset
;
1242 stencil_offset
+= r600_resource_va(screen
, surf
->base
.texture
);
1244 surf
->db_stencil_base
= stencil_offset
>> 8;
1245 surf
->db_stencil_info
= S_028044_FORMAT(V_028044_STENCIL_8
) |
1246 S_028044_TILE_SPLIT(stile_split
);
1248 surf
->db_stencil_base
= offset
;
1249 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1250 * Older kernels are out of luck. */
1251 surf
->db_stencil_info
= rctx
->screen
->b
.info
.drm_minor
>= 18 ?
1252 S_028044_FORMAT(V_028044_STENCIL_INVALID
) :
1253 S_028044_FORMAT(V_028044_STENCIL_8
);
1256 /* use htile only for first level */
1257 if (rtex
->htile_buffer
&& !level
) {
1258 uint64_t va
= r600_resource_va(&rctx
->screen
->b
.b
, &rtex
->htile_buffer
->b
.b
);
1259 surf
->db_htile_data_base
= va
>> 8;
1260 surf
->db_htile_surface
= S_028ABC_HTILE_WIDTH(1) |
1261 S_028ABC_HTILE_HEIGHT(1) |
1262 S_028ABC_FULL_CACHE(1) |
1264 surf
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
1265 surf
->db_preload_control
= 0;
1268 surf
->depth_initialized
= true;
1271 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
1272 const struct pipe_framebuffer_state
*state
)
1274 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1275 struct r600_surface
*surf
;
1276 struct r600_texture
*rtex
;
1277 uint32_t i
, log_samples
;
1279 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1280 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1281 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_CB
|
1282 R600_CONTEXT_FLUSH_AND_INV_CB_META
;
1284 if (rctx
->framebuffer
.state
.zsbuf
) {
1285 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1286 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB
;
1288 rtex
= (struct r600_texture
*)rctx
->framebuffer
.state
.zsbuf
->texture
;
1289 if (rtex
->htile_buffer
) {
1290 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB_META
;
1294 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1297 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1298 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&& state
->cbufs
[0] &&
1299 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1300 rctx
->framebuffer
.compressed_cb_mask
= 0;
1301 rctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
1303 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1304 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1308 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1310 r600_context_add_resource_size(ctx
, state
->cbufs
[i
]->texture
);
1312 if (!surf
->color_initialized
) {
1313 evergreen_init_color_surface(rctx
, surf
);
1316 if (!surf
->export_16bpc
) {
1317 rctx
->framebuffer
.export_16bpc
= false;
1320 if (rtex
->fmask
.size
&& rtex
->cmask
.size
) {
1321 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1325 /* Update alpha-test state dependencies.
1326 * Alpha-test is done on the first colorbuffer only. */
1327 if (state
->nr_cbufs
) {
1328 bool alphatest_bypass
= false;
1329 bool export_16bpc
= true;
1331 surf
= (struct r600_surface
*)state
->cbufs
[0];
1333 alphatest_bypass
= surf
->alphatest_bypass
;
1334 export_16bpc
= surf
->export_16bpc
;
1337 if (rctx
->alphatest_state
.bypass
!= alphatest_bypass
) {
1338 rctx
->alphatest_state
.bypass
= alphatest_bypass
;
1339 rctx
->alphatest_state
.atom
.dirty
= true;
1341 if (rctx
->alphatest_state
.cb0_export_16bpc
!= export_16bpc
) {
1342 rctx
->alphatest_state
.cb0_export_16bpc
= export_16bpc
;
1343 rctx
->alphatest_state
.atom
.dirty
= true;
1349 surf
= (struct r600_surface
*)state
->zsbuf
;
1351 r600_context_add_resource_size(ctx
, state
->zsbuf
->texture
);
1353 if (!surf
->depth_initialized
) {
1354 evergreen_init_depth_surface(rctx
, surf
);
1357 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1358 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1359 rctx
->poly_offset_state
.atom
.dirty
= true;
1362 if (rctx
->db_state
.rsurf
!= surf
) {
1363 rctx
->db_state
.rsurf
= surf
;
1364 rctx
->db_state
.atom
.dirty
= true;
1365 rctx
->db_misc_state
.atom
.dirty
= true;
1367 } else if (rctx
->db_state
.rsurf
) {
1368 rctx
->db_state
.rsurf
= NULL
;
1369 rctx
->db_state
.atom
.dirty
= true;
1370 rctx
->db_misc_state
.atom
.dirty
= true;
1373 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1374 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1375 rctx
->cb_misc_state
.atom
.dirty
= true;
1378 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1379 rctx
->alphatest_state
.bypass
= false;
1380 rctx
->alphatest_state
.atom
.dirty
= true;
1383 log_samples
= util_logbase2(rctx
->framebuffer
.nr_samples
);
1384 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1385 if ((rctx
->b
.chip_class
== CAYMAN
||
1386 rctx
->b
.family
== CHIP_RV770
) &&
1387 rctx
->db_misc_state
.log_samples
!= log_samples
) {
1388 rctx
->db_misc_state
.log_samples
= log_samples
;
1389 rctx
->db_misc_state
.atom
.dirty
= true;
1393 /* Calculate the CS size. */
1394 rctx
->framebuffer
.atom
.num_dw
= 4; /* SCISSOR */
1397 if (rctx
->b
.chip_class
== EVERGREEN
)
1398 rctx
->framebuffer
.atom
.num_dw
+= 14; /* Evergreen */
1400 rctx
->framebuffer
.atom
.num_dw
+= 25; /* Cayman */
1403 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 23;
1404 if (rctx
->keep_tiling_flags
)
1405 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 2;
1406 rctx
->framebuffer
.atom
.num_dw
+= (12 - state
->nr_cbufs
) * 3;
1410 rctx
->framebuffer
.atom
.num_dw
+= 24;
1411 if (rctx
->keep_tiling_flags
)
1412 rctx
->framebuffer
.atom
.num_dw
+= 2;
1413 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1414 rctx
->framebuffer
.atom
.num_dw
+= 4;
1417 rctx
->framebuffer
.atom
.dirty
= true;
1422 static uint32_t sample_locs_8x
[] = {
1423 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1424 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1425 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1426 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1427 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1428 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1429 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1430 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1432 static unsigned max_dist_8x
= 7;
1434 static void evergreen_get_sample_position(struct pipe_context
*ctx
,
1435 unsigned sample_count
,
1436 unsigned sample_index
,
1443 switch (sample_count
) {
1446 out_value
[0] = out_value
[1] = 0.5;
1449 offset
= 4 * (sample_index
* 2);
1450 val
.idx
= (eg_sample_locs_2x
[0] >> offset
) & 0xf;
1451 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1452 val
.idx
= (eg_sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1453 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1456 offset
= 4 * (sample_index
* 2);
1457 val
.idx
= (eg_sample_locs_4x
[0] >> offset
) & 0xf;
1458 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1459 val
.idx
= (eg_sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1460 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1463 offset
= 4 * (sample_index
% 4 * 2);
1464 index
= (sample_index
/ 4);
1465 val
.idx
= (sample_locs_8x
[index
] >> offset
) & 0xf;
1466 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1467 val
.idx
= (sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1468 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1473 static void evergreen_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
1476 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1477 unsigned max_dist
= 0;
1479 switch (nr_samples
) {
1484 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(eg_sample_locs_2x
));
1485 radeon_emit_array(cs
, eg_sample_locs_2x
, Elements(eg_sample_locs_2x
));
1486 max_dist
= eg_max_dist_2x
;
1489 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(eg_sample_locs_4x
));
1490 radeon_emit_array(cs
, eg_sample_locs_4x
, Elements(eg_sample_locs_4x
));
1491 max_dist
= eg_max_dist_4x
;
1494 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(sample_locs_8x
));
1495 radeon_emit_array(cs
, sample_locs_8x
, Elements(sample_locs_8x
));
1496 max_dist
= max_dist_8x
;
1500 if (nr_samples
> 1) {
1501 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1502 radeon_emit(cs
, S_028C00_LAST_PIXEL(1) |
1503 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1504 radeon_emit(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1505 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1507 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1508 radeon_emit(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1509 radeon_emit(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1513 static void evergreen_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1515 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1516 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1517 unsigned nr_cbufs
= state
->nr_cbufs
;
1519 struct r600_texture
*tex
= NULL
;
1520 struct r600_surface
*cb
= NULL
;
1522 /* XXX support more colorbuffers once we need them */
1523 assert(nr_cbufs
<= 8);
1528 for (i
= 0; i
< nr_cbufs
; i
++) {
1529 unsigned reloc
, cmask_reloc
;
1531 cb
= (struct r600_surface
*)state
->cbufs
[i
];
1533 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1534 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1538 tex
= (struct r600_texture
*)cb
->base
.texture
;
1539 reloc
= r600_context_bo_reloc(&rctx
->b
,
1541 (struct r600_resource
*)cb
->base
.texture
,
1542 RADEON_USAGE_READWRITE
,
1543 tex
->surface
.nsamples
> 1 ?
1544 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1545 RADEON_PRIO_COLOR_BUFFER
);
1547 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
1548 cmask_reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
,
1549 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
1550 RADEON_PRIO_COLOR_META
);
1552 cmask_reloc
= reloc
;
1555 r600_write_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 13);
1556 radeon_emit(cs
, cb
->cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
1557 radeon_emit(cs
, cb
->cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
1558 radeon_emit(cs
, cb
->cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
1559 radeon_emit(cs
, cb
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
1560 radeon_emit(cs
, cb
->cb_color_info
| tex
->cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
1561 radeon_emit(cs
, cb
->cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
1562 radeon_emit(cs
, cb
->cb_color_dim
); /* R_028C78_CB_COLOR0_DIM */
1563 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* R_028C7C_CB_COLOR0_CMASK */
1564 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1565 radeon_emit(cs
, cb
->cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
1566 radeon_emit(cs
, cb
->cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1567 radeon_emit(cs
, tex
->color_clear_value
[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1568 radeon_emit(cs
, tex
->color_clear_value
[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1570 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1571 radeon_emit(cs
, reloc
);
1573 if (!rctx
->keep_tiling_flags
) {
1574 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1575 radeon_emit(cs
, reloc
);
1578 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1579 radeon_emit(cs
, reloc
);
1581 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1582 radeon_emit(cs
, cmask_reloc
);
1584 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1585 radeon_emit(cs
, reloc
);
1587 /* set CB_COLOR1_INFO for possible dual-src blending */
1588 if (i
== 1 && state
->cbufs
[0]) {
1589 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C,
1590 cb
->cb_color_info
| tex
->cb_color_info
);
1592 if (!rctx
->keep_tiling_flags
) {
1593 unsigned reloc
= r600_context_bo_reloc(&rctx
->b
,
1595 (struct r600_resource
*)state
->cbufs
[0]->texture
,
1596 RADEON_USAGE_READWRITE
,
1597 RADEON_PRIO_COLOR_BUFFER
);
1599 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1600 radeon_emit(cs
, reloc
);
1604 if (rctx
->keep_tiling_flags
) {
1605 for (; i
< 8 ; i
++) {
1606 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
1608 for (; i
< 12; i
++) {
1609 r600_write_context_reg(cs
, R_028E50_CB_COLOR8_INFO
+ (i
- 8) * 0x1C, 0);
1615 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
1616 unsigned reloc
= r600_context_bo_reloc(&rctx
->b
,
1618 (struct r600_resource
*)state
->zsbuf
->texture
,
1619 RADEON_USAGE_READWRITE
,
1620 zb
->base
.texture
->nr_samples
> 1 ?
1621 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
1622 RADEON_PRIO_DEPTH_BUFFER
);
1624 r600_write_context_reg(cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1625 zb
->pa_su_poly_offset_db_fmt_cntl
);
1626 r600_write_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
1628 r600_write_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 8);
1629 radeon_emit(cs
, zb
->db_z_info
); /* R_028040_DB_Z_INFO */
1630 radeon_emit(cs
, zb
->db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1631 radeon_emit(cs
, zb
->db_depth_base
); /* R_028048_DB_Z_READ_BASE */
1632 radeon_emit(cs
, zb
->db_stencil_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1633 radeon_emit(cs
, zb
->db_depth_base
); /* R_028050_DB_Z_WRITE_BASE */
1634 radeon_emit(cs
, zb
->db_stencil_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1635 radeon_emit(cs
, zb
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1636 radeon_emit(cs
, zb
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1638 if (!rctx
->keep_tiling_flags
) {
1639 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028040_DB_Z_INFO */
1640 radeon_emit(cs
, reloc
);
1643 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1644 radeon_emit(cs
, reloc
);
1646 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1647 radeon_emit(cs
, reloc
);
1649 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1650 radeon_emit(cs
, reloc
);
1652 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1653 radeon_emit(cs
, reloc
);
1654 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1655 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1656 * Older kernels are out of luck. */
1657 r600_write_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
1658 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
1659 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
1662 /* Framebuffer dimensions. */
1663 evergreen_get_scissor_rect(rctx
, 0, 0, state
->width
, state
->height
, &tl
, &br
);
1665 r600_write_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
1666 radeon_emit(cs
, tl
); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1667 radeon_emit(cs
, br
); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1669 if (rctx
->b
.chip_class
== EVERGREEN
) {
1670 evergreen_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
1672 cayman_emit_msaa_state(cs
, rctx
->framebuffer
.nr_samples
);
1676 static void evergreen_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
1678 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1679 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
1680 float offset_units
= state
->offset_units
;
1681 float offset_scale
= state
->offset_scale
;
1683 switch (state
->zs_format
) {
1684 case PIPE_FORMAT_Z24X8_UNORM
:
1685 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1686 case PIPE_FORMAT_X8Z24_UNORM
:
1687 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1688 offset_units
*= 2.0f
;
1690 case PIPE_FORMAT_Z16_UNORM
:
1691 offset_units
*= 4.0f
;
1696 r600_write_context_reg_seq(cs
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
1697 radeon_emit(cs
, fui(offset_scale
));
1698 radeon_emit(cs
, fui(offset_units
));
1699 radeon_emit(cs
, fui(offset_scale
));
1700 radeon_emit(cs
, fui(offset_units
));
1703 static void evergreen_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1705 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1706 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1707 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1708 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1710 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1711 radeon_emit(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
1712 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
1713 * will assure that the alpha-test will work even if there is
1714 * no colorbuffer bound. */
1715 radeon_emit(cs
, 0xf | (a
->dual_src_blend
? ps_colormask
: 0) | fb_colormask
); /* R_02823C_CB_SHADER_MASK */
1718 static void evergreen_emit_db_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1720 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1721 struct r600_db_state
*a
= (struct r600_db_state
*)atom
;
1723 if (a
->rsurf
&& a
->rsurf
->db_htile_surface
) {
1724 struct r600_texture
*rtex
= (struct r600_texture
*)a
->rsurf
->base
.texture
;
1727 r600_write_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear_value
));
1728 r600_write_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, a
->rsurf
->db_htile_surface
);
1729 r600_write_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, a
->rsurf
->db_preload_control
);
1730 r600_write_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, a
->rsurf
->db_htile_data_base
);
1731 reloc_idx
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rtex
->htile_buffer
,
1732 RADEON_USAGE_READWRITE
, RADEON_PRIO_DEPTH_META
);
1733 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1734 cs
->buf
[cs
->cdw
++] = reloc_idx
;
1736 r600_write_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, 0);
1737 r600_write_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0);
1741 static void evergreen_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1743 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1744 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1745 unsigned db_render_control
= 0;
1746 unsigned db_count_control
= 0;
1747 unsigned db_render_override
=
1748 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
1749 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
1751 if (a
->occlusion_query_enabled
) {
1752 db_count_control
|= S_028004_PERFECT_ZPASS_COUNTS(1);
1753 if (rctx
->b
.chip_class
== CAYMAN
) {
1754 db_count_control
|= S_028004_SAMPLE_RATE(a
->log_samples
);
1756 db_render_override
|= S_02800C_NOOP_CULL_DISABLE(1);
1758 /* FIXME we should be able to use hyperz even if we are not writing to
1759 * zbuffer but somehow this trigger GPU lockup. See :
1761 * https://bugs.freedesktop.org/show_bug.cgi?id=60848
1763 * Disable hyperz for now if not writing to zbuffer.
1765 if (rctx
->db_state
.rsurf
&& rctx
->db_state
.rsurf
->db_htile_surface
&& rctx
->zwritemask
) {
1766 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1767 db_render_override
|= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF
);
1768 /* This is to fix a lockup when hyperz and alpha test are enabled at
1769 * the same time somehow GPU get confuse on which order to pick for
1772 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
1773 db_render_override
|= S_02800C_FORCE_SHADER_Z_ORDER(1);
1776 db_render_override
|= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
);
1778 if (a
->flush_depthstencil_through_cb
) {
1779 assert(a
->copy_depth
|| a
->copy_stencil
);
1781 db_render_control
|= S_028000_DEPTH_COPY_ENABLE(a
->copy_depth
) |
1782 S_028000_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
1783 S_028000_COPY_CENTROID(1) |
1784 S_028000_COPY_SAMPLE(a
->copy_sample
);
1785 } else if (a
->flush_depthstencil_in_place
) {
1786 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(1) |
1787 S_028000_STENCIL_COMPRESS_DISABLE(1);
1788 db_render_override
|= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1790 if (a
->htile_clear
) {
1791 /* FIXME we might want to disable cliprect here */
1792 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(1);
1795 r600_write_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1796 radeon_emit(cs
, db_render_control
); /* R_028000_DB_RENDER_CONTROL */
1797 radeon_emit(cs
, db_count_control
); /* R_028004_DB_COUNT_CONTROL */
1798 r600_write_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
1799 r600_write_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
1802 static void evergreen_emit_vertex_buffers(struct r600_context
*rctx
,
1803 struct r600_vertexbuf_state
*state
,
1804 unsigned resource_offset
,
1807 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1808 uint32_t dirty_mask
= state
->dirty_mask
;
1810 while (dirty_mask
) {
1811 struct pipe_vertex_buffer
*vb
;
1812 struct r600_resource
*rbuffer
;
1814 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
1816 vb
= &state
->vb
[buffer_index
];
1817 rbuffer
= (struct r600_resource
*)vb
->buffer
;
1820 va
= r600_resource_va(&rctx
->screen
->b
.b
, &rbuffer
->b
.b
);
1821 va
+= vb
->buffer_offset
;
1823 /* fetch resources start at index 992 */
1824 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
1825 radeon_emit(cs
, (resource_offset
+ buffer_index
) * 8);
1826 radeon_emit(cs
, va
); /* RESOURCEi_WORD0 */
1827 radeon_emit(cs
, rbuffer
->buf
->size
- vb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
1828 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1829 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1830 S_030008_STRIDE(vb
->stride
) |
1831 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
1832 radeon_emit(cs
, /* RESOURCEi_WORD3 */
1833 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
1834 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
1835 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
1836 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
1837 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1838 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1839 radeon_emit(cs
, 0); /* RESOURCEi_WORD6 */
1840 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
1842 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1843 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1844 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BUFFER_RO
));
1846 state
->dirty_mask
= 0;
1849 static void evergreen_fs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
1851 evergreen_emit_vertex_buffers(rctx
, &rctx
->vertex_buffer_state
, 992, 0);
1854 static void evergreen_cs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
1856 evergreen_emit_vertex_buffers(rctx
, &rctx
->cs_vertex_buffer_state
, 816,
1857 RADEON_CP_PACKET3_COMPUTE_MODE
);
1860 static void evergreen_emit_constant_buffers(struct r600_context
*rctx
,
1861 struct r600_constbuf_state
*state
,
1862 unsigned buffer_id_base
,
1863 unsigned reg_alu_constbuf_size
,
1864 unsigned reg_alu_const_cache
,
1867 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1868 uint32_t dirty_mask
= state
->dirty_mask
;
1870 while (dirty_mask
) {
1871 struct pipe_constant_buffer
*cb
;
1872 struct r600_resource
*rbuffer
;
1874 unsigned buffer_index
= ffs(dirty_mask
) - 1;
1875 unsigned gs_ring_buffer
= (buffer_index
== R600_GS_RING_CONST_BUFFER
);
1877 cb
= &state
->cb
[buffer_index
];
1878 rbuffer
= (struct r600_resource
*)cb
->buffer
;
1881 va
= r600_resource_va(&rctx
->screen
->b
.b
, &rbuffer
->b
.b
);
1882 va
+= cb
->buffer_offset
;
1884 if (!gs_ring_buffer
) {
1885 r600_write_context_reg_flag(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
1886 ALIGN_DIVUP(cb
->buffer_size
>> 4, 16), pkt_flags
);
1887 r600_write_context_reg_flag(cs
, reg_alu_const_cache
+ buffer_index
* 4, va
>> 8,
1891 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1892 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1893 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BUFFER_RO
));
1895 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
1896 radeon_emit(cs
, (buffer_id_base
+ buffer_index
) * 8);
1897 radeon_emit(cs
, va
); /* RESOURCEi_WORD0 */
1898 radeon_emit(cs
, rbuffer
->buf
->size
- cb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
1899 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1900 S_030008_ENDIAN_SWAP(gs_ring_buffer
? ENDIAN_NONE
: r600_endian_swap(32)) |
1901 S_030008_STRIDE(gs_ring_buffer
? 4 : 16) |
1902 S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
1903 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT
));
1904 radeon_emit(cs
, /* RESOURCEi_WORD3 */
1905 S_03000C_UNCACHED(gs_ring_buffer
? 1 : 0) |
1906 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
1907 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
1908 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
1909 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
1910 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1911 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1912 radeon_emit(cs
, 0); /* RESOURCEi_WORD6 */
1913 radeon_emit(cs
, /* RESOURCEi_WORD7 */
1914 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
));
1916 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1917 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1918 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BUFFER_RO
));
1920 dirty_mask
&= ~(1 << buffer_index
);
1922 state
->dirty_mask
= 0;
1925 static void evergreen_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1927 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
], 176,
1928 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
1929 R_028980_ALU_CONST_CACHE_VS_0
,
1930 0 /* PKT3 flags */);
1933 static void evergreen_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1935 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
], 336,
1936 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
1937 R_0289C0_ALU_CONST_CACHE_GS_0
,
1938 0 /* PKT3 flags */);
1941 static void evergreen_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1943 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
], 0,
1944 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
1945 R_028940_ALU_CONST_CACHE_PS_0
,
1946 0 /* PKT3 flags */);
1949 static void evergreen_emit_cs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1951 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_COMPUTE
], 816,
1952 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
,
1953 R_028F40_ALU_CONST_CACHE_LS_0
,
1954 RADEON_CP_PACKET3_COMPUTE_MODE
);
1957 static void evergreen_emit_sampler_views(struct r600_context
*rctx
,
1958 struct r600_samplerview_state
*state
,
1959 unsigned resource_id_base
)
1961 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1962 uint32_t dirty_mask
= state
->dirty_mask
;
1964 while (dirty_mask
) {
1965 struct r600_pipe_sampler_view
*rview
;
1966 unsigned resource_index
= u_bit_scan(&dirty_mask
);
1969 rview
= state
->views
[resource_index
];
1972 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0));
1973 radeon_emit(cs
, (resource_id_base
+ resource_index
) * 8);
1974 radeon_emit_array(cs
, rview
->tex_resource_words
, 8);
1976 reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rview
->tex_resource
,
1978 rview
->tex_resource
->b
.b
.nr_samples
> 1 ?
1979 RADEON_PRIO_SHADER_TEXTURE_MSAA
:
1980 RADEON_PRIO_SHADER_TEXTURE_RO
);
1981 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1982 radeon_emit(cs
, reloc
);
1984 if (!rview
->skip_mip_address_reloc
) {
1985 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1986 radeon_emit(cs
, reloc
);
1989 state
->dirty_mask
= 0;
1992 static void evergreen_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1994 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
, 176 + R600_MAX_CONST_BUFFERS
);
1997 static void evergreen_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1999 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
, 336 + R600_MAX_CONST_BUFFERS
);
2002 static void evergreen_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2004 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
, R600_MAX_CONST_BUFFERS
);
2007 static void evergreen_emit_sampler_states(struct r600_context
*rctx
,
2008 struct r600_textures_info
*texinfo
,
2009 unsigned resource_id_base
,
2010 unsigned border_index_reg
)
2012 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2013 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
2015 while (dirty_mask
) {
2016 struct r600_pipe_sampler_state
*rstate
;
2017 unsigned i
= u_bit_scan(&dirty_mask
);
2019 rstate
= texinfo
->states
.states
[i
];
2022 radeon_emit(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0));
2023 radeon_emit(cs
, (resource_id_base
+ i
) * 3);
2024 radeon_emit_array(cs
, rstate
->tex_sampler_words
, 3);
2026 if (rstate
->border_color_use
) {
2027 r600_write_config_reg_seq(cs
, border_index_reg
, 5);
2029 radeon_emit_array(cs
, rstate
->border_color
.ui
, 4);
2032 texinfo
->states
.dirty_mask
= 0;
2035 static void evergreen_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2037 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
);
2040 static void evergreen_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2042 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX
);
2045 static void evergreen_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2047 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
);
2050 static void evergreen_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2052 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2053 uint8_t mask
= s
->sample_mask
;
2055 r600_write_context_reg(rctx
->b
.rings
.gfx
.cs
, R_028C3C_PA_SC_AA_MASK
,
2056 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2059 static void cayman_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2061 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2062 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2063 uint16_t mask
= s
->sample_mask
;
2065 r600_write_context_reg_seq(cs
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2066 radeon_emit(cs
, mask
| (mask
<< 16)); /* X0Y0_X1Y0 */
2067 radeon_emit(cs
, mask
| (mask
<< 16)); /* X0Y1_X1Y1 */
2070 static void evergreen_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2072 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2073 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
2074 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
->cso
;
2076 r600_write_context_reg(cs
, R_0288A4_SQ_PGM_START_FS
,
2077 (r600_resource_va(rctx
->b
.b
.screen
, &shader
->buffer
->b
.b
) + shader
->offset
) >> 8);
2078 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2079 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, shader
->buffer
,
2080 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
));
2083 static void evergreen_emit_shader_stages(struct r600_context
*rctx
, struct r600_atom
*a
)
2085 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2086 struct r600_shader_stages_state
*state
= (struct r600_shader_stages_state
*)a
;
2088 uint32_t v
= 0, v2
= 0, primid
= 0;
2090 if (state
->geom_enable
) {
2093 if (rctx
->gs_shader
->current
->shader
.gs_max_out_vertices
<= 128)
2094 cut_val
= V_028A40_GS_CUT_128
;
2095 else if (rctx
->gs_shader
->current
->shader
.gs_max_out_vertices
<= 256)
2096 cut_val
= V_028A40_GS_CUT_256
;
2097 else if (rctx
->gs_shader
->current
->shader
.gs_max_out_vertices
<= 512)
2098 cut_val
= V_028A40_GS_CUT_512
;
2100 cut_val
= V_028A40_GS_CUT_1024
;
2101 v
= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
2103 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2105 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
2106 S_028A40_CUT_MODE(cut_val
);
2108 if (rctx
->gs_shader
->current
->shader
.gs_prim_id_input
)
2112 r600_write_context_reg(cs
, R_028B54_VGT_SHADER_STAGES_EN
, v
);
2113 r600_write_context_reg(cs
, R_028A40_VGT_GS_MODE
, v2
);
2114 r600_write_context_reg(cs
, R_028A84_VGT_PRIMITIVEID_EN
, primid
);
2117 static void evergreen_emit_gs_rings(struct r600_context
*rctx
, struct r600_atom
*a
)
2119 struct pipe_screen
*screen
= rctx
->b
.b
.screen
;
2120 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2121 struct r600_gs_rings_state
*state
= (struct r600_gs_rings_state
*)a
;
2122 struct r600_resource
*rbuffer
;
2124 r600_write_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2125 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2126 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
2128 if (state
->enable
) {
2129 rbuffer
=(struct r600_resource
*)state
->esgs_ring
.buffer
;
2130 r600_write_config_reg(cs
, R_008C40_SQ_ESGS_RING_BASE
,
2131 (r600_resource_va(screen
, &rbuffer
->b
.b
)) >> 8);
2132 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2133 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
2134 RADEON_USAGE_READWRITE
,
2135 RADEON_PRIO_SHADER_RESOURCE_RW
));
2136 r600_write_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
,
2137 state
->esgs_ring
.buffer_size
>> 8);
2139 rbuffer
=(struct r600_resource
*)state
->gsvs_ring
.buffer
;
2140 r600_write_config_reg(cs
, R_008C48_SQ_GSVS_RING_BASE
,
2141 (r600_resource_va(screen
, &rbuffer
->b
.b
)) >> 8);
2142 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2143 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
2144 RADEON_USAGE_READWRITE
,
2145 RADEON_PRIO_SHADER_RESOURCE_RW
));
2146 r600_write_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
,
2147 state
->gsvs_ring
.buffer_size
>> 8);
2149 r600_write_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
, 0);
2150 r600_write_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
, 0);
2153 r600_write_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2154 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2155 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
2158 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
2159 enum chip_class ctx_chip_class
,
2160 enum radeon_family ctx_family
,
2163 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2164 r600_store_value(cb
, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2165 /* always set the temp clauses */
2166 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2168 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2169 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2170 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2172 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2174 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
2176 r600_store_context_reg_seq(cb
, R_028350_SX_MISC
, 2);
2177 r600_store_value(cb
, 0);
2178 r600_store_value(cb
, S_028354_SURFACE_SYNC_MASK(0xf));
2180 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2183 static void cayman_init_atom_start_cs(struct r600_context
*rctx
)
2185 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2188 r600_init_command_buffer(cb
, 256);
2190 /* This must be first. */
2191 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2192 r600_store_value(cb
, 0x80000000);
2193 r600_store_value(cb
, 0x80000000);
2195 /* We're setting config registers here. */
2196 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2197 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2199 cayman_init_common_regs(cb
, rctx
->b
.chip_class
,
2200 rctx
->b
.family
, rctx
->screen
->b
.info
.drm_minor
);
2202 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2203 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2205 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2206 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2207 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2208 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2209 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2210 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2211 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2213 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2214 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2215 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2216 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2217 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2219 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2220 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2221 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2222 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2223 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2224 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2225 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2226 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2227 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2228 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2229 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2230 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2231 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2232 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2234 r600_store_context_reg(cb
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0);
2236 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2237 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
2238 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2240 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2242 r600_store_context_reg(cb
, CM_R_028AA8_IA_MULTI_VGT_PARAM
, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2244 r600_store_context_reg_seq(cb
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
2245 r600_store_value(cb
, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2246 r600_store_value(cb
, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2248 r600_store_context_reg_seq(cb
, CM_R_0288E8_SQ_LDS_ALLOC
, 2);
2249 r600_store_value(cb
, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2250 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2252 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2254 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2255 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2256 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2258 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2260 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2262 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2264 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2265 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2266 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2267 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2269 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2270 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2272 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2 * 16);
2273 for (tmp
= 0; tmp
< 16; tmp
++) {
2274 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2275 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2278 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2279 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
2280 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2282 r600_store_context_reg_seq(cb
, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2283 r600_store_value(cb
, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2284 r600_store_value(cb
, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2285 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2286 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2288 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2289 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2290 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2292 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2293 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2294 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2296 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2297 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2298 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2300 /* to avoid GPU doing any preloading of constant from random address */
2301 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2302 r600_store_value(cb
, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2303 r600_store_value(cb
, 0);
2304 r600_store_value(cb
, 0);
2305 r600_store_value(cb
, 0);
2306 r600_store_value(cb
, 0);
2307 r600_store_value(cb
, 0);
2308 r600_store_value(cb
, 0);
2309 r600_store_value(cb
, 0);
2310 r600_store_value(cb
, 0);
2311 r600_store_value(cb
, 0);
2312 r600_store_value(cb
, 0);
2313 r600_store_value(cb
, 0);
2314 r600_store_value(cb
, 0);
2315 r600_store_value(cb
, 0);
2316 r600_store_value(cb
, 0);
2317 r600_store_value(cb
, 0);
2319 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2320 r600_store_value(cb
, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2321 r600_store_value(cb
, 0);
2322 r600_store_value(cb
, 0);
2323 r600_store_value(cb
, 0);
2324 r600_store_value(cb
, 0);
2325 r600_store_value(cb
, 0);
2326 r600_store_value(cb
, 0);
2327 r600_store_value(cb
, 0);
2328 r600_store_value(cb
, 0);
2329 r600_store_value(cb
, 0);
2330 r600_store_value(cb
, 0);
2331 r600_store_value(cb
, 0);
2332 r600_store_value(cb
, 0);
2333 r600_store_value(cb
, 0);
2334 r600_store_value(cb
, 0);
2335 r600_store_value(cb
, 0);
2337 if (rctx
->screen
->b
.has_streamout
) {
2338 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2341 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
2342 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
2343 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2344 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
2345 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2346 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2347 r600_store_context_reg(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 0);
2349 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2350 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2351 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (64 * 4), 0x01000FFF);
2354 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
2355 enum chip_class ctx_chip_class
,
2356 enum radeon_family ctx_family
,
2395 switch (ctx_family
) {
2403 tmp
|= S_008C00_VC_ENABLE(1);
2406 tmp
|= S_008C00_EXPORT_SRC_C(1);
2407 tmp
|= S_008C00_CS_PRIO(cs_prio
);
2408 tmp
|= S_008C00_LS_PRIO(ls_prio
);
2409 tmp
|= S_008C00_HS_PRIO(hs_prio
);
2410 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2411 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2412 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2413 tmp
|= S_008C00_ES_PRIO(es_prio
);
2415 /* enable dynamic GPR resource management */
2416 if (ctx_drm_minor
>= 7) {
2417 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2418 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2419 /* always set temp clauses */
2420 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2421 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2422 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2423 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2424 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2425 r600_store_context_reg(cb
, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
,
2426 S_028838_PS_GPRS(0x1e) |
2427 S_028838_VS_GPRS(0x1e) |
2428 S_028838_GS_GPRS(0x1e) |
2429 S_028838_ES_GPRS(0x1e) |
2430 S_028838_HS_GPRS(0x1e) |
2431 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2433 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 4);
2434 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2436 tmp
= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
2437 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
2438 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
2439 r600_store_value(cb
, tmp
); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2441 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2442 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2443 r600_store_value(cb
, tmp
); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2445 tmp
= S_008C0C_NUM_HS_GPRS(num_hs_gprs
);
2446 tmp
|= S_008C0C_NUM_HS_GPRS(num_ls_gprs
);
2447 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2450 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
2452 /* The cs checker requires this register to be set. */
2453 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2455 r600_store_context_reg_seq(cb
, R_028350_SX_MISC
, 2);
2456 r600_store_value(cb
, 0);
2457 r600_store_value(cb
, S_028354_SURFACE_SYNC_MASK(0xf));
2462 void evergreen_init_atom_start_cs(struct r600_context
*rctx
)
2464 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2472 int num_ps_stack_entries
;
2473 int num_vs_stack_entries
;
2474 int num_gs_stack_entries
;
2475 int num_es_stack_entries
;
2476 int num_hs_stack_entries
;
2477 int num_ls_stack_entries
;
2478 enum radeon_family family
;
2481 if (rctx
->b
.chip_class
== CAYMAN
) {
2482 cayman_init_atom_start_cs(rctx
);
2486 r600_init_command_buffer(cb
, 256);
2488 /* This must be first. */
2489 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2490 r600_store_value(cb
, 0x80000000);
2491 r600_store_value(cb
, 0x80000000);
2493 /* We're setting config registers here. */
2494 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2495 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2497 evergreen_init_common_regs(cb
, rctx
->b
.chip_class
,
2498 rctx
->b
.family
, rctx
->screen
->b
.info
.drm_minor
);
2500 family
= rctx
->b
.family
;
2504 num_ps_threads
= 96;
2505 num_vs_threads
= 16;
2506 num_gs_threads
= 16;
2507 num_es_threads
= 16;
2508 num_hs_threads
= 16;
2509 num_ls_threads
= 16;
2510 num_ps_stack_entries
= 42;
2511 num_vs_stack_entries
= 42;
2512 num_gs_stack_entries
= 42;
2513 num_es_stack_entries
= 42;
2514 num_hs_stack_entries
= 42;
2515 num_ls_stack_entries
= 42;
2518 num_ps_threads
= 128;
2519 num_vs_threads
= 20;
2520 num_gs_threads
= 20;
2521 num_es_threads
= 20;
2522 num_hs_threads
= 20;
2523 num_ls_threads
= 20;
2524 num_ps_stack_entries
= 42;
2525 num_vs_stack_entries
= 42;
2526 num_gs_stack_entries
= 42;
2527 num_es_stack_entries
= 42;
2528 num_hs_stack_entries
= 42;
2529 num_ls_stack_entries
= 42;
2532 num_ps_threads
= 128;
2533 num_vs_threads
= 20;
2534 num_gs_threads
= 20;
2535 num_es_threads
= 20;
2536 num_hs_threads
= 20;
2537 num_ls_threads
= 20;
2538 num_ps_stack_entries
= 85;
2539 num_vs_stack_entries
= 85;
2540 num_gs_stack_entries
= 85;
2541 num_es_stack_entries
= 85;
2542 num_hs_stack_entries
= 85;
2543 num_ls_stack_entries
= 85;
2547 num_ps_threads
= 128;
2548 num_vs_threads
= 20;
2549 num_gs_threads
= 20;
2550 num_es_threads
= 20;
2551 num_hs_threads
= 20;
2552 num_ls_threads
= 20;
2553 num_ps_stack_entries
= 85;
2554 num_vs_stack_entries
= 85;
2555 num_gs_stack_entries
= 85;
2556 num_es_stack_entries
= 85;
2557 num_hs_stack_entries
= 85;
2558 num_ls_stack_entries
= 85;
2561 num_ps_threads
= 96;
2562 num_vs_threads
= 16;
2563 num_gs_threads
= 16;
2564 num_es_threads
= 16;
2565 num_hs_threads
= 16;
2566 num_ls_threads
= 16;
2567 num_ps_stack_entries
= 42;
2568 num_vs_stack_entries
= 42;
2569 num_gs_stack_entries
= 42;
2570 num_es_stack_entries
= 42;
2571 num_hs_stack_entries
= 42;
2572 num_ls_stack_entries
= 42;
2575 num_ps_threads
= 96;
2576 num_vs_threads
= 25;
2577 num_gs_threads
= 25;
2578 num_es_threads
= 25;
2579 num_hs_threads
= 25;
2580 num_ls_threads
= 25;
2581 num_ps_stack_entries
= 42;
2582 num_vs_stack_entries
= 42;
2583 num_gs_stack_entries
= 42;
2584 num_es_stack_entries
= 42;
2585 num_hs_stack_entries
= 42;
2586 num_ls_stack_entries
= 42;
2589 num_ps_threads
= 96;
2590 num_vs_threads
= 25;
2591 num_gs_threads
= 25;
2592 num_es_threads
= 25;
2593 num_hs_threads
= 25;
2594 num_ls_threads
= 25;
2595 num_ps_stack_entries
= 85;
2596 num_vs_stack_entries
= 85;
2597 num_gs_stack_entries
= 85;
2598 num_es_stack_entries
= 85;
2599 num_hs_stack_entries
= 85;
2600 num_ls_stack_entries
= 85;
2603 num_ps_threads
= 128;
2604 num_vs_threads
= 20;
2605 num_gs_threads
= 20;
2606 num_es_threads
= 20;
2607 num_hs_threads
= 20;
2608 num_ls_threads
= 20;
2609 num_ps_stack_entries
= 85;
2610 num_vs_stack_entries
= 85;
2611 num_gs_stack_entries
= 85;
2612 num_es_stack_entries
= 85;
2613 num_hs_stack_entries
= 85;
2614 num_ls_stack_entries
= 85;
2617 num_ps_threads
= 128;
2618 num_vs_threads
= 20;
2619 num_gs_threads
= 20;
2620 num_es_threads
= 20;
2621 num_hs_threads
= 20;
2622 num_ls_threads
= 20;
2623 num_ps_stack_entries
= 42;
2624 num_vs_stack_entries
= 42;
2625 num_gs_stack_entries
= 42;
2626 num_es_stack_entries
= 42;
2627 num_hs_stack_entries
= 42;
2628 num_ls_stack_entries
= 42;
2631 num_ps_threads
= 128;
2632 num_vs_threads
= 10;
2633 num_gs_threads
= 10;
2634 num_es_threads
= 10;
2635 num_hs_threads
= 10;
2636 num_ls_threads
= 10;
2637 num_ps_stack_entries
= 42;
2638 num_vs_stack_entries
= 42;
2639 num_gs_stack_entries
= 42;
2640 num_es_stack_entries
= 42;
2641 num_hs_stack_entries
= 42;
2642 num_ls_stack_entries
= 42;
2646 tmp
= S_008C18_NUM_PS_THREADS(num_ps_threads
);
2647 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
2648 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
2649 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
2651 r600_store_config_reg_seq(cb
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, 5);
2652 r600_store_value(cb
, tmp
); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2654 tmp
= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
2655 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
2656 r600_store_value(cb
, tmp
); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2658 tmp
= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2659 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2660 r600_store_value(cb
, tmp
); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2662 tmp
= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2663 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2664 r600_store_value(cb
, tmp
); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2666 tmp
= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
2667 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
2668 r600_store_value(cb
, tmp
); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2670 r600_store_config_reg(cb
, R_008E2C_SQ_LDS_RESOURCE_MGMT
,
2671 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2673 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2674 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2676 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2677 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2678 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2679 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2680 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2681 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2682 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2684 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2685 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2686 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2687 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2688 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2690 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2691 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2692 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2693 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2694 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2695 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2696 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2697 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2698 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2699 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2700 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2701 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2702 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2703 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2705 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2706 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
2707 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2709 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2711 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2713 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2714 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2715 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2717 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2719 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2721 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2722 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2723 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2725 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2 * 16);
2726 for (tmp
= 0; tmp
< 16; tmp
++) {
2727 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2728 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2731 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2732 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
2733 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2735 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2736 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2737 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2738 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2740 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2741 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2742 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2743 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2744 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2746 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2747 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2748 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2750 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2751 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2752 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2754 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2755 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2756 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2758 /* to avoid GPU doing any preloading of constant from random address */
2759 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2760 r600_store_value(cb
, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2761 r600_store_value(cb
, 0);
2762 r600_store_value(cb
, 0);
2763 r600_store_value(cb
, 0);
2764 r600_store_value(cb
, 0);
2765 r600_store_value(cb
, 0);
2766 r600_store_value(cb
, 0);
2767 r600_store_value(cb
, 0);
2768 r600_store_value(cb
, 0);
2769 r600_store_value(cb
, 0);
2770 r600_store_value(cb
, 0);
2771 r600_store_value(cb
, 0);
2772 r600_store_value(cb
, 0);
2773 r600_store_value(cb
, 0);
2774 r600_store_value(cb
, 0);
2775 r600_store_value(cb
, 0);
2777 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2778 r600_store_value(cb
, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2779 r600_store_value(cb
, 0);
2780 r600_store_value(cb
, 0);
2781 r600_store_value(cb
, 0);
2782 r600_store_value(cb
, 0);
2783 r600_store_value(cb
, 0);
2784 r600_store_value(cb
, 0);
2785 r600_store_value(cb
, 0);
2786 r600_store_value(cb
, 0);
2787 r600_store_value(cb
, 0);
2788 r600_store_value(cb
, 0);
2789 r600_store_value(cb
, 0);
2790 r600_store_value(cb
, 0);
2791 r600_store_value(cb
, 0);
2792 r600_store_value(cb
, 0);
2793 r600_store_value(cb
, 0);
2795 r600_store_context_reg(cb
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0);
2797 if (rctx
->screen
->b
.has_streamout
) {
2798 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2801 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
2802 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
2803 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2804 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
2805 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2806 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2807 r600_store_context_reg(cb
, R_0288EC_SQ_LDS_ALLOC_PS
, 0);
2808 r600_store_context_reg(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 0);
2810 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2811 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2812 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (64 * 4), 0x01000FFF);
2815 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2817 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2818 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2819 struct r600_shader
*rshader
= &shader
->shader
;
2820 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
= 0;
2821 int pos_index
= -1, face_index
= -1;
2823 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
2824 unsigned spi_baryc_cntl
, sid
, tmp
, num
= 0;
2825 unsigned z_export
= 0, stencil_export
= 0;
2826 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
2827 uint32_t spi_ps_input_cntl
[32];
2830 r600_init_command_buffer(cb
, 64);
2835 for (i
= 0; i
< rshader
->ninput
; i
++) {
2836 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2837 POSITION goes via GPRs from the SC so isn't counted */
2838 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2840 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
2844 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
2846 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
2847 have_perspective
= TRUE
;
2848 if (rshader
->input
[i
].centroid
)
2849 have_centroid
= TRUE
;
2852 sid
= rshader
->input
[i
].spi_sid
;
2855 tmp
= S_028644_SEMANTIC(sid
);
2857 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2858 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2859 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2860 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
)) {
2861 tmp
|= S_028644_FLAT_SHADE(1);
2864 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2865 (sprite_coord_enable
& (1 << rshader
->input
[i
].sid
))) {
2866 tmp
|= S_028644_PT_SPRITE_TEX(1);
2869 spi_ps_input_cntl
[num
++] = tmp
;
2873 r600_store_context_reg_seq(cb
, R_028644_SPI_PS_INPUT_CNTL_0
, num
);
2874 r600_store_array(cb
, num
, spi_ps_input_cntl
);
2876 for (i
= 0; i
< rshader
->noutput
; i
++) {
2877 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2879 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2882 if (rshader
->uses_kill
)
2883 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2885 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
2886 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export
);
2889 for (i
= 0; i
< rshader
->noutput
; i
++) {
2890 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2891 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2895 num_cout
= rshader
->nr_ps_color_exports
;
2897 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
2899 /* always at least export 1 component per pixel */
2902 shader
->nr_ps_color_outputs
= num_cout
;
2905 have_perspective
= TRUE
;
2908 if (!have_perspective
&& !have_linear
)
2909 have_perspective
= TRUE
;
2911 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
2912 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
2913 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
2915 if (pos_index
!= -1) {
2916 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
2917 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
2918 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
2919 spi_input_z
|= S_0286D8_PROVIDE_Z_TO_SPI(1);
2922 spi_ps_in_control_1
= 0;
2923 if (face_index
!= -1) {
2924 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2925 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2929 if (have_perspective
)
2930 spi_baryc_cntl
|= S_0286E0_PERSP_CENTER_ENA(1) |
2931 S_0286E0_PERSP_CENTROID_ENA(have_centroid
);
2933 spi_baryc_cntl
|= S_0286E0_LINEAR_CENTER_ENA(1) |
2934 S_0286E0_LINEAR_CENTROID_ENA(have_centroid
);
2936 r600_store_context_reg_seq(cb
, R_0286CC_SPI_PS_IN_CONTROL_0
, 2);
2937 r600_store_value(cb
, spi_ps_in_control_0
); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2938 r600_store_value(cb
, spi_ps_in_control_1
); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2940 r600_store_context_reg(cb
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
2941 r600_store_context_reg(cb
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
2942 r600_store_context_reg(cb
, R_02884C_SQ_PGM_EXPORTS_PS
, exports_ps
);
2944 r600_store_context_reg_seq(cb
, R_028840_SQ_PGM_START_PS
, 2);
2945 r600_store_value(cb
, r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8);
2946 r600_store_value(cb
, /* R_028844_SQ_PGM_RESOURCES_PS */
2947 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
2948 S_028844_PRIME_CACHE_ON_DRAW(1) |
2949 S_028844_STACK_SIZE(rshader
->bc
.nstack
));
2950 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2952 shader
->db_shader_control
= db_shader_control
;
2953 shader
->ps_depth_export
= z_export
| stencil_export
;
2955 shader
->sprite_coord_enable
= sprite_coord_enable
;
2956 if (rctx
->rasterizer
)
2957 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
2960 void evergreen_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2962 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2963 struct r600_shader
*rshader
= &shader
->shader
;
2965 r600_init_command_buffer(cb
, 32);
2967 r600_store_context_reg(cb
, R_028890_SQ_PGM_RESOURCES_ES
,
2968 S_028890_NUM_GPRS(rshader
->bc
.ngpr
) |
2969 S_028890_STACK_SIZE(rshader
->bc
.nstack
));
2970 r600_store_context_reg(cb
, R_02888C_SQ_PGM_START_ES
,
2971 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8);
2972 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2975 void evergreen_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2977 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2978 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2979 struct r600_shader
*rshader
= &shader
->shader
;
2980 struct r600_shader
*cp_shader
= &shader
->gs_copy_shader
->shader
;
2981 unsigned gsvs_itemsize
=
2982 (cp_shader
->ring_item_size
* rshader
->gs_max_out_vertices
) >> 2;
2984 r600_init_command_buffer(cb
, 64);
2986 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
2988 r600_store_context_reg(cb
, R_028AB8_VGT_VTX_CNT_EN
, 1);
2990 r600_store_context_reg(cb
, R_028B38_VGT_GS_MAX_VERT_OUT
,
2991 S_028B38_MAX_VERT_OUT(rshader
->gs_max_out_vertices
));
2992 r600_store_context_reg(cb
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
2993 r600_conv_prim_to_gs_out(rshader
->gs_output_prim
));
2995 if (rctx
->screen
->b
.info
.drm_minor
>= 35) {
2996 r600_store_context_reg(cb
, R_028B90_VGT_GS_INSTANCE_CNT
,
2998 S_028B90_ENABLE(0));
3000 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
3001 r600_store_value(cb
, cp_shader
->ring_item_size
>> 2);
3002 r600_store_value(cb
, 0);
3003 r600_store_value(cb
, 0);
3004 r600_store_value(cb
, 0);
3006 r600_store_context_reg(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
,
3007 (rshader
->ring_item_size
) >> 2);
3009 r600_store_context_reg(cb
, R_028904_SQ_GSVS_RING_ITEMSIZE
,
3012 r600_store_context_reg_seq(cb
, R_02892C_SQ_GSVS_RING_OFFSET_1
, 3);
3013 r600_store_value(cb
, gsvs_itemsize
);
3014 r600_store_value(cb
, gsvs_itemsize
);
3015 r600_store_value(cb
, gsvs_itemsize
);
3017 /* FIXME calculate these values somehow ??? */
3018 r600_store_context_reg_seq(cb
, R_028A54_GS_PER_ES
, 3);
3019 r600_store_value(cb
, 0x80); /* GS_PER_ES */
3020 r600_store_value(cb
, 0x100); /* ES_PER_GS */
3021 r600_store_value(cb
, 0x2); /* GS_PER_VS */
3023 r600_store_context_reg(cb
, R_028878_SQ_PGM_RESOURCES_GS
,
3024 S_028878_NUM_GPRS(rshader
->bc
.ngpr
) |
3025 S_028878_STACK_SIZE(rshader
->bc
.nstack
));
3026 r600_store_context_reg(cb
, R_028874_SQ_PGM_START_GS
,
3027 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8);
3028 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3032 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3034 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3035 struct r600_shader
*rshader
= &shader
->shader
;
3036 unsigned spi_vs_out_id
[10] = {};
3037 unsigned i
, tmp
, nparams
= 0;
3039 for (i
= 0; i
< rshader
->noutput
; i
++) {
3040 if (rshader
->output
[i
].spi_sid
) {
3041 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
3042 spi_vs_out_id
[nparams
/ 4] |= tmp
;
3047 r600_init_command_buffer(cb
, 32);
3049 r600_store_context_reg_seq(cb
, R_02861C_SPI_VS_OUT_ID_0
, 10);
3050 for (i
= 0; i
< 10; i
++) {
3051 r600_store_value(cb
, spi_vs_out_id
[i
]);
3054 /* Certain attributes (position, psize, etc.) don't count as params.
3055 * VS is required to export at least one param and r600_shader_from_tgsi()
3056 * takes care of adding a dummy export.
3061 r600_store_context_reg(cb
, R_0286C4_SPI_VS_OUT_CONFIG
,
3062 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
3063 r600_store_context_reg(cb
, R_028860_SQ_PGM_RESOURCES_VS
,
3064 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
3065 S_028860_STACK_SIZE(rshader
->bc
.nstack
));
3066 r600_store_context_reg(cb
, R_02885C_SQ_PGM_START_VS
,
3067 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8);
3068 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3070 shader
->pa_cl_vs_out_cntl
=
3071 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
3072 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
3073 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
3074 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
) |
3075 S_02881C_USE_VTX_EDGE_FLAG(rshader
->vs_out_edgeflag
) |
3076 S_02881C_USE_VTX_VIEWPORT_INDX(rshader
->vs_out_viewport
) |
3077 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader
->vs_out_layer
);
3080 void *evergreen_create_resolve_blend(struct r600_context
*rctx
)
3082 struct pipe_blend_state blend
;
3084 memset(&blend
, 0, sizeof(blend
));
3085 blend
.independent_blend_enable
= true;
3086 blend
.rt
[0].colormask
= 0xf;
3087 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_CB_RESOLVE
);
3090 void *evergreen_create_decompress_blend(struct r600_context
*rctx
)
3092 struct pipe_blend_state blend
;
3093 unsigned mode
= rctx
->screen
->has_compressed_msaa_texturing
?
3094 V_028808_CB_FMASK_DECOMPRESS
: V_028808_CB_DECOMPRESS
;
3096 memset(&blend
, 0, sizeof(blend
));
3097 blend
.independent_blend_enable
= true;
3098 blend
.rt
[0].colormask
= 0xf;
3099 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3102 void *evergreen_create_fastclear_blend(struct r600_context
*rctx
)
3104 struct pipe_blend_state blend
;
3105 unsigned mode
= V_028808_CB_ELIMINATE_FAST_CLEAR
;
3107 memset(&blend
, 0, sizeof(blend
));
3108 blend
.independent_blend_enable
= true;
3109 blend
.rt
[0].colormask
= 0xf;
3110 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3113 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
)
3115 struct pipe_depth_stencil_alpha_state dsa
= {{0}};
3117 return rctx
->b
.b
.create_depth_stencil_alpha_state(&rctx
->b
.b
, &dsa
);
3120 void evergreen_update_db_shader_control(struct r600_context
* rctx
)
3123 unsigned db_shader_control
;
3125 if (!rctx
->ps_shader
) {
3129 dual_export
= rctx
->framebuffer
.export_16bpc
&&
3130 !rctx
->ps_shader
->current
->ps_depth_export
;
3132 db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
3133 S_02880C_DUAL_EXPORT_ENABLE(dual_export
) |
3134 S_02880C_DB_SOURCE_FORMAT(dual_export
? V_02880C_EXPORT_DB_TWO
:
3135 V_02880C_EXPORT_DB_FULL
) |
3136 S_02880C_ALPHA_TO_MASK_DISABLE(rctx
->framebuffer
.cb0_is_integer
);
3138 /* When alpha test is enabled we can't trust the hw to make the proper
3139 * decision on the order in which ztest should be run related to fragment
3142 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3143 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3144 * execution and thus after alpha test so if discarded by the alpha test
3145 * the z value is not written.
3146 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3147 * get a hang unless you flush the DB in between. For now just use
3150 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
3151 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
3153 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
3156 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
) {
3157 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
3158 rctx
->db_misc_state
.atom
.dirty
= true;
3162 static void evergreen_dma_copy_tile(struct r600_context
*rctx
,
3163 struct pipe_resource
*dst
,
3168 struct pipe_resource
*src
,
3173 unsigned copy_height
,
3177 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.dma
.cs
;
3178 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3179 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3180 unsigned array_mode
, lbpp
, pitch_tile_max
, slice_tile_max
, size
;
3181 unsigned ncopy
, height
, cheight
, detile
, i
, x
, y
, z
, src_mode
, dst_mode
;
3182 unsigned sub_cmd
, bank_h
, bank_w
, mt_aspect
, nbanks
, tile_split
, non_disp_tiling
= 0;
3183 uint64_t base
, addr
;
3185 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
3186 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
3187 /* downcast linear aligned to linear to simplify test */
3188 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
3189 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
3190 assert(dst_mode
!= src_mode
);
3192 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3193 if (util_format_has_depth(util_format_description(src
->format
)))
3194 non_disp_tiling
= 1;
3197 sub_cmd
= EG_DMA_COPY_TILED
;
3198 lbpp
= util_logbase2(bpp
);
3199 pitch_tile_max
= ((pitch
/ bpp
) / 8) - 1;
3200 nbanks
= eg_num_banks(rctx
->screen
->b
.tiling_info
.num_banks
);
3202 if (dst_mode
== RADEON_SURF_MODE_LINEAR
) {
3204 array_mode
= evergreen_array_mode(src_mode
);
3205 slice_tile_max
= (rsrc
->surface
.level
[src_level
].nblk_x
* rsrc
->surface
.level
[src_level
].nblk_y
) / (8*8);
3206 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3207 /* linear height must be the same as the slice tile max height, it's ok even
3208 * if the linear destination/source have smaller heigh as the size of the
3209 * dma packet will be using the copy_height which is always smaller or equal
3210 * to the linear height
3212 height
= rsrc
->surface
.level
[src_level
].npix_y
;
3217 base
= rsrc
->surface
.level
[src_level
].offset
;
3218 addr
= rdst
->surface
.level
[dst_level
].offset
;
3219 addr
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
3220 addr
+= dst_y
* pitch
+ dst_x
* bpp
;
3221 bank_h
= eg_bank_wh(rsrc
->surface
.bankh
);
3222 bank_w
= eg_bank_wh(rsrc
->surface
.bankw
);
3223 mt_aspect
= eg_macro_tile_aspect(rsrc
->surface
.mtilea
);
3224 tile_split
= eg_tile_split(rsrc
->surface
.tile_split
);
3225 base
+= r600_resource_va(&rctx
->screen
->b
.b
, src
);
3226 addr
+= r600_resource_va(&rctx
->screen
->b
.b
, dst
);
3229 array_mode
= evergreen_array_mode(dst_mode
);
3230 slice_tile_max
= (rdst
->surface
.level
[dst_level
].nblk_x
* rdst
->surface
.level
[dst_level
].nblk_y
) / (8*8);
3231 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3232 /* linear height must be the same as the slice tile max height, it's ok even
3233 * if the linear destination/source have smaller heigh as the size of the
3234 * dma packet will be using the copy_height which is always smaller or equal
3235 * to the linear height
3237 height
= rdst
->surface
.level
[dst_level
].npix_y
;
3242 base
= rdst
->surface
.level
[dst_level
].offset
;
3243 addr
= rsrc
->surface
.level
[src_level
].offset
;
3244 addr
+= rsrc
->surface
.level
[src_level
].slice_size
* src_z
;
3245 addr
+= src_y
* pitch
+ src_x
* bpp
;
3246 bank_h
= eg_bank_wh(rdst
->surface
.bankh
);
3247 bank_w
= eg_bank_wh(rdst
->surface
.bankw
);
3248 mt_aspect
= eg_macro_tile_aspect(rdst
->surface
.mtilea
);
3249 tile_split
= eg_tile_split(rdst
->surface
.tile_split
);
3250 base
+= r600_resource_va(&rctx
->screen
->b
.b
, dst
);
3251 addr
+= r600_resource_va(&rctx
->screen
->b
.b
, src
);
3254 size
= (copy_height
* pitch
) / 4;
3255 ncopy
= (size
/ EG_DMA_COPY_MAX_SIZE
) + !!(size
% EG_DMA_COPY_MAX_SIZE
);
3256 r600_need_dma_space(&rctx
->b
, ncopy
* 9);
3258 for (i
= 0; i
< ncopy
; i
++) {
3259 cheight
= copy_height
;
3260 if (((cheight
* pitch
) / 4) > EG_DMA_COPY_MAX_SIZE
) {
3261 cheight
= (EG_DMA_COPY_MAX_SIZE
* 4) / pitch
;
3263 size
= (cheight
* pitch
) / 4;
3264 /* emit reloc before writting cs so that cs is always in consistent state */
3265 r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.dma
, &rsrc
->resource
,
3266 RADEON_USAGE_READ
, RADEON_PRIO_MIN
);
3267 r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.dma
, &rdst
->resource
,
3268 RADEON_USAGE_WRITE
, RADEON_PRIO_MIN
);
3269 cs
->buf
[cs
->cdw
++] = DMA_PACKET(DMA_PACKET_COPY
, sub_cmd
, size
);
3270 cs
->buf
[cs
->cdw
++] = base
>> 8;
3271 cs
->buf
[cs
->cdw
++] = (detile
<< 31) | (array_mode
<< 27) |
3272 (lbpp
<< 24) | (bank_h
<< 21) |
3273 (bank_w
<< 18) | (mt_aspect
<< 16);
3274 cs
->buf
[cs
->cdw
++] = (pitch_tile_max
<< 0) | ((height
- 1) << 16);
3275 cs
->buf
[cs
->cdw
++] = (slice_tile_max
<< 0);
3276 cs
->buf
[cs
->cdw
++] = (x
<< 0) | (z
<< 18);
3277 cs
->buf
[cs
->cdw
++] = (y
<< 0) | (tile_split
<< 21) | (nbanks
<< 25) | (non_disp_tiling
<< 28);
3278 cs
->buf
[cs
->cdw
++] = addr
& 0xfffffffc;
3279 cs
->buf
[cs
->cdw
++] = (addr
>> 32UL) & 0xff;
3280 copy_height
-= cheight
;
3281 addr
+= cheight
* pitch
;
3286 static void evergreen_dma_copy(struct pipe_context
*ctx
,
3287 struct pipe_resource
*dst
,
3289 unsigned dstx
, unsigned dsty
, unsigned dstz
,
3290 struct pipe_resource
*src
,
3292 const struct pipe_box
*src_box
)
3294 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3295 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3296 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3297 unsigned dst_pitch
, src_pitch
, bpp
, dst_mode
, src_mode
, copy_height
;
3298 unsigned src_w
, dst_w
;
3299 unsigned src_x
, src_y
;
3300 unsigned dst_x
= dstx
, dst_y
= dsty
, dst_z
= dstz
;
3302 if (rctx
->b
.rings
.dma
.cs
== NULL
) {
3306 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
3307 evergreen_dma_copy_buffer(rctx
, dst
, src
, dst_x
, src_box
->x
, src_box
->width
);
3311 if (src
->format
!= dst
->format
|| src_box
->depth
> 1 ||
3312 rdst
->dirty_level_mask
!= 0) {
3316 if (rsrc
->dirty_level_mask
) {
3317 ctx
->flush_resource(ctx
, src
);
3320 src_x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
3321 dst_x
= util_format_get_nblocksx(src
->format
, dst_x
);
3322 src_y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
3323 dst_y
= util_format_get_nblocksy(src
->format
, dst_y
);
3325 bpp
= rdst
->surface
.bpe
;
3326 dst_pitch
= rdst
->surface
.level
[dst_level
].pitch_bytes
;
3327 src_pitch
= rsrc
->surface
.level
[src_level
].pitch_bytes
;
3328 src_w
= rsrc
->surface
.level
[src_level
].npix_x
;
3329 dst_w
= rdst
->surface
.level
[dst_level
].npix_x
;
3330 copy_height
= src_box
->height
/ rsrc
->surface
.blk_h
;
3332 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
3333 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
3334 /* downcast linear aligned to linear to simplify test */
3335 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
3336 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
3338 if (src_pitch
!= dst_pitch
|| src_box
->x
|| dst_x
|| src_w
!= dst_w
) {
3339 /* FIXME evergreen can do partial blit */
3342 /* the x test here are currently useless (because we don't support partial blit)
3343 * but keep them around so we don't forget about those
3345 if (src_pitch
% 8 || src_box
->x
% 8 || dst_x
% 8 || src_box
->y
% 8 || dst_y
% 8) {
3349 /* 128 bpp surfaces require non_disp_tiling for both
3350 * tiled and linear buffers on cayman. However, async
3351 * DMA only supports it on the tiled side. As such
3352 * the tile order is backwards after a L2T/T2L packet.
3354 if ((rctx
->b
.chip_class
== CAYMAN
) &&
3355 (src_mode
!= dst_mode
) &&
3356 (util_format_get_blocksize(src
->format
) >= 16)) {
3360 if (src_mode
== dst_mode
) {
3361 uint64_t dst_offset
, src_offset
;
3362 /* simple dma blit would do NOTE code here assume :
3365 * dst_pitch == src_pitch
3367 src_offset
= rsrc
->surface
.level
[src_level
].offset
;
3368 src_offset
+= rsrc
->surface
.level
[src_level
].slice_size
* src_box
->z
;
3369 src_offset
+= src_y
* src_pitch
+ src_x
* bpp
;
3370 dst_offset
= rdst
->surface
.level
[dst_level
].offset
;
3371 dst_offset
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
3372 dst_offset
+= dst_y
* dst_pitch
+ dst_x
* bpp
;
3373 evergreen_dma_copy_buffer(rctx
, dst
, src
, dst_offset
, src_offset
,
3374 src_box
->height
* src_pitch
);
3376 evergreen_dma_copy_tile(rctx
, dst
, dst_level
, dst_x
, dst_y
, dst_z
,
3377 src
, src_level
, src_x
, src_y
, src_box
->z
,
3378 copy_height
, dst_pitch
, bpp
);
3383 ctx
->resource_copy_region(ctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
3384 src
, src_level
, src_box
);
3387 void evergreen_init_state_functions(struct r600_context
*rctx
)
3392 * To avoid GPU lockup registers must be emited in a specific order
3393 * (no kidding ...). The order below is important and have been
3394 * partialy infered from analyzing fglrx command stream.
3396 * Don't reorder atom without carefully checking the effect (GPU lockup
3397 * or piglit regression).
3401 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, evergreen_emit_framebuffer_state
, 0);
3403 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, evergreen_emit_vs_constant_buffers
, 0);
3404 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, evergreen_emit_gs_constant_buffers
, 0);
3405 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, evergreen_emit_ps_constant_buffers
, 0);
3406 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_COMPUTE
].atom
, id
++, evergreen_emit_cs_constant_buffers
, 0);
3407 /* shader program */
3408 r600_init_atom(rctx
, &rctx
->cs_shader_state
.atom
, id
++, evergreen_emit_cs_shader
, 0);
3410 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, evergreen_emit_vs_sampler_states
, 0);
3411 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, evergreen_emit_gs_sampler_states
, 0);
3412 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, evergreen_emit_ps_sampler_states
, 0);
3414 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, evergreen_fs_emit_vertex_buffers
, 0);
3415 r600_init_atom(rctx
, &rctx
->cs_vertex_buffer_state
.atom
, id
++, evergreen_cs_emit_vertex_buffers
, 0);
3416 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, evergreen_emit_vs_sampler_views
, 0);
3417 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, evergreen_emit_gs_sampler_views
, 0);
3418 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, evergreen_emit_ps_sampler_views
, 0);
3420 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 7);
3422 if (rctx
->b
.chip_class
== EVERGREEN
) {
3423 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, evergreen_emit_sample_mask
, 3);
3425 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, cayman_emit_sample_mask
, 4);
3427 rctx
->sample_mask
.sample_mask
= ~0;
3429 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
3430 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
3431 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
3432 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, evergreen_emit_cb_misc_state
, 4);
3433 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 6);
3434 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, evergreen_emit_clip_state
, 26);
3435 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, evergreen_emit_db_misc_state
, 10);
3436 r600_init_atom(rctx
, &rctx
->db_state
.atom
, id
++, evergreen_emit_db_state
, 14);
3437 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
3438 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, evergreen_emit_polygon_offset
, 6);
3439 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
3440 for (i
= 0; i
< 16; i
++) {
3441 r600_init_atom(rctx
, &rctx
->viewport
[i
].atom
, id
++, r600_emit_viewport_state
, 8);
3442 r600_init_atom(rctx
, &rctx
->scissor
[i
].atom
, id
++, evergreen_emit_scissor_state
, 4);
3443 rctx
->viewport
[i
].idx
= i
;
3444 rctx
->scissor
[i
].idx
= i
;
3446 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
3447 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, evergreen_emit_vertex_fetch_shader
, 5);
3448 rctx
->atoms
[id
++] = &rctx
->b
.streamout
.begin_atom
;
3449 rctx
->atoms
[id
++] = &rctx
->b
.streamout
.enable_atom
;
3450 r600_init_atom(rctx
, &rctx
->vertex_shader
.atom
, id
++, r600_emit_shader
, 23);
3451 r600_init_atom(rctx
, &rctx
->pixel_shader
.atom
, id
++, r600_emit_shader
, 0);
3452 r600_init_atom(rctx
, &rctx
->geometry_shader
.atom
, id
++, r600_emit_shader
, 0);
3453 r600_init_atom(rctx
, &rctx
->export_shader
.atom
, id
++, r600_emit_shader
, 0);
3454 r600_init_atom(rctx
, &rctx
->shader_stages
.atom
, id
++, evergreen_emit_shader_stages
, 6);
3455 r600_init_atom(rctx
, &rctx
->gs_rings
.atom
, id
++, evergreen_emit_gs_rings
, 26);
3457 rctx
->b
.b
.create_blend_state
= evergreen_create_blend_state
;
3458 rctx
->b
.b
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
3459 rctx
->b
.b
.create_rasterizer_state
= evergreen_create_rs_state
;
3460 rctx
->b
.b
.create_sampler_state
= evergreen_create_sampler_state
;
3461 rctx
->b
.b
.create_sampler_view
= evergreen_create_sampler_view
;
3462 rctx
->b
.b
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
3463 rctx
->b
.b
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
3464 rctx
->b
.b
.set_scissor_states
= evergreen_set_scissor_states
;
3466 if (rctx
->b
.chip_class
== EVERGREEN
)
3467 rctx
->b
.b
.get_sample_position
= evergreen_get_sample_position
;
3469 rctx
->b
.b
.get_sample_position
= cayman_get_sample_position
;
3470 rctx
->b
.dma_copy
= evergreen_dma_copy
;
3472 evergreen_init_compute_state_functions(rctx
);