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[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_blitter.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
38 #include "util/u_surface.h"
39 #include "util/u_pack_color.h"
40 #include "util/u_memory.h"
41 #include "util/u_inlines.h"
42 #include "util/u_framebuffer.h"
43 #include "pipebuffer/pb_buffer.h"
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "r600_formats.h"
50
51 static uint32_t r600_translate_blend_function(int blend_func)
52 {
53 switch (blend_func) {
54 case PIPE_BLEND_ADD:
55 return V_028780_COMB_DST_PLUS_SRC;
56 case PIPE_BLEND_SUBTRACT:
57 return V_028780_COMB_SRC_MINUS_DST;
58 case PIPE_BLEND_REVERSE_SUBTRACT:
59 return V_028780_COMB_DST_MINUS_SRC;
60 case PIPE_BLEND_MIN:
61 return V_028780_COMB_MIN_DST_SRC;
62 case PIPE_BLEND_MAX:
63 return V_028780_COMB_MAX_DST_SRC;
64 default:
65 R600_ERR("Unknown blend function %d\n", blend_func);
66 assert(0);
67 break;
68 }
69 return 0;
70 }
71
72 static uint32_t r600_translate_blend_factor(int blend_fact)
73 {
74 switch (blend_fact) {
75 case PIPE_BLENDFACTOR_ONE:
76 return V_028780_BLEND_ONE;
77 case PIPE_BLENDFACTOR_SRC_COLOR:
78 return V_028780_BLEND_SRC_COLOR;
79 case PIPE_BLENDFACTOR_SRC_ALPHA:
80 return V_028780_BLEND_SRC_ALPHA;
81 case PIPE_BLENDFACTOR_DST_ALPHA:
82 return V_028780_BLEND_DST_ALPHA;
83 case PIPE_BLENDFACTOR_DST_COLOR:
84 return V_028780_BLEND_DST_COLOR;
85 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
86 return V_028780_BLEND_SRC_ALPHA_SATURATE;
87 case PIPE_BLENDFACTOR_CONST_COLOR:
88 return V_028780_BLEND_CONST_COLOR;
89 case PIPE_BLENDFACTOR_CONST_ALPHA:
90 return V_028780_BLEND_CONST_ALPHA;
91 case PIPE_BLENDFACTOR_ZERO:
92 return V_028780_BLEND_ZERO;
93 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
94 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
95 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
96 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
97 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
98 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
99 case PIPE_BLENDFACTOR_INV_DST_COLOR:
100 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
101 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
102 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
103 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
104 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
105 case PIPE_BLENDFACTOR_SRC1_COLOR:
106 return V_028780_BLEND_SRC1_COLOR;
107 case PIPE_BLENDFACTOR_SRC1_ALPHA:
108 return V_028780_BLEND_SRC1_ALPHA;
109 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
110 return V_028780_BLEND_INV_SRC1_COLOR;
111 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
112 return V_028780_BLEND_INV_SRC1_ALPHA;
113 default:
114 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
115 assert(0);
116 break;
117 }
118 return 0;
119 }
120
121 static uint32_t r600_translate_stencil_op(int s_op)
122 {
123 switch (s_op) {
124 case PIPE_STENCIL_OP_KEEP:
125 return V_028800_STENCIL_KEEP;
126 case PIPE_STENCIL_OP_ZERO:
127 return V_028800_STENCIL_ZERO;
128 case PIPE_STENCIL_OP_REPLACE:
129 return V_028800_STENCIL_REPLACE;
130 case PIPE_STENCIL_OP_INCR:
131 return V_028800_STENCIL_INCR;
132 case PIPE_STENCIL_OP_DECR:
133 return V_028800_STENCIL_DECR;
134 case PIPE_STENCIL_OP_INCR_WRAP:
135 return V_028800_STENCIL_INCR_WRAP;
136 case PIPE_STENCIL_OP_DECR_WRAP:
137 return V_028800_STENCIL_DECR_WRAP;
138 case PIPE_STENCIL_OP_INVERT:
139 return V_028800_STENCIL_INVERT;
140 default:
141 R600_ERR("Unknown stencil op %d", s_op);
142 assert(0);
143 break;
144 }
145 return 0;
146 }
147
148 static uint32_t r600_translate_fill(uint32_t func)
149 {
150 switch(func) {
151 case PIPE_POLYGON_MODE_FILL:
152 return 2;
153 case PIPE_POLYGON_MODE_LINE:
154 return 1;
155 case PIPE_POLYGON_MODE_POINT:
156 return 0;
157 default:
158 assert(0);
159 return 0;
160 }
161 }
162
163 /* translates straight */
164 static uint32_t r600_translate_ds_func(int func)
165 {
166 return func;
167 }
168
169 static unsigned r600_tex_wrap(unsigned wrap)
170 {
171 switch (wrap) {
172 default:
173 case PIPE_TEX_WRAP_REPEAT:
174 return V_03C000_SQ_TEX_WRAP;
175 case PIPE_TEX_WRAP_CLAMP:
176 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
177 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
178 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
179 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
180 return V_03C000_SQ_TEX_CLAMP_BORDER;
181 case PIPE_TEX_WRAP_MIRROR_REPEAT:
182 return V_03C000_SQ_TEX_MIRROR;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP:
184 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
186 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
187 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
188 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
189 }
190 }
191
192 static unsigned r600_tex_filter(unsigned filter)
193 {
194 switch (filter) {
195 default:
196 case PIPE_TEX_FILTER_NEAREST:
197 return V_03C000_SQ_TEX_XY_FILTER_POINT;
198 case PIPE_TEX_FILTER_LINEAR:
199 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
200 }
201 }
202
203 static unsigned r600_tex_mipfilter(unsigned filter)
204 {
205 switch (filter) {
206 case PIPE_TEX_MIPFILTER_NEAREST:
207 return V_03C000_SQ_TEX_Z_FILTER_POINT;
208 case PIPE_TEX_MIPFILTER_LINEAR:
209 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
210 default:
211 case PIPE_TEX_MIPFILTER_NONE:
212 return V_03C000_SQ_TEX_Z_FILTER_NONE;
213 }
214 }
215
216 static unsigned r600_tex_compare(unsigned compare)
217 {
218 switch (compare) {
219 default:
220 case PIPE_FUNC_NEVER:
221 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
222 case PIPE_FUNC_LESS:
223 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
224 case PIPE_FUNC_EQUAL:
225 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
226 case PIPE_FUNC_LEQUAL:
227 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
228 case PIPE_FUNC_GREATER:
229 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
230 case PIPE_FUNC_NOTEQUAL:
231 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
232 case PIPE_FUNC_GEQUAL:
233 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
234 case PIPE_FUNC_ALWAYS:
235 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
236 }
237 }
238
239 static unsigned r600_tex_dim(unsigned dim)
240 {
241 switch (dim) {
242 default:
243 case PIPE_TEXTURE_1D:
244 return V_030000_SQ_TEX_DIM_1D;
245 case PIPE_TEXTURE_1D_ARRAY:
246 return V_030000_SQ_TEX_DIM_1D_ARRAY;
247 case PIPE_TEXTURE_2D:
248 case PIPE_TEXTURE_RECT:
249 return V_030000_SQ_TEX_DIM_2D;
250 case PIPE_TEXTURE_2D_ARRAY:
251 return V_030000_SQ_TEX_DIM_2D_ARRAY;
252 case PIPE_TEXTURE_3D:
253 return V_030000_SQ_TEX_DIM_3D;
254 case PIPE_TEXTURE_CUBE:
255 return V_030000_SQ_TEX_DIM_CUBEMAP;
256 }
257 }
258
259 static uint32_t r600_translate_dbformat(enum pipe_format format)
260 {
261 switch (format) {
262 case PIPE_FORMAT_Z16_UNORM:
263 return V_028040_Z_16;
264 case PIPE_FORMAT_Z24X8_UNORM:
265 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
266 return V_028040_Z_24;
267 case PIPE_FORMAT_Z32_FLOAT:
268 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
269 return V_028040_Z_32_FLOAT;
270 default:
271 return ~0U;
272 }
273 }
274
275 static uint32_t r600_translate_colorswap(enum pipe_format format)
276 {
277 switch (format) {
278 /* 8-bit buffers. */
279 case PIPE_FORMAT_L4A4_UNORM:
280 case PIPE_FORMAT_A4R4_UNORM:
281 return V_028C70_SWAP_ALT;
282
283 case PIPE_FORMAT_A8_UNORM:
284 case PIPE_FORMAT_A8_UINT:
285 case PIPE_FORMAT_A8_SINT:
286 case PIPE_FORMAT_R4A4_UNORM:
287 return V_028C70_SWAP_ALT_REV;
288 case PIPE_FORMAT_I8_UNORM:
289 case PIPE_FORMAT_L8_UNORM:
290 case PIPE_FORMAT_I8_UINT:
291 case PIPE_FORMAT_I8_SINT:
292 case PIPE_FORMAT_L8_UINT:
293 case PIPE_FORMAT_L8_SINT:
294 case PIPE_FORMAT_L8_SRGB:
295 case PIPE_FORMAT_R8_UNORM:
296 case PIPE_FORMAT_R8_SNORM:
297 case PIPE_FORMAT_R8_UINT:
298 case PIPE_FORMAT_R8_SINT:
299 return V_028C70_SWAP_STD;
300
301 /* 16-bit buffers. */
302 case PIPE_FORMAT_B5G6R5_UNORM:
303 return V_028C70_SWAP_STD_REV;
304
305 case PIPE_FORMAT_B5G5R5A1_UNORM:
306 case PIPE_FORMAT_B5G5R5X1_UNORM:
307 return V_028C70_SWAP_ALT;
308
309 case PIPE_FORMAT_B4G4R4A4_UNORM:
310 case PIPE_FORMAT_B4G4R4X4_UNORM:
311 return V_028C70_SWAP_ALT;
312
313 case PIPE_FORMAT_Z16_UNORM:
314 return V_028C70_SWAP_STD;
315
316 case PIPE_FORMAT_L8A8_UNORM:
317 case PIPE_FORMAT_L8A8_UINT:
318 case PIPE_FORMAT_L8A8_SINT:
319 case PIPE_FORMAT_L8A8_SRGB:
320 return V_028C70_SWAP_ALT;
321 case PIPE_FORMAT_R8G8_UNORM:
322 case PIPE_FORMAT_R8G8_UINT:
323 case PIPE_FORMAT_R8G8_SINT:
324 return V_028C70_SWAP_STD;
325
326 case PIPE_FORMAT_R16_UNORM:
327 case PIPE_FORMAT_R16_UINT:
328 case PIPE_FORMAT_R16_SINT:
329 case PIPE_FORMAT_R16_FLOAT:
330 return V_028C70_SWAP_STD;
331
332 /* 32-bit buffers. */
333 case PIPE_FORMAT_A8B8G8R8_SRGB:
334 return V_028C70_SWAP_STD_REV;
335 case PIPE_FORMAT_B8G8R8A8_SRGB:
336 return V_028C70_SWAP_ALT;
337
338 case PIPE_FORMAT_B8G8R8A8_UNORM:
339 case PIPE_FORMAT_B8G8R8X8_UNORM:
340 return V_028C70_SWAP_ALT;
341
342 case PIPE_FORMAT_A8R8G8B8_UNORM:
343 case PIPE_FORMAT_X8R8G8B8_UNORM:
344 return V_028C70_SWAP_ALT_REV;
345 case PIPE_FORMAT_R8G8B8A8_SNORM:
346 case PIPE_FORMAT_R8G8B8A8_UNORM:
347 case PIPE_FORMAT_R8G8B8A8_SSCALED:
348 case PIPE_FORMAT_R8G8B8A8_USCALED:
349 case PIPE_FORMAT_R8G8B8A8_SINT:
350 case PIPE_FORMAT_R8G8B8A8_UINT:
351 case PIPE_FORMAT_R8G8B8X8_UNORM:
352 return V_028C70_SWAP_STD;
353
354 case PIPE_FORMAT_A8B8G8R8_UNORM:
355 case PIPE_FORMAT_X8B8G8R8_UNORM:
356 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
357 return V_028C70_SWAP_STD_REV;
358
359 case PIPE_FORMAT_Z24X8_UNORM:
360 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
361 return V_028C70_SWAP_STD;
362
363 case PIPE_FORMAT_X8Z24_UNORM:
364 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
365 return V_028C70_SWAP_STD;
366
367 case PIPE_FORMAT_R10G10B10A2_UNORM:
368 case PIPE_FORMAT_R10G10B10X2_SNORM:
369 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
370 return V_028C70_SWAP_STD;
371
372 case PIPE_FORMAT_B10G10R10A2_UNORM:
373 case PIPE_FORMAT_B10G10R10A2_UINT:
374 return V_028C70_SWAP_ALT;
375
376 case PIPE_FORMAT_R11G11B10_FLOAT:
377 case PIPE_FORMAT_R32_FLOAT:
378 case PIPE_FORMAT_R32_UINT:
379 case PIPE_FORMAT_R32_SINT:
380 case PIPE_FORMAT_Z32_FLOAT:
381 case PIPE_FORMAT_R16G16_FLOAT:
382 case PIPE_FORMAT_R16G16_UNORM:
383 case PIPE_FORMAT_R16G16_UINT:
384 case PIPE_FORMAT_R16G16_SINT:
385 return V_028C70_SWAP_STD;
386
387 /* 64-bit buffers. */
388 case PIPE_FORMAT_R32G32_FLOAT:
389 case PIPE_FORMAT_R32G32_UINT:
390 case PIPE_FORMAT_R32G32_SINT:
391 case PIPE_FORMAT_R16G16B16A16_UNORM:
392 case PIPE_FORMAT_R16G16B16A16_SNORM:
393 case PIPE_FORMAT_R16G16B16A16_USCALED:
394 case PIPE_FORMAT_R16G16B16A16_SSCALED:
395 case PIPE_FORMAT_R16G16B16A16_UINT:
396 case PIPE_FORMAT_R16G16B16A16_SINT:
397 case PIPE_FORMAT_R16G16B16A16_FLOAT:
398 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
399
400 /* 128-bit buffers. */
401 case PIPE_FORMAT_R32G32B32A32_FLOAT:
402 case PIPE_FORMAT_R32G32B32A32_SNORM:
403 case PIPE_FORMAT_R32G32B32A32_UNORM:
404 case PIPE_FORMAT_R32G32B32A32_SSCALED:
405 case PIPE_FORMAT_R32G32B32A32_USCALED:
406 case PIPE_FORMAT_R32G32B32A32_SINT:
407 case PIPE_FORMAT_R32G32B32A32_UINT:
408 return V_028C70_SWAP_STD;
409 default:
410 R600_ERR("unsupported colorswap format %d\n", format);
411 return ~0U;
412 }
413 return ~0U;
414 }
415
416 static uint32_t r600_translate_colorformat(enum pipe_format format)
417 {
418 switch (format) {
419 /* 8-bit buffers. */
420 case PIPE_FORMAT_L4A4_UNORM:
421 case PIPE_FORMAT_R4A4_UNORM:
422 case PIPE_FORMAT_A4R4_UNORM:
423 return V_028C70_COLOR_4_4;
424
425 case PIPE_FORMAT_A8_UNORM:
426 case PIPE_FORMAT_A8_UINT:
427 case PIPE_FORMAT_A8_SINT:
428 case PIPE_FORMAT_I8_UNORM:
429 case PIPE_FORMAT_I8_UINT:
430 case PIPE_FORMAT_I8_SINT:
431 case PIPE_FORMAT_L8_UNORM:
432 case PIPE_FORMAT_L8_UINT:
433 case PIPE_FORMAT_L8_SINT:
434 case PIPE_FORMAT_L8_SRGB:
435 case PIPE_FORMAT_R8_UNORM:
436 case PIPE_FORMAT_R8_SNORM:
437 case PIPE_FORMAT_R8_UINT:
438 case PIPE_FORMAT_R8_SINT:
439 return V_028C70_COLOR_8;
440
441 /* 16-bit buffers. */
442 case PIPE_FORMAT_B5G6R5_UNORM:
443 return V_028C70_COLOR_5_6_5;
444
445 case PIPE_FORMAT_B5G5R5A1_UNORM:
446 case PIPE_FORMAT_B5G5R5X1_UNORM:
447 return V_028C70_COLOR_1_5_5_5;
448
449 case PIPE_FORMAT_B4G4R4A4_UNORM:
450 case PIPE_FORMAT_B4G4R4X4_UNORM:
451 return V_028C70_COLOR_4_4_4_4;
452
453 case PIPE_FORMAT_Z16_UNORM:
454 return V_028C70_COLOR_16;
455
456 case PIPE_FORMAT_L8A8_UNORM:
457 case PIPE_FORMAT_L8A8_UINT:
458 case PIPE_FORMAT_L8A8_SINT:
459 case PIPE_FORMAT_L8A8_SRGB:
460 case PIPE_FORMAT_R8G8_UNORM:
461 case PIPE_FORMAT_R8G8_UINT:
462 case PIPE_FORMAT_R8G8_SINT:
463 return V_028C70_COLOR_8_8;
464
465 case PIPE_FORMAT_R16_UNORM:
466 case PIPE_FORMAT_R16_UINT:
467 case PIPE_FORMAT_R16_SINT:
468 return V_028C70_COLOR_16;
469
470 case PIPE_FORMAT_R16_FLOAT:
471 return V_028C70_COLOR_16_FLOAT;
472
473 /* 32-bit buffers. */
474 case PIPE_FORMAT_A8B8G8R8_SRGB:
475 case PIPE_FORMAT_A8B8G8R8_UNORM:
476 case PIPE_FORMAT_A8R8G8B8_UNORM:
477 case PIPE_FORMAT_B8G8R8A8_SRGB:
478 case PIPE_FORMAT_B8G8R8A8_UNORM:
479 case PIPE_FORMAT_B8G8R8X8_UNORM:
480 case PIPE_FORMAT_R8G8B8A8_SNORM:
481 case PIPE_FORMAT_R8G8B8A8_UNORM:
482 case PIPE_FORMAT_R8G8B8X8_UNORM:
483 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
484 case PIPE_FORMAT_X8B8G8R8_UNORM:
485 case PIPE_FORMAT_X8R8G8B8_UNORM:
486 case PIPE_FORMAT_R8G8B8_UNORM:
487 case PIPE_FORMAT_R8G8B8A8_SSCALED:
488 case PIPE_FORMAT_R8G8B8A8_USCALED:
489 case PIPE_FORMAT_R8G8B8A8_SINT:
490 case PIPE_FORMAT_R8G8B8A8_UINT:
491 return V_028C70_COLOR_8_8_8_8;
492
493 case PIPE_FORMAT_R10G10B10A2_UNORM:
494 case PIPE_FORMAT_R10G10B10X2_SNORM:
495 case PIPE_FORMAT_B10G10R10A2_UNORM:
496 case PIPE_FORMAT_B10G10R10A2_UINT:
497 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
498 return V_028C70_COLOR_2_10_10_10;
499
500 case PIPE_FORMAT_Z24X8_UNORM:
501 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
502 return V_028C70_COLOR_8_24;
503
504 case PIPE_FORMAT_X8Z24_UNORM:
505 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
506 return V_028C70_COLOR_24_8;
507
508 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
509 return V_028C70_COLOR_X24_8_32_FLOAT;
510
511 case PIPE_FORMAT_R32_FLOAT:
512 case PIPE_FORMAT_Z32_FLOAT:
513 return V_028C70_COLOR_32_FLOAT;
514
515 case PIPE_FORMAT_R16G16_FLOAT:
516 return V_028C70_COLOR_16_16_FLOAT;
517
518 case PIPE_FORMAT_R16G16_SSCALED:
519 case PIPE_FORMAT_R16G16_UNORM:
520 case PIPE_FORMAT_R16G16_UINT:
521 case PIPE_FORMAT_R16G16_SINT:
522 return V_028C70_COLOR_16_16;
523
524 case PIPE_FORMAT_R11G11B10_FLOAT:
525 return V_028C70_COLOR_10_11_11_FLOAT;
526
527 /* 64-bit buffers. */
528 case PIPE_FORMAT_R16G16B16_USCALED:
529 case PIPE_FORMAT_R16G16B16_SSCALED:
530 case PIPE_FORMAT_R16G16B16A16_UINT:
531 case PIPE_FORMAT_R16G16B16A16_SINT:
532 case PIPE_FORMAT_R16G16B16A16_USCALED:
533 case PIPE_FORMAT_R16G16B16A16_SSCALED:
534 case PIPE_FORMAT_R16G16B16A16_UNORM:
535 case PIPE_FORMAT_R16G16B16A16_SNORM:
536 return V_028C70_COLOR_16_16_16_16;
537
538 case PIPE_FORMAT_R16G16B16_FLOAT:
539 case PIPE_FORMAT_R16G16B16A16_FLOAT:
540 return V_028C70_COLOR_16_16_16_16_FLOAT;
541
542 case PIPE_FORMAT_R32G32_FLOAT:
543 return V_028C70_COLOR_32_32_FLOAT;
544
545 case PIPE_FORMAT_R32G32_USCALED:
546 case PIPE_FORMAT_R32G32_SSCALED:
547 case PIPE_FORMAT_R32G32_SINT:
548 case PIPE_FORMAT_R32G32_UINT:
549 return V_028C70_COLOR_32_32;
550
551 /* 96-bit buffers. */
552 case PIPE_FORMAT_R32G32B32_FLOAT:
553 return V_028C70_COLOR_32_32_32_FLOAT;
554
555 /* 128-bit buffers. */
556 case PIPE_FORMAT_R32G32B32A32_SNORM:
557 case PIPE_FORMAT_R32G32B32A32_UNORM:
558 case PIPE_FORMAT_R32G32B32A32_SSCALED:
559 case PIPE_FORMAT_R32G32B32A32_USCALED:
560 case PIPE_FORMAT_R32G32B32A32_SINT:
561 case PIPE_FORMAT_R32G32B32A32_UINT:
562 return V_028C70_COLOR_32_32_32_32;
563 case PIPE_FORMAT_R32G32B32A32_FLOAT:
564 return V_028C70_COLOR_32_32_32_32_FLOAT;
565
566 /* YUV buffers. */
567 case PIPE_FORMAT_UYVY:
568 case PIPE_FORMAT_YUYV:
569 default:
570 return ~0U; /* Unsupported. */
571 }
572 }
573
574 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
575 {
576 if (R600_BIG_ENDIAN) {
577 switch(colorformat) {
578 case V_028C70_COLOR_4_4:
579 return ENDIAN_NONE;
580
581 /* 8-bit buffers. */
582 case V_028C70_COLOR_8:
583 return ENDIAN_NONE;
584
585 /* 16-bit buffers. */
586 case V_028C70_COLOR_5_6_5:
587 case V_028C70_COLOR_1_5_5_5:
588 case V_028C70_COLOR_4_4_4_4:
589 case V_028C70_COLOR_16:
590 case V_028C70_COLOR_8_8:
591 return ENDIAN_8IN16;
592
593 /* 32-bit buffers. */
594 case V_028C70_COLOR_8_8_8_8:
595 case V_028C70_COLOR_2_10_10_10:
596 case V_028C70_COLOR_8_24:
597 case V_028C70_COLOR_24_8:
598 case V_028C70_COLOR_32_FLOAT:
599 case V_028C70_COLOR_16_16_FLOAT:
600 case V_028C70_COLOR_16_16:
601 return ENDIAN_8IN32;
602
603 /* 64-bit buffers. */
604 case V_028C70_COLOR_16_16_16_16:
605 case V_028C70_COLOR_16_16_16_16_FLOAT:
606 return ENDIAN_8IN16;
607
608 case V_028C70_COLOR_32_32_FLOAT:
609 case V_028C70_COLOR_32_32:
610 case V_028C70_COLOR_X24_8_32_FLOAT:
611 return ENDIAN_8IN32;
612
613 /* 96-bit buffers. */
614 case V_028C70_COLOR_32_32_32_FLOAT:
615 /* 128-bit buffers. */
616 case V_028C70_COLOR_32_32_32_32_FLOAT:
617 case V_028C70_COLOR_32_32_32_32:
618 return ENDIAN_8IN32;
619 default:
620 return ENDIAN_NONE; /* Unsupported. */
621 }
622 } else {
623 return ENDIAN_NONE;
624 }
625 }
626
627 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
628 {
629 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
630 }
631
632 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
633 {
634 return r600_translate_colorformat(format) != ~0U &&
635 r600_translate_colorswap(format) != ~0U;
636 }
637
638 static bool r600_is_zs_format_supported(enum pipe_format format)
639 {
640 return r600_translate_dbformat(format) != ~0U;
641 }
642
643 boolean evergreen_is_format_supported(struct pipe_screen *screen,
644 enum pipe_format format,
645 enum pipe_texture_target target,
646 unsigned sample_count,
647 unsigned usage)
648 {
649 unsigned retval = 0;
650
651 if (target >= PIPE_MAX_TEXTURE_TYPES) {
652 R600_ERR("r600: unsupported texture type %d\n", target);
653 return FALSE;
654 }
655
656 if (!util_format_is_supported(format, usage))
657 return FALSE;
658
659 /* Multisample */
660 if (sample_count > 1)
661 return FALSE;
662
663 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
664 r600_is_sampler_format_supported(screen, format)) {
665 retval |= PIPE_BIND_SAMPLER_VIEW;
666 }
667
668 if ((usage & (PIPE_BIND_RENDER_TARGET |
669 PIPE_BIND_DISPLAY_TARGET |
670 PIPE_BIND_SCANOUT |
671 PIPE_BIND_SHARED)) &&
672 r600_is_colorbuffer_format_supported(format)) {
673 retval |= usage &
674 (PIPE_BIND_RENDER_TARGET |
675 PIPE_BIND_DISPLAY_TARGET |
676 PIPE_BIND_SCANOUT |
677 PIPE_BIND_SHARED);
678 }
679
680 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
681 r600_is_zs_format_supported(format)) {
682 retval |= PIPE_BIND_DEPTH_STENCIL;
683 }
684
685 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
686 r600_is_vertex_format_supported(format)) {
687 retval |= PIPE_BIND_VERTEX_BUFFER;
688 }
689
690 if (usage & PIPE_BIND_TRANSFER_READ)
691 retval |= PIPE_BIND_TRANSFER_READ;
692 if (usage & PIPE_BIND_TRANSFER_WRITE)
693 retval |= PIPE_BIND_TRANSFER_WRITE;
694
695 return retval == usage;
696 }
697
698 static void evergreen_set_blend_color(struct pipe_context *ctx,
699 const struct pipe_blend_color *state)
700 {
701 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
702 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
703
704 if (rstate == NULL)
705 return;
706
707 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
708 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL, 0);
709 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL, 0);
710 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL, 0);
711 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL, 0);
712
713 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
714 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
715 r600_context_pipe_state_set(&rctx->ctx, rstate);
716 }
717
718 static void *evergreen_create_blend_state(struct pipe_context *ctx,
719 const struct pipe_blend_state *state)
720 {
721 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
722 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
723 struct r600_pipe_state *rstate;
724 u32 color_control, target_mask;
725 /* FIXME there is more then 8 framebuffer */
726 unsigned blend_cntl[8];
727
728 if (blend == NULL) {
729 return NULL;
730 }
731
732 rstate = &blend->rstate;
733
734 rstate->id = R600_PIPE_STATE_BLEND;
735
736 target_mask = 0;
737 color_control = S_028808_MODE(1);
738 if (state->logicop_enable) {
739 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
740 } else {
741 color_control |= (0xcc << 16);
742 }
743 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
744 if (state->independent_blend_enable) {
745 for (int i = 0; i < 8; i++) {
746 target_mask |= (state->rt[i].colormask << (4 * i));
747 }
748 } else {
749 for (int i = 0; i < 8; i++) {
750 target_mask |= (state->rt[0].colormask << (4 * i));
751 }
752 }
753 blend->cb_target_mask = target_mask;
754
755 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
756 color_control, 0xFFFFFFFD, NULL, 0);
757
758 if (rctx->chip_class != CAYMAN)
759 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
760 else {
761 r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
762 r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
763 }
764
765 for (int i = 0; i < 8; i++) {
766 /* state->rt entries > 0 only written if independent blending */
767 const int j = state->independent_blend_enable ? i : 0;
768
769 unsigned eqRGB = state->rt[j].rgb_func;
770 unsigned srcRGB = state->rt[j].rgb_src_factor;
771 unsigned dstRGB = state->rt[j].rgb_dst_factor;
772 unsigned eqA = state->rt[j].alpha_func;
773 unsigned srcA = state->rt[j].alpha_src_factor;
774 unsigned dstA = state->rt[j].alpha_dst_factor;
775
776 blend_cntl[i] = 0;
777 if (!state->rt[j].blend_enable)
778 continue;
779
780 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
781 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
782 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
783 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
784
785 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
786 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
787 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
788 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
789 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
790 }
791 }
792 for (int i = 0; i < 8; i++) {
793 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL, 0);
794 }
795
796 return rstate;
797 }
798
799 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
800 const struct pipe_depth_stencil_alpha_state *state)
801 {
802 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
803 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
804 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
805 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
806 struct r600_pipe_state *rstate;
807
808 if (dsa == NULL) {
809 return NULL;
810 }
811
812 rstate = &dsa->rstate;
813
814 rstate->id = R600_PIPE_STATE_DSA;
815 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
816 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
817 stencil_ref_mask = 0;
818 stencil_ref_mask_bf = 0;
819 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
820 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
821 S_028800_ZFUNC(state->depth.func);
822
823 /* stencil */
824 if (state->stencil[0].enabled) {
825 db_depth_control |= S_028800_STENCIL_ENABLE(1);
826 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
827 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
828 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
829 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
830
831
832 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
833 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
834 if (state->stencil[1].enabled) {
835 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
836 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
837 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
838 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
839 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
840 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
841 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
842 }
843 }
844
845 /* alpha */
846 alpha_test_control = 0;
847 alpha_ref = 0;
848 if (state->alpha.enabled) {
849 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
850 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
851 alpha_ref = fui(state->alpha.ref_value);
852 }
853 dsa->alpha_ref = alpha_ref;
854
855 /* misc */
856 db_render_control = 0;
857 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
858 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
859 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
860 /* TODO db_render_override depends on query */
861 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
862 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
863 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
864 r600_pipe_state_add_reg(rstate,
865 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
866 0xFFFFFFFF & C_028430_STENCILREF, NULL, 0);
867 r600_pipe_state_add_reg(rstate,
868 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
869 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL, 0);
870 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
871 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL, 0);
872 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
873 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
874 * evergreen_pipe_shader_ps().*/
875 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL, 0);
876 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL, 0);
877 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL, 0);
878 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL, 0);
879 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL, 0);
880 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL, 0);
881 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL, 0);
882
883 return rstate;
884 }
885
886 static void *evergreen_create_rs_state(struct pipe_context *ctx,
887 const struct pipe_rasterizer_state *state)
888 {
889 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
890 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
891 struct r600_pipe_state *rstate;
892 unsigned tmp;
893 unsigned prov_vtx = 1, polygon_dual_mode;
894 unsigned clip_rule;
895
896 if (rs == NULL) {
897 return NULL;
898 }
899
900 rstate = &rs->rstate;
901 rs->clamp_vertex_color = state->clamp_vertex_color;
902 rs->clamp_fragment_color = state->clamp_fragment_color;
903 rs->flatshade = state->flatshade;
904 rs->sprite_coord_enable = state->sprite_coord_enable;
905
906 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
907
908 /* offset */
909 rs->offset_units = state->offset_units;
910 rs->offset_scale = state->offset_scale * 12.0f;
911
912 rstate->id = R600_PIPE_STATE_RASTERIZER;
913 if (state->flatshade_first)
914 prov_vtx = 0;
915 tmp = S_0286D4_FLAT_SHADE_ENA(state->flatshade);
916 if (state->sprite_coord_enable) {
917 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
918 S_0286D4_PNT_SPRITE_OVRD_X(2) |
919 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
920 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
921 S_0286D4_PNT_SPRITE_OVRD_W(1);
922 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
923 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
924 }
925 }
926 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL, 0);
927
928 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
929 state->fill_back != PIPE_POLYGON_MODE_FILL);
930 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
931 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
932 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
933 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
934 S_028814_FACE(!state->front_ccw) |
935 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
936 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
937 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
938 S_028814_POLY_MODE(polygon_dual_mode) |
939 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
940 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL, 0);
941 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
942 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
943 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL, 0);
944 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
945 /* point size 12.4 fixed point */
946 tmp = (unsigned)(state->point_size * 8.0);
947 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
948 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL, 0);
949
950 tmp = (unsigned)state->line_width * 8;
951 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
952
953 if (state->line_stipple_enable) {
954 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE,
955 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
956 S_028A0C_REPEAT_COUNT(state->line_stipple_factor),
957 0x9FFFFFFF, NULL, 0);
958 }
959
960 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
961 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
962 0xFFFFFFFF, NULL, 0);
963
964 if (rctx->chip_class == CAYMAN) {
965 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
966 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
967 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
968 0xFFFFFFFF, NULL, 0);
969 r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
970 r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
971 r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
972 r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
973
974
975 } else {
976 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
977
978 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
979 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
980 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
981 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
982
983 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
984 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
985 0xFFFFFFFF, NULL, 0);
986 }
987 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), 0xFFFFFFFF, NULL, 0);
988 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0);
989 return rstate;
990 }
991
992 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
993 const struct pipe_sampler_state *state)
994 {
995 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
996 union util_color uc;
997 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
998
999 if (rstate == NULL) {
1000 return NULL;
1001 }
1002
1003 rstate->id = R600_PIPE_STATE_SAMPLER;
1004 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1005 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1006 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1007 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1008 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1009 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1010 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1011 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1012 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1013 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1014 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL, 0);
1015 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1016 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
1017 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
1018 0xFFFFFFFF, NULL, 0);
1019 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
1020 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
1021 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
1022 S_03C008_TYPE(1),
1023 0xFFFFFFFF, NULL, 0);
1024
1025 if (uc.ui) {
1026 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), 0xFFFFFFFF, NULL, 0);
1027 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), 0xFFFFFFFF, NULL, 0);
1028 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), 0xFFFFFFFF, NULL, 0);
1029 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), 0xFFFFFFFF, NULL, 0);
1030 }
1031 return rstate;
1032 }
1033
1034 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
1035 struct pipe_resource *texture,
1036 const struct pipe_sampler_view *state)
1037 {
1038 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1039 struct r600_pipe_resource_state *rstate;
1040 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1041 unsigned format, endian;
1042 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1043 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1044 unsigned height, depth;
1045
1046 if (view == NULL)
1047 return NULL;
1048 rstate = &view->state;
1049
1050 /* initialize base object */
1051 view->base = *state;
1052 view->base.texture = NULL;
1053 pipe_reference(NULL, &texture->reference);
1054 view->base.texture = texture;
1055 view->base.reference.count = 1;
1056 view->base.context = ctx;
1057
1058 swizzle[0] = state->swizzle_r;
1059 swizzle[1] = state->swizzle_g;
1060 swizzle[2] = state->swizzle_b;
1061 swizzle[3] = state->swizzle_a;
1062
1063 format = r600_translate_texformat(ctx->screen, state->format,
1064 swizzle,
1065 &word4, &yuv_format);
1066 if (format == ~0) {
1067 format = 0;
1068 }
1069
1070 if (tmp->depth && !tmp->is_flushing_texture) {
1071 r600_texture_depth_flush(ctx, texture, TRUE);
1072 tmp = tmp->flushed_depth_texture;
1073 }
1074
1075 endian = r600_colorformat_endian_swap(format);
1076
1077 height = texture->height0;
1078 depth = texture->depth0;
1079
1080 pitch = align(tmp->pitch_in_blocks[0] *
1081 util_format_get_blockwidth(state->format), 8);
1082 array_mode = tmp->array_mode[0];
1083 tile_type = tmp->tile_type;
1084
1085 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1086 height = 1;
1087 depth = texture->array_size;
1088 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1089 depth = texture->array_size;
1090 }
1091
1092 rstate->bo[0] = &tmp->resource;
1093 rstate->bo[1] = &tmp->resource;
1094 rstate->bo_usage[0] = RADEON_USAGE_READ;
1095 rstate->bo_usage[1] = RADEON_USAGE_READ;
1096
1097 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1098 S_030000_PITCH((pitch / 8) - 1) |
1099 S_030000_NON_DISP_TILING_ORDER(tile_type) |
1100 S_030000_TEX_WIDTH(texture->width0 - 1));
1101 rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1102 S_030004_TEX_DEPTH(depth - 1) |
1103 S_030004_ARRAY_MODE(array_mode));
1104 rstate->val[2] = tmp->offset[0] >> 8;
1105 rstate->val[3] = tmp->offset[1] >> 8;
1106 rstate->val[4] = (word4 |
1107 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1108 S_030010_ENDIAN_SWAP(endian) |
1109 S_030010_BASE_LEVEL(state->u.tex.first_level));
1110 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1111 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1112 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1113 rstate->val[6] = (S_030018_MAX_ANISO(4 /* max 16 samples */));
1114 rstate->val[7] = (S_03001C_DATA_FORMAT(format) |
1115 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE));
1116
1117 return &view->base;
1118 }
1119
1120 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1121 struct pipe_sampler_view **views)
1122 {
1123 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1124 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1125
1126 for (int i = 0; i < count; i++) {
1127 if (resource[i]) {
1128 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
1129 i + R600_MAX_CONST_BUFFERS);
1130 }
1131 }
1132 }
1133
1134 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1135 struct pipe_sampler_view **views)
1136 {
1137 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1138 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1139 int i;
1140 int has_depth = 0;
1141
1142 for (i = 0; i < count; i++) {
1143 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1144 if (resource[i]) {
1145 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1146 has_depth = 1;
1147 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
1148 i + R600_MAX_CONST_BUFFERS);
1149 } else
1150 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1151 i + R600_MAX_CONST_BUFFERS);
1152
1153 pipe_sampler_view_reference(
1154 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1155 views[i]);
1156 } else {
1157 if (resource[i]) {
1158 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1159 has_depth = 1;
1160 }
1161 }
1162 }
1163 for (i = count; i < NUM_TEX_UNITS; i++) {
1164 if (rctx->ps_samplers.views[i]) {
1165 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1166 i + R600_MAX_CONST_BUFFERS);
1167 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1168 }
1169 }
1170 rctx->have_depth_texture = has_depth;
1171 rctx->ps_samplers.n_views = count;
1172 }
1173
1174 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1175 {
1176 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1177 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1178
1179
1180 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1181 rctx->ps_samplers.n_samplers = count;
1182
1183 for (int i = 0; i < count; i++) {
1184 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
1185 }
1186 }
1187
1188 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1189 {
1190 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1191 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1192
1193 for (int i = 0; i < count; i++) {
1194 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
1195 }
1196 }
1197
1198 static void evergreen_set_clip_state(struct pipe_context *ctx,
1199 const struct pipe_clip_state *state)
1200 {
1201 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1202 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1203
1204 if (rstate == NULL)
1205 return;
1206
1207 rctx->clip = *state;
1208 rstate->id = R600_PIPE_STATE_CLIP;
1209 for (int i = 0; i < state->nr; i++) {
1210 r600_pipe_state_add_reg(rstate,
1211 R_0285BC_PA_CL_UCP0_X + i * 16,
1212 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL, 0);
1213 r600_pipe_state_add_reg(rstate,
1214 R_0285C0_PA_CL_UCP0_Y + i * 16,
1215 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL, 0);
1216 r600_pipe_state_add_reg(rstate,
1217 R_0285C4_PA_CL_UCP0_Z + i * 16,
1218 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL, 0);
1219 r600_pipe_state_add_reg(rstate,
1220 R_0285C8_PA_CL_UCP0_W + i * 16,
1221 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL, 0);
1222 }
1223 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1224 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
1225 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
1226 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL, 0);
1227
1228 free(rctx->states[R600_PIPE_STATE_CLIP]);
1229 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1230 r600_context_pipe_state_set(&rctx->ctx, rstate);
1231 }
1232
1233 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1234 const struct pipe_poly_stipple *state)
1235 {
1236 }
1237
1238 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1239 {
1240 }
1241
1242 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1243 const struct pipe_scissor_state *state)
1244 {
1245 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1246 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1247 u32 tl, br;
1248
1249 if (rstate == NULL)
1250 return;
1251
1252 rstate->id = R600_PIPE_STATE_SCISSOR;
1253 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1254 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1255 r600_pipe_state_add_reg(rstate,
1256 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1257 0xFFFFFFFF, NULL, 0);
1258 r600_pipe_state_add_reg(rstate,
1259 R_028214_PA_SC_CLIPRECT_0_BR, br,
1260 0xFFFFFFFF, NULL, 0);
1261 r600_pipe_state_add_reg(rstate,
1262 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1263 0xFFFFFFFF, NULL, 0);
1264 r600_pipe_state_add_reg(rstate,
1265 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1266 0xFFFFFFFF, NULL, 0);
1267 r600_pipe_state_add_reg(rstate,
1268 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1269 0xFFFFFFFF, NULL, 0);
1270 r600_pipe_state_add_reg(rstate,
1271 R_028224_PA_SC_CLIPRECT_2_BR, br,
1272 0xFFFFFFFF, NULL, 0);
1273 r600_pipe_state_add_reg(rstate,
1274 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1275 0xFFFFFFFF, NULL, 0);
1276 r600_pipe_state_add_reg(rstate,
1277 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1278 0xFFFFFFFF, NULL, 0);
1279
1280 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1281 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1282 r600_context_pipe_state_set(&rctx->ctx, rstate);
1283 }
1284
1285 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
1286 const struct pipe_stencil_ref *state)
1287 {
1288 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1289 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1290 u32 tmp;
1291
1292 if (rstate == NULL)
1293 return;
1294
1295 rctx->stencil_ref = *state;
1296 rstate->id = R600_PIPE_STATE_STENCIL_REF;
1297 tmp = S_028430_STENCILREF(state->ref_value[0]);
1298 r600_pipe_state_add_reg(rstate,
1299 R_028430_DB_STENCILREFMASK, tmp,
1300 ~C_028430_STENCILREF, NULL, 0);
1301 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1302 r600_pipe_state_add_reg(rstate,
1303 R_028434_DB_STENCILREFMASK_BF, tmp,
1304 ~C_028434_STENCILREF_BF, NULL, 0);
1305
1306 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1307 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1308 r600_context_pipe_state_set(&rctx->ctx, rstate);
1309 }
1310
1311 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1312 const struct pipe_viewport_state *state)
1313 {
1314 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1315 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1316
1317 if (rstate == NULL)
1318 return;
1319
1320 rctx->viewport = *state;
1321 rstate->id = R600_PIPE_STATE_VIEWPORT;
1322 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
1323 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1324 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL, 0);
1325 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL, 0);
1326 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL, 0);
1327 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL, 0);
1328 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL, 0);
1329 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL, 0);
1330 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL, 0);
1331
1332 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1333 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1334 r600_context_pipe_state_set(&rctx->ctx, rstate);
1335 }
1336
1337 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1338 const struct pipe_framebuffer_state *state, int cb)
1339 {
1340 struct r600_resource_texture *rtex;
1341 struct r600_surface *surf;
1342 unsigned level = state->cbufs[cb]->u.tex.level;
1343 unsigned pitch, slice;
1344 unsigned color_info;
1345 unsigned format, swap, ntype, endian;
1346 unsigned offset;
1347 unsigned tile_type;
1348 const struct util_format_description *desc;
1349 int i;
1350 unsigned blend_clamp = 0, blend_bypass = 0;
1351
1352 surf = (struct r600_surface *)state->cbufs[cb];
1353 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1354
1355 if (rtex->depth)
1356 rctx->have_depth_fb = TRUE;
1357
1358 if (rtex->depth && !rtex->is_flushing_texture) {
1359 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1360 rtex = rtex->flushed_depth_texture;
1361 }
1362
1363 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1364 offset = r600_texture_get_offset(rtex,
1365 level, state->cbufs[cb]->u.tex.first_layer);
1366 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1367 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1368 desc = util_format_description(surf->base.format);
1369 for (i = 0; i < 4; i++) {
1370 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1371 break;
1372 }
1373 }
1374
1375 ntype = V_028C70_NUMBER_UNORM;
1376 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1377 ntype = V_028C70_NUMBER_SRGB;
1378 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1379 if (desc->channel[i].normalized)
1380 ntype = V_028C70_NUMBER_SNORM;
1381 else if (desc->channel[i].pure_integer)
1382 ntype = V_028C70_NUMBER_SINT;
1383 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1384 if (desc->channel[i].normalized)
1385 ntype = V_028C70_NUMBER_UNORM;
1386 else if (desc->channel[i].pure_integer)
1387 ntype = V_028C70_NUMBER_UINT;
1388 }
1389
1390 format = r600_translate_colorformat(surf->base.format);
1391 swap = r600_translate_colorswap(surf->base.format);
1392 if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1393 endian = ENDIAN_NONE;
1394 } else {
1395 endian = r600_colorformat_endian_swap(format);
1396 }
1397
1398 /* blend clamp should be set for all NORM/SRGB types */
1399 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1400 ntype == V_028C70_NUMBER_SRGB)
1401 blend_clamp = 1;
1402
1403 /* set blend bypass according to docs if SINT/UINT or
1404 8/24 COLOR variants */
1405 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1406 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1407 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1408 blend_clamp = 0;
1409 blend_bypass = 1;
1410 }
1411
1412 color_info = S_028C70_FORMAT(format) |
1413 S_028C70_COMP_SWAP(swap) |
1414 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
1415 S_028C70_BLEND_CLAMP(blend_clamp) |
1416 S_028C70_BLEND_BYPASS(blend_bypass) |
1417 S_028C70_NUMBER_TYPE(ntype) |
1418 S_028C70_ENDIAN(endian);
1419
1420 /* EXPORT_NORM is an optimzation that can be enabled for better
1421 * performance in certain cases.
1422 * EXPORT_NORM can be enabled if:
1423 * - 11-bit or smaller UNORM/SNORM/SRGB
1424 * - 16-bit or smaller FLOAT
1425 */
1426 /* FIXME: This should probably be the same for all CBs if we want
1427 * useful alpha tests. */
1428 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1429 ((desc->channel[i].size < 12 &&
1430 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1431 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1432 (desc->channel[i].size < 17 &&
1433 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1434 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1435 rctx->export_16bpc = true;
1436 } else {
1437 rctx->export_16bpc = false;
1438 }
1439 rctx->alpha_ref_dirty = true;
1440
1441 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1442 tile_type = rtex->tile_type;
1443 } else /* workaround for linear buffers */
1444 tile_type = 1;
1445
1446 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1447 r600_pipe_state_add_reg(rstate,
1448 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1449 offset >> 8, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1450 r600_pipe_state_add_reg(rstate,
1451 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1452 0x0, 0xFFFFFFFF, NULL, 0);
1453 r600_pipe_state_add_reg(rstate,
1454 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1455 color_info, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1456 r600_pipe_state_add_reg(rstate,
1457 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1458 S_028C64_PITCH_TILE_MAX(pitch),
1459 0xFFFFFFFF, NULL, 0);
1460 r600_pipe_state_add_reg(rstate,
1461 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1462 S_028C68_SLICE_TILE_MAX(slice),
1463 0xFFFFFFFF, NULL, 0);
1464 r600_pipe_state_add_reg(rstate,
1465 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1466 0x00000000, 0xFFFFFFFF, NULL, 0);
1467 r600_pipe_state_add_reg(rstate,
1468 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1469 S_028C74_NON_DISP_TILING_ORDER(tile_type),
1470 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1471 }
1472
1473 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1474 const struct pipe_framebuffer_state *state)
1475 {
1476 struct r600_resource_texture *rtex;
1477 struct r600_surface *surf;
1478 unsigned level, first_layer, pitch, slice, format, offset, array_mode;
1479
1480 if (state->zsbuf == NULL)
1481 return;
1482
1483 surf = (struct r600_surface *)state->zsbuf;
1484 level = surf->base.u.tex.level;
1485 rtex = (struct r600_resource_texture*)surf->base.texture;
1486
1487 /* XXX remove this once tiling is properly supported */
1488 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1489 V_028C70_ARRAY_1D_TILED_THIN1;
1490
1491 first_layer = surf->base.u.tex.first_layer;
1492 offset = r600_texture_get_offset(rtex, level, first_layer);
1493 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1494 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1495 format = r600_translate_dbformat(rtex->real_format);
1496
1497 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1498 offset >> 8, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1499 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1500 offset >> 8, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1501 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0);
1502
1503 if (rtex->stencil) {
1504 uint32_t stencil_offset =
1505 r600_texture_get_offset(rtex->stencil, level, first_layer);
1506
1507 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1508 stencil_offset >> 8, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1509 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1510 stencil_offset >> 8, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1511 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1512 1, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1513 } else {
1514 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1515 0, 0xFFFFFFFF, NULL, RADEON_USAGE_READWRITE);
1516 }
1517
1518 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
1519 S_028040_ARRAY_MODE(array_mode) | S_028040_FORMAT(format),
1520 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1521 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1522 S_028058_PITCH_TILE_MAX(pitch),
1523 0xFFFFFFFF, NULL, 0);
1524 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1525 S_02805C_SLICE_TILE_MAX(slice),
1526 0xFFFFFFFF, NULL, 0);
1527 }
1528
1529 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1530 const struct pipe_framebuffer_state *state)
1531 {
1532 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1533 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1534 u32 shader_mask, tl, br, target_mask;
1535 int tl_x, tl_y, br_x, br_y;
1536
1537 if (rstate == NULL)
1538 return;
1539
1540 evergreen_context_flush_dest_caches(&rctx->ctx);
1541 rctx->ctx.num_dest_buffers = state->nr_cbufs;
1542
1543 /* unreference old buffer and reference new one */
1544 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1545
1546 util_copy_framebuffer_state(&rctx->framebuffer, state);
1547
1548 /* build states */
1549 rctx->have_depth_fb = 0;
1550 rctx->nr_cbufs = state->nr_cbufs;
1551 for (int i = 0; i < state->nr_cbufs; i++) {
1552 evergreen_cb(rctx, rstate, state, i);
1553 }
1554 if (state->zsbuf) {
1555 evergreen_db(rctx, rstate, state);
1556 rctx->ctx.num_dest_buffers++;
1557 }
1558
1559 target_mask = 0x00000000;
1560 target_mask = 0xFFFFFFFF;
1561 shader_mask = 0;
1562 for (int i = 0; i < state->nr_cbufs; i++) {
1563 target_mask ^= 0xf << (i * 4);
1564 shader_mask |= 0xf << (i * 4);
1565 }
1566 tl_x = 0;
1567 tl_y = 0;
1568 br_x = state->width;
1569 br_y = state->height;
1570 /* EG hw workaround */
1571 if (br_x == 0)
1572 tl_x = 1;
1573 if (br_y == 0)
1574 tl_y = 1;
1575 /* cayman hw workaround */
1576 if (rctx->chip_class == CAYMAN) {
1577 if (br_x == 1 && br_y == 1)
1578 br_x = 2;
1579 }
1580 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1581 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1582
1583 r600_pipe_state_add_reg(rstate,
1584 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1585 0xFFFFFFFF, NULL, 0);
1586 r600_pipe_state_add_reg(rstate,
1587 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1588 0xFFFFFFFF, NULL, 0);
1589 r600_pipe_state_add_reg(rstate,
1590 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1591 0xFFFFFFFF, NULL, 0);
1592 r600_pipe_state_add_reg(rstate,
1593 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1594 0xFFFFFFFF, NULL, 0);
1595 r600_pipe_state_add_reg(rstate,
1596 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1597 0xFFFFFFFF, NULL, 0);
1598 r600_pipe_state_add_reg(rstate,
1599 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1600 0xFFFFFFFF, NULL, 0);
1601 r600_pipe_state_add_reg(rstate,
1602 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1603 0xFFFFFFFF, NULL, 0);
1604 r600_pipe_state_add_reg(rstate,
1605 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1606 0xFFFFFFFF, NULL, 0);
1607 r600_pipe_state_add_reg(rstate,
1608 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1609 0xFFFFFFFF, NULL, 0);
1610 r600_pipe_state_add_reg(rstate,
1611 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1612 0xFFFFFFFF, NULL, 0);
1613
1614 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1615 0x00000000, target_mask, NULL, 0);
1616 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1617 shader_mask, 0xFFFFFFFF, NULL, 0);
1618
1619
1620 if (rctx->chip_class == CAYMAN) {
1621 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1622 0x00000000, 0xFFFFFFFF, NULL, 0);
1623 } else {
1624 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1625 0x00000000, 0xFFFFFFFF, NULL, 0);
1626 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1627 0x00000000, 0xFFFFFFFF, NULL, 0);
1628 }
1629
1630 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1631 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1632 r600_context_pipe_state_set(&rctx->ctx, rstate);
1633
1634 if (state->zsbuf) {
1635 evergreen_polygon_offset_update(rctx);
1636 }
1637 }
1638
1639 static void evergreen_texture_barrier(struct pipe_context *ctx)
1640 {
1641 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1642
1643 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1644 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1645 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1646 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1647 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
1648 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
1649 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
1650 }
1651
1652 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
1653 {
1654 rctx->context.create_blend_state = evergreen_create_blend_state;
1655 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1656 rctx->context.create_fs_state = r600_create_shader_state;
1657 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1658 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1659 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1660 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1661 rctx->context.create_vs_state = r600_create_shader_state;
1662 rctx->context.bind_blend_state = r600_bind_blend_state;
1663 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1664 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1665 rctx->context.bind_fs_state = r600_bind_ps_shader;
1666 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1667 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1668 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1669 rctx->context.bind_vs_state = r600_bind_vs_shader;
1670 rctx->context.delete_blend_state = r600_delete_state;
1671 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1672 rctx->context.delete_fs_state = r600_delete_ps_shader;
1673 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1674 rctx->context.delete_sampler_state = r600_delete_state;
1675 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1676 rctx->context.delete_vs_state = r600_delete_vs_shader;
1677 rctx->context.set_blend_color = evergreen_set_blend_color;
1678 rctx->context.set_clip_state = evergreen_set_clip_state;
1679 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1680 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1681 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1682 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1683 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1684 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1685 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1686 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1687 rctx->context.set_index_buffer = r600_set_index_buffer;
1688 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1689 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1690 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1691 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1692 rctx->context.texture_barrier = evergreen_texture_barrier;
1693 rctx->context.create_stream_output_target = r600_create_so_target;
1694 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1695 rctx->context.set_stream_output_targets = r600_set_so_targets;
1696 }
1697
1698 static void cayman_init_config(struct r600_pipe_context *rctx)
1699 {
1700 struct r600_pipe_state *rstate = &rctx->config;
1701 unsigned tmp;
1702
1703 tmp = 0x00000000;
1704 tmp |= S_008C00_EXPORT_SRC_C(1);
1705 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
1706
1707 /* always set the temp clauses */
1708 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), 0xFFFFFFFF, NULL, 0);
1709 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL, 0);
1710 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL, 0);
1711 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL, 0);
1712
1713 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL, 0);
1714
1715 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1716 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1717 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
1718 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
1719 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL, 0);
1720 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL, 0);
1721 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
1722 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
1723 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1724 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1725 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1726 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1727 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL, 0);
1728 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
1729 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
1730 r600_pipe_state_add_reg(rstate, R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), 0xFFFFFFFF, NULL, 0);
1731 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL, 0);
1732 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL, 0);
1733 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL, 0);
1734
1735 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL, 0);
1736 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL, 0);
1737 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL, 0);
1738 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL, 0);
1739 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL, 0);
1740 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL, 0);
1741 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL, 0);
1742 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL, 0);
1743 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL, 0);
1744 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL, 0);
1745 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL, 0);
1746 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL, 0);
1747 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL, 0);
1748 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL, 0);
1749 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL, 0);
1750 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL, 0);
1751 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL, 0);
1752 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL, 0);
1753 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL, 0);
1754 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL, 0);
1755 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL, 0);
1756 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL, 0);
1757 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL, 0);
1758 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL, 0);
1759 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL, 0);
1760 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL, 0);
1761 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL, 0);
1762 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL, 0);
1763 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL, 0);
1764 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL, 0);
1765 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL, 0);
1766 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL, 0);
1767
1768 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1769
1770 r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, 0xffffffff, NULL, 0);
1771 r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, 0xffffffff, NULL, 0);
1772
1773 r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, 0xFFFFFFFF, NULL, 0);
1774 r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0xFFFFFFFF, NULL, 0);
1775
1776 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, 0xFFFFFFFF, NULL, 0);
1777 r600_context_pipe_state_set(&rctx->ctx, rstate);
1778 }
1779
1780 void evergreen_init_config(struct r600_pipe_context *rctx)
1781 {
1782 struct r600_pipe_state *rstate = &rctx->config;
1783 int ps_prio;
1784 int vs_prio;
1785 int gs_prio;
1786 int es_prio;
1787 int hs_prio, cs_prio, ls_prio;
1788 int num_ps_gprs;
1789 int num_vs_gprs;
1790 int num_gs_gprs;
1791 int num_es_gprs;
1792 int num_hs_gprs;
1793 int num_ls_gprs;
1794 int num_temp_gprs;
1795 int num_ps_threads;
1796 int num_vs_threads;
1797 int num_gs_threads;
1798 int num_es_threads;
1799 int num_hs_threads;
1800 int num_ls_threads;
1801 int num_ps_stack_entries;
1802 int num_vs_stack_entries;
1803 int num_gs_stack_entries;
1804 int num_es_stack_entries;
1805 int num_hs_stack_entries;
1806 int num_ls_stack_entries;
1807 enum radeon_family family;
1808 unsigned tmp;
1809
1810 family = rctx->family;
1811
1812 if (rctx->chip_class == CAYMAN) {
1813 cayman_init_config(rctx);
1814 return;
1815 }
1816
1817 ps_prio = 0;
1818 vs_prio = 1;
1819 gs_prio = 2;
1820 es_prio = 3;
1821 hs_prio = 0;
1822 ls_prio = 0;
1823 cs_prio = 0;
1824
1825 switch (family) {
1826 case CHIP_CEDAR:
1827 default:
1828 num_ps_gprs = 93;
1829 num_vs_gprs = 46;
1830 num_temp_gprs = 4;
1831 num_gs_gprs = 31;
1832 num_es_gprs = 31;
1833 num_hs_gprs = 23;
1834 num_ls_gprs = 23;
1835 num_ps_threads = 96;
1836 num_vs_threads = 16;
1837 num_gs_threads = 16;
1838 num_es_threads = 16;
1839 num_hs_threads = 16;
1840 num_ls_threads = 16;
1841 num_ps_stack_entries = 42;
1842 num_vs_stack_entries = 42;
1843 num_gs_stack_entries = 42;
1844 num_es_stack_entries = 42;
1845 num_hs_stack_entries = 42;
1846 num_ls_stack_entries = 42;
1847 break;
1848 case CHIP_REDWOOD:
1849 num_ps_gprs = 93;
1850 num_vs_gprs = 46;
1851 num_temp_gprs = 4;
1852 num_gs_gprs = 31;
1853 num_es_gprs = 31;
1854 num_hs_gprs = 23;
1855 num_ls_gprs = 23;
1856 num_ps_threads = 128;
1857 num_vs_threads = 20;
1858 num_gs_threads = 20;
1859 num_es_threads = 20;
1860 num_hs_threads = 20;
1861 num_ls_threads = 20;
1862 num_ps_stack_entries = 42;
1863 num_vs_stack_entries = 42;
1864 num_gs_stack_entries = 42;
1865 num_es_stack_entries = 42;
1866 num_hs_stack_entries = 42;
1867 num_ls_stack_entries = 42;
1868 break;
1869 case CHIP_JUNIPER:
1870 num_ps_gprs = 93;
1871 num_vs_gprs = 46;
1872 num_temp_gprs = 4;
1873 num_gs_gprs = 31;
1874 num_es_gprs = 31;
1875 num_hs_gprs = 23;
1876 num_ls_gprs = 23;
1877 num_ps_threads = 128;
1878 num_vs_threads = 20;
1879 num_gs_threads = 20;
1880 num_es_threads = 20;
1881 num_hs_threads = 20;
1882 num_ls_threads = 20;
1883 num_ps_stack_entries = 85;
1884 num_vs_stack_entries = 85;
1885 num_gs_stack_entries = 85;
1886 num_es_stack_entries = 85;
1887 num_hs_stack_entries = 85;
1888 num_ls_stack_entries = 85;
1889 break;
1890 case CHIP_CYPRESS:
1891 case CHIP_HEMLOCK:
1892 num_ps_gprs = 93;
1893 num_vs_gprs = 46;
1894 num_temp_gprs = 4;
1895 num_gs_gprs = 31;
1896 num_es_gprs = 31;
1897 num_hs_gprs = 23;
1898 num_ls_gprs = 23;
1899 num_ps_threads = 128;
1900 num_vs_threads = 20;
1901 num_gs_threads = 20;
1902 num_es_threads = 20;
1903 num_hs_threads = 20;
1904 num_ls_threads = 20;
1905 num_ps_stack_entries = 85;
1906 num_vs_stack_entries = 85;
1907 num_gs_stack_entries = 85;
1908 num_es_stack_entries = 85;
1909 num_hs_stack_entries = 85;
1910 num_ls_stack_entries = 85;
1911 break;
1912 case CHIP_PALM:
1913 num_ps_gprs = 93;
1914 num_vs_gprs = 46;
1915 num_temp_gprs = 4;
1916 num_gs_gprs = 31;
1917 num_es_gprs = 31;
1918 num_hs_gprs = 23;
1919 num_ls_gprs = 23;
1920 num_ps_threads = 96;
1921 num_vs_threads = 16;
1922 num_gs_threads = 16;
1923 num_es_threads = 16;
1924 num_hs_threads = 16;
1925 num_ls_threads = 16;
1926 num_ps_stack_entries = 42;
1927 num_vs_stack_entries = 42;
1928 num_gs_stack_entries = 42;
1929 num_es_stack_entries = 42;
1930 num_hs_stack_entries = 42;
1931 num_ls_stack_entries = 42;
1932 break;
1933 case CHIP_SUMO:
1934 num_ps_gprs = 93;
1935 num_vs_gprs = 46;
1936 num_temp_gprs = 4;
1937 num_gs_gprs = 31;
1938 num_es_gprs = 31;
1939 num_hs_gprs = 23;
1940 num_ls_gprs = 23;
1941 num_ps_threads = 96;
1942 num_vs_threads = 25;
1943 num_gs_threads = 25;
1944 num_es_threads = 25;
1945 num_hs_threads = 25;
1946 num_ls_threads = 25;
1947 num_ps_stack_entries = 42;
1948 num_vs_stack_entries = 42;
1949 num_gs_stack_entries = 42;
1950 num_es_stack_entries = 42;
1951 num_hs_stack_entries = 42;
1952 num_ls_stack_entries = 42;
1953 break;
1954 case CHIP_SUMO2:
1955 num_ps_gprs = 93;
1956 num_vs_gprs = 46;
1957 num_temp_gprs = 4;
1958 num_gs_gprs = 31;
1959 num_es_gprs = 31;
1960 num_hs_gprs = 23;
1961 num_ls_gprs = 23;
1962 num_ps_threads = 96;
1963 num_vs_threads = 25;
1964 num_gs_threads = 25;
1965 num_es_threads = 25;
1966 num_hs_threads = 25;
1967 num_ls_threads = 25;
1968 num_ps_stack_entries = 85;
1969 num_vs_stack_entries = 85;
1970 num_gs_stack_entries = 85;
1971 num_es_stack_entries = 85;
1972 num_hs_stack_entries = 85;
1973 num_ls_stack_entries = 85;
1974 break;
1975 case CHIP_BARTS:
1976 num_ps_gprs = 93;
1977 num_vs_gprs = 46;
1978 num_temp_gprs = 4;
1979 num_gs_gprs = 31;
1980 num_es_gprs = 31;
1981 num_hs_gprs = 23;
1982 num_ls_gprs = 23;
1983 num_ps_threads = 128;
1984 num_vs_threads = 20;
1985 num_gs_threads = 20;
1986 num_es_threads = 20;
1987 num_hs_threads = 20;
1988 num_ls_threads = 20;
1989 num_ps_stack_entries = 85;
1990 num_vs_stack_entries = 85;
1991 num_gs_stack_entries = 85;
1992 num_es_stack_entries = 85;
1993 num_hs_stack_entries = 85;
1994 num_ls_stack_entries = 85;
1995 break;
1996 case CHIP_TURKS:
1997 num_ps_gprs = 93;
1998 num_vs_gprs = 46;
1999 num_temp_gprs = 4;
2000 num_gs_gprs = 31;
2001 num_es_gprs = 31;
2002 num_hs_gprs = 23;
2003 num_ls_gprs = 23;
2004 num_ps_threads = 128;
2005 num_vs_threads = 20;
2006 num_gs_threads = 20;
2007 num_es_threads = 20;
2008 num_hs_threads = 20;
2009 num_ls_threads = 20;
2010 num_ps_stack_entries = 42;
2011 num_vs_stack_entries = 42;
2012 num_gs_stack_entries = 42;
2013 num_es_stack_entries = 42;
2014 num_hs_stack_entries = 42;
2015 num_ls_stack_entries = 42;
2016 break;
2017 case CHIP_CAICOS:
2018 num_ps_gprs = 93;
2019 num_vs_gprs = 46;
2020 num_temp_gprs = 4;
2021 num_gs_gprs = 31;
2022 num_es_gprs = 31;
2023 num_hs_gprs = 23;
2024 num_ls_gprs = 23;
2025 num_ps_threads = 128;
2026 num_vs_threads = 10;
2027 num_gs_threads = 10;
2028 num_es_threads = 10;
2029 num_hs_threads = 10;
2030 num_ls_threads = 10;
2031 num_ps_stack_entries = 42;
2032 num_vs_stack_entries = 42;
2033 num_gs_stack_entries = 42;
2034 num_es_stack_entries = 42;
2035 num_hs_stack_entries = 42;
2036 num_ls_stack_entries = 42;
2037 break;
2038 }
2039
2040 tmp = 0x00000000;
2041 switch (family) {
2042 case CHIP_CEDAR:
2043 case CHIP_PALM:
2044 case CHIP_SUMO:
2045 case CHIP_SUMO2:
2046 case CHIP_CAICOS:
2047 break;
2048 default:
2049 tmp |= S_008C00_VC_ENABLE(1);
2050 break;
2051 }
2052 tmp |= S_008C00_EXPORT_SRC_C(1);
2053 tmp |= S_008C00_CS_PRIO(cs_prio);
2054 tmp |= S_008C00_LS_PRIO(ls_prio);
2055 tmp |= S_008C00_HS_PRIO(hs_prio);
2056 tmp |= S_008C00_PS_PRIO(ps_prio);
2057 tmp |= S_008C00_VS_PRIO(vs_prio);
2058 tmp |= S_008C00_GS_PRIO(gs_prio);
2059 tmp |= S_008C00_ES_PRIO(es_prio);
2060 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
2061
2062 /* enable dynamic GPR resource management */
2063 if (rctx->screen->info.drm_minor >= 7) {
2064 /* always set temp clauses */
2065 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
2066 S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), 0xFFFFFFFF, NULL, 0);
2067 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL, 0);
2068 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL, 0);
2069 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL, 0);
2070 r600_pipe_state_add_reg(rstate, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2071 S_028838_PS_GPRS(0x1e) |
2072 S_028838_VS_GPRS(0x1e) |
2073 S_028838_GS_GPRS(0x1e) |
2074 S_028838_ES_GPRS(0x1e) |
2075 S_028838_HS_GPRS(0x1e) |
2076 S_028838_LS_GPRS(0x1e), 0xFFFFFFFF, NULL, 0); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2077 } else {
2078 tmp = 0;
2079 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2080 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2081 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2082 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2083
2084 tmp = 0;
2085 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
2086 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2087 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2088
2089 tmp = 0;
2090 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2091 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2092 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL, 0);
2093 }
2094
2095 tmp = 0;
2096 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
2097 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2098 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2099 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2100 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2101
2102 tmp = 0;
2103 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
2104 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2105 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2106
2107 tmp = 0;
2108 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2109 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2110 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2111
2112 tmp = 0;
2113 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2114 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2115 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2116
2117 tmp = 0;
2118 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2119 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2120 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL, 0);
2121
2122 tmp = 0;
2123 tmp |= S_008E2C_NUM_PS_LDS(0x1000);
2124 tmp |= S_008E2C_NUM_LS_LDS(0x1000);
2125 r600_pipe_state_add_reg(rstate, R_008E2C_SQ_LDS_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL, 0);
2126
2127 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2128 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL, 0);
2129
2130 #if 0
2131 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL, 0);
2132
2133 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL, 0);
2134 #endif
2135 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL, 0);
2136
2137 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2138 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2139 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2140 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2141 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2142 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2143
2144 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2145 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL, 0);
2146 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL, 0);
2147 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL, 0);
2148
2149 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2150 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2151 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
2152 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
2153 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL, 0);
2154 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL, 0);
2155 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
2156 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
2157 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2158 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2159 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2160 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2161 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL, 0);
2162 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
2163 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
2164 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL, 0);
2165 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL, 0);
2166 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL, 0);
2167
2168 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL, 0);
2169 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL, 0);
2170 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL, 0);
2171 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL, 0);
2172 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL, 0);
2173 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL, 0);
2174 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL, 0);
2175 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL, 0);
2176 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL, 0);
2177 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL, 0);
2178 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL, 0);
2179 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL, 0);
2180 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL, 0);
2181 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL, 0);
2182 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL, 0);
2183 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL, 0);
2184 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL, 0);
2185 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL, 0);
2186 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL, 0);
2187 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL, 0);
2188 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL, 0);
2189 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL, 0);
2190 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL, 0);
2191 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL, 0);
2192 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL, 0);
2193 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL, 0);
2194 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL, 0);
2195 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL, 0);
2196 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL, 0);
2197 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL, 0);
2198 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL, 0);
2199 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL, 0);
2200
2201 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2202
2203 r600_context_pipe_state_set(&rctx->ctx, rstate);
2204 }
2205
2206 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
2207 {
2208 struct r600_pipe_state state;
2209
2210 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2211 state.nregs = 0;
2212 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2213 float offset_units = rctx->rasterizer->offset_units;
2214 unsigned offset_db_fmt_cntl = 0, depth;
2215
2216 switch (rctx->framebuffer.zsbuf->texture->format) {
2217 case PIPE_FORMAT_Z24X8_UNORM:
2218 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2219 depth = -24;
2220 offset_units *= 2.0f;
2221 break;
2222 case PIPE_FORMAT_Z32_FLOAT:
2223 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2224 depth = -23;
2225 offset_units *= 1.0f;
2226 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2227 break;
2228 case PIPE_FORMAT_Z16_UNORM:
2229 depth = -16;
2230 offset_units *= 4.0f;
2231 break;
2232 default:
2233 return;
2234 }
2235 /* FIXME some of those reg can be computed with cso */
2236 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2237 r600_pipe_state_add_reg(&state,
2238 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2239 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
2240 r600_pipe_state_add_reg(&state,
2241 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2242 fui(offset_units), 0xFFFFFFFF, NULL, 0);
2243 r600_pipe_state_add_reg(&state,
2244 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2245 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
2246 r600_pipe_state_add_reg(&state,
2247 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2248 fui(offset_units), 0xFFFFFFFF, NULL, 0);
2249 r600_pipe_state_add_reg(&state,
2250 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2251 offset_db_fmt_cntl, 0xFFFFFFFF, NULL, 0);
2252 r600_context_pipe_state_set(&rctx->ctx, &state);
2253 }
2254 }
2255
2256 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2257 {
2258 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2259 struct r600_pipe_state *rstate = &shader->rstate;
2260 struct r600_shader *rshader = &shader->shader;
2261 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2262 int pos_index = -1, face_index = -1;
2263 int ninterp = 0;
2264 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2265 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2266
2267 rstate->nregs = 0;
2268
2269 db_shader_control = 0;
2270 for (i = 0; i < rshader->ninput; i++) {
2271 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2272 POSITION goes via GPRs from the SC so isn't counted */
2273 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2274 pos_index = i;
2275 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2276 face_index = i;
2277 else {
2278 ninterp++;
2279 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2280 have_linear = TRUE;
2281 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2282 have_perspective = TRUE;
2283 if (rshader->input[i].centroid)
2284 have_centroid = TRUE;
2285 }
2286
2287 sid = rshader->input[i].spi_sid;
2288
2289 if (sid) {
2290
2291 tmp = S_028644_SEMANTIC(sid);
2292
2293 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
2294 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
2295 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
2296 tmp |= S_028644_FLAT_SHADE(1);
2297 }
2298
2299 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2300 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2301 tmp |= S_028644_PT_SPRITE_TEX(1);
2302 }
2303
2304 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2305 tmp, 0xFFFFFFFF, NULL, 0);
2306
2307 idx++;
2308 }
2309 }
2310
2311 for (i = 0; i < rshader->noutput; i++) {
2312 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2313 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2314 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2315 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2316 }
2317 if (rshader->uses_kill)
2318 db_shader_control |= S_02880C_KILL_ENABLE(1);
2319
2320 exports_ps = 0;
2321 num_cout = 0;
2322 for (i = 0; i < rshader->noutput; i++) {
2323 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2324 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2325 exports_ps |= 1;
2326 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2327 if (rshader->fs_write_all)
2328 num_cout = rshader->nr_cbufs;
2329 else
2330 num_cout++;
2331 }
2332 }
2333 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2334 if (!exports_ps) {
2335 /* always at least export 1 component per pixel */
2336 exports_ps = 2;
2337 }
2338
2339 if (ninterp == 0) {
2340 ninterp = 1;
2341 have_perspective = TRUE;
2342 }
2343
2344 if (!have_perspective && !have_linear)
2345 have_perspective = TRUE;
2346
2347 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2348 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2349 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2350 spi_input_z = 0;
2351 if (pos_index != -1) {
2352 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2353 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2354 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2355 spi_input_z |= 1;
2356 }
2357
2358 spi_ps_in_control_1 = 0;
2359 if (face_index != -1) {
2360 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2361 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2362 }
2363
2364 spi_baryc_cntl = 0;
2365 if (have_perspective)
2366 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2367 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2368 if (have_linear)
2369 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2370 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2371
2372 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2373 spi_ps_in_control_0, 0xFFFFFFFF, NULL, 0);
2374 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2375 spi_ps_in_control_1, 0xFFFFFFFF, NULL, 0);
2376 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2377 0, 0xFFFFFFFF, NULL, 0);
2378 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL, 0);
2379 r600_pipe_state_add_reg(rstate,
2380 R_0286E0_SPI_BARYC_CNTL,
2381 spi_baryc_cntl,
2382 0xFFFFFFFF, NULL, 0);
2383
2384 r600_pipe_state_add_reg(rstate,
2385 R_028840_SQ_PGM_START_PS,
2386 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2387 r600_pipe_state_add_reg(rstate,
2388 R_028844_SQ_PGM_RESOURCES_PS,
2389 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2390 S_028844_PRIME_CACHE_ON_DRAW(1) |
2391 S_028844_STACK_SIZE(rshader->bc.nstack),
2392 0xFFFFFFFF, NULL, 0);
2393 r600_pipe_state_add_reg(rstate,
2394 R_028848_SQ_PGM_RESOURCES_2_PS,
2395 0x0, 0xFFFFFFFF, NULL, 0);
2396 r600_pipe_state_add_reg(rstate,
2397 R_02884C_SQ_PGM_EXPORTS_PS,
2398 exports_ps, 0xFFFFFFFF, NULL, 0);
2399 /* only set some bits here, the other bits are set in the dsa state */
2400 r600_pipe_state_add_reg(rstate,
2401 R_02880C_DB_SHADER_CONTROL,
2402 db_shader_control,
2403 S_02880C_Z_EXPORT_ENABLE(1) |
2404 S_02880C_STENCIL_EXPORT_ENABLE(1) |
2405 S_02880C_KILL_ENABLE(1),
2406 NULL, 0);
2407 r600_pipe_state_add_reg(rstate,
2408 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
2409 0xFFFFFFFF, NULL, 0);
2410
2411 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2412 }
2413
2414 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2415 {
2416 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2417 struct r600_pipe_state *rstate = &shader->rstate;
2418 struct r600_shader *rshader = &shader->shader;
2419 unsigned spi_vs_out_id[10] = {};
2420 unsigned i, tmp, nparams = 0;
2421
2422 /* clear previous register */
2423 rstate->nregs = 0;
2424
2425 for (i = 0; i < rshader->noutput; i++) {
2426 if (rshader->output[i].spi_sid) {
2427 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2428 spi_vs_out_id[nparams / 4] |= tmp;
2429 nparams++;
2430 }
2431 }
2432
2433 for (i = 0; i < 10; i++) {
2434 r600_pipe_state_add_reg(rstate,
2435 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2436 spi_vs_out_id[i], 0xFFFFFFFF, NULL, 0);
2437 }
2438
2439 /* Certain attributes (position, psize, etc.) don't count as params.
2440 * VS is required to export at least one param and r600_shader_from_tgsi()
2441 * takes care of adding a dummy export.
2442 */
2443 if (nparams < 1)
2444 nparams = 1;
2445
2446 r600_pipe_state_add_reg(rstate,
2447 R_0286C4_SPI_VS_OUT_CONFIG,
2448 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2449 0xFFFFFFFF, NULL, 0);
2450 r600_pipe_state_add_reg(rstate,
2451 R_028860_SQ_PGM_RESOURCES_VS,
2452 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2453 S_028860_STACK_SIZE(rshader->bc.nstack),
2454 0xFFFFFFFF, NULL, 0);
2455 r600_pipe_state_add_reg(rstate,
2456 R_028864_SQ_PGM_RESOURCES_2_VS,
2457 0x0, 0xFFFFFFFF, NULL, 0);
2458 r600_pipe_state_add_reg(rstate,
2459 R_02885C_SQ_PGM_START_VS,
2460 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2461
2462 r600_pipe_state_add_reg(rstate,
2463 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2464 0xFFFFFFFF, NULL, 0);
2465 }
2466
2467 void evergreen_fetch_shader(struct pipe_context *ctx,
2468 struct r600_vertex_element *ve)
2469 {
2470 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2471 struct r600_pipe_state *rstate = &ve->rstate;
2472 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2473 rstate->nregs = 0;
2474 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
2475 0x00000000, 0xFFFFFFFF, NULL, 0);
2476 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2477 0,
2478 0xFFFFFFFF, ve->fetch_shader, RADEON_USAGE_READ);
2479 }
2480
2481 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
2482 {
2483 struct pipe_depth_stencil_alpha_state dsa;
2484 struct r600_pipe_state *rstate;
2485
2486 memset(&dsa, 0, sizeof(dsa));
2487
2488 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2489 r600_pipe_state_add_reg(rstate,
2490 R_02880C_DB_SHADER_CONTROL,
2491 0x0,
2492 S_02880C_DUAL_EXPORT_ENABLE(1), NULL, 0);
2493 r600_pipe_state_add_reg(rstate,
2494 R_028000_DB_RENDER_CONTROL,
2495 S_028000_DEPTH_COPY_ENABLE(1) |
2496 S_028000_STENCIL_COPY_ENABLE(1) |
2497 S_028000_COPY_CENTROID(1),
2498 S_028000_DEPTH_COPY_ENABLE(1) |
2499 S_028000_STENCIL_COPY_ENABLE(1) |
2500 S_028000_COPY_CENTROID(1), NULL, 0);
2501 return rstate;
2502 }
2503
2504 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
2505 struct r600_pipe_resource_state *rstate)
2506 {
2507 rstate->id = R600_PIPE_STATE_RESOURCE;
2508
2509 rstate->val[0] = 0;
2510 rstate->bo[0] = NULL;
2511 rstate->val[1] = 0;
2512 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2513 rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2514 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2515 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2516 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2517 rstate->val[4] = 0;
2518 rstate->val[5] = 0;
2519 rstate->val[6] = 0;
2520 rstate->val[7] = 0xc0000000;
2521 }
2522
2523
2524 void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
2525 struct r600_resource *rbuffer,
2526 unsigned offset, unsigned stride,
2527 enum radeon_bo_usage usage)
2528 {
2529 rstate->bo[0] = rbuffer;
2530 rstate->bo_usage[0] = usage;
2531 rstate->val[0] = offset;
2532 rstate->val[1] = rbuffer->buf->size - offset - 1;
2533 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2534 S_030008_STRIDE(stride);
2535 }