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7fd3a368bf7ad2947cd28f1922be167e660c39ba
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_blitter.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
38 #include "util/u_surface.h"
39 #include "util/u_pack_color.h"
40 #include "util/u_memory.h"
41 #include "util/u_inlines.h"
42 #include "util/u_framebuffer.h"
43 #include "pipebuffer/pb_buffer.h"
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "r600_formats.h"
50
51 static uint32_t r600_translate_blend_function(int blend_func)
52 {
53 switch (blend_func) {
54 case PIPE_BLEND_ADD:
55 return V_028780_COMB_DST_PLUS_SRC;
56 case PIPE_BLEND_SUBTRACT:
57 return V_028780_COMB_SRC_MINUS_DST;
58 case PIPE_BLEND_REVERSE_SUBTRACT:
59 return V_028780_COMB_DST_MINUS_SRC;
60 case PIPE_BLEND_MIN:
61 return V_028780_COMB_MIN_DST_SRC;
62 case PIPE_BLEND_MAX:
63 return V_028780_COMB_MAX_DST_SRC;
64 default:
65 R600_ERR("Unknown blend function %d\n", blend_func);
66 assert(0);
67 break;
68 }
69 return 0;
70 }
71
72 static uint32_t r600_translate_blend_factor(int blend_fact)
73 {
74 switch (blend_fact) {
75 case PIPE_BLENDFACTOR_ONE:
76 return V_028780_BLEND_ONE;
77 case PIPE_BLENDFACTOR_SRC_COLOR:
78 return V_028780_BLEND_SRC_COLOR;
79 case PIPE_BLENDFACTOR_SRC_ALPHA:
80 return V_028780_BLEND_SRC_ALPHA;
81 case PIPE_BLENDFACTOR_DST_ALPHA:
82 return V_028780_BLEND_DST_ALPHA;
83 case PIPE_BLENDFACTOR_DST_COLOR:
84 return V_028780_BLEND_DST_COLOR;
85 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
86 return V_028780_BLEND_SRC_ALPHA_SATURATE;
87 case PIPE_BLENDFACTOR_CONST_COLOR:
88 return V_028780_BLEND_CONST_COLOR;
89 case PIPE_BLENDFACTOR_CONST_ALPHA:
90 return V_028780_BLEND_CONST_ALPHA;
91 case PIPE_BLENDFACTOR_ZERO:
92 return V_028780_BLEND_ZERO;
93 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
94 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
95 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
96 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
97 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
98 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
99 case PIPE_BLENDFACTOR_INV_DST_COLOR:
100 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
101 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
102 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
103 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
104 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
105 case PIPE_BLENDFACTOR_SRC1_COLOR:
106 return V_028780_BLEND_SRC1_COLOR;
107 case PIPE_BLENDFACTOR_SRC1_ALPHA:
108 return V_028780_BLEND_SRC1_ALPHA;
109 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
110 return V_028780_BLEND_INV_SRC1_COLOR;
111 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
112 return V_028780_BLEND_INV_SRC1_ALPHA;
113 default:
114 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
115 assert(0);
116 break;
117 }
118 return 0;
119 }
120
121 static uint32_t r600_translate_stencil_op(int s_op)
122 {
123 switch (s_op) {
124 case PIPE_STENCIL_OP_KEEP:
125 return V_028800_STENCIL_KEEP;
126 case PIPE_STENCIL_OP_ZERO:
127 return V_028800_STENCIL_ZERO;
128 case PIPE_STENCIL_OP_REPLACE:
129 return V_028800_STENCIL_REPLACE;
130 case PIPE_STENCIL_OP_INCR:
131 return V_028800_STENCIL_INCR;
132 case PIPE_STENCIL_OP_DECR:
133 return V_028800_STENCIL_DECR;
134 case PIPE_STENCIL_OP_INCR_WRAP:
135 return V_028800_STENCIL_INCR_WRAP;
136 case PIPE_STENCIL_OP_DECR_WRAP:
137 return V_028800_STENCIL_DECR_WRAP;
138 case PIPE_STENCIL_OP_INVERT:
139 return V_028800_STENCIL_INVERT;
140 default:
141 R600_ERR("Unknown stencil op %d", s_op);
142 assert(0);
143 break;
144 }
145 return 0;
146 }
147
148 static uint32_t r600_translate_fill(uint32_t func)
149 {
150 switch(func) {
151 case PIPE_POLYGON_MODE_FILL:
152 return 2;
153 case PIPE_POLYGON_MODE_LINE:
154 return 1;
155 case PIPE_POLYGON_MODE_POINT:
156 return 0;
157 default:
158 assert(0);
159 return 0;
160 }
161 }
162
163 /* translates straight */
164 static uint32_t r600_translate_ds_func(int func)
165 {
166 return func;
167 }
168
169 static unsigned r600_tex_wrap(unsigned wrap)
170 {
171 switch (wrap) {
172 default:
173 case PIPE_TEX_WRAP_REPEAT:
174 return V_03C000_SQ_TEX_WRAP;
175 case PIPE_TEX_WRAP_CLAMP:
176 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
177 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
178 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
179 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
180 return V_03C000_SQ_TEX_CLAMP_BORDER;
181 case PIPE_TEX_WRAP_MIRROR_REPEAT:
182 return V_03C000_SQ_TEX_MIRROR;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP:
184 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
186 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
187 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
188 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
189 }
190 }
191
192 static unsigned r600_tex_filter(unsigned filter)
193 {
194 switch (filter) {
195 default:
196 case PIPE_TEX_FILTER_NEAREST:
197 return V_03C000_SQ_TEX_XY_FILTER_POINT;
198 case PIPE_TEX_FILTER_LINEAR:
199 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
200 }
201 }
202
203 static unsigned r600_tex_mipfilter(unsigned filter)
204 {
205 switch (filter) {
206 case PIPE_TEX_MIPFILTER_NEAREST:
207 return V_03C000_SQ_TEX_Z_FILTER_POINT;
208 case PIPE_TEX_MIPFILTER_LINEAR:
209 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
210 default:
211 case PIPE_TEX_MIPFILTER_NONE:
212 return V_03C000_SQ_TEX_Z_FILTER_NONE;
213 }
214 }
215
216 static unsigned r600_tex_compare(unsigned compare)
217 {
218 switch (compare) {
219 default:
220 case PIPE_FUNC_NEVER:
221 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
222 case PIPE_FUNC_LESS:
223 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
224 case PIPE_FUNC_EQUAL:
225 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
226 case PIPE_FUNC_LEQUAL:
227 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
228 case PIPE_FUNC_GREATER:
229 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
230 case PIPE_FUNC_NOTEQUAL:
231 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
232 case PIPE_FUNC_GEQUAL:
233 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
234 case PIPE_FUNC_ALWAYS:
235 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
236 }
237 }
238
239 static unsigned r600_tex_dim(unsigned dim)
240 {
241 switch (dim) {
242 default:
243 case PIPE_TEXTURE_1D:
244 return V_030000_SQ_TEX_DIM_1D;
245 case PIPE_TEXTURE_1D_ARRAY:
246 return V_030000_SQ_TEX_DIM_1D_ARRAY;
247 case PIPE_TEXTURE_2D:
248 case PIPE_TEXTURE_RECT:
249 return V_030000_SQ_TEX_DIM_2D;
250 case PIPE_TEXTURE_2D_ARRAY:
251 return V_030000_SQ_TEX_DIM_2D_ARRAY;
252 case PIPE_TEXTURE_3D:
253 return V_030000_SQ_TEX_DIM_3D;
254 case PIPE_TEXTURE_CUBE:
255 return V_030000_SQ_TEX_DIM_CUBEMAP;
256 }
257 }
258
259 static uint32_t r600_translate_dbformat(enum pipe_format format)
260 {
261 switch (format) {
262 case PIPE_FORMAT_Z16_UNORM:
263 return V_028040_Z_16;
264 case PIPE_FORMAT_Z24X8_UNORM:
265 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
266 return V_028040_Z_24;
267 case PIPE_FORMAT_Z32_FLOAT:
268 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
269 return V_028040_Z_32_FLOAT;
270 default:
271 return ~0U;
272 }
273 }
274
275 static uint32_t r600_translate_colorswap(enum pipe_format format)
276 {
277 switch (format) {
278 /* 8-bit buffers. */
279 case PIPE_FORMAT_L4A4_UNORM:
280 case PIPE_FORMAT_A4R4_UNORM:
281 return V_028C70_SWAP_ALT;
282
283 case PIPE_FORMAT_A8_UNORM:
284 case PIPE_FORMAT_A8_UINT:
285 case PIPE_FORMAT_A8_SINT:
286 case PIPE_FORMAT_R4A4_UNORM:
287 return V_028C70_SWAP_ALT_REV;
288 case PIPE_FORMAT_I8_UNORM:
289 case PIPE_FORMAT_L8_UNORM:
290 case PIPE_FORMAT_I8_UINT:
291 case PIPE_FORMAT_I8_SINT:
292 case PIPE_FORMAT_L8_UINT:
293 case PIPE_FORMAT_L8_SINT:
294 case PIPE_FORMAT_L8_SRGB:
295 case PIPE_FORMAT_R8_UNORM:
296 case PIPE_FORMAT_R8_SNORM:
297 case PIPE_FORMAT_R8_UINT:
298 case PIPE_FORMAT_R8_SINT:
299 return V_028C70_SWAP_STD;
300
301 /* 16-bit buffers. */
302 case PIPE_FORMAT_B5G6R5_UNORM:
303 return V_028C70_SWAP_STD_REV;
304
305 case PIPE_FORMAT_B5G5R5A1_UNORM:
306 case PIPE_FORMAT_B5G5R5X1_UNORM:
307 return V_028C70_SWAP_ALT;
308
309 case PIPE_FORMAT_B4G4R4A4_UNORM:
310 case PIPE_FORMAT_B4G4R4X4_UNORM:
311 return V_028C70_SWAP_ALT;
312
313 case PIPE_FORMAT_Z16_UNORM:
314 return V_028C70_SWAP_STD;
315
316 case PIPE_FORMAT_L8A8_UNORM:
317 case PIPE_FORMAT_L8A8_UINT:
318 case PIPE_FORMAT_L8A8_SINT:
319 case PIPE_FORMAT_L8A8_SRGB:
320 return V_028C70_SWAP_ALT;
321 case PIPE_FORMAT_R8G8_UNORM:
322 case PIPE_FORMAT_R8G8_UINT:
323 case PIPE_FORMAT_R8G8_SINT:
324 return V_028C70_SWAP_STD;
325
326 case PIPE_FORMAT_R16_UNORM:
327 case PIPE_FORMAT_R16_UINT:
328 case PIPE_FORMAT_R16_SINT:
329 case PIPE_FORMAT_R16_FLOAT:
330 return V_028C70_SWAP_STD;
331
332 /* 32-bit buffers. */
333 case PIPE_FORMAT_A8B8G8R8_SRGB:
334 return V_028C70_SWAP_STD_REV;
335 case PIPE_FORMAT_B8G8R8A8_SRGB:
336 return V_028C70_SWAP_ALT;
337
338 case PIPE_FORMAT_B8G8R8A8_UNORM:
339 case PIPE_FORMAT_B8G8R8X8_UNORM:
340 return V_028C70_SWAP_ALT;
341
342 case PIPE_FORMAT_A8R8G8B8_UNORM:
343 case PIPE_FORMAT_X8R8G8B8_UNORM:
344 return V_028C70_SWAP_ALT_REV;
345 case PIPE_FORMAT_R8G8B8A8_SNORM:
346 case PIPE_FORMAT_R8G8B8A8_UNORM:
347 case PIPE_FORMAT_R8G8B8A8_SSCALED:
348 case PIPE_FORMAT_R8G8B8A8_USCALED:
349 case PIPE_FORMAT_R8G8B8A8_SINT:
350 case PIPE_FORMAT_R8G8B8A8_UINT:
351 case PIPE_FORMAT_R8G8B8X8_UNORM:
352 return V_028C70_SWAP_STD;
353
354 case PIPE_FORMAT_A8B8G8R8_UNORM:
355 case PIPE_FORMAT_X8B8G8R8_UNORM:
356 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
357 return V_028C70_SWAP_STD_REV;
358
359 case PIPE_FORMAT_Z24X8_UNORM:
360 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
361 return V_028C70_SWAP_STD;
362
363 case PIPE_FORMAT_X8Z24_UNORM:
364 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
365 return V_028C70_SWAP_STD;
366
367 case PIPE_FORMAT_R10G10B10A2_UNORM:
368 case PIPE_FORMAT_R10G10B10X2_SNORM:
369 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
370 return V_028C70_SWAP_STD;
371
372 case PIPE_FORMAT_B10G10R10A2_UNORM:
373 case PIPE_FORMAT_B10G10R10A2_UINT:
374 return V_028C70_SWAP_ALT;
375
376 case PIPE_FORMAT_R11G11B10_FLOAT:
377 case PIPE_FORMAT_R32_FLOAT:
378 case PIPE_FORMAT_R32_UINT:
379 case PIPE_FORMAT_R32_SINT:
380 case PIPE_FORMAT_Z32_FLOAT:
381 case PIPE_FORMAT_R16G16_FLOAT:
382 case PIPE_FORMAT_R16G16_UNORM:
383 case PIPE_FORMAT_R16G16_UINT:
384 case PIPE_FORMAT_R16G16_SINT:
385 return V_028C70_SWAP_STD;
386
387 /* 64-bit buffers. */
388 case PIPE_FORMAT_R32G32_FLOAT:
389 case PIPE_FORMAT_R32G32_UINT:
390 case PIPE_FORMAT_R32G32_SINT:
391 case PIPE_FORMAT_R16G16B16A16_UNORM:
392 case PIPE_FORMAT_R16G16B16A16_SNORM:
393 case PIPE_FORMAT_R16G16B16A16_USCALED:
394 case PIPE_FORMAT_R16G16B16A16_SSCALED:
395 case PIPE_FORMAT_R16G16B16A16_UINT:
396 case PIPE_FORMAT_R16G16B16A16_SINT:
397 case PIPE_FORMAT_R16G16B16A16_FLOAT:
398 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
399
400 /* 128-bit buffers. */
401 case PIPE_FORMAT_R32G32B32A32_FLOAT:
402 case PIPE_FORMAT_R32G32B32A32_SNORM:
403 case PIPE_FORMAT_R32G32B32A32_UNORM:
404 case PIPE_FORMAT_R32G32B32A32_SSCALED:
405 case PIPE_FORMAT_R32G32B32A32_USCALED:
406 case PIPE_FORMAT_R32G32B32A32_SINT:
407 case PIPE_FORMAT_R32G32B32A32_UINT:
408 return V_028C70_SWAP_STD;
409 default:
410 R600_ERR("unsupported colorswap format %d\n", format);
411 return ~0U;
412 }
413 return ~0U;
414 }
415
416 static uint32_t r600_translate_colorformat(enum pipe_format format)
417 {
418 switch (format) {
419 /* 8-bit buffers. */
420 case PIPE_FORMAT_A8_UNORM:
421 case PIPE_FORMAT_A8_UINT:
422 case PIPE_FORMAT_A8_SINT:
423 case PIPE_FORMAT_I8_UNORM:
424 case PIPE_FORMAT_I8_UINT:
425 case PIPE_FORMAT_I8_SINT:
426 case PIPE_FORMAT_L8_UNORM:
427 case PIPE_FORMAT_L8_UINT:
428 case PIPE_FORMAT_L8_SINT:
429 case PIPE_FORMAT_L8_SRGB:
430 case PIPE_FORMAT_R8_UNORM:
431 case PIPE_FORMAT_R8_SNORM:
432 case PIPE_FORMAT_R8_UINT:
433 case PIPE_FORMAT_R8_SINT:
434 return V_028C70_COLOR_8;
435
436 /* 16-bit buffers. */
437 case PIPE_FORMAT_B5G6R5_UNORM:
438 return V_028C70_COLOR_5_6_5;
439
440 case PIPE_FORMAT_B5G5R5A1_UNORM:
441 case PIPE_FORMAT_B5G5R5X1_UNORM:
442 return V_028C70_COLOR_1_5_5_5;
443
444 case PIPE_FORMAT_B4G4R4A4_UNORM:
445 case PIPE_FORMAT_B4G4R4X4_UNORM:
446 return V_028C70_COLOR_4_4_4_4;
447
448 case PIPE_FORMAT_Z16_UNORM:
449 return V_028C70_COLOR_16;
450
451 case PIPE_FORMAT_L8A8_UNORM:
452 case PIPE_FORMAT_L8A8_UINT:
453 case PIPE_FORMAT_L8A8_SINT:
454 case PIPE_FORMAT_L8A8_SRGB:
455 case PIPE_FORMAT_R8G8_UNORM:
456 case PIPE_FORMAT_R8G8_UINT:
457 case PIPE_FORMAT_R8G8_SINT:
458 return V_028C70_COLOR_8_8;
459
460 case PIPE_FORMAT_R16_UNORM:
461 case PIPE_FORMAT_R16_UINT:
462 case PIPE_FORMAT_R16_SINT:
463 return V_028C70_COLOR_16;
464
465 case PIPE_FORMAT_R16_FLOAT:
466 return V_028C70_COLOR_16_FLOAT;
467
468 /* 32-bit buffers. */
469 case PIPE_FORMAT_A8B8G8R8_SRGB:
470 case PIPE_FORMAT_A8B8G8R8_UNORM:
471 case PIPE_FORMAT_A8R8G8B8_UNORM:
472 case PIPE_FORMAT_B8G8R8A8_SRGB:
473 case PIPE_FORMAT_B8G8R8A8_UNORM:
474 case PIPE_FORMAT_B8G8R8X8_UNORM:
475 case PIPE_FORMAT_R8G8B8A8_SNORM:
476 case PIPE_FORMAT_R8G8B8A8_UNORM:
477 case PIPE_FORMAT_R8G8B8X8_UNORM:
478 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
479 case PIPE_FORMAT_X8B8G8R8_UNORM:
480 case PIPE_FORMAT_X8R8G8B8_UNORM:
481 case PIPE_FORMAT_R8G8B8_UNORM:
482 case PIPE_FORMAT_R8G8B8A8_SSCALED:
483 case PIPE_FORMAT_R8G8B8A8_USCALED:
484 case PIPE_FORMAT_R8G8B8A8_SINT:
485 case PIPE_FORMAT_R8G8B8A8_UINT:
486 return V_028C70_COLOR_8_8_8_8;
487
488 case PIPE_FORMAT_R10G10B10A2_UNORM:
489 case PIPE_FORMAT_R10G10B10X2_SNORM:
490 case PIPE_FORMAT_B10G10R10A2_UNORM:
491 case PIPE_FORMAT_B10G10R10A2_UINT:
492 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
493 return V_028C70_COLOR_2_10_10_10;
494
495 case PIPE_FORMAT_Z24X8_UNORM:
496 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
497 return V_028C70_COLOR_8_24;
498
499 case PIPE_FORMAT_X8Z24_UNORM:
500 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
501 return V_028C70_COLOR_24_8;
502
503 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
504 return V_028C70_COLOR_X24_8_32_FLOAT;
505
506 case PIPE_FORMAT_R32_UINT:
507 case PIPE_FORMAT_R32_SINT:
508 return V_028C70_COLOR_32;
509
510 case PIPE_FORMAT_R32_FLOAT:
511 case PIPE_FORMAT_Z32_FLOAT:
512 return V_028C70_COLOR_32_FLOAT;
513
514 case PIPE_FORMAT_R16G16_FLOAT:
515 return V_028C70_COLOR_16_16_FLOAT;
516
517 case PIPE_FORMAT_R16G16_SSCALED:
518 case PIPE_FORMAT_R16G16_UNORM:
519 case PIPE_FORMAT_R16G16_UINT:
520 case PIPE_FORMAT_R16G16_SINT:
521 return V_028C70_COLOR_16_16;
522
523 case PIPE_FORMAT_R11G11B10_FLOAT:
524 return V_028C70_COLOR_10_11_11_FLOAT;
525
526 /* 64-bit buffers. */
527 case PIPE_FORMAT_R16G16B16_USCALED:
528 case PIPE_FORMAT_R16G16B16_SSCALED:
529 case PIPE_FORMAT_R16G16B16A16_UINT:
530 case PIPE_FORMAT_R16G16B16A16_SINT:
531 case PIPE_FORMAT_R16G16B16A16_USCALED:
532 case PIPE_FORMAT_R16G16B16A16_SSCALED:
533 case PIPE_FORMAT_R16G16B16A16_UNORM:
534 case PIPE_FORMAT_R16G16B16A16_SNORM:
535 return V_028C70_COLOR_16_16_16_16;
536
537 case PIPE_FORMAT_R16G16B16_FLOAT:
538 case PIPE_FORMAT_R16G16B16A16_FLOAT:
539 return V_028C70_COLOR_16_16_16_16_FLOAT;
540
541 case PIPE_FORMAT_R32G32_FLOAT:
542 return V_028C70_COLOR_32_32_FLOAT;
543
544 case PIPE_FORMAT_R32G32_USCALED:
545 case PIPE_FORMAT_R32G32_SSCALED:
546 case PIPE_FORMAT_R32G32_SINT:
547 case PIPE_FORMAT_R32G32_UINT:
548 return V_028C70_COLOR_32_32;
549
550 /* 96-bit buffers. */
551 case PIPE_FORMAT_R32G32B32_FLOAT:
552 return V_028C70_COLOR_32_32_32_FLOAT;
553
554 /* 128-bit buffers. */
555 case PIPE_FORMAT_R32G32B32A32_SNORM:
556 case PIPE_FORMAT_R32G32B32A32_UNORM:
557 case PIPE_FORMAT_R32G32B32A32_SSCALED:
558 case PIPE_FORMAT_R32G32B32A32_USCALED:
559 case PIPE_FORMAT_R32G32B32A32_SINT:
560 case PIPE_FORMAT_R32G32B32A32_UINT:
561 return V_028C70_COLOR_32_32_32_32;
562 case PIPE_FORMAT_R32G32B32A32_FLOAT:
563 return V_028C70_COLOR_32_32_32_32_FLOAT;
564
565 /* YUV buffers. */
566 case PIPE_FORMAT_UYVY:
567 case PIPE_FORMAT_YUYV:
568 default:
569 return ~0U; /* Unsupported. */
570 }
571 }
572
573 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
574 {
575 if (R600_BIG_ENDIAN) {
576 switch(colorformat) {
577
578 /* 8-bit buffers. */
579 case V_028C70_COLOR_8:
580 return ENDIAN_NONE;
581
582 /* 16-bit buffers. */
583 case V_028C70_COLOR_5_6_5:
584 case V_028C70_COLOR_1_5_5_5:
585 case V_028C70_COLOR_4_4_4_4:
586 case V_028C70_COLOR_16:
587 case V_028C70_COLOR_8_8:
588 return ENDIAN_8IN16;
589
590 /* 32-bit buffers. */
591 case V_028C70_COLOR_8_8_8_8:
592 case V_028C70_COLOR_2_10_10_10:
593 case V_028C70_COLOR_8_24:
594 case V_028C70_COLOR_24_8:
595 case V_028C70_COLOR_32_FLOAT:
596 case V_028C70_COLOR_16_16_FLOAT:
597 case V_028C70_COLOR_16_16:
598 return ENDIAN_8IN32;
599
600 /* 64-bit buffers. */
601 case V_028C70_COLOR_16_16_16_16:
602 case V_028C70_COLOR_16_16_16_16_FLOAT:
603 return ENDIAN_8IN16;
604
605 case V_028C70_COLOR_32_32_FLOAT:
606 case V_028C70_COLOR_32_32:
607 case V_028C70_COLOR_X24_8_32_FLOAT:
608 return ENDIAN_8IN32;
609
610 /* 96-bit buffers. */
611 case V_028C70_COLOR_32_32_32_FLOAT:
612 /* 128-bit buffers. */
613 case V_028C70_COLOR_32_32_32_32_FLOAT:
614 case V_028C70_COLOR_32_32_32_32:
615 return ENDIAN_8IN32;
616 default:
617 return ENDIAN_NONE; /* Unsupported. */
618 }
619 } else {
620 return ENDIAN_NONE;
621 }
622 }
623
624 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
625 {
626 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
627 }
628
629 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
630 {
631 return r600_translate_colorformat(format) != ~0U &&
632 r600_translate_colorswap(format) != ~0U;
633 }
634
635 static bool r600_is_zs_format_supported(enum pipe_format format)
636 {
637 return r600_translate_dbformat(format) != ~0U;
638 }
639
640 boolean evergreen_is_format_supported(struct pipe_screen *screen,
641 enum pipe_format format,
642 enum pipe_texture_target target,
643 unsigned sample_count,
644 unsigned usage)
645 {
646 unsigned retval = 0;
647
648 if (target >= PIPE_MAX_TEXTURE_TYPES) {
649 R600_ERR("r600: unsupported texture type %d\n", target);
650 return FALSE;
651 }
652
653 if (!util_format_is_supported(format, usage))
654 return FALSE;
655
656 /* Multisample */
657 if (sample_count > 1)
658 return FALSE;
659
660 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
661 r600_is_sampler_format_supported(screen, format)) {
662 retval |= PIPE_BIND_SAMPLER_VIEW;
663 }
664
665 if ((usage & (PIPE_BIND_RENDER_TARGET |
666 PIPE_BIND_DISPLAY_TARGET |
667 PIPE_BIND_SCANOUT |
668 PIPE_BIND_SHARED)) &&
669 r600_is_colorbuffer_format_supported(format)) {
670 retval |= usage &
671 (PIPE_BIND_RENDER_TARGET |
672 PIPE_BIND_DISPLAY_TARGET |
673 PIPE_BIND_SCANOUT |
674 PIPE_BIND_SHARED);
675 }
676
677 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
678 r600_is_zs_format_supported(format)) {
679 retval |= PIPE_BIND_DEPTH_STENCIL;
680 }
681
682 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
683 r600_is_vertex_format_supported(format)) {
684 retval |= PIPE_BIND_VERTEX_BUFFER;
685 }
686
687 if (usage & PIPE_BIND_TRANSFER_READ)
688 retval |= PIPE_BIND_TRANSFER_READ;
689 if (usage & PIPE_BIND_TRANSFER_WRITE)
690 retval |= PIPE_BIND_TRANSFER_WRITE;
691
692 return retval == usage;
693 }
694
695 static void evergreen_set_blend_color(struct pipe_context *ctx,
696 const struct pipe_blend_color *state)
697 {
698 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
699 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
700
701 if (rstate == NULL)
702 return;
703
704 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
705 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL, 0);
706 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL, 0);
707 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL, 0);
708 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL, 0);
709
710 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
711 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
712 r600_context_pipe_state_set(&rctx->ctx, rstate);
713 }
714
715 static void *evergreen_create_blend_state(struct pipe_context *ctx,
716 const struct pipe_blend_state *state)
717 {
718 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
719 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
720 struct r600_pipe_state *rstate;
721 u32 color_control, target_mask;
722 /* FIXME there is more then 8 framebuffer */
723 unsigned blend_cntl[8];
724
725 if (blend == NULL) {
726 return NULL;
727 }
728
729 rstate = &blend->rstate;
730
731 rstate->id = R600_PIPE_STATE_BLEND;
732
733 target_mask = 0;
734 color_control = S_028808_MODE(1);
735 if (state->logicop_enable) {
736 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
737 } else {
738 color_control |= (0xcc << 16);
739 }
740 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
741 if (state->independent_blend_enable) {
742 for (int i = 0; i < 8; i++) {
743 target_mask |= (state->rt[i].colormask << (4 * i));
744 }
745 } else {
746 for (int i = 0; i < 8; i++) {
747 target_mask |= (state->rt[0].colormask << (4 * i));
748 }
749 }
750 blend->cb_target_mask = target_mask;
751
752 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
753 color_control, 0xFFFFFFFF, NULL, 0);
754
755 if (rctx->chip_class != CAYMAN)
756 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
757 else {
758 r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
759 r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
760 }
761
762 for (int i = 0; i < 8; i++) {
763 /* state->rt entries > 0 only written if independent blending */
764 const int j = state->independent_blend_enable ? i : 0;
765
766 unsigned eqRGB = state->rt[j].rgb_func;
767 unsigned srcRGB = state->rt[j].rgb_src_factor;
768 unsigned dstRGB = state->rt[j].rgb_dst_factor;
769 unsigned eqA = state->rt[j].alpha_func;
770 unsigned srcA = state->rt[j].alpha_src_factor;
771 unsigned dstA = state->rt[j].alpha_dst_factor;
772
773 blend_cntl[i] = 0;
774 if (!state->rt[j].blend_enable)
775 continue;
776
777 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
778 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
779 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
780 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
781
782 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
783 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
784 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
785 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
786 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
787 }
788 }
789 for (int i = 0; i < 8; i++) {
790 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL, 0);
791 }
792
793 return rstate;
794 }
795
796 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
797 const struct pipe_depth_stencil_alpha_state *state)
798 {
799 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
800 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
801 unsigned db_depth_control, alpha_test_control, alpha_ref;
802 unsigned db_render_override, db_render_control;
803 struct r600_pipe_state *rstate;
804
805 if (dsa == NULL) {
806 return NULL;
807 }
808
809 dsa->valuemask[0] = state->stencil[0].valuemask;
810 dsa->valuemask[1] = state->stencil[1].valuemask;
811 dsa->writemask[0] = state->stencil[0].writemask;
812 dsa->writemask[1] = state->stencil[1].writemask;
813
814 rstate = &dsa->rstate;
815
816 rstate->id = R600_PIPE_STATE_DSA;
817 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
818 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
819 S_028800_ZFUNC(state->depth.func);
820
821 /* stencil */
822 if (state->stencil[0].enabled) {
823 db_depth_control |= S_028800_STENCIL_ENABLE(1);
824 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
825 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
826 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
827 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
828
829 if (state->stencil[1].enabled) {
830 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
831 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
832 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
833 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
834 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
835 }
836 }
837
838 /* alpha */
839 alpha_test_control = 0;
840 alpha_ref = 0;
841 if (state->alpha.enabled) {
842 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
843 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
844 alpha_ref = fui(state->alpha.ref_value);
845 }
846 dsa->alpha_ref = alpha_ref;
847
848 /* misc */
849 db_render_control = 0;
850 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
851 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
852 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
853 /* TODO db_render_override depends on query */
854 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
855 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
856 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
857 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
858 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL, 0);
859 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
860 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
861 * evergreen_pipe_shader_ps().*/
862 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL, 0);
863 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL, 0);
864 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL, 0);
865 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL, 0);
866 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL, 0);
867 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL, 0);
868
869 return rstate;
870 }
871
872 static void *evergreen_create_rs_state(struct pipe_context *ctx,
873 const struct pipe_rasterizer_state *state)
874 {
875 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
876 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
877 struct r600_pipe_state *rstate;
878 unsigned tmp;
879 unsigned prov_vtx = 1, polygon_dual_mode;
880 unsigned clip_rule;
881 float psize_min, psize_max;
882
883 if (rs == NULL) {
884 return NULL;
885 }
886
887 rstate = &rs->rstate;
888 rs->flatshade = state->flatshade;
889 rs->sprite_coord_enable = state->sprite_coord_enable;
890 rs->two_side = state->light_twoside;
891 rs->clip_plane_enable = state->clip_plane_enable;
892
893 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
894
895 /* offset */
896 rs->offset_units = state->offset_units;
897 rs->offset_scale = state->offset_scale * 12.0f;
898
899 rstate->id = R600_PIPE_STATE_RASTERIZER;
900 if (state->flatshade_first)
901 prov_vtx = 0;
902 tmp = S_0286D4_FLAT_SHADE_ENA(1);
903 if (state->sprite_coord_enable) {
904 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
905 S_0286D4_PNT_SPRITE_OVRD_X(2) |
906 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
907 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
908 S_0286D4_PNT_SPRITE_OVRD_W(1);
909 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
910 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
911 }
912 }
913 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL, 0);
914
915 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
916 state->fill_back != PIPE_POLYGON_MODE_FILL);
917 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
918 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
919 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
920 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
921 S_028814_FACE(!state->front_ccw) |
922 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
923 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
924 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
925 S_028814_POLY_MODE(polygon_dual_mode) |
926 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
927 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL, 0);
928 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
929 /* point size 12.4 fixed point */
930 tmp = (unsigned)(state->point_size * 8.0);
931 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
932
933 if (state->point_size_per_vertex) {
934 psize_min = util_get_min_point_size(state);
935 psize_max = 8192;
936 } else {
937 /* Force the point size to be as if the vertex output was disabled. */
938 psize_min = state->point_size;
939 psize_max = state->point_size;
940 }
941 /* Divide by two, because 0.5 = 1 pixel. */
942 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
943 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
944 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
945 0xFFFFFFFF, NULL, 0);
946
947 tmp = (unsigned)state->line_width * 8;
948 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
949
950 if (state->line_stipple_enable) {
951 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE,
952 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
953 S_028A0C_REPEAT_COUNT(state->line_stipple_factor),
954 0x9FFFFFFF, NULL, 0);
955 }
956
957 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
958 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
959 0xFFFFFFFF, NULL, 0);
960
961 if (rctx->chip_class == CAYMAN) {
962 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
963 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
964 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
965 0xFFFFFFFF, NULL, 0);
966 r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
967 r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
968 r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
969 r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
970
971
972 } else {
973 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
974
975 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
976 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
977 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
978 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
979
980 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
981 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
982 0xFFFFFFFF, NULL, 0);
983 }
984 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), 0xFFFFFFFF, NULL, 0);
985 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0);
986 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
987 S_028810_PS_UCP_MODE(3) | S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
988 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
989 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1),
990 ~(C_028810_PS_UCP_MODE & C_028810_ZCLIP_NEAR_DISABLE &
991 C_028810_ZCLIP_FAR_DISABLE &
992 C_028810_DX_LINEAR_ATTR_CLIP_ENA), NULL, 0);
993 return rstate;
994 }
995
996 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
997 const struct pipe_sampler_state *state)
998 {
999 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1000 union util_color uc;
1001 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
1002
1003 if (rstate == NULL) {
1004 return NULL;
1005 }
1006
1007 rstate->id = R600_PIPE_STATE_SAMPLER;
1008 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1009 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1010 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1011 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1012 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1013 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1014 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1015 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1016 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1017 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1018 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL, 0);
1019 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1020 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
1021 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
1022 0xFFFFFFFF, NULL, 0);
1023 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
1024 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
1025 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
1026 S_03C008_TYPE(1),
1027 0xFFFFFFFF, NULL, 0);
1028
1029 if (uc.ui) {
1030 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), 0xFFFFFFFF, NULL, 0);
1031 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), 0xFFFFFFFF, NULL, 0);
1032 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), 0xFFFFFFFF, NULL, 0);
1033 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), 0xFFFFFFFF, NULL, 0);
1034 }
1035 return rstate;
1036 }
1037
1038 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
1039 struct pipe_resource *texture,
1040 const struct pipe_sampler_view *state)
1041 {
1042 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1043 struct r600_pipe_resource_state *rstate;
1044 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1045 unsigned format, endian;
1046 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1047 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1048 unsigned height, depth;
1049
1050 if (view == NULL)
1051 return NULL;
1052 rstate = &view->state;
1053
1054 /* initialize base object */
1055 view->base = *state;
1056 view->base.texture = NULL;
1057 pipe_reference(NULL, &texture->reference);
1058 view->base.texture = texture;
1059 view->base.reference.count = 1;
1060 view->base.context = ctx;
1061
1062 swizzle[0] = state->swizzle_r;
1063 swizzle[1] = state->swizzle_g;
1064 swizzle[2] = state->swizzle_b;
1065 swizzle[3] = state->swizzle_a;
1066
1067 format = r600_translate_texformat(ctx->screen, state->format,
1068 swizzle,
1069 &word4, &yuv_format);
1070 if (format == ~0) {
1071 format = 0;
1072 }
1073
1074 if (tmp->depth && !tmp->is_flushing_texture) {
1075 r600_texture_depth_flush(ctx, texture, TRUE);
1076 tmp = tmp->flushed_depth_texture;
1077 }
1078
1079 endian = r600_colorformat_endian_swap(format);
1080
1081 height = texture->height0;
1082 depth = texture->depth0;
1083
1084 pitch = align(tmp->pitch_in_blocks[0] *
1085 util_format_get_blockwidth(state->format), 8);
1086 array_mode = tmp->array_mode[0];
1087 tile_type = tmp->tile_type;
1088
1089 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1090 height = 1;
1091 depth = texture->array_size;
1092 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1093 depth = texture->array_size;
1094 }
1095
1096 rstate->bo[0] = &tmp->resource;
1097 rstate->bo[1] = &tmp->resource;
1098 rstate->bo_usage[0] = RADEON_USAGE_READ;
1099 rstate->bo_usage[1] = RADEON_USAGE_READ;
1100
1101 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1102 S_030000_PITCH((pitch / 8) - 1) |
1103 S_030000_NON_DISP_TILING_ORDER(tile_type) |
1104 S_030000_TEX_WIDTH(texture->width0 - 1));
1105 rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1106 S_030004_TEX_DEPTH(depth - 1) |
1107 S_030004_ARRAY_MODE(array_mode));
1108 rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1109 rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1110 rstate->val[4] = (word4 |
1111 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1112 S_030010_ENDIAN_SWAP(endian) |
1113 S_030010_BASE_LEVEL(state->u.tex.first_level));
1114 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1115 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1116 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1117 rstate->val[6] = (S_030018_MAX_ANISO(4 /* max 16 samples */));
1118 rstate->val[7] = (S_03001C_DATA_FORMAT(format) |
1119 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE));
1120
1121 return &view->base;
1122 }
1123
1124 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1125 struct pipe_sampler_view **views)
1126 {
1127 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1128 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1129
1130 for (int i = 0; i < count; i++) {
1131 if (resource[i]) {
1132 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
1133 i + R600_MAX_CONST_BUFFERS);
1134 }
1135 }
1136 }
1137
1138 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1139 struct pipe_sampler_view **views)
1140 {
1141 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1142 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1143 int i;
1144 int has_depth = 0;
1145
1146 for (i = 0; i < count; i++) {
1147 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1148 if (resource[i]) {
1149 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1150 has_depth = 1;
1151 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
1152 i + R600_MAX_CONST_BUFFERS);
1153 } else
1154 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1155 i + R600_MAX_CONST_BUFFERS);
1156
1157 pipe_sampler_view_reference(
1158 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1159 views[i]);
1160 } else {
1161 if (resource[i]) {
1162 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1163 has_depth = 1;
1164 }
1165 }
1166 }
1167 for (i = count; i < NUM_TEX_UNITS; i++) {
1168 if (rctx->ps_samplers.views[i]) {
1169 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1170 i + R600_MAX_CONST_BUFFERS);
1171 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1172 }
1173 }
1174 rctx->have_depth_texture = has_depth;
1175 rctx->ps_samplers.n_views = count;
1176 }
1177
1178 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1179 {
1180 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1181 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1182
1183
1184 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1185 rctx->ps_samplers.n_samplers = count;
1186
1187 for (int i = 0; i < count; i++) {
1188 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
1189 }
1190 }
1191
1192 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1193 {
1194 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1195 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1196
1197 for (int i = 0; i < count; i++) {
1198 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
1199 }
1200 }
1201
1202 static void evergreen_set_clip_state(struct pipe_context *ctx,
1203 const struct pipe_clip_state *state)
1204 {
1205 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1206 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1207 struct pipe_resource *cbuf;
1208
1209 if (rstate == NULL)
1210 return;
1211
1212 rctx->clip = *state;
1213 rstate->id = R600_PIPE_STATE_CLIP;
1214 for (int i = 0; i < 6; i++) {
1215 r600_pipe_state_add_reg(rstate,
1216 R_0285BC_PA_CL_UCP0_X + i * 16,
1217 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL, 0);
1218 r600_pipe_state_add_reg(rstate,
1219 R_0285C0_PA_CL_UCP0_Y + i * 16,
1220 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL, 0);
1221 r600_pipe_state_add_reg(rstate,
1222 R_0285C4_PA_CL_UCP0_Z + i * 16,
1223 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL, 0);
1224 r600_pipe_state_add_reg(rstate,
1225 R_0285C8_PA_CL_UCP0_W + i * 16,
1226 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL, 0);
1227 }
1228
1229 free(rctx->states[R600_PIPE_STATE_CLIP]);
1230 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1231 r600_context_pipe_state_set(&rctx->ctx, rstate);
1232
1233 cbuf = pipe_user_buffer_create(ctx->screen,
1234 state->ucp,
1235 4*4*8, /* 8*4 floats */
1236 PIPE_BIND_CONSTANT_BUFFER);
1237 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
1238 pipe_resource_reference(&cbuf, NULL);
1239 }
1240
1241 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1242 const struct pipe_poly_stipple *state)
1243 {
1244 }
1245
1246 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1247 {
1248 }
1249
1250 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1251 const struct pipe_scissor_state *state)
1252 {
1253 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1254 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1255 u32 tl, br;
1256
1257 if (rstate == NULL)
1258 return;
1259
1260 rstate->id = R600_PIPE_STATE_SCISSOR;
1261 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1262 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1263 r600_pipe_state_add_reg(rstate,
1264 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1265 0xFFFFFFFF, NULL, 0);
1266 r600_pipe_state_add_reg(rstate,
1267 R_028214_PA_SC_CLIPRECT_0_BR, br,
1268 0xFFFFFFFF, NULL, 0);
1269 r600_pipe_state_add_reg(rstate,
1270 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1271 0xFFFFFFFF, NULL, 0);
1272 r600_pipe_state_add_reg(rstate,
1273 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1274 0xFFFFFFFF, NULL, 0);
1275 r600_pipe_state_add_reg(rstate,
1276 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1277 0xFFFFFFFF, NULL, 0);
1278 r600_pipe_state_add_reg(rstate,
1279 R_028224_PA_SC_CLIPRECT_2_BR, br,
1280 0xFFFFFFFF, NULL, 0);
1281 r600_pipe_state_add_reg(rstate,
1282 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1283 0xFFFFFFFF, NULL, 0);
1284 r600_pipe_state_add_reg(rstate,
1285 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1286 0xFFFFFFFF, NULL, 0);
1287
1288 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1289 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1290 r600_context_pipe_state_set(&rctx->ctx, rstate);
1291 }
1292
1293 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1294 const struct pipe_viewport_state *state)
1295 {
1296 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1297 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1298
1299 if (rstate == NULL)
1300 return;
1301
1302 rctx->viewport = *state;
1303 rstate->id = R600_PIPE_STATE_VIEWPORT;
1304 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
1305 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1306 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL, 0);
1307 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL, 0);
1308 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL, 0);
1309 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL, 0);
1310 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL, 0);
1311 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL, 0);
1312 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL, 0);
1313
1314 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1315 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1316 r600_context_pipe_state_set(&rctx->ctx, rstate);
1317 }
1318
1319 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1320 const struct pipe_framebuffer_state *state, int cb)
1321 {
1322 struct r600_resource_texture *rtex;
1323 struct r600_surface *surf;
1324 unsigned level = state->cbufs[cb]->u.tex.level;
1325 unsigned pitch, slice;
1326 unsigned color_info;
1327 unsigned format, swap, ntype, endian;
1328 uint64_t offset;
1329 unsigned tile_type;
1330 const struct util_format_description *desc;
1331 int i;
1332 unsigned blend_clamp = 0, blend_bypass = 0;
1333
1334 surf = (struct r600_surface *)state->cbufs[cb];
1335 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1336
1337 if (rtex->depth)
1338 rctx->have_depth_fb = TRUE;
1339
1340 if (rtex->depth && !rtex->is_flushing_texture) {
1341 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1342 rtex = rtex->flushed_depth_texture;
1343 }
1344
1345 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1346 offset = r600_texture_get_offset(rtex,
1347 level, state->cbufs[cb]->u.tex.first_layer);
1348 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1349 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1350 desc = util_format_description(surf->base.format);
1351 for (i = 0; i < 4; i++) {
1352 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1353 break;
1354 }
1355 }
1356
1357 ntype = V_028C70_NUMBER_UNORM;
1358 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1359 ntype = V_028C70_NUMBER_SRGB;
1360 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1361 if (desc->channel[i].normalized)
1362 ntype = V_028C70_NUMBER_SNORM;
1363 else if (desc->channel[i].pure_integer)
1364 ntype = V_028C70_NUMBER_SINT;
1365 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1366 if (desc->channel[i].normalized)
1367 ntype = V_028C70_NUMBER_UNORM;
1368 else if (desc->channel[i].pure_integer)
1369 ntype = V_028C70_NUMBER_UINT;
1370 }
1371
1372 format = r600_translate_colorformat(surf->base.format);
1373 swap = r600_translate_colorswap(surf->base.format);
1374 if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1375 endian = ENDIAN_NONE;
1376 } else {
1377 endian = r600_colorformat_endian_swap(format);
1378 }
1379
1380 /* blend clamp should be set for all NORM/SRGB types */
1381 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1382 ntype == V_028C70_NUMBER_SRGB)
1383 blend_clamp = 1;
1384
1385 /* set blend bypass according to docs if SINT/UINT or
1386 8/24 COLOR variants */
1387 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1388 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1389 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1390 blend_clamp = 0;
1391 blend_bypass = 1;
1392 }
1393
1394 color_info = S_028C70_FORMAT(format) |
1395 S_028C70_COMP_SWAP(swap) |
1396 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
1397 S_028C70_BLEND_CLAMP(blend_clamp) |
1398 S_028C70_BLEND_BYPASS(blend_bypass) |
1399 S_028C70_NUMBER_TYPE(ntype) |
1400 S_028C70_ENDIAN(endian);
1401
1402 /* EXPORT_NORM is an optimzation that can be enabled for better
1403 * performance in certain cases.
1404 * EXPORT_NORM can be enabled if:
1405 * - 11-bit or smaller UNORM/SNORM/SRGB
1406 * - 16-bit or smaller FLOAT
1407 */
1408 /* FIXME: This should probably be the same for all CBs if we want
1409 * useful alpha tests. */
1410 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1411 ((desc->channel[i].size < 12 &&
1412 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1413 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1414 (desc->channel[i].size < 17 &&
1415 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1416 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1417 rctx->export_16bpc = true;
1418 } else {
1419 rctx->export_16bpc = false;
1420 }
1421 rctx->alpha_ref_dirty = true;
1422
1423 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1424 tile_type = rtex->tile_type;
1425 } else /* workaround for linear buffers */
1426 tile_type = 1;
1427
1428 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1429 offset >>= 8;
1430
1431 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1432 r600_pipe_state_add_reg(rstate,
1433 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1434 offset, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1435 r600_pipe_state_add_reg(rstate,
1436 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1437 0x0, 0xFFFFFFFF, NULL, 0);
1438 r600_pipe_state_add_reg(rstate,
1439 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1440 color_info, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1441 r600_pipe_state_add_reg(rstate,
1442 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1443 S_028C64_PITCH_TILE_MAX(pitch),
1444 0xFFFFFFFF, NULL, 0);
1445 r600_pipe_state_add_reg(rstate,
1446 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1447 S_028C68_SLICE_TILE_MAX(slice),
1448 0xFFFFFFFF, NULL, 0);
1449 r600_pipe_state_add_reg(rstate,
1450 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1451 0x00000000, 0xFFFFFFFF, NULL, 0);
1452 r600_pipe_state_add_reg(rstate,
1453 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1454 S_028C74_NON_DISP_TILING_ORDER(tile_type),
1455 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1456 }
1457
1458 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1459 const struct pipe_framebuffer_state *state)
1460 {
1461 struct r600_resource_texture *rtex;
1462 struct r600_surface *surf;
1463 unsigned level, first_layer, pitch, slice, format, array_mode;
1464 uint64_t offset;
1465
1466 if (state->zsbuf == NULL)
1467 return;
1468
1469 surf = (struct r600_surface *)state->zsbuf;
1470 level = surf->base.u.tex.level;
1471 rtex = (struct r600_resource_texture*)surf->base.texture;
1472
1473 /* XXX remove this once tiling is properly supported */
1474 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1475 V_028C70_ARRAY_1D_TILED_THIN1;
1476
1477 first_layer = surf->base.u.tex.first_layer;
1478 offset = r600_texture_get_offset(rtex, level, first_layer);
1479 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1480 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1481 format = r600_translate_dbformat(rtex->real_format);
1482
1483 offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1484 offset >>= 8;
1485
1486 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1487 offset, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1488 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1489 offset, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1490 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0);
1491
1492 if (rtex->stencil) {
1493 uint64_t stencil_offset =
1494 r600_texture_get_offset(rtex->stencil, level, first_layer);
1495
1496 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1497 stencil_offset >>= 8;
1498
1499 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1500 stencil_offset, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1501 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1502 stencil_offset, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1503 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1504 1, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1505 } else {
1506 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1507 0, 0xFFFFFFFF, NULL, RADEON_USAGE_READWRITE);
1508 }
1509
1510 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
1511 S_028040_ARRAY_MODE(array_mode) | S_028040_FORMAT(format),
1512 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1513 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1514 S_028058_PITCH_TILE_MAX(pitch),
1515 0xFFFFFFFF, NULL, 0);
1516 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1517 S_02805C_SLICE_TILE_MAX(slice),
1518 0xFFFFFFFF, NULL, 0);
1519 }
1520
1521 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1522 const struct pipe_framebuffer_state *state)
1523 {
1524 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1525 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1526 u32 shader_mask, tl, br, target_mask;
1527 int tl_x, tl_y, br_x, br_y;
1528
1529 if (rstate == NULL)
1530 return;
1531
1532 evergreen_context_flush_dest_caches(&rctx->ctx);
1533 rctx->ctx.num_dest_buffers = state->nr_cbufs;
1534
1535 /* unreference old buffer and reference new one */
1536 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1537
1538 util_copy_framebuffer_state(&rctx->framebuffer, state);
1539
1540 /* build states */
1541 rctx->have_depth_fb = 0;
1542 rctx->nr_cbufs = state->nr_cbufs;
1543 for (int i = 0; i < state->nr_cbufs; i++) {
1544 evergreen_cb(rctx, rstate, state, i);
1545 }
1546 if (state->zsbuf) {
1547 evergreen_db(rctx, rstate, state);
1548 rctx->ctx.num_dest_buffers++;
1549 }
1550
1551 target_mask = 0x00000000;
1552 target_mask = 0xFFFFFFFF;
1553 shader_mask = 0;
1554 for (int i = 0; i < state->nr_cbufs; i++) {
1555 target_mask ^= 0xf << (i * 4);
1556 shader_mask |= 0xf << (i * 4);
1557 }
1558 tl_x = 0;
1559 tl_y = 0;
1560 br_x = state->width;
1561 br_y = state->height;
1562 /* EG hw workaround */
1563 if (br_x == 0)
1564 tl_x = 1;
1565 if (br_y == 0)
1566 tl_y = 1;
1567 /* cayman hw workaround */
1568 if (rctx->chip_class == CAYMAN) {
1569 if (br_x == 1 && br_y == 1)
1570 br_x = 2;
1571 }
1572 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1573 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1574
1575 r600_pipe_state_add_reg(rstate,
1576 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1577 0xFFFFFFFF, NULL, 0);
1578 r600_pipe_state_add_reg(rstate,
1579 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1580 0xFFFFFFFF, NULL, 0);
1581 r600_pipe_state_add_reg(rstate,
1582 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1583 0xFFFFFFFF, NULL, 0);
1584 r600_pipe_state_add_reg(rstate,
1585 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1586 0xFFFFFFFF, NULL, 0);
1587 r600_pipe_state_add_reg(rstate,
1588 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1589 0xFFFFFFFF, NULL, 0);
1590 r600_pipe_state_add_reg(rstate,
1591 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1592 0xFFFFFFFF, NULL, 0);
1593 r600_pipe_state_add_reg(rstate,
1594 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1595 0xFFFFFFFF, NULL, 0);
1596 r600_pipe_state_add_reg(rstate,
1597 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1598 0xFFFFFFFF, NULL, 0);
1599 r600_pipe_state_add_reg(rstate,
1600 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1601 0xFFFFFFFF, NULL, 0);
1602 r600_pipe_state_add_reg(rstate,
1603 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1604 0xFFFFFFFF, NULL, 0);
1605
1606 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1607 0x00000000, target_mask, NULL, 0);
1608 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1609 shader_mask, 0xFFFFFFFF, NULL, 0);
1610
1611
1612 if (rctx->chip_class == CAYMAN) {
1613 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1614 0x00000000, 0xFFFFFFFF, NULL, 0);
1615 } else {
1616 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1617 0x00000000, 0xFFFFFFFF, NULL, 0);
1618 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0,
1619 0x00000000, 0xFFFFFFFF, NULL, 0);
1620 }
1621
1622 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1623 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1624 r600_context_pipe_state_set(&rctx->ctx, rstate);
1625
1626 if (state->zsbuf) {
1627 evergreen_polygon_offset_update(rctx);
1628 }
1629 }
1630
1631 static void evergreen_texture_barrier(struct pipe_context *ctx)
1632 {
1633 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1634
1635 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1636 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1637 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1638 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1639 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
1640 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
1641 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
1642 }
1643
1644 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
1645 {
1646 rctx->context.create_blend_state = evergreen_create_blend_state;
1647 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1648 rctx->context.create_fs_state = r600_create_shader_state;
1649 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1650 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1651 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1652 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1653 rctx->context.create_vs_state = r600_create_shader_state;
1654 rctx->context.bind_blend_state = r600_bind_blend_state;
1655 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1656 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1657 rctx->context.bind_fs_state = r600_bind_ps_shader;
1658 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1659 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1660 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1661 rctx->context.bind_vs_state = r600_bind_vs_shader;
1662 rctx->context.delete_blend_state = r600_delete_state;
1663 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1664 rctx->context.delete_fs_state = r600_delete_ps_shader;
1665 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1666 rctx->context.delete_sampler_state = r600_delete_state;
1667 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1668 rctx->context.delete_vs_state = r600_delete_vs_shader;
1669 rctx->context.set_blend_color = evergreen_set_blend_color;
1670 rctx->context.set_clip_state = evergreen_set_clip_state;
1671 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1672 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1673 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1674 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1675 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1676 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1677 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1678 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1679 rctx->context.set_index_buffer = r600_set_index_buffer;
1680 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1681 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1682 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1683 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1684 rctx->context.texture_barrier = evergreen_texture_barrier;
1685 rctx->context.create_stream_output_target = r600_create_so_target;
1686 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1687 rctx->context.set_stream_output_targets = r600_set_so_targets;
1688 }
1689
1690 static void cayman_init_config(struct r600_pipe_context *rctx)
1691 {
1692 struct r600_pipe_state *rstate = &rctx->config;
1693 unsigned tmp;
1694
1695 tmp = 0x00000000;
1696 tmp |= S_008C00_EXPORT_SRC_C(1);
1697 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
1698
1699 /* always set the temp clauses */
1700 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), 0xFFFFFFFF, NULL, 0);
1701 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL, 0);
1702 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL, 0);
1703 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL, 0);
1704
1705 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL, 0);
1706
1707 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1708 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1709 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
1710 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
1711 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL, 0);
1712 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL, 0);
1713 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
1714 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
1715 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1716 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1717 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1718 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1719 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL, 0);
1720 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
1721 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
1722 r600_pipe_state_add_reg(rstate, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), 0xFFFFFFFF, NULL, 0);
1723 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL, 0);
1724 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL, 0);
1725 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL, 0);
1726
1727 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL, 0);
1728 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL, 0);
1729 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL, 0);
1730 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL, 0);
1731 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL, 0);
1732 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL, 0);
1733 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL, 0);
1734 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL, 0);
1735 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL, 0);
1736 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL, 0);
1737 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL, 0);
1738 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL, 0);
1739 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL, 0);
1740 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL, 0);
1741 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL, 0);
1742 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL, 0);
1743 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL, 0);
1744 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL, 0);
1745 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL, 0);
1746 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL, 0);
1747 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL, 0);
1748 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL, 0);
1749 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL, 0);
1750 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL, 0);
1751 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL, 0);
1752 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL, 0);
1753 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL, 0);
1754 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL, 0);
1755 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL, 0);
1756 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL, 0);
1757 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL, 0);
1758 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL, 0);
1759
1760 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1761
1762 r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, 0xffffffff, NULL, 0);
1763 r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, 0xffffffff, NULL, 0);
1764
1765 r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, 0xFFFFFFFF, NULL, 0);
1766 r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0xFFFFFFFF, NULL, 0);
1767
1768 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, 0xFFFFFFFF, NULL, 0);
1769 r600_context_pipe_state_set(&rctx->ctx, rstate);
1770 }
1771
1772 void evergreen_init_config(struct r600_pipe_context *rctx)
1773 {
1774 struct r600_pipe_state *rstate = &rctx->config;
1775 int ps_prio;
1776 int vs_prio;
1777 int gs_prio;
1778 int es_prio;
1779 int hs_prio, cs_prio, ls_prio;
1780 int num_ps_gprs;
1781 int num_vs_gprs;
1782 int num_gs_gprs;
1783 int num_es_gprs;
1784 int num_hs_gprs;
1785 int num_ls_gprs;
1786 int num_temp_gprs;
1787 int num_ps_threads;
1788 int num_vs_threads;
1789 int num_gs_threads;
1790 int num_es_threads;
1791 int num_hs_threads;
1792 int num_ls_threads;
1793 int num_ps_stack_entries;
1794 int num_vs_stack_entries;
1795 int num_gs_stack_entries;
1796 int num_es_stack_entries;
1797 int num_hs_stack_entries;
1798 int num_ls_stack_entries;
1799 enum radeon_family family;
1800 unsigned tmp;
1801
1802 family = rctx->family;
1803
1804 if (rctx->chip_class == CAYMAN) {
1805 cayman_init_config(rctx);
1806 return;
1807 }
1808
1809 ps_prio = 0;
1810 vs_prio = 1;
1811 gs_prio = 2;
1812 es_prio = 3;
1813 hs_prio = 0;
1814 ls_prio = 0;
1815 cs_prio = 0;
1816
1817 switch (family) {
1818 case CHIP_CEDAR:
1819 default:
1820 num_ps_gprs = 93;
1821 num_vs_gprs = 46;
1822 num_temp_gprs = 4;
1823 num_gs_gprs = 31;
1824 num_es_gprs = 31;
1825 num_hs_gprs = 23;
1826 num_ls_gprs = 23;
1827 num_ps_threads = 96;
1828 num_vs_threads = 16;
1829 num_gs_threads = 16;
1830 num_es_threads = 16;
1831 num_hs_threads = 16;
1832 num_ls_threads = 16;
1833 num_ps_stack_entries = 42;
1834 num_vs_stack_entries = 42;
1835 num_gs_stack_entries = 42;
1836 num_es_stack_entries = 42;
1837 num_hs_stack_entries = 42;
1838 num_ls_stack_entries = 42;
1839 break;
1840 case CHIP_REDWOOD:
1841 num_ps_gprs = 93;
1842 num_vs_gprs = 46;
1843 num_temp_gprs = 4;
1844 num_gs_gprs = 31;
1845 num_es_gprs = 31;
1846 num_hs_gprs = 23;
1847 num_ls_gprs = 23;
1848 num_ps_threads = 128;
1849 num_vs_threads = 20;
1850 num_gs_threads = 20;
1851 num_es_threads = 20;
1852 num_hs_threads = 20;
1853 num_ls_threads = 20;
1854 num_ps_stack_entries = 42;
1855 num_vs_stack_entries = 42;
1856 num_gs_stack_entries = 42;
1857 num_es_stack_entries = 42;
1858 num_hs_stack_entries = 42;
1859 num_ls_stack_entries = 42;
1860 break;
1861 case CHIP_JUNIPER:
1862 num_ps_gprs = 93;
1863 num_vs_gprs = 46;
1864 num_temp_gprs = 4;
1865 num_gs_gprs = 31;
1866 num_es_gprs = 31;
1867 num_hs_gprs = 23;
1868 num_ls_gprs = 23;
1869 num_ps_threads = 128;
1870 num_vs_threads = 20;
1871 num_gs_threads = 20;
1872 num_es_threads = 20;
1873 num_hs_threads = 20;
1874 num_ls_threads = 20;
1875 num_ps_stack_entries = 85;
1876 num_vs_stack_entries = 85;
1877 num_gs_stack_entries = 85;
1878 num_es_stack_entries = 85;
1879 num_hs_stack_entries = 85;
1880 num_ls_stack_entries = 85;
1881 break;
1882 case CHIP_CYPRESS:
1883 case CHIP_HEMLOCK:
1884 num_ps_gprs = 93;
1885 num_vs_gprs = 46;
1886 num_temp_gprs = 4;
1887 num_gs_gprs = 31;
1888 num_es_gprs = 31;
1889 num_hs_gprs = 23;
1890 num_ls_gprs = 23;
1891 num_ps_threads = 128;
1892 num_vs_threads = 20;
1893 num_gs_threads = 20;
1894 num_es_threads = 20;
1895 num_hs_threads = 20;
1896 num_ls_threads = 20;
1897 num_ps_stack_entries = 85;
1898 num_vs_stack_entries = 85;
1899 num_gs_stack_entries = 85;
1900 num_es_stack_entries = 85;
1901 num_hs_stack_entries = 85;
1902 num_ls_stack_entries = 85;
1903 break;
1904 case CHIP_PALM:
1905 num_ps_gprs = 93;
1906 num_vs_gprs = 46;
1907 num_temp_gprs = 4;
1908 num_gs_gprs = 31;
1909 num_es_gprs = 31;
1910 num_hs_gprs = 23;
1911 num_ls_gprs = 23;
1912 num_ps_threads = 96;
1913 num_vs_threads = 16;
1914 num_gs_threads = 16;
1915 num_es_threads = 16;
1916 num_hs_threads = 16;
1917 num_ls_threads = 16;
1918 num_ps_stack_entries = 42;
1919 num_vs_stack_entries = 42;
1920 num_gs_stack_entries = 42;
1921 num_es_stack_entries = 42;
1922 num_hs_stack_entries = 42;
1923 num_ls_stack_entries = 42;
1924 break;
1925 case CHIP_SUMO:
1926 num_ps_gprs = 93;
1927 num_vs_gprs = 46;
1928 num_temp_gprs = 4;
1929 num_gs_gprs = 31;
1930 num_es_gprs = 31;
1931 num_hs_gprs = 23;
1932 num_ls_gprs = 23;
1933 num_ps_threads = 96;
1934 num_vs_threads = 25;
1935 num_gs_threads = 25;
1936 num_es_threads = 25;
1937 num_hs_threads = 25;
1938 num_ls_threads = 25;
1939 num_ps_stack_entries = 42;
1940 num_vs_stack_entries = 42;
1941 num_gs_stack_entries = 42;
1942 num_es_stack_entries = 42;
1943 num_hs_stack_entries = 42;
1944 num_ls_stack_entries = 42;
1945 break;
1946 case CHIP_SUMO2:
1947 num_ps_gprs = 93;
1948 num_vs_gprs = 46;
1949 num_temp_gprs = 4;
1950 num_gs_gprs = 31;
1951 num_es_gprs = 31;
1952 num_hs_gprs = 23;
1953 num_ls_gprs = 23;
1954 num_ps_threads = 96;
1955 num_vs_threads = 25;
1956 num_gs_threads = 25;
1957 num_es_threads = 25;
1958 num_hs_threads = 25;
1959 num_ls_threads = 25;
1960 num_ps_stack_entries = 85;
1961 num_vs_stack_entries = 85;
1962 num_gs_stack_entries = 85;
1963 num_es_stack_entries = 85;
1964 num_hs_stack_entries = 85;
1965 num_ls_stack_entries = 85;
1966 break;
1967 case CHIP_BARTS:
1968 num_ps_gprs = 93;
1969 num_vs_gprs = 46;
1970 num_temp_gprs = 4;
1971 num_gs_gprs = 31;
1972 num_es_gprs = 31;
1973 num_hs_gprs = 23;
1974 num_ls_gprs = 23;
1975 num_ps_threads = 128;
1976 num_vs_threads = 20;
1977 num_gs_threads = 20;
1978 num_es_threads = 20;
1979 num_hs_threads = 20;
1980 num_ls_threads = 20;
1981 num_ps_stack_entries = 85;
1982 num_vs_stack_entries = 85;
1983 num_gs_stack_entries = 85;
1984 num_es_stack_entries = 85;
1985 num_hs_stack_entries = 85;
1986 num_ls_stack_entries = 85;
1987 break;
1988 case CHIP_TURKS:
1989 num_ps_gprs = 93;
1990 num_vs_gprs = 46;
1991 num_temp_gprs = 4;
1992 num_gs_gprs = 31;
1993 num_es_gprs = 31;
1994 num_hs_gprs = 23;
1995 num_ls_gprs = 23;
1996 num_ps_threads = 128;
1997 num_vs_threads = 20;
1998 num_gs_threads = 20;
1999 num_es_threads = 20;
2000 num_hs_threads = 20;
2001 num_ls_threads = 20;
2002 num_ps_stack_entries = 42;
2003 num_vs_stack_entries = 42;
2004 num_gs_stack_entries = 42;
2005 num_es_stack_entries = 42;
2006 num_hs_stack_entries = 42;
2007 num_ls_stack_entries = 42;
2008 break;
2009 case CHIP_CAICOS:
2010 num_ps_gprs = 93;
2011 num_vs_gprs = 46;
2012 num_temp_gprs = 4;
2013 num_gs_gprs = 31;
2014 num_es_gprs = 31;
2015 num_hs_gprs = 23;
2016 num_ls_gprs = 23;
2017 num_ps_threads = 128;
2018 num_vs_threads = 10;
2019 num_gs_threads = 10;
2020 num_es_threads = 10;
2021 num_hs_threads = 10;
2022 num_ls_threads = 10;
2023 num_ps_stack_entries = 42;
2024 num_vs_stack_entries = 42;
2025 num_gs_stack_entries = 42;
2026 num_es_stack_entries = 42;
2027 num_hs_stack_entries = 42;
2028 num_ls_stack_entries = 42;
2029 break;
2030 }
2031
2032 tmp = 0x00000000;
2033 switch (family) {
2034 case CHIP_CEDAR:
2035 case CHIP_PALM:
2036 case CHIP_SUMO:
2037 case CHIP_SUMO2:
2038 case CHIP_CAICOS:
2039 break;
2040 default:
2041 tmp |= S_008C00_VC_ENABLE(1);
2042 break;
2043 }
2044 tmp |= S_008C00_EXPORT_SRC_C(1);
2045 tmp |= S_008C00_CS_PRIO(cs_prio);
2046 tmp |= S_008C00_LS_PRIO(ls_prio);
2047 tmp |= S_008C00_HS_PRIO(hs_prio);
2048 tmp |= S_008C00_PS_PRIO(ps_prio);
2049 tmp |= S_008C00_VS_PRIO(vs_prio);
2050 tmp |= S_008C00_GS_PRIO(gs_prio);
2051 tmp |= S_008C00_ES_PRIO(es_prio);
2052 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
2053
2054 /* enable dynamic GPR resource management */
2055 if (rctx->screen->info.drm_minor >= 7) {
2056 /* always set temp clauses */
2057 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
2058 S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), 0xFFFFFFFF, NULL, 0);
2059 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL, 0);
2060 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL, 0);
2061 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL, 0);
2062 r600_pipe_state_add_reg(rstate, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2063 S_028838_PS_GPRS(0x1e) |
2064 S_028838_VS_GPRS(0x1e) |
2065 S_028838_GS_GPRS(0x1e) |
2066 S_028838_ES_GPRS(0x1e) |
2067 S_028838_HS_GPRS(0x1e) |
2068 S_028838_LS_GPRS(0x1e), 0xFFFFFFFF, NULL, 0); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2069 } else {
2070 tmp = 0;
2071 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2072 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2073 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2074 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2075
2076 tmp = 0;
2077 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
2078 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2079 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2080
2081 tmp = 0;
2082 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2083 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2084 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL, 0);
2085 }
2086
2087 tmp = 0;
2088 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
2089 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2090 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2091 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2092 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2093
2094 tmp = 0;
2095 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
2096 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2097 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2098
2099 tmp = 0;
2100 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2101 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2102 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2103
2104 tmp = 0;
2105 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2106 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2107 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2108
2109 tmp = 0;
2110 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2111 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2112 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL, 0);
2113
2114 tmp = 0;
2115 tmp |= S_008E2C_NUM_PS_LDS(0x1000);
2116 tmp |= S_008E2C_NUM_LS_LDS(0x1000);
2117 r600_pipe_state_add_reg(rstate, R_008E2C_SQ_LDS_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL, 0);
2118
2119 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2120 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL, 0);
2121
2122 #if 0
2123 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL, 0);
2124
2125 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL, 0);
2126 #endif
2127 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL, 0);
2128
2129 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2130 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2131 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2132 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2133 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2134 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2135
2136 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2137 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL, 0);
2138 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL, 0);
2139 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL, 0);
2140
2141 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2142 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2143 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
2144 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
2145 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL, 0);
2146 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL, 0);
2147 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
2148 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
2149 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2150 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2151 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2152 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2153 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL, 0);
2154 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
2155 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
2156 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL, 0);
2157 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL, 0);
2158 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL, 0);
2159
2160 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL, 0);
2161 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL, 0);
2162 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL, 0);
2163 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL, 0);
2164 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL, 0);
2165 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL, 0);
2166 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL, 0);
2167 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL, 0);
2168 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL, 0);
2169 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL, 0);
2170 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL, 0);
2171 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL, 0);
2172 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL, 0);
2173 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL, 0);
2174 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL, 0);
2175 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL, 0);
2176 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL, 0);
2177 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL, 0);
2178 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL, 0);
2179 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL, 0);
2180 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL, 0);
2181 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL, 0);
2182 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL, 0);
2183 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL, 0);
2184 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL, 0);
2185 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL, 0);
2186 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL, 0);
2187 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL, 0);
2188 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL, 0);
2189 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL, 0);
2190 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL, 0);
2191 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL, 0);
2192
2193 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2194
2195 r600_context_pipe_state_set(&rctx->ctx, rstate);
2196 }
2197
2198 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
2199 {
2200 struct r600_pipe_state state;
2201
2202 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2203 state.nregs = 0;
2204 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2205 float offset_units = rctx->rasterizer->offset_units;
2206 unsigned offset_db_fmt_cntl = 0, depth;
2207
2208 switch (rctx->framebuffer.zsbuf->texture->format) {
2209 case PIPE_FORMAT_Z24X8_UNORM:
2210 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2211 depth = -24;
2212 offset_units *= 2.0f;
2213 break;
2214 case PIPE_FORMAT_Z32_FLOAT:
2215 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2216 depth = -23;
2217 offset_units *= 1.0f;
2218 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2219 break;
2220 case PIPE_FORMAT_Z16_UNORM:
2221 depth = -16;
2222 offset_units *= 4.0f;
2223 break;
2224 default:
2225 return;
2226 }
2227 /* FIXME some of those reg can be computed with cso */
2228 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2229 r600_pipe_state_add_reg(&state,
2230 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2231 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
2232 r600_pipe_state_add_reg(&state,
2233 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2234 fui(offset_units), 0xFFFFFFFF, NULL, 0);
2235 r600_pipe_state_add_reg(&state,
2236 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2237 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
2238 r600_pipe_state_add_reg(&state,
2239 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2240 fui(offset_units), 0xFFFFFFFF, NULL, 0);
2241 r600_pipe_state_add_reg(&state,
2242 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2243 offset_db_fmt_cntl, 0xFFFFFFFF, NULL, 0);
2244 r600_context_pipe_state_set(&rctx->ctx, &state);
2245 }
2246 }
2247
2248 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2249 {
2250 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2251 struct r600_pipe_state *rstate = &shader->rstate;
2252 struct r600_shader *rshader = &shader->shader;
2253 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2254 int pos_index = -1, face_index = -1;
2255 int ninterp = 0;
2256 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2257 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2258
2259 rstate->nregs = 0;
2260
2261 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2262 for (i = 0; i < rshader->ninput; i++) {
2263 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2264 POSITION goes via GPRs from the SC so isn't counted */
2265 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2266 pos_index = i;
2267 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2268 face_index = i;
2269 else {
2270 ninterp++;
2271 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2272 have_linear = TRUE;
2273 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2274 have_perspective = TRUE;
2275 if (rshader->input[i].centroid)
2276 have_centroid = TRUE;
2277 }
2278
2279 sid = rshader->input[i].spi_sid;
2280
2281 if (sid) {
2282
2283 tmp = S_028644_SEMANTIC(sid);
2284
2285 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2286 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2287 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2288 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2289 tmp |= S_028644_FLAT_SHADE(1);
2290 }
2291
2292 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2293 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2294 tmp |= S_028644_PT_SPRITE_TEX(1);
2295 }
2296
2297 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2298 tmp, 0xFFFFFFFF, NULL, 0);
2299
2300 idx++;
2301 }
2302 }
2303
2304 for (i = 0; i < rshader->noutput; i++) {
2305 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2306 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2307 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2308 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2309 }
2310 if (rshader->uses_kill)
2311 db_shader_control |= S_02880C_KILL_ENABLE(1);
2312
2313 exports_ps = 0;
2314 num_cout = 0;
2315 for (i = 0; i < rshader->noutput; i++) {
2316 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2317 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2318 exports_ps |= 1;
2319 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2320 if (rshader->fs_write_all)
2321 num_cout = rshader->nr_cbufs;
2322 else
2323 num_cout++;
2324 }
2325 }
2326 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2327 if (!exports_ps) {
2328 /* always at least export 1 component per pixel */
2329 exports_ps = 2;
2330 }
2331
2332 if (ninterp == 0) {
2333 ninterp = 1;
2334 have_perspective = TRUE;
2335 }
2336
2337 if (!have_perspective && !have_linear)
2338 have_perspective = TRUE;
2339
2340 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2341 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2342 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2343 spi_input_z = 0;
2344 if (pos_index != -1) {
2345 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2346 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2347 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2348 spi_input_z |= 1;
2349 }
2350
2351 spi_ps_in_control_1 = 0;
2352 if (face_index != -1) {
2353 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2354 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2355 }
2356
2357 spi_baryc_cntl = 0;
2358 if (have_perspective)
2359 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2360 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2361 if (have_linear)
2362 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2363 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2364
2365 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2366 spi_ps_in_control_0, 0xFFFFFFFF, NULL, 0);
2367 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2368 spi_ps_in_control_1, 0xFFFFFFFF, NULL, 0);
2369 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2370 0, 0xFFFFFFFF, NULL, 0);
2371 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL, 0);
2372 r600_pipe_state_add_reg(rstate,
2373 R_0286E0_SPI_BARYC_CNTL,
2374 spi_baryc_cntl,
2375 0xFFFFFFFF, NULL, 0);
2376
2377 r600_pipe_state_add_reg(rstate,
2378 R_028840_SQ_PGM_START_PS,
2379 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2380 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2381 r600_pipe_state_add_reg(rstate,
2382 R_028844_SQ_PGM_RESOURCES_PS,
2383 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2384 S_028844_PRIME_CACHE_ON_DRAW(1) |
2385 S_028844_STACK_SIZE(rshader->bc.nstack),
2386 0xFFFFFFFF, NULL, 0);
2387 r600_pipe_state_add_reg(rstate,
2388 R_028848_SQ_PGM_RESOURCES_2_PS,
2389 S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO),
2390 0xFFFFFFFF, NULL, 0);
2391 r600_pipe_state_add_reg(rstate,
2392 R_02884C_SQ_PGM_EXPORTS_PS,
2393 exports_ps, 0xFFFFFFFF, NULL, 0);
2394 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2395 db_shader_control,
2396 0xFFFFFFFF, NULL, 0);
2397 r600_pipe_state_add_reg(rstate,
2398 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
2399 0xFFFFFFFF, NULL, 0);
2400
2401 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2402 if (rctx->rasterizer)
2403 shader->flatshade = rctx->rasterizer->flatshade;
2404 }
2405
2406 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2407 {
2408 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2409 struct r600_pipe_state *rstate = &shader->rstate;
2410 struct r600_shader *rshader = &shader->shader;
2411 unsigned spi_vs_out_id[10] = {};
2412 unsigned i, tmp, nparams = 0;
2413
2414 /* clear previous register */
2415 rstate->nregs = 0;
2416
2417 for (i = 0; i < rshader->noutput; i++) {
2418 if (rshader->output[i].spi_sid) {
2419 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2420 spi_vs_out_id[nparams / 4] |= tmp;
2421 nparams++;
2422 }
2423 }
2424
2425 for (i = 0; i < 10; i++) {
2426 r600_pipe_state_add_reg(rstate,
2427 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2428 spi_vs_out_id[i], 0xFFFFFFFF, NULL, 0);
2429 }
2430
2431 /* Certain attributes (position, psize, etc.) don't count as params.
2432 * VS is required to export at least one param and r600_shader_from_tgsi()
2433 * takes care of adding a dummy export.
2434 */
2435 if (nparams < 1)
2436 nparams = 1;
2437
2438 r600_pipe_state_add_reg(rstate,
2439 R_0286C4_SPI_VS_OUT_CONFIG,
2440 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2441 0xFFFFFFFF, NULL, 0);
2442 r600_pipe_state_add_reg(rstate,
2443 R_028860_SQ_PGM_RESOURCES_VS,
2444 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2445 S_028860_STACK_SIZE(rshader->bc.nstack),
2446 0xFFFFFFFF, NULL, 0);
2447 r600_pipe_state_add_reg(rstate,
2448 R_028864_SQ_PGM_RESOURCES_2_VS,
2449 S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO),
2450 0xFFFFFFFF, NULL, 0);
2451 r600_pipe_state_add_reg(rstate,
2452 R_02885C_SQ_PGM_START_VS,
2453 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2454 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2455
2456 r600_pipe_state_add_reg(rstate,
2457 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2458 0xFFFFFFFF, NULL, 0);
2459
2460 r600_pipe_state_add_reg(rstate,
2461 R_02881C_PA_CL_VS_OUT_CNTL,
2462 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2463 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2464 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2465 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size),
2466 S_02881C_VS_OUT_CCDIST0_VEC_ENA(1) |
2467 S_02881C_VS_OUT_CCDIST1_VEC_ENA(1) |
2468 S_02881C_VS_OUT_MISC_VEC_ENA(1) |
2469 S_02881C_USE_VTX_POINT_SIZE(1),
2470 NULL, 0);
2471 }
2472
2473 void evergreen_fetch_shader(struct pipe_context *ctx,
2474 struct r600_vertex_element *ve)
2475 {
2476 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2477 struct r600_pipe_state *rstate = &ve->rstate;
2478 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2479 rstate->nregs = 0;
2480 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
2481 0x00000000, 0xFFFFFFFF, NULL, 0);
2482 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2483 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2484 0xFFFFFFFF, ve->fetch_shader, RADEON_USAGE_READ);
2485 }
2486
2487 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
2488 {
2489 struct pipe_depth_stencil_alpha_state dsa;
2490 struct r600_pipe_state *rstate;
2491
2492 memset(&dsa, 0, sizeof(dsa));
2493
2494 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2495 r600_pipe_state_add_reg(rstate,
2496 R_028000_DB_RENDER_CONTROL,
2497 S_028000_DEPTH_COPY_ENABLE(1) |
2498 S_028000_STENCIL_COPY_ENABLE(1) |
2499 S_028000_COPY_CENTROID(1),
2500 0xFFFFFFFF, NULL, 0);
2501 return rstate;
2502 }
2503
2504 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
2505 struct r600_pipe_resource_state *rstate)
2506 {
2507 rstate->id = R600_PIPE_STATE_RESOURCE;
2508
2509 rstate->val[0] = 0;
2510 rstate->bo[0] = NULL;
2511 rstate->val[1] = 0;
2512 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2513 rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2514 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2515 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2516 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2517 rstate->val[4] = 0;
2518 rstate->val[5] = 0;
2519 rstate->val[6] = 0;
2520 rstate->val[7] = 0xc0000000;
2521 }
2522
2523
2524 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
2525 struct r600_pipe_resource_state *rstate,
2526 struct r600_resource *rbuffer,
2527 unsigned offset, unsigned stride,
2528 enum radeon_bo_usage usage)
2529 {
2530 uint64_t va;
2531
2532 va = r600_resource_va(ctx->screen, (void *)rbuffer);
2533 rstate->bo[0] = rbuffer;
2534 rstate->bo_usage[0] = usage;
2535 rstate->val[0] = (offset + va) & 0xFFFFFFFFUL;
2536 rstate->val[1] = rbuffer->buf->size - offset - 1;
2537 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2538 S_030008_STRIDE(stride) |
2539 (((va + offset) >> 32UL) & 0xFF);
2540 }