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r600g: fix grammar constant_buffer -> constant_buffers
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "evergreend.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31 #include "evergreen_compute.h"
32
33 static uint32_t eg_num_banks(uint32_t nbanks)
34 {
35 switch (nbanks) {
36 case 2:
37 return 0;
38 case 4:
39 return 1;
40 case 8:
41 default:
42 return 2;
43 case 16:
44 return 3;
45 }
46 }
47
48
49 static unsigned eg_tile_split(unsigned tile_split)
50 {
51 switch (tile_split) {
52 case 64: tile_split = 0; break;
53 case 128: tile_split = 1; break;
54 case 256: tile_split = 2; break;
55 case 512: tile_split = 3; break;
56 default:
57 case 1024: tile_split = 4; break;
58 case 2048: tile_split = 5; break;
59 case 4096: tile_split = 6; break;
60 }
61 return tile_split;
62 }
63
64 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65 {
66 switch (macro_tile_aspect) {
67 default:
68 case 1: macro_tile_aspect = 0; break;
69 case 2: macro_tile_aspect = 1; break;
70 case 4: macro_tile_aspect = 2; break;
71 case 8: macro_tile_aspect = 3; break;
72 }
73 return macro_tile_aspect;
74 }
75
76 static unsigned eg_bank_wh(unsigned bankwh)
77 {
78 switch (bankwh) {
79 default:
80 case 1: bankwh = 0; break;
81 case 2: bankwh = 1; break;
82 case 4: bankwh = 2; break;
83 case 8: bankwh = 3; break;
84 }
85 return bankwh;
86 }
87
88 static uint32_t r600_translate_blend_function(int blend_func)
89 {
90 switch (blend_func) {
91 case PIPE_BLEND_ADD:
92 return V_028780_COMB_DST_PLUS_SRC;
93 case PIPE_BLEND_SUBTRACT:
94 return V_028780_COMB_SRC_MINUS_DST;
95 case PIPE_BLEND_REVERSE_SUBTRACT:
96 return V_028780_COMB_DST_MINUS_SRC;
97 case PIPE_BLEND_MIN:
98 return V_028780_COMB_MIN_DST_SRC;
99 case PIPE_BLEND_MAX:
100 return V_028780_COMB_MAX_DST_SRC;
101 default:
102 R600_ERR("Unknown blend function %d\n", blend_func);
103 assert(0);
104 break;
105 }
106 return 0;
107 }
108
109 static uint32_t r600_translate_blend_factor(int blend_fact)
110 {
111 switch (blend_fact) {
112 case PIPE_BLENDFACTOR_ONE:
113 return V_028780_BLEND_ONE;
114 case PIPE_BLENDFACTOR_SRC_COLOR:
115 return V_028780_BLEND_SRC_COLOR;
116 case PIPE_BLENDFACTOR_SRC_ALPHA:
117 return V_028780_BLEND_SRC_ALPHA;
118 case PIPE_BLENDFACTOR_DST_ALPHA:
119 return V_028780_BLEND_DST_ALPHA;
120 case PIPE_BLENDFACTOR_DST_COLOR:
121 return V_028780_BLEND_DST_COLOR;
122 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123 return V_028780_BLEND_SRC_ALPHA_SATURATE;
124 case PIPE_BLENDFACTOR_CONST_COLOR:
125 return V_028780_BLEND_CONST_COLOR;
126 case PIPE_BLENDFACTOR_CONST_ALPHA:
127 return V_028780_BLEND_CONST_ALPHA;
128 case PIPE_BLENDFACTOR_ZERO:
129 return V_028780_BLEND_ZERO;
130 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136 case PIPE_BLENDFACTOR_INV_DST_COLOR:
137 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_SRC1_COLOR:
143 return V_028780_BLEND_SRC1_COLOR;
144 case PIPE_BLENDFACTOR_SRC1_ALPHA:
145 return V_028780_BLEND_SRC1_ALPHA;
146 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147 return V_028780_BLEND_INV_SRC1_COLOR;
148 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149 return V_028780_BLEND_INV_SRC1_ALPHA;
150 default:
151 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152 assert(0);
153 break;
154 }
155 return 0;
156 }
157
158 static unsigned r600_tex_dim(unsigned dim)
159 {
160 switch (dim) {
161 default:
162 case PIPE_TEXTURE_1D:
163 return V_030000_SQ_TEX_DIM_1D;
164 case PIPE_TEXTURE_1D_ARRAY:
165 return V_030000_SQ_TEX_DIM_1D_ARRAY;
166 case PIPE_TEXTURE_2D:
167 case PIPE_TEXTURE_RECT:
168 return V_030000_SQ_TEX_DIM_2D;
169 case PIPE_TEXTURE_2D_ARRAY:
170 return V_030000_SQ_TEX_DIM_2D_ARRAY;
171 case PIPE_TEXTURE_3D:
172 return V_030000_SQ_TEX_DIM_3D;
173 case PIPE_TEXTURE_CUBE:
174 return V_030000_SQ_TEX_DIM_CUBEMAP;
175 }
176 }
177
178 static uint32_t r600_translate_dbformat(enum pipe_format format)
179 {
180 switch (format) {
181 case PIPE_FORMAT_Z16_UNORM:
182 return V_028040_Z_16;
183 case PIPE_FORMAT_Z24X8_UNORM:
184 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
185 return V_028040_Z_24;
186 case PIPE_FORMAT_Z32_FLOAT:
187 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
188 return V_028040_Z_32_FLOAT;
189 default:
190 return ~0U;
191 }
192 }
193
194 static uint32_t r600_translate_colorswap(enum pipe_format format)
195 {
196 switch (format) {
197 /* 8-bit buffers. */
198 case PIPE_FORMAT_L4A4_UNORM:
199 case PIPE_FORMAT_A4R4_UNORM:
200 return V_028C70_SWAP_ALT;
201
202 case PIPE_FORMAT_A8_UNORM:
203 case PIPE_FORMAT_A8_SNORM:
204 case PIPE_FORMAT_A8_UINT:
205 case PIPE_FORMAT_A8_SINT:
206 case PIPE_FORMAT_A16_UNORM:
207 case PIPE_FORMAT_A16_SNORM:
208 case PIPE_FORMAT_A16_UINT:
209 case PIPE_FORMAT_A16_SINT:
210 case PIPE_FORMAT_A16_FLOAT:
211 case PIPE_FORMAT_A32_UINT:
212 case PIPE_FORMAT_A32_SINT:
213 case PIPE_FORMAT_A32_FLOAT:
214 case PIPE_FORMAT_R4A4_UNORM:
215 return V_028C70_SWAP_ALT_REV;
216 case PIPE_FORMAT_I8_UNORM:
217 case PIPE_FORMAT_I8_SNORM:
218 case PIPE_FORMAT_I8_UINT:
219 case PIPE_FORMAT_I8_SINT:
220 case PIPE_FORMAT_I16_UNORM:
221 case PIPE_FORMAT_I16_SNORM:
222 case PIPE_FORMAT_I16_UINT:
223 case PIPE_FORMAT_I16_SINT:
224 case PIPE_FORMAT_I16_FLOAT:
225 case PIPE_FORMAT_I32_UINT:
226 case PIPE_FORMAT_I32_SINT:
227 case PIPE_FORMAT_I32_FLOAT:
228 case PIPE_FORMAT_L8_UNORM:
229 case PIPE_FORMAT_L8_SNORM:
230 case PIPE_FORMAT_L8_UINT:
231 case PIPE_FORMAT_L8_SINT:
232 case PIPE_FORMAT_L8_SRGB:
233 case PIPE_FORMAT_L16_UNORM:
234 case PIPE_FORMAT_L16_SNORM:
235 case PIPE_FORMAT_L16_UINT:
236 case PIPE_FORMAT_L16_SINT:
237 case PIPE_FORMAT_L16_FLOAT:
238 case PIPE_FORMAT_L32_UINT:
239 case PIPE_FORMAT_L32_SINT:
240 case PIPE_FORMAT_L32_FLOAT:
241 case PIPE_FORMAT_R8_UNORM:
242 case PIPE_FORMAT_R8_SNORM:
243 case PIPE_FORMAT_R8_UINT:
244 case PIPE_FORMAT_R8_SINT:
245 return V_028C70_SWAP_STD;
246
247 /* 16-bit buffers. */
248 case PIPE_FORMAT_B5G6R5_UNORM:
249 return V_028C70_SWAP_STD_REV;
250
251 case PIPE_FORMAT_B5G5R5A1_UNORM:
252 case PIPE_FORMAT_B5G5R5X1_UNORM:
253 return V_028C70_SWAP_ALT;
254
255 case PIPE_FORMAT_B4G4R4A4_UNORM:
256 case PIPE_FORMAT_B4G4R4X4_UNORM:
257 return V_028C70_SWAP_ALT;
258
259 case PIPE_FORMAT_Z16_UNORM:
260 return V_028C70_SWAP_STD;
261
262 case PIPE_FORMAT_L8A8_UNORM:
263 case PIPE_FORMAT_L8A8_SNORM:
264 case PIPE_FORMAT_L8A8_UINT:
265 case PIPE_FORMAT_L8A8_SINT:
266 case PIPE_FORMAT_L8A8_SRGB:
267 case PIPE_FORMAT_L16A16_UNORM:
268 case PIPE_FORMAT_L16A16_SNORM:
269 case PIPE_FORMAT_L16A16_UINT:
270 case PIPE_FORMAT_L16A16_SINT:
271 case PIPE_FORMAT_L16A16_FLOAT:
272 case PIPE_FORMAT_L32A32_UINT:
273 case PIPE_FORMAT_L32A32_SINT:
274 case PIPE_FORMAT_L32A32_FLOAT:
275 return V_028C70_SWAP_ALT;
276 case PIPE_FORMAT_R8G8_UNORM:
277 case PIPE_FORMAT_R8G8_SNORM:
278 case PIPE_FORMAT_R8G8_UINT:
279 case PIPE_FORMAT_R8G8_SINT:
280 return V_028C70_SWAP_STD;
281
282 case PIPE_FORMAT_R16_UNORM:
283 case PIPE_FORMAT_R16_SNORM:
284 case PIPE_FORMAT_R16_UINT:
285 case PIPE_FORMAT_R16_SINT:
286 case PIPE_FORMAT_R16_FLOAT:
287 return V_028C70_SWAP_STD;
288
289 /* 32-bit buffers. */
290 case PIPE_FORMAT_A8B8G8R8_SRGB:
291 return V_028C70_SWAP_STD_REV;
292 case PIPE_FORMAT_B8G8R8A8_SRGB:
293 return V_028C70_SWAP_ALT;
294
295 case PIPE_FORMAT_B8G8R8A8_UNORM:
296 case PIPE_FORMAT_B8G8R8X8_UNORM:
297 return V_028C70_SWAP_ALT;
298
299 case PIPE_FORMAT_A8R8G8B8_UNORM:
300 case PIPE_FORMAT_X8R8G8B8_UNORM:
301 return V_028C70_SWAP_ALT_REV;
302 case PIPE_FORMAT_R8G8B8A8_SNORM:
303 case PIPE_FORMAT_R8G8B8A8_UNORM:
304 case PIPE_FORMAT_R8G8B8A8_SINT:
305 case PIPE_FORMAT_R8G8B8A8_UINT:
306 case PIPE_FORMAT_R8G8B8X8_UNORM:
307 return V_028C70_SWAP_STD;
308
309 case PIPE_FORMAT_A8B8G8R8_UNORM:
310 case PIPE_FORMAT_X8B8G8R8_UNORM:
311 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
312 return V_028C70_SWAP_STD_REV;
313
314 case PIPE_FORMAT_Z24X8_UNORM:
315 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
316 return V_028C70_SWAP_STD;
317
318 case PIPE_FORMAT_X8Z24_UNORM:
319 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
320 return V_028C70_SWAP_STD;
321
322 case PIPE_FORMAT_R10G10B10A2_UNORM:
323 case PIPE_FORMAT_R10G10B10X2_SNORM:
324 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
325 return V_028C70_SWAP_STD;
326
327 case PIPE_FORMAT_B10G10R10A2_UNORM:
328 case PIPE_FORMAT_B10G10R10A2_UINT:
329 return V_028C70_SWAP_ALT;
330
331 case PIPE_FORMAT_R11G11B10_FLOAT:
332 case PIPE_FORMAT_R32_FLOAT:
333 case PIPE_FORMAT_R32_UINT:
334 case PIPE_FORMAT_R32_SINT:
335 case PIPE_FORMAT_Z32_FLOAT:
336 case PIPE_FORMAT_R16G16_FLOAT:
337 case PIPE_FORMAT_R16G16_UNORM:
338 case PIPE_FORMAT_R16G16_SNORM:
339 case PIPE_FORMAT_R16G16_UINT:
340 case PIPE_FORMAT_R16G16_SINT:
341 case PIPE_FORMAT_R16G16B16_FLOAT:
342 case PIPE_FORMAT_R32G32B32_FLOAT:
343 return V_028C70_SWAP_STD;
344
345 /* 64-bit buffers. */
346 case PIPE_FORMAT_R32G32_FLOAT:
347 case PIPE_FORMAT_R32G32_UINT:
348 case PIPE_FORMAT_R32G32_SINT:
349 case PIPE_FORMAT_R16G16B16A16_UNORM:
350 case PIPE_FORMAT_R16G16B16A16_SNORM:
351 case PIPE_FORMAT_R16G16B16A16_UINT:
352 case PIPE_FORMAT_R16G16B16A16_SINT:
353 case PIPE_FORMAT_R16G16B16A16_FLOAT:
354 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
355
356 /* 128-bit buffers. */
357 case PIPE_FORMAT_R32G32B32A32_FLOAT:
358 case PIPE_FORMAT_R32G32B32A32_SNORM:
359 case PIPE_FORMAT_R32G32B32A32_UNORM:
360 case PIPE_FORMAT_R32G32B32A32_SINT:
361 case PIPE_FORMAT_R32G32B32A32_UINT:
362 return V_028C70_SWAP_STD;
363 default:
364 R600_ERR("unsupported colorswap format %d\n", format);
365 return ~0U;
366 }
367 return ~0U;
368 }
369
370 static uint32_t r600_translate_colorformat(enum pipe_format format)
371 {
372 switch (format) {
373 /* 8-bit buffers. */
374 case PIPE_FORMAT_A8_UNORM:
375 case PIPE_FORMAT_A8_SNORM:
376 case PIPE_FORMAT_A8_UINT:
377 case PIPE_FORMAT_A8_SINT:
378 case PIPE_FORMAT_I8_UNORM:
379 case PIPE_FORMAT_I8_SNORM:
380 case PIPE_FORMAT_I8_UINT:
381 case PIPE_FORMAT_I8_SINT:
382 case PIPE_FORMAT_L8_UNORM:
383 case PIPE_FORMAT_L8_SNORM:
384 case PIPE_FORMAT_L8_UINT:
385 case PIPE_FORMAT_L8_SINT:
386 case PIPE_FORMAT_L8_SRGB:
387 case PIPE_FORMAT_R8_UNORM:
388 case PIPE_FORMAT_R8_SNORM:
389 case PIPE_FORMAT_R8_UINT:
390 case PIPE_FORMAT_R8_SINT:
391 return V_028C70_COLOR_8;
392
393 /* 16-bit buffers. */
394 case PIPE_FORMAT_B5G6R5_UNORM:
395 return V_028C70_COLOR_5_6_5;
396
397 case PIPE_FORMAT_B5G5R5A1_UNORM:
398 case PIPE_FORMAT_B5G5R5X1_UNORM:
399 return V_028C70_COLOR_1_5_5_5;
400
401 case PIPE_FORMAT_B4G4R4A4_UNORM:
402 case PIPE_FORMAT_B4G4R4X4_UNORM:
403 return V_028C70_COLOR_4_4_4_4;
404
405 case PIPE_FORMAT_Z16_UNORM:
406 return V_028C70_COLOR_16;
407
408 case PIPE_FORMAT_L8A8_UNORM:
409 case PIPE_FORMAT_L8A8_SNORM:
410 case PIPE_FORMAT_L8A8_UINT:
411 case PIPE_FORMAT_L8A8_SINT:
412 case PIPE_FORMAT_L8A8_SRGB:
413 case PIPE_FORMAT_R8G8_UNORM:
414 case PIPE_FORMAT_R8G8_SNORM:
415 case PIPE_FORMAT_R8G8_UINT:
416 case PIPE_FORMAT_R8G8_SINT:
417 return V_028C70_COLOR_8_8;
418
419 case PIPE_FORMAT_R16_UNORM:
420 case PIPE_FORMAT_R16_SNORM:
421 case PIPE_FORMAT_R16_UINT:
422 case PIPE_FORMAT_R16_SINT:
423 case PIPE_FORMAT_A16_UNORM:
424 case PIPE_FORMAT_A16_SNORM:
425 case PIPE_FORMAT_A16_UINT:
426 case PIPE_FORMAT_A16_SINT:
427 case PIPE_FORMAT_L16_UNORM:
428 case PIPE_FORMAT_L16_SNORM:
429 case PIPE_FORMAT_L16_UINT:
430 case PIPE_FORMAT_L16_SINT:
431 case PIPE_FORMAT_I16_UNORM:
432 case PIPE_FORMAT_I16_SNORM:
433 case PIPE_FORMAT_I16_UINT:
434 case PIPE_FORMAT_I16_SINT:
435 return V_028C70_COLOR_16;
436
437 case PIPE_FORMAT_R16_FLOAT:
438 case PIPE_FORMAT_A16_FLOAT:
439 case PIPE_FORMAT_L16_FLOAT:
440 case PIPE_FORMAT_I16_FLOAT:
441 return V_028C70_COLOR_16_FLOAT;
442
443 /* 32-bit buffers. */
444 case PIPE_FORMAT_A8B8G8R8_SRGB:
445 case PIPE_FORMAT_A8B8G8R8_UNORM:
446 case PIPE_FORMAT_A8R8G8B8_UNORM:
447 case PIPE_FORMAT_B8G8R8A8_SRGB:
448 case PIPE_FORMAT_B8G8R8A8_UNORM:
449 case PIPE_FORMAT_B8G8R8X8_UNORM:
450 case PIPE_FORMAT_R8G8B8A8_SNORM:
451 case PIPE_FORMAT_R8G8B8A8_UNORM:
452 case PIPE_FORMAT_R8G8B8X8_UNORM:
453 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
454 case PIPE_FORMAT_X8B8G8R8_UNORM:
455 case PIPE_FORMAT_X8R8G8B8_UNORM:
456 case PIPE_FORMAT_R8G8B8_UNORM:
457 case PIPE_FORMAT_R8G8B8A8_SINT:
458 case PIPE_FORMAT_R8G8B8A8_UINT:
459 return V_028C70_COLOR_8_8_8_8;
460
461 case PIPE_FORMAT_R10G10B10A2_UNORM:
462 case PIPE_FORMAT_R10G10B10X2_SNORM:
463 case PIPE_FORMAT_B10G10R10A2_UNORM:
464 case PIPE_FORMAT_B10G10R10A2_UINT:
465 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
466 return V_028C70_COLOR_2_10_10_10;
467
468 case PIPE_FORMAT_Z24X8_UNORM:
469 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
470 return V_028C70_COLOR_8_24;
471
472 case PIPE_FORMAT_X8Z24_UNORM:
473 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
474 return V_028C70_COLOR_24_8;
475
476 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
477 return V_028C70_COLOR_X24_8_32_FLOAT;
478
479 case PIPE_FORMAT_R32_UINT:
480 case PIPE_FORMAT_R32_SINT:
481 case PIPE_FORMAT_A32_UINT:
482 case PIPE_FORMAT_A32_SINT:
483 case PIPE_FORMAT_L32_UINT:
484 case PIPE_FORMAT_L32_SINT:
485 case PIPE_FORMAT_I32_UINT:
486 case PIPE_FORMAT_I32_SINT:
487 return V_028C70_COLOR_32;
488
489 case PIPE_FORMAT_R32_FLOAT:
490 case PIPE_FORMAT_A32_FLOAT:
491 case PIPE_FORMAT_L32_FLOAT:
492 case PIPE_FORMAT_I32_FLOAT:
493 case PIPE_FORMAT_Z32_FLOAT:
494 return V_028C70_COLOR_32_FLOAT;
495
496 case PIPE_FORMAT_R16G16_FLOAT:
497 case PIPE_FORMAT_L16A16_FLOAT:
498 return V_028C70_COLOR_16_16_FLOAT;
499
500 case PIPE_FORMAT_R16G16_UNORM:
501 case PIPE_FORMAT_R16G16_SNORM:
502 case PIPE_FORMAT_R16G16_UINT:
503 case PIPE_FORMAT_R16G16_SINT:
504 case PIPE_FORMAT_L16A16_UNORM:
505 case PIPE_FORMAT_L16A16_SNORM:
506 case PIPE_FORMAT_L16A16_UINT:
507 case PIPE_FORMAT_L16A16_SINT:
508 return V_028C70_COLOR_16_16;
509
510 case PIPE_FORMAT_R11G11B10_FLOAT:
511 return V_028C70_COLOR_10_11_11_FLOAT;
512
513 /* 64-bit buffers. */
514 case PIPE_FORMAT_R16G16B16A16_UINT:
515 case PIPE_FORMAT_R16G16B16A16_SINT:
516 case PIPE_FORMAT_R16G16B16A16_UNORM:
517 case PIPE_FORMAT_R16G16B16A16_SNORM:
518 return V_028C70_COLOR_16_16_16_16;
519
520 case PIPE_FORMAT_R16G16B16_FLOAT:
521 case PIPE_FORMAT_R16G16B16A16_FLOAT:
522 return V_028C70_COLOR_16_16_16_16_FLOAT;
523
524 case PIPE_FORMAT_R32G32_FLOAT:
525 case PIPE_FORMAT_L32A32_FLOAT:
526 return V_028C70_COLOR_32_32_FLOAT;
527
528 case PIPE_FORMAT_R32G32_SINT:
529 case PIPE_FORMAT_R32G32_UINT:
530 case PIPE_FORMAT_L32A32_UINT:
531 case PIPE_FORMAT_L32A32_SINT:
532 return V_028C70_COLOR_32_32;
533
534 /* 96-bit buffers. */
535 case PIPE_FORMAT_R32G32B32_FLOAT:
536 return V_028C70_COLOR_32_32_32_FLOAT;
537
538 /* 128-bit buffers. */
539 case PIPE_FORMAT_R32G32B32A32_SNORM:
540 case PIPE_FORMAT_R32G32B32A32_UNORM:
541 case PIPE_FORMAT_R32G32B32A32_SINT:
542 case PIPE_FORMAT_R32G32B32A32_UINT:
543 return V_028C70_COLOR_32_32_32_32;
544 case PIPE_FORMAT_R32G32B32A32_FLOAT:
545 return V_028C70_COLOR_32_32_32_32_FLOAT;
546
547 /* YUV buffers. */
548 case PIPE_FORMAT_UYVY:
549 case PIPE_FORMAT_YUYV:
550 default:
551 return ~0U; /* Unsupported. */
552 }
553 }
554
555 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
556 {
557 if (R600_BIG_ENDIAN) {
558 switch(colorformat) {
559
560 /* 8-bit buffers. */
561 case V_028C70_COLOR_8:
562 return ENDIAN_NONE;
563
564 /* 16-bit buffers. */
565 case V_028C70_COLOR_5_6_5:
566 case V_028C70_COLOR_1_5_5_5:
567 case V_028C70_COLOR_4_4_4_4:
568 case V_028C70_COLOR_16:
569 case V_028C70_COLOR_8_8:
570 return ENDIAN_8IN16;
571
572 /* 32-bit buffers. */
573 case V_028C70_COLOR_8_8_8_8:
574 case V_028C70_COLOR_2_10_10_10:
575 case V_028C70_COLOR_8_24:
576 case V_028C70_COLOR_24_8:
577 case V_028C70_COLOR_32_FLOAT:
578 case V_028C70_COLOR_16_16_FLOAT:
579 case V_028C70_COLOR_16_16:
580 return ENDIAN_8IN32;
581
582 /* 64-bit buffers. */
583 case V_028C70_COLOR_16_16_16_16:
584 case V_028C70_COLOR_16_16_16_16_FLOAT:
585 return ENDIAN_8IN16;
586
587 case V_028C70_COLOR_32_32_FLOAT:
588 case V_028C70_COLOR_32_32:
589 case V_028C70_COLOR_X24_8_32_FLOAT:
590 return ENDIAN_8IN32;
591
592 /* 96-bit buffers. */
593 case V_028C70_COLOR_32_32_32_FLOAT:
594 /* 128-bit buffers. */
595 case V_028C70_COLOR_32_32_32_32_FLOAT:
596 case V_028C70_COLOR_32_32_32_32:
597 return ENDIAN_8IN32;
598 default:
599 return ENDIAN_NONE; /* Unsupported. */
600 }
601 } else {
602 return ENDIAN_NONE;
603 }
604 }
605
606 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
607 {
608 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
609 }
610
611 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
612 {
613 return r600_translate_colorformat(format) != ~0U &&
614 r600_translate_colorswap(format) != ~0U;
615 }
616
617 static bool r600_is_zs_format_supported(enum pipe_format format)
618 {
619 return r600_translate_dbformat(format) != ~0U;
620 }
621
622 boolean evergreen_is_format_supported(struct pipe_screen *screen,
623 enum pipe_format format,
624 enum pipe_texture_target target,
625 unsigned sample_count,
626 unsigned usage)
627 {
628 unsigned retval = 0;
629
630 if (target >= PIPE_MAX_TEXTURE_TYPES) {
631 R600_ERR("r600: unsupported texture type %d\n", target);
632 return FALSE;
633 }
634
635 if (!util_format_is_supported(format, usage))
636 return FALSE;
637
638 /* Multisample */
639 if (sample_count > 1)
640 return FALSE;
641
642 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
643 r600_is_sampler_format_supported(screen, format)) {
644 retval |= PIPE_BIND_SAMPLER_VIEW;
645 }
646
647 if ((usage & (PIPE_BIND_RENDER_TARGET |
648 PIPE_BIND_DISPLAY_TARGET |
649 PIPE_BIND_SCANOUT |
650 PIPE_BIND_SHARED)) &&
651 r600_is_colorbuffer_format_supported(format)) {
652 retval |= usage &
653 (PIPE_BIND_RENDER_TARGET |
654 PIPE_BIND_DISPLAY_TARGET |
655 PIPE_BIND_SCANOUT |
656 PIPE_BIND_SHARED);
657 }
658
659 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
660 r600_is_zs_format_supported(format)) {
661 retval |= PIPE_BIND_DEPTH_STENCIL;
662 }
663
664 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
665 r600_is_vertex_format_supported(format)) {
666 retval |= PIPE_BIND_VERTEX_BUFFER;
667 }
668
669 if (usage & PIPE_BIND_TRANSFER_READ)
670 retval |= PIPE_BIND_TRANSFER_READ;
671 if (usage & PIPE_BIND_TRANSFER_WRITE)
672 retval |= PIPE_BIND_TRANSFER_WRITE;
673
674 return retval == usage;
675 }
676
677 static void *evergreen_create_blend_state(struct pipe_context *ctx,
678 const struct pipe_blend_state *state)
679 {
680 struct r600_context *rctx = (struct r600_context *)ctx;
681 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
682 struct r600_pipe_state *rstate;
683 uint32_t color_control = 0, target_mask;
684 /* XXX there is more then 8 framebuffer */
685 unsigned blend_cntl[8];
686
687 if (blend == NULL) {
688 return NULL;
689 }
690
691 rstate = &blend->rstate;
692
693 rstate->id = R600_PIPE_STATE_BLEND;
694
695 target_mask = 0;
696 if (state->logicop_enable) {
697 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
698 } else {
699 color_control |= (0xcc << 16);
700 }
701 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
702 if (state->independent_blend_enable) {
703 for (int i = 0; i < 8; i++) {
704 target_mask |= (state->rt[i].colormask << (4 * i));
705 }
706 } else {
707 for (int i = 0; i < 8; i++) {
708 target_mask |= (state->rt[0].colormask << (4 * i));
709 }
710 }
711 blend->cb_target_mask = target_mask;
712
713 if (target_mask)
714 color_control |= S_028808_MODE(V_028808_CB_NORMAL);
715 else
716 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
717
718 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
719 color_control);
720 /* only have dual source on MRT0 */
721 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
722 for (int i = 0; i < 8; i++) {
723 /* state->rt entries > 0 only written if independent blending */
724 const int j = state->independent_blend_enable ? i : 0;
725
726 unsigned eqRGB = state->rt[j].rgb_func;
727 unsigned srcRGB = state->rt[j].rgb_src_factor;
728 unsigned dstRGB = state->rt[j].rgb_dst_factor;
729 unsigned eqA = state->rt[j].alpha_func;
730 unsigned srcA = state->rt[j].alpha_src_factor;
731 unsigned dstA = state->rt[j].alpha_dst_factor;
732
733 blend_cntl[i] = 0;
734 if (!state->rt[j].blend_enable)
735 continue;
736
737 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
738 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
739 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
740 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
741
742 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
743 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
744 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
745 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
746 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
747 }
748 }
749 for (int i = 0; i < 8; i++) {
750 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
751 }
752
753 return rstate;
754 }
755
756 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
757 const struct pipe_depth_stencil_alpha_state *state)
758 {
759 struct r600_context *rctx = (struct r600_context *)ctx;
760 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
761 unsigned db_depth_control, alpha_test_control, alpha_ref;
762 unsigned db_render_control;
763 struct r600_pipe_state *rstate;
764
765 if (dsa == NULL) {
766 return NULL;
767 }
768
769 dsa->valuemask[0] = state->stencil[0].valuemask;
770 dsa->valuemask[1] = state->stencil[1].valuemask;
771 dsa->writemask[0] = state->stencil[0].writemask;
772 dsa->writemask[1] = state->stencil[1].writemask;
773
774 rstate = &dsa->rstate;
775
776 rstate->id = R600_PIPE_STATE_DSA;
777 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
778 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
779 S_028800_ZFUNC(state->depth.func);
780
781 /* stencil */
782 if (state->stencil[0].enabled) {
783 db_depth_control |= S_028800_STENCIL_ENABLE(1);
784 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
785 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
786 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
787 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
788
789 if (state->stencil[1].enabled) {
790 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
791 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
792 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
793 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
794 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
795 }
796 }
797
798 /* alpha */
799 alpha_test_control = 0;
800 alpha_ref = 0;
801 if (state->alpha.enabled) {
802 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
803 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
804 alpha_ref = fui(state->alpha.ref_value);
805 }
806 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
807 dsa->alpha_ref = alpha_ref;
808
809 /* misc */
810 db_render_control = 0;
811 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
812 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control);
813 return rstate;
814 }
815
816 static void *evergreen_create_rs_state(struct pipe_context *ctx,
817 const struct pipe_rasterizer_state *state)
818 {
819 struct r600_context *rctx = (struct r600_context *)ctx;
820 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
821 struct r600_pipe_state *rstate;
822 unsigned tmp;
823 unsigned prov_vtx = 1, polygon_dual_mode;
824 float psize_min, psize_max;
825
826 if (rs == NULL) {
827 return NULL;
828 }
829
830 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
831 state->fill_back != PIPE_POLYGON_MODE_FILL);
832
833 if (state->flatshade_first)
834 prov_vtx = 0;
835
836 rstate = &rs->rstate;
837 rs->flatshade = state->flatshade;
838 rs->sprite_coord_enable = state->sprite_coord_enable;
839 rs->two_side = state->light_twoside;
840 rs->clip_plane_enable = state->clip_plane_enable;
841 rs->pa_sc_line_stipple = state->line_stipple_enable ?
842 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
843 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
844 rs->pa_cl_clip_cntl =
845 S_028810_PS_UCP_MODE(3) |
846 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
847 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
848 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
849
850 /* offset */
851 rs->offset_units = state->offset_units;
852 rs->offset_scale = state->offset_scale * 12.0f;
853
854 rstate->id = R600_PIPE_STATE_RASTERIZER;
855 tmp = S_0286D4_FLAT_SHADE_ENA(1);
856 if (state->sprite_coord_enable) {
857 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
858 S_0286D4_PNT_SPRITE_OVRD_X(2) |
859 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
860 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
861 S_0286D4_PNT_SPRITE_OVRD_W(1);
862 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
863 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
864 }
865 }
866 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
867
868 /* point size 12.4 fixed point */
869 tmp = (unsigned)(state->point_size * 8.0);
870 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
871
872 if (state->point_size_per_vertex) {
873 psize_min = util_get_min_point_size(state);
874 psize_max = 8192;
875 } else {
876 /* Force the point size to be as if the vertex output was disabled. */
877 psize_min = state->point_size;
878 psize_max = state->point_size;
879 }
880 /* Divide by two, because 0.5 = 1 pixel. */
881 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
882 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
883 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
884
885 tmp = (unsigned)state->line_width * 8;
886 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
887 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
888 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
889 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
890
891 if (rctx->chip_class == CAYMAN) {
892 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
893 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
894 } else {
895 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
896 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
897 }
898 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
899 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
900 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
901 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
902 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
903 S_028814_FACE(!state->front_ccw) |
904 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
905 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
906 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
907 S_028814_POLY_MODE(polygon_dual_mode) |
908 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
909 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
910 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
911 return rstate;
912 }
913
914 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
915 const struct pipe_sampler_state *state)
916 {
917 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
918 union util_color uc;
919 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
920
921 if (rstate == NULL) {
922 return NULL;
923 }
924
925 rstate->id = R600_PIPE_STATE_SAMPLER;
926 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
927 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
928 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
929 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
930 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
931 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
932 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
933 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
934 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
935 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
936 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
937 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
938 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
939 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
940 NULL, 0);
941 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
942 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
943 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
944 S_03C008_TYPE(1),
945 NULL, 0);
946
947 if (uc.ui) {
948 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
949 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
950 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
951 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
952 }
953 return rstate;
954 }
955
956 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
957 struct pipe_resource *texture,
958 const struct pipe_sampler_view *state)
959 {
960 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
961 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
962 struct r600_pipe_resource_state *rstate;
963 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
964 unsigned format, endian;
965 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
966 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
967 unsigned height, depth, width;
968 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
969
970 if (view == NULL)
971 return NULL;
972 rstate = &view->state;
973
974 /* initialize base object */
975 view->base = *state;
976 view->base.texture = NULL;
977 pipe_reference(NULL, &texture->reference);
978 view->base.texture = texture;
979 view->base.reference.count = 1;
980 view->base.context = ctx;
981
982 swizzle[0] = state->swizzle_r;
983 swizzle[1] = state->swizzle_g;
984 swizzle[2] = state->swizzle_b;
985 swizzle[3] = state->swizzle_a;
986
987 format = r600_translate_texformat(ctx->screen, state->format,
988 swizzle,
989 &word4, &yuv_format);
990 assert(format != ~0);
991 if (format == ~0) {
992 FREE(view);
993 return NULL;
994 }
995
996 if (tmp->is_depth && !tmp->is_flushing_texture) {
997 r600_init_flushed_depth_texture(ctx, texture, NULL);
998 tmp = tmp->flushed_depth_texture;
999 if (!tmp) {
1000 FREE(view);
1001 return NULL;
1002 }
1003 }
1004
1005 endian = r600_colorformat_endian_swap(format);
1006
1007 if (!rscreen->use_surface_alloc) {
1008 height = texture->height0;
1009 depth = texture->depth0;
1010 width = texture->width0;
1011 pitch = align(tmp->pitch_in_blocks[0] *
1012 util_format_get_blockwidth(state->format), 8);
1013 array_mode = tmp->array_mode[0];
1014 tile_type = tmp->tile_type;
1015 tile_split = 0;
1016 macro_aspect = 0;
1017 bankw = 0;
1018 bankh = 0;
1019 } else {
1020 width = tmp->surface.level[0].npix_x;
1021 height = tmp->surface.level[0].npix_y;
1022 depth = tmp->surface.level[0].npix_z;
1023 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1024 tile_type = tmp->tile_type;
1025
1026 switch (tmp->surface.level[0].mode) {
1027 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1028 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1029 break;
1030 case RADEON_SURF_MODE_2D:
1031 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1032 break;
1033 case RADEON_SURF_MODE_1D:
1034 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1035 break;
1036 case RADEON_SURF_MODE_LINEAR:
1037 default:
1038 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1039 break;
1040 }
1041 tile_split = tmp->surface.tile_split;
1042 macro_aspect = tmp->surface.mtilea;
1043 bankw = tmp->surface.bankw;
1044 bankh = tmp->surface.bankh;
1045 tile_split = eg_tile_split(tile_split);
1046 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1047 bankw = eg_bank_wh(bankw);
1048 bankh = eg_bank_wh(bankh);
1049 }
1050 /* 128 bit formats require tile type = 1 */
1051 if (rscreen->chip_class == CAYMAN) {
1052 if (util_format_get_blocksize(state->format) >= 16)
1053 tile_type = 1;
1054 }
1055 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1056
1057 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1058 height = 1;
1059 depth = texture->array_size;
1060 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1061 depth = texture->array_size;
1062 }
1063
1064 rstate->bo[0] = &tmp->resource;
1065 rstate->bo[1] = &tmp->resource;
1066 rstate->bo_usage[0] = RADEON_USAGE_READ;
1067 rstate->bo_usage[1] = RADEON_USAGE_READ;
1068
1069 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1070 S_030000_PITCH((pitch / 8) - 1) |
1071 S_030000_TEX_WIDTH(width - 1));
1072 if (rscreen->chip_class == CAYMAN)
1073 rstate->val[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1074 else
1075 rstate->val[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1076 rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1077 S_030004_TEX_DEPTH(depth - 1) |
1078 S_030004_ARRAY_MODE(array_mode));
1079 rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1080 if (state->u.tex.last_level) {
1081 rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1082 } else {
1083 rstate->val[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1084 }
1085 rstate->val[4] = (word4 |
1086 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1087 S_030010_ENDIAN_SWAP(endian) |
1088 S_030010_BASE_LEVEL(state->u.tex.first_level));
1089 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1090 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1091 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1092 /* aniso max 16 samples */
1093 rstate->val[6] = (S_030018_MAX_ANISO(4)) |
1094 (S_030018_TILE_SPLIT(tile_split));
1095 rstate->val[7] = S_03001C_DATA_FORMAT(format) |
1096 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1097 S_03001C_BANK_WIDTH(bankw) |
1098 S_03001C_BANK_HEIGHT(bankh) |
1099 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1100 S_03001C_NUM_BANKS(nbanks);
1101
1102 return &view->base;
1103 }
1104
1105 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1106 struct pipe_sampler_view **views)
1107 {
1108 struct r600_context *rctx = (struct r600_context *)ctx;
1109 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1110
1111 for (int i = 0; i < count; i++) {
1112 if (resource[i]) {
1113 r600_context_pipe_state_set_vs_resource(rctx, &resource[i]->state,
1114 i + R600_MAX_CONST_BUFFERS);
1115 }
1116 }
1117 }
1118
1119 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1120 struct pipe_sampler_view **views)
1121 {
1122 struct r600_context *rctx = (struct r600_context *)ctx;
1123 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1124 int i;
1125 int has_depth = 0;
1126
1127 for (i = 0; i < count; i++) {
1128 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1129 if (resource[i]) {
1130 if (((struct r600_resource_texture *)resource[i]->base.texture)->is_depth)
1131 has_depth = 1;
1132 r600_context_pipe_state_set_ps_resource(rctx, &resource[i]->state,
1133 i + R600_MAX_CONST_BUFFERS);
1134 } else
1135 r600_context_pipe_state_set_ps_resource(rctx, NULL,
1136 i + R600_MAX_CONST_BUFFERS);
1137
1138 pipe_sampler_view_reference(
1139 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1140 views[i]);
1141 } else {
1142 if (resource[i]) {
1143 if (((struct r600_resource_texture *)resource[i]->base.texture)->is_depth)
1144 has_depth = 1;
1145 }
1146 }
1147 }
1148 for (i = count; i < NUM_TEX_UNITS; i++) {
1149 if (rctx->ps_samplers.views[i]) {
1150 r600_context_pipe_state_set_ps_resource(rctx, NULL,
1151 i + R600_MAX_CONST_BUFFERS);
1152 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1153 }
1154 }
1155 rctx->have_depth_texture = has_depth;
1156 rctx->ps_samplers.n_views = count;
1157 }
1158
1159 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1160 {
1161 struct r600_context *rctx = (struct r600_context *)ctx;
1162 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1163
1164 if (count)
1165 r600_inval_texture_cache(rctx);
1166
1167 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1168 rctx->ps_samplers.n_samplers = count;
1169
1170 for (int i = 0; i < count; i++) {
1171 evergreen_context_pipe_state_set_ps_sampler(rctx, rstates[i], i);
1172 }
1173 }
1174
1175 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1176 {
1177 struct r600_context *rctx = (struct r600_context *)ctx;
1178 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1179
1180 if (count)
1181 r600_inval_texture_cache(rctx);
1182
1183 for (int i = 0; i < count; i++) {
1184 evergreen_context_pipe_state_set_vs_sampler(rctx, rstates[i], i);
1185 }
1186 }
1187
1188 static void evergreen_set_clip_state(struct pipe_context *ctx,
1189 const struct pipe_clip_state *state)
1190 {
1191 struct r600_context *rctx = (struct r600_context *)ctx;
1192 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1193 struct pipe_constant_buffer cb;
1194
1195 if (rstate == NULL)
1196 return;
1197
1198 rctx->clip = *state;
1199 rstate->id = R600_PIPE_STATE_CLIP;
1200 for (int i = 0; i < 6; i++) {
1201 r600_pipe_state_add_reg(rstate,
1202 R_0285BC_PA_CL_UCP0_X + i * 16,
1203 fui(state->ucp[i][0]));
1204 r600_pipe_state_add_reg(rstate,
1205 R_0285C0_PA_CL_UCP0_Y + i * 16,
1206 fui(state->ucp[i][1]) );
1207 r600_pipe_state_add_reg(rstate,
1208 R_0285C4_PA_CL_UCP0_Z + i * 16,
1209 fui(state->ucp[i][2]));
1210 r600_pipe_state_add_reg(rstate,
1211 R_0285C8_PA_CL_UCP0_W + i * 16,
1212 fui(state->ucp[i][3]));
1213 }
1214
1215 free(rctx->states[R600_PIPE_STATE_CLIP]);
1216 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1217 r600_context_pipe_state_set(rctx, rstate);
1218
1219 cb.buffer = NULL;
1220 cb.user_buffer = state->ucp;
1221 cb.buffer_offset = 0;
1222 cb.buffer_size = 4*4*8;
1223 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1224 pipe_resource_reference(&cb.buffer, NULL);
1225 }
1226
1227 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1228 const struct pipe_poly_stipple *state)
1229 {
1230 }
1231
1232 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1233 {
1234 }
1235
1236 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1237 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1238 uint32_t *tl, uint32_t *br)
1239 {
1240 /* EG hw workaround */
1241 if (br_x == 0)
1242 tl_x = 1;
1243 if (br_y == 0)
1244 tl_y = 1;
1245
1246 /* cayman hw workaround */
1247 if (rctx->chip_class == CAYMAN) {
1248 if (br_x == 1 && br_y == 1)
1249 br_x = 2;
1250 }
1251
1252 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1253 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1254 }
1255
1256 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1257 const struct pipe_scissor_state *state)
1258 {
1259 struct r600_context *rctx = (struct r600_context *)ctx;
1260 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1261 uint32_t tl, br;
1262
1263 if (rstate == NULL)
1264 return;
1265
1266 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1267
1268 rstate->id = R600_PIPE_STATE_SCISSOR;
1269 r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1270 r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1271
1272 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1273 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1274 r600_context_pipe_state_set(rctx, rstate);
1275 }
1276
1277 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1278 const struct pipe_viewport_state *state)
1279 {
1280 struct r600_context *rctx = (struct r600_context *)ctx;
1281 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1282
1283 if (rstate == NULL)
1284 return;
1285
1286 rctx->viewport = *state;
1287 rstate->id = R600_PIPE_STATE_VIEWPORT;
1288 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1289 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1290 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1291 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1292 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1293 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1294
1295 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1296 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1297 r600_context_pipe_state_set(rctx, rstate);
1298 }
1299
1300 void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1301 const struct pipe_framebuffer_state *state, int cb)
1302 {
1303 struct r600_screen *rscreen = rctx->screen;
1304 struct r600_resource_texture *rtex;
1305 struct pipe_resource * pipe_tex;
1306 struct r600_surface *surf;
1307 unsigned level = state->cbufs[cb]->u.tex.level;
1308 unsigned pitch, slice;
1309 unsigned color_info, color_attrib, color_dim = 0;
1310 unsigned format, swap, ntype, endian;
1311 uint64_t offset;
1312 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1313 const struct util_format_description *desc;
1314 int i;
1315 unsigned blend_clamp = 0, blend_bypass = 0;
1316
1317 surf = (struct r600_surface *)state->cbufs[cb];
1318 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1319 pipe_tex = state->cbufs[cb]->texture;
1320
1321 if (rtex->is_depth)
1322 rctx->have_depth_fb = TRUE;
1323
1324 if (rtex->is_depth && !rtex->is_flushing_texture) {
1325 r600_init_flushed_depth_texture(&rctx->context,
1326 state->cbufs[cb]->texture, NULL);
1327 rtex = rtex->flushed_depth_texture;
1328 assert(rtex);
1329 }
1330
1331 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1332 if (!rscreen->use_surface_alloc) {
1333 offset = r600_texture_get_offset(rtex,
1334 level, state->cbufs[cb]->u.tex.first_layer);
1335 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1336 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1337 if (slice) {
1338 slice = slice - 1;
1339 }
1340 color_info = S_028C70_ARRAY_MODE(rtex->array_mode[level]);
1341 tile_split = 0;
1342 macro_aspect = 0;
1343 bankw = 0;
1344 bankh = 0;
1345 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1346 tile_type = rtex->tile_type;
1347 } else {
1348 /* workaround for linear buffers */
1349 tile_type = 1;
1350 }
1351 } else {
1352 offset = rtex->surface.level[level].offset;
1353 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1354 offset += rtex->surface.level[level].slice_size *
1355 state->cbufs[cb]->u.tex.first_layer;
1356 }
1357 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1358 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1359 if (slice) {
1360 slice = slice - 1;
1361 }
1362 color_info = 0;
1363 switch (rtex->surface.level[level].mode) {
1364 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1365 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1366 tile_type = 1;
1367 break;
1368 case RADEON_SURF_MODE_1D:
1369 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1370 tile_type = rtex->tile_type;
1371 break;
1372 case RADEON_SURF_MODE_2D:
1373 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1374 tile_type = rtex->tile_type;
1375 break;
1376 case RADEON_SURF_MODE_LINEAR:
1377 default:
1378 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1379 tile_type = 1;
1380 break;
1381 }
1382 tile_split = rtex->surface.tile_split;
1383 macro_aspect = rtex->surface.mtilea;
1384 bankw = rtex->surface.bankw;
1385 bankh = rtex->surface.bankh;
1386 tile_split = eg_tile_split(tile_split);
1387 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1388 bankw = eg_bank_wh(bankw);
1389 bankh = eg_bank_wh(bankh);
1390 }
1391 /* 128 bit formats require tile type = 1 */
1392 if (rscreen->chip_class == CAYMAN) {
1393 if (util_format_get_blocksize(surf->base.format) >= 16)
1394 tile_type = 1;
1395 }
1396 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1397 desc = util_format_description(surf->base.format);
1398 for (i = 0; i < 4; i++) {
1399 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1400 break;
1401 }
1402 }
1403
1404 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1405 S_028C74_NUM_BANKS(nbanks) |
1406 S_028C74_BANK_WIDTH(bankw) |
1407 S_028C74_BANK_HEIGHT(bankh) |
1408 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1409 S_028C74_NON_DISP_TILING_ORDER(tile_type);
1410
1411 ntype = V_028C70_NUMBER_UNORM;
1412 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1413 ntype = V_028C70_NUMBER_SRGB;
1414 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1415 if (desc->channel[i].normalized)
1416 ntype = V_028C70_NUMBER_SNORM;
1417 else if (desc->channel[i].pure_integer)
1418 ntype = V_028C70_NUMBER_SINT;
1419 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1420 if (desc->channel[i].normalized)
1421 ntype = V_028C70_NUMBER_UNORM;
1422 else if (desc->channel[i].pure_integer)
1423 ntype = V_028C70_NUMBER_UINT;
1424 }
1425
1426 format = r600_translate_colorformat(surf->base.format);
1427 assert(format != ~0);
1428
1429 swap = r600_translate_colorswap(surf->base.format);
1430 assert(swap != ~0);
1431
1432 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1433 endian = ENDIAN_NONE;
1434 } else {
1435 endian = r600_colorformat_endian_swap(format);
1436 }
1437
1438 /* blend clamp should be set for all NORM/SRGB types */
1439 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1440 ntype == V_028C70_NUMBER_SRGB)
1441 blend_clamp = 1;
1442
1443 /* set blend bypass according to docs if SINT/UINT or
1444 8/24 COLOR variants */
1445 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1446 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1447 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1448 blend_clamp = 0;
1449 blend_bypass = 1;
1450 }
1451
1452 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT)
1453 rctx->sx_alpha_test_control |= S_028410_ALPHA_TEST_BYPASS(1);
1454 else
1455 rctx->sx_alpha_test_control &= C_028410_ALPHA_TEST_BYPASS;
1456
1457 color_info |= S_028C70_FORMAT(format) |
1458 S_028C70_COMP_SWAP(swap) |
1459 S_028C70_BLEND_CLAMP(blend_clamp) |
1460 S_028C70_BLEND_BYPASS(blend_bypass) |
1461 S_028C70_NUMBER_TYPE(ntype) |
1462 S_028C70_ENDIAN(endian);
1463
1464 if (rtex->is_rat) {
1465 color_info |= S_028C70_RAT(1);
1466 color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0)
1467 | S_028C78_HEIGHT_MAX(pipe_tex->height0);
1468 }
1469
1470 /* EXPORT_NORM is an optimzation that can be enabled for better
1471 * performance in certain cases.
1472 * EXPORT_NORM can be enabled if:
1473 * - 11-bit or smaller UNORM/SNORM/SRGB
1474 * - 16-bit or smaller FLOAT
1475 */
1476 /* XXX: This should probably be the same for all CBs if we want
1477 * useful alpha tests. */
1478 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1479 ((desc->channel[i].size < 12 &&
1480 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1481 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1482 (desc->channel[i].size < 17 &&
1483 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1484 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1485 } else {
1486 rctx->export_16bpc = false;
1487 }
1488 rctx->alpha_ref_dirty = true;
1489
1490 /* for possible dual-src MRT */
1491 if (cb == 0 && rctx->framebuffer.nr_cbufs == 1 && !rtex->is_rat) {
1492 r600_pipe_state_add_reg_bo(rstate,
1493 R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1494 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1495 }
1496
1497 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1498 offset >>= 8;
1499
1500 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1501 r600_pipe_state_add_reg_bo(rstate,
1502 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1503 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1504 r600_pipe_state_add_reg(rstate,
1505 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1506 color_dim);
1507 r600_pipe_state_add_reg_bo(rstate,
1508 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1509 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1510 r600_pipe_state_add_reg(rstate,
1511 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1512 S_028C64_PITCH_TILE_MAX(pitch));
1513 r600_pipe_state_add_reg(rstate,
1514 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1515 S_028C68_SLICE_TILE_MAX(slice));
1516 if (!rscreen->use_surface_alloc) {
1517 r600_pipe_state_add_reg(rstate,
1518 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1519 0x00000000);
1520 } else {
1521 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1522 r600_pipe_state_add_reg(rstate,
1523 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1524 0x00000000);
1525 } else {
1526 r600_pipe_state_add_reg(rstate,
1527 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1528 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1529 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1530 }
1531 }
1532 r600_pipe_state_add_reg_bo(rstate,
1533 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1534 color_attrib,
1535 &rtex->resource, RADEON_USAGE_READWRITE);
1536 }
1537
1538 static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1539 const struct pipe_framebuffer_state *state)
1540 {
1541 struct r600_screen *rscreen = rctx->screen;
1542 struct r600_resource_texture *rtex;
1543 struct r600_surface *surf;
1544 uint64_t offset;
1545 unsigned level, first_layer, pitch, slice, format, array_mode;
1546 unsigned macro_aspect, tile_split, bankh, bankw, z_info, nbanks;
1547
1548 if (state->zsbuf == NULL)
1549 return;
1550
1551 surf = (struct r600_surface *)state->zsbuf;
1552 level = surf->base.u.tex.level;
1553 rtex = (struct r600_resource_texture*)surf->base.texture;
1554 first_layer = surf->base.u.tex.first_layer;
1555 format = r600_translate_dbformat(surf->base.format);
1556 assert(format != ~0);
1557
1558 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1559 /* XXX remove this once tiling is properly supported */
1560 if (!rscreen->use_surface_alloc) {
1561 /* XXX remove this once tiling is properly supported */
1562 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1563 V_028C70_ARRAY_1D_TILED_THIN1;
1564
1565 offset += r600_texture_get_offset(rtex, level, first_layer);
1566 pitch = (rtex->pitch_in_blocks[level] / 8) - 1;
1567 slice = ((rtex->pitch_in_blocks[level] * surf->aligned_height) / 64);
1568 if (slice) {
1569 slice = slice - 1;
1570 }
1571 tile_split = 0;
1572 macro_aspect = 0;
1573 bankw = 0;
1574 bankh = 0;
1575 } else {
1576 offset += rtex->surface.level[level].offset;
1577 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1578 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1579 if (slice) {
1580 slice = slice - 1;
1581 }
1582 switch (rtex->surface.level[level].mode) {
1583 case RADEON_SURF_MODE_2D:
1584 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1585 break;
1586 case RADEON_SURF_MODE_1D:
1587 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1588 case RADEON_SURF_MODE_LINEAR:
1589 default:
1590 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1591 break;
1592 }
1593 tile_split = rtex->surface.tile_split;
1594 macro_aspect = rtex->surface.mtilea;
1595 bankw = rtex->surface.bankw;
1596 bankh = rtex->surface.bankh;
1597 tile_split = eg_tile_split(tile_split);
1598 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1599 bankw = eg_bank_wh(bankw);
1600 bankh = eg_bank_wh(bankh);
1601 }
1602 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1603 offset >>= 8;
1604
1605 z_info = S_028040_ARRAY_MODE(array_mode) |
1606 S_028040_FORMAT(format) |
1607 S_028040_TILE_SPLIT(tile_split)|
1608 S_028040_NUM_BANKS(nbanks) |
1609 S_028040_BANK_WIDTH(bankw) |
1610 S_028040_BANK_HEIGHT(bankh) |
1611 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1612
1613 r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE,
1614 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1615 r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE,
1616 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1617 if (!rscreen->use_surface_alloc) {
1618 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1619 0x00000000);
1620 } else {
1621 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1622 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1623 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1624 }
1625
1626 if (rtex->stencil) {
1627 uint64_t stencil_offset =
1628 r600_texture_get_offset(rtex->stencil, level, first_layer);
1629 unsigned stile_split;
1630
1631 stile_split = eg_tile_split(rtex->stencil->surface.tile_split);
1632 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1633 stencil_offset >>= 8;
1634
1635 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
1636 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1637 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1638 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1639 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1640 1 | S_028044_TILE_SPLIT(stile_split),
1641 &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1642 } else {
1643 if (rscreen->use_surface_alloc && rtex->surface.flags & RADEON_SURF_SBUFFER) {
1644 uint64_t stencil_offset = rtex->surface.stencil_offset;
1645 unsigned stile_split = rtex->surface.stencil_tile_split;
1646
1647 stile_split = eg_tile_split(stile_split);
1648 stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1649 stencil_offset += rtex->surface.level[level].offset / 4;
1650 stencil_offset >>= 8;
1651
1652 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
1653 stencil_offset, &rtex->resource,
1654 RADEON_USAGE_READWRITE);
1655 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1656 stencil_offset, &rtex->resource,
1657 RADEON_USAGE_READWRITE);
1658 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1659 1 | S_028044_TILE_SPLIT(stile_split),
1660 &rtex->resource,
1661 RADEON_USAGE_READWRITE);
1662 } else {
1663 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
1664 offset, &rtex->resource,
1665 RADEON_USAGE_READWRITE);
1666 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1667 offset, &rtex->resource,
1668 RADEON_USAGE_READWRITE);
1669 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1670 0, NULL, RADEON_USAGE_READWRITE);
1671 }
1672 }
1673
1674 r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, z_info,
1675 &rtex->resource, RADEON_USAGE_READWRITE);
1676 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1677 S_028058_PITCH_TILE_MAX(pitch));
1678 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1679 S_02805C_SLICE_TILE_MAX(slice));
1680 }
1681
1682 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1683 const struct pipe_framebuffer_state *state)
1684 {
1685 struct r600_context *rctx = (struct r600_context *)ctx;
1686 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1687 uint32_t tl, br;
1688 int i;
1689
1690 if (rstate == NULL)
1691 return;
1692
1693 r600_flush_framebuffer(rctx, false);
1694
1695 /* unreference old buffer and reference new one */
1696 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1697
1698 util_copy_framebuffer_state(&rctx->framebuffer, state);
1699
1700 /* build states */
1701 rctx->have_depth_fb = 0;
1702 rctx->export_16bpc = true;
1703 rctx->nr_cbufs = state->nr_cbufs;
1704 for (i = 0; i < state->nr_cbufs; i++) {
1705 evergreen_cb(rctx, rstate, state, i);
1706 }
1707
1708 for (; i < 8 ; i++) {
1709 r600_pipe_state_add_reg(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1710 }
1711
1712 if (state->zsbuf) {
1713 evergreen_db(rctx, rstate, state);
1714 }
1715
1716 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1717
1718 r600_pipe_state_add_reg(rstate,
1719 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1720 r600_pipe_state_add_reg(rstate,
1721 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1722
1723 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1724 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1725 r600_context_pipe_state_set(rctx, rstate);
1726
1727 if (state->zsbuf) {
1728 evergreen_polygon_offset_update(rctx);
1729 }
1730
1731 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1732 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1733 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1734 }
1735 }
1736
1737 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1738 {
1739 struct radeon_winsys_cs *cs = rctx->cs;
1740 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1741 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1742 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1743
1744 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1745 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1746 r600_write_value(cs, (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1747 }
1748
1749 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1750 {
1751 struct radeon_winsys_cs *cs = rctx->cs;
1752 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1753 unsigned db_count_control = 0;
1754 unsigned db_render_override =
1755 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1756 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1757 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1758
1759 if (a->occlusion_query_enabled) {
1760 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1761 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1762 }
1763
1764 r600_write_context_reg(cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1765 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1766 }
1767
1768 static void evergreen_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1769 {
1770 struct radeon_winsys_cs *cs = rctx->cs;
1771 struct pipe_vertex_buffer *vb = rctx->vertex_buffer;
1772 unsigned count = rctx->nr_vertex_buffers;
1773 unsigned i;
1774 uint64_t va;
1775
1776 for (i = 0; i < count; i++) {
1777 struct r600_resource *rbuffer = (struct r600_resource*)vb[i].buffer;
1778
1779 if (!rbuffer) {
1780 continue;
1781 }
1782
1783 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1784 va += vb[i].buffer_offset;
1785
1786 /* fetch resources start at index 992 */
1787 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1788 r600_write_value(cs, (992 + i) * 8);
1789 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1790 r600_write_value(cs, rbuffer->buf->size - vb[i].buffer_offset - 1); /* RESOURCEi_WORD1 */
1791 r600_write_value(cs, /* RESOURCEi_WORD2 */
1792 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1793 S_030008_STRIDE(vb[i].stride) |
1794 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1795 r600_write_value(cs, /* RESOURCEi_WORD3 */
1796 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1797 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1798 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1799 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1800 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1801 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1802 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1803 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1804
1805 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1806 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1807 }
1808 }
1809
1810 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1811 struct r600_constbuf_state *state,
1812 unsigned buffer_id_base,
1813 unsigned reg_alu_constbuf_size,
1814 unsigned reg_alu_const_cache)
1815 {
1816 struct radeon_winsys_cs *cs = rctx->cs;
1817 uint32_t dirty_mask = state->dirty_mask;
1818
1819 while (dirty_mask) {
1820 struct pipe_constant_buffer *cb;
1821 struct r600_resource *rbuffer;
1822 uint64_t va;
1823 unsigned buffer_index = ffs(dirty_mask) - 1;
1824
1825 cb = &state->cb[buffer_index];
1826 rbuffer = (struct r600_resource*)cb->buffer;
1827 assert(rbuffer);
1828
1829 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1830 va += cb->buffer_offset;
1831
1832 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1833 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1834 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
1835
1836 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1837 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1838
1839 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1840 r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
1841 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1842 r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1843 r600_write_value(cs, /* RESOURCEi_WORD2 */
1844 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1845 S_030008_STRIDE(16) |
1846 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1847 r600_write_value(cs, /* RESOURCEi_WORD3 */
1848 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1849 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1850 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1851 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1852 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1853 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1854 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1855 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1856
1857 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1858 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1859
1860 dirty_mask &= ~(1 << buffer_index);
1861 }
1862 state->dirty_mask = 0;
1863 }
1864
1865 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1866 {
1867 evergreen_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 176,
1868 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1869 R_028980_ALU_CONST_CACHE_VS_0);
1870 }
1871
1872 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1873 {
1874 evergreen_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1875 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1876 R_028940_ALU_CONST_CACHE_PS_0);
1877 }
1878
1879 void evergreen_init_state_functions(struct r600_context *rctx)
1880 {
1881 r600_init_atom(&rctx->cb_misc_state.atom, evergreen_emit_cb_misc_state, 0, 0);
1882 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1883 r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 6, 0);
1884 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1885 r600_init_atom(&rctx->vertex_buffer_state, evergreen_emit_vertex_buffers, 0, 0);
1886 r600_init_atom(&rctx->vs_constbuf_state.atom, evergreen_emit_vs_constant_buffers, 0, 0);
1887 r600_init_atom(&rctx->ps_constbuf_state.atom, evergreen_emit_ps_constant_buffers, 0, 0);
1888
1889 rctx->context.create_blend_state = evergreen_create_blend_state;
1890 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1891 rctx->context.create_fs_state = r600_create_shader_state_ps;
1892 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1893 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1894 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1895 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1896 rctx->context.create_vs_state = r600_create_shader_state_vs;
1897 rctx->context.bind_blend_state = r600_bind_blend_state;
1898 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1899 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1900 rctx->context.bind_fs_state = r600_bind_ps_shader;
1901 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1902 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1903 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1904 rctx->context.bind_vs_state = r600_bind_vs_shader;
1905 rctx->context.delete_blend_state = r600_delete_state;
1906 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1907 rctx->context.delete_fs_state = r600_delete_ps_shader;
1908 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1909 rctx->context.delete_sampler_state = r600_delete_state;
1910 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1911 rctx->context.delete_vs_state = r600_delete_vs_shader;
1912 rctx->context.set_blend_color = r600_set_blend_color;
1913 rctx->context.set_clip_state = evergreen_set_clip_state;
1914 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1915 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1916 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1917 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1918 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1919 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1920 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1921 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1922 rctx->context.set_index_buffer = r600_set_index_buffer;
1923 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1924 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1925 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1926 rctx->context.texture_barrier = r600_texture_barrier;
1927 rctx->context.create_stream_output_target = r600_create_so_target;
1928 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1929 rctx->context.set_stream_output_targets = r600_set_so_targets;
1930 evergreen_init_compute_state_functions(rctx);
1931 }
1932
1933 static void cayman_init_atom_start_cs(struct r600_context *rctx)
1934 {
1935 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1936
1937 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1938
1939 /* This must be first. */
1940 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1941 r600_store_value(cb, 0x80000000);
1942 r600_store_value(cb, 0x80000000);
1943
1944 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
1945 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
1946 /* always set the temp clauses */
1947 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
1948
1949 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
1950 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
1951 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
1952
1953 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
1954
1955 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
1956
1957 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
1958 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
1959 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
1960 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
1961 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
1962 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
1963 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
1964 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
1965 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
1966 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
1967 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
1968 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
1969 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
1970 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
1971
1972 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
1973 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
1974 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
1975
1976 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
1977 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
1978 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
1979
1980 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
1981
1982 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
1983
1984 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1985 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
1986 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
1987
1988 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
1989 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
1990 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
1991
1992 r600_store_context_reg(cb, CM_R_028804_DB_EQAA, 0x110000);
1993
1994 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
1995 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
1996 r600_store_value(cb, 0);
1997 r600_store_value(cb, 0);
1998 r600_store_value(cb, 0);
1999 r600_store_value(cb, 0);
2000 r600_store_value(cb, 0);
2001 r600_store_value(cb, 0);
2002 r600_store_value(cb, 0);
2003 r600_store_value(cb, 0);
2004 r600_store_value(cb, 0);
2005 r600_store_value(cb, 0);
2006 r600_store_value(cb, 0);
2007 r600_store_value(cb, 0);
2008 r600_store_value(cb, 0);
2009 r600_store_value(cb, 0);
2010 r600_store_value(cb, 0);
2011 r600_store_value(cb, 0);
2012 r600_store_value(cb, 0);
2013 r600_store_value(cb, 0);
2014 r600_store_value(cb, 0);
2015 r600_store_value(cb, 0);
2016 r600_store_value(cb, 0);
2017 r600_store_value(cb, 0);
2018 r600_store_value(cb, 0);
2019 r600_store_value(cb, 0);
2020 r600_store_value(cb, 0);
2021 r600_store_value(cb, 0);
2022 r600_store_value(cb, 0);
2023 r600_store_value(cb, 0);
2024 r600_store_value(cb, 0);
2025 r600_store_value(cb, 0);
2026 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2027 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2028 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2029
2030 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2031
2032 r600_store_context_reg_seq(cb, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2033 r600_store_value(cb, ~0); /* CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 */
2034 r600_store_value(cb, ~0); /* CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 */
2035
2036 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2037 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2038 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2039
2040 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2041
2042 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2043 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2044 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2045 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2046
2047 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2048 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2049
2050 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2051 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2052 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2053
2054 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2055 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2056 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2057 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2058
2059 r600_store_context_reg_seq(cb, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
2060 r600_store_value(cb, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2061 r600_store_value(cb, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2062
2063 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2064 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2065 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2066 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2067 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2068
2069 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2070 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2071 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2072
2073 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2074 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2075 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2076
2077 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2078 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2079 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2080
2081 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2082 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2083
2084 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2085 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2086 }
2087
2088 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2089 {
2090 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2091 int ps_prio;
2092 int vs_prio;
2093 int gs_prio;
2094 int es_prio;
2095 int hs_prio, cs_prio, ls_prio;
2096 int num_ps_gprs;
2097 int num_vs_gprs;
2098 int num_gs_gprs;
2099 int num_es_gprs;
2100 int num_hs_gprs;
2101 int num_ls_gprs;
2102 int num_temp_gprs;
2103 int num_ps_threads;
2104 int num_vs_threads;
2105 int num_gs_threads;
2106 int num_es_threads;
2107 int num_hs_threads;
2108 int num_ls_threads;
2109 int num_ps_stack_entries;
2110 int num_vs_stack_entries;
2111 int num_gs_stack_entries;
2112 int num_es_stack_entries;
2113 int num_hs_stack_entries;
2114 int num_ls_stack_entries;
2115 enum radeon_family family;
2116 unsigned tmp;
2117
2118 if (rctx->chip_class == CAYMAN) {
2119 cayman_init_atom_start_cs(rctx);
2120 return;
2121 }
2122
2123 r600_init_command_buffer(cb, 256, EMIT_EARLY);
2124
2125 /* This must be first. */
2126 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2127 r600_store_value(cb, 0x80000000);
2128 r600_store_value(cb, 0x80000000);
2129
2130 family = rctx->family;
2131 ps_prio = 0;
2132 vs_prio = 1;
2133 gs_prio = 2;
2134 es_prio = 3;
2135 hs_prio = 0;
2136 ls_prio = 0;
2137 cs_prio = 0;
2138
2139 switch (family) {
2140 case CHIP_CEDAR:
2141 default:
2142 num_ps_gprs = 93;
2143 num_vs_gprs = 46;
2144 num_temp_gprs = 4;
2145 num_gs_gprs = 31;
2146 num_es_gprs = 31;
2147 num_hs_gprs = 23;
2148 num_ls_gprs = 23;
2149 num_ps_threads = 96;
2150 num_vs_threads = 16;
2151 num_gs_threads = 16;
2152 num_es_threads = 16;
2153 num_hs_threads = 16;
2154 num_ls_threads = 16;
2155 num_ps_stack_entries = 42;
2156 num_vs_stack_entries = 42;
2157 num_gs_stack_entries = 42;
2158 num_es_stack_entries = 42;
2159 num_hs_stack_entries = 42;
2160 num_ls_stack_entries = 42;
2161 break;
2162 case CHIP_REDWOOD:
2163 num_ps_gprs = 93;
2164 num_vs_gprs = 46;
2165 num_temp_gprs = 4;
2166 num_gs_gprs = 31;
2167 num_es_gprs = 31;
2168 num_hs_gprs = 23;
2169 num_ls_gprs = 23;
2170 num_ps_threads = 128;
2171 num_vs_threads = 20;
2172 num_gs_threads = 20;
2173 num_es_threads = 20;
2174 num_hs_threads = 20;
2175 num_ls_threads = 20;
2176 num_ps_stack_entries = 42;
2177 num_vs_stack_entries = 42;
2178 num_gs_stack_entries = 42;
2179 num_es_stack_entries = 42;
2180 num_hs_stack_entries = 42;
2181 num_ls_stack_entries = 42;
2182 break;
2183 case CHIP_JUNIPER:
2184 num_ps_gprs = 93;
2185 num_vs_gprs = 46;
2186 num_temp_gprs = 4;
2187 num_gs_gprs = 31;
2188 num_es_gprs = 31;
2189 num_hs_gprs = 23;
2190 num_ls_gprs = 23;
2191 num_ps_threads = 128;
2192 num_vs_threads = 20;
2193 num_gs_threads = 20;
2194 num_es_threads = 20;
2195 num_hs_threads = 20;
2196 num_ls_threads = 20;
2197 num_ps_stack_entries = 85;
2198 num_vs_stack_entries = 85;
2199 num_gs_stack_entries = 85;
2200 num_es_stack_entries = 85;
2201 num_hs_stack_entries = 85;
2202 num_ls_stack_entries = 85;
2203 break;
2204 case CHIP_CYPRESS:
2205 case CHIP_HEMLOCK:
2206 num_ps_gprs = 93;
2207 num_vs_gprs = 46;
2208 num_temp_gprs = 4;
2209 num_gs_gprs = 31;
2210 num_es_gprs = 31;
2211 num_hs_gprs = 23;
2212 num_ls_gprs = 23;
2213 num_ps_threads = 128;
2214 num_vs_threads = 20;
2215 num_gs_threads = 20;
2216 num_es_threads = 20;
2217 num_hs_threads = 20;
2218 num_ls_threads = 20;
2219 num_ps_stack_entries = 85;
2220 num_vs_stack_entries = 85;
2221 num_gs_stack_entries = 85;
2222 num_es_stack_entries = 85;
2223 num_hs_stack_entries = 85;
2224 num_ls_stack_entries = 85;
2225 break;
2226 case CHIP_PALM:
2227 num_ps_gprs = 93;
2228 num_vs_gprs = 46;
2229 num_temp_gprs = 4;
2230 num_gs_gprs = 31;
2231 num_es_gprs = 31;
2232 num_hs_gprs = 23;
2233 num_ls_gprs = 23;
2234 num_ps_threads = 96;
2235 num_vs_threads = 16;
2236 num_gs_threads = 16;
2237 num_es_threads = 16;
2238 num_hs_threads = 16;
2239 num_ls_threads = 16;
2240 num_ps_stack_entries = 42;
2241 num_vs_stack_entries = 42;
2242 num_gs_stack_entries = 42;
2243 num_es_stack_entries = 42;
2244 num_hs_stack_entries = 42;
2245 num_ls_stack_entries = 42;
2246 break;
2247 case CHIP_SUMO:
2248 num_ps_gprs = 93;
2249 num_vs_gprs = 46;
2250 num_temp_gprs = 4;
2251 num_gs_gprs = 31;
2252 num_es_gprs = 31;
2253 num_hs_gprs = 23;
2254 num_ls_gprs = 23;
2255 num_ps_threads = 96;
2256 num_vs_threads = 25;
2257 num_gs_threads = 25;
2258 num_es_threads = 25;
2259 num_hs_threads = 25;
2260 num_ls_threads = 25;
2261 num_ps_stack_entries = 42;
2262 num_vs_stack_entries = 42;
2263 num_gs_stack_entries = 42;
2264 num_es_stack_entries = 42;
2265 num_hs_stack_entries = 42;
2266 num_ls_stack_entries = 42;
2267 break;
2268 case CHIP_SUMO2:
2269 num_ps_gprs = 93;
2270 num_vs_gprs = 46;
2271 num_temp_gprs = 4;
2272 num_gs_gprs = 31;
2273 num_es_gprs = 31;
2274 num_hs_gprs = 23;
2275 num_ls_gprs = 23;
2276 num_ps_threads = 96;
2277 num_vs_threads = 25;
2278 num_gs_threads = 25;
2279 num_es_threads = 25;
2280 num_hs_threads = 25;
2281 num_ls_threads = 25;
2282 num_ps_stack_entries = 85;
2283 num_vs_stack_entries = 85;
2284 num_gs_stack_entries = 85;
2285 num_es_stack_entries = 85;
2286 num_hs_stack_entries = 85;
2287 num_ls_stack_entries = 85;
2288 break;
2289 case CHIP_BARTS:
2290 num_ps_gprs = 93;
2291 num_vs_gprs = 46;
2292 num_temp_gprs = 4;
2293 num_gs_gprs = 31;
2294 num_es_gprs = 31;
2295 num_hs_gprs = 23;
2296 num_ls_gprs = 23;
2297 num_ps_threads = 128;
2298 num_vs_threads = 20;
2299 num_gs_threads = 20;
2300 num_es_threads = 20;
2301 num_hs_threads = 20;
2302 num_ls_threads = 20;
2303 num_ps_stack_entries = 85;
2304 num_vs_stack_entries = 85;
2305 num_gs_stack_entries = 85;
2306 num_es_stack_entries = 85;
2307 num_hs_stack_entries = 85;
2308 num_ls_stack_entries = 85;
2309 break;
2310 case CHIP_TURKS:
2311 num_ps_gprs = 93;
2312 num_vs_gprs = 46;
2313 num_temp_gprs = 4;
2314 num_gs_gprs = 31;
2315 num_es_gprs = 31;
2316 num_hs_gprs = 23;
2317 num_ls_gprs = 23;
2318 num_ps_threads = 128;
2319 num_vs_threads = 20;
2320 num_gs_threads = 20;
2321 num_es_threads = 20;
2322 num_hs_threads = 20;
2323 num_ls_threads = 20;
2324 num_ps_stack_entries = 42;
2325 num_vs_stack_entries = 42;
2326 num_gs_stack_entries = 42;
2327 num_es_stack_entries = 42;
2328 num_hs_stack_entries = 42;
2329 num_ls_stack_entries = 42;
2330 break;
2331 case CHIP_CAICOS:
2332 num_ps_gprs = 93;
2333 num_vs_gprs = 46;
2334 num_temp_gprs = 4;
2335 num_gs_gprs = 31;
2336 num_es_gprs = 31;
2337 num_hs_gprs = 23;
2338 num_ls_gprs = 23;
2339 num_ps_threads = 128;
2340 num_vs_threads = 10;
2341 num_gs_threads = 10;
2342 num_es_threads = 10;
2343 num_hs_threads = 10;
2344 num_ls_threads = 10;
2345 num_ps_stack_entries = 42;
2346 num_vs_stack_entries = 42;
2347 num_gs_stack_entries = 42;
2348 num_es_stack_entries = 42;
2349 num_hs_stack_entries = 42;
2350 num_ls_stack_entries = 42;
2351 break;
2352 }
2353
2354 tmp = 0;
2355 switch (family) {
2356 case CHIP_CEDAR:
2357 case CHIP_PALM:
2358 case CHIP_SUMO:
2359 case CHIP_SUMO2:
2360 case CHIP_CAICOS:
2361 break;
2362 default:
2363 tmp |= S_008C00_VC_ENABLE(1);
2364 break;
2365 }
2366 tmp |= S_008C00_EXPORT_SRC_C(1);
2367 tmp |= S_008C00_CS_PRIO(cs_prio);
2368 tmp |= S_008C00_LS_PRIO(ls_prio);
2369 tmp |= S_008C00_HS_PRIO(hs_prio);
2370 tmp |= S_008C00_PS_PRIO(ps_prio);
2371 tmp |= S_008C00_VS_PRIO(vs_prio);
2372 tmp |= S_008C00_GS_PRIO(gs_prio);
2373 tmp |= S_008C00_ES_PRIO(es_prio);
2374
2375 /* enable dynamic GPR resource management */
2376 if (rctx->screen->info.drm_minor >= 7) {
2377 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2378 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2379 /* always set temp clauses */
2380 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2381 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2382 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2383 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2384 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2385 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2386 S_028838_PS_GPRS(0x1e) |
2387 S_028838_VS_GPRS(0x1e) |
2388 S_028838_GS_GPRS(0x1e) |
2389 S_028838_ES_GPRS(0x1e) |
2390 S_028838_HS_GPRS(0x1e) |
2391 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2392 } else {
2393 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2394 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2395
2396 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2397 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2398 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2399 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2400
2401 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2402 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2403 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2404
2405 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2406 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2407 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2408 }
2409
2410 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2411 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2412 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2413 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2414 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2415 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2416
2417 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2418 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2419 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2420
2421 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2422 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2423 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2424
2425 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2426 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2427 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2428
2429 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2430 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2431 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2432
2433 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2434 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2435
2436 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2437 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2438
2439 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2440
2441 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2442 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2443 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2444 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2445 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2446 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2447 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2448
2449 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2450 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2451 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2452 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2453 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2454
2455 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2456 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2457 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2458 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2459 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2460 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2461 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2462 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2463 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2464 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2465 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2466 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2467 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2468 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2469
2470 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2471 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2472 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2473
2474 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2475 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2476 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2477
2478 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2479
2480 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2481 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2482 r600_store_value(cb, 0);
2483 r600_store_value(cb, 0);
2484 r600_store_value(cb, 0);
2485 r600_store_value(cb, 0);
2486 r600_store_value(cb, 0);
2487 r600_store_value(cb, 0);
2488 r600_store_value(cb, 0);
2489 r600_store_value(cb, 0);
2490 r600_store_value(cb, 0);
2491 r600_store_value(cb, 0);
2492 r600_store_value(cb, 0);
2493 r600_store_value(cb, 0);
2494 r600_store_value(cb, 0);
2495 r600_store_value(cb, 0);
2496 r600_store_value(cb, 0);
2497 r600_store_value(cb, 0);
2498 r600_store_value(cb, 0);
2499 r600_store_value(cb, 0);
2500 r600_store_value(cb, 0);
2501 r600_store_value(cb, 0);
2502 r600_store_value(cb, 0);
2503 r600_store_value(cb, 0);
2504 r600_store_value(cb, 0);
2505 r600_store_value(cb, 0);
2506 r600_store_value(cb, 0);
2507 r600_store_value(cb, 0);
2508 r600_store_value(cb, 0);
2509 r600_store_value(cb, 0);
2510 r600_store_value(cb, 0);
2511 r600_store_value(cb, 0);
2512 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2513 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2514 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2515
2516 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2517
2518 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2519 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2520 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2521
2522 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2523 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2524 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2525
2526 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2527 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2528 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2529
2530 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2531 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2532 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2533
2534 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2535 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2536 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2537 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2538
2539 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2540
2541 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2542 r600_store_value(cb, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
2543 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2544
2545 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 5);
2546 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2547 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2548 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2549 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2550 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
2551
2552 r600_store_context_reg(cb, R_028C3C_PA_SC_AA_MASK, ~0);
2553
2554 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2555 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2556 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2557
2558 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2559 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2560 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2561
2562 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2563 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2564 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2565
2566 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2567 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2568
2569 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2570 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2571 }
2572
2573 void evergreen_polygon_offset_update(struct r600_context *rctx)
2574 {
2575 struct r600_pipe_state state;
2576
2577 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2578 state.nregs = 0;
2579 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2580 float offset_units = rctx->rasterizer->offset_units;
2581 unsigned offset_db_fmt_cntl = 0, depth;
2582
2583 switch (rctx->framebuffer.zsbuf->format) {
2584 case PIPE_FORMAT_Z24X8_UNORM:
2585 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2586 depth = -24;
2587 offset_units *= 2.0f;
2588 break;
2589 case PIPE_FORMAT_Z32_FLOAT:
2590 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2591 depth = -23;
2592 offset_units *= 1.0f;
2593 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2594 break;
2595 case PIPE_FORMAT_Z16_UNORM:
2596 depth = -16;
2597 offset_units *= 4.0f;
2598 break;
2599 default:
2600 return;
2601 }
2602 /* XXX some of those reg can be computed with cso */
2603 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2604 r600_pipe_state_add_reg(&state,
2605 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2606 fui(rctx->rasterizer->offset_scale));
2607 r600_pipe_state_add_reg(&state,
2608 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2609 fui(offset_units));
2610 r600_pipe_state_add_reg(&state,
2611 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2612 fui(rctx->rasterizer->offset_scale));
2613 r600_pipe_state_add_reg(&state,
2614 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2615 fui(offset_units));
2616 r600_pipe_state_add_reg(&state,
2617 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2618 offset_db_fmt_cntl);
2619 r600_context_pipe_state_set(rctx, &state);
2620 }
2621 }
2622
2623 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2624 {
2625 struct r600_context *rctx = (struct r600_context *)ctx;
2626 struct r600_pipe_state *rstate = &shader->rstate;
2627 struct r600_shader *rshader = &shader->shader;
2628 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2629 int pos_index = -1, face_index = -1;
2630 int ninterp = 0;
2631 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2632 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2633 unsigned z_export = 0, stencil_export = 0;
2634
2635 rstate->nregs = 0;
2636
2637 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2638 for (i = 0; i < rshader->ninput; i++) {
2639 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2640 POSITION goes via GPRs from the SC so isn't counted */
2641 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2642 pos_index = i;
2643 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2644 face_index = i;
2645 else {
2646 ninterp++;
2647 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2648 have_linear = TRUE;
2649 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2650 have_perspective = TRUE;
2651 if (rshader->input[i].centroid)
2652 have_centroid = TRUE;
2653 }
2654
2655 sid = rshader->input[i].spi_sid;
2656
2657 if (sid) {
2658
2659 tmp = S_028644_SEMANTIC(sid);
2660
2661 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2662 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2663 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2664 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2665 tmp |= S_028644_FLAT_SHADE(1);
2666 }
2667
2668 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2669 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2670 tmp |= S_028644_PT_SPRITE_TEX(1);
2671 }
2672
2673 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2674 tmp);
2675
2676 idx++;
2677 }
2678 }
2679
2680 for (i = 0; i < rshader->noutput; i++) {
2681 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2682 z_export = 1;
2683 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2684 stencil_export = 1;
2685 }
2686 if (rshader->uses_kill)
2687 db_shader_control |= S_02880C_KILL_ENABLE(1);
2688
2689 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2690 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
2691
2692 exports_ps = 0;
2693 for (i = 0; i < rshader->noutput; i++) {
2694 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2695 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2696 exports_ps |= 1;
2697 }
2698
2699 num_cout = rshader->nr_ps_color_exports;
2700
2701 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2702 if (!exports_ps) {
2703 /* always at least export 1 component per pixel */
2704 exports_ps = 2;
2705 }
2706 shader->nr_ps_color_outputs = num_cout;
2707 if (ninterp == 0) {
2708 ninterp = 1;
2709 have_perspective = TRUE;
2710 }
2711
2712 if (!have_perspective && !have_linear)
2713 have_perspective = TRUE;
2714
2715 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2716 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2717 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2718 spi_input_z = 0;
2719 if (pos_index != -1) {
2720 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2721 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2722 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2723 spi_input_z |= 1;
2724 }
2725
2726 spi_ps_in_control_1 = 0;
2727 if (face_index != -1) {
2728 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2729 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2730 }
2731
2732 spi_baryc_cntl = 0;
2733 if (have_perspective)
2734 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2735 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2736 if (have_linear)
2737 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2738 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2739
2740 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2741 spi_ps_in_control_0);
2742 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2743 spi_ps_in_control_1);
2744 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2745 0);
2746 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2747 r600_pipe_state_add_reg(rstate,
2748 R_0286E0_SPI_BARYC_CNTL,
2749 spi_baryc_cntl);
2750
2751 r600_pipe_state_add_reg_bo(rstate,
2752 R_028840_SQ_PGM_START_PS,
2753 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2754 shader->bo, RADEON_USAGE_READ);
2755 r600_pipe_state_add_reg(rstate,
2756 R_028844_SQ_PGM_RESOURCES_PS,
2757 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2758 S_028844_PRIME_CACHE_ON_DRAW(1) |
2759 S_028844_STACK_SIZE(rshader->bc.nstack));
2760 r600_pipe_state_add_reg(rstate,
2761 R_02884C_SQ_PGM_EXPORTS_PS,
2762 exports_ps);
2763
2764 shader->db_shader_control = db_shader_control;
2765 shader->ps_depth_export = z_export | stencil_export;
2766
2767 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2768 if (rctx->rasterizer)
2769 shader->flatshade = rctx->rasterizer->flatshade;
2770 }
2771
2772 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2773 {
2774 struct r600_context *rctx = (struct r600_context *)ctx;
2775 struct r600_pipe_state *rstate = &shader->rstate;
2776 struct r600_shader *rshader = &shader->shader;
2777 unsigned spi_vs_out_id[10] = {};
2778 unsigned i, tmp, nparams = 0;
2779
2780 /* clear previous register */
2781 rstate->nregs = 0;
2782
2783 for (i = 0; i < rshader->noutput; i++) {
2784 if (rshader->output[i].spi_sid) {
2785 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2786 spi_vs_out_id[nparams / 4] |= tmp;
2787 nparams++;
2788 }
2789 }
2790
2791 for (i = 0; i < 10; i++) {
2792 r600_pipe_state_add_reg(rstate,
2793 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2794 spi_vs_out_id[i]);
2795 }
2796
2797 /* Certain attributes (position, psize, etc.) don't count as params.
2798 * VS is required to export at least one param and r600_shader_from_tgsi()
2799 * takes care of adding a dummy export.
2800 */
2801 if (nparams < 1)
2802 nparams = 1;
2803
2804 r600_pipe_state_add_reg(rstate,
2805 R_0286C4_SPI_VS_OUT_CONFIG,
2806 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2807 r600_pipe_state_add_reg(rstate,
2808 R_028860_SQ_PGM_RESOURCES_VS,
2809 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2810 S_028860_STACK_SIZE(rshader->bc.nstack));
2811 r600_pipe_state_add_reg_bo(rstate,
2812 R_02885C_SQ_PGM_START_VS,
2813 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2814 shader->bo, RADEON_USAGE_READ);
2815
2816 shader->pa_cl_vs_out_cntl =
2817 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2818 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2819 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2820 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2821 }
2822
2823 void evergreen_fetch_shader(struct pipe_context *ctx,
2824 struct r600_vertex_element *ve)
2825 {
2826 struct r600_context *rctx = (struct r600_context *)ctx;
2827 struct r600_pipe_state *rstate = &ve->rstate;
2828 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2829 rstate->nregs = 0;
2830 r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
2831 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2832 ve->fetch_shader, RADEON_USAGE_READ);
2833 }
2834
2835 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2836 {
2837 struct pipe_depth_stencil_alpha_state dsa;
2838 struct r600_pipe_state *rstate;
2839
2840 memset(&dsa, 0, sizeof(dsa));
2841
2842 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2843 r600_pipe_state_add_reg(rstate,
2844 R_028000_DB_RENDER_CONTROL,
2845 S_028000_DEPTH_COPY_ENABLE(1) |
2846 S_028000_STENCIL_COPY_ENABLE(1) |
2847 S_028000_COPY_CENTROID(1));
2848 /* Don't set the 'is_flush' flag in r600_pipe_dsa, evergreen doesn't need it. */
2849 return rstate;
2850 }
2851
2852 void evergreen_update_dual_export_state(struct r600_context * rctx)
2853 {
2854 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2855 !rctx->ps_shader->current->ps_depth_export;
2856
2857 unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
2858 V_02880C_EXPORT_DB_FULL;
2859
2860 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2861 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
2862 S_02880C_DB_SOURCE_FORMAT(db_source_format);
2863
2864 if (db_shader_control != rctx->db_shader_control) {
2865 struct r600_pipe_state rstate;
2866
2867 rctx->db_shader_control = db_shader_control;
2868
2869 rstate.nregs = 0;
2870 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2871 r600_context_pipe_state_set(rctx, &rstate);
2872 }
2873 }