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r600: add some missing cayman register defines
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static inline unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 default:
39 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
40 break;
41 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
42 break;
43 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
44 }
45 }
46
47 static uint32_t eg_num_banks(uint32_t nbanks)
48 {
49 switch (nbanks) {
50 case 2:
51 return 0;
52 case 4:
53 return 1;
54 case 8:
55 default:
56 return 2;
57 case 16:
58 return 3;
59 }
60 }
61
62
63 static unsigned eg_tile_split(unsigned tile_split)
64 {
65 switch (tile_split) {
66 case 64: tile_split = 0; break;
67 case 128: tile_split = 1; break;
68 case 256: tile_split = 2; break;
69 case 512: tile_split = 3; break;
70 default:
71 case 1024: tile_split = 4; break;
72 case 2048: tile_split = 5; break;
73 case 4096: tile_split = 6; break;
74 }
75 return tile_split;
76 }
77
78 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
79 {
80 switch (macro_tile_aspect) {
81 default:
82 case 1: macro_tile_aspect = 0; break;
83 case 2: macro_tile_aspect = 1; break;
84 case 4: macro_tile_aspect = 2; break;
85 case 8: macro_tile_aspect = 3; break;
86 }
87 return macro_tile_aspect;
88 }
89
90 static unsigned eg_bank_wh(unsigned bankwh)
91 {
92 switch (bankwh) {
93 default:
94 case 1: bankwh = 0; break;
95 case 2: bankwh = 1; break;
96 case 4: bankwh = 2; break;
97 case 8: bankwh = 3; break;
98 }
99 return bankwh;
100 }
101
102 static uint32_t r600_translate_blend_function(int blend_func)
103 {
104 switch (blend_func) {
105 case PIPE_BLEND_ADD:
106 return V_028780_COMB_DST_PLUS_SRC;
107 case PIPE_BLEND_SUBTRACT:
108 return V_028780_COMB_SRC_MINUS_DST;
109 case PIPE_BLEND_REVERSE_SUBTRACT:
110 return V_028780_COMB_DST_MINUS_SRC;
111 case PIPE_BLEND_MIN:
112 return V_028780_COMB_MIN_DST_SRC;
113 case PIPE_BLEND_MAX:
114 return V_028780_COMB_MAX_DST_SRC;
115 default:
116 R600_ERR("Unknown blend function %d\n", blend_func);
117 assert(0);
118 break;
119 }
120 return 0;
121 }
122
123 static uint32_t r600_translate_blend_factor(int blend_fact)
124 {
125 switch (blend_fact) {
126 case PIPE_BLENDFACTOR_ONE:
127 return V_028780_BLEND_ONE;
128 case PIPE_BLENDFACTOR_SRC_COLOR:
129 return V_028780_BLEND_SRC_COLOR;
130 case PIPE_BLENDFACTOR_SRC_ALPHA:
131 return V_028780_BLEND_SRC_ALPHA;
132 case PIPE_BLENDFACTOR_DST_ALPHA:
133 return V_028780_BLEND_DST_ALPHA;
134 case PIPE_BLENDFACTOR_DST_COLOR:
135 return V_028780_BLEND_DST_COLOR;
136 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
137 return V_028780_BLEND_SRC_ALPHA_SATURATE;
138 case PIPE_BLENDFACTOR_CONST_COLOR:
139 return V_028780_BLEND_CONST_COLOR;
140 case PIPE_BLENDFACTOR_CONST_ALPHA:
141 return V_028780_BLEND_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_ZERO:
143 return V_028780_BLEND_ZERO;
144 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
145 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
146 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
147 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
148 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
149 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
150 case PIPE_BLENDFACTOR_INV_DST_COLOR:
151 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
152 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
153 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
154 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
155 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
156 case PIPE_BLENDFACTOR_SRC1_COLOR:
157 return V_028780_BLEND_SRC1_COLOR;
158 case PIPE_BLENDFACTOR_SRC1_ALPHA:
159 return V_028780_BLEND_SRC1_ALPHA;
160 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
161 return V_028780_BLEND_INV_SRC1_COLOR;
162 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
163 return V_028780_BLEND_INV_SRC1_ALPHA;
164 default:
165 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
166 assert(0);
167 break;
168 }
169 return 0;
170 }
171
172 static unsigned r600_tex_dim(struct r600_texture *rtex,
173 unsigned view_target, unsigned nr_samples)
174 {
175 unsigned res_target = rtex->resource.b.b.target;
176
177 if (view_target == PIPE_TEXTURE_CUBE ||
178 view_target == PIPE_TEXTURE_CUBE_ARRAY)
179 res_target = view_target;
180 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
181 else if (res_target == PIPE_TEXTURE_CUBE ||
182 res_target == PIPE_TEXTURE_CUBE_ARRAY)
183 res_target = PIPE_TEXTURE_2D_ARRAY;
184
185 switch (res_target) {
186 default:
187 case PIPE_TEXTURE_1D:
188 return V_030000_SQ_TEX_DIM_1D;
189 case PIPE_TEXTURE_1D_ARRAY:
190 return V_030000_SQ_TEX_DIM_1D_ARRAY;
191 case PIPE_TEXTURE_2D:
192 case PIPE_TEXTURE_RECT:
193 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
194 V_030000_SQ_TEX_DIM_2D;
195 case PIPE_TEXTURE_2D_ARRAY:
196 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
197 V_030000_SQ_TEX_DIM_2D_ARRAY;
198 case PIPE_TEXTURE_3D:
199 return V_030000_SQ_TEX_DIM_3D;
200 case PIPE_TEXTURE_CUBE:
201 case PIPE_TEXTURE_CUBE_ARRAY:
202 return V_030000_SQ_TEX_DIM_CUBEMAP;
203 }
204 }
205
206 static uint32_t r600_translate_dbformat(enum pipe_format format)
207 {
208 switch (format) {
209 case PIPE_FORMAT_Z16_UNORM:
210 return V_028040_Z_16;
211 case PIPE_FORMAT_Z24X8_UNORM:
212 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
213 case PIPE_FORMAT_X8Z24_UNORM:
214 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
215 return V_028040_Z_24;
216 case PIPE_FORMAT_Z32_FLOAT:
217 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
218 return V_028040_Z_32_FLOAT;
219 default:
220 return ~0U;
221 }
222 }
223
224 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
225 {
226 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
227 FALSE) != ~0U;
228 }
229
230 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
231 {
232 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
233 r600_translate_colorswap(format, FALSE) != ~0U;
234 }
235
236 static bool r600_is_zs_format_supported(enum pipe_format format)
237 {
238 return r600_translate_dbformat(format) != ~0U;
239 }
240
241 boolean evergreen_is_format_supported(struct pipe_screen *screen,
242 enum pipe_format format,
243 enum pipe_texture_target target,
244 unsigned sample_count,
245 unsigned usage)
246 {
247 struct r600_screen *rscreen = (struct r600_screen*)screen;
248 unsigned retval = 0;
249
250 if (target >= PIPE_MAX_TEXTURE_TYPES) {
251 R600_ERR("r600: unsupported texture type %d\n", target);
252 return FALSE;
253 }
254
255 if (!util_format_is_supported(format, usage))
256 return FALSE;
257
258 if (sample_count > 1) {
259 if (!rscreen->has_msaa)
260 return FALSE;
261
262 switch (sample_count) {
263 case 2:
264 case 4:
265 case 8:
266 break;
267 default:
268 return FALSE;
269 }
270 }
271
272 if (usage & PIPE_BIND_SAMPLER_VIEW) {
273 if (target == PIPE_BUFFER) {
274 if (r600_is_vertex_format_supported(format))
275 retval |= PIPE_BIND_SAMPLER_VIEW;
276 } else {
277 if (r600_is_sampler_format_supported(screen, format))
278 retval |= PIPE_BIND_SAMPLER_VIEW;
279 }
280 }
281
282 if ((usage & (PIPE_BIND_RENDER_TARGET |
283 PIPE_BIND_DISPLAY_TARGET |
284 PIPE_BIND_SCANOUT |
285 PIPE_BIND_SHARED |
286 PIPE_BIND_BLENDABLE)) &&
287 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
288 retval |= usage &
289 (PIPE_BIND_RENDER_TARGET |
290 PIPE_BIND_DISPLAY_TARGET |
291 PIPE_BIND_SCANOUT |
292 PIPE_BIND_SHARED);
293 if (!util_format_is_pure_integer(format) &&
294 !util_format_is_depth_or_stencil(format))
295 retval |= usage & PIPE_BIND_BLENDABLE;
296 }
297
298 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
299 r600_is_zs_format_supported(format)) {
300 retval |= PIPE_BIND_DEPTH_STENCIL;
301 }
302
303 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
304 r600_is_vertex_format_supported(format)) {
305 retval |= PIPE_BIND_VERTEX_BUFFER;
306 }
307
308 if ((usage & PIPE_BIND_LINEAR) &&
309 !util_format_is_compressed(format) &&
310 !(usage & PIPE_BIND_DEPTH_STENCIL))
311 retval |= PIPE_BIND_LINEAR;
312
313 return retval == usage;
314 }
315
316 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
317 const struct pipe_blend_state *state, int mode)
318 {
319 uint32_t color_control = 0, target_mask = 0;
320 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
321
322 if (!blend) {
323 return NULL;
324 }
325
326 r600_init_command_buffer(&blend->buffer, 20);
327 r600_init_command_buffer(&blend->buffer_no_blend, 20);
328
329 if (state->logicop_enable) {
330 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
331 } else {
332 color_control |= (0xcc << 16);
333 }
334 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
335 if (state->independent_blend_enable) {
336 for (int i = 0; i < 8; i++) {
337 target_mask |= (state->rt[i].colormask << (4 * i));
338 }
339 } else {
340 for (int i = 0; i < 8; i++) {
341 target_mask |= (state->rt[0].colormask << (4 * i));
342 }
343 }
344
345 /* only have dual source on MRT0 */
346 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
347 blend->cb_target_mask = target_mask;
348 blend->alpha_to_one = state->alpha_to_one;
349
350 if (target_mask)
351 color_control |= S_028808_MODE(mode);
352 else
353 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
354
355
356 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
357 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
358 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
359 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
360 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
361 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
362 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
363 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
364
365 /* Copy over the dwords set so far into buffer_no_blend.
366 * Only the CB_BLENDi_CONTROL registers must be set after this. */
367 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
368 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
369
370 for (int i = 0; i < 8; i++) {
371 /* state->rt entries > 0 only written if independent blending */
372 const int j = state->independent_blend_enable ? i : 0;
373
374 unsigned eqRGB = state->rt[j].rgb_func;
375 unsigned srcRGB = state->rt[j].rgb_src_factor;
376 unsigned dstRGB = state->rt[j].rgb_dst_factor;
377 unsigned eqA = state->rt[j].alpha_func;
378 unsigned srcA = state->rt[j].alpha_src_factor;
379 unsigned dstA = state->rt[j].alpha_dst_factor;
380 uint32_t bc = 0;
381
382 r600_store_value(&blend->buffer_no_blend, 0);
383
384 if (!state->rt[j].blend_enable) {
385 r600_store_value(&blend->buffer, 0);
386 continue;
387 }
388
389 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
390 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
391 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
392 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
393
394 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
395 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
396 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
397 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
398 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
399 }
400 r600_store_value(&blend->buffer, bc);
401 }
402 return blend;
403 }
404
405 static void *evergreen_create_blend_state(struct pipe_context *ctx,
406 const struct pipe_blend_state *state)
407 {
408
409 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
410 }
411
412 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
413 const struct pipe_depth_stencil_alpha_state *state)
414 {
415 unsigned db_depth_control, alpha_test_control, alpha_ref;
416 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
417
418 if (!dsa) {
419 return NULL;
420 }
421
422 r600_init_command_buffer(&dsa->buffer, 3);
423
424 dsa->valuemask[0] = state->stencil[0].valuemask;
425 dsa->valuemask[1] = state->stencil[1].valuemask;
426 dsa->writemask[0] = state->stencil[0].writemask;
427 dsa->writemask[1] = state->stencil[1].writemask;
428 dsa->zwritemask = state->depth.writemask;
429
430 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
431 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
432 S_028800_ZFUNC(state->depth.func);
433
434 /* stencil */
435 if (state->stencil[0].enabled) {
436 db_depth_control |= S_028800_STENCIL_ENABLE(1);
437 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
438 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
439 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
440 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
441
442 if (state->stencil[1].enabled) {
443 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
444 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
445 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
446 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
447 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
448 }
449 }
450
451 /* alpha */
452 alpha_test_control = 0;
453 alpha_ref = 0;
454 if (state->alpha.enabled) {
455 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
456 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
457 alpha_ref = fui(state->alpha.ref_value);
458 }
459 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
460 dsa->alpha_ref = alpha_ref;
461
462 /* misc */
463 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
464 return dsa;
465 }
466
467 static void *evergreen_create_rs_state(struct pipe_context *ctx,
468 const struct pipe_rasterizer_state *state)
469 {
470 struct r600_context *rctx = (struct r600_context *)ctx;
471 unsigned tmp, spi_interp;
472 float psize_min, psize_max;
473 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
474
475 if (!rs) {
476 return NULL;
477 }
478
479 r600_init_command_buffer(&rs->buffer, 30);
480
481 rs->scissor_enable = state->scissor;
482 rs->clip_halfz = state->clip_halfz;
483 rs->flatshade = state->flatshade;
484 rs->sprite_coord_enable = state->sprite_coord_enable;
485 rs->rasterizer_discard = state->rasterizer_discard;
486 rs->two_side = state->light_twoside;
487 rs->clip_plane_enable = state->clip_plane_enable;
488 rs->pa_sc_line_stipple = state->line_stipple_enable ?
489 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
490 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
491 rs->pa_cl_clip_cntl =
492 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
493 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
494 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
495 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
496 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
497 rs->multisample_enable = state->multisample;
498
499 /* offset */
500 rs->offset_units = state->offset_units;
501 rs->offset_scale = state->offset_scale * 16.0f;
502 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
503 rs->offset_units_unscaled = state->offset_units_unscaled;
504
505 if (state->point_size_per_vertex) {
506 psize_min = util_get_min_point_size(state);
507 psize_max = 8192;
508 } else {
509 /* Force the point size to be as if the vertex output was disabled. */
510 psize_min = state->point_size;
511 psize_max = state->point_size;
512 }
513
514 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
515 if (state->sprite_coord_enable) {
516 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
517 S_0286D4_PNT_SPRITE_OVRD_X(2) |
518 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
519 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
520 S_0286D4_PNT_SPRITE_OVRD_W(1);
521 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
522 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
523 }
524 }
525
526 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
527 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
528 tmp = r600_pack_float_12p4(state->point_size/2);
529 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
530 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
531 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
532 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
533 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
534 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
535 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
536
537 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
538 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
539 S_028A48_MSAA_ENABLE(state->multisample) |
540 S_028A48_VPORT_SCISSOR_ENABLE(1) |
541 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
542
543 if (rctx->b.chip_class == CAYMAN) {
544 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
545 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
546 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
547 } else {
548 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
549 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
550 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
551 }
552
553 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
554 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
555 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
556 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
557 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
558 S_028814_FACE(!state->front_ccw) |
559 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
560 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
561 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
562 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
563 state->fill_back != PIPE_POLYGON_MODE_FILL) |
564 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
565 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
566 return rs;
567 }
568
569 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
570 const struct pipe_sampler_state *state)
571 {
572 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
573 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
574 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
575 : state->max_anisotropy;
576 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
577
578 if (!ss) {
579 return NULL;
580 }
581
582 ss->border_color_use = sampler_state_needs_border_color(state);
583
584 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
585 ss->tex_sampler_words[0] =
586 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
587 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
588 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
589 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
590 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
591 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
592 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
593 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
594 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
595 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
596 ss->tex_sampler_words[1] =
597 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
598 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
599 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
600 ss->tex_sampler_words[2] =
601 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
602 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
603 S_03C008_TYPE(1);
604
605 if (ss->border_color_use) {
606 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
607 }
608 return ss;
609 }
610
611 struct eg_buf_res_params {
612 enum pipe_format pipe_format;
613 unsigned offset;
614 unsigned size;
615 unsigned char swizzle[4];
616 bool uncached;
617 bool force_swizzle;
618 };
619
620 static void evergreen_fill_buffer_resource_words(struct r600_context *rctx,
621 struct pipe_resource *buffer,
622 struct eg_buf_res_params *params,
623 bool *skip_mip_address_reloc,
624 unsigned tex_resource_words[8])
625 {
626 struct r600_texture *tmp = (struct r600_texture*)buffer;
627 uint64_t va;
628 int stride = util_format_get_blocksize(params->pipe_format);
629 unsigned format, num_format, format_comp, endian;
630 unsigned swizzle_res;
631 const struct util_format_description *desc;
632
633 r600_vertex_data_type(params->pipe_format,
634 &format, &num_format, &format_comp,
635 &endian);
636
637 desc = util_format_description(params->pipe_format);
638
639 if (params->force_swizzle)
640 swizzle_res = r600_get_swizzle_combined(params->swizzle, NULL, TRUE);
641 else
642 swizzle_res = r600_get_swizzle_combined(desc->swizzle, params->swizzle, TRUE);
643
644 va = tmp->resource.gpu_address + params->offset;
645 *skip_mip_address_reloc = true;
646 tex_resource_words[0] = va;
647 tex_resource_words[1] = params->size - 1;
648 tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
649 S_030008_STRIDE(stride) |
650 S_030008_DATA_FORMAT(format) |
651 S_030008_NUM_FORMAT_ALL(num_format) |
652 S_030008_FORMAT_COMP_ALL(format_comp) |
653 S_030008_ENDIAN_SWAP(endian);
654 tex_resource_words[3] = swizzle_res | S_03000C_UNCACHED(params->uncached);
655 /*
656 * in theory dword 4 is for number of elements, for use with resinfo,
657 * but it seems to utterly fail to work, the amd gpu shader analyser
658 * uses a const buffer to store the element sizes for buffer txq
659 */
660 tex_resource_words[4] = 0;
661 tex_resource_words[5] = tex_resource_words[6] = 0;
662 tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
663 }
664
665 static struct pipe_sampler_view *
666 texture_buffer_sampler_view(struct r600_context *rctx,
667 struct r600_pipe_sampler_view *view,
668 unsigned width0, unsigned height0)
669 {
670 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
671 struct eg_buf_res_params params;
672
673 memset(&params, 0, sizeof(params));
674
675 params.pipe_format = view->base.format;
676 params.offset = view->base.u.buf.offset;
677 params.size = view->base.u.buf.size;
678 params.swizzle[0] = view->base.swizzle_r;
679 params.swizzle[1] = view->base.swizzle_g;
680 params.swizzle[2] = view->base.swizzle_b;
681 params.swizzle[3] = view->base.swizzle_a;
682
683 evergreen_fill_buffer_resource_words(rctx, view->base.texture,
684 &params, &view->skip_mip_address_reloc,
685 view->tex_resource_words);
686 view->tex_resource = &tmp->resource;
687
688 if (tmp->resource.gpu_address)
689 LIST_ADDTAIL(&view->list, &rctx->texture_buffers);
690 return &view->base;
691 }
692
693 struct eg_tex_res_params {
694 enum pipe_format pipe_format;
695 int force_level;
696 unsigned width0;
697 unsigned height0;
698 unsigned first_level;
699 unsigned last_level;
700 unsigned first_layer;
701 unsigned last_layer;
702 unsigned target;
703 unsigned char swizzle[4];
704 };
705
706 static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
707 struct pipe_resource *texture,
708 struct eg_tex_res_params *params,
709 bool *skip_mip_address_reloc,
710 unsigned tex_resource_words[8])
711 {
712 struct r600_screen *rscreen = (struct r600_screen*)rctx->b.b.screen;
713 struct r600_texture *tmp = (struct r600_texture*)texture;
714 unsigned format, endian;
715 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
716 unsigned char array_mode = 0, non_disp_tiling = 0;
717 unsigned height, depth, width;
718 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
719 struct legacy_surf_level *surflevel;
720 unsigned base_level, first_level, last_level;
721 unsigned dim, last_layer;
722 uint64_t va;
723 bool do_endian_swap = FALSE;
724
725 tile_split = tmp->surface.u.legacy.tile_split;
726 surflevel = tmp->surface.u.legacy.level;
727
728 /* Texturing with separate depth and stencil. */
729 if (tmp->db_compatible) {
730 switch (params->pipe_format) {
731 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
732 params->pipe_format = PIPE_FORMAT_Z32_FLOAT;
733 break;
734 case PIPE_FORMAT_X8Z24_UNORM:
735 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
736 /* Z24 is always stored like this for DB
737 * compatibility.
738 */
739 params->pipe_format = PIPE_FORMAT_Z24X8_UNORM;
740 break;
741 case PIPE_FORMAT_X24S8_UINT:
742 case PIPE_FORMAT_S8X24_UINT:
743 case PIPE_FORMAT_X32_S8X24_UINT:
744 params->pipe_format = PIPE_FORMAT_S8_UINT;
745 tile_split = tmp->surface.u.legacy.stencil_tile_split;
746 surflevel = tmp->surface.u.legacy.stencil_level;
747 break;
748 default:;
749 }
750 }
751
752 if (R600_BIG_ENDIAN)
753 do_endian_swap = !tmp->db_compatible;
754
755 format = r600_translate_texformat(rctx->b.b.screen, params->pipe_format,
756 params->swizzle,
757 &word4, &yuv_format, do_endian_swap);
758 assert(format != ~0);
759 if (format == ~0) {
760 return -1;
761 }
762
763 endian = r600_colorformat_endian_swap(format, do_endian_swap);
764
765 base_level = 0;
766 first_level = params->first_level;
767 last_level = params->last_level;
768 width = params->width0;
769 height = params->height0;
770 depth = texture->depth0;
771
772 if (params->force_level) {
773 base_level = params->force_level;
774 first_level = 0;
775 last_level = 0;
776 width = u_minify(width, params->force_level);
777 height = u_minify(height, params->force_level);
778 depth = u_minify(depth, params->force_level);
779 }
780
781 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(params->pipe_format);
782 non_disp_tiling = tmp->non_disp_tiling;
783
784 switch (surflevel[base_level].mode) {
785 default:
786 case RADEON_SURF_MODE_LINEAR_ALIGNED:
787 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
788 break;
789 case RADEON_SURF_MODE_2D:
790 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
791 break;
792 case RADEON_SURF_MODE_1D:
793 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
794 break;
795 }
796 macro_aspect = tmp->surface.u.legacy.mtilea;
797 bankw = tmp->surface.u.legacy.bankw;
798 bankh = tmp->surface.u.legacy.bankh;
799 tile_split = eg_tile_split(tile_split);
800 macro_aspect = eg_macro_tile_aspect(macro_aspect);
801 bankw = eg_bank_wh(bankw);
802 bankh = eg_bank_wh(bankh);
803 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
804
805 /* 128 bit formats require tile type = 1 */
806 if (rscreen->b.chip_class == CAYMAN) {
807 if (util_format_get_blocksize(params->pipe_format) >= 16)
808 non_disp_tiling = 1;
809 }
810 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
811
812 if (params->target == PIPE_TEXTURE_1D_ARRAY) {
813 height = 1;
814 depth = texture->array_size;
815 } else if (params->target == PIPE_TEXTURE_2D_ARRAY) {
816 depth = texture->array_size;
817 } else if (params->target == PIPE_TEXTURE_CUBE_ARRAY)
818 depth = texture->array_size / 6;
819
820 va = tmp->resource.gpu_address;
821
822 /* array type views and views into array types need to use layer offset */
823 dim = r600_tex_dim(tmp, params->target, texture->nr_samples);
824 tex_resource_words[0] = (S_030000_DIM(dim) |
825 S_030000_PITCH((pitch / 8) - 1) |
826 S_030000_TEX_WIDTH(width - 1));
827 if (rscreen->b.chip_class == CAYMAN)
828 tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
829 else
830 tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
831 tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
832 S_030004_TEX_DEPTH(depth - 1) |
833 S_030004_ARRAY_MODE(array_mode));
834 tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
835
836 *skip_mip_address_reloc = false;
837 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
838 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
839 if (tmp->is_depth) {
840 /* disable FMASK (0 = disabled) */
841 tex_resource_words[3] = 0;
842 *skip_mip_address_reloc = true;
843 } else {
844 /* FMASK should be in MIP_ADDRESS for multisample textures */
845 tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
846 }
847 } else if (last_level && texture->nr_samples <= 1) {
848 tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
849 } else {
850 tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
851 }
852
853 last_layer = params->last_layer;
854 if (params->target != texture->target && depth == 1) {
855 last_layer = params->first_layer;
856 }
857 tex_resource_words[4] = (word4 |
858 S_030010_ENDIAN_SWAP(endian));
859 tex_resource_words[5] = S_030014_BASE_ARRAY(params->first_layer) |
860 S_030014_LAST_ARRAY(last_layer);
861 tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
862
863 if (texture->nr_samples > 1) {
864 unsigned log_samples = util_logbase2(texture->nr_samples);
865 if (rscreen->b.chip_class == CAYMAN) {
866 tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
867 }
868 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
869 tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
870 tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
871 } else {
872 bool no_mip = first_level == last_level;
873
874 tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
875 tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
876 /* aniso max 16 samples */
877 tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
878 }
879
880 tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
881 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
882 S_03001C_BANK_WIDTH(bankw) |
883 S_03001C_BANK_HEIGHT(bankh) |
884 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
885 S_03001C_NUM_BANKS(nbanks) |
886 S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible);
887 return 0;
888 }
889
890 struct pipe_sampler_view *
891 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
892 struct pipe_resource *texture,
893 const struct pipe_sampler_view *state,
894 unsigned width0, unsigned height0,
895 unsigned force_level)
896 {
897 struct r600_context *rctx = (struct r600_context*)ctx;
898 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
899 struct r600_texture *tmp = (struct r600_texture*)texture;
900 struct eg_tex_res_params params;
901 int ret;
902
903 if (!view)
904 return NULL;
905
906 /* initialize base object */
907 view->base = *state;
908 view->base.texture = NULL;
909 pipe_reference(NULL, &texture->reference);
910 view->base.texture = texture;
911 view->base.reference.count = 1;
912 view->base.context = ctx;
913
914 if (state->target == PIPE_BUFFER)
915 return texture_buffer_sampler_view(rctx, view, width0, height0);
916
917 memset(&params, 0, sizeof(params));
918 params.pipe_format = state->format;
919 params.force_level = force_level;
920 params.width0 = width0;
921 params.height0 = height0;
922 params.first_level = state->u.tex.first_level;
923 params.last_level = state->u.tex.last_level;
924 params.first_layer = state->u.tex.first_layer;
925 params.last_layer = state->u.tex.last_layer;
926 params.target = state->target;
927 params.swizzle[0] = state->swizzle_r;
928 params.swizzle[1] = state->swizzle_g;
929 params.swizzle[2] = state->swizzle_b;
930 params.swizzle[3] = state->swizzle_a;
931
932 ret = evergreen_fill_tex_resource_words(rctx, texture, &params,
933 &view->skip_mip_address_reloc,
934 view->tex_resource_words);
935 if (ret != 0) {
936 FREE(view);
937 return NULL;
938 }
939
940 if (state->format == PIPE_FORMAT_X24S8_UINT ||
941 state->format == PIPE_FORMAT_S8X24_UINT ||
942 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
943 state->format == PIPE_FORMAT_S8_UINT)
944 view->is_stencil_sampler = true;
945
946 view->tex_resource = &tmp->resource;
947
948 return &view->base;
949 }
950
951 static struct pipe_sampler_view *
952 evergreen_create_sampler_view(struct pipe_context *ctx,
953 struct pipe_resource *tex,
954 const struct pipe_sampler_view *state)
955 {
956 return evergreen_create_sampler_view_custom(ctx, tex, state,
957 tex->width0, tex->height0, 0);
958 }
959
960 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
961 {
962 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
963 struct r600_config_state *a = (struct r600_config_state*)atom;
964
965 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
966 if (a->dyn_gpr_enabled) {
967 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
968 radeon_emit(cs, 0);
969 radeon_emit(cs, 0);
970 } else {
971 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
972 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
973 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
974 }
975 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
976 if (a->dyn_gpr_enabled) {
977 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
978 S_028838_PS_GPRS(0x1e) |
979 S_028838_VS_GPRS(0x1e) |
980 S_028838_GS_GPRS(0x1e) |
981 S_028838_ES_GPRS(0x1e) |
982 S_028838_HS_GPRS(0x1e) |
983 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
984 }
985 }
986
987 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
988 {
989 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
990 struct pipe_clip_state *state = &rctx->clip_state.state;
991
992 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
993 radeon_emit_array(cs, (unsigned*)state, 6*4);
994 }
995
996 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
997 const struct pipe_poly_stipple *state)
998 {
999 }
1000
1001 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1002 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1003 uint32_t *tl, uint32_t *br)
1004 {
1005 struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
1006
1007 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
1008
1009 *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
1010 *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
1011 }
1012
1013 struct r600_tex_color_info {
1014 unsigned info;
1015 unsigned view;
1016 unsigned dim;
1017 unsigned pitch;
1018 unsigned slice;
1019 unsigned attrib;
1020 unsigned ntype;
1021 unsigned fmask;
1022 unsigned fmask_slice;
1023 uint64_t offset;
1024 boolean export_16bpc;
1025 };
1026
1027 static void evergreen_set_color_surface_buffer(struct r600_context *rctx,
1028 struct r600_resource *res,
1029 enum pipe_format pformat,
1030 unsigned first_element,
1031 unsigned last_element,
1032 struct r600_tex_color_info *color)
1033 {
1034 unsigned format, swap, ntype, endian;
1035 const struct util_format_description *desc;
1036 unsigned block_size = util_format_get_blocksize(res->b.b.format);
1037 unsigned pitch_alignment =
1038 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
1039 unsigned pitch = align(res->b.b.width0, pitch_alignment);
1040 int i;
1041 unsigned width_elements;
1042
1043 width_elements = last_element - first_element + 1;
1044
1045 format = r600_translate_colorformat(rctx->b.chip_class, pformat, FALSE);
1046 swap = r600_translate_colorswap(pformat, FALSE);
1047
1048 endian = r600_colorformat_endian_swap(format, FALSE);
1049
1050 desc = util_format_description(pformat);
1051 for (i = 0; i < 4; i++) {
1052 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1053 break;
1054 }
1055 }
1056 ntype = V_028C70_NUMBER_UNORM;
1057 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1058 ntype = V_028C70_NUMBER_SRGB;
1059 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1060 if (desc->channel[i].normalized)
1061 ntype = V_028C70_NUMBER_SNORM;
1062 else if (desc->channel[i].pure_integer)
1063 ntype = V_028C70_NUMBER_SINT;
1064 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1065 if (desc->channel[i].normalized)
1066 ntype = V_028C70_NUMBER_UNORM;
1067 else if (desc->channel[i].pure_integer)
1068 ntype = V_028C70_NUMBER_UINT;
1069 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1070 ntype = V_028C70_NUMBER_FLOAT;
1071 }
1072
1073 pitch = (pitch / 8) - 1;
1074 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1075
1076 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1077 color->info |= S_028C70_FORMAT(format) |
1078 S_028C70_COMP_SWAP(swap) |
1079 S_028C70_BLEND_CLAMP(0) |
1080 S_028C70_BLEND_BYPASS(1) |
1081 S_028C70_NUMBER_TYPE(ntype) |
1082 S_028C70_ENDIAN(endian);
1083 color->attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1084 color->ntype = ntype;
1085 color->export_16bpc = false;
1086 color->dim = width_elements - 1;
1087 color->slice = 0; /* (width_elements / 64) - 1;*/
1088 color->view = 0;
1089 color->offset = (res->gpu_address + first_element) >> 8;
1090
1091 color->fmask = color->offset;
1092 color->fmask_slice = 0;
1093 }
1094
1095 static void evergreen_set_color_surface_common(struct r600_context *rctx,
1096 struct r600_texture *rtex,
1097 unsigned level,
1098 unsigned first_layer,
1099 unsigned last_layer,
1100 enum pipe_format pformat,
1101 struct r600_tex_color_info *color)
1102 {
1103 struct r600_screen *rscreen = rctx->screen;
1104 unsigned pitch, slice;
1105 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1106 unsigned format, swap, ntype, endian;
1107 const struct util_format_description *desc;
1108 bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
1109 int i;
1110
1111 color->offset = rtex->surface.u.legacy.level[level].offset;
1112 color->view = S_028C6C_SLICE_START(first_layer) |
1113 S_028C6C_SLICE_MAX(last_layer);
1114
1115 color->offset += rtex->resource.gpu_address;
1116 color->offset >>= 8;
1117
1118 color->dim = 0;
1119 pitch = (rtex->surface.u.legacy.level[level].nblk_x) / 8 - 1;
1120 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1121 if (slice) {
1122 slice = slice - 1;
1123 }
1124
1125 color->info = 0;
1126 switch (rtex->surface.u.legacy.level[level].mode) {
1127 default:
1128 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1129 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1130 non_disp_tiling = 1;
1131 break;
1132 case RADEON_SURF_MODE_1D:
1133 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1134 non_disp_tiling = rtex->non_disp_tiling;
1135 break;
1136 case RADEON_SURF_MODE_2D:
1137 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1138 non_disp_tiling = rtex->non_disp_tiling;
1139 break;
1140 }
1141 tile_split = rtex->surface.u.legacy.tile_split;
1142 macro_aspect = rtex->surface.u.legacy.mtilea;
1143 bankw = rtex->surface.u.legacy.bankw;
1144 bankh = rtex->surface.u.legacy.bankh;
1145 if (rtex->fmask.size)
1146 fmask_bankh = rtex->fmask.bank_height;
1147 else
1148 fmask_bankh = rtex->surface.u.legacy.bankh;
1149 tile_split = eg_tile_split(tile_split);
1150 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1151 bankw = eg_bank_wh(bankw);
1152 bankh = eg_bank_wh(bankh);
1153 fmask_bankh = eg_bank_wh(fmask_bankh);
1154
1155 if (rscreen->b.chip_class == CAYMAN) {
1156 if (util_format_get_blocksize(pformat) >= 16)
1157 non_disp_tiling = 1;
1158 }
1159 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1160 desc = util_format_description(pformat);
1161 for (i = 0; i < 4; i++) {
1162 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1163 break;
1164 }
1165 }
1166 color->attrib = S_028C74_TILE_SPLIT(tile_split)|
1167 S_028C74_NUM_BANKS(nbanks) |
1168 S_028C74_BANK_WIDTH(bankw) |
1169 S_028C74_BANK_HEIGHT(bankh) |
1170 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1171 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1172 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1173
1174 if (rctx->b.chip_class == CAYMAN) {
1175 color->attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1176 PIPE_SWIZZLE_1);
1177
1178 if (rtex->resource.b.b.nr_samples > 1) {
1179 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1180 color->attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1181 S_028C74_NUM_FRAGMENTS(log_samples);
1182 }
1183 }
1184
1185 ntype = V_028C70_NUMBER_UNORM;
1186 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1187 ntype = V_028C70_NUMBER_SRGB;
1188 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1189 if (desc->channel[i].normalized)
1190 ntype = V_028C70_NUMBER_SNORM;
1191 else if (desc->channel[i].pure_integer)
1192 ntype = V_028C70_NUMBER_SINT;
1193 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1194 if (desc->channel[i].normalized)
1195 ntype = V_028C70_NUMBER_UNORM;
1196 else if (desc->channel[i].pure_integer)
1197 ntype = V_028C70_NUMBER_UINT;
1198 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1199 ntype = V_028C70_NUMBER_FLOAT;
1200 }
1201
1202 if (R600_BIG_ENDIAN)
1203 do_endian_swap = !rtex->db_compatible;
1204
1205 format = r600_translate_colorformat(rctx->b.chip_class, pformat, do_endian_swap);
1206 assert(format != ~0);
1207 swap = r600_translate_colorswap(pformat, do_endian_swap);
1208 assert(swap != ~0);
1209
1210 endian = r600_colorformat_endian_swap(format, do_endian_swap);
1211
1212 /* blend clamp should be set for all NORM/SRGB types */
1213 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1214 ntype == V_028C70_NUMBER_SRGB)
1215 blend_clamp = 1;
1216
1217 /* set blend bypass according to docs if SINT/UINT or
1218 8/24 COLOR variants */
1219 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1220 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1221 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1222 blend_clamp = 0;
1223 blend_bypass = 1;
1224 }
1225
1226 color->ntype = ntype;
1227 color->info |= S_028C70_FORMAT(format) |
1228 S_028C70_COMP_SWAP(swap) |
1229 S_028C70_BLEND_CLAMP(blend_clamp) |
1230 S_028C70_BLEND_BYPASS(blend_bypass) |
1231 S_028C70_SIMPLE_FLOAT(1) |
1232 S_028C70_NUMBER_TYPE(ntype) |
1233 S_028C70_ENDIAN(endian);
1234
1235 if (rtex->fmask.size) {
1236 color->info |= S_028C70_COMPRESSION(1);
1237 }
1238
1239 /* EXPORT_NORM is an optimzation that can be enabled for better
1240 * performance in certain cases.
1241 * EXPORT_NORM can be enabled if:
1242 * - 11-bit or smaller UNORM/SNORM/SRGB
1243 * - 16-bit or smaller FLOAT
1244 */
1245 color->export_16bpc = false;
1246 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1247 ((desc->channel[i].size < 12 &&
1248 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1249 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1250 (desc->channel[i].size < 17 &&
1251 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1252 color->info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1253 color->export_16bpc = true;
1254 }
1255
1256 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1257 color->slice = S_028C68_SLICE_TILE_MAX(slice);
1258
1259 if (rtex->fmask.size) {
1260 color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8;
1261 color->fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1262 } else {
1263 color->fmask = color->offset;
1264 color->fmask_slice = S_028C88_TILE_MAX(slice);
1265 }
1266 }
1267
1268 /**
1269 * This function intializes the CB* register values for RATs. It is meant
1270 * to be used for 1D aligned buffers that do not have an associated
1271 * radeon_surf.
1272 */
1273 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1274 struct r600_surface *surf)
1275 {
1276 struct pipe_resource *pipe_buffer = surf->base.texture;
1277 struct r600_tex_color_info color;
1278
1279 evergreen_set_color_surface_buffer(rctx, (struct r600_resource *)surf->base.texture,
1280 surf->base.format, 0, pipe_buffer->width0,
1281 &color);
1282
1283 surf->cb_color_base = color.offset;
1284 surf->cb_color_dim = color.dim;
1285 surf->cb_color_info = color.info | S_028C70_RAT(1);
1286 surf->cb_color_pitch = color.pitch;
1287 surf->cb_color_slice = color.slice;
1288 surf->cb_color_view = color.view;
1289 surf->cb_color_attrib = color.attrib;
1290 surf->cb_color_fmask = color.fmask;
1291 surf->cb_color_fmask_slice = color.fmask_slice;
1292
1293 surf->cb_color_view = 0;
1294
1295 /* Set the buffer range the GPU will have access to: */
1296 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
1297 0, pipe_buffer->width0);
1298 }
1299
1300
1301 void evergreen_init_color_surface(struct r600_context *rctx,
1302 struct r600_surface *surf)
1303 {
1304 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1305 unsigned level = surf->base.u.tex.level;
1306 struct r600_tex_color_info color;
1307
1308 evergreen_set_color_surface_common(rctx, rtex, level,
1309 surf->base.u.tex.first_layer,
1310 surf->base.u.tex.last_layer,
1311 surf->base.format,
1312 &color);
1313
1314 surf->alphatest_bypass = color.ntype == V_028C70_NUMBER_UINT ||
1315 color.ntype == V_028C70_NUMBER_SINT;
1316 surf->export_16bpc = color.export_16bpc;
1317
1318 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1319 surf->cb_color_base = color.offset;
1320 surf->cb_color_dim = color.dim;
1321 surf->cb_color_info = color.info;
1322 surf->cb_color_pitch = color.pitch;
1323 surf->cb_color_slice = color.slice;
1324 surf->cb_color_view = color.view;
1325 surf->cb_color_attrib = color.attrib;
1326 surf->cb_color_fmask = color.fmask;
1327 surf->cb_color_fmask_slice = color.fmask_slice;
1328
1329 surf->color_initialized = true;
1330 }
1331
1332 static void evergreen_init_depth_surface(struct r600_context *rctx,
1333 struct r600_surface *surf)
1334 {
1335 struct r600_screen *rscreen = rctx->screen;
1336 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1337 unsigned level = surf->base.u.tex.level;
1338 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
1339 uint64_t offset;
1340 unsigned format, array_mode;
1341 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1342
1343
1344 format = r600_translate_dbformat(surf->base.format);
1345 assert(format != ~0);
1346
1347 offset = rtex->resource.gpu_address;
1348 offset += rtex->surface.u.legacy.level[level].offset;
1349
1350 switch (rtex->surface.u.legacy.level[level].mode) {
1351 case RADEON_SURF_MODE_2D:
1352 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1353 break;
1354 case RADEON_SURF_MODE_1D:
1355 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1356 default:
1357 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1358 break;
1359 }
1360 tile_split = rtex->surface.u.legacy.tile_split;
1361 macro_aspect = rtex->surface.u.legacy.mtilea;
1362 bankw = rtex->surface.u.legacy.bankw;
1363 bankh = rtex->surface.u.legacy.bankh;
1364 tile_split = eg_tile_split(tile_split);
1365 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1366 bankw = eg_bank_wh(bankw);
1367 bankh = eg_bank_wh(bankh);
1368 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1369 offset >>= 8;
1370
1371 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1372 S_028040_FORMAT(format) |
1373 S_028040_TILE_SPLIT(tile_split)|
1374 S_028040_NUM_BANKS(nbanks) |
1375 S_028040_BANK_WIDTH(bankw) |
1376 S_028040_BANK_HEIGHT(bankh) |
1377 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1378 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1379 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1380 }
1381
1382 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1383
1384 surf->db_depth_base = offset;
1385 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1386 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1387 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1388 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1389 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1390 levelinfo->nblk_y / 64 - 1);
1391
1392 if (rtex->surface.has_stencil) {
1393 uint64_t stencil_offset;
1394 unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split;
1395
1396 stile_split = eg_tile_split(stile_split);
1397
1398 stencil_offset = rtex->surface.u.legacy.stencil_level[level].offset;
1399 stencil_offset += rtex->resource.gpu_address;
1400
1401 surf->db_stencil_base = stencil_offset >> 8;
1402 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1403 S_028044_TILE_SPLIT(stile_split);
1404 } else {
1405 surf->db_stencil_base = offset;
1406 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1407 * Older kernels are out of luck. */
1408 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1409 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1410 S_028044_FORMAT(V_028044_STENCIL_8);
1411 }
1412
1413 if (r600_htile_enabled(rtex, level)) {
1414 uint64_t va = rtex->resource.gpu_address + rtex->htile_offset;
1415 surf->db_htile_data_base = va >> 8;
1416 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1417 S_028ABC_HTILE_HEIGHT(1) |
1418 S_028ABC_FULL_CACHE(1);
1419 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1420 surf->db_preload_control = 0;
1421 }
1422
1423 surf->depth_initialized = true;
1424 }
1425
1426 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1427 const struct pipe_framebuffer_state *state)
1428 {
1429 struct r600_context *rctx = (struct r600_context *)ctx;
1430 struct r600_surface *surf;
1431 struct r600_texture *rtex;
1432 uint32_t i, log_samples;
1433
1434 /* Flush TC when changing the framebuffer state, because the only
1435 * client not using TC that can change textures is the framebuffer.
1436 * Other places don't typically have to flush TC.
1437 */
1438 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1439 R600_CONTEXT_FLUSH_AND_INV |
1440 R600_CONTEXT_FLUSH_AND_INV_CB |
1441 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1442 R600_CONTEXT_FLUSH_AND_INV_DB |
1443 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1444 R600_CONTEXT_INV_TEX_CACHE;
1445
1446 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1447
1448 /* Colorbuffers. */
1449 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1450 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1451 util_format_is_pure_integer(state->cbufs[0]->format);
1452 rctx->framebuffer.compressed_cb_mask = 0;
1453 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1454
1455 for (i = 0; i < state->nr_cbufs; i++) {
1456 surf = (struct r600_surface*)state->cbufs[i];
1457 if (!surf)
1458 continue;
1459
1460 rtex = (struct r600_texture*)surf->base.texture;
1461
1462 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1463
1464 if (!surf->color_initialized) {
1465 evergreen_init_color_surface(rctx, surf);
1466 }
1467
1468 if (!surf->export_16bpc) {
1469 rctx->framebuffer.export_16bpc = false;
1470 }
1471
1472 if (rtex->fmask.size) {
1473 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1474 }
1475 }
1476
1477 /* Update alpha-test state dependencies.
1478 * Alpha-test is done on the first colorbuffer only. */
1479 if (state->nr_cbufs) {
1480 bool alphatest_bypass = false;
1481 bool export_16bpc = true;
1482
1483 surf = (struct r600_surface*)state->cbufs[0];
1484 if (surf) {
1485 alphatest_bypass = surf->alphatest_bypass;
1486 export_16bpc = surf->export_16bpc;
1487 }
1488
1489 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1490 rctx->alphatest_state.bypass = alphatest_bypass;
1491 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1492 }
1493 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1494 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1495 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1496 }
1497 }
1498
1499 /* ZS buffer. */
1500 if (state->zsbuf) {
1501 surf = (struct r600_surface*)state->zsbuf;
1502
1503 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1504
1505 if (!surf->depth_initialized) {
1506 evergreen_init_depth_surface(rctx, surf);
1507 }
1508
1509 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1510 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1511 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1512 }
1513
1514 if (rctx->db_state.rsurf != surf) {
1515 rctx->db_state.rsurf = surf;
1516 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1517 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1518 }
1519 } else if (rctx->db_state.rsurf) {
1520 rctx->db_state.rsurf = NULL;
1521 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1522 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1523 }
1524
1525 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1526 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1527 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1528 }
1529
1530 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1531 rctx->alphatest_state.bypass = false;
1532 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1533 }
1534
1535 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1536 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1537 if ((rctx->b.chip_class == CAYMAN ||
1538 rctx->b.family == CHIP_RV770) &&
1539 rctx->db_misc_state.log_samples != log_samples) {
1540 rctx->db_misc_state.log_samples = log_samples;
1541 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1542 }
1543
1544
1545 /* Calculate the CS size. */
1546 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1547
1548 /* MSAA. */
1549 if (rctx->b.chip_class == EVERGREEN)
1550 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1551 else
1552 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1553
1554 /* Colorbuffers. */
1555 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1556 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1557 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1558
1559 /* ZS buffer. */
1560 if (state->zsbuf) {
1561 rctx->framebuffer.atom.num_dw += 24;
1562 rctx->framebuffer.atom.num_dw += 2;
1563 } else if (rctx->screen->b.info.drm_minor >= 18) {
1564 rctx->framebuffer.atom.num_dw += 4;
1565 }
1566
1567 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1568
1569 r600_set_sample_locations_constant_buffer(rctx);
1570 rctx->framebuffer.do_update_surf_dirtiness = true;
1571 }
1572
1573 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1574 {
1575 struct r600_context *rctx = (struct r600_context *)ctx;
1576
1577 if (rctx->ps_iter_samples == min_samples)
1578 return;
1579
1580 rctx->ps_iter_samples = min_samples;
1581 if (rctx->framebuffer.nr_samples > 1) {
1582 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1583 }
1584 }
1585
1586 /* 8xMSAA */
1587 static uint32_t sample_locs_8x[] = {
1588 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1589 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1590 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1591 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1592 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1593 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1594 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1595 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1596 };
1597 static unsigned max_dist_8x = 7;
1598
1599 static void evergreen_get_sample_position(struct pipe_context *ctx,
1600 unsigned sample_count,
1601 unsigned sample_index,
1602 float *out_value)
1603 {
1604 int offset, index;
1605 struct {
1606 int idx:4;
1607 } val;
1608 switch (sample_count) {
1609 case 1:
1610 default:
1611 out_value[0] = out_value[1] = 0.5;
1612 break;
1613 case 2:
1614 offset = 4 * (sample_index * 2);
1615 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1616 out_value[0] = (float)(val.idx + 8) / 16.0f;
1617 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1618 out_value[1] = (float)(val.idx + 8) / 16.0f;
1619 break;
1620 case 4:
1621 offset = 4 * (sample_index * 2);
1622 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1623 out_value[0] = (float)(val.idx + 8) / 16.0f;
1624 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1625 out_value[1] = (float)(val.idx + 8) / 16.0f;
1626 break;
1627 case 8:
1628 offset = 4 * (sample_index % 4 * 2);
1629 index = (sample_index / 4);
1630 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1631 out_value[0] = (float)(val.idx + 8) / 16.0f;
1632 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1633 out_value[1] = (float)(val.idx + 8) / 16.0f;
1634 break;
1635 }
1636 }
1637
1638 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1639 {
1640
1641 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1642 unsigned max_dist = 0;
1643
1644 switch (nr_samples) {
1645 default:
1646 nr_samples = 0;
1647 break;
1648 case 2:
1649 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x));
1650 radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x));
1651 max_dist = eg_max_dist_2x;
1652 break;
1653 case 4:
1654 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x));
1655 radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x));
1656 max_dist = eg_max_dist_4x;
1657 break;
1658 case 8:
1659 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x));
1660 radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x));
1661 max_dist = max_dist_8x;
1662 break;
1663 }
1664
1665 if (nr_samples > 1) {
1666 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1667 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1668 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1669 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1670 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1671 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1672 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1673 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1674 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1675 } else {
1676 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1677 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1678 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1679 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1680 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1681 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1682 }
1683 }
1684
1685 static void evergreen_emit_image_state(struct r600_context *rctx, struct r600_atom *atom,
1686 int immed_id_base, int res_id_base, int offset)
1687 {
1688 struct r600_image_state *state = (struct r600_image_state *)atom;
1689 struct pipe_framebuffer_state *fb_state = &rctx->framebuffer.state;
1690 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1691 struct r600_texture *rtex;
1692 struct r600_resource *resource;
1693 uint32_t pkt_flags = 0;
1694 int i;
1695
1696 for (i = 0; i < R600_MAX_IMAGES; i++) {
1697 struct r600_image_view *image = &state->views[i];
1698 unsigned reloc, immed_reloc;
1699 int idx = i + offset;
1700
1701 idx += fb_state->nr_cbufs + (rctx->dual_src_blend ? 1 : 0);
1702 if (!image->base.resource)
1703 continue;
1704
1705 resource = (struct r600_resource *)image->base.resource;
1706 if (resource->b.b.target != PIPE_BUFFER)
1707 rtex = (struct r600_texture *)image->base.resource;
1708 else
1709 rtex = NULL;
1710
1711 reloc = radeon_add_to_buffer_list(&rctx->b,
1712 &rctx->b.gfx,
1713 resource,
1714 RADEON_USAGE_READWRITE,
1715 RADEON_PRIO_SHADER_RW_BUFFER);
1716
1717 immed_reloc = radeon_add_to_buffer_list(&rctx->b,
1718 &rctx->b.gfx,
1719 resource->immed_buffer,
1720 RADEON_USAGE_READWRITE,
1721 RADEON_PRIO_SHADER_RW_BUFFER);
1722
1723 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13);
1724
1725 radeon_emit(cs, image->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1726 radeon_emit(cs, image->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1727 radeon_emit(cs, image->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1728 radeon_emit(cs, image->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1729 radeon_emit(cs, image->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1730 radeon_emit(cs, image->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1731 radeon_emit(cs, image->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1732 radeon_emit(cs, rtex ? rtex->cmask.base_address_reg : image->cb_color_base); /* R_028C7C_CB_COLOR0_CMASK */
1733 radeon_emit(cs, rtex ? rtex->cmask.slice_tile_max : 0); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1734 radeon_emit(cs, image->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1735 radeon_emit(cs, image->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1736 radeon_emit(cs, rtex ? rtex->color_clear_value[0] : 0); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1737 radeon_emit(cs, rtex ? rtex->color_clear_value[1] : 0); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1738
1739 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1740 radeon_emit(cs, reloc);
1741
1742 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1743 radeon_emit(cs, reloc);
1744
1745 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1746 radeon_emit(cs, reloc);
1747
1748 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1749 radeon_emit(cs, reloc);
1750
1751 radeon_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1752 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /**/
1753 radeon_emit(cs, immed_reloc);
1754
1755 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1756 radeon_emit(cs, (immed_id_base + i + offset) * 8);
1757 radeon_emit_array(cs, image->immed_resource_words, 8);
1758
1759 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1760 radeon_emit(cs, immed_reloc);
1761
1762 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1763 radeon_emit(cs, (res_id_base + i + offset) * 8);
1764 radeon_emit_array(cs, image->resource_words, 8);
1765
1766 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1767 radeon_emit(cs, reloc);
1768
1769 if (!image->skip_mip_address_reloc) {
1770 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1771 radeon_emit(cs, reloc);
1772 }
1773 }
1774 }
1775
1776 static void evergreen_emit_fragment_image_state(struct r600_context *rctx, struct r600_atom *atom)
1777 {
1778 evergreen_emit_image_state(rctx, atom,
1779 R600_IMAGE_IMMED_RESOURCE_OFFSET,
1780 R600_IMAGE_REAL_RESOURCE_OFFSET, 0);
1781 }
1782
1783 static void evergreen_emit_fragment_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1784 {
1785 int offset = util_bitcount(rctx->fragment_images.enabled_mask);
1786 evergreen_emit_image_state(rctx, atom,
1787 R600_IMAGE_IMMED_RESOURCE_OFFSET,
1788 R600_IMAGE_REAL_RESOURCE_OFFSET, offset);
1789 }
1790
1791 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1792 {
1793 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1794 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1795 unsigned nr_cbufs = state->nr_cbufs;
1796 unsigned i, tl, br;
1797 struct r600_texture *tex = NULL;
1798 struct r600_surface *cb = NULL;
1799
1800 /* XXX support more colorbuffers once we need them */
1801 assert(nr_cbufs <= 8);
1802 if (nr_cbufs > 8)
1803 nr_cbufs = 8;
1804
1805 /* Colorbuffers. */
1806 for (i = 0; i < nr_cbufs; i++) {
1807 unsigned reloc, cmask_reloc;
1808
1809 cb = (struct r600_surface*)state->cbufs[i];
1810 if (!cb) {
1811 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1812 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1813 continue;
1814 }
1815
1816 tex = (struct r600_texture *)cb->base.texture;
1817 reloc = radeon_add_to_buffer_list(&rctx->b,
1818 &rctx->b.gfx,
1819 (struct r600_resource*)cb->base.texture,
1820 RADEON_USAGE_READWRITE,
1821 tex->resource.b.b.nr_samples > 1 ?
1822 RADEON_PRIO_COLOR_BUFFER_MSAA :
1823 RADEON_PRIO_COLOR_BUFFER);
1824
1825 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1826 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1827 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1828 RADEON_PRIO_CMASK);
1829 } else {
1830 cmask_reloc = reloc;
1831 }
1832
1833 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1834 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1835 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1836 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1837 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1838 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1839 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1840 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1841 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1842 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1843 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1844 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1845 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1846 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1847
1848 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1849 radeon_emit(cs, reloc);
1850
1851 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1852 radeon_emit(cs, reloc);
1853
1854 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1855 radeon_emit(cs, cmask_reloc);
1856
1857 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1858 radeon_emit(cs, reloc);
1859 }
1860 /* set CB_COLOR1_INFO for possible dual-src blending */
1861 if (rctx->framebuffer.dual_src_blend && i == 1 && state->cbufs[0]) {
1862 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1863 cb->cb_color_info | tex->cb_color_info);
1864 i++;
1865 }
1866 i += util_bitcount(rctx->fragment_images.enabled_mask);
1867 i += util_bitcount(rctx->fragment_buffers.enabled_mask);
1868 for (; i < 8 ; i++)
1869 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1870 for (; i < 12; i++)
1871 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1872
1873 /* ZS buffer. */
1874 if (state->zsbuf) {
1875 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1876 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1877 &rctx->b.gfx,
1878 (struct r600_resource*)state->zsbuf->texture,
1879 RADEON_USAGE_READWRITE,
1880 zb->base.texture->nr_samples > 1 ?
1881 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1882 RADEON_PRIO_DEPTH_BUFFER);
1883
1884 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1885
1886 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1887 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1888 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1889 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1890 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1891 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1892 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1893 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1894 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1895
1896 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1897 radeon_emit(cs, reloc);
1898
1899 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1900 radeon_emit(cs, reloc);
1901
1902 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1903 radeon_emit(cs, reloc);
1904
1905 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1906 radeon_emit(cs, reloc);
1907 } else if (rctx->screen->b.info.drm_minor >= 18) {
1908 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1909 * Older kernels are out of luck. */
1910 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1911 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1912 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1913 }
1914
1915 /* Framebuffer dimensions. */
1916 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1917
1918 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1919 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1920 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1921
1922 if (rctx->b.chip_class == EVERGREEN) {
1923 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1924 } else {
1925 unsigned sc_mode_cntl_1 =
1926 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1927 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1928
1929 if (rctx->framebuffer.nr_samples > 1)
1930 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1931 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples,
1932 rctx->ps_iter_samples, 0, sc_mode_cntl_1);
1933 }
1934 }
1935
1936 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1937 {
1938 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1939 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1940 float offset_units = state->offset_units;
1941 float offset_scale = state->offset_scale;
1942 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
1943
1944 if (!state->offset_units_unscaled) {
1945 switch (state->zs_format) {
1946 case PIPE_FORMAT_Z24X8_UNORM:
1947 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1948 case PIPE_FORMAT_X8Z24_UNORM:
1949 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1950 offset_units *= 2.0f;
1951 pa_su_poly_offset_db_fmt_cntl =
1952 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1953 break;
1954 case PIPE_FORMAT_Z16_UNORM:
1955 offset_units *= 4.0f;
1956 pa_su_poly_offset_db_fmt_cntl =
1957 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1958 break;
1959 default:
1960 pa_su_poly_offset_db_fmt_cntl =
1961 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1962 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1963 }
1964 }
1965
1966 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1967 radeon_emit(cs, fui(offset_scale));
1968 radeon_emit(cs, fui(offset_units));
1969 radeon_emit(cs, fui(offset_scale));
1970 radeon_emit(cs, fui(offset_units));
1971
1972 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1973 pa_su_poly_offset_db_fmt_cntl);
1974 }
1975
1976 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1977 {
1978 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1979 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1980 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1981 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1982 unsigned rat_colormask = ((1ULL << ((unsigned)(a->nr_image_rats + a->nr_buffer_rats) * 4)) - 1) << (a->nr_cbufs * 4);
1983 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1984 radeon_emit(cs, (a->blend_colormask & fb_colormask) | rat_colormask); /* R_028238_CB_TARGET_MASK */
1985 /* This must match the used export instructions exactly.
1986 * Other values may lead to undefined behavior and hangs.
1987 */
1988 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
1989 }
1990
1991 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1992 {
1993 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1994 struct r600_db_state *a = (struct r600_db_state*)atom;
1995
1996 if (a->rsurf && a->rsurf->db_htile_surface) {
1997 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1998 unsigned reloc_idx;
1999
2000 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2001 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
2002 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
2003 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
2004 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
2005 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
2006 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2007 radeon_emit(cs, reloc_idx);
2008 } else {
2009 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
2010 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
2011 }
2012 }
2013
2014 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2015 {
2016 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2017 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2018 unsigned db_render_control = 0;
2019 unsigned db_count_control = 0;
2020 unsigned db_render_override =
2021 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2022 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2023
2024 if (rctx->b.num_occlusion_queries > 0 &&
2025 !a->occlusion_queries_disabled) {
2026 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
2027 if (rctx->b.chip_class == CAYMAN) {
2028 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
2029 }
2030 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
2031 } else {
2032 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
2033 }
2034
2035 /* This is to fix a lockup when hyperz and alpha test are enabled at
2036 * the same time somehow GPU get confuse on which order to pick for
2037 * z test
2038 */
2039 if (rctx->alphatest_state.sx_alpha_test_control)
2040 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
2041
2042 if (a->flush_depthstencil_through_cb) {
2043 assert(a->copy_depth || a->copy_stencil);
2044
2045 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
2046 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
2047 S_028000_COPY_CENTROID(1) |
2048 S_028000_COPY_SAMPLE(a->copy_sample);
2049 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
2050 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
2051 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
2052 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2053 }
2054 if (a->htile_clear) {
2055 /* FIXME we might want to disable cliprect here */
2056 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
2057 }
2058
2059 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
2060 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
2061 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
2062 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2063 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2064 }
2065
2066 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
2067 struct r600_vertexbuf_state *state,
2068 unsigned resource_offset,
2069 unsigned pkt_flags)
2070 {
2071 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2072 uint32_t dirty_mask = state->dirty_mask;
2073
2074 while (dirty_mask) {
2075 struct pipe_vertex_buffer *vb;
2076 struct r600_resource *rbuffer;
2077 uint64_t va;
2078 unsigned buffer_index = u_bit_scan(&dirty_mask);
2079
2080 vb = &state->vb[buffer_index];
2081 rbuffer = (struct r600_resource*)vb->buffer.resource;
2082 assert(rbuffer);
2083
2084 va = rbuffer->gpu_address + vb->buffer_offset;
2085
2086 /* fetch resources start at index 992 */
2087 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2088 radeon_emit(cs, (resource_offset + buffer_index) * 8);
2089 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2090 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2091 radeon_emit(cs, /* RESOURCEi_WORD2 */
2092 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2093 S_030008_STRIDE(vb->stride) |
2094 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2095 radeon_emit(cs, /* RESOURCEi_WORD3 */
2096 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2097 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2098 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2099 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2100 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2101 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2102 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2103 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2104
2105 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2106 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2107 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
2108 }
2109 state->dirty_mask = 0;
2110 }
2111
2112 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2113 {
2114 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
2115 }
2116
2117 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2118 {
2119 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
2120 RADEON_CP_PACKET3_COMPUTE_MODE);
2121 }
2122
2123 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2124 struct r600_constbuf_state *state,
2125 unsigned buffer_id_base,
2126 unsigned reg_alu_constbuf_size,
2127 unsigned reg_alu_const_cache,
2128 unsigned pkt_flags)
2129 {
2130 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2131 uint32_t dirty_mask = state->dirty_mask;
2132
2133 while (dirty_mask) {
2134 struct pipe_constant_buffer *cb;
2135 struct r600_resource *rbuffer;
2136 uint64_t va;
2137 unsigned buffer_index = ffs(dirty_mask) - 1;
2138 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
2139
2140 cb = &state->cb[buffer_index];
2141 rbuffer = (struct r600_resource*)cb->buffer;
2142 assert(rbuffer);
2143
2144 va = rbuffer->gpu_address + cb->buffer_offset;
2145
2146 if (!gs_ring_buffer) {
2147 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
2148 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
2149 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
2150 pkt_flags);
2151 }
2152
2153 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2154 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2155 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2156
2157 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2158 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
2159 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2160 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2161 radeon_emit(cs, /* RESOURCEi_WORD2 */
2162 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
2163 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
2164 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
2165 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
2166 radeon_emit(cs, /* RESOURCEi_WORD3 */
2167 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
2168 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2169 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2170 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2171 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2172 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2173 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2174 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2175 radeon_emit(cs, /* RESOURCEi_WORD7 */
2176 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
2177
2178 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2179 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2180 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2181
2182 dirty_mask &= ~(1 << buffer_index);
2183 }
2184 state->dirty_mask = 0;
2185 }
2186
2187 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
2188 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2189 {
2190 if (rctx->vs_shader->current->shader.vs_as_ls) {
2191 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2192 EG_FETCH_CONSTANTS_OFFSET_LS,
2193 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2194 R_028F40_ALU_CONST_CACHE_LS_0,
2195 0 /* PKT3 flags */);
2196 } else {
2197 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2198 EG_FETCH_CONSTANTS_OFFSET_VS,
2199 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2200 R_028980_ALU_CONST_CACHE_VS_0,
2201 0 /* PKT3 flags */);
2202 }
2203 }
2204
2205 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2206 {
2207 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
2208 EG_FETCH_CONSTANTS_OFFSET_GS,
2209 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2210 R_0289C0_ALU_CONST_CACHE_GS_0,
2211 0 /* PKT3 flags */);
2212 }
2213
2214 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2215 {
2216 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
2217 EG_FETCH_CONSTANTS_OFFSET_PS,
2218 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2219 R_028940_ALU_CONST_CACHE_PS_0,
2220 0 /* PKT3 flags */);
2221 }
2222
2223 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2224 {
2225 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
2226 EG_FETCH_CONSTANTS_OFFSET_CS,
2227 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2228 R_028F40_ALU_CONST_CACHE_LS_0,
2229 RADEON_CP_PACKET3_COMPUTE_MODE);
2230 }
2231
2232 /* tes constants can be emitted to VS or ES - which are common */
2233 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2234 {
2235 if (!rctx->tes_shader)
2236 return;
2237 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2238 EG_FETCH_CONSTANTS_OFFSET_VS,
2239 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2240 R_028980_ALU_CONST_CACHE_VS_0,
2241 0);
2242 }
2243
2244 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2245 {
2246 if (!rctx->tes_shader)
2247 return;
2248 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2249 EG_FETCH_CONSTANTS_OFFSET_HS,
2250 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
2251 R_028F00_ALU_CONST_CACHE_HS_0,
2252 0);
2253 }
2254
2255 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2256 struct r600_samplerview_state *state,
2257 unsigned resource_id_base, unsigned pkt_flags)
2258 {
2259 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2260 uint32_t dirty_mask = state->dirty_mask;
2261
2262 while (dirty_mask) {
2263 struct r600_pipe_sampler_view *rview;
2264 unsigned resource_index = u_bit_scan(&dirty_mask);
2265 unsigned reloc;
2266
2267 rview = state->views[resource_index];
2268 assert(rview);
2269
2270 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2271 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2272 radeon_emit_array(cs, rview->tex_resource_words, 8);
2273
2274 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2275 RADEON_USAGE_READ,
2276 r600_get_sampler_view_priority(rview->tex_resource));
2277 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2278 radeon_emit(cs, reloc);
2279
2280 if (!rview->skip_mip_address_reloc) {
2281 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2282 radeon_emit(cs, reloc);
2283 }
2284 }
2285 state->dirty_mask = 0;
2286 }
2287
2288 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2289 {
2290 if (rctx->vs_shader->current->shader.vs_as_ls) {
2291 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2292 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2293 } else {
2294 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2295 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2296 }
2297 }
2298
2299 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2300 {
2301 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2302 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2303 }
2304
2305 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2306 {
2307 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2308 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2309 }
2310
2311 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2312 {
2313 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2314 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2315 }
2316
2317 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2318 {
2319 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2320 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2321 }
2322
2323 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2324 {
2325 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2326 EG_FETCH_CONSTANTS_OFFSET_CS + 2, RADEON_CP_PACKET3_COMPUTE_MODE);
2327 }
2328
2329 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2330 struct r600_textures_info *texinfo,
2331 unsigned resource_id_base,
2332 unsigned border_index_reg,
2333 unsigned pkt_flags)
2334 {
2335 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2336 uint32_t dirty_mask = texinfo->states.dirty_mask;
2337
2338 while (dirty_mask) {
2339 struct r600_pipe_sampler_state *rstate;
2340 unsigned i = u_bit_scan(&dirty_mask);
2341
2342 rstate = texinfo->states.states[i];
2343 assert(rstate);
2344
2345 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2346 radeon_emit(cs, (resource_id_base + i) * 3);
2347 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2348
2349 if (rstate->border_color_use) {
2350 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2351 radeon_emit(cs, i);
2352 radeon_emit_array(cs, rstate->border_color.ui, 4);
2353 }
2354 }
2355 texinfo->states.dirty_mask = 0;
2356 }
2357
2358 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2359 {
2360 if (rctx->vs_shader->current->shader.vs_as_ls) {
2361 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2362 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2363 } else {
2364 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2365 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2366 }
2367 }
2368
2369 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2370 {
2371 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2372 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2373 }
2374
2375 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2376 {
2377 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2378 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2379 }
2380
2381 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2382 {
2383 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2384 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2385 }
2386
2387 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2388 {
2389 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2390 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2391 }
2392
2393 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2394 {
2395 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2396 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2397 RADEON_CP_PACKET3_COMPUTE_MODE);
2398 }
2399
2400 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2401 {
2402 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2403 uint8_t mask = s->sample_mask;
2404
2405 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2406 mask | (mask << 8) | (mask << 16) | (mask << 24));
2407 }
2408
2409 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2410 {
2411 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2412 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2413 uint16_t mask = s->sample_mask;
2414
2415 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2416 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2417 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2418 }
2419
2420 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2421 {
2422 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2423 struct r600_cso_state *state = (struct r600_cso_state*)a;
2424 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2425
2426 if (!shader)
2427 return;
2428
2429 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2430 (shader->buffer->gpu_address + shader->offset) >> 8);
2431 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2432 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2433 RADEON_USAGE_READ,
2434 RADEON_PRIO_SHADER_BINARY));
2435 }
2436
2437 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2438 {
2439 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2440 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2441
2442 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2443
2444 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2445 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2446 primid = 1;
2447 }
2448
2449 if (state->geom_enable) {
2450 uint32_t cut_val;
2451
2452 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2453 cut_val = V_028A40_GS_CUT_128;
2454 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2455 cut_val = V_028A40_GS_CUT_256;
2456 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2457 cut_val = V_028A40_GS_CUT_512;
2458 else
2459 cut_val = V_028A40_GS_CUT_1024;
2460
2461 v = S_028B54_GS_EN(1) |
2462 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2463 if (!rctx->tes_shader)
2464 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2465
2466 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2467 S_028A40_CUT_MODE(cut_val);
2468
2469 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2470 primid = 1;
2471 }
2472
2473 if (rctx->tes_shader) {
2474 uint32_t type, partitioning, topology;
2475 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2476 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2477 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2478 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2479 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2480 switch (tes_prim_mode) {
2481 case PIPE_PRIM_LINES:
2482 type = V_028B6C_TESS_ISOLINE;
2483 break;
2484 case PIPE_PRIM_TRIANGLES:
2485 type = V_028B6C_TESS_TRIANGLE;
2486 break;
2487 case PIPE_PRIM_QUADS:
2488 type = V_028B6C_TESS_QUAD;
2489 break;
2490 default:
2491 assert(0);
2492 return;
2493 }
2494
2495 switch (tes_spacing) {
2496 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2497 partitioning = V_028B6C_PART_FRAC_ODD;
2498 break;
2499 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2500 partitioning = V_028B6C_PART_FRAC_EVEN;
2501 break;
2502 case PIPE_TESS_SPACING_EQUAL:
2503 partitioning = V_028B6C_PART_INTEGER;
2504 break;
2505 default:
2506 assert(0);
2507 return;
2508 }
2509
2510 if (tes_point_mode)
2511 topology = V_028B6C_OUTPUT_POINT;
2512 else if (tes_prim_mode == PIPE_PRIM_LINES)
2513 topology = V_028B6C_OUTPUT_LINE;
2514 else if (tes_vertex_order_cw)
2515 /* XXX follow radeonsi and invert */
2516 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2517 else
2518 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2519
2520 tf_param = S_028B6C_TYPE(type) |
2521 S_028B6C_PARTITIONING(partitioning) |
2522 S_028B6C_TOPOLOGY(topology);
2523 }
2524
2525 if (rctx->tes_shader) {
2526 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2527 S_028B54_HS_EN(1);
2528 if (!state->geom_enable)
2529 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2530 else
2531 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2532 }
2533
2534 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2535 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2536 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2537 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2538 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2539 }
2540
2541 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2542 {
2543 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2544 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2545 struct r600_resource *rbuffer;
2546
2547 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2548 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2549 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2550
2551 if (state->enable) {
2552 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2553 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2554 rbuffer->gpu_address >> 8);
2555 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2556 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2557 RADEON_USAGE_READWRITE,
2558 RADEON_PRIO_SHADER_RINGS));
2559 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2560 state->esgs_ring.buffer_size >> 8);
2561
2562 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2563 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2564 rbuffer->gpu_address >> 8);
2565 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2566 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2567 RADEON_USAGE_READWRITE,
2568 RADEON_PRIO_SHADER_RINGS));
2569 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2570 state->gsvs_ring.buffer_size >> 8);
2571 } else {
2572 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2573 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2574 }
2575
2576 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2577 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2578 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2579 }
2580
2581 void cayman_init_common_regs(struct r600_command_buffer *cb,
2582 enum chip_class ctx_chip_class,
2583 enum radeon_family ctx_family,
2584 int ctx_drm_minor)
2585 {
2586 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2587 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2588 /* always set the temp clauses */
2589 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2590
2591 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2592 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2593 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2594
2595 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2596
2597 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2598 r600_store_value(cb, 0);
2599 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2600
2601 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2602 }
2603
2604 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2605 {
2606 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2607 int i;
2608
2609 r600_init_command_buffer(cb, 338);
2610
2611 /* This must be first. */
2612 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2613 r600_store_value(cb, 0x80000000);
2614 r600_store_value(cb, 0x80000000);
2615
2616 /* We're setting config registers here. */
2617 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2618 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2619
2620 /* This enables pipeline stat & streamout queries.
2621 * They are only disabled by blits.
2622 */
2623 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2624 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2625
2626 cayman_init_common_regs(cb, rctx->b.chip_class,
2627 rctx->b.family, rctx->screen->b.info.drm_minor);
2628
2629 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2630 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2631
2632 /* remove LS/HS from one SIMD for hw workaround */
2633 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2634 r600_store_value(cb, 0xffffffff);
2635 r600_store_value(cb, 0xffffffff);
2636 r600_store_value(cb, 0xfffffffe);
2637
2638 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2639 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2640 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2641 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2642 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2643 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2644 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2645
2646 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2647 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2648 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2649 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2650 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2651
2652 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2653 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2654 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2655 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2656 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2657 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2658 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2659 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2660 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2661 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2662 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2663 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2664 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2665 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2666
2667 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2668
2669 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2670
2671 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2672 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2673 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2674
2675 r600_store_context_reg(cb, R_028724_GDS_ADDR_SIZE, 0x3fff);
2676 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2677 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2678 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2679
2680 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2681
2682 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2683 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2684 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2685
2686 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2687
2688 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2689
2690 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2691
2692 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2693 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2694 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2695 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2696
2697 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2698 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2699
2700 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2701 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2702
2703 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2704 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2705 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2706
2707 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2708 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2709 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2710
2711 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2712 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2713 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2714 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2715 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2716 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2717
2718 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2719
2720 /* to avoid GPU doing any preloading of constant from random address */
2721 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2722 for (i = 0; i < 16; i++)
2723 r600_store_value(cb, 0);
2724
2725 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2726 for (i = 0; i < 16; i++)
2727 r600_store_value(cb, 0);
2728
2729 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2730 for (i = 0; i < 16; i++)
2731 r600_store_value(cb, 0);
2732
2733 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2734 for (i = 0; i < 16; i++)
2735 r600_store_value(cb, 0);
2736
2737 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2738 for (i = 0; i < 16; i++)
2739 r600_store_value(cb, 0);
2740
2741 if (rctx->screen->b.has_streamout) {
2742 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2743 }
2744
2745 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2746 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2747 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2748 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2749 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2750 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2751
2752 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2753 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2754 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2755 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2756 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2757 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2758 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2759 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2760 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2761 }
2762
2763 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2764 enum chip_class ctx_chip_class,
2765 enum radeon_family ctx_family,
2766 int ctx_drm_minor)
2767 {
2768 int ps_prio;
2769 int vs_prio;
2770 int gs_prio;
2771 int es_prio;
2772
2773 int hs_prio;
2774 int cs_prio;
2775 int ls_prio;
2776
2777 unsigned tmp;
2778
2779 ps_prio = 0;
2780 vs_prio = 1;
2781 gs_prio = 2;
2782 es_prio = 3;
2783 hs_prio = 3;
2784 ls_prio = 3;
2785 cs_prio = 0;
2786
2787 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2788 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2789 rctx->r6xx_num_clause_temp_gprs = 4;
2790 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2791 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2792 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2793 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2794
2795 tmp = 0;
2796 switch (ctx_family) {
2797 case CHIP_CEDAR:
2798 case CHIP_PALM:
2799 case CHIP_SUMO:
2800 case CHIP_SUMO2:
2801 case CHIP_CAICOS:
2802 break;
2803 default:
2804 tmp |= S_008C00_VC_ENABLE(1);
2805 break;
2806 }
2807 tmp |= S_008C00_EXPORT_SRC_C(1);
2808 tmp |= S_008C00_CS_PRIO(cs_prio);
2809 tmp |= S_008C00_LS_PRIO(ls_prio);
2810 tmp |= S_008C00_HS_PRIO(hs_prio);
2811 tmp |= S_008C00_PS_PRIO(ps_prio);
2812 tmp |= S_008C00_VS_PRIO(vs_prio);
2813 tmp |= S_008C00_GS_PRIO(gs_prio);
2814 tmp |= S_008C00_ES_PRIO(es_prio);
2815
2816 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2817 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2818
2819 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2820 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2821 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2822
2823 /* The cs checker requires this register to be set. */
2824 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2825
2826 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2827 r600_store_value(cb, 0);
2828 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2829
2830 return;
2831 }
2832
2833 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2834 {
2835 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2836 int num_ps_threads;
2837 int num_vs_threads;
2838 int num_gs_threads;
2839 int num_es_threads;
2840 int num_hs_threads;
2841 int num_ls_threads;
2842
2843 int num_ps_stack_entries;
2844 int num_vs_stack_entries;
2845 int num_gs_stack_entries;
2846 int num_es_stack_entries;
2847 int num_hs_stack_entries;
2848 int num_ls_stack_entries;
2849 enum radeon_family family;
2850 unsigned tmp, i;
2851
2852 if (rctx->b.chip_class == CAYMAN) {
2853 cayman_init_atom_start_cs(rctx);
2854 return;
2855 }
2856
2857 r600_init_command_buffer(cb, 338);
2858
2859 /* This must be first. */
2860 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2861 r600_store_value(cb, 0x80000000);
2862 r600_store_value(cb, 0x80000000);
2863
2864 /* We're setting config registers here. */
2865 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2866 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2867
2868 /* This enables pipeline stat & streamout queries.
2869 * They are only disabled by blits.
2870 */
2871 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2872 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2873
2874 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2875 rctx->b.family, rctx->screen->b.info.drm_minor);
2876
2877 family = rctx->b.family;
2878 switch (family) {
2879 case CHIP_CEDAR:
2880 default:
2881 num_ps_threads = 96;
2882 num_vs_threads = 16;
2883 num_gs_threads = 16;
2884 num_es_threads = 16;
2885 num_hs_threads = 16;
2886 num_ls_threads = 16;
2887 num_ps_stack_entries = 42;
2888 num_vs_stack_entries = 42;
2889 num_gs_stack_entries = 42;
2890 num_es_stack_entries = 42;
2891 num_hs_stack_entries = 42;
2892 num_ls_stack_entries = 42;
2893 break;
2894 case CHIP_REDWOOD:
2895 num_ps_threads = 128;
2896 num_vs_threads = 20;
2897 num_gs_threads = 20;
2898 num_es_threads = 20;
2899 num_hs_threads = 20;
2900 num_ls_threads = 20;
2901 num_ps_stack_entries = 42;
2902 num_vs_stack_entries = 42;
2903 num_gs_stack_entries = 42;
2904 num_es_stack_entries = 42;
2905 num_hs_stack_entries = 42;
2906 num_ls_stack_entries = 42;
2907 break;
2908 case CHIP_JUNIPER:
2909 num_ps_threads = 128;
2910 num_vs_threads = 20;
2911 num_gs_threads = 20;
2912 num_es_threads = 20;
2913 num_hs_threads = 20;
2914 num_ls_threads = 20;
2915 num_ps_stack_entries = 85;
2916 num_vs_stack_entries = 85;
2917 num_gs_stack_entries = 85;
2918 num_es_stack_entries = 85;
2919 num_hs_stack_entries = 85;
2920 num_ls_stack_entries = 85;
2921 break;
2922 case CHIP_CYPRESS:
2923 case CHIP_HEMLOCK:
2924 num_ps_threads = 128;
2925 num_vs_threads = 20;
2926 num_gs_threads = 20;
2927 num_es_threads = 20;
2928 num_hs_threads = 20;
2929 num_ls_threads = 20;
2930 num_ps_stack_entries = 85;
2931 num_vs_stack_entries = 85;
2932 num_gs_stack_entries = 85;
2933 num_es_stack_entries = 85;
2934 num_hs_stack_entries = 85;
2935 num_ls_stack_entries = 85;
2936 break;
2937 case CHIP_PALM:
2938 num_ps_threads = 96;
2939 num_vs_threads = 16;
2940 num_gs_threads = 16;
2941 num_es_threads = 16;
2942 num_hs_threads = 16;
2943 num_ls_threads = 16;
2944 num_ps_stack_entries = 42;
2945 num_vs_stack_entries = 42;
2946 num_gs_stack_entries = 42;
2947 num_es_stack_entries = 42;
2948 num_hs_stack_entries = 42;
2949 num_ls_stack_entries = 42;
2950 break;
2951 case CHIP_SUMO:
2952 num_ps_threads = 96;
2953 num_vs_threads = 25;
2954 num_gs_threads = 25;
2955 num_es_threads = 25;
2956 num_hs_threads = 16;
2957 num_ls_threads = 16;
2958 num_ps_stack_entries = 42;
2959 num_vs_stack_entries = 42;
2960 num_gs_stack_entries = 42;
2961 num_es_stack_entries = 42;
2962 num_hs_stack_entries = 42;
2963 num_ls_stack_entries = 42;
2964 break;
2965 case CHIP_SUMO2:
2966 num_ps_threads = 96;
2967 num_vs_threads = 25;
2968 num_gs_threads = 25;
2969 num_es_threads = 25;
2970 num_hs_threads = 16;
2971 num_ls_threads = 16;
2972 num_ps_stack_entries = 85;
2973 num_vs_stack_entries = 85;
2974 num_gs_stack_entries = 85;
2975 num_es_stack_entries = 85;
2976 num_hs_stack_entries = 85;
2977 num_ls_stack_entries = 85;
2978 break;
2979 case CHIP_BARTS:
2980 num_ps_threads = 128;
2981 num_vs_threads = 20;
2982 num_gs_threads = 20;
2983 num_es_threads = 20;
2984 num_hs_threads = 20;
2985 num_ls_threads = 20;
2986 num_ps_stack_entries = 85;
2987 num_vs_stack_entries = 85;
2988 num_gs_stack_entries = 85;
2989 num_es_stack_entries = 85;
2990 num_hs_stack_entries = 85;
2991 num_ls_stack_entries = 85;
2992 break;
2993 case CHIP_TURKS:
2994 num_ps_threads = 128;
2995 num_vs_threads = 20;
2996 num_gs_threads = 20;
2997 num_es_threads = 20;
2998 num_hs_threads = 20;
2999 num_ls_threads = 20;
3000 num_ps_stack_entries = 42;
3001 num_vs_stack_entries = 42;
3002 num_gs_stack_entries = 42;
3003 num_es_stack_entries = 42;
3004 num_hs_stack_entries = 42;
3005 num_ls_stack_entries = 42;
3006 break;
3007 case CHIP_CAICOS:
3008 num_ps_threads = 96;
3009 num_vs_threads = 10;
3010 num_gs_threads = 10;
3011 num_es_threads = 10;
3012 num_hs_threads = 10;
3013 num_ls_threads = 10;
3014 num_ps_stack_entries = 42;
3015 num_vs_stack_entries = 42;
3016 num_gs_stack_entries = 42;
3017 num_es_stack_entries = 42;
3018 num_hs_stack_entries = 42;
3019 num_ls_stack_entries = 42;
3020 break;
3021 }
3022
3023 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
3024 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
3025 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
3026 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
3027
3028 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
3029 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3030
3031 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
3032 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
3033 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3034
3035 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
3036 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
3037 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3038
3039 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
3040 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
3041 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3042
3043 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
3044 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
3045 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3046
3047 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
3048 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
3049
3050 /* remove LS/HS from one SIMD for hw workaround */
3051 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
3052 r600_store_value(cb, 0xffffffff);
3053 r600_store_value(cb, 0xffffffff);
3054 r600_store_value(cb, 0xfffffffe);
3055
3056 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
3057 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
3058
3059 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
3060 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3061 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3062 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3063 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3064 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3065 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3066
3067 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3068 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3069 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3070 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3071 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3072
3073 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
3074 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3075 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
3076 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3077 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3078 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3079 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3080 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3081 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
3082 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3083 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3084 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3085 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3086 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
3087
3088 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
3089
3090 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
3091
3092 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
3093 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3094 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
3095
3096 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
3097
3098 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
3099
3100 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
3101 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3102 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3103
3104 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
3105 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
3106
3107 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
3108 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3109 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3110 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3111
3112 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
3113 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3114 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3115
3116 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
3117 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3118 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3119
3120 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3121 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3122 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3123 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3124 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
3125 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3126 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3127
3128 /* to avoid GPU doing any preloading of constant from random address */
3129 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
3130 for (i = 0; i < 16; i++)
3131 r600_store_value(cb, 0);
3132
3133 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
3134 for (i = 0; i < 16; i++)
3135 r600_store_value(cb, 0);
3136
3137 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
3138 for (i = 0; i < 16; i++)
3139 r600_store_value(cb, 0);
3140
3141 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
3142 for (i = 0; i < 16; i++)
3143 r600_store_value(cb, 0);
3144
3145 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
3146 for (i = 0; i < 16; i++)
3147 r600_store_value(cb, 0);
3148
3149 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
3150
3151 if (rctx->screen->b.has_streamout) {
3152 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3153 }
3154
3155 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
3156 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3157 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
3158 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
3159 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3160 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3161
3162 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
3163 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
3164 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
3165
3166 if (rctx->b.family == CHIP_CAICOS) {
3167 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
3168 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3169 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3170 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
3171 } else {
3172 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
3173 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3174 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3175 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
3176 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
3177 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
3178 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
3179 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
3180 }
3181
3182 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3183 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3184 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
3185 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
3186 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
3187 }
3188
3189 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3190 {
3191 struct r600_context *rctx = (struct r600_context *)ctx;
3192 struct r600_command_buffer *cb = &shader->command_buffer;
3193 struct r600_shader *rshader = &shader->shader;
3194 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
3195 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
3196 int ninterp = 0;
3197 boolean have_perspective = FALSE, have_linear = FALSE;
3198 static const unsigned spi_baryc_enable_bit[6] = {
3199 S_0286E0_PERSP_SAMPLE_ENA(1),
3200 S_0286E0_PERSP_CENTER_ENA(1),
3201 S_0286E0_PERSP_CENTROID_ENA(1),
3202 S_0286E0_LINEAR_SAMPLE_ENA(1),
3203 S_0286E0_LINEAR_CENTER_ENA(1),
3204 S_0286E0_LINEAR_CENTROID_ENA(1)
3205 };
3206 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
3207 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
3208 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3209 uint32_t spi_ps_input_cntl[32];
3210
3211 if (!cb->buf) {
3212 r600_init_command_buffer(cb, 64);
3213 } else {
3214 cb->num_dw = 0;
3215 }
3216
3217 for (i = 0; i < rshader->ninput; i++) {
3218 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3219 POSITION goes via GPRs from the SC so isn't counted */
3220 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3221 pos_index = i;
3222 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
3223 if (face_index == -1)
3224 face_index = i;
3225 }
3226 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3227 if (face_index == -1)
3228 face_index = i; /* lives in same register, same enable bit */
3229 }
3230 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
3231 fixed_pt_position_index = i;
3232 }
3233 else {
3234 ninterp++;
3235 int k = eg_get_interpolator_index(
3236 rshader->input[i].interpolate,
3237 rshader->input[i].interpolate_location);
3238 if (k >= 0) {
3239 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3240 have_perspective |= k < 3;
3241 have_linear |= !(k < 3);
3242 }
3243 }
3244
3245 sid = rshader->input[i].spi_sid;
3246
3247 if (sid) {
3248 tmp = S_028644_SEMANTIC(sid);
3249
3250 /* D3D 9 behaviour. GL is undefined */
3251 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
3252 tmp |= S_028644_DEFAULT_VAL(3);
3253
3254 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3255 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3256 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3257 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3258 tmp |= S_028644_FLAT_SHADE(1);
3259 }
3260
3261 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3262 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3263 tmp |= S_028644_PT_SPRITE_TEX(1);
3264 }
3265
3266 spi_ps_input_cntl[num++] = tmp;
3267 }
3268 }
3269
3270 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3271 r600_store_array(cb, num, spi_ps_input_cntl);
3272
3273 for (i = 0; i < rshader->noutput; i++) {
3274 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3275 z_export = 1;
3276 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3277 stencil_export = 1;
3278 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3279 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3280 mask_export = 1;
3281 }
3282 if (rshader->uses_kill)
3283 db_shader_control |= S_02880C_KILL_ENABLE(1);
3284
3285 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3286 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3287 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3288
3289 if (shader->selector->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
3290 db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
3291 S_02880C_EXEC_ON_NOOP(shader->selector->info.writes_memory);
3292 } else if (shader->selector->info.writes_memory) {
3293 db_shader_control |= S_02880C_EXEC_ON_HIER_FAIL(1);
3294 }
3295
3296 switch (rshader->ps_conservative_z) {
3297 default: /* fall through */
3298 case TGSI_FS_DEPTH_LAYOUT_ANY:
3299 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3300 break;
3301 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3302 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3303 break;
3304 case TGSI_FS_DEPTH_LAYOUT_LESS:
3305 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3306 break;
3307 }
3308
3309 exports_ps = 0;
3310 for (i = 0; i < rshader->noutput; i++) {
3311 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3312 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3313 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3314 exports_ps |= 1;
3315 }
3316
3317 num_cout = rshader->nr_ps_color_exports;
3318
3319 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3320 if (!exports_ps) {
3321 /* always at least export 1 component per pixel */
3322 exports_ps = 2;
3323 }
3324 shader->nr_ps_color_outputs = num_cout;
3325 if (ninterp == 0) {
3326 ninterp = 1;
3327 have_perspective = TRUE;
3328 }
3329 if (!spi_baryc_cntl)
3330 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3331
3332 if (!have_perspective && !have_linear)
3333 have_perspective = TRUE;
3334
3335 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3336 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3337 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3338 spi_input_z = 0;
3339 if (pos_index != -1) {
3340 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3341 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3342 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3343 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3344 }
3345
3346 spi_ps_in_control_1 = 0;
3347 if (face_index != -1) {
3348 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3349 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3350 }
3351 if (fixed_pt_position_index != -1) {
3352 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3353 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3354 }
3355
3356 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3357 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3358 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3359
3360 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3361 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3362 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3363
3364 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3365 r600_store_value(cb, shader->bo->gpu_address >> 8);
3366 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3367 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3368 S_028844_PRIME_CACHE_ON_DRAW(1) |
3369 S_028844_DX10_CLAMP(1) |
3370 S_028844_STACK_SIZE(rshader->bc.nstack));
3371 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3372
3373 shader->db_shader_control = db_shader_control;
3374 shader->ps_depth_export = z_export | stencil_export | mask_export;
3375
3376 shader->sprite_coord_enable = sprite_coord_enable;
3377 if (rctx->rasterizer)
3378 shader->flatshade = rctx->rasterizer->flatshade;
3379 }
3380
3381 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3382 {
3383 struct r600_command_buffer *cb = &shader->command_buffer;
3384 struct r600_shader *rshader = &shader->shader;
3385
3386 r600_init_command_buffer(cb, 32);
3387
3388 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3389 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3390 S_028890_DX10_CLAMP(1) |
3391 S_028890_STACK_SIZE(rshader->bc.nstack));
3392 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3393 shader->bo->gpu_address >> 8);
3394 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3395 }
3396
3397 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3398 {
3399 struct r600_context *rctx = (struct r600_context *)ctx;
3400 struct r600_command_buffer *cb = &shader->command_buffer;
3401 struct r600_shader *rshader = &shader->shader;
3402 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3403 unsigned gsvs_itemsizes[4] = {
3404 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3405 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3406 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3407 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3408 };
3409
3410 r600_init_command_buffer(cb, 64);
3411
3412 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3413
3414
3415 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3416 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3417 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3418 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3419
3420 if (rctx->screen->b.info.drm_minor >= 35) {
3421 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3422 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3423 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3424 }
3425 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3426 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3427 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3428 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3429 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3430
3431 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3432 (rshader->ring_item_sizes[0]) >> 2);
3433
3434 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3435 gsvs_itemsizes[0] +
3436 gsvs_itemsizes[1] +
3437 gsvs_itemsizes[2] +
3438 gsvs_itemsizes[3]);
3439
3440 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3441 r600_store_value(cb, gsvs_itemsizes[0]);
3442 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3443 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3444
3445 /* FIXME calculate these values somehow ??? */
3446 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3447 r600_store_value(cb, 0x80); /* GS_PER_ES */
3448 r600_store_value(cb, 0x100); /* ES_PER_GS */
3449 r600_store_value(cb, 0x2); /* GS_PER_VS */
3450
3451 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3452 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3453 S_028878_DX10_CLAMP(1) |
3454 S_028878_STACK_SIZE(rshader->bc.nstack));
3455 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3456 shader->bo->gpu_address >> 8);
3457 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3458 }
3459
3460
3461 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3462 {
3463 struct r600_command_buffer *cb = &shader->command_buffer;
3464 struct r600_shader *rshader = &shader->shader;
3465 unsigned spi_vs_out_id[10] = {};
3466 unsigned i, tmp, nparams = 0;
3467
3468 for (i = 0; i < rshader->noutput; i++) {
3469 if (rshader->output[i].spi_sid) {
3470 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3471 spi_vs_out_id[nparams / 4] |= tmp;
3472 nparams++;
3473 }
3474 }
3475
3476 r600_init_command_buffer(cb, 32);
3477
3478 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3479 for (i = 0; i < 10; i++) {
3480 r600_store_value(cb, spi_vs_out_id[i]);
3481 }
3482
3483 /* Certain attributes (position, psize, etc.) don't count as params.
3484 * VS is required to export at least one param and r600_shader_from_tgsi()
3485 * takes care of adding a dummy export.
3486 */
3487 if (nparams < 1)
3488 nparams = 1;
3489
3490 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3491 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3492 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3493 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3494 S_028860_DX10_CLAMP(1) |
3495 S_028860_STACK_SIZE(rshader->bc.nstack));
3496 if (rshader->vs_position_window_space) {
3497 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3498 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3499 } else {
3500 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3501 S_028818_VTX_W0_FMT(1) |
3502 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3503 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3504 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3505
3506 }
3507 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3508 shader->bo->gpu_address >> 8);
3509 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3510
3511 shader->pa_cl_vs_out_cntl =
3512 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->cc_dist_mask & 0x0F) != 0) |
3513 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->cc_dist_mask & 0xF0) != 0) |
3514 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3515 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3516 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3517 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3518 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3519 }
3520
3521 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3522 {
3523 struct r600_command_buffer *cb = &shader->command_buffer;
3524 struct r600_shader *rshader = &shader->shader;
3525
3526 r600_init_command_buffer(cb, 32);
3527 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3528 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3529 S_0288BC_DX10_CLAMP(1) |
3530 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3531 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3532 shader->bo->gpu_address >> 8);
3533 }
3534
3535 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3536 {
3537 struct r600_command_buffer *cb = &shader->command_buffer;
3538 struct r600_shader *rshader = &shader->shader;
3539
3540 r600_init_command_buffer(cb, 32);
3541 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3542 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3543 S_0288D4_DX10_CLAMP(1) |
3544 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3545 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3546 shader->bo->gpu_address >> 8);
3547 }
3548 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3549 {
3550 struct pipe_blend_state blend;
3551
3552 memset(&blend, 0, sizeof(blend));
3553 blend.independent_blend_enable = true;
3554 blend.rt[0].colormask = 0xf;
3555 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3556 }
3557
3558 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3559 {
3560 struct pipe_blend_state blend;
3561 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3562 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3563
3564 memset(&blend, 0, sizeof(blend));
3565 blend.independent_blend_enable = true;
3566 blend.rt[0].colormask = 0xf;
3567 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3568 }
3569
3570 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3571 {
3572 struct pipe_blend_state blend;
3573 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3574
3575 memset(&blend, 0, sizeof(blend));
3576 blend.independent_blend_enable = true;
3577 blend.rt[0].colormask = 0xf;
3578 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3579 }
3580
3581 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3582 {
3583 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3584
3585 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3586 }
3587
3588 void evergreen_update_db_shader_control(struct r600_context * rctx)
3589 {
3590 bool dual_export;
3591 unsigned db_shader_control;
3592
3593 if (!rctx->ps_shader) {
3594 return;
3595 }
3596
3597 dual_export = rctx->framebuffer.export_16bpc &&
3598 !rctx->ps_shader->current->ps_depth_export;
3599
3600 db_shader_control = rctx->ps_shader->current->db_shader_control |
3601 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3602 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3603 V_02880C_EXPORT_DB_FULL) |
3604 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3605
3606 /* When alpha test is enabled we can't trust the hw to make the proper
3607 * decision on the order in which ztest should be run related to fragment
3608 * shader execution.
3609 *
3610 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3611 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3612 * execution and thus after alpha test so if discarded by the alpha test
3613 * the z value is not written.
3614 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3615 * get a hang unless you flush the DB in between. For now just use
3616 * LATE_Z.
3617 */
3618 if (rctx->alphatest_state.sx_alpha_test_control || rctx->ps_shader->info.writes_memory) {
3619 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3620 } else {
3621 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3622 }
3623
3624 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3625 rctx->db_misc_state.db_shader_control = db_shader_control;
3626 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3627 }
3628 }
3629
3630 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3631 struct pipe_resource *dst,
3632 unsigned dst_level,
3633 unsigned dst_x,
3634 unsigned dst_y,
3635 unsigned dst_z,
3636 struct pipe_resource *src,
3637 unsigned src_level,
3638 unsigned src_x,
3639 unsigned src_y,
3640 unsigned src_z,
3641 unsigned copy_height,
3642 unsigned pitch,
3643 unsigned bpp)
3644 {
3645 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3646 struct r600_texture *rsrc = (struct r600_texture*)src;
3647 struct r600_texture *rdst = (struct r600_texture*)dst;
3648 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3649 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3650 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3651 uint64_t base, addr;
3652
3653 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3654 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3655 assert(dst_mode != src_mode);
3656
3657 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3658 if (util_format_has_depth(util_format_description(src->format)))
3659 non_disp_tiling = 1;
3660
3661 y = 0;
3662 sub_cmd = EG_DMA_COPY_TILED;
3663 lbpp = util_logbase2(bpp);
3664 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3665 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3666
3667 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
3668 /* T2L */
3669 array_mode = evergreen_array_mode(src_mode);
3670 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
3671 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3672 /* linear height must be the same as the slice tile max height, it's ok even
3673 * if the linear destination/source have smaller heigh as the size of the
3674 * dma packet will be using the copy_height which is always smaller or equal
3675 * to the linear height
3676 */
3677 height = u_minify(rsrc->resource.b.b.height0, src_level);
3678 detile = 1;
3679 x = src_x;
3680 y = src_y;
3681 z = src_z;
3682 base = rsrc->surface.u.legacy.level[src_level].offset;
3683 addr = rdst->surface.u.legacy.level[dst_level].offset;
3684 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3685 addr += dst_y * pitch + dst_x * bpp;
3686 bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh);
3687 bank_w = eg_bank_wh(rsrc->surface.u.legacy.bankw);
3688 mt_aspect = eg_macro_tile_aspect(rsrc->surface.u.legacy.mtilea);
3689 tile_split = eg_tile_split(rsrc->surface.u.legacy.tile_split);
3690 base += rsrc->resource.gpu_address;
3691 addr += rdst->resource.gpu_address;
3692 } else {
3693 /* L2T */
3694 array_mode = evergreen_array_mode(dst_mode);
3695 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
3696 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3697 /* linear height must be the same as the slice tile max height, it's ok even
3698 * if the linear destination/source have smaller heigh as the size of the
3699 * dma packet will be using the copy_height which is always smaller or equal
3700 * to the linear height
3701 */
3702 height = u_minify(rdst->resource.b.b.height0, dst_level);
3703 detile = 0;
3704 x = dst_x;
3705 y = dst_y;
3706 z = dst_z;
3707 base = rdst->surface.u.legacy.level[dst_level].offset;
3708 addr = rsrc->surface.u.legacy.level[src_level].offset;
3709 addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z;
3710 addr += src_y * pitch + src_x * bpp;
3711 bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh);
3712 bank_w = eg_bank_wh(rdst->surface.u.legacy.bankw);
3713 mt_aspect = eg_macro_tile_aspect(rdst->surface.u.legacy.mtilea);
3714 tile_split = eg_tile_split(rdst->surface.u.legacy.tile_split);
3715 base += rdst->resource.gpu_address;
3716 addr += rsrc->resource.gpu_address;
3717 }
3718
3719 size = (copy_height * pitch) / 4;
3720 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3721 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
3722
3723 for (i = 0; i < ncopy; i++) {
3724 cheight = copy_height;
3725 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3726 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3727 }
3728 size = (cheight * pitch) / 4;
3729 /* emit reloc before writing cs so that cs is always in consistent state */
3730 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3731 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3732 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3733 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3734 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size));
3735 radeon_emit(cs, base >> 8);
3736 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
3737 (lbpp << 24) | (bank_h << 21) |
3738 (bank_w << 18) | (mt_aspect << 16));
3739 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
3740 radeon_emit(cs, (slice_tile_max << 0));
3741 radeon_emit(cs, (x << 0) | (z << 18));
3742 radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28));
3743 radeon_emit(cs, addr & 0xfffffffc);
3744 radeon_emit(cs, (addr >> 32UL) & 0xff);
3745 copy_height -= cheight;
3746 addr += cheight * pitch;
3747 y += cheight;
3748 }
3749 }
3750
3751 static void evergreen_dma_copy(struct pipe_context *ctx,
3752 struct pipe_resource *dst,
3753 unsigned dst_level,
3754 unsigned dstx, unsigned dsty, unsigned dstz,
3755 struct pipe_resource *src,
3756 unsigned src_level,
3757 const struct pipe_box *src_box)
3758 {
3759 struct r600_context *rctx = (struct r600_context *)ctx;
3760 struct r600_texture *rsrc = (struct r600_texture*)src;
3761 struct r600_texture *rdst = (struct r600_texture*)dst;
3762 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3763 unsigned src_w, dst_w;
3764 unsigned src_x, src_y;
3765 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3766
3767 if (rctx->b.dma.cs == NULL) {
3768 goto fallback;
3769 }
3770
3771 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3772 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3773 return;
3774 }
3775
3776 if (src_box->depth > 1 ||
3777 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3778 dstz, rsrc, src_level, src_box))
3779 goto fallback;
3780
3781 src_x = util_format_get_nblocksx(src->format, src_box->x);
3782 dst_x = util_format_get_nblocksx(src->format, dst_x);
3783 src_y = util_format_get_nblocksy(src->format, src_box->y);
3784 dst_y = util_format_get_nblocksy(src->format, dst_y);
3785
3786 bpp = rdst->surface.bpe;
3787 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
3788 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
3789 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
3790 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
3791 copy_height = src_box->height / rsrc->surface.blk_h;
3792
3793 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3794 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3795
3796 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3797 /* FIXME evergreen can do partial blit */
3798 goto fallback;
3799 }
3800 /* the x test here are currently useless (because we don't support partial blit)
3801 * but keep them around so we don't forget about those
3802 */
3803 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3804 goto fallback;
3805 }
3806
3807 /* 128 bpp surfaces require non_disp_tiling for both
3808 * tiled and linear buffers on cayman. However, async
3809 * DMA only supports it on the tiled side. As such
3810 * the tile order is backwards after a L2T/T2L packet.
3811 */
3812 if ((rctx->b.chip_class == CAYMAN) &&
3813 (src_mode != dst_mode) &&
3814 (util_format_get_blocksize(src->format) >= 16)) {
3815 goto fallback;
3816 }
3817
3818 if (src_mode == dst_mode) {
3819 uint64_t dst_offset, src_offset;
3820 /* simple dma blit would do NOTE code here assume :
3821 * src_box.x/y == 0
3822 * dst_x/y == 0
3823 * dst_pitch == src_pitch
3824 */
3825 src_offset= rsrc->surface.u.legacy.level[src_level].offset;
3826 src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
3827 src_offset += src_y * src_pitch + src_x * bpp;
3828 dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
3829 dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3830 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3831 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3832 src_box->height * src_pitch);
3833 } else {
3834 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3835 src, src_level, src_x, src_y, src_box->z,
3836 copy_height, dst_pitch, bpp);
3837 }
3838 return;
3839
3840 fallback:
3841 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3842 src, src_level, src_box);
3843 }
3844
3845 static void evergreen_set_tess_state(struct pipe_context *ctx,
3846 const float default_outer_level[4],
3847 const float default_inner_level[2])
3848 {
3849 struct r600_context *rctx = (struct r600_context *)ctx;
3850
3851 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3852 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3853 rctx->tess_state_dirty = true;
3854 }
3855
3856 static void evergreen_setup_immed_buffer(struct r600_context *rctx,
3857 struct r600_image_view *rview,
3858 enum pipe_format pformat)
3859 {
3860 struct r600_screen *rscreen = (struct r600_screen *)rctx->b.b.screen;
3861 uint32_t immed_size = rscreen->b.info.max_se * 256 * 64 * util_format_get_blocksize(pformat);
3862 struct eg_buf_res_params buf_params;
3863 bool skip_reloc = false;
3864 struct r600_resource *resource = (struct r600_resource *)rview->base.resource;
3865 if (!resource->immed_buffer) {
3866 eg_resource_alloc_immed(&rscreen->b, resource, immed_size);
3867 }
3868
3869 memset(&buf_params, 0, sizeof(buf_params));
3870 buf_params.pipe_format = pformat;
3871 buf_params.size = resource->immed_buffer->b.b.width0;
3872 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
3873 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
3874 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
3875 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
3876 buf_params.uncached = 1;
3877 evergreen_fill_buffer_resource_words(rctx, &resource->immed_buffer->b.b,
3878 &buf_params, &skip_reloc,
3879 rview->immed_resource_words);
3880 }
3881
3882 static void evergreen_set_hw_atomic_buffers(struct pipe_context *ctx,
3883 unsigned start_slot,
3884 unsigned count,
3885 const struct pipe_shader_buffer *buffers)
3886 {
3887 struct r600_context *rctx = (struct r600_context *)ctx;
3888 struct r600_atomic_buffer_state *astate;
3889 int i, idx;
3890
3891 astate = &rctx->atomic_buffer_state;
3892
3893 /* we'd probably like to expand this to 8 later so put the logic in */
3894 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
3895 const struct pipe_shader_buffer *buf;
3896 struct pipe_shader_buffer *abuf;
3897
3898 abuf = &astate->buffer[i];
3899
3900 if (!buffers || !buffers[idx].buffer) {
3901 pipe_resource_reference(&abuf->buffer, NULL);
3902 astate->enabled_mask &= ~(1 << i);
3903 continue;
3904 }
3905 buf = &buffers[idx];
3906
3907 pipe_resource_reference(&abuf->buffer, buf->buffer);
3908 abuf->buffer_offset = buf->buffer_offset;
3909 abuf->buffer_size = buf->buffer_size;
3910 astate->enabled_mask |= (1 << i);
3911 }
3912 }
3913
3914 static void evergreen_set_shader_buffers(struct pipe_context *ctx,
3915 enum pipe_shader_type shader, unsigned start_slot,
3916 unsigned count,
3917 const struct pipe_shader_buffer *buffers)
3918 {
3919 struct r600_context *rctx = (struct r600_context *)ctx;
3920 struct r600_image_state *istate = NULL;
3921 struct r600_image_view *rview;
3922 struct r600_tex_color_info color;
3923 struct eg_buf_res_params buf_params;
3924 struct r600_resource *resource;
3925 int i, idx;
3926 unsigned old_mask;
3927
3928 if (shader != PIPE_SHADER_FRAGMENT && count == 0)
3929 return;
3930
3931 assert(shader == PIPE_SHADER_FRAGMENT);
3932 istate = &rctx->fragment_buffers;
3933
3934 old_mask = istate->enabled_mask;
3935 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
3936 const struct pipe_shader_buffer *buf;
3937 unsigned res_type;
3938
3939 rview = &istate->views[i];
3940
3941 if (!buffers || !buffers[idx].buffer) {
3942 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
3943 istate->enabled_mask &= ~(1 << i);
3944 continue;
3945 }
3946
3947 buf = &buffers[idx];
3948 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, buf->buffer);
3949
3950 resource = (struct r600_resource *)rview->base.resource;
3951
3952 evergreen_setup_immed_buffer(rctx, rview, PIPE_FORMAT_R32_UINT);
3953
3954 color.offset = 0;
3955 color.view = 0;
3956 evergreen_set_color_surface_buffer(rctx, resource,
3957 PIPE_FORMAT_R32_UINT,
3958 buf->buffer_offset,
3959 buf->buffer_offset + buf->buffer_size,
3960 &color);
3961
3962 res_type = V_028C70_BUFFER;
3963
3964 rview->cb_color_base = color.offset;
3965 rview->cb_color_dim = color.dim;
3966 rview->cb_color_info = color.info |
3967 S_028C70_RAT(1) |
3968 S_028C70_RESOURCE_TYPE(res_type);
3969 rview->cb_color_pitch = color.pitch;
3970 rview->cb_color_slice = color.slice;
3971 rview->cb_color_view = color.view;
3972 rview->cb_color_attrib = color.attrib;
3973 rview->cb_color_fmask = color.fmask;
3974 rview->cb_color_fmask_slice = color.fmask_slice;
3975
3976 memset(&buf_params, 0, sizeof(buf_params));
3977 buf_params.pipe_format = PIPE_FORMAT_R32_UINT;
3978 buf_params.offset = buf->buffer_offset;
3979 buf_params.size = buf->buffer_size;
3980 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
3981 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
3982 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
3983 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
3984 buf_params.force_swizzle = true;
3985 buf_params.uncached = 1;
3986 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
3987 &buf_params,
3988 &rview->skip_mip_address_reloc,
3989 rview->resource_words);
3990
3991 istate->enabled_mask |= (1 << i);
3992 }
3993
3994 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
3995
3996 if (old_mask != istate->enabled_mask)
3997 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
3998
3999 if (rctx->cb_misc_state.nr_buffer_rats != util_bitcount(istate->enabled_mask)) {
4000 rctx->cb_misc_state.nr_buffer_rats = util_bitcount(istate->enabled_mask);
4001 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4002 }
4003
4004 r600_mark_atom_dirty(rctx, &istate->atom);
4005 }
4006
4007 static void evergreen_set_shader_images(struct pipe_context *ctx,
4008 enum pipe_shader_type shader, unsigned start_slot,
4009 unsigned count,
4010 const struct pipe_image_view *images)
4011 {
4012 struct r600_context *rctx = (struct r600_context *)ctx;
4013 int i;
4014 struct r600_image_view *rview;
4015 struct pipe_resource *image;
4016 struct r600_resource *resource;
4017 struct r600_tex_color_info color;
4018 struct eg_buf_res_params buf_params;
4019 struct eg_tex_res_params tex_params;
4020 unsigned old_mask;
4021 struct r600_image_state *istate = NULL;
4022 int idx;
4023 if (shader != PIPE_SHADER_FRAGMENT && count == 0)
4024 return;
4025
4026 istate = &rctx->fragment_images;
4027
4028 assert (shader == PIPE_SHADER_FRAGMENT);
4029 old_mask = istate->enabled_mask;
4030 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4031 unsigned res_type;
4032 const struct pipe_image_view *iview;
4033 rview = &istate->views[i];
4034
4035 if (!images || !images[idx].resource) {
4036 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
4037 istate->enabled_mask &= ~(1 << i);
4038 continue;
4039 }
4040
4041 iview = &images[idx];
4042 image = iview->resource;
4043 resource = (struct r600_resource *)image;
4044
4045 r600_context_add_resource_size(ctx, image);
4046
4047 rview->base = *iview;
4048 rview->base.resource = NULL;
4049 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, image);
4050
4051 evergreen_setup_immed_buffer(rctx, rview, iview->format);
4052
4053 bool is_buffer = image->target == PIPE_BUFFER;
4054 struct r600_texture *rtex = (struct r600_texture *)image;
4055 if (!is_buffer & rtex->db_compatible)
4056 istate->compressed_depthtex_mask |= 1 << i;
4057 else
4058 istate->compressed_depthtex_mask &= ~(1 << i);
4059
4060 if (!is_buffer && rtex->cmask.size)
4061 istate->compressed_colortex_mask |= 1 << i;
4062 else
4063 istate->compressed_colortex_mask &= ~(1 << i);
4064 if (!is_buffer) {
4065
4066 evergreen_set_color_surface_common(rctx, rtex,
4067 iview->u.tex.level,
4068 iview->u.tex.first_layer,
4069 iview->u.tex.last_layer,
4070 iview->format,
4071 &color);
4072 color.dim = S_028C78_WIDTH_MAX(u_minify(image->width0, iview->u.tex.level) - 1) |
4073 S_028C78_HEIGHT_MAX(u_minify(image->height0, iview->u.tex.level) - 1);
4074 } else {
4075 color.offset = 0;
4076 color.view = 0;
4077 evergreen_set_color_surface_buffer(rctx, resource,
4078 iview->format,
4079 iview->u.buf.offset,
4080 iview->u.buf.size,
4081 &color);
4082 }
4083
4084 switch (image->target) {
4085 case PIPE_BUFFER:
4086 res_type = V_028C70_BUFFER;
4087 break;
4088 case PIPE_TEXTURE_1D:
4089 res_type = V_028C70_TEXTURE1D;
4090 break;
4091 case PIPE_TEXTURE_1D_ARRAY:
4092 res_type = V_028C70_TEXTURE1DARRAY;
4093 break;
4094 case PIPE_TEXTURE_2D:
4095 case PIPE_TEXTURE_RECT:
4096 res_type = V_028C70_TEXTURE2D;
4097 break;
4098 case PIPE_TEXTURE_3D:
4099 res_type = V_028C70_TEXTURE3D;
4100 break;
4101 case PIPE_TEXTURE_2D_ARRAY:
4102 case PIPE_TEXTURE_CUBE:
4103 case PIPE_TEXTURE_CUBE_ARRAY:
4104 res_type = V_028C70_TEXTURE2DARRAY;
4105 break;
4106 default:
4107 assert(0);
4108 res_type = 0;
4109 break;
4110 }
4111
4112 rview->cb_color_base = color.offset;
4113 rview->cb_color_dim = color.dim;
4114 rview->cb_color_info = color.info |
4115 S_028C70_RAT(1) |
4116 S_028C70_RESOURCE_TYPE(res_type);
4117 rview->cb_color_pitch = color.pitch;
4118 rview->cb_color_slice = color.slice;
4119 rview->cb_color_view = color.view;
4120 rview->cb_color_attrib = color.attrib;
4121 rview->cb_color_fmask = color.fmask;
4122 rview->cb_color_fmask_slice = color.fmask_slice;
4123
4124 if (image->target != PIPE_BUFFER) {
4125 memset(&tex_params, 0, sizeof(tex_params));
4126 tex_params.pipe_format = iview->format;
4127 tex_params.force_level = 0;
4128 tex_params.width0 = image->width0;
4129 tex_params.height0 = image->height0;
4130 tex_params.first_level = iview->u.tex.level;
4131 tex_params.last_level = iview->u.tex.level;
4132 tex_params.first_layer = iview->u.tex.first_layer;
4133 tex_params.last_layer = iview->u.tex.last_layer;
4134 tex_params.target = image->target;
4135 tex_params.swizzle[0] = PIPE_SWIZZLE_X;
4136 tex_params.swizzle[1] = PIPE_SWIZZLE_Y;
4137 tex_params.swizzle[2] = PIPE_SWIZZLE_Z;
4138 tex_params.swizzle[3] = PIPE_SWIZZLE_W;
4139 evergreen_fill_tex_resource_words(rctx, &resource->b.b, &tex_params,
4140 &rview->skip_mip_address_reloc,
4141 rview->resource_words);
4142
4143 } else {
4144 memset(&buf_params, 0, sizeof(buf_params));
4145 buf_params.pipe_format = iview->format;
4146 buf_params.size = iview->u.buf.size;
4147 buf_params.offset = iview->u.buf.offset;
4148 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
4149 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
4150 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
4151 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
4152 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4153 &buf_params,
4154 &rview->skip_mip_address_reloc,
4155 rview->resource_words);
4156 }
4157 istate->enabled_mask |= (1 << i);
4158 }
4159
4160 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
4161 istate->dirty_buffer_constants = TRUE;
4162 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
4163 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
4164 R600_CONTEXT_FLUSH_AND_INV_CB_META;
4165
4166 if (old_mask != istate->enabled_mask)
4167 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4168
4169 if (rctx->cb_misc_state.nr_image_rats != util_bitcount(istate->enabled_mask)) {
4170 rctx->cb_misc_state.nr_image_rats = util_bitcount(istate->enabled_mask);
4171 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4172 }
4173
4174 r600_mark_atom_dirty(rctx, &istate->atom);
4175 }
4176
4177 void evergreen_init_state_functions(struct r600_context *rctx)
4178 {
4179 unsigned id = 1;
4180 unsigned i;
4181 /* !!!
4182 * To avoid GPU lockup registers must be emitted in a specific order
4183 * (no kidding ...). The order below is important and have been
4184 * partially inferred from analyzing fglrx command stream.
4185 *
4186 * Don't reorder atom without carefully checking the effect (GPU lockup
4187 * or piglit regression).
4188 * !!!
4189 */
4190 if (rctx->b.chip_class == EVERGREEN) {
4191 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
4192 rctx->config_state.dyn_gpr_enabled = true;
4193 }
4194 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
4195 r600_init_atom(rctx, &rctx->fragment_images.atom, id++, evergreen_emit_fragment_image_state, 0);
4196 r600_init_atom(rctx, &rctx->fragment_buffers.atom, id++, evergreen_emit_fragment_buffer_state, 0);
4197 /* shader const */
4198 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
4199 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
4200 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
4201 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
4202 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
4203 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
4204 /* shader program */
4205 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
4206 /* sampler */
4207 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
4208 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
4209 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
4210 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
4211 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
4212 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
4213 /* resources */
4214 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
4215 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
4216 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
4217 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
4218 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
4219 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
4220 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
4221 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
4222
4223 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
4224
4225 if (rctx->b.chip_class == EVERGREEN) {
4226 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
4227 } else {
4228 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
4229 }
4230 rctx->sample_mask.sample_mask = ~0;
4231
4232 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
4233 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
4234 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
4235 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
4236 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
4237 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
4238 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
4239 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
4240 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
4241 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9);
4242 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
4243 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
4244 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
4245 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
4246 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
4247 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
4248 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
4249 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
4250 for (i = 0; i < EG_NUM_HW_STAGES; i++)
4251 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
4252 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
4253 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
4254
4255 rctx->b.b.create_blend_state = evergreen_create_blend_state;
4256 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
4257 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
4258 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
4259 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
4260 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
4261 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
4262 rctx->b.b.set_min_samples = evergreen_set_min_samples;
4263 rctx->b.b.set_tess_state = evergreen_set_tess_state;
4264 rctx->b.b.set_hw_atomic_buffers = evergreen_set_hw_atomic_buffers;
4265 rctx->b.b.set_shader_images = evergreen_set_shader_images;
4266 rctx->b.b.set_shader_buffers = evergreen_set_shader_buffers;
4267 if (rctx->b.chip_class == EVERGREEN)
4268 rctx->b.b.get_sample_position = evergreen_get_sample_position;
4269 else
4270 rctx->b.b.get_sample_position = cayman_get_sample_position;
4271 rctx->b.dma_copy = evergreen_dma_copy;
4272
4273 evergreen_init_compute_state_functions(rctx);
4274 }
4275
4276 /**
4277 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
4278 *
4279 * The information about LDS and other non-compile-time parameters is then
4280 * written to the const buffer.
4281
4282 * const buffer contains -
4283 * uint32_t input_patch_size
4284 * uint32_t input_vertex_size
4285 * uint32_t num_tcs_input_cp
4286 * uint32_t num_tcs_output_cp;
4287 * uint32_t output_patch_size
4288 * uint32_t output_vertex_size
4289 * uint32_t output_patch0_offset
4290 * uint32_t perpatch_output_offset
4291 * and the same constbuf is bound to LS/HS/VS(ES).
4292 */
4293 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
4294 {
4295 struct pipe_constant_buffer constbuf = {0};
4296 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
4297 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
4298 unsigned num_tcs_input_cp = info->vertices_per_patch;
4299 unsigned num_tcs_outputs;
4300 unsigned num_tcs_output_cp;
4301 unsigned num_tcs_patch_outputs;
4302 unsigned num_tcs_inputs;
4303 unsigned input_vertex_size, output_vertex_size;
4304 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
4305 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
4306 uint32_t values[16];
4307 unsigned num_waves;
4308 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
4309 unsigned wave_divisor = (16 * num_pipes);
4310
4311 *num_patches = 1;
4312
4313 if (!rctx->tes_shader) {
4314 rctx->lds_alloc = 0;
4315 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4316 R600_LDS_INFO_CONST_BUFFER, NULL);
4317 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4318 R600_LDS_INFO_CONST_BUFFER, NULL);
4319 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4320 R600_LDS_INFO_CONST_BUFFER, NULL);
4321 return;
4322 }
4323
4324 if (rctx->lds_alloc != 0 &&
4325 rctx->last_ls == ls &&
4326 !rctx->tess_state_dirty &&
4327 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
4328 rctx->last_tcs == tcs)
4329 return;
4330
4331 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
4332
4333 if (rctx->tcs_shader) {
4334 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
4335 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
4336 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
4337 } else {
4338 num_tcs_outputs = num_tcs_inputs;
4339 num_tcs_output_cp = num_tcs_input_cp;
4340 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
4341 }
4342
4343 /* size in bytes */
4344 input_vertex_size = num_tcs_inputs * 16;
4345 output_vertex_size = num_tcs_outputs * 16;
4346
4347 input_patch_size = num_tcs_input_cp * input_vertex_size;
4348
4349 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
4350 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
4351
4352 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
4353 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
4354
4355 lds_size = output_patch0_offset + output_patch_size * *num_patches;
4356
4357 values[0] = input_patch_size;
4358 values[1] = input_vertex_size;
4359 values[2] = num_tcs_input_cp;
4360 values[3] = num_tcs_output_cp;
4361
4362 values[4] = output_patch_size;
4363 values[5] = output_vertex_size;
4364 values[6] = output_patch0_offset;
4365 values[7] = perpatch_output_offset;
4366
4367 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
4368 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
4369 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
4370
4371 rctx->lds_alloc = (lds_size | (num_waves << 14));
4372
4373 memcpy(&values[8], rctx->tess_state, 6 * sizeof(float));
4374 values[14] = 0;
4375 values[15] = 0;
4376
4377 rctx->tess_state_dirty = false;
4378 rctx->last_ls = ls;
4379 rctx->last_tcs = tcs;
4380 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
4381
4382 constbuf.user_buffer = values;
4383 constbuf.buffer_size = 16 * 4;
4384
4385 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4386 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4387 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4388 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4389 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4390 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4391 pipe_resource_reference(&constbuf.buffer, NULL);
4392 }
4393
4394 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
4395 const struct pipe_draw_info *info,
4396 unsigned num_patches)
4397 {
4398 unsigned num_output_cp;
4399
4400 if (!rctx->tes_shader)
4401 return 0;
4402
4403 num_output_cp = rctx->tcs_shader ?
4404 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
4405 info->vertices_per_patch;
4406
4407 return S_028B58_NUM_PATCHES(num_patches) |
4408 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
4409 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
4410 }
4411
4412 void evergreen_set_ls_hs_config(struct r600_context *rctx,
4413 struct radeon_winsys_cs *cs,
4414 uint32_t ls_hs_config)
4415 {
4416 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
4417 }
4418
4419 void evergreen_set_lds_alloc(struct r600_context *rctx,
4420 struct radeon_winsys_cs *cs,
4421 uint32_t lds_alloc)
4422 {
4423 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
4424 }
4425
4426 /* on evergreen if you are running tessellation you need to disable dynamic
4427 GPRs to workaround a hardware bug.*/
4428 bool evergreen_adjust_gprs(struct r600_context *rctx)
4429 {
4430 unsigned num_gprs[EG_NUM_HW_STAGES];
4431 unsigned def_gprs[EG_NUM_HW_STAGES];
4432 unsigned cur_gprs[EG_NUM_HW_STAGES];
4433 unsigned new_gprs[EG_NUM_HW_STAGES];
4434 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
4435 unsigned max_gprs;
4436 unsigned i;
4437 unsigned total_gprs;
4438 unsigned tmp[3];
4439 bool rework = false, set_default = false, set_dirty = false;
4440 max_gprs = 0;
4441 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4442 def_gprs[i] = rctx->default_gprs[i];
4443 max_gprs += def_gprs[i];
4444 }
4445 max_gprs += def_num_clause_temp_gprs * 2;
4446
4447 /* if we have no TESS and dyn gpr is enabled then do nothing. */
4448 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
4449 if (rctx->config_state.dyn_gpr_enabled)
4450 return true;
4451
4452 /* transition back to dyn gpr enabled state */
4453 rctx->config_state.dyn_gpr_enabled = true;
4454 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4455 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4456 return true;
4457 }
4458
4459
4460 /* gather required shader gprs */
4461 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4462 if (rctx->hw_shader_stages[i].shader)
4463 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
4464 else
4465 num_gprs[i] = 0;
4466 }
4467
4468 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4469 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4470 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4471 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4472 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4473 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4474
4475 total_gprs = 0;
4476 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4477 new_gprs[i] = num_gprs[i];
4478 total_gprs += num_gprs[i];
4479 }
4480
4481 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
4482 return false;
4483
4484 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4485 if (new_gprs[i] > cur_gprs[i]) {
4486 rework = true;
4487 break;
4488 }
4489 }
4490
4491 if (rctx->config_state.dyn_gpr_enabled) {
4492 set_dirty = true;
4493 rctx->config_state.dyn_gpr_enabled = false;
4494 }
4495
4496 if (rework) {
4497 set_default = true;
4498 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4499 if (new_gprs[i] > def_gprs[i])
4500 set_default = false;
4501 }
4502
4503 if (set_default) {
4504 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4505 new_gprs[i] = def_gprs[i];
4506 }
4507 } else {
4508 unsigned ps_value = max_gprs;
4509
4510 ps_value -= (def_num_clause_temp_gprs * 2);
4511 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
4512 ps_value -= new_gprs[i];
4513
4514 new_gprs[R600_HW_STAGE_PS] = ps_value;
4515 }
4516
4517 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
4518 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
4519 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
4520
4521 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
4522 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
4523
4524 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
4525 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
4526
4527 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
4528 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
4529 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
4530 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
4531 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
4532 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
4533 set_dirty = true;
4534 }
4535 }
4536
4537
4538 if (set_dirty) {
4539 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4540 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4541 }
4542 return true;
4543 }
4544
4545 #define AC_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
4546
4547 void eg_trace_emit(struct r600_context *rctx)
4548 {
4549 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4550 unsigned reloc;
4551
4552 if (rctx->b.chip_class < EVERGREEN)
4553 return;
4554
4555 /* This must be done after r600_need_cs_space. */
4556 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4557 (struct r600_resource*)rctx->trace_buf, RADEON_USAGE_WRITE,
4558 RADEON_PRIO_CP_DMA);
4559
4560 rctx->trace_id++;
4561 radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rctx->trace_buf,
4562 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
4563 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
4564 radeon_emit(cs, rctx->trace_buf->gpu_address);
4565 radeon_emit(cs, rctx->trace_buf->gpu_address >> 32 | MEM_WRITE_32_BITS | MEM_WRITE_CONFIRM);
4566 radeon_emit(cs, rctx->trace_id);
4567 radeon_emit(cs, 0);
4568 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4569 radeon_emit(cs, reloc);
4570 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4571 radeon_emit(cs, AC_ENCODE_TRACE_POINT(rctx->trace_id));
4572 }
4573
4574 static void evergreen_emit_set_append_cnt(struct r600_context *rctx,
4575 struct r600_shader_atomic *atomic,
4576 struct r600_resource *resource,
4577 uint32_t pkt_flags)
4578 {
4579 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4580 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4581 resource,
4582 RADEON_USAGE_READ,
4583 RADEON_PRIO_SHADER_RW_BUFFER);
4584 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4585 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4586
4587 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4 - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
4588
4589 radeon_emit(cs, PKT3(PKT3_SET_APPEND_CNT, 2, 0) | pkt_flags);
4590 radeon_emit(cs, (reg_val << 16) | 0x3);
4591 radeon_emit(cs, dst_offset & 0xfffffffc);
4592 radeon_emit(cs, (dst_offset >> 32) & 0xff);
4593 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4594 radeon_emit(cs, reloc);
4595 }
4596
4597 static void evergreen_emit_event_write_eos(struct r600_context *rctx,
4598 struct r600_shader_atomic *atomic,
4599 struct r600_resource *resource,
4600 uint32_t pkt_flags)
4601 {
4602 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4603 uint32_t event = EVENT_TYPE_PS_DONE;
4604 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4605 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4606 resource,
4607 RADEON_USAGE_WRITE,
4608 RADEON_PRIO_SHADER_RW_BUFFER);
4609 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4610 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4) >> 2;
4611
4612 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4613 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4614 radeon_emit(cs, (dst_offset) & 0xffffffff);
4615 radeon_emit(cs, (0 << 29) | ((dst_offset >> 32) & 0xff));
4616 radeon_emit(cs, reg_val);
4617 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4618 radeon_emit(cs, reloc);
4619 }
4620
4621 static void cayman_emit_event_write_eos(struct r600_context *rctx,
4622 struct r600_shader_atomic *atomic,
4623 struct r600_resource *resource,
4624 uint32_t pkt_flags)
4625 {
4626 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4627 uint32_t event = EVENT_TYPE_PS_DONE;
4628 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4629 resource,
4630 RADEON_USAGE_WRITE,
4631 RADEON_PRIO_SHADER_RW_BUFFER);
4632 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4633
4634 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4635 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4636 radeon_emit(cs, (dst_offset) & 0xffffffff);
4637 radeon_emit(cs, (1 << 29) | ((dst_offset >> 32) & 0xff));
4638 radeon_emit(cs, (atomic->hw_idx) | (1 << 16));
4639 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4640 radeon_emit(cs, reloc);
4641 }
4642
4643 /* writes count from a buffer into GDS */
4644 static void cayman_write_count_to_gds(struct r600_context *rctx,
4645 struct r600_shader_atomic *atomic,
4646 struct r600_resource *resource,
4647 uint32_t pkt_flags)
4648 {
4649 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4650 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4651 resource,
4652 RADEON_USAGE_READ,
4653 RADEON_PRIO_SHADER_RW_BUFFER);
4654 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4655
4656 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0) | pkt_flags);
4657 radeon_emit(cs, dst_offset & 0xffffffff);
4658 radeon_emit(cs, PKT3_CP_DMA_CP_SYNC | PKT3_CP_DMA_DST_SEL(1) | ((dst_offset >> 32) & 0xff));// GDS
4659 radeon_emit(cs, atomic->hw_idx * 4);
4660 radeon_emit(cs, 0);
4661 radeon_emit(cs, PKT3_CP_DMA_CMD_DAS | 4);
4662 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4663 radeon_emit(cs, reloc);
4664 }
4665
4666 bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
4667 struct r600_shader_atomic *combined_atomics,
4668 uint8_t *atomic_used_mask_p)
4669 {
4670 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4671 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4672 unsigned pkt_flags = 0;
4673 uint8_t atomic_used_mask = 0;
4674 int i, j, k;
4675
4676 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4677 uint8_t num_atomic_stage;
4678 struct r600_pipe_shader *pshader;
4679
4680 pshader = rctx->hw_shader_stages[i].shader;
4681 if (!pshader)
4682 continue;
4683
4684 num_atomic_stage = pshader->shader.nhwatomic_ranges;
4685 if (!num_atomic_stage)
4686 continue;
4687
4688 for (j = 0; j < num_atomic_stage; j++) {
4689 struct r600_shader_atomic *atomic = &pshader->shader.atomics[j];
4690 int natomics = atomic->end - atomic->start + 1;
4691
4692 for (k = 0; k < natomics; k++) {
4693 /* seen this in a previous stage */
4694 if (atomic_used_mask & (1u << (atomic->hw_idx + k)))
4695 continue;
4696
4697 combined_atomics[atomic->hw_idx + k].hw_idx = atomic->hw_idx + k;
4698 combined_atomics[atomic->hw_idx + k].buffer_id = atomic->buffer_id;
4699 combined_atomics[atomic->hw_idx + k].start = atomic->start + k;
4700 combined_atomics[atomic->hw_idx + k].end = combined_atomics[atomic->hw_idx + k].start + 1;
4701 atomic_used_mask |= (1u << (atomic->hw_idx + k));
4702 }
4703 }
4704 }
4705
4706 uint32_t mask = atomic_used_mask;
4707 while (mask) {
4708 unsigned atomic_index = u_bit_scan(&mask);
4709 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
4710 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
4711 assert(resource);
4712
4713 if (rctx->b.chip_class == CAYMAN)
4714 cayman_write_count_to_gds(rctx, atomic, resource, pkt_flags);
4715 else
4716 evergreen_emit_set_append_cnt(rctx, atomic, resource, pkt_flags);
4717 }
4718 *atomic_used_mask_p = atomic_used_mask;
4719 return true;
4720 }
4721
4722 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
4723 struct r600_shader_atomic *combined_atomics,
4724 uint8_t *atomic_used_mask_p)
4725 {
4726 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4727 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4728 uint32_t pkt_flags = 0;
4729 uint32_t event = EVENT_TYPE_PS_DONE;
4730 uint32_t mask = astate->enabled_mask;
4731 uint64_t dst_offset;
4732 unsigned reloc;
4733
4734 mask = *atomic_used_mask_p;
4735 if (!mask)
4736 return;
4737
4738 while (mask) {
4739 unsigned atomic_index = u_bit_scan(&mask);
4740 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
4741 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
4742 assert(resource);
4743
4744 if (rctx->b.chip_class == CAYMAN)
4745 cayman_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
4746 else
4747 evergreen_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
4748 }
4749
4750 ++rctx->append_fence_id;
4751 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4752 r600_resource(rctx->append_fence),
4753 RADEON_USAGE_READWRITE,
4754 RADEON_PRIO_SHADER_RW_BUFFER);
4755 dst_offset = r600_resource(rctx->append_fence)->gpu_address;
4756 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4757 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4758 radeon_emit(cs, dst_offset & 0xffffffff);
4759 radeon_emit(cs, (2 << 29) | ((dst_offset >> 32) & 0xff));
4760 radeon_emit(cs, rctx->append_fence_id);
4761 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4762 radeon_emit(cs, reloc);
4763
4764 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0) | pkt_flags);
4765 radeon_emit(cs, WAIT_REG_MEM_GEQUAL | WAIT_REG_MEM_MEMORY | (1 << 8));
4766 radeon_emit(cs, dst_offset & 0xffffffff);
4767 radeon_emit(cs, ((dst_offset >> 32) & 0xff));
4768 radeon_emit(cs, rctx->append_fence_id);
4769 radeon_emit(cs, 0xffffffff);
4770 radeon_emit(cs, 0xa);
4771 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4772 radeon_emit(cs, reloc);
4773 }