2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "evergreend.h"
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31 #include "evergreen_compute.h"
33 static uint32_t eg_num_banks(uint32_t nbanks
)
49 static unsigned eg_tile_split(unsigned tile_split
)
52 case 64: tile_split
= 0; break;
53 case 128: tile_split
= 1; break;
54 case 256: tile_split
= 2; break;
55 case 512: tile_split
= 3; break;
57 case 1024: tile_split
= 4; break;
58 case 2048: tile_split
= 5; break;
59 case 4096: tile_split
= 6; break;
64 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect
)
66 switch (macro_tile_aspect
) {
68 case 1: macro_tile_aspect
= 0; break;
69 case 2: macro_tile_aspect
= 1; break;
70 case 4: macro_tile_aspect
= 2; break;
71 case 8: macro_tile_aspect
= 3; break;
73 return macro_tile_aspect
;
76 static unsigned eg_bank_wh(unsigned bankwh
)
80 case 1: bankwh
= 0; break;
81 case 2: bankwh
= 1; break;
82 case 4: bankwh
= 2; break;
83 case 8: bankwh
= 3; break;
88 static uint32_t r600_translate_blend_function(int blend_func
)
92 return V_028780_COMB_DST_PLUS_SRC
;
93 case PIPE_BLEND_SUBTRACT
:
94 return V_028780_COMB_SRC_MINUS_DST
;
95 case PIPE_BLEND_REVERSE_SUBTRACT
:
96 return V_028780_COMB_DST_MINUS_SRC
;
98 return V_028780_COMB_MIN_DST_SRC
;
100 return V_028780_COMB_MAX_DST_SRC
;
102 R600_ERR("Unknown blend function %d\n", blend_func
);
109 static uint32_t r600_translate_blend_factor(int blend_fact
)
111 switch (blend_fact
) {
112 case PIPE_BLENDFACTOR_ONE
:
113 return V_028780_BLEND_ONE
;
114 case PIPE_BLENDFACTOR_SRC_COLOR
:
115 return V_028780_BLEND_SRC_COLOR
;
116 case PIPE_BLENDFACTOR_SRC_ALPHA
:
117 return V_028780_BLEND_SRC_ALPHA
;
118 case PIPE_BLENDFACTOR_DST_ALPHA
:
119 return V_028780_BLEND_DST_ALPHA
;
120 case PIPE_BLENDFACTOR_DST_COLOR
:
121 return V_028780_BLEND_DST_COLOR
;
122 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
123 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
124 case PIPE_BLENDFACTOR_CONST_COLOR
:
125 return V_028780_BLEND_CONST_COLOR
;
126 case PIPE_BLENDFACTOR_CONST_ALPHA
:
127 return V_028780_BLEND_CONST_ALPHA
;
128 case PIPE_BLENDFACTOR_ZERO
:
129 return V_028780_BLEND_ZERO
;
130 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
131 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
132 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
133 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
134 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
135 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
136 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
137 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
138 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
139 return V_028780_BLEND_ONE_MINUS_CONST_COLOR
;
140 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
141 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA
;
142 case PIPE_BLENDFACTOR_SRC1_COLOR
:
143 return V_028780_BLEND_SRC1_COLOR
;
144 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
145 return V_028780_BLEND_SRC1_ALPHA
;
146 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
147 return V_028780_BLEND_INV_SRC1_COLOR
;
148 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
149 return V_028780_BLEND_INV_SRC1_ALPHA
;
151 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
158 static unsigned r600_tex_dim(unsigned dim
)
162 case PIPE_TEXTURE_1D
:
163 return V_030000_SQ_TEX_DIM_1D
;
164 case PIPE_TEXTURE_1D_ARRAY
:
165 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
166 case PIPE_TEXTURE_2D
:
167 case PIPE_TEXTURE_RECT
:
168 return V_030000_SQ_TEX_DIM_2D
;
169 case PIPE_TEXTURE_2D_ARRAY
:
170 return V_030000_SQ_TEX_DIM_2D_ARRAY
;
171 case PIPE_TEXTURE_3D
:
172 return V_030000_SQ_TEX_DIM_3D
;
173 case PIPE_TEXTURE_CUBE
:
174 return V_030000_SQ_TEX_DIM_CUBEMAP
;
178 static uint32_t r600_translate_dbformat(enum pipe_format format
)
181 case PIPE_FORMAT_Z16_UNORM
:
182 return V_028040_Z_16
;
183 case PIPE_FORMAT_Z24X8_UNORM
:
184 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
185 return V_028040_Z_24
;
186 case PIPE_FORMAT_Z32_FLOAT
:
187 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
188 return V_028040_Z_32_FLOAT
;
194 static uint32_t r600_translate_colorswap(enum pipe_format format
)
198 case PIPE_FORMAT_L4A4_UNORM
:
199 case PIPE_FORMAT_A4R4_UNORM
:
200 return V_028C70_SWAP_ALT
;
202 case PIPE_FORMAT_A8_UNORM
:
203 case PIPE_FORMAT_A8_SNORM
:
204 case PIPE_FORMAT_A8_UINT
:
205 case PIPE_FORMAT_A8_SINT
:
206 case PIPE_FORMAT_A16_UNORM
:
207 case PIPE_FORMAT_A16_SNORM
:
208 case PIPE_FORMAT_A16_UINT
:
209 case PIPE_FORMAT_A16_SINT
:
210 case PIPE_FORMAT_A16_FLOAT
:
211 case PIPE_FORMAT_A32_UINT
:
212 case PIPE_FORMAT_A32_SINT
:
213 case PIPE_FORMAT_A32_FLOAT
:
214 case PIPE_FORMAT_R4A4_UNORM
:
215 return V_028C70_SWAP_ALT_REV
;
216 case PIPE_FORMAT_I8_UNORM
:
217 case PIPE_FORMAT_I8_SNORM
:
218 case PIPE_FORMAT_I8_UINT
:
219 case PIPE_FORMAT_I8_SINT
:
220 case PIPE_FORMAT_I16_UNORM
:
221 case PIPE_FORMAT_I16_SNORM
:
222 case PIPE_FORMAT_I16_UINT
:
223 case PIPE_FORMAT_I16_SINT
:
224 case PIPE_FORMAT_I16_FLOAT
:
225 case PIPE_FORMAT_I32_UINT
:
226 case PIPE_FORMAT_I32_SINT
:
227 case PIPE_FORMAT_I32_FLOAT
:
228 case PIPE_FORMAT_L8_UNORM
:
229 case PIPE_FORMAT_L8_SNORM
:
230 case PIPE_FORMAT_L8_UINT
:
231 case PIPE_FORMAT_L8_SINT
:
232 case PIPE_FORMAT_L8_SRGB
:
233 case PIPE_FORMAT_L16_UNORM
:
234 case PIPE_FORMAT_L16_SNORM
:
235 case PIPE_FORMAT_L16_UINT
:
236 case PIPE_FORMAT_L16_SINT
:
237 case PIPE_FORMAT_L16_FLOAT
:
238 case PIPE_FORMAT_L32_UINT
:
239 case PIPE_FORMAT_L32_SINT
:
240 case PIPE_FORMAT_L32_FLOAT
:
241 case PIPE_FORMAT_R8_UNORM
:
242 case PIPE_FORMAT_R8_SNORM
:
243 case PIPE_FORMAT_R8_UINT
:
244 case PIPE_FORMAT_R8_SINT
:
245 return V_028C70_SWAP_STD
;
247 /* 16-bit buffers. */
248 case PIPE_FORMAT_B5G6R5_UNORM
:
249 return V_028C70_SWAP_STD_REV
;
251 case PIPE_FORMAT_B5G5R5A1_UNORM
:
252 case PIPE_FORMAT_B5G5R5X1_UNORM
:
253 return V_028C70_SWAP_ALT
;
255 case PIPE_FORMAT_B4G4R4A4_UNORM
:
256 case PIPE_FORMAT_B4G4R4X4_UNORM
:
257 return V_028C70_SWAP_ALT
;
259 case PIPE_FORMAT_Z16_UNORM
:
260 return V_028C70_SWAP_STD
;
262 case PIPE_FORMAT_L8A8_UNORM
:
263 case PIPE_FORMAT_L8A8_SNORM
:
264 case PIPE_FORMAT_L8A8_UINT
:
265 case PIPE_FORMAT_L8A8_SINT
:
266 case PIPE_FORMAT_L8A8_SRGB
:
267 case PIPE_FORMAT_L16A16_UNORM
:
268 case PIPE_FORMAT_L16A16_SNORM
:
269 case PIPE_FORMAT_L16A16_UINT
:
270 case PIPE_FORMAT_L16A16_SINT
:
271 case PIPE_FORMAT_L16A16_FLOAT
:
272 case PIPE_FORMAT_L32A32_UINT
:
273 case PIPE_FORMAT_L32A32_SINT
:
274 case PIPE_FORMAT_L32A32_FLOAT
:
275 return V_028C70_SWAP_ALT
;
276 case PIPE_FORMAT_R8G8_UNORM
:
277 case PIPE_FORMAT_R8G8_SNORM
:
278 case PIPE_FORMAT_R8G8_UINT
:
279 case PIPE_FORMAT_R8G8_SINT
:
280 return V_028C70_SWAP_STD
;
282 case PIPE_FORMAT_R16_UNORM
:
283 case PIPE_FORMAT_R16_SNORM
:
284 case PIPE_FORMAT_R16_UINT
:
285 case PIPE_FORMAT_R16_SINT
:
286 case PIPE_FORMAT_R16_FLOAT
:
287 return V_028C70_SWAP_STD
;
289 /* 32-bit buffers. */
290 case PIPE_FORMAT_A8B8G8R8_SRGB
:
291 return V_028C70_SWAP_STD_REV
;
292 case PIPE_FORMAT_B8G8R8A8_SRGB
:
293 return V_028C70_SWAP_ALT
;
295 case PIPE_FORMAT_B8G8R8A8_UNORM
:
296 case PIPE_FORMAT_B8G8R8X8_UNORM
:
297 return V_028C70_SWAP_ALT
;
299 case PIPE_FORMAT_A8R8G8B8_UNORM
:
300 case PIPE_FORMAT_X8R8G8B8_UNORM
:
301 return V_028C70_SWAP_ALT_REV
;
302 case PIPE_FORMAT_R8G8B8A8_SNORM
:
303 case PIPE_FORMAT_R8G8B8A8_UNORM
:
304 case PIPE_FORMAT_R8G8B8A8_SINT
:
305 case PIPE_FORMAT_R8G8B8A8_UINT
:
306 case PIPE_FORMAT_R8G8B8X8_UNORM
:
307 return V_028C70_SWAP_STD
;
309 case PIPE_FORMAT_A8B8G8R8_UNORM
:
310 case PIPE_FORMAT_X8B8G8R8_UNORM
:
311 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
312 return V_028C70_SWAP_STD_REV
;
314 case PIPE_FORMAT_Z24X8_UNORM
:
315 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
316 return V_028C70_SWAP_STD
;
318 case PIPE_FORMAT_X8Z24_UNORM
:
319 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
320 return V_028C70_SWAP_STD
;
322 case PIPE_FORMAT_R10G10B10A2_UNORM
:
323 case PIPE_FORMAT_R10G10B10X2_SNORM
:
324 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
325 return V_028C70_SWAP_STD
;
327 case PIPE_FORMAT_B10G10R10A2_UNORM
:
328 case PIPE_FORMAT_B10G10R10A2_UINT
:
329 return V_028C70_SWAP_ALT
;
331 case PIPE_FORMAT_R11G11B10_FLOAT
:
332 case PIPE_FORMAT_R32_FLOAT
:
333 case PIPE_FORMAT_R32_UINT
:
334 case PIPE_FORMAT_R32_SINT
:
335 case PIPE_FORMAT_Z32_FLOAT
:
336 case PIPE_FORMAT_R16G16_FLOAT
:
337 case PIPE_FORMAT_R16G16_UNORM
:
338 case PIPE_FORMAT_R16G16_SNORM
:
339 case PIPE_FORMAT_R16G16_UINT
:
340 case PIPE_FORMAT_R16G16_SINT
:
341 case PIPE_FORMAT_R16G16B16_FLOAT
:
342 case PIPE_FORMAT_R32G32B32_FLOAT
:
343 return V_028C70_SWAP_STD
;
345 /* 64-bit buffers. */
346 case PIPE_FORMAT_R32G32_FLOAT
:
347 case PIPE_FORMAT_R32G32_UINT
:
348 case PIPE_FORMAT_R32G32_SINT
:
349 case PIPE_FORMAT_R16G16B16A16_UNORM
:
350 case PIPE_FORMAT_R16G16B16A16_SNORM
:
351 case PIPE_FORMAT_R16G16B16A16_UINT
:
352 case PIPE_FORMAT_R16G16B16A16_SINT
:
353 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
354 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
356 /* 128-bit buffers. */
357 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
358 case PIPE_FORMAT_R32G32B32A32_SNORM
:
359 case PIPE_FORMAT_R32G32B32A32_UNORM
:
360 case PIPE_FORMAT_R32G32B32A32_SINT
:
361 case PIPE_FORMAT_R32G32B32A32_UINT
:
362 return V_028C70_SWAP_STD
;
364 R600_ERR("unsupported colorswap format %d\n", format
);
370 static uint32_t r600_translate_colorformat(enum pipe_format format
)
374 case PIPE_FORMAT_A8_UNORM
:
375 case PIPE_FORMAT_A8_SNORM
:
376 case PIPE_FORMAT_A8_UINT
:
377 case PIPE_FORMAT_A8_SINT
:
378 case PIPE_FORMAT_I8_UNORM
:
379 case PIPE_FORMAT_I8_SNORM
:
380 case PIPE_FORMAT_I8_UINT
:
381 case PIPE_FORMAT_I8_SINT
:
382 case PIPE_FORMAT_L8_UNORM
:
383 case PIPE_FORMAT_L8_SNORM
:
384 case PIPE_FORMAT_L8_UINT
:
385 case PIPE_FORMAT_L8_SINT
:
386 case PIPE_FORMAT_L8_SRGB
:
387 case PIPE_FORMAT_R8_UNORM
:
388 case PIPE_FORMAT_R8_SNORM
:
389 case PIPE_FORMAT_R8_UINT
:
390 case PIPE_FORMAT_R8_SINT
:
391 return V_028C70_COLOR_8
;
393 /* 16-bit buffers. */
394 case PIPE_FORMAT_B5G6R5_UNORM
:
395 return V_028C70_COLOR_5_6_5
;
397 case PIPE_FORMAT_B5G5R5A1_UNORM
:
398 case PIPE_FORMAT_B5G5R5X1_UNORM
:
399 return V_028C70_COLOR_1_5_5_5
;
401 case PIPE_FORMAT_B4G4R4A4_UNORM
:
402 case PIPE_FORMAT_B4G4R4X4_UNORM
:
403 return V_028C70_COLOR_4_4_4_4
;
405 case PIPE_FORMAT_Z16_UNORM
:
406 return V_028C70_COLOR_16
;
408 case PIPE_FORMAT_L8A8_UNORM
:
409 case PIPE_FORMAT_L8A8_SNORM
:
410 case PIPE_FORMAT_L8A8_UINT
:
411 case PIPE_FORMAT_L8A8_SINT
:
412 case PIPE_FORMAT_L8A8_SRGB
:
413 case PIPE_FORMAT_R8G8_UNORM
:
414 case PIPE_FORMAT_R8G8_SNORM
:
415 case PIPE_FORMAT_R8G8_UINT
:
416 case PIPE_FORMAT_R8G8_SINT
:
417 return V_028C70_COLOR_8_8
;
419 case PIPE_FORMAT_R16_UNORM
:
420 case PIPE_FORMAT_R16_SNORM
:
421 case PIPE_FORMAT_R16_UINT
:
422 case PIPE_FORMAT_R16_SINT
:
423 case PIPE_FORMAT_A16_UNORM
:
424 case PIPE_FORMAT_A16_SNORM
:
425 case PIPE_FORMAT_A16_UINT
:
426 case PIPE_FORMAT_A16_SINT
:
427 case PIPE_FORMAT_L16_UNORM
:
428 case PIPE_FORMAT_L16_SNORM
:
429 case PIPE_FORMAT_L16_UINT
:
430 case PIPE_FORMAT_L16_SINT
:
431 case PIPE_FORMAT_I16_UNORM
:
432 case PIPE_FORMAT_I16_SNORM
:
433 case PIPE_FORMAT_I16_UINT
:
434 case PIPE_FORMAT_I16_SINT
:
435 return V_028C70_COLOR_16
;
437 case PIPE_FORMAT_R16_FLOAT
:
438 case PIPE_FORMAT_A16_FLOAT
:
439 case PIPE_FORMAT_L16_FLOAT
:
440 case PIPE_FORMAT_I16_FLOAT
:
441 return V_028C70_COLOR_16_FLOAT
;
443 /* 32-bit buffers. */
444 case PIPE_FORMAT_A8B8G8R8_SRGB
:
445 case PIPE_FORMAT_A8B8G8R8_UNORM
:
446 case PIPE_FORMAT_A8R8G8B8_UNORM
:
447 case PIPE_FORMAT_B8G8R8A8_SRGB
:
448 case PIPE_FORMAT_B8G8R8A8_UNORM
:
449 case PIPE_FORMAT_B8G8R8X8_UNORM
:
450 case PIPE_FORMAT_R8G8B8A8_SNORM
:
451 case PIPE_FORMAT_R8G8B8A8_UNORM
:
452 case PIPE_FORMAT_R8G8B8X8_UNORM
:
453 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
454 case PIPE_FORMAT_X8B8G8R8_UNORM
:
455 case PIPE_FORMAT_X8R8G8B8_UNORM
:
456 case PIPE_FORMAT_R8G8B8_UNORM
:
457 case PIPE_FORMAT_R8G8B8A8_SINT
:
458 case PIPE_FORMAT_R8G8B8A8_UINT
:
459 return V_028C70_COLOR_8_8_8_8
;
461 case PIPE_FORMAT_R10G10B10A2_UNORM
:
462 case PIPE_FORMAT_R10G10B10X2_SNORM
:
463 case PIPE_FORMAT_B10G10R10A2_UNORM
:
464 case PIPE_FORMAT_B10G10R10A2_UINT
:
465 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
466 return V_028C70_COLOR_2_10_10_10
;
468 case PIPE_FORMAT_Z24X8_UNORM
:
469 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
470 return V_028C70_COLOR_8_24
;
472 case PIPE_FORMAT_X8Z24_UNORM
:
473 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
474 return V_028C70_COLOR_24_8
;
476 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
477 return V_028C70_COLOR_X24_8_32_FLOAT
;
479 case PIPE_FORMAT_R32_UINT
:
480 case PIPE_FORMAT_R32_SINT
:
481 case PIPE_FORMAT_A32_UINT
:
482 case PIPE_FORMAT_A32_SINT
:
483 case PIPE_FORMAT_L32_UINT
:
484 case PIPE_FORMAT_L32_SINT
:
485 case PIPE_FORMAT_I32_UINT
:
486 case PIPE_FORMAT_I32_SINT
:
487 return V_028C70_COLOR_32
;
489 case PIPE_FORMAT_R32_FLOAT
:
490 case PIPE_FORMAT_A32_FLOAT
:
491 case PIPE_FORMAT_L32_FLOAT
:
492 case PIPE_FORMAT_I32_FLOAT
:
493 case PIPE_FORMAT_Z32_FLOAT
:
494 return V_028C70_COLOR_32_FLOAT
;
496 case PIPE_FORMAT_R16G16_FLOAT
:
497 case PIPE_FORMAT_L16A16_FLOAT
:
498 return V_028C70_COLOR_16_16_FLOAT
;
500 case PIPE_FORMAT_R16G16_UNORM
:
501 case PIPE_FORMAT_R16G16_SNORM
:
502 case PIPE_FORMAT_R16G16_UINT
:
503 case PIPE_FORMAT_R16G16_SINT
:
504 case PIPE_FORMAT_L16A16_UNORM
:
505 case PIPE_FORMAT_L16A16_SNORM
:
506 case PIPE_FORMAT_L16A16_UINT
:
507 case PIPE_FORMAT_L16A16_SINT
:
508 return V_028C70_COLOR_16_16
;
510 case PIPE_FORMAT_R11G11B10_FLOAT
:
511 return V_028C70_COLOR_10_11_11_FLOAT
;
513 /* 64-bit buffers. */
514 case PIPE_FORMAT_R16G16B16A16_UINT
:
515 case PIPE_FORMAT_R16G16B16A16_SINT
:
516 case PIPE_FORMAT_R16G16B16A16_UNORM
:
517 case PIPE_FORMAT_R16G16B16A16_SNORM
:
518 return V_028C70_COLOR_16_16_16_16
;
520 case PIPE_FORMAT_R16G16B16_FLOAT
:
521 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
522 return V_028C70_COLOR_16_16_16_16_FLOAT
;
524 case PIPE_FORMAT_R32G32_FLOAT
:
525 case PIPE_FORMAT_L32A32_FLOAT
:
526 return V_028C70_COLOR_32_32_FLOAT
;
528 case PIPE_FORMAT_R32G32_SINT
:
529 case PIPE_FORMAT_R32G32_UINT
:
530 case PIPE_FORMAT_L32A32_UINT
:
531 case PIPE_FORMAT_L32A32_SINT
:
532 return V_028C70_COLOR_32_32
;
534 /* 96-bit buffers. */
535 case PIPE_FORMAT_R32G32B32_FLOAT
:
536 return V_028C70_COLOR_32_32_32_FLOAT
;
538 /* 128-bit buffers. */
539 case PIPE_FORMAT_R32G32B32A32_SNORM
:
540 case PIPE_FORMAT_R32G32B32A32_UNORM
:
541 case PIPE_FORMAT_R32G32B32A32_SINT
:
542 case PIPE_FORMAT_R32G32B32A32_UINT
:
543 return V_028C70_COLOR_32_32_32_32
;
544 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
545 return V_028C70_COLOR_32_32_32_32_FLOAT
;
548 case PIPE_FORMAT_UYVY
:
549 case PIPE_FORMAT_YUYV
:
551 return ~0U; /* Unsupported. */
555 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
557 if (R600_BIG_ENDIAN
) {
558 switch(colorformat
) {
561 case V_028C70_COLOR_8
:
564 /* 16-bit buffers. */
565 case V_028C70_COLOR_5_6_5
:
566 case V_028C70_COLOR_1_5_5_5
:
567 case V_028C70_COLOR_4_4_4_4
:
568 case V_028C70_COLOR_16
:
569 case V_028C70_COLOR_8_8
:
572 /* 32-bit buffers. */
573 case V_028C70_COLOR_8_8_8_8
:
574 case V_028C70_COLOR_2_10_10_10
:
575 case V_028C70_COLOR_8_24
:
576 case V_028C70_COLOR_24_8
:
577 case V_028C70_COLOR_32_FLOAT
:
578 case V_028C70_COLOR_16_16_FLOAT
:
579 case V_028C70_COLOR_16_16
:
582 /* 64-bit buffers. */
583 case V_028C70_COLOR_16_16_16_16
:
584 case V_028C70_COLOR_16_16_16_16_FLOAT
:
587 case V_028C70_COLOR_32_32_FLOAT
:
588 case V_028C70_COLOR_32_32
:
589 case V_028C70_COLOR_X24_8_32_FLOAT
:
592 /* 96-bit buffers. */
593 case V_028C70_COLOR_32_32_32_FLOAT
:
594 /* 128-bit buffers. */
595 case V_028C70_COLOR_32_32_32_32_FLOAT
:
596 case V_028C70_COLOR_32_32_32_32
:
599 return ENDIAN_NONE
; /* Unsupported. */
606 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
608 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
611 static bool r600_is_colorbuffer_format_supported(enum pipe_format format
)
613 return r600_translate_colorformat(format
) != ~0U &&
614 r600_translate_colorswap(format
) != ~0U;
617 static bool r600_is_zs_format_supported(enum pipe_format format
)
619 return r600_translate_dbformat(format
) != ~0U;
622 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
623 enum pipe_format format
,
624 enum pipe_texture_target target
,
625 unsigned sample_count
,
630 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
631 R600_ERR("r600: unsupported texture type %d\n", target
);
635 if (!util_format_is_supported(format
, usage
))
639 if (sample_count
> 1)
642 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
643 r600_is_sampler_format_supported(screen
, format
)) {
644 retval
|= PIPE_BIND_SAMPLER_VIEW
;
647 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
648 PIPE_BIND_DISPLAY_TARGET
|
650 PIPE_BIND_SHARED
)) &&
651 r600_is_colorbuffer_format_supported(format
)) {
653 (PIPE_BIND_RENDER_TARGET
|
654 PIPE_BIND_DISPLAY_TARGET
|
659 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
660 r600_is_zs_format_supported(format
)) {
661 retval
|= PIPE_BIND_DEPTH_STENCIL
;
664 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
665 r600_is_vertex_format_supported(format
)) {
666 retval
|= PIPE_BIND_VERTEX_BUFFER
;
669 if (usage
& PIPE_BIND_TRANSFER_READ
)
670 retval
|= PIPE_BIND_TRANSFER_READ
;
671 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
672 retval
|= PIPE_BIND_TRANSFER_WRITE
;
674 return retval
== usage
;
677 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
678 const struct pipe_blend_state
*state
)
680 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
681 struct r600_pipe_blend
*blend
= CALLOC_STRUCT(r600_pipe_blend
);
682 struct r600_pipe_state
*rstate
;
683 uint32_t color_control
, target_mask
;
684 /* XXX there is more then 8 framebuffer */
685 unsigned blend_cntl
[8];
691 rstate
= &blend
->rstate
;
693 rstate
->id
= R600_PIPE_STATE_BLEND
;
696 color_control
= S_028808_MODE(1);
697 if (state
->logicop_enable
) {
698 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
700 color_control
|= (0xcc << 16);
702 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
703 if (state
->independent_blend_enable
) {
704 for (int i
= 0; i
< 8; i
++) {
705 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
708 for (int i
= 0; i
< 8; i
++) {
709 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
712 blend
->cb_target_mask
= target_mask
;
714 r600_pipe_state_add_reg(rstate
, R_028808_CB_COLOR_CONTROL
,
716 /* only have dual source on MRT0 */
717 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
718 for (int i
= 0; i
< 8; i
++) {
719 /* state->rt entries > 0 only written if independent blending */
720 const int j
= state
->independent_blend_enable
? i
: 0;
722 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
723 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
724 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
725 unsigned eqA
= state
->rt
[j
].alpha_func
;
726 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
727 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
730 if (!state
->rt
[j
].blend_enable
)
733 blend_cntl
[i
] |= S_028780_BLEND_CONTROL_ENABLE(1);
734 blend_cntl
[i
] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
735 blend_cntl
[i
] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
736 blend_cntl
[i
] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
738 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
739 blend_cntl
[i
] |= S_028780_SEPARATE_ALPHA_BLEND(1);
740 blend_cntl
[i
] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
741 blend_cntl
[i
] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
742 blend_cntl
[i
] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
745 for (int i
= 0; i
< 8; i
++) {
746 r600_pipe_state_add_reg(rstate
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
[i
]);
752 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
753 const struct pipe_depth_stencil_alpha_state
*state
)
755 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
756 struct r600_pipe_dsa
*dsa
= CALLOC_STRUCT(r600_pipe_dsa
);
757 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
758 unsigned db_render_control
;
759 struct r600_pipe_state
*rstate
;
765 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
766 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
767 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
768 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
770 rstate
= &dsa
->rstate
;
772 rstate
->id
= R600_PIPE_STATE_DSA
;
773 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
774 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
775 S_028800_ZFUNC(state
->depth
.func
);
778 if (state
->stencil
[0].enabled
) {
779 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
780 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
781 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
782 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
783 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
785 if (state
->stencil
[1].enabled
) {
786 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
787 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
788 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
789 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
790 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
795 alpha_test_control
= 0;
797 if (state
->alpha
.enabled
) {
798 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
799 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
800 alpha_ref
= fui(state
->alpha
.ref_value
);
802 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
803 dsa
->alpha_ref
= alpha_ref
;
806 db_render_control
= 0;
807 r600_pipe_state_add_reg(rstate
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
808 r600_pipe_state_add_reg(rstate
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
812 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
813 const struct pipe_rasterizer_state
*state
)
815 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
816 struct r600_pipe_rasterizer
*rs
= CALLOC_STRUCT(r600_pipe_rasterizer
);
817 struct r600_pipe_state
*rstate
;
819 unsigned prov_vtx
= 1, polygon_dual_mode
;
820 float psize_min
, psize_max
;
826 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
827 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
829 if (state
->flatshade_first
)
832 rstate
= &rs
->rstate
;
833 rs
->flatshade
= state
->flatshade
;
834 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
835 rs
->two_side
= state
->light_twoside
;
836 rs
->clip_plane_enable
= state
->clip_plane_enable
;
837 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
838 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
839 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
840 rs
->pa_cl_clip_cntl
=
841 S_028810_PS_UCP_MODE(3) |
842 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
843 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
844 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
847 rs
->offset_units
= state
->offset_units
;
848 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
850 rstate
->id
= R600_PIPE_STATE_RASTERIZER
;
851 tmp
= S_0286D4_FLAT_SHADE_ENA(1);
852 if (state
->sprite_coord_enable
) {
853 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
854 S_0286D4_PNT_SPRITE_OVRD_X(2) |
855 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
856 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
857 S_0286D4_PNT_SPRITE_OVRD_W(1);
858 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
859 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
862 r600_pipe_state_add_reg(rstate
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
);
864 /* point size 12.4 fixed point */
865 tmp
= (unsigned)(state
->point_size
* 8.0);
866 r600_pipe_state_add_reg(rstate
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
868 if (state
->point_size_per_vertex
) {
869 psize_min
= util_get_min_point_size(state
);
872 /* Force the point size to be as if the vertex output was disabled. */
873 psize_min
= state
->point_size
;
874 psize_max
= state
->point_size
;
876 /* Divide by two, because 0.5 = 1 pixel. */
877 r600_pipe_state_add_reg(rstate
, R_028A04_PA_SU_POINT_MINMAX
,
878 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
879 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
881 tmp
= (unsigned)state
->line_width
* 8;
882 r600_pipe_state_add_reg(rstate
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
883 r600_pipe_state_add_reg(rstate
, R_028A48_PA_SC_MODE_CNTL_0
,
884 S_028A48_VPORT_SCISSOR_ENABLE(state
->scissor
) |
885 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
));
887 if (rctx
->chip_class
== CAYMAN
) {
888 r600_pipe_state_add_reg(rstate
, CM_R_028BE4_PA_SU_VTX_CNTL
,
889 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
));
891 r600_pipe_state_add_reg(rstate
, R_028C08_PA_SU_VTX_CNTL
,
892 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
));
894 r600_pipe_state_add_reg(rstate
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
895 r600_pipe_state_add_reg(rstate
, R_028814_PA_SU_SC_MODE_CNTL
,
896 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
897 S_028814_CULL_FRONT(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
898 S_028814_CULL_BACK(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
899 S_028814_FACE(!state
->front_ccw
) |
900 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
901 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
902 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
903 S_028814_POLY_MODE(polygon_dual_mode
) |
904 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
905 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
906 r600_pipe_state_add_reg(rstate
, R_028350_SX_MISC
, S_028350_MULTIPASS(state
->rasterizer_discard
));
910 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
911 const struct pipe_sampler_state
*state
)
913 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
915 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
917 if (rstate
== NULL
) {
921 rstate
->id
= R600_PIPE_STATE_SAMPLER
;
922 util_pack_color(state
->border_color
.f
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
923 r600_pipe_state_add_reg_noblock(rstate
, R_03C000_SQ_TEX_SAMPLER_WORD0_0
,
924 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
925 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
926 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
927 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
928 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
929 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
930 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
931 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
932 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0), NULL
, 0);
933 r600_pipe_state_add_reg_noblock(rstate
, R_03C004_SQ_TEX_SAMPLER_WORD1_0
,
934 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
935 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)),
937 r600_pipe_state_add_reg_noblock(rstate
, R_03C008_SQ_TEX_SAMPLER_WORD2_0
,
938 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
939 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
944 r600_pipe_state_add_reg_noblock(rstate
, R_00A404_TD_PS_SAMPLER0_BORDER_RED
, fui(state
->border_color
.f
[0]), NULL
, 0);
945 r600_pipe_state_add_reg_noblock(rstate
, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN
, fui(state
->border_color
.f
[1]), NULL
, 0);
946 r600_pipe_state_add_reg_noblock(rstate
, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE
, fui(state
->border_color
.f
[2]), NULL
, 0);
947 r600_pipe_state_add_reg_noblock(rstate
, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA
, fui(state
->border_color
.f
[3]), NULL
, 0);
952 static struct pipe_sampler_view
*evergreen_create_sampler_view(struct pipe_context
*ctx
,
953 struct pipe_resource
*texture
,
954 const struct pipe_sampler_view
*state
)
956 struct r600_screen
*rscreen
= (struct r600_screen
*)ctx
->screen
;
957 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
958 struct r600_pipe_resource_state
*rstate
;
959 struct r600_resource_texture
*tmp
= (struct r600_resource_texture
*)texture
;
960 unsigned format
, endian
;
961 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
962 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
963 unsigned height
, depth
, width
;
964 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
968 rstate
= &view
->state
;
970 /* initialize base object */
972 view
->base
.texture
= NULL
;
973 pipe_reference(NULL
, &texture
->reference
);
974 view
->base
.texture
= texture
;
975 view
->base
.reference
.count
= 1;
976 view
->base
.context
= ctx
;
978 swizzle
[0] = state
->swizzle_r
;
979 swizzle
[1] = state
->swizzle_g
;
980 swizzle
[2] = state
->swizzle_b
;
981 swizzle
[3] = state
->swizzle_a
;
983 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
985 &word4
, &yuv_format
);
990 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
991 r600_init_flushed_depth_texture(ctx
, texture
);
992 tmp
= tmp
->flushed_depth_texture
;
999 endian
= r600_colorformat_endian_swap(format
);
1001 if (!rscreen
->use_surface_alloc
) {
1002 height
= texture
->height0
;
1003 depth
= texture
->depth0
;
1004 width
= texture
->width0
;
1005 pitch
= align(tmp
->pitch_in_blocks
[0] *
1006 util_format_get_blockwidth(state
->format
), 8);
1007 array_mode
= tmp
->array_mode
[0];
1008 tile_type
= tmp
->tile_type
;
1014 width
= tmp
->surface
.level
[0].npix_x
;
1015 height
= tmp
->surface
.level
[0].npix_y
;
1016 depth
= tmp
->surface
.level
[0].npix_z
;
1017 pitch
= tmp
->surface
.level
[0].nblk_x
* util_format_get_blockwidth(state
->format
);
1018 tile_type
= tmp
->tile_type
;
1020 switch (tmp
->surface
.level
[0].mode
) {
1021 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1022 array_mode
= V_028C70_ARRAY_LINEAR_ALIGNED
;
1024 case RADEON_SURF_MODE_2D
:
1025 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1027 case RADEON_SURF_MODE_1D
:
1028 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1030 case RADEON_SURF_MODE_LINEAR
:
1032 array_mode
= V_028C70_ARRAY_LINEAR_GENERAL
;
1035 tile_split
= tmp
->surface
.tile_split
;
1036 macro_aspect
= tmp
->surface
.mtilea
;
1037 bankw
= tmp
->surface
.bankw
;
1038 bankh
= tmp
->surface
.bankh
;
1039 tile_split
= eg_tile_split(tile_split
);
1040 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1041 bankw
= eg_bank_wh(bankw
);
1042 bankh
= eg_bank_wh(bankh
);
1044 /* 128 bit formats require tile type = 1 */
1045 if (rscreen
->chip_class
== CAYMAN
) {
1046 if (util_format_get_blocksize(state
->format
) >= 16)
1049 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1051 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
1053 depth
= texture
->array_size
;
1054 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
1055 depth
= texture
->array_size
;
1058 rstate
->bo
[0] = &tmp
->resource
;
1059 rstate
->bo
[1] = &tmp
->resource
;
1060 rstate
->bo_usage
[0] = RADEON_USAGE_READ
;
1061 rstate
->bo_usage
[1] = RADEON_USAGE_READ
;
1063 rstate
->val
[0] = (S_030000_DIM(r600_tex_dim(texture
->target
)) |
1064 S_030000_PITCH((pitch
/ 8) - 1) |
1065 S_030000_TEX_WIDTH(width
- 1));
1066 if (rscreen
->chip_class
== CAYMAN
)
1067 rstate
->val
[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type
);
1069 rstate
->val
[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type
);
1070 rstate
->val
[1] = (S_030004_TEX_HEIGHT(height
- 1) |
1071 S_030004_TEX_DEPTH(depth
- 1) |
1072 S_030004_ARRAY_MODE(array_mode
));
1073 rstate
->val
[2] = (tmp
->offset
[0] + r600_resource_va(ctx
->screen
, texture
)) >> 8;
1074 if (state
->u
.tex
.last_level
) {
1075 rstate
->val
[3] = (tmp
->offset
[1] + r600_resource_va(ctx
->screen
, texture
)) >> 8;
1077 rstate
->val
[3] = (tmp
->offset
[0] + r600_resource_va(ctx
->screen
, texture
)) >> 8;
1079 rstate
->val
[4] = (word4
|
1080 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
1081 S_030010_ENDIAN_SWAP(endian
) |
1082 S_030010_BASE_LEVEL(state
->u
.tex
.first_level
));
1083 rstate
->val
[5] = (S_030014_LAST_LEVEL(state
->u
.tex
.last_level
) |
1084 S_030014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
1085 S_030014_LAST_ARRAY(state
->u
.tex
.last_layer
));
1086 /* aniso max 16 samples */
1087 rstate
->val
[6] = (S_030018_MAX_ANISO(4)) |
1088 (S_030018_TILE_SPLIT(tile_split
));
1089 rstate
->val
[7] = S_03001C_DATA_FORMAT(format
) |
1090 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
) |
1091 S_03001C_BANK_WIDTH(bankw
) |
1092 S_03001C_BANK_HEIGHT(bankh
) |
1093 S_03001C_MACRO_TILE_ASPECT(macro_aspect
) |
1094 S_03001C_NUM_BANKS(nbanks
);
1099 static void evergreen_set_vs_sampler_view(struct pipe_context
*ctx
, unsigned count
,
1100 struct pipe_sampler_view
**views
)
1102 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1103 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
1105 for (int i
= 0; i
< count
; i
++) {
1107 r600_context_pipe_state_set_vs_resource(rctx
, &resource
[i
]->state
,
1108 i
+ R600_MAX_CONST_BUFFERS
);
1113 static void evergreen_set_ps_sampler_view(struct pipe_context
*ctx
, unsigned count
,
1114 struct pipe_sampler_view
**views
)
1116 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1117 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
1121 for (i
= 0; i
< count
; i
++) {
1122 if (&rctx
->ps_samplers
.views
[i
]->base
!= views
[i
]) {
1124 if (((struct r600_resource_texture
*)resource
[i
]->base
.texture
)->is_depth
)
1126 r600_context_pipe_state_set_ps_resource(rctx
, &resource
[i
]->state
,
1127 i
+ R600_MAX_CONST_BUFFERS
);
1129 r600_context_pipe_state_set_ps_resource(rctx
, NULL
,
1130 i
+ R600_MAX_CONST_BUFFERS
);
1132 pipe_sampler_view_reference(
1133 (struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
],
1137 if (((struct r600_resource_texture
*)resource
[i
]->base
.texture
)->is_depth
)
1142 for (i
= count
; i
< NUM_TEX_UNITS
; i
++) {
1143 if (rctx
->ps_samplers
.views
[i
]) {
1144 r600_context_pipe_state_set_ps_resource(rctx
, NULL
,
1145 i
+ R600_MAX_CONST_BUFFERS
);
1146 pipe_sampler_view_reference((struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
], NULL
);
1149 rctx
->have_depth_texture
= has_depth
;
1150 rctx
->ps_samplers
.n_views
= count
;
1153 static void evergreen_bind_ps_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
1155 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1156 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
1159 r600_inval_texture_cache(rctx
);
1161 memcpy(rctx
->ps_samplers
.samplers
, states
, sizeof(void*) * count
);
1162 rctx
->ps_samplers
.n_samplers
= count
;
1164 for (int i
= 0; i
< count
; i
++) {
1165 evergreen_context_pipe_state_set_ps_sampler(rctx
, rstates
[i
], i
);
1169 static void evergreen_bind_vs_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
1171 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1172 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
1175 r600_inval_texture_cache(rctx
);
1177 for (int i
= 0; i
< count
; i
++) {
1178 evergreen_context_pipe_state_set_vs_sampler(rctx
, rstates
[i
], i
);
1182 static void evergreen_set_clip_state(struct pipe_context
*ctx
,
1183 const struct pipe_clip_state
*state
)
1185 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1186 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1187 struct pipe_constant_buffer cb
;
1192 rctx
->clip
= *state
;
1193 rstate
->id
= R600_PIPE_STATE_CLIP
;
1194 for (int i
= 0; i
< 6; i
++) {
1195 r600_pipe_state_add_reg(rstate
,
1196 R_0285BC_PA_CL_UCP0_X
+ i
* 16,
1197 fui(state
->ucp
[i
][0]));
1198 r600_pipe_state_add_reg(rstate
,
1199 R_0285C0_PA_CL_UCP0_Y
+ i
* 16,
1200 fui(state
->ucp
[i
][1]) );
1201 r600_pipe_state_add_reg(rstate
,
1202 R_0285C4_PA_CL_UCP0_Z
+ i
* 16,
1203 fui(state
->ucp
[i
][2]));
1204 r600_pipe_state_add_reg(rstate
,
1205 R_0285C8_PA_CL_UCP0_W
+ i
* 16,
1206 fui(state
->ucp
[i
][3]));
1209 free(rctx
->states
[R600_PIPE_STATE_CLIP
]);
1210 rctx
->states
[R600_PIPE_STATE_CLIP
] = rstate
;
1211 r600_context_pipe_state_set(rctx
, rstate
);
1214 cb
.user_buffer
= state
->ucp
;
1215 cb
.buffer_offset
= 0;
1216 cb
.buffer_size
= 4*4*8;
1217 r600_set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, 1, &cb
);
1218 pipe_resource_reference(&cb
.buffer
, NULL
);
1221 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
1222 const struct pipe_poly_stipple
*state
)
1226 static void evergreen_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1230 static void evergreen_get_scissor_rect(struct r600_context
*rctx
,
1231 unsigned tl_x
, unsigned tl_y
, unsigned br_x
, unsigned br_y
,
1232 uint32_t *tl
, uint32_t *br
)
1234 /* EG hw workaround */
1240 /* cayman hw workaround */
1241 if (rctx
->chip_class
== CAYMAN
) {
1242 if (br_x
== 1 && br_y
== 1)
1246 *tl
= S_028240_TL_X(tl_x
) | S_028240_TL_Y(tl_y
);
1247 *br
= S_028244_BR_X(br_x
) | S_028244_BR_Y(br_y
);
1250 static void evergreen_set_scissor_state(struct pipe_context
*ctx
,
1251 const struct pipe_scissor_state
*state
)
1253 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1254 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1260 evergreen_get_scissor_rect(rctx
, state
->minx
, state
->miny
, state
->maxx
, state
->maxy
, &tl
, &br
);
1262 rstate
->id
= R600_PIPE_STATE_SCISSOR
;
1263 r600_pipe_state_add_reg(rstate
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
);
1264 r600_pipe_state_add_reg(rstate
, R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
);
1266 free(rctx
->states
[R600_PIPE_STATE_SCISSOR
]);
1267 rctx
->states
[R600_PIPE_STATE_SCISSOR
] = rstate
;
1268 r600_context_pipe_state_set(rctx
, rstate
);
1271 static void evergreen_set_viewport_state(struct pipe_context
*ctx
,
1272 const struct pipe_viewport_state
*state
)
1274 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1275 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1280 rctx
->viewport
= *state
;
1281 rstate
->id
= R600_PIPE_STATE_VIEWPORT
;
1282 r600_pipe_state_add_reg(rstate
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]));
1283 r600_pipe_state_add_reg(rstate
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]));
1284 r600_pipe_state_add_reg(rstate
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]));
1285 r600_pipe_state_add_reg(rstate
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]));
1286 r600_pipe_state_add_reg(rstate
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]));
1287 r600_pipe_state_add_reg(rstate
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]));
1289 free(rctx
->states
[R600_PIPE_STATE_VIEWPORT
]);
1290 rctx
->states
[R600_PIPE_STATE_VIEWPORT
] = rstate
;
1291 r600_context_pipe_state_set(rctx
, rstate
);
1294 static void evergreen_cb(struct r600_context
*rctx
, struct r600_pipe_state
*rstate
,
1295 const struct pipe_framebuffer_state
*state
, int cb
)
1297 struct r600_screen
*rscreen
= rctx
->screen
;
1298 struct r600_resource_texture
*rtex
;
1299 struct r600_surface
*surf
;
1300 unsigned level
= state
->cbufs
[cb
]->u
.tex
.level
;
1301 unsigned pitch
, slice
;
1302 unsigned color_info
, color_attrib
;
1303 unsigned format
, swap
, ntype
, endian
;
1305 unsigned tile_type
, macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1306 const struct util_format_description
*desc
;
1308 unsigned blend_clamp
= 0, blend_bypass
= 0;
1310 surf
= (struct r600_surface
*)state
->cbufs
[cb
];
1311 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
1314 rctx
->have_depth_fb
= TRUE
;
1316 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
1317 r600_init_flushed_depth_texture(&rctx
->context
, state
->cbufs
[cb
]->texture
);
1318 rtex
= rtex
->flushed_depth_texture
;
1322 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1323 if (!rscreen
->use_surface_alloc
) {
1324 offset
= r600_texture_get_offset(rtex
,
1325 level
, state
->cbufs
[cb
]->u
.tex
.first_layer
);
1326 pitch
= rtex
->pitch_in_blocks
[level
] / 8 - 1;
1327 slice
= rtex
->pitch_in_blocks
[level
] * surf
->aligned_height
/ 64;
1331 color_info
= S_028C70_ARRAY_MODE(rtex
->array_mode
[level
]);
1336 if (rtex
->array_mode
[level
] > V_028C70_ARRAY_LINEAR_ALIGNED
) {
1337 tile_type
= rtex
->tile_type
;
1339 /* workaround for linear buffers */
1343 offset
= rtex
->surface
.level
[level
].offset
;
1344 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1345 offset
+= rtex
->surface
.level
[level
].slice_size
*
1346 state
->cbufs
[cb
]->u
.tex
.first_layer
;
1348 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1349 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1354 switch (rtex
->surface
.level
[level
].mode
) {
1355 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1356 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1359 case RADEON_SURF_MODE_1D
:
1360 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1
);
1361 tile_type
= rtex
->tile_type
;
1363 case RADEON_SURF_MODE_2D
:
1364 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1
);
1365 tile_type
= rtex
->tile_type
;
1367 case RADEON_SURF_MODE_LINEAR
:
1369 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL
);
1373 tile_split
= rtex
->surface
.tile_split
;
1374 macro_aspect
= rtex
->surface
.mtilea
;
1375 bankw
= rtex
->surface
.bankw
;
1376 bankh
= rtex
->surface
.bankh
;
1377 tile_split
= eg_tile_split(tile_split
);
1378 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1379 bankw
= eg_bank_wh(bankw
);
1380 bankh
= eg_bank_wh(bankh
);
1382 /* 128 bit formats require tile type = 1 */
1383 if (rscreen
->chip_class
== CAYMAN
) {
1384 if (util_format_get_blocksize(surf
->base
.format
) >= 16)
1387 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1388 desc
= util_format_description(surf
->base
.format
);
1389 for (i
= 0; i
< 4; i
++) {
1390 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1395 color_attrib
= S_028C74_TILE_SPLIT(tile_split
)|
1396 S_028C74_NUM_BANKS(nbanks
) |
1397 S_028C74_BANK_WIDTH(bankw
) |
1398 S_028C74_BANK_HEIGHT(bankh
) |
1399 S_028C74_MACRO_TILE_ASPECT(macro_aspect
) |
1400 S_028C74_NON_DISP_TILING_ORDER(tile_type
);
1402 ntype
= V_028C70_NUMBER_UNORM
;
1403 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1404 ntype
= V_028C70_NUMBER_SRGB
;
1405 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1406 if (desc
->channel
[i
].normalized
)
1407 ntype
= V_028C70_NUMBER_SNORM
;
1408 else if (desc
->channel
[i
].pure_integer
)
1409 ntype
= V_028C70_NUMBER_SINT
;
1410 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1411 if (desc
->channel
[i
].normalized
)
1412 ntype
= V_028C70_NUMBER_UNORM
;
1413 else if (desc
->channel
[i
].pure_integer
)
1414 ntype
= V_028C70_NUMBER_UINT
;
1417 format
= r600_translate_colorformat(surf
->base
.format
);
1418 swap
= r600_translate_colorswap(surf
->base
.format
);
1419 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1420 endian
= ENDIAN_NONE
;
1422 endian
= r600_colorformat_endian_swap(format
);
1425 /* blend clamp should be set for all NORM/SRGB types */
1426 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
1427 ntype
== V_028C70_NUMBER_SRGB
)
1430 /* set blend bypass according to docs if SINT/UINT or
1431 8/24 COLOR variants */
1432 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1433 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1434 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1439 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
)
1440 rctx
->sx_alpha_test_control
|= S_028410_ALPHA_TEST_BYPASS(1);
1442 rctx
->sx_alpha_test_control
&= C_028410_ALPHA_TEST_BYPASS
;
1444 color_info
|= S_028C70_FORMAT(format
) |
1445 S_028C70_COMP_SWAP(swap
) |
1446 S_028C70_BLEND_CLAMP(blend_clamp
) |
1447 S_028C70_BLEND_BYPASS(blend_bypass
) |
1448 S_028C70_NUMBER_TYPE(ntype
) |
1449 S_028C70_ENDIAN(endian
);
1451 /* EXPORT_NORM is an optimzation that can be enabled for better
1452 * performance in certain cases.
1453 * EXPORT_NORM can be enabled if:
1454 * - 11-bit or smaller UNORM/SNORM/SRGB
1455 * - 16-bit or smaller FLOAT
1457 /* XXX: This should probably be the same for all CBs if we want
1458 * useful alpha tests. */
1459 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1460 ((desc
->channel
[i
].size
< 12 &&
1461 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1462 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
1463 (desc
->channel
[i
].size
< 17 &&
1464 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1465 color_info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
1466 rctx
->export_16bpc
= true;
1468 rctx
->export_16bpc
= false;
1470 rctx
->alpha_ref_dirty
= true;
1472 /* for possible dual-src MRT */
1473 if (cb
== 0 && rctx
->framebuffer
.nr_cbufs
== 1) {
1474 r600_pipe_state_add_reg_bo(rstate
,
1475 R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C,
1476 color_info
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1479 offset
+= r600_resource_va(rctx
->context
.screen
, state
->cbufs
[cb
]->texture
);
1482 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1483 r600_pipe_state_add_reg_bo(rstate
,
1484 R_028C60_CB_COLOR0_BASE
+ cb
* 0x3C,
1485 offset
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1486 r600_pipe_state_add_reg(rstate
,
1487 R_028C78_CB_COLOR0_DIM
+ cb
* 0x3C,
1489 r600_pipe_state_add_reg_bo(rstate
,
1490 R_028C70_CB_COLOR0_INFO
+ cb
* 0x3C,
1491 color_info
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1492 r600_pipe_state_add_reg(rstate
,
1493 R_028C64_CB_COLOR0_PITCH
+ cb
* 0x3C,
1494 S_028C64_PITCH_TILE_MAX(pitch
));
1495 r600_pipe_state_add_reg(rstate
,
1496 R_028C68_CB_COLOR0_SLICE
+ cb
* 0x3C,
1497 S_028C68_SLICE_TILE_MAX(slice
));
1498 if (!rscreen
->use_surface_alloc
) {
1499 r600_pipe_state_add_reg(rstate
,
1500 R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C,
1503 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1504 r600_pipe_state_add_reg(rstate
,
1505 R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C,
1508 r600_pipe_state_add_reg(rstate
,
1509 R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C,
1510 S_028C6C_SLICE_START(state
->cbufs
[cb
]->u
.tex
.first_layer
) |
1511 S_028C6C_SLICE_MAX(state
->cbufs
[cb
]->u
.tex
.last_layer
));
1514 r600_pipe_state_add_reg_bo(rstate
,
1515 R_028C74_CB_COLOR0_ATTRIB
+ cb
* 0x3C,
1517 &rtex
->resource
, RADEON_USAGE_READWRITE
);
1520 static void evergreen_db(struct r600_context
*rctx
, struct r600_pipe_state
*rstate
,
1521 const struct pipe_framebuffer_state
*state
)
1523 struct r600_screen
*rscreen
= rctx
->screen
;
1524 struct r600_resource_texture
*rtex
;
1525 struct r600_surface
*surf
;
1527 unsigned level
, first_layer
, pitch
, slice
, format
, array_mode
;
1528 unsigned macro_aspect
, tile_split
, bankh
, bankw
, z_info
, nbanks
;
1530 if (state
->zsbuf
== NULL
)
1533 surf
= (struct r600_surface
*)state
->zsbuf
;
1534 level
= surf
->base
.u
.tex
.level
;
1535 rtex
= (struct r600_resource_texture
*)surf
->base
.texture
;
1536 first_layer
= surf
->base
.u
.tex
.first_layer
;
1537 format
= r600_translate_dbformat(rtex
->real_format
);
1539 offset
= r600_resource_va(rctx
->context
.screen
, surf
->base
.texture
);
1540 /* XXX remove this once tiling is properly supported */
1541 if (!rscreen
->use_surface_alloc
) {
1542 /* XXX remove this once tiling is properly supported */
1543 array_mode
= rtex
->array_mode
[level
] ? rtex
->array_mode
[level
] :
1544 V_028C70_ARRAY_1D_TILED_THIN1
;
1546 offset
+= r600_texture_get_offset(rtex
, level
, first_layer
);
1547 pitch
= (rtex
->pitch_in_blocks
[level
] / 8) - 1;
1548 slice
= ((rtex
->pitch_in_blocks
[level
] * surf
->aligned_height
) / 64);
1557 offset
+= rtex
->surface
.level
[level
].offset
;
1558 pitch
= (rtex
->surface
.level
[level
].nblk_x
/ 8) - 1;
1559 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1563 switch (rtex
->surface
.level
[level
].mode
) {
1564 case RADEON_SURF_MODE_2D
:
1565 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1567 case RADEON_SURF_MODE_1D
:
1568 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1569 case RADEON_SURF_MODE_LINEAR
:
1571 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1574 tile_split
= rtex
->surface
.tile_split
;
1575 macro_aspect
= rtex
->surface
.mtilea
;
1576 bankw
= rtex
->surface
.bankw
;
1577 bankh
= rtex
->surface
.bankh
;
1578 tile_split
= eg_tile_split(tile_split
);
1579 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1580 bankw
= eg_bank_wh(bankw
);
1581 bankh
= eg_bank_wh(bankh
);
1583 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1586 z_info
= S_028040_ARRAY_MODE(array_mode
) |
1587 S_028040_FORMAT(format
) |
1588 S_028040_TILE_SPLIT(tile_split
)|
1589 S_028040_NUM_BANKS(nbanks
) |
1590 S_028040_BANK_WIDTH(bankw
) |
1591 S_028040_BANK_HEIGHT(bankh
) |
1592 S_028040_MACRO_TILE_ASPECT(macro_aspect
);
1594 r600_pipe_state_add_reg_bo(rstate
, R_028048_DB_Z_READ_BASE
,
1595 offset
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1596 r600_pipe_state_add_reg_bo(rstate
, R_028050_DB_Z_WRITE_BASE
,
1597 offset
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1598 if (!rscreen
->use_surface_alloc
) {
1599 r600_pipe_state_add_reg(rstate
, R_028008_DB_DEPTH_VIEW
,
1602 r600_pipe_state_add_reg(rstate
, R_028008_DB_DEPTH_VIEW
,
1603 S_028008_SLICE_START(state
->zsbuf
->u
.tex
.first_layer
) |
1604 S_028008_SLICE_MAX(state
->zsbuf
->u
.tex
.last_layer
));
1607 if (rtex
->stencil
) {
1608 uint64_t stencil_offset
=
1609 r600_texture_get_offset(rtex
->stencil
, level
, first_layer
);
1610 unsigned stile_split
;
1612 stile_split
= eg_tile_split(rtex
->stencil
->surface
.tile_split
);
1613 stencil_offset
+= r600_resource_va(rctx
->context
.screen
, (void*)rtex
->stencil
);
1614 stencil_offset
>>= 8;
1616 r600_pipe_state_add_reg_bo(rstate
, R_02804C_DB_STENCIL_READ_BASE
,
1617 stencil_offset
, &rtex
->stencil
->resource
, RADEON_USAGE_READWRITE
);
1618 r600_pipe_state_add_reg_bo(rstate
, R_028054_DB_STENCIL_WRITE_BASE
,
1619 stencil_offset
, &rtex
->stencil
->resource
, RADEON_USAGE_READWRITE
);
1620 r600_pipe_state_add_reg_bo(rstate
, R_028044_DB_STENCIL_INFO
,
1621 1 | S_028044_TILE_SPLIT(stile_split
),
1622 &rtex
->stencil
->resource
, RADEON_USAGE_READWRITE
);
1624 if (rscreen
->use_surface_alloc
&& rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1625 uint64_t stencil_offset
= rtex
->surface
.stencil_offset
;
1626 unsigned stile_split
= rtex
->surface
.stencil_tile_split
;
1628 stile_split
= eg_tile_split(stile_split
);
1629 stencil_offset
+= r600_resource_va(rctx
->context
.screen
, surf
->base
.texture
);
1630 stencil_offset
+= rtex
->surface
.level
[level
].offset
/ 4;
1631 stencil_offset
>>= 8;
1633 r600_pipe_state_add_reg_bo(rstate
, R_02804C_DB_STENCIL_READ_BASE
,
1634 stencil_offset
, &rtex
->resource
,
1635 RADEON_USAGE_READWRITE
);
1636 r600_pipe_state_add_reg_bo(rstate
, R_028054_DB_STENCIL_WRITE_BASE
,
1637 stencil_offset
, &rtex
->resource
,
1638 RADEON_USAGE_READWRITE
);
1639 r600_pipe_state_add_reg_bo(rstate
, R_028044_DB_STENCIL_INFO
,
1640 1 | S_028044_TILE_SPLIT(stile_split
),
1642 RADEON_USAGE_READWRITE
);
1644 r600_pipe_state_add_reg_bo(rstate
, R_02804C_DB_STENCIL_READ_BASE
,
1645 offset
, &rtex
->resource
,
1646 RADEON_USAGE_READWRITE
);
1647 r600_pipe_state_add_reg_bo(rstate
, R_028054_DB_STENCIL_WRITE_BASE
,
1648 offset
, &rtex
->resource
,
1649 RADEON_USAGE_READWRITE
);
1650 r600_pipe_state_add_reg_bo(rstate
, R_028044_DB_STENCIL_INFO
,
1651 0, NULL
, RADEON_USAGE_READWRITE
);
1655 r600_pipe_state_add_reg_bo(rstate
, R_028040_DB_Z_INFO
, z_info
,
1656 &rtex
->resource
, RADEON_USAGE_READWRITE
);
1657 r600_pipe_state_add_reg(rstate
, R_028058_DB_DEPTH_SIZE
,
1658 S_028058_PITCH_TILE_MAX(pitch
));
1659 r600_pipe_state_add_reg(rstate
, R_02805C_DB_DEPTH_SLICE
,
1660 S_02805C_SLICE_TILE_MAX(slice
));
1663 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
1664 const struct pipe_framebuffer_state
*state
)
1666 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1667 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1673 r600_flush_framebuffer(rctx
, false);
1675 /* unreference old buffer and reference new one */
1676 rstate
->id
= R600_PIPE_STATE_FRAMEBUFFER
;
1678 util_copy_framebuffer_state(&rctx
->framebuffer
, state
);
1681 rctx
->have_depth_fb
= 0;
1682 rctx
->nr_cbufs
= state
->nr_cbufs
;
1683 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1684 evergreen_cb(rctx
, rstate
, state
, i
);
1687 evergreen_db(rctx
, rstate
, state
);
1690 rctx
->fb_cb_shader_mask
= 0;
1691 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1692 rctx
->fb_cb_shader_mask
|= 0xf << (i
* 4);
1695 evergreen_get_scissor_rect(rctx
, 0, 0, state
->width
, state
->height
, &tl
, &br
);
1697 r600_pipe_state_add_reg(rstate
,
1698 R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
);
1699 r600_pipe_state_add_reg(rstate
,
1700 R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
);
1702 free(rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
]);
1703 rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
] = rstate
;
1704 r600_context_pipe_state_set(rctx
, rstate
);
1707 evergreen_polygon_offset_update(rctx
);
1711 static void evergreen_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1713 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1714 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1715 unsigned db_count_control
= 0;
1716 unsigned db_render_override
=
1717 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
) |
1718 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
1719 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
1721 if (a
->occlusion_query_enabled
) {
1722 db_count_control
|= S_028004_PERFECT_ZPASS_COUNTS(1);
1723 db_render_override
|= S_02800C_NOOP_CULL_DISABLE(1);
1726 r600_write_context_reg(cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1727 r600_write_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
1730 static void evergreen_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1732 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1733 struct pipe_vertex_buffer
*vb
= rctx
->vertex_buffer
;
1734 unsigned count
= rctx
->nr_vertex_buffers
;
1738 for (i
= 0; i
< count
; i
++) {
1739 struct r600_resource
*rbuffer
= (struct r600_resource
*)vb
[i
].buffer
;
1745 va
= r600_resource_va(&rctx
->screen
->screen
, &rbuffer
->b
.b
);
1746 va
+= vb
[i
].buffer_offset
;
1748 /* fetch resources start at index 992 */
1749 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0));
1750 r600_write_value(cs
, (992 + i
) * 8);
1751 r600_write_value(cs
, va
); /* RESOURCEi_WORD0 */
1752 r600_write_value(cs
, rbuffer
->buf
->size
- vb
[i
].buffer_offset
- 1); /* RESOURCEi_WORD1 */
1753 r600_write_value(cs
, /* RESOURCEi_WORD2 */
1754 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1755 S_030008_STRIDE(vb
[i
].stride
) |
1756 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
1757 r600_write_value(cs
, /* RESOURCEi_WORD3 */
1758 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
1759 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
1760 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
1761 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
1762 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
1763 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
1764 r600_write_value(cs
, 0); /* RESOURCEi_WORD6 */
1765 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
1767 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1768 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1772 static void evergreen_emit_constant_buffer(struct r600_context
*rctx
,
1773 struct r600_constbuf_state
*state
,
1774 unsigned buffer_id_base
,
1775 unsigned reg_alu_constbuf_size
,
1776 unsigned reg_alu_const_cache
)
1778 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1779 uint32_t dirty_mask
= state
->dirty_mask
;
1781 while (dirty_mask
) {
1782 struct pipe_constant_buffer
*cb
;
1783 struct r600_resource
*rbuffer
;
1785 unsigned buffer_index
= ffs(dirty_mask
) - 1;
1787 cb
= &state
->cb
[buffer_index
];
1788 rbuffer
= (struct r600_resource
*)cb
->buffer
;
1791 va
= r600_resource_va(&rctx
->screen
->screen
, &rbuffer
->b
.b
);
1792 va
+= cb
->buffer_offset
;
1794 r600_write_context_reg(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
1795 ALIGN_DIVUP(cb
->buffer_size
>> 4, 16));
1796 r600_write_context_reg(cs
, reg_alu_const_cache
+ buffer_index
* 4, va
>> 8);
1798 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1799 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1801 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0));
1802 r600_write_value(cs
, (buffer_id_base
+ buffer_index
) * 8);
1803 r600_write_value(cs
, va
); /* RESOURCEi_WORD0 */
1804 r600_write_value(cs
, rbuffer
->buf
->size
- cb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
1805 r600_write_value(cs
, /* RESOURCEi_WORD2 */
1806 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1807 S_030008_STRIDE(16) |
1808 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
1809 r600_write_value(cs
, /* RESOURCEi_WORD3 */
1810 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
1811 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
1812 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
1813 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
1814 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
1815 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
1816 r600_write_value(cs
, 0); /* RESOURCEi_WORD6 */
1817 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
1819 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1820 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1822 dirty_mask
&= ~(1 << buffer_index
);
1824 state
->dirty_mask
= 0;
1827 static void evergreen_emit_vs_constant_buffer(struct r600_context
*rctx
, struct r600_atom
*atom
)
1829 evergreen_emit_constant_buffer(rctx
, &rctx
->vs_constbuf_state
, 176,
1830 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
1831 R_028980_ALU_CONST_CACHE_VS_0
);
1834 static void evergreen_emit_ps_constant_buffer(struct r600_context
*rctx
, struct r600_atom
*atom
)
1836 evergreen_emit_constant_buffer(rctx
, &rctx
->ps_constbuf_state
, 0,
1837 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
1838 R_028940_ALU_CONST_CACHE_PS_0
);
1841 void evergreen_init_state_functions(struct r600_context
*rctx
)
1843 r600_init_atom(&rctx
->db_misc_state
.atom
, evergreen_emit_db_misc_state
, 6, 0);
1844 r600_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1845 r600_init_atom(&rctx
->vertex_buffer_state
, evergreen_emit_vertex_buffers
, 0, 0);
1846 r600_init_atom(&rctx
->vs_constbuf_state
.atom
, evergreen_emit_vs_constant_buffer
, 0, 0);
1847 r600_init_atom(&rctx
->ps_constbuf_state
.atom
, evergreen_emit_ps_constant_buffer
, 0, 0);
1849 rctx
->context
.create_blend_state
= evergreen_create_blend_state
;
1850 rctx
->context
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
1851 rctx
->context
.create_fs_state
= r600_create_shader_state_ps
;
1852 rctx
->context
.create_rasterizer_state
= evergreen_create_rs_state
;
1853 rctx
->context
.create_sampler_state
= evergreen_create_sampler_state
;
1854 rctx
->context
.create_sampler_view
= evergreen_create_sampler_view
;
1855 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
1856 rctx
->context
.create_vs_state
= r600_create_shader_state_vs
;
1857 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1858 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
1859 rctx
->context
.bind_fragment_sampler_states
= evergreen_bind_ps_sampler
;
1860 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
1861 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1862 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1863 rctx
->context
.bind_vertex_sampler_states
= evergreen_bind_vs_sampler
;
1864 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
1865 rctx
->context
.delete_blend_state
= r600_delete_state
;
1866 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
1867 rctx
->context
.delete_fs_state
= r600_delete_ps_shader
;
1868 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1869 rctx
->context
.delete_sampler_state
= r600_delete_state
;
1870 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
1871 rctx
->context
.delete_vs_state
= r600_delete_vs_shader
;
1872 rctx
->context
.set_blend_color
= r600_set_blend_color
;
1873 rctx
->context
.set_clip_state
= evergreen_set_clip_state
;
1874 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1875 rctx
->context
.set_fragment_sampler_views
= evergreen_set_ps_sampler_view
;
1876 rctx
->context
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
1877 rctx
->context
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
1878 rctx
->context
.set_sample_mask
= evergreen_set_sample_mask
;
1879 rctx
->context
.set_scissor_state
= evergreen_set_scissor_state
;
1880 rctx
->context
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
1881 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1882 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1883 rctx
->context
.set_vertex_sampler_views
= evergreen_set_vs_sampler_view
;
1884 rctx
->context
.set_viewport_state
= evergreen_set_viewport_state
;
1885 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1886 rctx
->context
.texture_barrier
= r600_texture_barrier
;
1887 rctx
->context
.create_stream_output_target
= r600_create_so_target
;
1888 rctx
->context
.stream_output_target_destroy
= r600_so_target_destroy
;
1889 rctx
->context
.set_stream_output_targets
= r600_set_so_targets
;
1890 evergreen_init_compute_state_functions(rctx
);
1893 static void cayman_init_atom_start_cs(struct r600_context
*rctx
)
1895 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
1897 r600_init_command_buffer(cb
, 256, EMIT_EARLY
);
1899 /* This must be first. */
1900 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1901 r600_store_value(cb
, 0x80000000);
1902 r600_store_value(cb
, 0x80000000);
1904 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
1905 r600_store_value(cb
, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
1906 /* always set the temp clauses */
1907 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
1909 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
1910 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
1911 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
1913 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
1915 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
1917 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
1918 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
1919 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
1920 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
1921 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
1922 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
1923 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
1924 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
1925 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
1926 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
1927 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
1928 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
1929 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
1930 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
1932 r600_store_context_reg_seq(cb
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
1933 r600_store_value(cb
, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
1934 r600_store_value(cb
, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
1936 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
1937 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
1938 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
1940 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
1942 r600_store_context_reg(cb
, CM_R_028AA8_IA_MULTI_VGT_PARAM
, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
1944 r600_store_context_reg_seq(cb
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1945 r600_store_value(cb
, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
1946 r600_store_value(cb
, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
1948 r600_store_context_reg_seq(cb
, CM_R_0288E8_SQ_LDS_ALLOC
, 2);
1949 r600_store_value(cb
, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
1950 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
1952 r600_store_context_reg(cb
, CM_R_028804_DB_EQAA
, 0x110000);
1954 r600_store_context_reg_seq(cb
, R_028380_SQ_VTX_SEMANTIC_0
, 34);
1955 r600_store_value(cb
, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
1956 r600_store_value(cb
, 0);
1957 r600_store_value(cb
, 0);
1958 r600_store_value(cb
, 0);
1959 r600_store_value(cb
, 0);
1960 r600_store_value(cb
, 0);
1961 r600_store_value(cb
, 0);
1962 r600_store_value(cb
, 0);
1963 r600_store_value(cb
, 0);
1964 r600_store_value(cb
, 0);
1965 r600_store_value(cb
, 0);
1966 r600_store_value(cb
, 0);
1967 r600_store_value(cb
, 0);
1968 r600_store_value(cb
, 0);
1969 r600_store_value(cb
, 0);
1970 r600_store_value(cb
, 0);
1971 r600_store_value(cb
, 0);
1972 r600_store_value(cb
, 0);
1973 r600_store_value(cb
, 0);
1974 r600_store_value(cb
, 0);
1975 r600_store_value(cb
, 0);
1976 r600_store_value(cb
, 0);
1977 r600_store_value(cb
, 0);
1978 r600_store_value(cb
, 0);
1979 r600_store_value(cb
, 0);
1980 r600_store_value(cb
, 0);
1981 r600_store_value(cb
, 0);
1982 r600_store_value(cb
, 0);
1983 r600_store_value(cb
, 0);
1984 r600_store_value(cb
, 0);
1985 r600_store_value(cb
, 0);
1986 r600_store_value(cb
, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
1987 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
1988 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
1990 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
1992 r600_store_context_reg_seq(cb
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
1993 r600_store_value(cb
, ~0); /* CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 */
1994 r600_store_value(cb
, ~0); /* CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 */
1996 r600_store_context_reg_seq(cb
, R_028028_DB_STENCIL_CLEAR
, 2);
1997 r600_store_value(cb
, 0); /* R_028028_DB_STENCIL_CLEAR */
1998 r600_store_value(cb
, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2000 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2002 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2003 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2004 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2005 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2007 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2008 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2010 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
2011 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2012 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2014 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2015 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
2016 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2017 r600_store_context_reg(cb
, R_028B70_DB_ALPHA_TO_MASK
, 0x0000AA00);
2019 r600_store_context_reg_seq(cb
, CM_R_028BDC_PA_SC_LINE_CNTL
, 2);
2020 r600_store_value(cb
, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2021 r600_store_value(cb
, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2023 r600_store_context_reg_seq(cb
, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2024 r600_store_value(cb
, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2025 r600_store_value(cb
, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2026 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2027 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2029 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2030 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2031 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2033 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2034 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2035 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2037 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2038 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2039 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2041 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2042 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2044 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2045 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2048 void evergreen_init_atom_start_cs(struct r600_context
*rctx
)
2050 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2055 int hs_prio
, cs_prio
, ls_prio
;
2069 int num_ps_stack_entries
;
2070 int num_vs_stack_entries
;
2071 int num_gs_stack_entries
;
2072 int num_es_stack_entries
;
2073 int num_hs_stack_entries
;
2074 int num_ls_stack_entries
;
2075 enum radeon_family family
;
2078 if (rctx
->chip_class
== CAYMAN
) {
2079 cayman_init_atom_start_cs(rctx
);
2083 r600_init_command_buffer(cb
, 256, EMIT_EARLY
);
2085 /* This must be first. */
2086 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2087 r600_store_value(cb
, 0x80000000);
2088 r600_store_value(cb
, 0x80000000);
2090 family
= rctx
->family
;
2109 num_ps_threads
= 96;
2110 num_vs_threads
= 16;
2111 num_gs_threads
= 16;
2112 num_es_threads
= 16;
2113 num_hs_threads
= 16;
2114 num_ls_threads
= 16;
2115 num_ps_stack_entries
= 42;
2116 num_vs_stack_entries
= 42;
2117 num_gs_stack_entries
= 42;
2118 num_es_stack_entries
= 42;
2119 num_hs_stack_entries
= 42;
2120 num_ls_stack_entries
= 42;
2130 num_ps_threads
= 128;
2131 num_vs_threads
= 20;
2132 num_gs_threads
= 20;
2133 num_es_threads
= 20;
2134 num_hs_threads
= 20;
2135 num_ls_threads
= 20;
2136 num_ps_stack_entries
= 42;
2137 num_vs_stack_entries
= 42;
2138 num_gs_stack_entries
= 42;
2139 num_es_stack_entries
= 42;
2140 num_hs_stack_entries
= 42;
2141 num_ls_stack_entries
= 42;
2151 num_ps_threads
= 128;
2152 num_vs_threads
= 20;
2153 num_gs_threads
= 20;
2154 num_es_threads
= 20;
2155 num_hs_threads
= 20;
2156 num_ls_threads
= 20;
2157 num_ps_stack_entries
= 85;
2158 num_vs_stack_entries
= 85;
2159 num_gs_stack_entries
= 85;
2160 num_es_stack_entries
= 85;
2161 num_hs_stack_entries
= 85;
2162 num_ls_stack_entries
= 85;
2173 num_ps_threads
= 128;
2174 num_vs_threads
= 20;
2175 num_gs_threads
= 20;
2176 num_es_threads
= 20;
2177 num_hs_threads
= 20;
2178 num_ls_threads
= 20;
2179 num_ps_stack_entries
= 85;
2180 num_vs_stack_entries
= 85;
2181 num_gs_stack_entries
= 85;
2182 num_es_stack_entries
= 85;
2183 num_hs_stack_entries
= 85;
2184 num_ls_stack_entries
= 85;
2194 num_ps_threads
= 96;
2195 num_vs_threads
= 16;
2196 num_gs_threads
= 16;
2197 num_es_threads
= 16;
2198 num_hs_threads
= 16;
2199 num_ls_threads
= 16;
2200 num_ps_stack_entries
= 42;
2201 num_vs_stack_entries
= 42;
2202 num_gs_stack_entries
= 42;
2203 num_es_stack_entries
= 42;
2204 num_hs_stack_entries
= 42;
2205 num_ls_stack_entries
= 42;
2215 num_ps_threads
= 96;
2216 num_vs_threads
= 25;
2217 num_gs_threads
= 25;
2218 num_es_threads
= 25;
2219 num_hs_threads
= 25;
2220 num_ls_threads
= 25;
2221 num_ps_stack_entries
= 42;
2222 num_vs_stack_entries
= 42;
2223 num_gs_stack_entries
= 42;
2224 num_es_stack_entries
= 42;
2225 num_hs_stack_entries
= 42;
2226 num_ls_stack_entries
= 42;
2236 num_ps_threads
= 96;
2237 num_vs_threads
= 25;
2238 num_gs_threads
= 25;
2239 num_es_threads
= 25;
2240 num_hs_threads
= 25;
2241 num_ls_threads
= 25;
2242 num_ps_stack_entries
= 85;
2243 num_vs_stack_entries
= 85;
2244 num_gs_stack_entries
= 85;
2245 num_es_stack_entries
= 85;
2246 num_hs_stack_entries
= 85;
2247 num_ls_stack_entries
= 85;
2257 num_ps_threads
= 128;
2258 num_vs_threads
= 20;
2259 num_gs_threads
= 20;
2260 num_es_threads
= 20;
2261 num_hs_threads
= 20;
2262 num_ls_threads
= 20;
2263 num_ps_stack_entries
= 85;
2264 num_vs_stack_entries
= 85;
2265 num_gs_stack_entries
= 85;
2266 num_es_stack_entries
= 85;
2267 num_hs_stack_entries
= 85;
2268 num_ls_stack_entries
= 85;
2278 num_ps_threads
= 128;
2279 num_vs_threads
= 20;
2280 num_gs_threads
= 20;
2281 num_es_threads
= 20;
2282 num_hs_threads
= 20;
2283 num_ls_threads
= 20;
2284 num_ps_stack_entries
= 42;
2285 num_vs_stack_entries
= 42;
2286 num_gs_stack_entries
= 42;
2287 num_es_stack_entries
= 42;
2288 num_hs_stack_entries
= 42;
2289 num_ls_stack_entries
= 42;
2299 num_ps_threads
= 128;
2300 num_vs_threads
= 10;
2301 num_gs_threads
= 10;
2302 num_es_threads
= 10;
2303 num_hs_threads
= 10;
2304 num_ls_threads
= 10;
2305 num_ps_stack_entries
= 42;
2306 num_vs_stack_entries
= 42;
2307 num_gs_stack_entries
= 42;
2308 num_es_stack_entries
= 42;
2309 num_hs_stack_entries
= 42;
2310 num_ls_stack_entries
= 42;
2323 tmp
|= S_008C00_VC_ENABLE(1);
2326 tmp
|= S_008C00_EXPORT_SRC_C(1);
2327 tmp
|= S_008C00_CS_PRIO(cs_prio
);
2328 tmp
|= S_008C00_LS_PRIO(ls_prio
);
2329 tmp
|= S_008C00_HS_PRIO(hs_prio
);
2330 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2331 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2332 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2333 tmp
|= S_008C00_ES_PRIO(es_prio
);
2335 /* enable dynamic GPR resource management */
2336 if (rctx
->screen
->info
.drm_minor
>= 7) {
2337 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2338 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2339 /* always set temp clauses */
2340 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2341 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2342 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2343 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2344 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2345 r600_store_context_reg(cb
, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
,
2346 S_028838_PS_GPRS(0x1e) |
2347 S_028838_VS_GPRS(0x1e) |
2348 S_028838_GS_GPRS(0x1e) |
2349 S_028838_ES_GPRS(0x1e) |
2350 S_028838_HS_GPRS(0x1e) |
2351 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2353 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 4);
2354 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2356 tmp
= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
2357 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
2358 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
2359 r600_store_value(cb
, tmp
); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2361 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2362 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2363 r600_store_value(cb
, tmp
); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2365 tmp
= S_008C0C_NUM_HS_GPRS(num_hs_gprs
);
2366 tmp
|= S_008C0C_NUM_HS_GPRS(num_ls_gprs
);
2367 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2370 tmp
= S_008C18_NUM_PS_THREADS(num_ps_threads
);
2371 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
2372 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
2373 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
2374 r600_store_config_reg_seq(cb
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, 5);
2375 r600_store_value(cb
, tmp
); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2377 tmp
= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
2378 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
2379 r600_store_value(cb
, tmp
); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2381 tmp
= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2382 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2383 r600_store_value(cb
, tmp
); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2385 tmp
= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2386 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2387 r600_store_value(cb
, tmp
); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2389 tmp
= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
2390 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
2391 r600_store_value(cb
, tmp
); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2393 r600_store_config_reg(cb
, R_008E2C_SQ_LDS_RESOURCE_MGMT
,
2394 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2396 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2397 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2399 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
2401 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2402 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2403 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2404 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2405 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2406 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2407 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2409 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2410 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2411 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2412 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2413 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2415 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2416 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2417 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2418 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2419 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2420 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2421 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2422 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2423 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2424 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2425 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2426 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2427 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2428 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2430 r600_store_context_reg_seq(cb
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
2431 r600_store_value(cb
, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2432 r600_store_value(cb
, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2434 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2435 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
2436 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2438 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2440 r600_store_context_reg_seq(cb
, R_028380_SQ_VTX_SEMANTIC_0
, 34);
2441 r600_store_value(cb
, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2442 r600_store_value(cb
, 0);
2443 r600_store_value(cb
, 0);
2444 r600_store_value(cb
, 0);
2445 r600_store_value(cb
, 0);
2446 r600_store_value(cb
, 0);
2447 r600_store_value(cb
, 0);
2448 r600_store_value(cb
, 0);
2449 r600_store_value(cb
, 0);
2450 r600_store_value(cb
, 0);
2451 r600_store_value(cb
, 0);
2452 r600_store_value(cb
, 0);
2453 r600_store_value(cb
, 0);
2454 r600_store_value(cb
, 0);
2455 r600_store_value(cb
, 0);
2456 r600_store_value(cb
, 0);
2457 r600_store_value(cb
, 0);
2458 r600_store_value(cb
, 0);
2459 r600_store_value(cb
, 0);
2460 r600_store_value(cb
, 0);
2461 r600_store_value(cb
, 0);
2462 r600_store_value(cb
, 0);
2463 r600_store_value(cb
, 0);
2464 r600_store_value(cb
, 0);
2465 r600_store_value(cb
, 0);
2466 r600_store_value(cb
, 0);
2467 r600_store_value(cb
, 0);
2468 r600_store_value(cb
, 0);
2469 r600_store_value(cb
, 0);
2470 r600_store_value(cb
, 0);
2471 r600_store_value(cb
, 0);
2472 r600_store_value(cb
, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2473 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2474 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2476 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2478 r600_store_context_reg_seq(cb
, R_028028_DB_STENCIL_CLEAR
, 2);
2479 r600_store_value(cb
, 0); /* R_028028_DB_STENCIL_CLEAR */
2480 r600_store_value(cb
, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2482 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2483 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2484 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2486 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
2487 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2488 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2490 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2491 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
2492 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2494 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2495 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2496 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2497 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2499 r600_store_context_reg(cb
, R_028B70_DB_ALPHA_TO_MASK
, 0x0000AA00);
2501 r600_store_context_reg_seq(cb
, R_028C00_PA_SC_LINE_CNTL
, 2);
2502 r600_store_value(cb
, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
2503 r600_store_value(cb
, 0); /* R_028C04_PA_SC_AA_CONFIG */
2505 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 5);
2506 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2507 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2508 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2509 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2510 r600_store_value(cb
, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
2512 r600_store_context_reg(cb
, R_028C3C_PA_SC_AA_MASK
, ~0);
2514 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2515 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2516 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2518 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2519 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2520 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2522 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2523 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2524 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2526 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2527 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2529 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2530 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2533 void evergreen_polygon_offset_update(struct r600_context
*rctx
)
2535 struct r600_pipe_state state
;
2537 state
.id
= R600_PIPE_STATE_POLYGON_OFFSET
;
2539 if (rctx
->rasterizer
&& rctx
->framebuffer
.zsbuf
) {
2540 float offset_units
= rctx
->rasterizer
->offset_units
;
2541 unsigned offset_db_fmt_cntl
= 0, depth
;
2543 switch (rctx
->framebuffer
.zsbuf
->texture
->format
) {
2544 case PIPE_FORMAT_Z24X8_UNORM
:
2545 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2547 offset_units
*= 2.0f
;
2549 case PIPE_FORMAT_Z32_FLOAT
:
2550 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2552 offset_units
*= 1.0f
;
2553 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2555 case PIPE_FORMAT_Z16_UNORM
:
2557 offset_units
*= 4.0f
;
2562 /* XXX some of those reg can be computed with cso */
2563 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
2564 r600_pipe_state_add_reg(&state
,
2565 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
2566 fui(rctx
->rasterizer
->offset_scale
));
2567 r600_pipe_state_add_reg(&state
,
2568 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
2570 r600_pipe_state_add_reg(&state
,
2571 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
2572 fui(rctx
->rasterizer
->offset_scale
));
2573 r600_pipe_state_add_reg(&state
,
2574 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
2576 r600_pipe_state_add_reg(&state
,
2577 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
2578 offset_db_fmt_cntl
);
2579 r600_context_pipe_state_set(rctx
, &state
);
2583 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2585 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2586 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2587 struct r600_shader
*rshader
= &shader
->shader
;
2588 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
2589 int pos_index
= -1, face_index
= -1;
2591 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
2592 unsigned spi_baryc_cntl
, sid
, tmp
, idx
= 0;
2596 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2597 for (i
= 0; i
< rshader
->ninput
; i
++) {
2598 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2599 POSITION goes via GPRs from the SC so isn't counted */
2600 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2602 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
2606 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
2608 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
2609 have_perspective
= TRUE
;
2610 if (rshader
->input
[i
].centroid
)
2611 have_centroid
= TRUE
;
2614 sid
= rshader
->input
[i
].spi_sid
;
2618 tmp
= S_028644_SEMANTIC(sid
);
2620 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2621 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2622 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2623 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
)) {
2624 tmp
|= S_028644_FLAT_SHADE(1);
2627 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2628 (rctx
->sprite_coord_enable
& (1 << rshader
->input
[i
].sid
))) {
2629 tmp
|= S_028644_PT_SPRITE_TEX(1);
2632 r600_pipe_state_add_reg(rstate
, R_028644_SPI_PS_INPUT_CNTL_0
+ idx
* 4,
2639 for (i
= 0; i
< rshader
->noutput
; i
++) {
2640 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2641 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(1);
2642 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2643 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(1);
2645 if (rshader
->uses_kill
)
2646 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2649 for (i
= 0; i
< rshader
->noutput
; i
++) {
2650 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2651 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2655 num_cout
= rshader
->nr_ps_color_exports
;
2657 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
2659 /* always at least export 1 component per pixel */
2662 shader
->ps_cb_shader_mask
= (1ULL << ((unsigned)num_cout
* 4)) - 1;
2665 have_perspective
= TRUE
;
2668 if (!have_perspective
&& !have_linear
)
2669 have_perspective
= TRUE
;
2671 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
2672 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
2673 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
2675 if (pos_index
!= -1) {
2676 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
2677 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
2678 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
2682 spi_ps_in_control_1
= 0;
2683 if (face_index
!= -1) {
2684 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2685 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2689 if (have_perspective
)
2690 spi_baryc_cntl
|= S_0286E0_PERSP_CENTER_ENA(1) |
2691 S_0286E0_PERSP_CENTROID_ENA(have_centroid
);
2693 spi_baryc_cntl
|= S_0286E0_LINEAR_CENTER_ENA(1) |
2694 S_0286E0_LINEAR_CENTROID_ENA(have_centroid
);
2696 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
,
2697 spi_ps_in_control_0
);
2698 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
,
2699 spi_ps_in_control_1
);
2700 r600_pipe_state_add_reg(rstate
, R_0286E4_SPI_PS_IN_CONTROL_2
,
2702 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
2703 r600_pipe_state_add_reg(rstate
,
2704 R_0286E0_SPI_BARYC_CNTL
,
2707 r600_pipe_state_add_reg_bo(rstate
,
2708 R_028840_SQ_PGM_START_PS
,
2709 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8,
2710 shader
->bo
, RADEON_USAGE_READ
);
2711 r600_pipe_state_add_reg(rstate
,
2712 R_028844_SQ_PGM_RESOURCES_PS
,
2713 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
2714 S_028844_PRIME_CACHE_ON_DRAW(1) |
2715 S_028844_STACK_SIZE(rshader
->bc
.nstack
));
2716 r600_pipe_state_add_reg(rstate
,
2717 R_02884C_SQ_PGM_EXPORTS_PS
,
2719 r600_pipe_state_add_reg(rstate
, R_02880C_DB_SHADER_CONTROL
,
2722 shader
->sprite_coord_enable
= rctx
->sprite_coord_enable
;
2723 if (rctx
->rasterizer
)
2724 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
2727 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2729 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2730 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2731 struct r600_shader
*rshader
= &shader
->shader
;
2732 unsigned spi_vs_out_id
[10] = {};
2733 unsigned i
, tmp
, nparams
= 0;
2735 /* clear previous register */
2738 for (i
= 0; i
< rshader
->noutput
; i
++) {
2739 if (rshader
->output
[i
].spi_sid
) {
2740 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
2741 spi_vs_out_id
[nparams
/ 4] |= tmp
;
2746 for (i
= 0; i
< 10; i
++) {
2747 r600_pipe_state_add_reg(rstate
,
2748 R_02861C_SPI_VS_OUT_ID_0
+ i
* 4,
2752 /* Certain attributes (position, psize, etc.) don't count as params.
2753 * VS is required to export at least one param and r600_shader_from_tgsi()
2754 * takes care of adding a dummy export.
2759 r600_pipe_state_add_reg(rstate
,
2760 R_0286C4_SPI_VS_OUT_CONFIG
,
2761 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
2762 r600_pipe_state_add_reg(rstate
,
2763 R_028860_SQ_PGM_RESOURCES_VS
,
2764 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
2765 S_028860_STACK_SIZE(rshader
->bc
.nstack
));
2766 r600_pipe_state_add_reg_bo(rstate
,
2767 R_02885C_SQ_PGM_START_VS
,
2768 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8,
2769 shader
->bo
, RADEON_USAGE_READ
);
2771 shader
->pa_cl_vs_out_cntl
=
2772 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
2773 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
2774 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
2775 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
);
2778 void evergreen_fetch_shader(struct pipe_context
*ctx
,
2779 struct r600_vertex_element
*ve
)
2781 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2782 struct r600_pipe_state
*rstate
= &ve
->rstate
;
2783 rstate
->id
= R600_PIPE_STATE_FETCH_SHADER
;
2785 r600_pipe_state_add_reg_bo(rstate
, R_0288A4_SQ_PGM_START_FS
,
2786 r600_resource_va(ctx
->screen
, (void *)ve
->fetch_shader
) >> 8,
2787 ve
->fetch_shader
, RADEON_USAGE_READ
);
2790 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
)
2792 struct pipe_depth_stencil_alpha_state dsa
;
2793 struct r600_pipe_state
*rstate
;
2795 memset(&dsa
, 0, sizeof(dsa
));
2797 rstate
= rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
2798 r600_pipe_state_add_reg(rstate
,
2799 R_028000_DB_RENDER_CONTROL
,
2800 S_028000_DEPTH_COPY_ENABLE(1) |
2801 S_028000_STENCIL_COPY_ENABLE(1) |
2802 S_028000_COPY_CENTROID(1));
2803 /* Don't set the 'is_flush' flag in r600_pipe_dsa, evergreen doesn't need it. */