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r600g: Add start_compute_cs atom to struct r600_context
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "evergreend.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31 #include "evergreen_compute.h"
32
33 static uint32_t eg_num_banks(uint32_t nbanks)
34 {
35 switch (nbanks) {
36 case 2:
37 return 0;
38 case 4:
39 return 1;
40 case 8:
41 default:
42 return 2;
43 case 16:
44 return 3;
45 }
46 }
47
48
49 static unsigned eg_tile_split(unsigned tile_split)
50 {
51 switch (tile_split) {
52 case 64: tile_split = 0; break;
53 case 128: tile_split = 1; break;
54 case 256: tile_split = 2; break;
55 case 512: tile_split = 3; break;
56 default:
57 case 1024: tile_split = 4; break;
58 case 2048: tile_split = 5; break;
59 case 4096: tile_split = 6; break;
60 }
61 return tile_split;
62 }
63
64 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65 {
66 switch (macro_tile_aspect) {
67 default:
68 case 1: macro_tile_aspect = 0; break;
69 case 2: macro_tile_aspect = 1; break;
70 case 4: macro_tile_aspect = 2; break;
71 case 8: macro_tile_aspect = 3; break;
72 }
73 return macro_tile_aspect;
74 }
75
76 static unsigned eg_bank_wh(unsigned bankwh)
77 {
78 switch (bankwh) {
79 default:
80 case 1: bankwh = 0; break;
81 case 2: bankwh = 1; break;
82 case 4: bankwh = 2; break;
83 case 8: bankwh = 3; break;
84 }
85 return bankwh;
86 }
87
88 static uint32_t r600_translate_blend_function(int blend_func)
89 {
90 switch (blend_func) {
91 case PIPE_BLEND_ADD:
92 return V_028780_COMB_DST_PLUS_SRC;
93 case PIPE_BLEND_SUBTRACT:
94 return V_028780_COMB_SRC_MINUS_DST;
95 case PIPE_BLEND_REVERSE_SUBTRACT:
96 return V_028780_COMB_DST_MINUS_SRC;
97 case PIPE_BLEND_MIN:
98 return V_028780_COMB_MIN_DST_SRC;
99 case PIPE_BLEND_MAX:
100 return V_028780_COMB_MAX_DST_SRC;
101 default:
102 R600_ERR("Unknown blend function %d\n", blend_func);
103 assert(0);
104 break;
105 }
106 return 0;
107 }
108
109 static uint32_t r600_translate_blend_factor(int blend_fact)
110 {
111 switch (blend_fact) {
112 case PIPE_BLENDFACTOR_ONE:
113 return V_028780_BLEND_ONE;
114 case PIPE_BLENDFACTOR_SRC_COLOR:
115 return V_028780_BLEND_SRC_COLOR;
116 case PIPE_BLENDFACTOR_SRC_ALPHA:
117 return V_028780_BLEND_SRC_ALPHA;
118 case PIPE_BLENDFACTOR_DST_ALPHA:
119 return V_028780_BLEND_DST_ALPHA;
120 case PIPE_BLENDFACTOR_DST_COLOR:
121 return V_028780_BLEND_DST_COLOR;
122 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123 return V_028780_BLEND_SRC_ALPHA_SATURATE;
124 case PIPE_BLENDFACTOR_CONST_COLOR:
125 return V_028780_BLEND_CONST_COLOR;
126 case PIPE_BLENDFACTOR_CONST_ALPHA:
127 return V_028780_BLEND_CONST_ALPHA;
128 case PIPE_BLENDFACTOR_ZERO:
129 return V_028780_BLEND_ZERO;
130 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136 case PIPE_BLENDFACTOR_INV_DST_COLOR:
137 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_SRC1_COLOR:
143 return V_028780_BLEND_SRC1_COLOR;
144 case PIPE_BLENDFACTOR_SRC1_ALPHA:
145 return V_028780_BLEND_SRC1_ALPHA;
146 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147 return V_028780_BLEND_INV_SRC1_COLOR;
148 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149 return V_028780_BLEND_INV_SRC1_ALPHA;
150 default:
151 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152 assert(0);
153 break;
154 }
155 return 0;
156 }
157
158 static unsigned r600_tex_dim(unsigned dim)
159 {
160 switch (dim) {
161 default:
162 case PIPE_TEXTURE_1D:
163 return V_030000_SQ_TEX_DIM_1D;
164 case PIPE_TEXTURE_1D_ARRAY:
165 return V_030000_SQ_TEX_DIM_1D_ARRAY;
166 case PIPE_TEXTURE_2D:
167 case PIPE_TEXTURE_RECT:
168 return V_030000_SQ_TEX_DIM_2D;
169 case PIPE_TEXTURE_2D_ARRAY:
170 return V_030000_SQ_TEX_DIM_2D_ARRAY;
171 case PIPE_TEXTURE_3D:
172 return V_030000_SQ_TEX_DIM_3D;
173 case PIPE_TEXTURE_CUBE:
174 return V_030000_SQ_TEX_DIM_CUBEMAP;
175 }
176 }
177
178 static uint32_t r600_translate_dbformat(enum pipe_format format)
179 {
180 switch (format) {
181 case PIPE_FORMAT_Z16_UNORM:
182 return V_028040_Z_16;
183 case PIPE_FORMAT_Z24X8_UNORM:
184 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
185 return V_028040_Z_24;
186 case PIPE_FORMAT_Z32_FLOAT:
187 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
188 return V_028040_Z_32_FLOAT;
189 default:
190 return ~0U;
191 }
192 }
193
194 static uint32_t r600_translate_colorswap(enum pipe_format format)
195 {
196 switch (format) {
197 /* 8-bit buffers. */
198 case PIPE_FORMAT_L4A4_UNORM:
199 case PIPE_FORMAT_A4R4_UNORM:
200 return V_028C70_SWAP_ALT;
201
202 case PIPE_FORMAT_A8_UNORM:
203 case PIPE_FORMAT_A8_SNORM:
204 case PIPE_FORMAT_A8_UINT:
205 case PIPE_FORMAT_A8_SINT:
206 case PIPE_FORMAT_A16_UNORM:
207 case PIPE_FORMAT_A16_SNORM:
208 case PIPE_FORMAT_A16_UINT:
209 case PIPE_FORMAT_A16_SINT:
210 case PIPE_FORMAT_A16_FLOAT:
211 case PIPE_FORMAT_A32_UINT:
212 case PIPE_FORMAT_A32_SINT:
213 case PIPE_FORMAT_A32_FLOAT:
214 case PIPE_FORMAT_R4A4_UNORM:
215 return V_028C70_SWAP_ALT_REV;
216 case PIPE_FORMAT_I8_UNORM:
217 case PIPE_FORMAT_I8_SNORM:
218 case PIPE_FORMAT_I8_UINT:
219 case PIPE_FORMAT_I8_SINT:
220 case PIPE_FORMAT_I16_UNORM:
221 case PIPE_FORMAT_I16_SNORM:
222 case PIPE_FORMAT_I16_UINT:
223 case PIPE_FORMAT_I16_SINT:
224 case PIPE_FORMAT_I16_FLOAT:
225 case PIPE_FORMAT_I32_UINT:
226 case PIPE_FORMAT_I32_SINT:
227 case PIPE_FORMAT_I32_FLOAT:
228 case PIPE_FORMAT_L8_UNORM:
229 case PIPE_FORMAT_L8_SNORM:
230 case PIPE_FORMAT_L8_UINT:
231 case PIPE_FORMAT_L8_SINT:
232 case PIPE_FORMAT_L8_SRGB:
233 case PIPE_FORMAT_L16_UNORM:
234 case PIPE_FORMAT_L16_SNORM:
235 case PIPE_FORMAT_L16_UINT:
236 case PIPE_FORMAT_L16_SINT:
237 case PIPE_FORMAT_L16_FLOAT:
238 case PIPE_FORMAT_L32_UINT:
239 case PIPE_FORMAT_L32_SINT:
240 case PIPE_FORMAT_L32_FLOAT:
241 case PIPE_FORMAT_R8_UNORM:
242 case PIPE_FORMAT_R8_SNORM:
243 case PIPE_FORMAT_R8_UINT:
244 case PIPE_FORMAT_R8_SINT:
245 return V_028C70_SWAP_STD;
246
247 /* 16-bit buffers. */
248 case PIPE_FORMAT_B5G6R5_UNORM:
249 return V_028C70_SWAP_STD_REV;
250
251 case PIPE_FORMAT_B5G5R5A1_UNORM:
252 case PIPE_FORMAT_B5G5R5X1_UNORM:
253 return V_028C70_SWAP_ALT;
254
255 case PIPE_FORMAT_B4G4R4A4_UNORM:
256 case PIPE_FORMAT_B4G4R4X4_UNORM:
257 return V_028C70_SWAP_ALT;
258
259 case PIPE_FORMAT_Z16_UNORM:
260 return V_028C70_SWAP_STD;
261
262 case PIPE_FORMAT_L8A8_UNORM:
263 case PIPE_FORMAT_L8A8_SNORM:
264 case PIPE_FORMAT_L8A8_UINT:
265 case PIPE_FORMAT_L8A8_SINT:
266 case PIPE_FORMAT_L8A8_SRGB:
267 case PIPE_FORMAT_L16A16_UNORM:
268 case PIPE_FORMAT_L16A16_SNORM:
269 case PIPE_FORMAT_L16A16_UINT:
270 case PIPE_FORMAT_L16A16_SINT:
271 case PIPE_FORMAT_L16A16_FLOAT:
272 case PIPE_FORMAT_L32A32_UINT:
273 case PIPE_FORMAT_L32A32_SINT:
274 case PIPE_FORMAT_L32A32_FLOAT:
275 return V_028C70_SWAP_ALT;
276 case PIPE_FORMAT_R8G8_UNORM:
277 case PIPE_FORMAT_R8G8_SNORM:
278 case PIPE_FORMAT_R8G8_UINT:
279 case PIPE_FORMAT_R8G8_SINT:
280 return V_028C70_SWAP_STD;
281
282 case PIPE_FORMAT_R16_UNORM:
283 case PIPE_FORMAT_R16_SNORM:
284 case PIPE_FORMAT_R16_UINT:
285 case PIPE_FORMAT_R16_SINT:
286 case PIPE_FORMAT_R16_FLOAT:
287 return V_028C70_SWAP_STD;
288
289 /* 32-bit buffers. */
290 case PIPE_FORMAT_A8B8G8R8_SRGB:
291 return V_028C70_SWAP_STD_REV;
292 case PIPE_FORMAT_B8G8R8A8_SRGB:
293 return V_028C70_SWAP_ALT;
294
295 case PIPE_FORMAT_B8G8R8A8_UNORM:
296 case PIPE_FORMAT_B8G8R8X8_UNORM:
297 return V_028C70_SWAP_ALT;
298
299 case PIPE_FORMAT_A8R8G8B8_UNORM:
300 case PIPE_FORMAT_X8R8G8B8_UNORM:
301 return V_028C70_SWAP_ALT_REV;
302 case PIPE_FORMAT_R8G8B8A8_SNORM:
303 case PIPE_FORMAT_R8G8B8A8_UNORM:
304 case PIPE_FORMAT_R8G8B8A8_SINT:
305 case PIPE_FORMAT_R8G8B8A8_UINT:
306 case PIPE_FORMAT_R8G8B8X8_UNORM:
307 return V_028C70_SWAP_STD;
308
309 case PIPE_FORMAT_A8B8G8R8_UNORM:
310 case PIPE_FORMAT_X8B8G8R8_UNORM:
311 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
312 return V_028C70_SWAP_STD_REV;
313
314 case PIPE_FORMAT_Z24X8_UNORM:
315 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
316 return V_028C70_SWAP_STD;
317
318 case PIPE_FORMAT_X8Z24_UNORM:
319 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
320 return V_028C70_SWAP_STD;
321
322 case PIPE_FORMAT_R10G10B10A2_UNORM:
323 case PIPE_FORMAT_R10G10B10X2_SNORM:
324 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
325 return V_028C70_SWAP_STD;
326
327 case PIPE_FORMAT_B10G10R10A2_UNORM:
328 case PIPE_FORMAT_B10G10R10A2_UINT:
329 return V_028C70_SWAP_ALT;
330
331 case PIPE_FORMAT_R11G11B10_FLOAT:
332 case PIPE_FORMAT_R32_FLOAT:
333 case PIPE_FORMAT_R32_UINT:
334 case PIPE_FORMAT_R32_SINT:
335 case PIPE_FORMAT_Z32_FLOAT:
336 case PIPE_FORMAT_R16G16_FLOAT:
337 case PIPE_FORMAT_R16G16_UNORM:
338 case PIPE_FORMAT_R16G16_SNORM:
339 case PIPE_FORMAT_R16G16_UINT:
340 case PIPE_FORMAT_R16G16_SINT:
341 case PIPE_FORMAT_R16G16B16_FLOAT:
342 case PIPE_FORMAT_R32G32B32_FLOAT:
343 return V_028C70_SWAP_STD;
344
345 /* 64-bit buffers. */
346 case PIPE_FORMAT_R32G32_FLOAT:
347 case PIPE_FORMAT_R32G32_UINT:
348 case PIPE_FORMAT_R32G32_SINT:
349 case PIPE_FORMAT_R16G16B16A16_UNORM:
350 case PIPE_FORMAT_R16G16B16A16_SNORM:
351 case PIPE_FORMAT_R16G16B16A16_UINT:
352 case PIPE_FORMAT_R16G16B16A16_SINT:
353 case PIPE_FORMAT_R16G16B16A16_FLOAT:
354 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
355
356 /* 128-bit buffers. */
357 case PIPE_FORMAT_R32G32B32A32_FLOAT:
358 case PIPE_FORMAT_R32G32B32A32_SNORM:
359 case PIPE_FORMAT_R32G32B32A32_UNORM:
360 case PIPE_FORMAT_R32G32B32A32_SINT:
361 case PIPE_FORMAT_R32G32B32A32_UINT:
362 return V_028C70_SWAP_STD;
363 default:
364 R600_ERR("unsupported colorswap format %d\n", format);
365 return ~0U;
366 }
367 return ~0U;
368 }
369
370 static uint32_t r600_translate_colorformat(enum pipe_format format)
371 {
372 switch (format) {
373 /* 8-bit buffers. */
374 case PIPE_FORMAT_A8_UNORM:
375 case PIPE_FORMAT_A8_SNORM:
376 case PIPE_FORMAT_A8_UINT:
377 case PIPE_FORMAT_A8_SINT:
378 case PIPE_FORMAT_I8_UNORM:
379 case PIPE_FORMAT_I8_SNORM:
380 case PIPE_FORMAT_I8_UINT:
381 case PIPE_FORMAT_I8_SINT:
382 case PIPE_FORMAT_L8_UNORM:
383 case PIPE_FORMAT_L8_SNORM:
384 case PIPE_FORMAT_L8_UINT:
385 case PIPE_FORMAT_L8_SINT:
386 case PIPE_FORMAT_L8_SRGB:
387 case PIPE_FORMAT_R8_UNORM:
388 case PIPE_FORMAT_R8_SNORM:
389 case PIPE_FORMAT_R8_UINT:
390 case PIPE_FORMAT_R8_SINT:
391 return V_028C70_COLOR_8;
392
393 /* 16-bit buffers. */
394 case PIPE_FORMAT_B5G6R5_UNORM:
395 return V_028C70_COLOR_5_6_5;
396
397 case PIPE_FORMAT_B5G5R5A1_UNORM:
398 case PIPE_FORMAT_B5G5R5X1_UNORM:
399 return V_028C70_COLOR_1_5_5_5;
400
401 case PIPE_FORMAT_B4G4R4A4_UNORM:
402 case PIPE_FORMAT_B4G4R4X4_UNORM:
403 return V_028C70_COLOR_4_4_4_4;
404
405 case PIPE_FORMAT_Z16_UNORM:
406 return V_028C70_COLOR_16;
407
408 case PIPE_FORMAT_L8A8_UNORM:
409 case PIPE_FORMAT_L8A8_SNORM:
410 case PIPE_FORMAT_L8A8_UINT:
411 case PIPE_FORMAT_L8A8_SINT:
412 case PIPE_FORMAT_L8A8_SRGB:
413 case PIPE_FORMAT_R8G8_UNORM:
414 case PIPE_FORMAT_R8G8_SNORM:
415 case PIPE_FORMAT_R8G8_UINT:
416 case PIPE_FORMAT_R8G8_SINT:
417 return V_028C70_COLOR_8_8;
418
419 case PIPE_FORMAT_R16_UNORM:
420 case PIPE_FORMAT_R16_SNORM:
421 case PIPE_FORMAT_R16_UINT:
422 case PIPE_FORMAT_R16_SINT:
423 case PIPE_FORMAT_A16_UNORM:
424 case PIPE_FORMAT_A16_SNORM:
425 case PIPE_FORMAT_A16_UINT:
426 case PIPE_FORMAT_A16_SINT:
427 case PIPE_FORMAT_L16_UNORM:
428 case PIPE_FORMAT_L16_SNORM:
429 case PIPE_FORMAT_L16_UINT:
430 case PIPE_FORMAT_L16_SINT:
431 case PIPE_FORMAT_I16_UNORM:
432 case PIPE_FORMAT_I16_SNORM:
433 case PIPE_FORMAT_I16_UINT:
434 case PIPE_FORMAT_I16_SINT:
435 return V_028C70_COLOR_16;
436
437 case PIPE_FORMAT_R16_FLOAT:
438 case PIPE_FORMAT_A16_FLOAT:
439 case PIPE_FORMAT_L16_FLOAT:
440 case PIPE_FORMAT_I16_FLOAT:
441 return V_028C70_COLOR_16_FLOAT;
442
443 /* 32-bit buffers. */
444 case PIPE_FORMAT_A8B8G8R8_SRGB:
445 case PIPE_FORMAT_A8B8G8R8_UNORM:
446 case PIPE_FORMAT_A8R8G8B8_UNORM:
447 case PIPE_FORMAT_B8G8R8A8_SRGB:
448 case PIPE_FORMAT_B8G8R8A8_UNORM:
449 case PIPE_FORMAT_B8G8R8X8_UNORM:
450 case PIPE_FORMAT_R8G8B8A8_SNORM:
451 case PIPE_FORMAT_R8G8B8A8_UNORM:
452 case PIPE_FORMAT_R8G8B8X8_UNORM:
453 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
454 case PIPE_FORMAT_X8B8G8R8_UNORM:
455 case PIPE_FORMAT_X8R8G8B8_UNORM:
456 case PIPE_FORMAT_R8G8B8_UNORM:
457 case PIPE_FORMAT_R8G8B8A8_SINT:
458 case PIPE_FORMAT_R8G8B8A8_UINT:
459 return V_028C70_COLOR_8_8_8_8;
460
461 case PIPE_FORMAT_R10G10B10A2_UNORM:
462 case PIPE_FORMAT_R10G10B10X2_SNORM:
463 case PIPE_FORMAT_B10G10R10A2_UNORM:
464 case PIPE_FORMAT_B10G10R10A2_UINT:
465 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
466 return V_028C70_COLOR_2_10_10_10;
467
468 case PIPE_FORMAT_Z24X8_UNORM:
469 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
470 return V_028C70_COLOR_8_24;
471
472 case PIPE_FORMAT_X8Z24_UNORM:
473 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
474 return V_028C70_COLOR_24_8;
475
476 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
477 return V_028C70_COLOR_X24_8_32_FLOAT;
478
479 case PIPE_FORMAT_R32_UINT:
480 case PIPE_FORMAT_R32_SINT:
481 case PIPE_FORMAT_A32_UINT:
482 case PIPE_FORMAT_A32_SINT:
483 case PIPE_FORMAT_L32_UINT:
484 case PIPE_FORMAT_L32_SINT:
485 case PIPE_FORMAT_I32_UINT:
486 case PIPE_FORMAT_I32_SINT:
487 return V_028C70_COLOR_32;
488
489 case PIPE_FORMAT_R32_FLOAT:
490 case PIPE_FORMAT_A32_FLOAT:
491 case PIPE_FORMAT_L32_FLOAT:
492 case PIPE_FORMAT_I32_FLOAT:
493 case PIPE_FORMAT_Z32_FLOAT:
494 return V_028C70_COLOR_32_FLOAT;
495
496 case PIPE_FORMAT_R16G16_FLOAT:
497 case PIPE_FORMAT_L16A16_FLOAT:
498 return V_028C70_COLOR_16_16_FLOAT;
499
500 case PIPE_FORMAT_R16G16_UNORM:
501 case PIPE_FORMAT_R16G16_SNORM:
502 case PIPE_FORMAT_R16G16_UINT:
503 case PIPE_FORMAT_R16G16_SINT:
504 case PIPE_FORMAT_L16A16_UNORM:
505 case PIPE_FORMAT_L16A16_SNORM:
506 case PIPE_FORMAT_L16A16_UINT:
507 case PIPE_FORMAT_L16A16_SINT:
508 return V_028C70_COLOR_16_16;
509
510 case PIPE_FORMAT_R11G11B10_FLOAT:
511 return V_028C70_COLOR_10_11_11_FLOAT;
512
513 /* 64-bit buffers. */
514 case PIPE_FORMAT_R16G16B16A16_UINT:
515 case PIPE_FORMAT_R16G16B16A16_SINT:
516 case PIPE_FORMAT_R16G16B16A16_UNORM:
517 case PIPE_FORMAT_R16G16B16A16_SNORM:
518 return V_028C70_COLOR_16_16_16_16;
519
520 case PIPE_FORMAT_R16G16B16_FLOAT:
521 case PIPE_FORMAT_R16G16B16A16_FLOAT:
522 return V_028C70_COLOR_16_16_16_16_FLOAT;
523
524 case PIPE_FORMAT_R32G32_FLOAT:
525 case PIPE_FORMAT_L32A32_FLOAT:
526 return V_028C70_COLOR_32_32_FLOAT;
527
528 case PIPE_FORMAT_R32G32_SINT:
529 case PIPE_FORMAT_R32G32_UINT:
530 case PIPE_FORMAT_L32A32_UINT:
531 case PIPE_FORMAT_L32A32_SINT:
532 return V_028C70_COLOR_32_32;
533
534 /* 96-bit buffers. */
535 case PIPE_FORMAT_R32G32B32_FLOAT:
536 return V_028C70_COLOR_32_32_32_FLOAT;
537
538 /* 128-bit buffers. */
539 case PIPE_FORMAT_R32G32B32A32_SNORM:
540 case PIPE_FORMAT_R32G32B32A32_UNORM:
541 case PIPE_FORMAT_R32G32B32A32_SINT:
542 case PIPE_FORMAT_R32G32B32A32_UINT:
543 return V_028C70_COLOR_32_32_32_32;
544 case PIPE_FORMAT_R32G32B32A32_FLOAT:
545 return V_028C70_COLOR_32_32_32_32_FLOAT;
546
547 /* YUV buffers. */
548 case PIPE_FORMAT_UYVY:
549 case PIPE_FORMAT_YUYV:
550 default:
551 return ~0U; /* Unsupported. */
552 }
553 }
554
555 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
556 {
557 if (R600_BIG_ENDIAN) {
558 switch(colorformat) {
559
560 /* 8-bit buffers. */
561 case V_028C70_COLOR_8:
562 return ENDIAN_NONE;
563
564 /* 16-bit buffers. */
565 case V_028C70_COLOR_5_6_5:
566 case V_028C70_COLOR_1_5_5_5:
567 case V_028C70_COLOR_4_4_4_4:
568 case V_028C70_COLOR_16:
569 case V_028C70_COLOR_8_8:
570 return ENDIAN_8IN16;
571
572 /* 32-bit buffers. */
573 case V_028C70_COLOR_8_8_8_8:
574 case V_028C70_COLOR_2_10_10_10:
575 case V_028C70_COLOR_8_24:
576 case V_028C70_COLOR_24_8:
577 case V_028C70_COLOR_32_FLOAT:
578 case V_028C70_COLOR_16_16_FLOAT:
579 case V_028C70_COLOR_16_16:
580 return ENDIAN_8IN32;
581
582 /* 64-bit buffers. */
583 case V_028C70_COLOR_16_16_16_16:
584 case V_028C70_COLOR_16_16_16_16_FLOAT:
585 return ENDIAN_8IN16;
586
587 case V_028C70_COLOR_32_32_FLOAT:
588 case V_028C70_COLOR_32_32:
589 case V_028C70_COLOR_X24_8_32_FLOAT:
590 return ENDIAN_8IN32;
591
592 /* 96-bit buffers. */
593 case V_028C70_COLOR_32_32_32_FLOAT:
594 /* 128-bit buffers. */
595 case V_028C70_COLOR_32_32_32_32_FLOAT:
596 case V_028C70_COLOR_32_32_32_32:
597 return ENDIAN_8IN32;
598 default:
599 return ENDIAN_NONE; /* Unsupported. */
600 }
601 } else {
602 return ENDIAN_NONE;
603 }
604 }
605
606 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
607 {
608 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
609 }
610
611 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
612 {
613 return r600_translate_colorformat(format) != ~0U &&
614 r600_translate_colorswap(format) != ~0U;
615 }
616
617 static bool r600_is_zs_format_supported(enum pipe_format format)
618 {
619 return r600_translate_dbformat(format) != ~0U;
620 }
621
622 boolean evergreen_is_format_supported(struct pipe_screen *screen,
623 enum pipe_format format,
624 enum pipe_texture_target target,
625 unsigned sample_count,
626 unsigned usage)
627 {
628 unsigned retval = 0;
629
630 if (target >= PIPE_MAX_TEXTURE_TYPES) {
631 R600_ERR("r600: unsupported texture type %d\n", target);
632 return FALSE;
633 }
634
635 if (!util_format_is_supported(format, usage))
636 return FALSE;
637
638 /* Multisample */
639 if (sample_count > 1)
640 return FALSE;
641
642 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
643 r600_is_sampler_format_supported(screen, format)) {
644 retval |= PIPE_BIND_SAMPLER_VIEW;
645 }
646
647 if ((usage & (PIPE_BIND_RENDER_TARGET |
648 PIPE_BIND_DISPLAY_TARGET |
649 PIPE_BIND_SCANOUT |
650 PIPE_BIND_SHARED)) &&
651 r600_is_colorbuffer_format_supported(format)) {
652 retval |= usage &
653 (PIPE_BIND_RENDER_TARGET |
654 PIPE_BIND_DISPLAY_TARGET |
655 PIPE_BIND_SCANOUT |
656 PIPE_BIND_SHARED);
657 }
658
659 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
660 r600_is_zs_format_supported(format)) {
661 retval |= PIPE_BIND_DEPTH_STENCIL;
662 }
663
664 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
665 r600_is_vertex_format_supported(format)) {
666 retval |= PIPE_BIND_VERTEX_BUFFER;
667 }
668
669 if (usage & PIPE_BIND_TRANSFER_READ)
670 retval |= PIPE_BIND_TRANSFER_READ;
671 if (usage & PIPE_BIND_TRANSFER_WRITE)
672 retval |= PIPE_BIND_TRANSFER_WRITE;
673
674 return retval == usage;
675 }
676
677 static void *evergreen_create_blend_state(struct pipe_context *ctx,
678 const struct pipe_blend_state *state)
679 {
680 struct r600_context *rctx = (struct r600_context *)ctx;
681 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
682 struct r600_pipe_state *rstate;
683 uint32_t color_control, target_mask;
684 /* XXX there is more then 8 framebuffer */
685 unsigned blend_cntl[8];
686
687 if (blend == NULL) {
688 return NULL;
689 }
690
691 rstate = &blend->rstate;
692
693 rstate->id = R600_PIPE_STATE_BLEND;
694
695 target_mask = 0;
696 color_control = S_028808_MODE(1);
697 if (state->logicop_enable) {
698 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
699 } else {
700 color_control |= (0xcc << 16);
701 }
702 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
703 if (state->independent_blend_enable) {
704 for (int i = 0; i < 8; i++) {
705 target_mask |= (state->rt[i].colormask << (4 * i));
706 }
707 } else {
708 for (int i = 0; i < 8; i++) {
709 target_mask |= (state->rt[0].colormask << (4 * i));
710 }
711 }
712 blend->cb_target_mask = target_mask;
713
714 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
715 color_control);
716 /* only have dual source on MRT0 */
717 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
718 for (int i = 0; i < 8; i++) {
719 /* state->rt entries > 0 only written if independent blending */
720 const int j = state->independent_blend_enable ? i : 0;
721
722 unsigned eqRGB = state->rt[j].rgb_func;
723 unsigned srcRGB = state->rt[j].rgb_src_factor;
724 unsigned dstRGB = state->rt[j].rgb_dst_factor;
725 unsigned eqA = state->rt[j].alpha_func;
726 unsigned srcA = state->rt[j].alpha_src_factor;
727 unsigned dstA = state->rt[j].alpha_dst_factor;
728
729 blend_cntl[i] = 0;
730 if (!state->rt[j].blend_enable)
731 continue;
732
733 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
734 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
735 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
736 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
737
738 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
739 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
740 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
741 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
742 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
743 }
744 }
745 for (int i = 0; i < 8; i++) {
746 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
747 }
748
749 return rstate;
750 }
751
752 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
753 const struct pipe_depth_stencil_alpha_state *state)
754 {
755 struct r600_context *rctx = (struct r600_context *)ctx;
756 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
757 unsigned db_depth_control, alpha_test_control, alpha_ref;
758 unsigned db_render_control;
759 struct r600_pipe_state *rstate;
760
761 if (dsa == NULL) {
762 return NULL;
763 }
764
765 dsa->valuemask[0] = state->stencil[0].valuemask;
766 dsa->valuemask[1] = state->stencil[1].valuemask;
767 dsa->writemask[0] = state->stencil[0].writemask;
768 dsa->writemask[1] = state->stencil[1].writemask;
769
770 rstate = &dsa->rstate;
771
772 rstate->id = R600_PIPE_STATE_DSA;
773 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
774 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
775 S_028800_ZFUNC(state->depth.func);
776
777 /* stencil */
778 if (state->stencil[0].enabled) {
779 db_depth_control |= S_028800_STENCIL_ENABLE(1);
780 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
781 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
782 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
783 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
784
785 if (state->stencil[1].enabled) {
786 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
787 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
788 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
789 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
790 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
791 }
792 }
793
794 /* alpha */
795 alpha_test_control = 0;
796 alpha_ref = 0;
797 if (state->alpha.enabled) {
798 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
799 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
800 alpha_ref = fui(state->alpha.ref_value);
801 }
802 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
803 dsa->alpha_ref = alpha_ref;
804
805 /* misc */
806 db_render_control = 0;
807 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
808 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control);
809 return rstate;
810 }
811
812 static void *evergreen_create_rs_state(struct pipe_context *ctx,
813 const struct pipe_rasterizer_state *state)
814 {
815 struct r600_context *rctx = (struct r600_context *)ctx;
816 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
817 struct r600_pipe_state *rstate;
818 unsigned tmp;
819 unsigned prov_vtx = 1, polygon_dual_mode;
820 float psize_min, psize_max;
821
822 if (rs == NULL) {
823 return NULL;
824 }
825
826 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
827 state->fill_back != PIPE_POLYGON_MODE_FILL);
828
829 if (state->flatshade_first)
830 prov_vtx = 0;
831
832 rstate = &rs->rstate;
833 rs->flatshade = state->flatshade;
834 rs->sprite_coord_enable = state->sprite_coord_enable;
835 rs->two_side = state->light_twoside;
836 rs->clip_plane_enable = state->clip_plane_enable;
837 rs->pa_sc_line_stipple = state->line_stipple_enable ?
838 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
839 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
840 rs->pa_cl_clip_cntl =
841 S_028810_PS_UCP_MODE(3) |
842 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
843 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
844 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
845
846 /* offset */
847 rs->offset_units = state->offset_units;
848 rs->offset_scale = state->offset_scale * 12.0f;
849
850 rstate->id = R600_PIPE_STATE_RASTERIZER;
851 tmp = S_0286D4_FLAT_SHADE_ENA(1);
852 if (state->sprite_coord_enable) {
853 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
854 S_0286D4_PNT_SPRITE_OVRD_X(2) |
855 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
856 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
857 S_0286D4_PNT_SPRITE_OVRD_W(1);
858 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
859 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
860 }
861 }
862 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
863
864 /* point size 12.4 fixed point */
865 tmp = (unsigned)(state->point_size * 8.0);
866 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
867
868 if (state->point_size_per_vertex) {
869 psize_min = util_get_min_point_size(state);
870 psize_max = 8192;
871 } else {
872 /* Force the point size to be as if the vertex output was disabled. */
873 psize_min = state->point_size;
874 psize_max = state->point_size;
875 }
876 /* Divide by two, because 0.5 = 1 pixel. */
877 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
878 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
879 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
880
881 tmp = (unsigned)state->line_width * 8;
882 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
883 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
884 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
885 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
886
887 if (rctx->chip_class == CAYMAN) {
888 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
889 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
890 } else {
891 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
892 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
893 }
894 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
895 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
896 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
897 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
898 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
899 S_028814_FACE(!state->front_ccw) |
900 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
901 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
902 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
903 S_028814_POLY_MODE(polygon_dual_mode) |
904 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
905 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
906 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
907 return rstate;
908 }
909
910 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
911 const struct pipe_sampler_state *state)
912 {
913 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
914 union util_color uc;
915 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
916
917 if (rstate == NULL) {
918 return NULL;
919 }
920
921 rstate->id = R600_PIPE_STATE_SAMPLER;
922 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
923 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
924 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
925 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
926 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
927 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
928 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
929 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
930 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
931 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
932 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
933 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
934 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
935 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
936 NULL, 0);
937 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
938 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
939 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
940 S_03C008_TYPE(1),
941 NULL, 0);
942
943 if (uc.ui) {
944 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
945 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
946 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
947 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
948 }
949 return rstate;
950 }
951
952 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
953 struct pipe_resource *texture,
954 const struct pipe_sampler_view *state)
955 {
956 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
957 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
958 struct r600_pipe_resource_state *rstate;
959 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
960 unsigned format, endian;
961 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
962 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
963 unsigned height, depth, width;
964 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
965
966 if (view == NULL)
967 return NULL;
968 rstate = &view->state;
969
970 /* initialize base object */
971 view->base = *state;
972 view->base.texture = NULL;
973 pipe_reference(NULL, &texture->reference);
974 view->base.texture = texture;
975 view->base.reference.count = 1;
976 view->base.context = ctx;
977
978 swizzle[0] = state->swizzle_r;
979 swizzle[1] = state->swizzle_g;
980 swizzle[2] = state->swizzle_b;
981 swizzle[3] = state->swizzle_a;
982
983 format = r600_translate_texformat(ctx->screen, state->format,
984 swizzle,
985 &word4, &yuv_format);
986 assert(format != ~0);
987 if (format == ~0) {
988 FREE(view);
989 return NULL;
990 }
991
992 if (tmp->is_depth && !tmp->is_flushing_texture) {
993 r600_init_flushed_depth_texture(ctx, texture);
994 tmp = tmp->flushed_depth_texture;
995 if (!tmp) {
996 FREE(view);
997 return NULL;
998 }
999 }
1000
1001 endian = r600_colorformat_endian_swap(format);
1002
1003 if (!rscreen->use_surface_alloc) {
1004 height = texture->height0;
1005 depth = texture->depth0;
1006 width = texture->width0;
1007 pitch = align(tmp->pitch_in_blocks[0] *
1008 util_format_get_blockwidth(state->format), 8);
1009 array_mode = tmp->array_mode[0];
1010 tile_type = tmp->tile_type;
1011 tile_split = 0;
1012 macro_aspect = 0;
1013 bankw = 0;
1014 bankh = 0;
1015 } else {
1016 width = tmp->surface.level[0].npix_x;
1017 height = tmp->surface.level[0].npix_y;
1018 depth = tmp->surface.level[0].npix_z;
1019 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1020 tile_type = tmp->tile_type;
1021
1022 switch (tmp->surface.level[0].mode) {
1023 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1024 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1025 break;
1026 case RADEON_SURF_MODE_2D:
1027 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1028 break;
1029 case RADEON_SURF_MODE_1D:
1030 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1031 break;
1032 case RADEON_SURF_MODE_LINEAR:
1033 default:
1034 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1035 break;
1036 }
1037 tile_split = tmp->surface.tile_split;
1038 macro_aspect = tmp->surface.mtilea;
1039 bankw = tmp->surface.bankw;
1040 bankh = tmp->surface.bankh;
1041 tile_split = eg_tile_split(tile_split);
1042 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1043 bankw = eg_bank_wh(bankw);
1044 bankh = eg_bank_wh(bankh);
1045 }
1046 /* 128 bit formats require tile type = 1 */
1047 if (rscreen->chip_class == CAYMAN) {
1048 if (util_format_get_blocksize(state->format) >= 16)
1049 tile_type = 1;
1050 }
1051 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1052
1053 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1054 height = 1;
1055 depth = texture->array_size;
1056 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1057 depth = texture->array_size;
1058 }
1059
1060 rstate->bo[0] = &tmp->resource;
1061 rstate->bo[1] = &tmp->resource;
1062 rstate->bo_usage[0] = RADEON_USAGE_READ;
1063 rstate->bo_usage[1] = RADEON_USAGE_READ;
1064
1065 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1066 S_030000_PITCH((pitch / 8) - 1) |
1067 S_030000_TEX_WIDTH(width - 1));
1068 if (rscreen->chip_class == CAYMAN)
1069 rstate->val[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1070 else
1071 rstate->val[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1072 rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1073 S_030004_TEX_DEPTH(depth - 1) |
1074 S_030004_ARRAY_MODE(array_mode));
1075 rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1076 if (state->u.tex.last_level) {
1077 rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1078 } else {
1079 rstate->val[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1080 }
1081 rstate->val[4] = (word4 |
1082 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1083 S_030010_ENDIAN_SWAP(endian) |
1084 S_030010_BASE_LEVEL(state->u.tex.first_level));
1085 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1086 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1087 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1088 /* aniso max 16 samples */
1089 rstate->val[6] = (S_030018_MAX_ANISO(4)) |
1090 (S_030018_TILE_SPLIT(tile_split));
1091 rstate->val[7] = S_03001C_DATA_FORMAT(format) |
1092 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1093 S_03001C_BANK_WIDTH(bankw) |
1094 S_03001C_BANK_HEIGHT(bankh) |
1095 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1096 S_03001C_NUM_BANKS(nbanks);
1097
1098 return &view->base;
1099 }
1100
1101 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1102 struct pipe_sampler_view **views)
1103 {
1104 struct r600_context *rctx = (struct r600_context *)ctx;
1105 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1106
1107 for (int i = 0; i < count; i++) {
1108 if (resource[i]) {
1109 r600_context_pipe_state_set_vs_resource(rctx, &resource[i]->state,
1110 i + R600_MAX_CONST_BUFFERS);
1111 }
1112 }
1113 }
1114
1115 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1116 struct pipe_sampler_view **views)
1117 {
1118 struct r600_context *rctx = (struct r600_context *)ctx;
1119 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1120 int i;
1121 int has_depth = 0;
1122
1123 for (i = 0; i < count; i++) {
1124 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1125 if (resource[i]) {
1126 if (((struct r600_resource_texture *)resource[i]->base.texture)->is_depth)
1127 has_depth = 1;
1128 r600_context_pipe_state_set_ps_resource(rctx, &resource[i]->state,
1129 i + R600_MAX_CONST_BUFFERS);
1130 } else
1131 r600_context_pipe_state_set_ps_resource(rctx, NULL,
1132 i + R600_MAX_CONST_BUFFERS);
1133
1134 pipe_sampler_view_reference(
1135 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1136 views[i]);
1137 } else {
1138 if (resource[i]) {
1139 if (((struct r600_resource_texture *)resource[i]->base.texture)->is_depth)
1140 has_depth = 1;
1141 }
1142 }
1143 }
1144 for (i = count; i < NUM_TEX_UNITS; i++) {
1145 if (rctx->ps_samplers.views[i]) {
1146 r600_context_pipe_state_set_ps_resource(rctx, NULL,
1147 i + R600_MAX_CONST_BUFFERS);
1148 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1149 }
1150 }
1151 rctx->have_depth_texture = has_depth;
1152 rctx->ps_samplers.n_views = count;
1153 }
1154
1155 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1156 {
1157 struct r600_context *rctx = (struct r600_context *)ctx;
1158 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1159
1160 if (count)
1161 r600_inval_texture_cache(rctx);
1162
1163 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1164 rctx->ps_samplers.n_samplers = count;
1165
1166 for (int i = 0; i < count; i++) {
1167 evergreen_context_pipe_state_set_ps_sampler(rctx, rstates[i], i);
1168 }
1169 }
1170
1171 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1172 {
1173 struct r600_context *rctx = (struct r600_context *)ctx;
1174 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1175
1176 if (count)
1177 r600_inval_texture_cache(rctx);
1178
1179 for (int i = 0; i < count; i++) {
1180 evergreen_context_pipe_state_set_vs_sampler(rctx, rstates[i], i);
1181 }
1182 }
1183
1184 static void evergreen_set_clip_state(struct pipe_context *ctx,
1185 const struct pipe_clip_state *state)
1186 {
1187 struct r600_context *rctx = (struct r600_context *)ctx;
1188 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1189 struct pipe_constant_buffer cb;
1190
1191 if (rstate == NULL)
1192 return;
1193
1194 rctx->clip = *state;
1195 rstate->id = R600_PIPE_STATE_CLIP;
1196 for (int i = 0; i < 6; i++) {
1197 r600_pipe_state_add_reg(rstate,
1198 R_0285BC_PA_CL_UCP0_X + i * 16,
1199 fui(state->ucp[i][0]));
1200 r600_pipe_state_add_reg(rstate,
1201 R_0285C0_PA_CL_UCP0_Y + i * 16,
1202 fui(state->ucp[i][1]) );
1203 r600_pipe_state_add_reg(rstate,
1204 R_0285C4_PA_CL_UCP0_Z + i * 16,
1205 fui(state->ucp[i][2]));
1206 r600_pipe_state_add_reg(rstate,
1207 R_0285C8_PA_CL_UCP0_W + i * 16,
1208 fui(state->ucp[i][3]));
1209 }
1210
1211 free(rctx->states[R600_PIPE_STATE_CLIP]);
1212 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1213 r600_context_pipe_state_set(rctx, rstate);
1214
1215 cb.buffer = NULL;
1216 cb.user_buffer = state->ucp;
1217 cb.buffer_offset = 0;
1218 cb.buffer_size = 4*4*8;
1219 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1220 pipe_resource_reference(&cb.buffer, NULL);
1221 }
1222
1223 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1224 const struct pipe_poly_stipple *state)
1225 {
1226 }
1227
1228 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1229 {
1230 }
1231
1232 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1233 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1234 uint32_t *tl, uint32_t *br)
1235 {
1236 /* EG hw workaround */
1237 if (br_x == 0)
1238 tl_x = 1;
1239 if (br_y == 0)
1240 tl_y = 1;
1241
1242 /* cayman hw workaround */
1243 if (rctx->chip_class == CAYMAN) {
1244 if (br_x == 1 && br_y == 1)
1245 br_x = 2;
1246 }
1247
1248 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1249 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1250 }
1251
1252 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1253 const struct pipe_scissor_state *state)
1254 {
1255 struct r600_context *rctx = (struct r600_context *)ctx;
1256 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1257 uint32_t tl, br;
1258
1259 if (rstate == NULL)
1260 return;
1261
1262 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1263
1264 rstate->id = R600_PIPE_STATE_SCISSOR;
1265 r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1266 r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1267
1268 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1269 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1270 r600_context_pipe_state_set(rctx, rstate);
1271 }
1272
1273 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1274 const struct pipe_viewport_state *state)
1275 {
1276 struct r600_context *rctx = (struct r600_context *)ctx;
1277 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1278
1279 if (rstate == NULL)
1280 return;
1281
1282 rctx->viewport = *state;
1283 rstate->id = R600_PIPE_STATE_VIEWPORT;
1284 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1285 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1286 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1287 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1288 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1289 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1290
1291 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1292 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1293 r600_context_pipe_state_set(rctx, rstate);
1294 }
1295
1296 static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1297 const struct pipe_framebuffer_state *state, int cb)
1298 {
1299 struct r600_screen *rscreen = rctx->screen;
1300 struct r600_resource_texture *rtex;
1301 struct r600_surface *surf;
1302 unsigned level = state->cbufs[cb]->u.tex.level;
1303 unsigned pitch, slice;
1304 unsigned color_info, color_attrib;
1305 unsigned format, swap, ntype, endian;
1306 uint64_t offset;
1307 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1308 const struct util_format_description *desc;
1309 int i;
1310 unsigned blend_clamp = 0, blend_bypass = 0;
1311
1312 surf = (struct r600_surface *)state->cbufs[cb];
1313 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1314
1315 if (rtex->is_depth)
1316 rctx->have_depth_fb = TRUE;
1317
1318 if (rtex->is_depth && !rtex->is_flushing_texture) {
1319 r600_init_flushed_depth_texture(&rctx->context, state->cbufs[cb]->texture);
1320 rtex = rtex->flushed_depth_texture;
1321 assert(rtex);
1322 }
1323
1324 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1325 if (!rscreen->use_surface_alloc) {
1326 offset = r600_texture_get_offset(rtex,
1327 level, state->cbufs[cb]->u.tex.first_layer);
1328 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1329 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1330 if (slice) {
1331 slice = slice - 1;
1332 }
1333 color_info = S_028C70_ARRAY_MODE(rtex->array_mode[level]);
1334 tile_split = 0;
1335 macro_aspect = 0;
1336 bankw = 0;
1337 bankh = 0;
1338 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1339 tile_type = rtex->tile_type;
1340 } else {
1341 /* workaround for linear buffers */
1342 tile_type = 1;
1343 }
1344 } else {
1345 offset = rtex->surface.level[level].offset;
1346 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1347 offset += rtex->surface.level[level].slice_size *
1348 state->cbufs[cb]->u.tex.first_layer;
1349 }
1350 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1351 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1352 if (slice) {
1353 slice = slice - 1;
1354 }
1355 color_info = 0;
1356 switch (rtex->surface.level[level].mode) {
1357 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1358 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1359 tile_type = 1;
1360 break;
1361 case RADEON_SURF_MODE_1D:
1362 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1363 tile_type = rtex->tile_type;
1364 break;
1365 case RADEON_SURF_MODE_2D:
1366 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1367 tile_type = rtex->tile_type;
1368 break;
1369 case RADEON_SURF_MODE_LINEAR:
1370 default:
1371 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1372 tile_type = 1;
1373 break;
1374 }
1375 tile_split = rtex->surface.tile_split;
1376 macro_aspect = rtex->surface.mtilea;
1377 bankw = rtex->surface.bankw;
1378 bankh = rtex->surface.bankh;
1379 tile_split = eg_tile_split(tile_split);
1380 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1381 bankw = eg_bank_wh(bankw);
1382 bankh = eg_bank_wh(bankh);
1383 }
1384 /* 128 bit formats require tile type = 1 */
1385 if (rscreen->chip_class == CAYMAN) {
1386 if (util_format_get_blocksize(surf->base.format) >= 16)
1387 tile_type = 1;
1388 }
1389 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1390 desc = util_format_description(surf->base.format);
1391 for (i = 0; i < 4; i++) {
1392 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1393 break;
1394 }
1395 }
1396
1397 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1398 S_028C74_NUM_BANKS(nbanks) |
1399 S_028C74_BANK_WIDTH(bankw) |
1400 S_028C74_BANK_HEIGHT(bankh) |
1401 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1402 S_028C74_NON_DISP_TILING_ORDER(tile_type);
1403
1404 ntype = V_028C70_NUMBER_UNORM;
1405 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1406 ntype = V_028C70_NUMBER_SRGB;
1407 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1408 if (desc->channel[i].normalized)
1409 ntype = V_028C70_NUMBER_SNORM;
1410 else if (desc->channel[i].pure_integer)
1411 ntype = V_028C70_NUMBER_SINT;
1412 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1413 if (desc->channel[i].normalized)
1414 ntype = V_028C70_NUMBER_UNORM;
1415 else if (desc->channel[i].pure_integer)
1416 ntype = V_028C70_NUMBER_UINT;
1417 }
1418
1419 format = r600_translate_colorformat(surf->base.format);
1420 assert(format != ~0);
1421
1422 swap = r600_translate_colorswap(surf->base.format);
1423 assert(swap != ~0);
1424
1425 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1426 endian = ENDIAN_NONE;
1427 } else {
1428 endian = r600_colorformat_endian_swap(format);
1429 }
1430
1431 /* blend clamp should be set for all NORM/SRGB types */
1432 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1433 ntype == V_028C70_NUMBER_SRGB)
1434 blend_clamp = 1;
1435
1436 /* set blend bypass according to docs if SINT/UINT or
1437 8/24 COLOR variants */
1438 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1439 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1440 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1441 blend_clamp = 0;
1442 blend_bypass = 1;
1443 }
1444
1445 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT)
1446 rctx->sx_alpha_test_control |= S_028410_ALPHA_TEST_BYPASS(1);
1447 else
1448 rctx->sx_alpha_test_control &= C_028410_ALPHA_TEST_BYPASS;
1449
1450 color_info |= S_028C70_FORMAT(format) |
1451 S_028C70_COMP_SWAP(swap) |
1452 S_028C70_BLEND_CLAMP(blend_clamp) |
1453 S_028C70_BLEND_BYPASS(blend_bypass) |
1454 S_028C70_NUMBER_TYPE(ntype) |
1455 S_028C70_ENDIAN(endian);
1456
1457 /* EXPORT_NORM is an optimzation that can be enabled for better
1458 * performance in certain cases.
1459 * EXPORT_NORM can be enabled if:
1460 * - 11-bit or smaller UNORM/SNORM/SRGB
1461 * - 16-bit or smaller FLOAT
1462 */
1463 /* XXX: This should probably be the same for all CBs if we want
1464 * useful alpha tests. */
1465 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1466 ((desc->channel[i].size < 12 &&
1467 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1468 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1469 (desc->channel[i].size < 17 &&
1470 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1471 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1472 } else {
1473 rctx->export_16bpc = false;
1474 }
1475 rctx->alpha_ref_dirty = true;
1476
1477 /* for possible dual-src MRT */
1478 if (cb == 0 && rctx->framebuffer.nr_cbufs == 1) {
1479 r600_pipe_state_add_reg_bo(rstate,
1480 R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1481 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1482 }
1483
1484 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1485 offset >>= 8;
1486
1487 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1488 r600_pipe_state_add_reg_bo(rstate,
1489 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1490 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1491 r600_pipe_state_add_reg(rstate,
1492 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1493 0x0);
1494 r600_pipe_state_add_reg_bo(rstate,
1495 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1496 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1497 r600_pipe_state_add_reg(rstate,
1498 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1499 S_028C64_PITCH_TILE_MAX(pitch));
1500 r600_pipe_state_add_reg(rstate,
1501 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1502 S_028C68_SLICE_TILE_MAX(slice));
1503 if (!rscreen->use_surface_alloc) {
1504 r600_pipe_state_add_reg(rstate,
1505 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1506 0x00000000);
1507 } else {
1508 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1509 r600_pipe_state_add_reg(rstate,
1510 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1511 0x00000000);
1512 } else {
1513 r600_pipe_state_add_reg(rstate,
1514 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1515 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1516 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1517 }
1518 }
1519 r600_pipe_state_add_reg_bo(rstate,
1520 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1521 color_attrib,
1522 &rtex->resource, RADEON_USAGE_READWRITE);
1523 }
1524
1525 static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1526 const struct pipe_framebuffer_state *state)
1527 {
1528 struct r600_screen *rscreen = rctx->screen;
1529 struct r600_resource_texture *rtex;
1530 struct r600_surface *surf;
1531 uint64_t offset;
1532 unsigned level, first_layer, pitch, slice, format, array_mode;
1533 unsigned macro_aspect, tile_split, bankh, bankw, z_info, nbanks;
1534
1535 if (state->zsbuf == NULL)
1536 return;
1537
1538 surf = (struct r600_surface *)state->zsbuf;
1539 level = surf->base.u.tex.level;
1540 rtex = (struct r600_resource_texture*)surf->base.texture;
1541 first_layer = surf->base.u.tex.first_layer;
1542 format = r600_translate_dbformat(surf->base.format);
1543 assert(format != ~0);
1544
1545 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1546 /* XXX remove this once tiling is properly supported */
1547 if (!rscreen->use_surface_alloc) {
1548 /* XXX remove this once tiling is properly supported */
1549 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1550 V_028C70_ARRAY_1D_TILED_THIN1;
1551
1552 offset += r600_texture_get_offset(rtex, level, first_layer);
1553 pitch = (rtex->pitch_in_blocks[level] / 8) - 1;
1554 slice = ((rtex->pitch_in_blocks[level] * surf->aligned_height) / 64);
1555 if (slice) {
1556 slice = slice - 1;
1557 }
1558 tile_split = 0;
1559 macro_aspect = 0;
1560 bankw = 0;
1561 bankh = 0;
1562 } else {
1563 offset += rtex->surface.level[level].offset;
1564 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1565 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1566 if (slice) {
1567 slice = slice - 1;
1568 }
1569 switch (rtex->surface.level[level].mode) {
1570 case RADEON_SURF_MODE_2D:
1571 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1572 break;
1573 case RADEON_SURF_MODE_1D:
1574 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1575 case RADEON_SURF_MODE_LINEAR:
1576 default:
1577 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1578 break;
1579 }
1580 tile_split = rtex->surface.tile_split;
1581 macro_aspect = rtex->surface.mtilea;
1582 bankw = rtex->surface.bankw;
1583 bankh = rtex->surface.bankh;
1584 tile_split = eg_tile_split(tile_split);
1585 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1586 bankw = eg_bank_wh(bankw);
1587 bankh = eg_bank_wh(bankh);
1588 }
1589 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1590 offset >>= 8;
1591
1592 z_info = S_028040_ARRAY_MODE(array_mode) |
1593 S_028040_FORMAT(format) |
1594 S_028040_TILE_SPLIT(tile_split)|
1595 S_028040_NUM_BANKS(nbanks) |
1596 S_028040_BANK_WIDTH(bankw) |
1597 S_028040_BANK_HEIGHT(bankh) |
1598 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1599
1600 r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE,
1601 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1602 r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE,
1603 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1604 if (!rscreen->use_surface_alloc) {
1605 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1606 0x00000000);
1607 } else {
1608 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1609 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1610 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1611 }
1612
1613 if (rtex->stencil) {
1614 uint64_t stencil_offset =
1615 r600_texture_get_offset(rtex->stencil, level, first_layer);
1616 unsigned stile_split;
1617
1618 stile_split = eg_tile_split(rtex->stencil->surface.tile_split);
1619 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1620 stencil_offset >>= 8;
1621
1622 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
1623 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1624 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1625 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1626 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1627 1 | S_028044_TILE_SPLIT(stile_split),
1628 &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1629 } else {
1630 if (rscreen->use_surface_alloc && rtex->surface.flags & RADEON_SURF_SBUFFER) {
1631 uint64_t stencil_offset = rtex->surface.stencil_offset;
1632 unsigned stile_split = rtex->surface.stencil_tile_split;
1633
1634 stile_split = eg_tile_split(stile_split);
1635 stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1636 stencil_offset += rtex->surface.level[level].offset / 4;
1637 stencil_offset >>= 8;
1638
1639 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
1640 stencil_offset, &rtex->resource,
1641 RADEON_USAGE_READWRITE);
1642 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1643 stencil_offset, &rtex->resource,
1644 RADEON_USAGE_READWRITE);
1645 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1646 1 | S_028044_TILE_SPLIT(stile_split),
1647 &rtex->resource,
1648 RADEON_USAGE_READWRITE);
1649 } else {
1650 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
1651 offset, &rtex->resource,
1652 RADEON_USAGE_READWRITE);
1653 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1654 offset, &rtex->resource,
1655 RADEON_USAGE_READWRITE);
1656 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1657 0, NULL, RADEON_USAGE_READWRITE);
1658 }
1659 }
1660
1661 r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, z_info,
1662 &rtex->resource, RADEON_USAGE_READWRITE);
1663 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1664 S_028058_PITCH_TILE_MAX(pitch));
1665 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1666 S_02805C_SLICE_TILE_MAX(slice));
1667 }
1668
1669 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1670 const struct pipe_framebuffer_state *state)
1671 {
1672 struct r600_context *rctx = (struct r600_context *)ctx;
1673 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1674 uint32_t tl, br;
1675 int i;
1676
1677 if (rstate == NULL)
1678 return;
1679
1680 r600_flush_framebuffer(rctx, false);
1681
1682 /* unreference old buffer and reference new one */
1683 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1684
1685 util_copy_framebuffer_state(&rctx->framebuffer, state);
1686
1687 /* build states */
1688 rctx->have_depth_fb = 0;
1689 rctx->export_16bpc = true;
1690 rctx->nr_cbufs = state->nr_cbufs;
1691 for (i = 0; i < state->nr_cbufs; i++) {
1692 evergreen_cb(rctx, rstate, state, i);
1693 }
1694
1695 for (; i < 8 ; i++) {
1696 r600_pipe_state_add_reg(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1697 }
1698
1699 if (state->zsbuf) {
1700 evergreen_db(rctx, rstate, state);
1701 }
1702
1703 rctx->fb_cb_shader_mask = 0;
1704 for (int i = 0; i < state->nr_cbufs; i++) {
1705 rctx->fb_cb_shader_mask |= 0xf << (i * 4);
1706 }
1707
1708 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1709
1710 r600_pipe_state_add_reg(rstate,
1711 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1712 r600_pipe_state_add_reg(rstate,
1713 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1714
1715 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1716 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1717 r600_context_pipe_state_set(rctx, rstate);
1718
1719 if (state->zsbuf) {
1720 evergreen_polygon_offset_update(rctx);
1721 }
1722 }
1723
1724 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1725 {
1726 struct radeon_winsys_cs *cs = rctx->cs;
1727 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1728 unsigned db_count_control = 0;
1729 unsigned db_render_override =
1730 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1731 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1732 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1733
1734 if (a->occlusion_query_enabled) {
1735 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1736 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1737 }
1738
1739 r600_write_context_reg(cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1740 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1741 }
1742
1743 static void evergreen_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1744 {
1745 struct radeon_winsys_cs *cs = rctx->cs;
1746 struct pipe_vertex_buffer *vb = rctx->vertex_buffer;
1747 unsigned count = rctx->nr_vertex_buffers;
1748 unsigned i;
1749 uint64_t va;
1750
1751 for (i = 0; i < count; i++) {
1752 struct r600_resource *rbuffer = (struct r600_resource*)vb[i].buffer;
1753
1754 if (!rbuffer) {
1755 continue;
1756 }
1757
1758 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1759 va += vb[i].buffer_offset;
1760
1761 /* fetch resources start at index 992 */
1762 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1763 r600_write_value(cs, (992 + i) * 8);
1764 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1765 r600_write_value(cs, rbuffer->buf->size - vb[i].buffer_offset - 1); /* RESOURCEi_WORD1 */
1766 r600_write_value(cs, /* RESOURCEi_WORD2 */
1767 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1768 S_030008_STRIDE(vb[i].stride) |
1769 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1770 r600_write_value(cs, /* RESOURCEi_WORD3 */
1771 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1772 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1773 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1774 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1775 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1776 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1777 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1778 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1779
1780 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1781 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1782 }
1783 }
1784
1785 static void evergreen_emit_constant_buffer(struct r600_context *rctx,
1786 struct r600_constbuf_state *state,
1787 unsigned buffer_id_base,
1788 unsigned reg_alu_constbuf_size,
1789 unsigned reg_alu_const_cache)
1790 {
1791 struct radeon_winsys_cs *cs = rctx->cs;
1792 uint32_t dirty_mask = state->dirty_mask;
1793
1794 while (dirty_mask) {
1795 struct pipe_constant_buffer *cb;
1796 struct r600_resource *rbuffer;
1797 uint64_t va;
1798 unsigned buffer_index = ffs(dirty_mask) - 1;
1799
1800 cb = &state->cb[buffer_index];
1801 rbuffer = (struct r600_resource*)cb->buffer;
1802 assert(rbuffer);
1803
1804 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1805 va += cb->buffer_offset;
1806
1807 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1808 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1809 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
1810
1811 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1812 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1813
1814 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1815 r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
1816 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1817 r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1818 r600_write_value(cs, /* RESOURCEi_WORD2 */
1819 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1820 S_030008_STRIDE(16) |
1821 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1822 r600_write_value(cs, /* RESOURCEi_WORD3 */
1823 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1824 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1825 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1826 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1827 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1828 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1829 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1830 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1831
1832 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1833 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1834
1835 dirty_mask &= ~(1 << buffer_index);
1836 }
1837 state->dirty_mask = 0;
1838 }
1839
1840 static void evergreen_emit_vs_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
1841 {
1842 evergreen_emit_constant_buffer(rctx, &rctx->vs_constbuf_state, 176,
1843 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1844 R_028980_ALU_CONST_CACHE_VS_0);
1845 }
1846
1847 static void evergreen_emit_ps_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
1848 {
1849 evergreen_emit_constant_buffer(rctx, &rctx->ps_constbuf_state, 0,
1850 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1851 R_028940_ALU_CONST_CACHE_PS_0);
1852 }
1853
1854 void evergreen_init_state_functions(struct r600_context *rctx)
1855 {
1856 r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 6, 0);
1857 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1858 r600_init_atom(&rctx->vertex_buffer_state, evergreen_emit_vertex_buffers, 0, 0);
1859 r600_init_atom(&rctx->vs_constbuf_state.atom, evergreen_emit_vs_constant_buffer, 0, 0);
1860 r600_init_atom(&rctx->ps_constbuf_state.atom, evergreen_emit_ps_constant_buffer, 0, 0);
1861
1862 rctx->context.create_blend_state = evergreen_create_blend_state;
1863 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1864 rctx->context.create_fs_state = r600_create_shader_state_ps;
1865 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1866 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1867 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1868 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1869 rctx->context.create_vs_state = r600_create_shader_state_vs;
1870 rctx->context.bind_blend_state = r600_bind_blend_state;
1871 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1872 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1873 rctx->context.bind_fs_state = r600_bind_ps_shader;
1874 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1875 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1876 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1877 rctx->context.bind_vs_state = r600_bind_vs_shader;
1878 rctx->context.delete_blend_state = r600_delete_state;
1879 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1880 rctx->context.delete_fs_state = r600_delete_ps_shader;
1881 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1882 rctx->context.delete_sampler_state = r600_delete_state;
1883 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1884 rctx->context.delete_vs_state = r600_delete_vs_shader;
1885 rctx->context.set_blend_color = r600_set_blend_color;
1886 rctx->context.set_clip_state = evergreen_set_clip_state;
1887 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1888 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1889 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1890 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1891 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1892 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1893 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1894 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1895 rctx->context.set_index_buffer = r600_set_index_buffer;
1896 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1897 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1898 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1899 rctx->context.texture_barrier = r600_texture_barrier;
1900 rctx->context.create_stream_output_target = r600_create_so_target;
1901 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1902 rctx->context.set_stream_output_targets = r600_set_so_targets;
1903 evergreen_init_compute_state_functions(rctx);
1904 }
1905
1906 static void cayman_init_atom_start_cs(struct r600_context *rctx)
1907 {
1908 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1909
1910 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1911
1912 /* This must be first. */
1913 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1914 r600_store_value(cb, 0x80000000);
1915 r600_store_value(cb, 0x80000000);
1916
1917 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
1918 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
1919 /* always set the temp clauses */
1920 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
1921
1922 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
1923 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
1924 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
1925
1926 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
1927
1928 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
1929
1930 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
1931 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
1932 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
1933 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
1934 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
1935 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
1936 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
1937 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
1938 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
1939 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
1940 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
1941 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
1942 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
1943 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
1944
1945 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
1946 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
1947 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
1948
1949 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
1950 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
1951 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
1952
1953 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
1954
1955 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
1956
1957 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1958 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
1959 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
1960
1961 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
1962 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
1963 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
1964
1965 r600_store_context_reg(cb, CM_R_028804_DB_EQAA, 0x110000);
1966
1967 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
1968 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
1969 r600_store_value(cb, 0);
1970 r600_store_value(cb, 0);
1971 r600_store_value(cb, 0);
1972 r600_store_value(cb, 0);
1973 r600_store_value(cb, 0);
1974 r600_store_value(cb, 0);
1975 r600_store_value(cb, 0);
1976 r600_store_value(cb, 0);
1977 r600_store_value(cb, 0);
1978 r600_store_value(cb, 0);
1979 r600_store_value(cb, 0);
1980 r600_store_value(cb, 0);
1981 r600_store_value(cb, 0);
1982 r600_store_value(cb, 0);
1983 r600_store_value(cb, 0);
1984 r600_store_value(cb, 0);
1985 r600_store_value(cb, 0);
1986 r600_store_value(cb, 0);
1987 r600_store_value(cb, 0);
1988 r600_store_value(cb, 0);
1989 r600_store_value(cb, 0);
1990 r600_store_value(cb, 0);
1991 r600_store_value(cb, 0);
1992 r600_store_value(cb, 0);
1993 r600_store_value(cb, 0);
1994 r600_store_value(cb, 0);
1995 r600_store_value(cb, 0);
1996 r600_store_value(cb, 0);
1997 r600_store_value(cb, 0);
1998 r600_store_value(cb, 0);
1999 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2000 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2001 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2002
2003 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2004
2005 r600_store_context_reg_seq(cb, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2006 r600_store_value(cb, ~0); /* CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 */
2007 r600_store_value(cb, ~0); /* CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 */
2008
2009 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2010 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2011 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2012
2013 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2014
2015 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2016 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2017 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2018 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2019
2020 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2021 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2022
2023 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2024 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2025 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2026
2027 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2028 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2029 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2030 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2031
2032 r600_store_context_reg_seq(cb, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
2033 r600_store_value(cb, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2034 r600_store_value(cb, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2035
2036 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2037 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2038 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2039 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2040 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2041
2042 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2043 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2044 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2045
2046 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2047 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2048 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2049
2050 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2051 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2052 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2053
2054 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2055 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2056
2057 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2058 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2059 }
2060
2061 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2062 {
2063 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2064 int ps_prio;
2065 int vs_prio;
2066 int gs_prio;
2067 int es_prio;
2068 int hs_prio, cs_prio, ls_prio;
2069 int num_ps_gprs;
2070 int num_vs_gprs;
2071 int num_gs_gprs;
2072 int num_es_gprs;
2073 int num_hs_gprs;
2074 int num_ls_gprs;
2075 int num_temp_gprs;
2076 int num_ps_threads;
2077 int num_vs_threads;
2078 int num_gs_threads;
2079 int num_es_threads;
2080 int num_hs_threads;
2081 int num_ls_threads;
2082 int num_ps_stack_entries;
2083 int num_vs_stack_entries;
2084 int num_gs_stack_entries;
2085 int num_es_stack_entries;
2086 int num_hs_stack_entries;
2087 int num_ls_stack_entries;
2088 enum radeon_family family;
2089 unsigned tmp;
2090
2091 if (rctx->chip_class == CAYMAN) {
2092 cayman_init_atom_start_cs(rctx);
2093 return;
2094 }
2095
2096 r600_init_command_buffer(cb, 256, EMIT_EARLY);
2097
2098 /* This must be first. */
2099 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2100 r600_store_value(cb, 0x80000000);
2101 r600_store_value(cb, 0x80000000);
2102
2103 family = rctx->family;
2104 ps_prio = 0;
2105 vs_prio = 1;
2106 gs_prio = 2;
2107 es_prio = 3;
2108 hs_prio = 0;
2109 ls_prio = 0;
2110 cs_prio = 0;
2111
2112 switch (family) {
2113 case CHIP_CEDAR:
2114 default:
2115 num_ps_gprs = 93;
2116 num_vs_gprs = 46;
2117 num_temp_gprs = 4;
2118 num_gs_gprs = 31;
2119 num_es_gprs = 31;
2120 num_hs_gprs = 23;
2121 num_ls_gprs = 23;
2122 num_ps_threads = 96;
2123 num_vs_threads = 16;
2124 num_gs_threads = 16;
2125 num_es_threads = 16;
2126 num_hs_threads = 16;
2127 num_ls_threads = 16;
2128 num_ps_stack_entries = 42;
2129 num_vs_stack_entries = 42;
2130 num_gs_stack_entries = 42;
2131 num_es_stack_entries = 42;
2132 num_hs_stack_entries = 42;
2133 num_ls_stack_entries = 42;
2134 break;
2135 case CHIP_REDWOOD:
2136 num_ps_gprs = 93;
2137 num_vs_gprs = 46;
2138 num_temp_gprs = 4;
2139 num_gs_gprs = 31;
2140 num_es_gprs = 31;
2141 num_hs_gprs = 23;
2142 num_ls_gprs = 23;
2143 num_ps_threads = 128;
2144 num_vs_threads = 20;
2145 num_gs_threads = 20;
2146 num_es_threads = 20;
2147 num_hs_threads = 20;
2148 num_ls_threads = 20;
2149 num_ps_stack_entries = 42;
2150 num_vs_stack_entries = 42;
2151 num_gs_stack_entries = 42;
2152 num_es_stack_entries = 42;
2153 num_hs_stack_entries = 42;
2154 num_ls_stack_entries = 42;
2155 break;
2156 case CHIP_JUNIPER:
2157 num_ps_gprs = 93;
2158 num_vs_gprs = 46;
2159 num_temp_gprs = 4;
2160 num_gs_gprs = 31;
2161 num_es_gprs = 31;
2162 num_hs_gprs = 23;
2163 num_ls_gprs = 23;
2164 num_ps_threads = 128;
2165 num_vs_threads = 20;
2166 num_gs_threads = 20;
2167 num_es_threads = 20;
2168 num_hs_threads = 20;
2169 num_ls_threads = 20;
2170 num_ps_stack_entries = 85;
2171 num_vs_stack_entries = 85;
2172 num_gs_stack_entries = 85;
2173 num_es_stack_entries = 85;
2174 num_hs_stack_entries = 85;
2175 num_ls_stack_entries = 85;
2176 break;
2177 case CHIP_CYPRESS:
2178 case CHIP_HEMLOCK:
2179 num_ps_gprs = 93;
2180 num_vs_gprs = 46;
2181 num_temp_gprs = 4;
2182 num_gs_gprs = 31;
2183 num_es_gprs = 31;
2184 num_hs_gprs = 23;
2185 num_ls_gprs = 23;
2186 num_ps_threads = 128;
2187 num_vs_threads = 20;
2188 num_gs_threads = 20;
2189 num_es_threads = 20;
2190 num_hs_threads = 20;
2191 num_ls_threads = 20;
2192 num_ps_stack_entries = 85;
2193 num_vs_stack_entries = 85;
2194 num_gs_stack_entries = 85;
2195 num_es_stack_entries = 85;
2196 num_hs_stack_entries = 85;
2197 num_ls_stack_entries = 85;
2198 break;
2199 case CHIP_PALM:
2200 num_ps_gprs = 93;
2201 num_vs_gprs = 46;
2202 num_temp_gprs = 4;
2203 num_gs_gprs = 31;
2204 num_es_gprs = 31;
2205 num_hs_gprs = 23;
2206 num_ls_gprs = 23;
2207 num_ps_threads = 96;
2208 num_vs_threads = 16;
2209 num_gs_threads = 16;
2210 num_es_threads = 16;
2211 num_hs_threads = 16;
2212 num_ls_threads = 16;
2213 num_ps_stack_entries = 42;
2214 num_vs_stack_entries = 42;
2215 num_gs_stack_entries = 42;
2216 num_es_stack_entries = 42;
2217 num_hs_stack_entries = 42;
2218 num_ls_stack_entries = 42;
2219 break;
2220 case CHIP_SUMO:
2221 num_ps_gprs = 93;
2222 num_vs_gprs = 46;
2223 num_temp_gprs = 4;
2224 num_gs_gprs = 31;
2225 num_es_gprs = 31;
2226 num_hs_gprs = 23;
2227 num_ls_gprs = 23;
2228 num_ps_threads = 96;
2229 num_vs_threads = 25;
2230 num_gs_threads = 25;
2231 num_es_threads = 25;
2232 num_hs_threads = 25;
2233 num_ls_threads = 25;
2234 num_ps_stack_entries = 42;
2235 num_vs_stack_entries = 42;
2236 num_gs_stack_entries = 42;
2237 num_es_stack_entries = 42;
2238 num_hs_stack_entries = 42;
2239 num_ls_stack_entries = 42;
2240 break;
2241 case CHIP_SUMO2:
2242 num_ps_gprs = 93;
2243 num_vs_gprs = 46;
2244 num_temp_gprs = 4;
2245 num_gs_gprs = 31;
2246 num_es_gprs = 31;
2247 num_hs_gprs = 23;
2248 num_ls_gprs = 23;
2249 num_ps_threads = 96;
2250 num_vs_threads = 25;
2251 num_gs_threads = 25;
2252 num_es_threads = 25;
2253 num_hs_threads = 25;
2254 num_ls_threads = 25;
2255 num_ps_stack_entries = 85;
2256 num_vs_stack_entries = 85;
2257 num_gs_stack_entries = 85;
2258 num_es_stack_entries = 85;
2259 num_hs_stack_entries = 85;
2260 num_ls_stack_entries = 85;
2261 break;
2262 case CHIP_BARTS:
2263 num_ps_gprs = 93;
2264 num_vs_gprs = 46;
2265 num_temp_gprs = 4;
2266 num_gs_gprs = 31;
2267 num_es_gprs = 31;
2268 num_hs_gprs = 23;
2269 num_ls_gprs = 23;
2270 num_ps_threads = 128;
2271 num_vs_threads = 20;
2272 num_gs_threads = 20;
2273 num_es_threads = 20;
2274 num_hs_threads = 20;
2275 num_ls_threads = 20;
2276 num_ps_stack_entries = 85;
2277 num_vs_stack_entries = 85;
2278 num_gs_stack_entries = 85;
2279 num_es_stack_entries = 85;
2280 num_hs_stack_entries = 85;
2281 num_ls_stack_entries = 85;
2282 break;
2283 case CHIP_TURKS:
2284 num_ps_gprs = 93;
2285 num_vs_gprs = 46;
2286 num_temp_gprs = 4;
2287 num_gs_gprs = 31;
2288 num_es_gprs = 31;
2289 num_hs_gprs = 23;
2290 num_ls_gprs = 23;
2291 num_ps_threads = 128;
2292 num_vs_threads = 20;
2293 num_gs_threads = 20;
2294 num_es_threads = 20;
2295 num_hs_threads = 20;
2296 num_ls_threads = 20;
2297 num_ps_stack_entries = 42;
2298 num_vs_stack_entries = 42;
2299 num_gs_stack_entries = 42;
2300 num_es_stack_entries = 42;
2301 num_hs_stack_entries = 42;
2302 num_ls_stack_entries = 42;
2303 break;
2304 case CHIP_CAICOS:
2305 num_ps_gprs = 93;
2306 num_vs_gprs = 46;
2307 num_temp_gprs = 4;
2308 num_gs_gprs = 31;
2309 num_es_gprs = 31;
2310 num_hs_gprs = 23;
2311 num_ls_gprs = 23;
2312 num_ps_threads = 128;
2313 num_vs_threads = 10;
2314 num_gs_threads = 10;
2315 num_es_threads = 10;
2316 num_hs_threads = 10;
2317 num_ls_threads = 10;
2318 num_ps_stack_entries = 42;
2319 num_vs_stack_entries = 42;
2320 num_gs_stack_entries = 42;
2321 num_es_stack_entries = 42;
2322 num_hs_stack_entries = 42;
2323 num_ls_stack_entries = 42;
2324 break;
2325 }
2326
2327 tmp = 0;
2328 switch (family) {
2329 case CHIP_CEDAR:
2330 case CHIP_PALM:
2331 case CHIP_SUMO:
2332 case CHIP_SUMO2:
2333 case CHIP_CAICOS:
2334 break;
2335 default:
2336 tmp |= S_008C00_VC_ENABLE(1);
2337 break;
2338 }
2339 tmp |= S_008C00_EXPORT_SRC_C(1);
2340 tmp |= S_008C00_CS_PRIO(cs_prio);
2341 tmp |= S_008C00_LS_PRIO(ls_prio);
2342 tmp |= S_008C00_HS_PRIO(hs_prio);
2343 tmp |= S_008C00_PS_PRIO(ps_prio);
2344 tmp |= S_008C00_VS_PRIO(vs_prio);
2345 tmp |= S_008C00_GS_PRIO(gs_prio);
2346 tmp |= S_008C00_ES_PRIO(es_prio);
2347
2348 /* enable dynamic GPR resource management */
2349 if (rctx->screen->info.drm_minor >= 7) {
2350 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2351 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2352 /* always set temp clauses */
2353 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2354 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2355 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2356 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2357 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2358 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2359 S_028838_PS_GPRS(0x1e) |
2360 S_028838_VS_GPRS(0x1e) |
2361 S_028838_GS_GPRS(0x1e) |
2362 S_028838_ES_GPRS(0x1e) |
2363 S_028838_HS_GPRS(0x1e) |
2364 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2365 } else {
2366 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2367 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2368
2369 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2370 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2371 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2372 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2373
2374 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2375 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2376 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2377
2378 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2379 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2380 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2381 }
2382
2383 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2384 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2385 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2386 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2387 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2388 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2389
2390 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2391 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2392 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2393
2394 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2395 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2396 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2397
2398 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2399 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2400 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2401
2402 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2403 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2404 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2405
2406 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2407 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2408
2409 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2410 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2411
2412 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2413
2414 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2415 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2416 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2417 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2418 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2419 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2420 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2421
2422 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2423 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2424 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2425 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2426 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2427
2428 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2429 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2430 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2431 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2432 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2433 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2434 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2435 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2436 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2437 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2438 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2439 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2440 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2441 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2442
2443 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2444 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2445 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2446
2447 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2448 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2449 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2450
2451 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2452
2453 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2454 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2455 r600_store_value(cb, 0);
2456 r600_store_value(cb, 0);
2457 r600_store_value(cb, 0);
2458 r600_store_value(cb, 0);
2459 r600_store_value(cb, 0);
2460 r600_store_value(cb, 0);
2461 r600_store_value(cb, 0);
2462 r600_store_value(cb, 0);
2463 r600_store_value(cb, 0);
2464 r600_store_value(cb, 0);
2465 r600_store_value(cb, 0);
2466 r600_store_value(cb, 0);
2467 r600_store_value(cb, 0);
2468 r600_store_value(cb, 0);
2469 r600_store_value(cb, 0);
2470 r600_store_value(cb, 0);
2471 r600_store_value(cb, 0);
2472 r600_store_value(cb, 0);
2473 r600_store_value(cb, 0);
2474 r600_store_value(cb, 0);
2475 r600_store_value(cb, 0);
2476 r600_store_value(cb, 0);
2477 r600_store_value(cb, 0);
2478 r600_store_value(cb, 0);
2479 r600_store_value(cb, 0);
2480 r600_store_value(cb, 0);
2481 r600_store_value(cb, 0);
2482 r600_store_value(cb, 0);
2483 r600_store_value(cb, 0);
2484 r600_store_value(cb, 0);
2485 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2486 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2487 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2488
2489 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2490
2491 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2492 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2493 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2494
2495 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2496 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2497 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2498
2499 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2500 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2501 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2502
2503 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2504 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2505 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2506
2507 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2508 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2509 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2510 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2511
2512 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2513
2514 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2515 r600_store_value(cb, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
2516 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2517
2518 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 5);
2519 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2520 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2521 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2522 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2523 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
2524
2525 r600_store_context_reg(cb, R_028C3C_PA_SC_AA_MASK, ~0);
2526
2527 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2528 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2529 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2530
2531 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2532 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2533 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2534
2535 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2536 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2537 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2538
2539 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2540 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2541
2542 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2543 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2544 }
2545
2546 void evergreen_polygon_offset_update(struct r600_context *rctx)
2547 {
2548 struct r600_pipe_state state;
2549
2550 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2551 state.nregs = 0;
2552 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2553 float offset_units = rctx->rasterizer->offset_units;
2554 unsigned offset_db_fmt_cntl = 0, depth;
2555
2556 switch (rctx->framebuffer.zsbuf->format) {
2557 case PIPE_FORMAT_Z24X8_UNORM:
2558 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2559 depth = -24;
2560 offset_units *= 2.0f;
2561 break;
2562 case PIPE_FORMAT_Z32_FLOAT:
2563 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2564 depth = -23;
2565 offset_units *= 1.0f;
2566 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2567 break;
2568 case PIPE_FORMAT_Z16_UNORM:
2569 depth = -16;
2570 offset_units *= 4.0f;
2571 break;
2572 default:
2573 return;
2574 }
2575 /* XXX some of those reg can be computed with cso */
2576 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2577 r600_pipe_state_add_reg(&state,
2578 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2579 fui(rctx->rasterizer->offset_scale));
2580 r600_pipe_state_add_reg(&state,
2581 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2582 fui(offset_units));
2583 r600_pipe_state_add_reg(&state,
2584 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2585 fui(rctx->rasterizer->offset_scale));
2586 r600_pipe_state_add_reg(&state,
2587 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2588 fui(offset_units));
2589 r600_pipe_state_add_reg(&state,
2590 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2591 offset_db_fmt_cntl);
2592 r600_context_pipe_state_set(rctx, &state);
2593 }
2594 }
2595
2596 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2597 {
2598 struct r600_context *rctx = (struct r600_context *)ctx;
2599 struct r600_pipe_state *rstate = &shader->rstate;
2600 struct r600_shader *rshader = &shader->shader;
2601 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2602 int pos_index = -1, face_index = -1;
2603 int ninterp = 0;
2604 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2605 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2606 unsigned z_export = 0, stencil_export = 0;
2607
2608 rstate->nregs = 0;
2609
2610 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2611 for (i = 0; i < rshader->ninput; i++) {
2612 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2613 POSITION goes via GPRs from the SC so isn't counted */
2614 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2615 pos_index = i;
2616 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2617 face_index = i;
2618 else {
2619 ninterp++;
2620 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2621 have_linear = TRUE;
2622 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2623 have_perspective = TRUE;
2624 if (rshader->input[i].centroid)
2625 have_centroid = TRUE;
2626 }
2627
2628 sid = rshader->input[i].spi_sid;
2629
2630 if (sid) {
2631
2632 tmp = S_028644_SEMANTIC(sid);
2633
2634 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2635 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2636 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2637 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2638 tmp |= S_028644_FLAT_SHADE(1);
2639 }
2640
2641 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2642 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2643 tmp |= S_028644_PT_SPRITE_TEX(1);
2644 }
2645
2646 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2647 tmp);
2648
2649 idx++;
2650 }
2651 }
2652
2653 for (i = 0; i < rshader->noutput; i++) {
2654 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2655 z_export = 1;
2656 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2657 stencil_export = 1;
2658 }
2659 if (rshader->uses_kill)
2660 db_shader_control |= S_02880C_KILL_ENABLE(1);
2661
2662 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2663 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
2664
2665 exports_ps = 0;
2666 for (i = 0; i < rshader->noutput; i++) {
2667 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2668 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2669 exports_ps |= 1;
2670 }
2671
2672 num_cout = rshader->nr_ps_color_exports;
2673
2674 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2675 if (!exports_ps) {
2676 /* always at least export 1 component per pixel */
2677 exports_ps = 2;
2678 }
2679 shader->ps_cb_shader_mask = (1ULL << ((unsigned)num_cout * 4)) - 1;
2680 if (ninterp == 0) {
2681 ninterp = 1;
2682 have_perspective = TRUE;
2683 }
2684
2685 if (!have_perspective && !have_linear)
2686 have_perspective = TRUE;
2687
2688 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2689 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2690 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2691 spi_input_z = 0;
2692 if (pos_index != -1) {
2693 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2694 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2695 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2696 spi_input_z |= 1;
2697 }
2698
2699 spi_ps_in_control_1 = 0;
2700 if (face_index != -1) {
2701 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2702 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2703 }
2704
2705 spi_baryc_cntl = 0;
2706 if (have_perspective)
2707 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2708 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2709 if (have_linear)
2710 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2711 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2712
2713 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2714 spi_ps_in_control_0);
2715 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2716 spi_ps_in_control_1);
2717 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2718 0);
2719 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2720 r600_pipe_state_add_reg(rstate,
2721 R_0286E0_SPI_BARYC_CNTL,
2722 spi_baryc_cntl);
2723
2724 r600_pipe_state_add_reg_bo(rstate,
2725 R_028840_SQ_PGM_START_PS,
2726 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2727 shader->bo, RADEON_USAGE_READ);
2728 r600_pipe_state_add_reg(rstate,
2729 R_028844_SQ_PGM_RESOURCES_PS,
2730 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2731 S_028844_PRIME_CACHE_ON_DRAW(1) |
2732 S_028844_STACK_SIZE(rshader->bc.nstack));
2733 r600_pipe_state_add_reg(rstate,
2734 R_02884C_SQ_PGM_EXPORTS_PS,
2735 exports_ps);
2736
2737 shader->db_shader_control = db_shader_control;
2738 shader->ps_depth_export = z_export | stencil_export;
2739
2740 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2741 if (rctx->rasterizer)
2742 shader->flatshade = rctx->rasterizer->flatshade;
2743 }
2744
2745 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2746 {
2747 struct r600_context *rctx = (struct r600_context *)ctx;
2748 struct r600_pipe_state *rstate = &shader->rstate;
2749 struct r600_shader *rshader = &shader->shader;
2750 unsigned spi_vs_out_id[10] = {};
2751 unsigned i, tmp, nparams = 0;
2752
2753 /* clear previous register */
2754 rstate->nregs = 0;
2755
2756 for (i = 0; i < rshader->noutput; i++) {
2757 if (rshader->output[i].spi_sid) {
2758 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2759 spi_vs_out_id[nparams / 4] |= tmp;
2760 nparams++;
2761 }
2762 }
2763
2764 for (i = 0; i < 10; i++) {
2765 r600_pipe_state_add_reg(rstate,
2766 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2767 spi_vs_out_id[i]);
2768 }
2769
2770 /* Certain attributes (position, psize, etc.) don't count as params.
2771 * VS is required to export at least one param and r600_shader_from_tgsi()
2772 * takes care of adding a dummy export.
2773 */
2774 if (nparams < 1)
2775 nparams = 1;
2776
2777 r600_pipe_state_add_reg(rstate,
2778 R_0286C4_SPI_VS_OUT_CONFIG,
2779 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2780 r600_pipe_state_add_reg(rstate,
2781 R_028860_SQ_PGM_RESOURCES_VS,
2782 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2783 S_028860_STACK_SIZE(rshader->bc.nstack));
2784 r600_pipe_state_add_reg_bo(rstate,
2785 R_02885C_SQ_PGM_START_VS,
2786 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2787 shader->bo, RADEON_USAGE_READ);
2788
2789 shader->pa_cl_vs_out_cntl =
2790 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2791 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2792 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2793 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2794 }
2795
2796 void evergreen_fetch_shader(struct pipe_context *ctx,
2797 struct r600_vertex_element *ve)
2798 {
2799 struct r600_context *rctx = (struct r600_context *)ctx;
2800 struct r600_pipe_state *rstate = &ve->rstate;
2801 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2802 rstate->nregs = 0;
2803 r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
2804 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2805 ve->fetch_shader, RADEON_USAGE_READ);
2806 }
2807
2808 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2809 {
2810 struct pipe_depth_stencil_alpha_state dsa;
2811 struct r600_pipe_state *rstate;
2812
2813 memset(&dsa, 0, sizeof(dsa));
2814
2815 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2816 r600_pipe_state_add_reg(rstate,
2817 R_028000_DB_RENDER_CONTROL,
2818 S_028000_DEPTH_COPY_ENABLE(1) |
2819 S_028000_STENCIL_COPY_ENABLE(1) |
2820 S_028000_COPY_CENTROID(1));
2821 /* Don't set the 'is_flush' flag in r600_pipe_dsa, evergreen doesn't need it. */
2822 return rstate;
2823 }
2824
2825 void evergreen_update_dual_export_state(struct r600_context * rctx)
2826 {
2827 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2828 !rctx->ps_shader->current->ps_depth_export;
2829
2830 unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
2831 V_02880C_EXPORT_DB_FULL;
2832
2833 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2834 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
2835 S_02880C_DB_SOURCE_FORMAT(db_source_format);
2836
2837 if (db_shader_control != rctx->db_shader_control) {
2838 struct r600_pipe_state rstate;
2839
2840 rctx->db_shader_control = db_shader_control;
2841
2842 rstate.nregs = 0;
2843 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2844 r600_context_pipe_state_set(rctx, &rstate);
2845 }
2846 }