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r600g: don't run with scissors.
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <pipebuffer/pb_buffer.h>
43 #include "r600.h"
44 #include "evergreend.h"
45 #include "r600_resource.h"
46 #include "r600_shader.h"
47 #include "r600_pipe.h"
48 #include "eg_state_inlines.h"
49
50 static void evergreen_set_blend_color(struct pipe_context *ctx,
51 const struct pipe_blend_color *state)
52 {
53 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
54 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
55
56 if (rstate == NULL)
57 return;
58
59 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
60 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
61 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
62 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
63 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
64
65 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
66 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
67 r600_context_pipe_state_set(&rctx->ctx, rstate);
68 }
69
70 static void *evergreen_create_blend_state(struct pipe_context *ctx,
71 const struct pipe_blend_state *state)
72 {
73 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
74 struct r600_pipe_state *rstate;
75 u32 color_control, target_mask;
76 /* FIXME there is more then 8 framebuffer */
77 unsigned blend_cntl[8];
78
79 if (blend == NULL) {
80 return NULL;
81 }
82 rstate = &blend->rstate;
83
84 rstate->id = R600_PIPE_STATE_BLEND;
85
86 target_mask = 0;
87 color_control = S_028808_MODE(1);
88 if (state->logicop_enable) {
89 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
90 } else {
91 color_control |= (0xcc << 16);
92 }
93 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
94 if (state->independent_blend_enable) {
95 for (int i = 0; i < 8; i++) {
96 target_mask |= (state->rt[i].colormask << (4 * i));
97 }
98 } else {
99 for (int i = 0; i < 8; i++) {
100 target_mask |= (state->rt[0].colormask << (4 * i));
101 }
102 }
103 blend->cb_target_mask = target_mask;
104 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
105 color_control, 0xFFFFFFFF, NULL);
106 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
107
108 for (int i = 0; i < 8; i++) {
109 unsigned eqRGB = state->rt[i].rgb_func;
110 unsigned srcRGB = state->rt[i].rgb_src_factor;
111 unsigned dstRGB = state->rt[i].rgb_dst_factor;
112 unsigned eqA = state->rt[i].alpha_func;
113 unsigned srcA = state->rt[i].alpha_src_factor;
114 unsigned dstA = state->rt[i].alpha_dst_factor;
115
116 blend_cntl[i] = 0;
117 if (!state->rt[i].blend_enable)
118 continue;
119
120 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
121 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
122 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
123 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
124
125 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
126 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
127 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
128 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
129 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
130 }
131 }
132 for (int i = 0; i < 8; i++) {
133 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
134 }
135
136 return rstate;
137 }
138
139 static void evergreen_bind_blend_state(struct pipe_context *ctx, void *state)
140 {
141 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
142 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
143 struct r600_pipe_state *rstate;
144
145 if (state == NULL)
146 return;
147 rstate = &blend->rstate;
148 rctx->states[rstate->id] = rstate;
149 rctx->cb_target_mask = blend->cb_target_mask;
150 r600_context_pipe_state_set(&rctx->ctx, rstate);
151 }
152
153 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
154 const struct pipe_depth_stencil_alpha_state *state)
155 {
156 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
157 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
158 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
159
160 if (rstate == NULL) {
161 return NULL;
162 }
163
164 rstate->id = R600_PIPE_STATE_DSA;
165 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
166 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
167 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
168 * be set if shader use texkill instruction
169 */
170 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
171 stencil_ref_mask = 0;
172 stencil_ref_mask_bf = 0;
173 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
174 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
175 S_028800_ZFUNC(state->depth.func);
176
177 /* stencil */
178 if (state->stencil[0].enabled) {
179 db_depth_control |= S_028800_STENCIL_ENABLE(1);
180 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
181 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
182 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
183 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
184
185
186 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
187 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
188 if (state->stencil[1].enabled) {
189 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
190 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
191 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
192 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
193 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
194 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
195 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
196 }
197 }
198
199 /* alpha */
200 alpha_test_control = 0;
201 alpha_ref = 0;
202 if (state->alpha.enabled) {
203 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
204 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
205 alpha_ref = fui(state->alpha.ref_value);
206 }
207
208 /* misc */
209 db_render_control = 0;
210 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
211 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
212 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
213 /* TODO db_render_override depends on query */
214 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
215 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
216 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
217 r600_pipe_state_add_reg(rstate,
218 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
219 0xFFFFFFFF & C_028430_STENCILREF, NULL);
220 r600_pipe_state_add_reg(rstate,
221 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
222 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
223 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
224 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
225 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
226 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
227 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
228 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
229 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
230 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
231 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
232 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
233
234 return rstate;
235 }
236
237 static void *evergreen_create_rs_state(struct pipe_context *ctx,
238 const struct pipe_rasterizer_state *state)
239 {
240 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
241 struct r600_pipe_state *rstate;
242 unsigned tmp;
243 unsigned prov_vtx = 1, polygon_dual_mode;
244
245 if (rs == NULL) {
246 return NULL;
247 }
248
249 rstate = &rs->rstate;
250 rs->flatshade = state->flatshade;
251 rs->sprite_coord_enable = state->sprite_coord_enable;
252
253 /* offset */
254 rs->offset_units = state->offset_units;
255 rs->offset_scale = state->offset_scale * 12.0f;
256
257 rstate->id = R600_PIPE_STATE_RASTERIZER;
258 if (state->flatshade_first)
259 prov_vtx = 0;
260 tmp = 0x00000001;
261 if (state->sprite_coord_enable) {
262 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
263 S_0286D4_PNT_SPRITE_OVRD_X(2) |
264 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
265 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
266 S_0286D4_PNT_SPRITE_OVRD_W(1);
267 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
268 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
269 }
270 }
271 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
272
273 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
274 state->fill_back != PIPE_POLYGON_MODE_FILL);
275 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
276 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
277 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
278 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
279 S_028814_FACE(!state->front_ccw) |
280 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
281 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
282 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
283 S_028814_POLY_MODE(polygon_dual_mode) |
284 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
285 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
286 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
287 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
288 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
289 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
290 /* point size 12.4 fixed point */
291 tmp = (unsigned)(state->point_size * 8.0);
292 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
293 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
294 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
295 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
296 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
297 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
298 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
299 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
300 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
301 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 0x00000005, 0xFFFFFFFF, NULL);
302 return rstate;
303 }
304
305 static void evergreen_bind_rs_state(struct pipe_context *ctx, void *state)
306 {
307 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
308 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
309
310 if (state == NULL)
311 return;
312
313 rctx->flatshade = rs->flatshade;
314 rctx->sprite_coord_enable = rs->sprite_coord_enable;
315 rctx->rasterizer = rs;
316
317 rctx->states[rs->rstate.id] = &rs->rstate;
318 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
319 }
320
321 static void evergreen_delete_rs_state(struct pipe_context *ctx, void *state)
322 {
323 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
324 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
325
326 if (rctx->rasterizer == rs) {
327 rctx->rasterizer = NULL;
328 }
329 if (rctx->states[rs->rstate.id] == &rs->rstate) {
330 rctx->states[rs->rstate.id] = NULL;
331 }
332 free(rs);
333 }
334
335 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
336 const struct pipe_sampler_state *state)
337 {
338 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
339 union util_color uc;
340
341 if (rstate == NULL) {
342 return NULL;
343 }
344
345 rstate->id = R600_PIPE_STATE_SAMPLER;
346 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
347 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
348 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
349 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
350 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
351 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
352 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
353 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
354 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
355 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
356 /* FIXME LOD it depends on texture base level ... */
357 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
358 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
359 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)),
360 0xFFFFFFFF, NULL);
361 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
362 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
363 S_03C008_TYPE(1),
364 0xFFFFFFFF, NULL);
365
366 if (uc.ui) {
367 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
368 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
369 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
370 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
371 }
372 return rstate;
373 }
374
375 static void *evergreen_create_vertex_elements(struct pipe_context *ctx,
376 unsigned count,
377 const struct pipe_vertex_element *elements)
378 {
379 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
380
381 assert(count < 32);
382 v->count = count;
383 v->refcount = 1;
384 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
385 return v;
386 }
387
388 static void evergreen_sampler_view_destroy(struct pipe_context *ctx,
389 struct pipe_sampler_view *state)
390 {
391 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
392
393 pipe_resource_reference(&state->texture, NULL);
394 FREE(resource);
395 }
396
397 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
398 struct pipe_resource *texture,
399 const struct pipe_sampler_view *state)
400 {
401 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
402 struct r600_pipe_state *rstate;
403 const struct util_format_description *desc;
404 struct r600_resource_texture *tmp;
405 struct r600_resource *rbuffer;
406 unsigned format;
407 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
408 unsigned char swizzle[4];
409 struct r600_bo *bo[2];
410
411 if (resource == NULL)
412 return NULL;
413 rstate = &resource->state;
414
415 /* initialize base object */
416 resource->base = *state;
417 resource->base.texture = NULL;
418 pipe_reference(NULL, &texture->reference);
419 resource->base.texture = texture;
420 resource->base.reference.count = 1;
421 resource->base.context = ctx;
422
423 swizzle[0] = state->swizzle_r;
424 swizzle[1] = state->swizzle_g;
425 swizzle[2] = state->swizzle_b;
426 swizzle[3] = state->swizzle_a;
427 format = r600_translate_texformat(state->format,
428 swizzle,
429 &word4, &yuv_format);
430 if (format == ~0) {
431 format = 0;
432 }
433 desc = util_format_description(state->format);
434 if (desc == NULL) {
435 R600_ERR("unknow format %d\n", state->format);
436 }
437 tmp = (struct r600_resource_texture*)texture;
438 rbuffer = &tmp->resource;
439 bo[0] = rbuffer->bo;
440 bo[1] = rbuffer->bo;
441 /* FIXME depth texture decompression */
442 if (tmp->depth) {
443 r600_texture_depth_flush(ctx, texture);
444 tmp = (struct r600_resource_texture*)texture;
445 rbuffer = &tmp->flushed_depth_texture->resource;
446 bo[0] = rbuffer->bo;
447 bo[1] = rbuffer->bo;
448 }
449 pitch = align(tmp->pitch[0] / tmp->bpt, 8);
450
451 /* FIXME properly handle first level != 0 */
452 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
453 S_030000_DIM(r600_tex_dim(texture->target)) |
454 S_030000_PITCH((pitch / 8) - 1) |
455 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
456 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
457 S_030004_TEX_HEIGHT(texture->height0 - 1) |
458 S_030004_TEX_DEPTH(texture->depth0 - 1),
459 0xFFFFFFFF, NULL);
460 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
461 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
462 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
463 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
464 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
465 word4 | S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
466 S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
467 S_030010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
468 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
469 S_030014_LAST_LEVEL(state->last_level) |
470 S_030014_BASE_ARRAY(0) |
471 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
472 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
473 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
474 S_03001C_DATA_FORMAT(format) |
475 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
476
477 return &resource->base;
478 }
479
480 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
481 struct pipe_sampler_view **views)
482 {
483 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
484 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
485
486 for (int i = 0; i < count; i++) {
487 if (resource[i]) {
488 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i + PIPE_MAX_ATTRIBS);
489 }
490 }
491 }
492
493 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
494 struct pipe_sampler_view **views)
495 {
496 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
497 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
498
499 for (int i = 0; i < count; i++) {
500 if (resource[i]) {
501 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
502 }
503 }
504 }
505
506 static void evergreen_bind_state(struct pipe_context *ctx, void *state)
507 {
508 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
509 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
510
511 if (state == NULL)
512 return;
513 rctx->states[rstate->id] = rstate;
514 r600_context_pipe_state_set(&rctx->ctx, rstate);
515 }
516
517 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
518 {
519 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
520 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
521
522 for (int i = 0; i < count; i++) {
523 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
524 }
525 }
526
527 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
528 {
529 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
530 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
531
532 for (int i = 0; i < count; i++) {
533 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
534 }
535 }
536
537 static void evergreen_delete_state(struct pipe_context *ctx, void *state)
538 {
539 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
540 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
541
542 if (rctx->states[rstate->id] == rstate) {
543 rctx->states[rstate->id] = NULL;
544 }
545 for (int i = 0; i < rstate->nregs; i++) {
546 r600_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
547 }
548 free(rstate);
549 }
550
551 static void evergreen_delete_vertex_element(struct pipe_context *ctx, void *state)
552 {
553 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
554
555 if (v == NULL)
556 return;
557 if (--v->refcount)
558 return;
559 free(v);
560 }
561
562 static void evergreen_set_clip_state(struct pipe_context *ctx,
563 const struct pipe_clip_state *state)
564 {
565 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
566 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
567
568 if (rstate == NULL)
569 return;
570
571 rctx->clip = *state;
572 rstate->id = R600_PIPE_STATE_CLIP;
573 for (int i = 0; i < state->nr; i++) {
574 r600_pipe_state_add_reg(rstate,
575 R_0285BC_PA_CL_UCP0_X + i * 4,
576 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
577 r600_pipe_state_add_reg(rstate,
578 R_0285C0_PA_CL_UCP0_Y + i * 4,
579 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
580 r600_pipe_state_add_reg(rstate,
581 R_0285C4_PA_CL_UCP0_Z + i * 4,
582 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
583 r600_pipe_state_add_reg(rstate,
584 R_0285C8_PA_CL_UCP0_W + i * 4,
585 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
586 }
587 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
588 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
589 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
590 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
591
592 free(rctx->states[R600_PIPE_STATE_CLIP]);
593 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
594 r600_context_pipe_state_set(&rctx->ctx, rstate);
595 }
596
597 static void evergreen_bind_vertex_elements(struct pipe_context *ctx, void *state)
598 {
599 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
600 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
601
602 evergreen_delete_vertex_element(ctx, rctx->vertex_elements);
603 rctx->vertex_elements = v;
604 if (v) {
605 v->refcount++;
606 // rctx->vs_rebuild = TRUE;
607 }
608 }
609
610 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
611 const struct pipe_poly_stipple *state)
612 {
613 }
614
615 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
616 {
617 }
618
619 static void evergreen_set_scissor_state(struct pipe_context *ctx,
620 const struct pipe_scissor_state *state)
621 {
622 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
623 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
624 u32 tl, br;
625
626 if (rstate == NULL)
627 return;
628
629 rstate->id = R600_PIPE_STATE_SCISSOR;
630 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
631 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
632 r600_pipe_state_add_reg(rstate,
633 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
634 0xFFFFFFFF, NULL);
635 r600_pipe_state_add_reg(rstate,
636 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
637 0xFFFFFFFF, NULL);
638 r600_pipe_state_add_reg(rstate,
639 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
640 0xFFFFFFFF, NULL);
641 r600_pipe_state_add_reg(rstate,
642 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
643 0xFFFFFFFF, NULL);
644 r600_pipe_state_add_reg(rstate,
645 R_028210_PA_SC_CLIPRECT_0_TL, tl,
646 0xFFFFFFFF, NULL);
647 r600_pipe_state_add_reg(rstate,
648 R_028214_PA_SC_CLIPRECT_0_BR, br,
649 0xFFFFFFFF, NULL);
650 r600_pipe_state_add_reg(rstate,
651 R_028218_PA_SC_CLIPRECT_1_TL, tl,
652 0xFFFFFFFF, NULL);
653 r600_pipe_state_add_reg(rstate,
654 R_02821C_PA_SC_CLIPRECT_1_BR, br,
655 0xFFFFFFFF, NULL);
656 r600_pipe_state_add_reg(rstate,
657 R_028220_PA_SC_CLIPRECT_2_TL, tl,
658 0xFFFFFFFF, NULL);
659 r600_pipe_state_add_reg(rstate,
660 R_028224_PA_SC_CLIPRECT_2_BR, br,
661 0xFFFFFFFF, NULL);
662 r600_pipe_state_add_reg(rstate,
663 R_028228_PA_SC_CLIPRECT_3_TL, tl,
664 0xFFFFFFFF, NULL);
665 r600_pipe_state_add_reg(rstate,
666 R_02822C_PA_SC_CLIPRECT_3_BR, br,
667 0xFFFFFFFF, NULL);
668 r600_pipe_state_add_reg(rstate,
669 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
670 0xFFFFFFFF, NULL);
671 r600_pipe_state_add_reg(rstate,
672 R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
673 0xFFFFFFFF, NULL);
674 r600_pipe_state_add_reg(rstate,
675 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
676 0xFFFFFFFF, NULL);
677
678 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
679 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
680 r600_context_pipe_state_set(&rctx->ctx, rstate);
681 }
682
683 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
684 const struct pipe_stencil_ref *state)
685 {
686 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
687 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
688 u32 tmp;
689
690 if (rstate == NULL)
691 return;
692
693 rctx->stencil_ref = *state;
694 rstate->id = R600_PIPE_STATE_STENCIL_REF;
695 tmp = S_028430_STENCILREF(state->ref_value[0]);
696 r600_pipe_state_add_reg(rstate,
697 R_028430_DB_STENCILREFMASK, tmp,
698 ~C_028430_STENCILREF, NULL);
699 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
700 r600_pipe_state_add_reg(rstate,
701 R_028434_DB_STENCILREFMASK_BF, tmp,
702 ~C_028434_STENCILREF_BF, NULL);
703
704 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
705 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
706 r600_context_pipe_state_set(&rctx->ctx, rstate);
707 }
708
709 static void evergreen_set_viewport_state(struct pipe_context *ctx,
710 const struct pipe_viewport_state *state)
711 {
712 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
713 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
714
715 if (rstate == NULL)
716 return;
717
718 rctx->viewport = *state;
719 rstate->id = R600_PIPE_STATE_VIEWPORT;
720 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
721 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
722 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
723 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
724 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
725 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
726 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
727 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
728 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
729
730 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
731 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
732 r600_context_pipe_state_set(&rctx->ctx, rstate);
733 }
734
735 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
736 const struct pipe_framebuffer_state *state, int cb)
737 {
738 struct r600_resource_texture *rtex;
739 struct r600_resource *rbuffer;
740 unsigned level = state->cbufs[cb]->level;
741 unsigned pitch, slice;
742 unsigned color_info;
743 unsigned format, swap, ntype;
744 const struct util_format_description *desc;
745 struct r600_bo *bo[3];
746
747 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
748 rbuffer = &rtex->resource;
749 bo[0] = rbuffer->bo;
750 bo[1] = rbuffer->bo;
751 bo[2] = rbuffer->bo;
752
753 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
754 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
755 ntype = 0;
756 desc = util_format_description(rtex->resource.base.b.format);
757 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
758 ntype = V_028C70_NUMBER_SRGB;
759
760 format = r600_translate_colorformat(rtex->resource.base.b.format);
761 swap = r600_translate_colorswap(rtex->resource.base.b.format);
762 color_info = S_028C70_FORMAT(format) |
763 S_028C70_COMP_SWAP(swap) |
764 S_028C70_BLEND_CLAMP(1) |
765 S_028C70_NUMBER_TYPE(ntype);
766 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
767 color_info |= S_028C70_SOURCE_FORMAT(1);
768
769 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
770 r600_pipe_state_add_reg(rstate,
771 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
772 (state->cbufs[cb]->offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
773 r600_pipe_state_add_reg(rstate,
774 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
775 0x0, 0xFFFFFFFF, NULL);
776 r600_pipe_state_add_reg(rstate,
777 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
778 color_info, 0xFFFFFFFF, bo[0]);
779 r600_pipe_state_add_reg(rstate,
780 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
781 S_028C64_PITCH_TILE_MAX(pitch),
782 0xFFFFFFFF, NULL);
783 r600_pipe_state_add_reg(rstate,
784 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
785 S_028C68_SLICE_TILE_MAX(slice),
786 0xFFFFFFFF, NULL);
787 r600_pipe_state_add_reg(rstate,
788 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
789 0x00000000, 0xFFFFFFFF, NULL);
790 r600_pipe_state_add_reg(rstate,
791 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
792 S_028C74_NON_DISP_TILING_ORDER(1),
793 0xFFFFFFFF, bo[0]);
794 }
795
796 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
797 const struct pipe_framebuffer_state *state)
798 {
799 struct r600_resource_texture *rtex;
800 struct r600_resource *rbuffer;
801 unsigned level;
802 unsigned pitch, slice, format, stencil_format;
803
804 if (state->zsbuf == NULL)
805 return;
806
807 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
808 rtex->tiled = 1;
809 rtex->array_mode = 2;
810 rtex->tile_type = 1;
811 rtex->depth = 1;
812 rbuffer = &rtex->resource;
813
814 level = state->zsbuf->level;
815 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
816 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
817 format = r600_translate_dbformat(state->zsbuf->texture->format);
818 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
819
820 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
821 (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
822 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
823 (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
824
825 if (stencil_format) {
826 uint32_t stencil_offset;
827
828 stencil_offset = ((state->zsbuf->height * rtex->pitch[level]) + 255) & ~255;
829 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
830 (state->zsbuf->offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
831 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
832 (state->zsbuf->offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
833 }
834
835 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
836 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
837 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
838
839 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
840 S_028040_ARRAY_MODE(rtex->array_mode) | S_028040_FORMAT(format),
841 0xFFFFFFFF, rbuffer->bo);
842 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
843 S_028058_PITCH_TILE_MAX(pitch),
844 0xFFFFFFFF, NULL);
845 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
846 S_02805C_SLICE_TILE_MAX(slice),
847 0xFFFFFFFF, NULL);
848 }
849
850 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
851 const struct pipe_framebuffer_state *state)
852 {
853 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
854 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
855 u32 shader_mask, tl, br, target_mask;
856
857 if (rstate == NULL)
858 return;
859
860 /* unreference old buffer and reference new one */
861 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
862 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
863 pipe_surface_reference(&rctx->framebuffer.cbufs[i], NULL);
864 }
865 for (int i = 0; i < state->nr_cbufs; i++) {
866 pipe_surface_reference(&rctx->framebuffer.cbufs[i], state->cbufs[i]);
867 }
868 pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
869 rctx->framebuffer = *state;
870 rctx->pframebuffer = &rctx->framebuffer;
871
872 /* build states */
873 for (int i = 0; i < state->nr_cbufs; i++) {
874 evergreen_cb(rctx, rstate, state, i);
875 }
876 if (state->zsbuf) {
877 evergreen_db(rctx, rstate, state);
878 }
879
880 target_mask = 0x00000000;
881 target_mask = 0xFFFFFFFF;
882 shader_mask = 0;
883 for (int i = 0; i < state->nr_cbufs; i++) {
884 target_mask ^= 0xf << (i * 4);
885 shader_mask |= 0xf << (i * 4);
886 }
887 tl = S_028240_TL_X(0) | S_028240_TL_Y(0);
888 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
889
890 r600_pipe_state_add_reg(rstate,
891 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
892 0xFFFFFFFF, NULL);
893 r600_pipe_state_add_reg(rstate,
894 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
895 0xFFFFFFFF, NULL);
896 r600_pipe_state_add_reg(rstate,
897 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
898 0xFFFFFFFF, NULL);
899 r600_pipe_state_add_reg(rstate,
900 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
901 0xFFFFFFFF, NULL);
902 r600_pipe_state_add_reg(rstate,
903 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
904 0xFFFFFFFF, NULL);
905 r600_pipe_state_add_reg(rstate,
906 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
907 0xFFFFFFFF, NULL);
908 r600_pipe_state_add_reg(rstate,
909 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
910 0xFFFFFFFF, NULL);
911 r600_pipe_state_add_reg(rstate,
912 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
913 0xFFFFFFFF, NULL);
914 r600_pipe_state_add_reg(rstate,
915 R_028210_PA_SC_CLIPRECT_0_TL, tl,
916 0xFFFFFFFF, NULL);
917 r600_pipe_state_add_reg(rstate,
918 R_028214_PA_SC_CLIPRECT_0_BR, br,
919 0xFFFFFFFF, NULL);
920 r600_pipe_state_add_reg(rstate,
921 R_028218_PA_SC_CLIPRECT_1_TL, tl,
922 0xFFFFFFFF, NULL);
923 r600_pipe_state_add_reg(rstate,
924 R_02821C_PA_SC_CLIPRECT_1_BR, br,
925 0xFFFFFFFF, NULL);
926 r600_pipe_state_add_reg(rstate,
927 R_028220_PA_SC_CLIPRECT_2_TL, tl,
928 0xFFFFFFFF, NULL);
929 r600_pipe_state_add_reg(rstate,
930 R_028224_PA_SC_CLIPRECT_2_BR, br,
931 0xFFFFFFFF, NULL);
932 r600_pipe_state_add_reg(rstate,
933 R_028228_PA_SC_CLIPRECT_3_TL, tl,
934 0xFFFFFFFF, NULL);
935 r600_pipe_state_add_reg(rstate,
936 R_02822C_PA_SC_CLIPRECT_3_BR, br,
937 0xFFFFFFFF, NULL);
938 r600_pipe_state_add_reg(rstate,
939 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
940 0xFFFFFFFF, NULL);
941 r600_pipe_state_add_reg(rstate,
942 R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
943 0xFFFFFFFF, NULL);
944 r600_pipe_state_add_reg(rstate,
945 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
946 0xFFFFFFFF, NULL);
947
948 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
949 0x00000000, target_mask, NULL);
950 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
951 shader_mask, 0xFFFFFFFF, NULL);
952 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
953 0x00000000, 0xFFFFFFFF, NULL);
954 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
955 0x00000000, 0xFFFFFFFF, NULL);
956
957 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
958 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
959 r600_context_pipe_state_set(&rctx->ctx, rstate);
960 }
961
962 static void evergreen_set_index_buffer(struct pipe_context *ctx,
963 const struct pipe_index_buffer *ib)
964 {
965 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
966
967 if (ib) {
968 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
969 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
970 } else {
971 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
972 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
973 }
974
975 /* TODO make this more like a state */
976 }
977
978 static void evergreen_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
979 const struct pipe_vertex_buffer *buffers)
980 {
981 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
982
983 for (int i = 0; i < rctx->nvertex_buffer; i++) {
984 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
985 }
986 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
987 for (int i = 0; i < count; i++) {
988 rctx->vertex_buffer[i].buffer = NULL;
989 if (r600_buffer_is_user_buffer(buffers[i].buffer))
990 rctx->any_user_vbs = TRUE;
991 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
992 }
993 rctx->nvertex_buffer = count;
994 }
995
996 static void evergreen_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
997 struct pipe_resource *buffer)
998 {
999 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1000 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1001
1002 switch (shader) {
1003 case PIPE_SHADER_VERTEX:
1004 rctx->vs_const_buffer.nregs = 0;
1005 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1006 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1007 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1008 0xFFFFFFFF, NULL);
1009 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1010 R_028980_ALU_CONST_CACHE_VS_0,
1011 (r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1012 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
1013 break;
1014 case PIPE_SHADER_FRAGMENT:
1015 rctx->ps_const_buffer.nregs = 0;
1016 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1017 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1018 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1019 0xFFFFFFFF, NULL);
1020 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1021 R_028940_ALU_CONST_CACHE_PS_0,
1022 (r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1023 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
1024 break;
1025 default:
1026 R600_ERR("unsupported %d\n", shader);
1027 return;
1028 }
1029 }
1030
1031 static void *evergreen_create_shader_state(struct pipe_context *ctx,
1032 const struct pipe_shader_state *state)
1033 {
1034 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
1035 int r;
1036
1037 r = r600_pipe_shader_create(ctx, shader, state->tokens);
1038 if (r) {
1039 return NULL;
1040 }
1041 return shader;
1042 }
1043
1044 static void evergreen_bind_ps_shader(struct pipe_context *ctx, void *state)
1045 {
1046 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1047
1048 /* TODO delete old shader */
1049 rctx->ps_shader = (struct r600_pipe_shader *)state;
1050 }
1051
1052 static void evergreen_bind_vs_shader(struct pipe_context *ctx, void *state)
1053 {
1054 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1055
1056 /* TODO delete old shader */
1057 rctx->vs_shader = (struct r600_pipe_shader *)state;
1058 }
1059
1060 static void evergreen_delete_ps_shader(struct pipe_context *ctx, void *state)
1061 {
1062 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1063 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1064
1065 if (rctx->ps_shader == shader) {
1066 rctx->ps_shader = NULL;
1067 }
1068 /* TODO proper delete */
1069 free(shader);
1070 }
1071
1072 static void evergreen_delete_vs_shader(struct pipe_context *ctx, void *state)
1073 {
1074 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1075 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1076
1077 if (rctx->vs_shader == shader) {
1078 rctx->vs_shader = NULL;
1079 }
1080 /* TODO proper delete */
1081 free(shader);
1082 }
1083
1084 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
1085 {
1086 rctx->context.create_blend_state = evergreen_create_blend_state;
1087 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1088 rctx->context.create_fs_state = evergreen_create_shader_state;
1089 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1090 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1091 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1092 rctx->context.create_vertex_elements_state = evergreen_create_vertex_elements;
1093 rctx->context.create_vs_state = evergreen_create_shader_state;
1094 rctx->context.bind_blend_state = evergreen_bind_blend_state;
1095 rctx->context.bind_depth_stencil_alpha_state = evergreen_bind_state;
1096 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1097 rctx->context.bind_fs_state = evergreen_bind_ps_shader;
1098 rctx->context.bind_rasterizer_state = evergreen_bind_rs_state;
1099 rctx->context.bind_vertex_elements_state = evergreen_bind_vertex_elements;
1100 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1101 rctx->context.bind_vs_state = evergreen_bind_vs_shader;
1102 rctx->context.delete_blend_state = evergreen_delete_state;
1103 rctx->context.delete_depth_stencil_alpha_state = evergreen_delete_state;
1104 rctx->context.delete_fs_state = evergreen_delete_ps_shader;
1105 rctx->context.delete_rasterizer_state = evergreen_delete_rs_state;
1106 rctx->context.delete_sampler_state = evergreen_delete_state;
1107 rctx->context.delete_vertex_elements_state = evergreen_delete_vertex_element;
1108 rctx->context.delete_vs_state = evergreen_delete_vs_shader;
1109 rctx->context.set_blend_color = evergreen_set_blend_color;
1110 rctx->context.set_clip_state = evergreen_set_clip_state;
1111 rctx->context.set_constant_buffer = evergreen_set_constant_buffer;
1112 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1113 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1114 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1115 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1116 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1117 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1118 rctx->context.set_vertex_buffers = evergreen_set_vertex_buffers;
1119 rctx->context.set_index_buffer = evergreen_set_index_buffer;
1120 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1121 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1122 rctx->context.sampler_view_destroy = evergreen_sampler_view_destroy;
1123 }
1124
1125 void evergreen_init_config(struct r600_pipe_context *rctx)
1126 {
1127 struct r600_pipe_state *rstate = &rctx->config;
1128 int ps_prio;
1129 int vs_prio;
1130 int gs_prio;
1131 int es_prio;
1132 int hs_prio, cs_prio, ls_prio;
1133 int num_ps_gprs;
1134 int num_vs_gprs;
1135 int num_gs_gprs;
1136 int num_es_gprs;
1137 int num_hs_gprs;
1138 int num_ls_gprs;
1139 int num_temp_gprs;
1140 int num_ps_threads;
1141 int num_vs_threads;
1142 int num_gs_threads;
1143 int num_es_threads;
1144 int num_hs_threads;
1145 int num_ls_threads;
1146 int num_ps_stack_entries;
1147 int num_vs_stack_entries;
1148 int num_gs_stack_entries;
1149 int num_es_stack_entries;
1150 int num_hs_stack_entries;
1151 int num_ls_stack_entries;
1152 enum radeon_family family;
1153 unsigned tmp;
1154
1155 family = r600_get_family(rctx->radeon);
1156 ps_prio = 0;
1157 vs_prio = 1;
1158 gs_prio = 2;
1159 es_prio = 3;
1160 hs_prio = 0;
1161 ls_prio = 0;
1162 cs_prio = 0;
1163
1164 switch (family) {
1165 case CHIP_CEDAR:
1166 default:
1167 num_ps_gprs = 93;
1168 num_vs_gprs = 46;
1169 num_temp_gprs = 4;
1170 num_gs_gprs = 31;
1171 num_es_gprs = 31;
1172 num_hs_gprs = 23;
1173 num_ls_gprs = 23;
1174 num_ps_threads = 96;
1175 num_vs_threads = 16;
1176 num_gs_threads = 16;
1177 num_es_threads = 16;
1178 num_hs_threads = 16;
1179 num_ls_threads = 16;
1180 num_ps_stack_entries = 42;
1181 num_vs_stack_entries = 42;
1182 num_gs_stack_entries = 42;
1183 num_es_stack_entries = 42;
1184 num_hs_stack_entries = 42;
1185 num_ls_stack_entries = 42;
1186 break;
1187 case CHIP_REDWOOD:
1188 num_ps_gprs = 93;
1189 num_vs_gprs = 46;
1190 num_temp_gprs = 4;
1191 num_gs_gprs = 31;
1192 num_es_gprs = 31;
1193 num_hs_gprs = 23;
1194 num_ls_gprs = 23;
1195 num_ps_threads = 128;
1196 num_vs_threads = 20;
1197 num_gs_threads = 20;
1198 num_es_threads = 20;
1199 num_hs_threads = 20;
1200 num_ls_threads = 20;
1201 num_ps_stack_entries = 42;
1202 num_vs_stack_entries = 42;
1203 num_gs_stack_entries = 42;
1204 num_es_stack_entries = 42;
1205 num_hs_stack_entries = 42;
1206 num_ls_stack_entries = 42;
1207 break;
1208 case CHIP_JUNIPER:
1209 num_ps_gprs = 93;
1210 num_vs_gprs = 46;
1211 num_temp_gprs = 4;
1212 num_gs_gprs = 31;
1213 num_es_gprs = 31;
1214 num_hs_gprs = 23;
1215 num_ls_gprs = 23;
1216 num_ps_threads = 128;
1217 num_vs_threads = 20;
1218 num_gs_threads = 20;
1219 num_es_threads = 20;
1220 num_hs_threads = 20;
1221 num_ls_threads = 20;
1222 num_ps_stack_entries = 85;
1223 num_vs_stack_entries = 85;
1224 num_gs_stack_entries = 85;
1225 num_es_stack_entries = 85;
1226 num_hs_stack_entries = 85;
1227 num_ls_stack_entries = 85;
1228 break;
1229 case CHIP_CYPRESS:
1230 case CHIP_HEMLOCK:
1231 num_ps_gprs = 93;
1232 num_vs_gprs = 46;
1233 num_temp_gprs = 4;
1234 num_gs_gprs = 31;
1235 num_es_gprs = 31;
1236 num_hs_gprs = 23;
1237 num_ls_gprs = 23;
1238 num_ps_threads = 128;
1239 num_vs_threads = 20;
1240 num_gs_threads = 20;
1241 num_es_threads = 20;
1242 num_hs_threads = 20;
1243 num_ls_threads = 20;
1244 num_ps_stack_entries = 85;
1245 num_vs_stack_entries = 85;
1246 num_gs_stack_entries = 85;
1247 num_es_stack_entries = 85;
1248 num_hs_stack_entries = 85;
1249 num_ls_stack_entries = 85;
1250 break;
1251 }
1252
1253 tmp = 0x00000000;
1254 switch (family) {
1255 case CHIP_CEDAR:
1256 break;
1257 default:
1258 tmp |= S_008C00_VC_ENABLE(1);
1259 break;
1260 }
1261 tmp |= S_008C00_EXPORT_SRC_C(1);
1262 tmp |= S_008C00_CS_PRIO(cs_prio);
1263 tmp |= S_008C00_LS_PRIO(ls_prio);
1264 tmp |= S_008C00_HS_PRIO(hs_prio);
1265 tmp |= S_008C00_PS_PRIO(ps_prio);
1266 tmp |= S_008C00_VS_PRIO(vs_prio);
1267 tmp |= S_008C00_GS_PRIO(gs_prio);
1268 tmp |= S_008C00_ES_PRIO(es_prio);
1269 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1270
1271 tmp = 0;
1272 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1273 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1274 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1275 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1276
1277 tmp = 0;
1278 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1279 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1280 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1281
1282 tmp = 0;
1283 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1284 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1285 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1286
1287 tmp = 0;
1288 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1289 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1290 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1291 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1292 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1293
1294 tmp = 0;
1295 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1296 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1297 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1298
1299 tmp = 0;
1300 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1301 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1302 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1303
1304 tmp = 0;
1305 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1306 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1307 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1308
1309 tmp = 0;
1310 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1311 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1312 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1313
1314 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1315 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1316
1317 // r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1318
1319 // r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1320 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1321 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1322
1323 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1324 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1325 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1326 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1327 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1328 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1329
1330 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1331 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1332 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1333 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1334
1335 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1336 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1337 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1338 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1339 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1340 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1341 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1342 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1343 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1344 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1345 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1346 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1347 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1348 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1349 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1350 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1351 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1352 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1353
1354 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1355 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1356 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1357 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1358 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1359 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1360 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1361 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1362 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1363 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1364 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1365 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1366 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1367 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1368 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1369 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1370 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1371 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1372 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1373 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1374 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1375 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1376 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1377 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1378 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1379 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1380 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1381 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1382 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1383 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1384 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1385 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1386
1387 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1388 0x0, 0xFFFFFFFF, NULL);
1389
1390 r600_context_pipe_state_set(&rctx->ctx, rstate);
1391 }
1392
1393 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
1394 void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
1395 {
1396 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1397 struct r600_pipe_state *rstate;
1398 struct r600_resource *rbuffer;
1399 unsigned i, j, offset, prim;
1400 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
1401 struct pipe_vertex_buffer *vertex_buffer;
1402 struct r600_draw rdraw;
1403 struct r600_pipe_state vgt;
1404 struct r600_drawl draw;
1405
1406 if (rctx->any_user_vbs) {
1407 r600_upload_user_buffers(rctx);
1408 rctx->any_user_vbs = FALSE;
1409 }
1410
1411 memset(&draw, 0, sizeof(struct r600_drawl));
1412 draw.ctx = ctx;
1413 draw.mode = info->mode;
1414 draw.start = info->start;
1415 draw.count = info->count;
1416 if (info->indexed && rctx->index_buffer.buffer) {
1417 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
1418 draw.min_index = info->min_index;
1419 draw.max_index = info->max_index;
1420 draw.index_bias = info->index_bias;
1421
1422 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
1423 &rctx->index_buffer.index_size,
1424 &draw.start,
1425 info->count);
1426
1427 draw.index_size = rctx->index_buffer.index_size;
1428 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
1429 draw.index_buffer_offset = draw.start * draw.index_size;
1430 draw.start = 0;
1431 r600_upload_index_buffer(rctx, &draw);
1432 } else {
1433 draw.index_size = 0;
1434 draw.index_buffer = NULL;
1435 draw.min_index = info->min_index;
1436 draw.max_index = info->max_index;
1437 draw.index_bias = info->start;
1438 }
1439
1440 switch (draw.index_size) {
1441 case 2:
1442 vgt_draw_initiator = 0;
1443 vgt_dma_index_type = 0;
1444 break;
1445 case 4:
1446 vgt_draw_initiator = 0;
1447 vgt_dma_index_type = 1;
1448 break;
1449 case 0:
1450 vgt_draw_initiator = 2;
1451 vgt_dma_index_type = 0;
1452 break;
1453 default:
1454 R600_ERR("unsupported index size %d\n", draw.index_size);
1455 return;
1456 }
1457 if (r600_conv_pipe_prim(draw.mode, &prim))
1458 return;
1459
1460 /* rebuild vertex shader if input format changed */
1461 if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
1462 return;
1463 if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
1464 return;
1465
1466 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
1467 uint32_t word3, word2;
1468 uint32_t format;
1469 rstate = &rctx->vs_resource[i];
1470
1471 rstate->id = R600_PIPE_STATE_RESOURCE;
1472 rstate->nregs = 0;
1473
1474 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
1475 vertex_buffer = &rctx->vertex_buffer[j];
1476 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
1477 offset = rctx->vertex_elements->elements[i].src_offset +
1478 vertex_buffer->buffer_offset +
1479 r600_bo_offset(rbuffer->bo);
1480
1481 format = r600_translate_vertex_data_type(rctx->vertex_elements->elements[i].src_format);
1482
1483 word2 = format | S_030008_STRIDE(vertex_buffer->stride);
1484
1485 word3 = r600_translate_vertex_data_swizzle(rctx->vertex_elements->elements[i].src_format);
1486
1487 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
1488 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
1489 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
1490 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3, word3, 0xFFFFFFFF, NULL);
1491 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
1492 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
1493 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x00000000, 0xFFFFFFFF, NULL);
1494 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7, 0xC0000000, 0xFFFFFFFF, NULL);
1495 evergreen_vs_resource_set(&rctx->ctx, rstate, i);
1496 }
1497
1498 mask = 0;
1499 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
1500 mask |= (0xF << (i * 4));
1501 }
1502
1503 vgt.id = R600_PIPE_STATE_VGT;
1504 vgt.nregs = 0;
1505 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
1506 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw.index_bias, 0xFFFFFFFF, NULL);
1507 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
1508 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw.max_index, 0xFFFFFFFF, NULL);
1509 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw.min_index, 0xFFFFFFFF, NULL);
1510 r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
1511 r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
1512
1513 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1514 float offset_units = rctx->rasterizer->offset_units;
1515 unsigned offset_db_fmt_cntl = 0, depth;
1516
1517 switch (rctx->framebuffer.zsbuf->texture->format) {
1518 case PIPE_FORMAT_Z24X8_UNORM:
1519 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1520 depth = -24;
1521 offset_units *= 2.0f;
1522 break;
1523 case PIPE_FORMAT_Z32_FLOAT:
1524 depth = -23;
1525 offset_units *= 1.0f;
1526 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1527 break;
1528 case PIPE_FORMAT_Z16_UNORM:
1529 depth = -16;
1530 offset_units *= 4.0f;
1531 break;
1532 default:
1533 return;
1534 }
1535 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1536 r600_pipe_state_add_reg(&vgt,
1537 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1538 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1539 r600_pipe_state_add_reg(&vgt,
1540 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1541 fui(offset_units), 0xFFFFFFFF, NULL);
1542 r600_pipe_state_add_reg(&vgt,
1543 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1544 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1545 r600_pipe_state_add_reg(&vgt,
1546 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1547 fui(offset_units), 0xFFFFFFFF, NULL);
1548 r600_pipe_state_add_reg(&vgt,
1549 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1550 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1551 }
1552 r600_context_pipe_state_set(&rctx->ctx, &vgt);
1553
1554 rdraw.vgt_num_indices = draw.count;
1555 rdraw.vgt_num_instances = 1;
1556 rdraw.vgt_index_type = vgt_dma_index_type;
1557 rdraw.vgt_draw_initiator = vgt_draw_initiator;
1558 rdraw.indices = NULL;
1559 if (draw.index_buffer) {
1560 rbuffer = (struct r600_resource*)draw.index_buffer;
1561 rdraw.indices = rbuffer->bo;
1562 rdraw.indices_bo_offset = draw.index_buffer_offset;
1563 }
1564 evergreen_context_draw(&rctx->ctx, &rdraw);
1565
1566 pipe_resource_reference(&draw.index_buffer, NULL);
1567 }
1568
1569 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1570 {
1571 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1572 struct r600_pipe_state *rstate = &shader->rstate;
1573 struct r600_shader *rshader = &shader->shader;
1574 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
1575 boolean have_pos = FALSE, have_face = FALSE;
1576
1577 /* clear previous register */
1578 rstate->nregs = 0;
1579
1580 for (i = 0; i < rshader->ninput; i++) {
1581 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
1582 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1583 have_pos = TRUE;
1584 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
1585 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
1586 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
1587 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
1588 }
1589 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1590 have_face = TRUE;
1591 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
1592 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
1593 tmp |= S_028644_PT_SPRITE_TEX(1);
1594 }
1595 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
1596 }
1597 for (i = 0; i < rshader->noutput; i++) {
1598 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1599 r600_pipe_state_add_reg(rstate,
1600 R_02880C_DB_SHADER_CONTROL,
1601 S_02880C_Z_EXPORT_ENABLE(1),
1602 S_02880C_Z_EXPORT_ENABLE(1), NULL);
1603 }
1604
1605 exports_ps = 0;
1606 num_cout = 0;
1607 for (i = 0; i < rshader->noutput; i++) {
1608 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1609 exports_ps |= 1;
1610 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1611 num_cout++;
1612 }
1613 }
1614 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1615 if (!exports_ps) {
1616 /* always at least export 1 component per pixel */
1617 exports_ps = 2;
1618 }
1619
1620 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
1621 S_0286CC_PERSP_GRADIENT_ENA(1);
1622 spi_input_z = 0;
1623 if (have_pos) {
1624 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1);
1625 spi_input_z |= 1;
1626 }
1627 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1628 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1629 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1630 S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
1631 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1632 r600_pipe_state_add_reg(rstate,
1633 R_028840_SQ_PGM_START_PS,
1634 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1635 r600_pipe_state_add_reg(rstate,
1636 R_028844_SQ_PGM_RESOURCES_PS,
1637 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1638 S_028844_PRIME_CACHE_ON_DRAW(1) |
1639 S_028844_STACK_SIZE(rshader->bc.nstack),
1640 0xFFFFFFFF, NULL);
1641 r600_pipe_state_add_reg(rstate,
1642 R_028848_SQ_PGM_RESOURCES_2_PS,
1643 0x0, 0xFFFFFFFF, NULL);
1644 r600_pipe_state_add_reg(rstate,
1645 R_02884C_SQ_PGM_EXPORTS_PS,
1646 exports_ps, 0xFFFFFFFF, NULL);
1647 r600_pipe_state_add_reg(rstate,
1648 R_0286E0_SPI_BARYC_CNTL,
1649 S_0286E0_PERSP_CENTROID_ENA(1) |
1650 S_0286E0_LINEAR_CENTROID_ENA(1),
1651 0xFFFFFFFF, NULL);
1652
1653 if (rshader->uses_kill) {
1654 /* only set some bits here, the other bits are set in the dsa state */
1655 r600_pipe_state_add_reg(rstate,
1656 R_02880C_DB_SHADER_CONTROL,
1657 S_02880C_KILL_ENABLE(1),
1658 S_02880C_KILL_ENABLE(1), NULL);
1659 }
1660
1661 r600_pipe_state_add_reg(rstate,
1662 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
1663 0xFFFFFFFF, NULL);
1664 }
1665
1666 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1667 {
1668 struct r600_pipe_state *rstate = &shader->rstate;
1669 struct r600_shader *rshader = &shader->shader;
1670 unsigned spi_vs_out_id[10];
1671 unsigned i, tmp;
1672
1673 /* clear previous register */
1674 rstate->nregs = 0;
1675
1676 /* so far never got proper semantic id from tgsi */
1677 for (i = 0; i < 10; i++) {
1678 spi_vs_out_id[i] = 0;
1679 }
1680 for (i = 0; i < 32; i++) {
1681 tmp = i << ((i & 3) * 8);
1682 spi_vs_out_id[i / 4] |= tmp;
1683 }
1684 for (i = 0; i < 10; i++) {
1685 r600_pipe_state_add_reg(rstate,
1686 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1687 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1688 }
1689
1690 r600_pipe_state_add_reg(rstate,
1691 R_0286C4_SPI_VS_OUT_CONFIG,
1692 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1693 0xFFFFFFFF, NULL);
1694 r600_pipe_state_add_reg(rstate,
1695 R_028860_SQ_PGM_RESOURCES_VS,
1696 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1697 S_028860_STACK_SIZE(rshader->bc.nstack),
1698 0xFFFFFFFF, NULL);
1699 r600_pipe_state_add_reg(rstate,
1700 R_028864_SQ_PGM_RESOURCES_2_VS,
1701 0x0, 0xFFFFFFFF, NULL);
1702 r600_pipe_state_add_reg(rstate,
1703 R_0288A8_SQ_PGM_RESOURCES_FS,
1704 0x00000000, 0xFFFFFFFF, NULL);
1705 r600_pipe_state_add_reg(rstate,
1706 R_02885C_SQ_PGM_START_VS,
1707 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1708 r600_pipe_state_add_reg(rstate,
1709 R_0288A4_SQ_PGM_START_FS,
1710 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1711
1712 r600_pipe_state_add_reg(rstate,
1713 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1714 0xFFFFFFFF, NULL);
1715 }
1716
1717 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1718 {
1719 struct pipe_depth_stencil_alpha_state dsa;
1720 struct r600_pipe_state *rstate;
1721
1722 memset(&dsa, 0, sizeof(dsa));
1723
1724 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1725 r600_pipe_state_add_reg(rstate,
1726 R_02880C_DB_SHADER_CONTROL,
1727 0x0,
1728 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1729 r600_pipe_state_add_reg(rstate,
1730 R_028000_DB_RENDER_CONTROL,
1731 S_028000_DEPTH_COPY_ENABLE(1) |
1732 S_028000_STENCIL_COPY_ENABLE(1) |
1733 S_028000_COPY_CENTROID(1),
1734 S_028000_DEPTH_COPY_ENABLE(1) |
1735 S_028000_STENCIL_COPY_ENABLE(1) |
1736 S_028000_COPY_CENTROID(1), NULL);
1737 return rstate;
1738 }