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r600g: remove obsolete todo comments
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <stdio.h>
25 #include <errno.h>
26 #include "pipe/p_defines.h"
27 #include "pipe/p_state.h"
28 #include "pipe/p_context.h"
29 #include "tgsi/tgsi_scan.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "tgsi/tgsi_util.h"
32 #include "util/u_blitter.h"
33 #include "util/u_double_list.h"
34 #include "util/u_transfer.h"
35 #include "util/u_surface.h"
36 #include "util/u_pack_color.h"
37 #include "util/u_memory.h"
38 #include "util/u_inlines.h"
39 #include "util/u_framebuffer.h"
40 #include "pipebuffer/pb_buffer.h"
41 #include "r600.h"
42 #include "evergreend.h"
43 #include "r600_resource.h"
44 #include "r600_shader.h"
45 #include "r600_pipe.h"
46 #include "r600_formats.h"
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(unsigned dim)
174 {
175 switch (dim) {
176 default:
177 case PIPE_TEXTURE_1D:
178 return V_030000_SQ_TEX_DIM_1D;
179 case PIPE_TEXTURE_1D_ARRAY:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY;
181 case PIPE_TEXTURE_2D:
182 case PIPE_TEXTURE_RECT:
183 return V_030000_SQ_TEX_DIM_2D;
184 case PIPE_TEXTURE_2D_ARRAY:
185 return V_030000_SQ_TEX_DIM_2D_ARRAY;
186 case PIPE_TEXTURE_3D:
187 return V_030000_SQ_TEX_DIM_3D;
188 case PIPE_TEXTURE_CUBE:
189 return V_030000_SQ_TEX_DIM_CUBEMAP;
190 }
191 }
192
193 static uint32_t r600_translate_dbformat(enum pipe_format format)
194 {
195 switch (format) {
196 case PIPE_FORMAT_Z16_UNORM:
197 return V_028040_Z_16;
198 case PIPE_FORMAT_Z24X8_UNORM:
199 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
200 return V_028040_Z_24;
201 case PIPE_FORMAT_Z32_FLOAT:
202 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
203 return V_028040_Z_32_FLOAT;
204 default:
205 return ~0U;
206 }
207 }
208
209 static uint32_t r600_translate_colorswap(enum pipe_format format)
210 {
211 switch (format) {
212 /* 8-bit buffers. */
213 case PIPE_FORMAT_L4A4_UNORM:
214 case PIPE_FORMAT_A4R4_UNORM:
215 return V_028C70_SWAP_ALT;
216
217 case PIPE_FORMAT_A8_UNORM:
218 case PIPE_FORMAT_A8_UINT:
219 case PIPE_FORMAT_A8_SINT:
220 case PIPE_FORMAT_R4A4_UNORM:
221 return V_028C70_SWAP_ALT_REV;
222 case PIPE_FORMAT_I8_UNORM:
223 case PIPE_FORMAT_L8_UNORM:
224 case PIPE_FORMAT_I8_UINT:
225 case PIPE_FORMAT_I8_SINT:
226 case PIPE_FORMAT_L8_UINT:
227 case PIPE_FORMAT_L8_SINT:
228 case PIPE_FORMAT_L8_SRGB:
229 case PIPE_FORMAT_R8_UNORM:
230 case PIPE_FORMAT_R8_SNORM:
231 case PIPE_FORMAT_R8_UINT:
232 case PIPE_FORMAT_R8_SINT:
233 return V_028C70_SWAP_STD;
234
235 /* 16-bit buffers. */
236 case PIPE_FORMAT_B5G6R5_UNORM:
237 return V_028C70_SWAP_STD_REV;
238
239 case PIPE_FORMAT_B5G5R5A1_UNORM:
240 case PIPE_FORMAT_B5G5R5X1_UNORM:
241 return V_028C70_SWAP_ALT;
242
243 case PIPE_FORMAT_B4G4R4A4_UNORM:
244 case PIPE_FORMAT_B4G4R4X4_UNORM:
245 return V_028C70_SWAP_ALT;
246
247 case PIPE_FORMAT_Z16_UNORM:
248 return V_028C70_SWAP_STD;
249
250 case PIPE_FORMAT_L8A8_UNORM:
251 case PIPE_FORMAT_L8A8_UINT:
252 case PIPE_FORMAT_L8A8_SINT:
253 case PIPE_FORMAT_L8A8_SRGB:
254 return V_028C70_SWAP_ALT;
255 case PIPE_FORMAT_R8G8_UNORM:
256 case PIPE_FORMAT_R8G8_UINT:
257 case PIPE_FORMAT_R8G8_SINT:
258 return V_028C70_SWAP_STD;
259
260 case PIPE_FORMAT_R16_UNORM:
261 case PIPE_FORMAT_R16_UINT:
262 case PIPE_FORMAT_R16_SINT:
263 case PIPE_FORMAT_R16_FLOAT:
264 return V_028C70_SWAP_STD;
265
266 /* 32-bit buffers. */
267 case PIPE_FORMAT_A8B8G8R8_SRGB:
268 return V_028C70_SWAP_STD_REV;
269 case PIPE_FORMAT_B8G8R8A8_SRGB:
270 return V_028C70_SWAP_ALT;
271
272 case PIPE_FORMAT_B8G8R8A8_UNORM:
273 case PIPE_FORMAT_B8G8R8X8_UNORM:
274 return V_028C70_SWAP_ALT;
275
276 case PIPE_FORMAT_A8R8G8B8_UNORM:
277 case PIPE_FORMAT_X8R8G8B8_UNORM:
278 return V_028C70_SWAP_ALT_REV;
279 case PIPE_FORMAT_R8G8B8A8_SNORM:
280 case PIPE_FORMAT_R8G8B8A8_UNORM:
281 case PIPE_FORMAT_R8G8B8A8_SSCALED:
282 case PIPE_FORMAT_R8G8B8A8_USCALED:
283 case PIPE_FORMAT_R8G8B8A8_SINT:
284 case PIPE_FORMAT_R8G8B8A8_UINT:
285 case PIPE_FORMAT_R8G8B8X8_UNORM:
286 return V_028C70_SWAP_STD;
287
288 case PIPE_FORMAT_A8B8G8R8_UNORM:
289 case PIPE_FORMAT_X8B8G8R8_UNORM:
290 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
291 return V_028C70_SWAP_STD_REV;
292
293 case PIPE_FORMAT_Z24X8_UNORM:
294 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
295 return V_028C70_SWAP_STD;
296
297 case PIPE_FORMAT_X8Z24_UNORM:
298 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
299 return V_028C70_SWAP_STD;
300
301 case PIPE_FORMAT_R10G10B10A2_UNORM:
302 case PIPE_FORMAT_R10G10B10X2_SNORM:
303 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
304 return V_028C70_SWAP_STD;
305
306 case PIPE_FORMAT_B10G10R10A2_UNORM:
307 case PIPE_FORMAT_B10G10R10A2_UINT:
308 return V_028C70_SWAP_ALT;
309
310 case PIPE_FORMAT_R11G11B10_FLOAT:
311 case PIPE_FORMAT_R32_FLOAT:
312 case PIPE_FORMAT_R32_UINT:
313 case PIPE_FORMAT_R32_SINT:
314 case PIPE_FORMAT_Z32_FLOAT:
315 case PIPE_FORMAT_R16G16_FLOAT:
316 case PIPE_FORMAT_R16G16_UNORM:
317 case PIPE_FORMAT_R16G16_UINT:
318 case PIPE_FORMAT_R16G16_SINT:
319 return V_028C70_SWAP_STD;
320
321 /* 64-bit buffers. */
322 case PIPE_FORMAT_R32G32_FLOAT:
323 case PIPE_FORMAT_R32G32_UINT:
324 case PIPE_FORMAT_R32G32_SINT:
325 case PIPE_FORMAT_R16G16B16A16_UNORM:
326 case PIPE_FORMAT_R16G16B16A16_SNORM:
327 case PIPE_FORMAT_R16G16B16A16_USCALED:
328 case PIPE_FORMAT_R16G16B16A16_SSCALED:
329 case PIPE_FORMAT_R16G16B16A16_UINT:
330 case PIPE_FORMAT_R16G16B16A16_SINT:
331 case PIPE_FORMAT_R16G16B16A16_FLOAT:
332 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
333
334 /* 128-bit buffers. */
335 case PIPE_FORMAT_R32G32B32A32_FLOAT:
336 case PIPE_FORMAT_R32G32B32A32_SNORM:
337 case PIPE_FORMAT_R32G32B32A32_UNORM:
338 case PIPE_FORMAT_R32G32B32A32_SSCALED:
339 case PIPE_FORMAT_R32G32B32A32_USCALED:
340 case PIPE_FORMAT_R32G32B32A32_SINT:
341 case PIPE_FORMAT_R32G32B32A32_UINT:
342 return V_028C70_SWAP_STD;
343 default:
344 R600_ERR("unsupported colorswap format %d\n", format);
345 return ~0U;
346 }
347 return ~0U;
348 }
349
350 static uint32_t r600_translate_colorformat(enum pipe_format format)
351 {
352 switch (format) {
353 /* 8-bit buffers. */
354 case PIPE_FORMAT_A8_UNORM:
355 case PIPE_FORMAT_A8_UINT:
356 case PIPE_FORMAT_A8_SINT:
357 case PIPE_FORMAT_I8_UNORM:
358 case PIPE_FORMAT_I8_UINT:
359 case PIPE_FORMAT_I8_SINT:
360 case PIPE_FORMAT_L8_UNORM:
361 case PIPE_FORMAT_L8_UINT:
362 case PIPE_FORMAT_L8_SINT:
363 case PIPE_FORMAT_L8_SRGB:
364 case PIPE_FORMAT_R8_UNORM:
365 case PIPE_FORMAT_R8_SNORM:
366 case PIPE_FORMAT_R8_UINT:
367 case PIPE_FORMAT_R8_SINT:
368 return V_028C70_COLOR_8;
369
370 /* 16-bit buffers. */
371 case PIPE_FORMAT_B5G6R5_UNORM:
372 return V_028C70_COLOR_5_6_5;
373
374 case PIPE_FORMAT_B5G5R5A1_UNORM:
375 case PIPE_FORMAT_B5G5R5X1_UNORM:
376 return V_028C70_COLOR_1_5_5_5;
377
378 case PIPE_FORMAT_B4G4R4A4_UNORM:
379 case PIPE_FORMAT_B4G4R4X4_UNORM:
380 return V_028C70_COLOR_4_4_4_4;
381
382 case PIPE_FORMAT_Z16_UNORM:
383 return V_028C70_COLOR_16;
384
385 case PIPE_FORMAT_L8A8_UNORM:
386 case PIPE_FORMAT_L8A8_UINT:
387 case PIPE_FORMAT_L8A8_SINT:
388 case PIPE_FORMAT_L8A8_SRGB:
389 case PIPE_FORMAT_R8G8_UNORM:
390 case PIPE_FORMAT_R8G8_UINT:
391 case PIPE_FORMAT_R8G8_SINT:
392 return V_028C70_COLOR_8_8;
393
394 case PIPE_FORMAT_R16_UNORM:
395 case PIPE_FORMAT_R16_UINT:
396 case PIPE_FORMAT_R16_SINT:
397 return V_028C70_COLOR_16;
398
399 case PIPE_FORMAT_R16_FLOAT:
400 return V_028C70_COLOR_16_FLOAT;
401
402 /* 32-bit buffers. */
403 case PIPE_FORMAT_A8B8G8R8_SRGB:
404 case PIPE_FORMAT_A8B8G8R8_UNORM:
405 case PIPE_FORMAT_A8R8G8B8_UNORM:
406 case PIPE_FORMAT_B8G8R8A8_SRGB:
407 case PIPE_FORMAT_B8G8R8A8_UNORM:
408 case PIPE_FORMAT_B8G8R8X8_UNORM:
409 case PIPE_FORMAT_R8G8B8A8_SNORM:
410 case PIPE_FORMAT_R8G8B8A8_UNORM:
411 case PIPE_FORMAT_R8G8B8X8_UNORM:
412 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
413 case PIPE_FORMAT_X8B8G8R8_UNORM:
414 case PIPE_FORMAT_X8R8G8B8_UNORM:
415 case PIPE_FORMAT_R8G8B8_UNORM:
416 case PIPE_FORMAT_R8G8B8A8_SSCALED:
417 case PIPE_FORMAT_R8G8B8A8_USCALED:
418 case PIPE_FORMAT_R8G8B8A8_SINT:
419 case PIPE_FORMAT_R8G8B8A8_UINT:
420 return V_028C70_COLOR_8_8_8_8;
421
422 case PIPE_FORMAT_R10G10B10A2_UNORM:
423 case PIPE_FORMAT_R10G10B10X2_SNORM:
424 case PIPE_FORMAT_B10G10R10A2_UNORM:
425 case PIPE_FORMAT_B10G10R10A2_UINT:
426 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
427 return V_028C70_COLOR_2_10_10_10;
428
429 case PIPE_FORMAT_Z24X8_UNORM:
430 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
431 return V_028C70_COLOR_8_24;
432
433 case PIPE_FORMAT_X8Z24_UNORM:
434 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
435 return V_028C70_COLOR_24_8;
436
437 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
438 return V_028C70_COLOR_X24_8_32_FLOAT;
439
440 case PIPE_FORMAT_R32_UINT:
441 case PIPE_FORMAT_R32_SINT:
442 return V_028C70_COLOR_32;
443
444 case PIPE_FORMAT_R32_FLOAT:
445 case PIPE_FORMAT_Z32_FLOAT:
446 return V_028C70_COLOR_32_FLOAT;
447
448 case PIPE_FORMAT_R16G16_FLOAT:
449 return V_028C70_COLOR_16_16_FLOAT;
450
451 case PIPE_FORMAT_R16G16_SSCALED:
452 case PIPE_FORMAT_R16G16_UNORM:
453 case PIPE_FORMAT_R16G16_UINT:
454 case PIPE_FORMAT_R16G16_SINT:
455 return V_028C70_COLOR_16_16;
456
457 case PIPE_FORMAT_R11G11B10_FLOAT:
458 return V_028C70_COLOR_10_11_11_FLOAT;
459
460 /* 64-bit buffers. */
461 case PIPE_FORMAT_R16G16B16_USCALED:
462 case PIPE_FORMAT_R16G16B16_SSCALED:
463 case PIPE_FORMAT_R16G16B16A16_UINT:
464 case PIPE_FORMAT_R16G16B16A16_SINT:
465 case PIPE_FORMAT_R16G16B16A16_USCALED:
466 case PIPE_FORMAT_R16G16B16A16_SSCALED:
467 case PIPE_FORMAT_R16G16B16A16_UNORM:
468 case PIPE_FORMAT_R16G16B16A16_SNORM:
469 return V_028C70_COLOR_16_16_16_16;
470
471 case PIPE_FORMAT_R16G16B16_FLOAT:
472 case PIPE_FORMAT_R16G16B16A16_FLOAT:
473 return V_028C70_COLOR_16_16_16_16_FLOAT;
474
475 case PIPE_FORMAT_R32G32_FLOAT:
476 return V_028C70_COLOR_32_32_FLOAT;
477
478 case PIPE_FORMAT_R32G32_USCALED:
479 case PIPE_FORMAT_R32G32_SSCALED:
480 case PIPE_FORMAT_R32G32_SINT:
481 case PIPE_FORMAT_R32G32_UINT:
482 return V_028C70_COLOR_32_32;
483
484 /* 96-bit buffers. */
485 case PIPE_FORMAT_R32G32B32_FLOAT:
486 return V_028C70_COLOR_32_32_32_FLOAT;
487
488 /* 128-bit buffers. */
489 case PIPE_FORMAT_R32G32B32A32_SNORM:
490 case PIPE_FORMAT_R32G32B32A32_UNORM:
491 case PIPE_FORMAT_R32G32B32A32_SSCALED:
492 case PIPE_FORMAT_R32G32B32A32_USCALED:
493 case PIPE_FORMAT_R32G32B32A32_SINT:
494 case PIPE_FORMAT_R32G32B32A32_UINT:
495 return V_028C70_COLOR_32_32_32_32;
496 case PIPE_FORMAT_R32G32B32A32_FLOAT:
497 return V_028C70_COLOR_32_32_32_32_FLOAT;
498
499 /* YUV buffers. */
500 case PIPE_FORMAT_UYVY:
501 case PIPE_FORMAT_YUYV:
502 default:
503 return ~0U; /* Unsupported. */
504 }
505 }
506
507 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
508 {
509 if (R600_BIG_ENDIAN) {
510 switch(colorformat) {
511
512 /* 8-bit buffers. */
513 case V_028C70_COLOR_8:
514 return ENDIAN_NONE;
515
516 /* 16-bit buffers. */
517 case V_028C70_COLOR_5_6_5:
518 case V_028C70_COLOR_1_5_5_5:
519 case V_028C70_COLOR_4_4_4_4:
520 case V_028C70_COLOR_16:
521 case V_028C70_COLOR_8_8:
522 return ENDIAN_8IN16;
523
524 /* 32-bit buffers. */
525 case V_028C70_COLOR_8_8_8_8:
526 case V_028C70_COLOR_2_10_10_10:
527 case V_028C70_COLOR_8_24:
528 case V_028C70_COLOR_24_8:
529 case V_028C70_COLOR_32_FLOAT:
530 case V_028C70_COLOR_16_16_FLOAT:
531 case V_028C70_COLOR_16_16:
532 return ENDIAN_8IN32;
533
534 /* 64-bit buffers. */
535 case V_028C70_COLOR_16_16_16_16:
536 case V_028C70_COLOR_16_16_16_16_FLOAT:
537 return ENDIAN_8IN16;
538
539 case V_028C70_COLOR_32_32_FLOAT:
540 case V_028C70_COLOR_32_32:
541 case V_028C70_COLOR_X24_8_32_FLOAT:
542 return ENDIAN_8IN32;
543
544 /* 96-bit buffers. */
545 case V_028C70_COLOR_32_32_32_FLOAT:
546 /* 128-bit buffers. */
547 case V_028C70_COLOR_32_32_32_32_FLOAT:
548 case V_028C70_COLOR_32_32_32_32:
549 return ENDIAN_8IN32;
550 default:
551 return ENDIAN_NONE; /* Unsupported. */
552 }
553 } else {
554 return ENDIAN_NONE;
555 }
556 }
557
558 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
559 {
560 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
561 }
562
563 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
564 {
565 return r600_translate_colorformat(format) != ~0U &&
566 r600_translate_colorswap(format) != ~0U;
567 }
568
569 static bool r600_is_zs_format_supported(enum pipe_format format)
570 {
571 return r600_translate_dbformat(format) != ~0U;
572 }
573
574 boolean evergreen_is_format_supported(struct pipe_screen *screen,
575 enum pipe_format format,
576 enum pipe_texture_target target,
577 unsigned sample_count,
578 unsigned usage)
579 {
580 unsigned retval = 0;
581
582 if (target >= PIPE_MAX_TEXTURE_TYPES) {
583 R600_ERR("r600: unsupported texture type %d\n", target);
584 return FALSE;
585 }
586
587 if (!util_format_is_supported(format, usage))
588 return FALSE;
589
590 /* Multisample */
591 if (sample_count > 1)
592 return FALSE;
593
594 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
595 r600_is_sampler_format_supported(screen, format)) {
596 retval |= PIPE_BIND_SAMPLER_VIEW;
597 }
598
599 if ((usage & (PIPE_BIND_RENDER_TARGET |
600 PIPE_BIND_DISPLAY_TARGET |
601 PIPE_BIND_SCANOUT |
602 PIPE_BIND_SHARED)) &&
603 r600_is_colorbuffer_format_supported(format)) {
604 retval |= usage &
605 (PIPE_BIND_RENDER_TARGET |
606 PIPE_BIND_DISPLAY_TARGET |
607 PIPE_BIND_SCANOUT |
608 PIPE_BIND_SHARED);
609 }
610
611 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
612 r600_is_zs_format_supported(format)) {
613 retval |= PIPE_BIND_DEPTH_STENCIL;
614 }
615
616 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
617 r600_is_vertex_format_supported(format)) {
618 retval |= PIPE_BIND_VERTEX_BUFFER;
619 }
620
621 if (usage & PIPE_BIND_TRANSFER_READ)
622 retval |= PIPE_BIND_TRANSFER_READ;
623 if (usage & PIPE_BIND_TRANSFER_WRITE)
624 retval |= PIPE_BIND_TRANSFER_WRITE;
625
626 return retval == usage;
627 }
628
629 static void *evergreen_create_blend_state(struct pipe_context *ctx,
630 const struct pipe_blend_state *state)
631 {
632 struct r600_context *rctx = (struct r600_context *)ctx;
633 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
634 struct r600_pipe_state *rstate;
635 uint32_t color_control, target_mask;
636 /* XXX there is more then 8 framebuffer */
637 unsigned blend_cntl[8];
638
639 if (blend == NULL) {
640 return NULL;
641 }
642
643 rstate = &blend->rstate;
644
645 rstate->id = R600_PIPE_STATE_BLEND;
646
647 target_mask = 0;
648 color_control = S_028808_MODE(1);
649 if (state->logicop_enable) {
650 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
651 } else {
652 color_control |= (0xcc << 16);
653 }
654 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
655 if (state->independent_blend_enable) {
656 for (int i = 0; i < 8; i++) {
657 target_mask |= (state->rt[i].colormask << (4 * i));
658 }
659 } else {
660 for (int i = 0; i < 8; i++) {
661 target_mask |= (state->rt[0].colormask << (4 * i));
662 }
663 }
664 blend->cb_target_mask = target_mask;
665
666 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
667 color_control, NULL, 0);
668
669 for (int i = 0; i < 8; i++) {
670 /* state->rt entries > 0 only written if independent blending */
671 const int j = state->independent_blend_enable ? i : 0;
672
673 unsigned eqRGB = state->rt[j].rgb_func;
674 unsigned srcRGB = state->rt[j].rgb_src_factor;
675 unsigned dstRGB = state->rt[j].rgb_dst_factor;
676 unsigned eqA = state->rt[j].alpha_func;
677 unsigned srcA = state->rt[j].alpha_src_factor;
678 unsigned dstA = state->rt[j].alpha_dst_factor;
679
680 blend_cntl[i] = 0;
681 if (!state->rt[j].blend_enable)
682 continue;
683
684 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
685 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
686 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
687 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
688
689 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
690 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
691 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
692 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
693 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
694 }
695 }
696 for (int i = 0; i < 8; i++) {
697 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], NULL, 0);
698 }
699
700 return rstate;
701 }
702
703 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
704 const struct pipe_depth_stencil_alpha_state *state)
705 {
706 struct r600_context *rctx = (struct r600_context *)ctx;
707 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
708 unsigned db_depth_control, alpha_test_control, alpha_ref;
709 unsigned db_render_control;
710 struct r600_pipe_state *rstate;
711
712 if (dsa == NULL) {
713 return NULL;
714 }
715
716 dsa->valuemask[0] = state->stencil[0].valuemask;
717 dsa->valuemask[1] = state->stencil[1].valuemask;
718 dsa->writemask[0] = state->stencil[0].writemask;
719 dsa->writemask[1] = state->stencil[1].writemask;
720
721 rstate = &dsa->rstate;
722
723 rstate->id = R600_PIPE_STATE_DSA;
724 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
725 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
726 S_028800_ZFUNC(state->depth.func);
727
728 /* stencil */
729 if (state->stencil[0].enabled) {
730 db_depth_control |= S_028800_STENCIL_ENABLE(1);
731 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
732 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
733 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
734 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
735
736 if (state->stencil[1].enabled) {
737 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
738 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
739 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
740 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
741 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
742 }
743 }
744
745 /* alpha */
746 alpha_test_control = 0;
747 alpha_ref = 0;
748 if (state->alpha.enabled) {
749 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
750 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
751 alpha_ref = fui(state->alpha.ref_value);
752 }
753 dsa->alpha_ref = alpha_ref;
754
755 /* misc */
756 db_render_control = 0;
757 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
758 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
759 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0);
760 return rstate;
761 }
762
763 static void *evergreen_create_rs_state(struct pipe_context *ctx,
764 const struct pipe_rasterizer_state *state)
765 {
766 struct r600_context *rctx = (struct r600_context *)ctx;
767 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
768 struct r600_pipe_state *rstate;
769 unsigned tmp;
770 unsigned prov_vtx = 1, polygon_dual_mode;
771 unsigned clip_rule;
772 float psize_min, psize_max;
773
774 if (rs == NULL) {
775 return NULL;
776 }
777
778 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
779 state->fill_back != PIPE_POLYGON_MODE_FILL);
780
781 if (state->flatshade_first)
782 prov_vtx = 0;
783
784 rstate = &rs->rstate;
785 rs->flatshade = state->flatshade;
786 rs->sprite_coord_enable = state->sprite_coord_enable;
787 rs->two_side = state->light_twoside;
788 rs->clip_plane_enable = state->clip_plane_enable;
789 rs->pa_sc_line_stipple = state->line_stipple_enable ?
790 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
791 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
792 rs->pa_cl_clip_cntl =
793 S_028810_PS_UCP_MODE(3) |
794 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
795 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
796 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
797
798 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
799
800 /* offset */
801 rs->offset_units = state->offset_units;
802 rs->offset_scale = state->offset_scale * 12.0f;
803
804 rstate->id = R600_PIPE_STATE_RASTERIZER;
805 tmp = S_0286D4_FLAT_SHADE_ENA(1);
806 if (state->sprite_coord_enable) {
807 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
808 S_0286D4_PNT_SPRITE_OVRD_X(2) |
809 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
810 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
811 S_0286D4_PNT_SPRITE_OVRD_W(1);
812 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
813 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
814 }
815 }
816 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
817
818 /* point size 12.4 fixed point */
819 tmp = (unsigned)(state->point_size * 8.0);
820 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
821
822 if (state->point_size_per_vertex) {
823 psize_min = util_get_min_point_size(state);
824 psize_max = 8192;
825 } else {
826 /* Force the point size to be as if the vertex output was disabled. */
827 psize_min = state->point_size;
828 psize_max = state->point_size;
829 }
830 /* Divide by two, because 0.5 = 1 pixel. */
831 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
832 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
833 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
834 NULL, 0);
835
836 tmp = (unsigned)state->line_width * 8;
837 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
838 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
839 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
840 NULL, 0);
841
842 if (rctx->chip_class == CAYMAN) {
843 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
844 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
845 NULL, 0);
846 } else {
847 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
848 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
849 NULL, 0);
850 }
851 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
852 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0);
853 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
854 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
855 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
856 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
857 S_028814_FACE(!state->front_ccw) |
858 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
859 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
860 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
861 S_028814_POLY_MODE(polygon_dual_mode) |
862 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
863 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)),
864 NULL, 0);
865 return rstate;
866 }
867
868 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
869 const struct pipe_sampler_state *state)
870 {
871 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
872 union util_color uc;
873 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
874
875 if (rstate == NULL) {
876 return NULL;
877 }
878
879 rstate->id = R600_PIPE_STATE_SAMPLER;
880 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
881 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
882 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
883 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
884 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
885 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
886 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
887 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
888 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
889 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
890 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
891 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
892 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
893 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
894 NULL, 0);
895 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
896 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
897 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
898 S_03C008_TYPE(1),
899 NULL, 0);
900
901 if (uc.ui) {
902 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
903 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
904 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
905 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
906 }
907 return rstate;
908 }
909
910 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
911 struct pipe_resource *texture,
912 const struct pipe_sampler_view *state)
913 {
914 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
915 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
916 struct r600_pipe_resource_state *rstate;
917 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
918 unsigned format, endian;
919 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
920 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
921 unsigned height, depth, width;
922 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
923
924 if (view == NULL)
925 return NULL;
926 rstate = &view->state;
927
928 /* initialize base object */
929 view->base = *state;
930 view->base.texture = NULL;
931 pipe_reference(NULL, &texture->reference);
932 view->base.texture = texture;
933 view->base.reference.count = 1;
934 view->base.context = ctx;
935
936 swizzle[0] = state->swizzle_r;
937 swizzle[1] = state->swizzle_g;
938 swizzle[2] = state->swizzle_b;
939 swizzle[3] = state->swizzle_a;
940
941 format = r600_translate_texformat(ctx->screen, state->format,
942 swizzle,
943 &word4, &yuv_format);
944 if (format == ~0) {
945 format = 0;
946 }
947
948 if (tmp->is_depth && !tmp->is_flushing_texture) {
949 r600_texture_depth_flush(ctx, texture, TRUE);
950 tmp = tmp->flushed_depth_texture;
951 }
952
953 endian = r600_colorformat_endian_swap(format);
954
955 if (!rscreen->use_surface_alloc) {
956 height = texture->height0;
957 depth = texture->depth0;
958 width = texture->width0;
959 pitch = align(tmp->pitch_in_blocks[0] *
960 util_format_get_blockwidth(state->format), 8);
961 array_mode = tmp->array_mode[0];
962 tile_type = tmp->tile_type;
963 tile_split = 0;
964 macro_aspect = 0;
965 bankw = 0;
966 bankh = 0;
967 } else {
968 width = tmp->surface.level[0].npix_x;
969 height = tmp->surface.level[0].npix_y;
970 depth = tmp->surface.level[0].npix_z;
971 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
972 tile_type = tmp->tile_type;
973
974 switch (tmp->surface.level[0].mode) {
975 case RADEON_SURF_MODE_LINEAR_ALIGNED:
976 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
977 break;
978 case RADEON_SURF_MODE_2D:
979 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
980 break;
981 case RADEON_SURF_MODE_1D:
982 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
983 break;
984 case RADEON_SURF_MODE_LINEAR:
985 default:
986 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
987 break;
988 }
989 tile_split = tmp->surface.tile_split;
990 macro_aspect = tmp->surface.mtilea;
991 bankw = tmp->surface.bankw;
992 bankh = tmp->surface.bankh;
993 tile_split = eg_tile_split(tile_split);
994 macro_aspect = eg_macro_tile_aspect(macro_aspect);
995 bankw = eg_bank_wh(bankw);
996 bankh = eg_bank_wh(bankh);
997 }
998 /* 128 bit formats require tile type = 1 */
999 if (rscreen->chip_class == CAYMAN) {
1000 if (util_format_get_blocksize(state->format) >= 16)
1001 tile_type = 1;
1002 }
1003 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1004
1005 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1006 height = 1;
1007 depth = texture->array_size;
1008 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1009 depth = texture->array_size;
1010 }
1011
1012 rstate->bo[0] = &tmp->resource;
1013 rstate->bo[1] = &tmp->resource;
1014 rstate->bo_usage[0] = RADEON_USAGE_READ;
1015 rstate->bo_usage[1] = RADEON_USAGE_READ;
1016
1017 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1018 S_030000_PITCH((pitch / 8) - 1) |
1019 S_030000_TEX_WIDTH(width - 1));
1020 if (rscreen->chip_class == CAYMAN)
1021 rstate->val[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1022 else
1023 rstate->val[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1024 rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1025 S_030004_TEX_DEPTH(depth - 1) |
1026 S_030004_ARRAY_MODE(array_mode));
1027 rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1028 if (state->u.tex.last_level) {
1029 rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1030 } else {
1031 rstate->val[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1032 }
1033 rstate->val[4] = (word4 |
1034 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1035 S_030010_ENDIAN_SWAP(endian) |
1036 S_030010_BASE_LEVEL(state->u.tex.first_level));
1037 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1038 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1039 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1040 /* aniso max 16 samples */
1041 rstate->val[6] = (S_030018_MAX_ANISO(4)) |
1042 (S_030018_TILE_SPLIT(tile_split));
1043 rstate->val[7] = S_03001C_DATA_FORMAT(format) |
1044 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1045 S_03001C_BANK_WIDTH(bankw) |
1046 S_03001C_BANK_HEIGHT(bankh) |
1047 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1048 S_03001C_NUM_BANKS(nbanks);
1049
1050 return &view->base;
1051 }
1052
1053 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1054 struct pipe_sampler_view **views)
1055 {
1056 struct r600_context *rctx = (struct r600_context *)ctx;
1057 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1058
1059 for (int i = 0; i < count; i++) {
1060 if (resource[i]) {
1061 r600_context_pipe_state_set_vs_resource(rctx, &resource[i]->state,
1062 i + R600_MAX_CONST_BUFFERS);
1063 }
1064 }
1065 }
1066
1067 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1068 struct pipe_sampler_view **views)
1069 {
1070 struct r600_context *rctx = (struct r600_context *)ctx;
1071 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1072 int i;
1073 int has_depth = 0;
1074
1075 for (i = 0; i < count; i++) {
1076 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1077 if (resource[i]) {
1078 if (((struct r600_resource_texture *)resource[i]->base.texture)->is_depth)
1079 has_depth = 1;
1080 r600_context_pipe_state_set_ps_resource(rctx, &resource[i]->state,
1081 i + R600_MAX_CONST_BUFFERS);
1082 } else
1083 r600_context_pipe_state_set_ps_resource(rctx, NULL,
1084 i + R600_MAX_CONST_BUFFERS);
1085
1086 pipe_sampler_view_reference(
1087 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1088 views[i]);
1089 } else {
1090 if (resource[i]) {
1091 if (((struct r600_resource_texture *)resource[i]->base.texture)->is_depth)
1092 has_depth = 1;
1093 }
1094 }
1095 }
1096 for (i = count; i < NUM_TEX_UNITS; i++) {
1097 if (rctx->ps_samplers.views[i]) {
1098 r600_context_pipe_state_set_ps_resource(rctx, NULL,
1099 i + R600_MAX_CONST_BUFFERS);
1100 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1101 }
1102 }
1103 rctx->have_depth_texture = has_depth;
1104 rctx->ps_samplers.n_views = count;
1105 }
1106
1107 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1108 {
1109 struct r600_context *rctx = (struct r600_context *)ctx;
1110 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1111
1112 if (count)
1113 r600_inval_texture_cache(rctx);
1114
1115 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1116 rctx->ps_samplers.n_samplers = count;
1117
1118 for (int i = 0; i < count; i++) {
1119 evergreen_context_pipe_state_set_ps_sampler(rctx, rstates[i], i);
1120 }
1121 }
1122
1123 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1124 {
1125 struct r600_context *rctx = (struct r600_context *)ctx;
1126 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1127
1128 if (count)
1129 r600_inval_texture_cache(rctx);
1130
1131 for (int i = 0; i < count; i++) {
1132 evergreen_context_pipe_state_set_vs_sampler(rctx, rstates[i], i);
1133 }
1134 }
1135
1136 static void evergreen_set_clip_state(struct pipe_context *ctx,
1137 const struct pipe_clip_state *state)
1138 {
1139 struct r600_context *rctx = (struct r600_context *)ctx;
1140 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1141 struct pipe_resource *cbuf;
1142
1143 if (rstate == NULL)
1144 return;
1145
1146 rctx->clip = *state;
1147 rstate->id = R600_PIPE_STATE_CLIP;
1148 for (int i = 0; i < 6; i++) {
1149 r600_pipe_state_add_reg(rstate,
1150 R_0285BC_PA_CL_UCP0_X + i * 16,
1151 fui(state->ucp[i][0]), NULL, 0);
1152 r600_pipe_state_add_reg(rstate,
1153 R_0285C0_PA_CL_UCP0_Y + i * 16,
1154 fui(state->ucp[i][1]) , NULL, 0);
1155 r600_pipe_state_add_reg(rstate,
1156 R_0285C4_PA_CL_UCP0_Z + i * 16,
1157 fui(state->ucp[i][2]), NULL, 0);
1158 r600_pipe_state_add_reg(rstate,
1159 R_0285C8_PA_CL_UCP0_W + i * 16,
1160 fui(state->ucp[i][3]), NULL, 0);
1161 }
1162
1163 free(rctx->states[R600_PIPE_STATE_CLIP]);
1164 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1165 r600_context_pipe_state_set(rctx, rstate);
1166
1167 cbuf = pipe_user_buffer_create(ctx->screen,
1168 state->ucp,
1169 4*4*8, /* 8*4 floats */
1170 PIPE_BIND_CONSTANT_BUFFER);
1171 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
1172 pipe_resource_reference(&cbuf, NULL);
1173 }
1174
1175 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1176 const struct pipe_poly_stipple *state)
1177 {
1178 }
1179
1180 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1181 {
1182 }
1183
1184 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1185 const struct pipe_scissor_state *state)
1186 {
1187 struct r600_context *rctx = (struct r600_context *)ctx;
1188 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1189 uint32_t tl, br;
1190
1191 if (rstate == NULL)
1192 return;
1193
1194 rstate->id = R600_PIPE_STATE_SCISSOR;
1195 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1196 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1197 r600_pipe_state_add_reg(rstate,
1198 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1199 NULL, 0);
1200 r600_pipe_state_add_reg(rstate,
1201 R_028214_PA_SC_CLIPRECT_0_BR, br,
1202 NULL, 0);
1203 r600_pipe_state_add_reg(rstate,
1204 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1205 NULL, 0);
1206 r600_pipe_state_add_reg(rstate,
1207 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1208 NULL, 0);
1209 r600_pipe_state_add_reg(rstate,
1210 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1211 NULL, 0);
1212 r600_pipe_state_add_reg(rstate,
1213 R_028224_PA_SC_CLIPRECT_2_BR, br,
1214 NULL, 0);
1215 r600_pipe_state_add_reg(rstate,
1216 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1217 NULL, 0);
1218 r600_pipe_state_add_reg(rstate,
1219 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1220 NULL, 0);
1221
1222 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1223 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1224 r600_context_pipe_state_set(rctx, rstate);
1225 }
1226
1227 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1228 const struct pipe_viewport_state *state)
1229 {
1230 struct r600_context *rctx = (struct r600_context *)ctx;
1231 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1232
1233 if (rstate == NULL)
1234 return;
1235
1236 rctx->viewport = *state;
1237 rstate->id = R600_PIPE_STATE_VIEWPORT;
1238 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
1239 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
1240 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
1241 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
1242 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
1243 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
1244
1245 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1246 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1247 r600_context_pipe_state_set(rctx, rstate);
1248 }
1249
1250 static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1251 const struct pipe_framebuffer_state *state, int cb)
1252 {
1253 struct r600_screen *rscreen = rctx->screen;
1254 struct r600_resource_texture *rtex;
1255 struct r600_surface *surf;
1256 unsigned level = state->cbufs[cb]->u.tex.level;
1257 unsigned pitch, slice;
1258 unsigned color_info, color_attrib;
1259 unsigned format, swap, ntype, endian;
1260 uint64_t offset;
1261 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1262 const struct util_format_description *desc;
1263 int i;
1264 unsigned blend_clamp = 0, blend_bypass = 0;
1265
1266 surf = (struct r600_surface *)state->cbufs[cb];
1267 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1268
1269 if (rtex->is_depth)
1270 rctx->have_depth_fb = TRUE;
1271
1272 if (rtex->is_depth && !rtex->is_flushing_texture) {
1273 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1274 rtex = rtex->flushed_depth_texture;
1275 }
1276
1277 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1278 if (!rscreen->use_surface_alloc) {
1279 offset = r600_texture_get_offset(rtex,
1280 level, state->cbufs[cb]->u.tex.first_layer);
1281 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1282 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1283 if (slice) {
1284 slice = slice - 1;
1285 }
1286 color_info = S_028C70_ARRAY_MODE(rtex->array_mode[level]);
1287 tile_split = 0;
1288 macro_aspect = 0;
1289 bankw = 0;
1290 bankh = 0;
1291 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1292 tile_type = rtex->tile_type;
1293 } else {
1294 /* workaround for linear buffers */
1295 tile_type = 1;
1296 }
1297 } else {
1298 offset = rtex->surface.level[level].offset;
1299 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1300 offset += rtex->surface.level[level].slice_size *
1301 state->cbufs[cb]->u.tex.first_layer;
1302 }
1303 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1304 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1305 if (slice) {
1306 slice = slice - 1;
1307 }
1308 color_info = 0;
1309 switch (rtex->surface.level[level].mode) {
1310 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1311 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1312 tile_type = 1;
1313 break;
1314 case RADEON_SURF_MODE_1D:
1315 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1316 tile_type = rtex->tile_type;
1317 break;
1318 case RADEON_SURF_MODE_2D:
1319 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1320 tile_type = rtex->tile_type;
1321 break;
1322 case RADEON_SURF_MODE_LINEAR:
1323 default:
1324 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1325 tile_type = 1;
1326 break;
1327 }
1328 tile_split = rtex->surface.tile_split;
1329 macro_aspect = rtex->surface.mtilea;
1330 bankw = rtex->surface.bankw;
1331 bankh = rtex->surface.bankh;
1332 tile_split = eg_tile_split(tile_split);
1333 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1334 bankw = eg_bank_wh(bankw);
1335 bankh = eg_bank_wh(bankh);
1336 }
1337 /* 128 bit formats require tile type = 1 */
1338 if (rscreen->chip_class == CAYMAN) {
1339 if (util_format_get_blocksize(surf->base.format) >= 16)
1340 tile_type = 1;
1341 }
1342 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1343 desc = util_format_description(surf->base.format);
1344 for (i = 0; i < 4; i++) {
1345 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1346 break;
1347 }
1348 }
1349
1350 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1351 S_028C74_NUM_BANKS(nbanks) |
1352 S_028C74_BANK_WIDTH(bankw) |
1353 S_028C74_BANK_HEIGHT(bankh) |
1354 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1355 S_028C74_NON_DISP_TILING_ORDER(tile_type);
1356
1357 ntype = V_028C70_NUMBER_UNORM;
1358 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1359 ntype = V_028C70_NUMBER_SRGB;
1360 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1361 if (desc->channel[i].normalized)
1362 ntype = V_028C70_NUMBER_SNORM;
1363 else if (desc->channel[i].pure_integer)
1364 ntype = V_028C70_NUMBER_SINT;
1365 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1366 if (desc->channel[i].normalized)
1367 ntype = V_028C70_NUMBER_UNORM;
1368 else if (desc->channel[i].pure_integer)
1369 ntype = V_028C70_NUMBER_UINT;
1370 }
1371
1372 format = r600_translate_colorformat(surf->base.format);
1373 swap = r600_translate_colorswap(surf->base.format);
1374 if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1375 endian = ENDIAN_NONE;
1376 } else {
1377 endian = r600_colorformat_endian_swap(format);
1378 }
1379
1380 /* blend clamp should be set for all NORM/SRGB types */
1381 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1382 ntype == V_028C70_NUMBER_SRGB)
1383 blend_clamp = 1;
1384
1385 /* set blend bypass according to docs if SINT/UINT or
1386 8/24 COLOR variants */
1387 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1388 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1389 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1390 blend_clamp = 0;
1391 blend_bypass = 1;
1392 }
1393
1394 color_info |= S_028C70_FORMAT(format) |
1395 S_028C70_COMP_SWAP(swap) |
1396 S_028C70_BLEND_CLAMP(blend_clamp) |
1397 S_028C70_BLEND_BYPASS(blend_bypass) |
1398 S_028C70_NUMBER_TYPE(ntype) |
1399 S_028C70_ENDIAN(endian);
1400
1401 /* EXPORT_NORM is an optimzation that can be enabled for better
1402 * performance in certain cases.
1403 * EXPORT_NORM can be enabled if:
1404 * - 11-bit or smaller UNORM/SNORM/SRGB
1405 * - 16-bit or smaller FLOAT
1406 */
1407 /* XXX: This should probably be the same for all CBs if we want
1408 * useful alpha tests. */
1409 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1410 ((desc->channel[i].size < 12 &&
1411 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1412 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1413 (desc->channel[i].size < 17 &&
1414 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1415 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1416 rctx->export_16bpc = true;
1417 } else {
1418 rctx->export_16bpc = false;
1419 }
1420 rctx->alpha_ref_dirty = true;
1421
1422
1423 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1424 offset >>= 8;
1425
1426 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1427 r600_pipe_state_add_reg(rstate,
1428 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1429 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1430 r600_pipe_state_add_reg(rstate,
1431 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1432 0x0, NULL, 0);
1433 r600_pipe_state_add_reg(rstate,
1434 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1435 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1436 r600_pipe_state_add_reg(rstate,
1437 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1438 S_028C64_PITCH_TILE_MAX(pitch),
1439 NULL, 0);
1440 r600_pipe_state_add_reg(rstate,
1441 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1442 S_028C68_SLICE_TILE_MAX(slice),
1443 NULL, 0);
1444 if (!rscreen->use_surface_alloc) {
1445 r600_pipe_state_add_reg(rstate,
1446 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1447 0x00000000, NULL, 0);
1448 } else {
1449 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1450 r600_pipe_state_add_reg(rstate,
1451 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1452 0x00000000, NULL, 0);
1453 } else {
1454 r600_pipe_state_add_reg(rstate,
1455 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1456 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1457 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
1458 NULL, 0);
1459 }
1460 }
1461 r600_pipe_state_add_reg(rstate,
1462 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1463 color_attrib,
1464 &rtex->resource, RADEON_USAGE_READWRITE);
1465 }
1466
1467 static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1468 const struct pipe_framebuffer_state *state)
1469 {
1470 struct r600_screen *rscreen = rctx->screen;
1471 struct r600_resource_texture *rtex;
1472 struct r600_surface *surf;
1473 uint64_t offset;
1474 unsigned level, first_layer, pitch, slice, format, array_mode;
1475 unsigned macro_aspect, tile_split, bankh, bankw, z_info, nbanks;
1476
1477 if (state->zsbuf == NULL)
1478 return;
1479
1480 surf = (struct r600_surface *)state->zsbuf;
1481 level = surf->base.u.tex.level;
1482 rtex = (struct r600_resource_texture*)surf->base.texture;
1483 first_layer = surf->base.u.tex.first_layer;
1484 format = r600_translate_dbformat(rtex->real_format);
1485
1486 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1487 /* XXX remove this once tiling is properly supported */
1488 if (!rscreen->use_surface_alloc) {
1489 /* XXX remove this once tiling is properly supported */
1490 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1491 V_028C70_ARRAY_1D_TILED_THIN1;
1492
1493 offset += r600_texture_get_offset(rtex, level, first_layer);
1494 pitch = (rtex->pitch_in_blocks[level] / 8) - 1;
1495 slice = ((rtex->pitch_in_blocks[level] * surf->aligned_height) / 64);
1496 if (slice) {
1497 slice = slice - 1;
1498 }
1499 tile_split = 0;
1500 macro_aspect = 0;
1501 bankw = 0;
1502 bankh = 0;
1503 } else {
1504 offset += rtex->surface.level[level].offset;
1505 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1506 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1507 if (slice) {
1508 slice = slice - 1;
1509 }
1510 switch (rtex->surface.level[level].mode) {
1511 case RADEON_SURF_MODE_2D:
1512 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1513 break;
1514 case RADEON_SURF_MODE_1D:
1515 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1516 case RADEON_SURF_MODE_LINEAR:
1517 default:
1518 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1519 break;
1520 }
1521 tile_split = rtex->surface.tile_split;
1522 macro_aspect = rtex->surface.mtilea;
1523 bankw = rtex->surface.bankw;
1524 bankh = rtex->surface.bankh;
1525 tile_split = eg_tile_split(tile_split);
1526 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1527 bankw = eg_bank_wh(bankw);
1528 bankh = eg_bank_wh(bankh);
1529 }
1530 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1531 offset >>= 8;
1532
1533 z_info = S_028040_ARRAY_MODE(array_mode) |
1534 S_028040_FORMAT(format) |
1535 S_028040_TILE_SPLIT(tile_split)|
1536 S_028040_NUM_BANKS(nbanks) |
1537 S_028040_BANK_WIDTH(bankw) |
1538 S_028040_BANK_HEIGHT(bankh) |
1539 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1540
1541 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1542 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1543 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1544 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1545 if (!rscreen->use_surface_alloc) {
1546 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1547 0x00000000, NULL, 0);
1548 } else {
1549 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1550 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1551 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer),
1552 NULL, 0);
1553 }
1554
1555 if (rtex->stencil) {
1556 uint64_t stencil_offset =
1557 r600_texture_get_offset(rtex->stencil, level, first_layer);
1558 unsigned stile_split;
1559
1560 stile_split = eg_tile_split(rtex->stencil->surface.tile_split);
1561 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1562 stencil_offset >>= 8;
1563
1564 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1565 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1566 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1567 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1568 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1569 1 | S_028044_TILE_SPLIT(stile_split),
1570 &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1571 } else {
1572 if (rscreen->use_surface_alloc && rtex->surface.flags & RADEON_SURF_SBUFFER) {
1573 uint64_t stencil_offset = rtex->surface.stencil_offset;
1574 unsigned stile_split = rtex->surface.stencil_tile_split;
1575
1576 stile_split = eg_tile_split(stile_split);
1577 stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1578 stencil_offset += rtex->surface.level[level].offset / 4;
1579 stencil_offset >>= 8;
1580
1581 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1582 stencil_offset, &rtex->resource,
1583 RADEON_USAGE_READWRITE);
1584 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1585 stencil_offset, &rtex->resource,
1586 RADEON_USAGE_READWRITE);
1587 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1588 1 | S_028044_TILE_SPLIT(stile_split),
1589 &rtex->resource,
1590 RADEON_USAGE_READWRITE);
1591 } else {
1592 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1593 offset, &rtex->resource,
1594 RADEON_USAGE_READWRITE);
1595 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1596 offset, &rtex->resource,
1597 RADEON_USAGE_READWRITE);
1598 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1599 0, NULL, RADEON_USAGE_READWRITE);
1600 }
1601 }
1602
1603 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, z_info,
1604 &rtex->resource, RADEON_USAGE_READWRITE);
1605 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1606 S_028058_PITCH_TILE_MAX(pitch),
1607 NULL, 0);
1608 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1609 S_02805C_SLICE_TILE_MAX(slice),
1610 NULL, 0);
1611 }
1612
1613 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1614 const struct pipe_framebuffer_state *state)
1615 {
1616 struct r600_context *rctx = (struct r600_context *)ctx;
1617 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1618 uint32_t shader_mask, tl, br;
1619 int tl_x, tl_y, br_x, br_y;
1620
1621 if (rstate == NULL)
1622 return;
1623
1624 r600_flush_framebuffer(rctx, false);
1625
1626 /* unreference old buffer and reference new one */
1627 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1628
1629 util_copy_framebuffer_state(&rctx->framebuffer, state);
1630
1631 /* build states */
1632 rctx->have_depth_fb = 0;
1633 rctx->nr_cbufs = state->nr_cbufs;
1634 for (int i = 0; i < state->nr_cbufs; i++) {
1635 evergreen_cb(rctx, rstate, state, i);
1636 }
1637 if (state->zsbuf) {
1638 evergreen_db(rctx, rstate, state);
1639 }
1640
1641 shader_mask = 0;
1642 for (int i = 0; i < state->nr_cbufs; i++) {
1643 shader_mask |= 0xf << (i * 4);
1644 }
1645 tl_x = 0;
1646 tl_y = 0;
1647 br_x = state->width;
1648 br_y = state->height;
1649 /* EG hw workaround */
1650 if (br_x == 0)
1651 tl_x = 1;
1652 if (br_y == 0)
1653 tl_y = 1;
1654 /* cayman hw workaround */
1655 if (rctx->chip_class == CAYMAN) {
1656 if (br_x == 1 && br_y == 1)
1657 br_x = 2;
1658 }
1659 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1660 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1661
1662 r600_pipe_state_add_reg(rstate,
1663 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1664 NULL, 0);
1665 r600_pipe_state_add_reg(rstate,
1666 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1667 NULL, 0);
1668 r600_pipe_state_add_reg(rstate,
1669 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1670 NULL, 0);
1671 r600_pipe_state_add_reg(rstate,
1672 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1673 NULL, 0);
1674 r600_pipe_state_add_reg(rstate,
1675 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1676 NULL, 0);
1677 r600_pipe_state_add_reg(rstate,
1678 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1679 NULL, 0);
1680 r600_pipe_state_add_reg(rstate,
1681 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1682 NULL, 0);
1683 r600_pipe_state_add_reg(rstate,
1684 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1685 NULL, 0);
1686 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1687 shader_mask, NULL, 0);
1688
1689 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1690 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1691 r600_context_pipe_state_set(rctx, rstate);
1692
1693 if (state->zsbuf) {
1694 evergreen_polygon_offset_update(rctx);
1695 }
1696 }
1697
1698 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1699 {
1700 struct radeon_winsys_cs *cs = rctx->cs;
1701 struct r600_atom_db_misc_state *a = (struct r600_atom_db_misc_state*)atom;
1702 unsigned db_count_control = 0;
1703 unsigned db_render_override =
1704 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1705 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1706 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1707
1708 if (a->occlusion_query_enabled) {
1709 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1710 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1711 }
1712
1713 r600_write_context_reg(cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1714 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1715 }
1716
1717 void evergreen_init_state_functions(struct r600_context *rctx)
1718 {
1719 r600_init_atom(&rctx->atom_db_misc_state.atom, evergreen_emit_db_misc_state, 6, 0);
1720
1721 rctx->context.create_blend_state = evergreen_create_blend_state;
1722 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1723 rctx->context.create_fs_state = r600_create_shader_state;
1724 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1725 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1726 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1727 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1728 rctx->context.create_vs_state = r600_create_shader_state;
1729 rctx->context.bind_blend_state = r600_bind_blend_state;
1730 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1731 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1732 rctx->context.bind_fs_state = r600_bind_ps_shader;
1733 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1734 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1735 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1736 rctx->context.bind_vs_state = r600_bind_vs_shader;
1737 rctx->context.delete_blend_state = r600_delete_state;
1738 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1739 rctx->context.delete_fs_state = r600_delete_ps_shader;
1740 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1741 rctx->context.delete_sampler_state = r600_delete_state;
1742 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1743 rctx->context.delete_vs_state = r600_delete_vs_shader;
1744 rctx->context.set_blend_color = r600_set_blend_color;
1745 rctx->context.set_clip_state = evergreen_set_clip_state;
1746 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1747 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1748 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1749 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1750 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1751 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1752 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1753 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1754 rctx->context.set_index_buffer = r600_set_index_buffer;
1755 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1756 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1757 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1758 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1759 rctx->context.texture_barrier = r600_texture_barrier;
1760 rctx->context.create_stream_output_target = r600_create_so_target;
1761 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1762 rctx->context.set_stream_output_targets = r600_set_so_targets;
1763 }
1764
1765 static void cayman_init_atom_start_cs(struct r600_context *rctx)
1766 {
1767 struct r600_command_buffer *cb = &rctx->atom_start_cs;
1768
1769 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1770
1771 /* This must be first. */
1772 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1773 r600_store_value(cb, 0x80000000);
1774 r600_store_value(cb, 0x80000000);
1775
1776 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
1777 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
1778 /* always set the temp clauses */
1779 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
1780
1781 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
1782 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
1783 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
1784
1785 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
1786
1787 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
1788
1789 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
1790 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
1791 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
1792 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
1793 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
1794 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
1795 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
1796 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
1797 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
1798 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
1799 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
1800 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
1801 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
1802 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
1803
1804 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
1805 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
1806 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
1807
1808 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
1809 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
1810 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
1811
1812 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
1813
1814 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
1815
1816 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1817 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
1818 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
1819
1820 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
1821 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
1822 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
1823
1824 r600_store_context_reg(cb, CM_R_028804_DB_EQAA, 0x110000);
1825
1826 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
1827 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
1828 r600_store_value(cb, 0);
1829 r600_store_value(cb, 0);
1830 r600_store_value(cb, 0);
1831 r600_store_value(cb, 0);
1832 r600_store_value(cb, 0);
1833 r600_store_value(cb, 0);
1834 r600_store_value(cb, 0);
1835 r600_store_value(cb, 0);
1836 r600_store_value(cb, 0);
1837 r600_store_value(cb, 0);
1838 r600_store_value(cb, 0);
1839 r600_store_value(cb, 0);
1840 r600_store_value(cb, 0);
1841 r600_store_value(cb, 0);
1842 r600_store_value(cb, 0);
1843 r600_store_value(cb, 0);
1844 r600_store_value(cb, 0);
1845 r600_store_value(cb, 0);
1846 r600_store_value(cb, 0);
1847 r600_store_value(cb, 0);
1848 r600_store_value(cb, 0);
1849 r600_store_value(cb, 0);
1850 r600_store_value(cb, 0);
1851 r600_store_value(cb, 0);
1852 r600_store_value(cb, 0);
1853 r600_store_value(cb, 0);
1854 r600_store_value(cb, 0);
1855 r600_store_value(cb, 0);
1856 r600_store_value(cb, 0);
1857 r600_store_value(cb, 0);
1858 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
1859 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
1860 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
1861
1862 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
1863
1864 r600_store_context_reg_seq(cb, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
1865 r600_store_value(cb, ~0); /* CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 */
1866 r600_store_value(cb, ~0); /* CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 */
1867
1868 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
1869 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
1870 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
1871
1872 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
1873
1874 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
1875 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
1876 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
1877 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
1878
1879 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
1880
1881 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
1882 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
1883 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
1884
1885 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1886 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
1887 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
1888 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
1889
1890 r600_store_context_reg_seq(cb, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
1891 r600_store_value(cb, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1892 r600_store_value(cb, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1893
1894 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
1895 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
1896 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
1897 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
1898 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
1899
1900 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
1901 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
1902 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
1903
1904 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
1905 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
1906 }
1907
1908 void evergreen_init_atom_start_cs(struct r600_context *rctx)
1909 {
1910 struct r600_command_buffer *cb = &rctx->atom_start_cs;
1911 int ps_prio;
1912 int vs_prio;
1913 int gs_prio;
1914 int es_prio;
1915 int hs_prio, cs_prio, ls_prio;
1916 int num_ps_gprs;
1917 int num_vs_gprs;
1918 int num_gs_gprs;
1919 int num_es_gprs;
1920 int num_hs_gprs;
1921 int num_ls_gprs;
1922 int num_temp_gprs;
1923 int num_ps_threads;
1924 int num_vs_threads;
1925 int num_gs_threads;
1926 int num_es_threads;
1927 int num_hs_threads;
1928 int num_ls_threads;
1929 int num_ps_stack_entries;
1930 int num_vs_stack_entries;
1931 int num_gs_stack_entries;
1932 int num_es_stack_entries;
1933 int num_hs_stack_entries;
1934 int num_ls_stack_entries;
1935 enum radeon_family family;
1936 unsigned tmp;
1937
1938 if (rctx->chip_class == CAYMAN) {
1939 cayman_init_atom_start_cs(rctx);
1940 return;
1941 }
1942
1943 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1944
1945 /* This must be first. */
1946 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1947 r600_store_value(cb, 0x80000000);
1948 r600_store_value(cb, 0x80000000);
1949
1950 family = rctx->family;
1951 ps_prio = 0;
1952 vs_prio = 1;
1953 gs_prio = 2;
1954 es_prio = 3;
1955 hs_prio = 0;
1956 ls_prio = 0;
1957 cs_prio = 0;
1958
1959 switch (family) {
1960 case CHIP_CEDAR:
1961 default:
1962 num_ps_gprs = 93;
1963 num_vs_gprs = 46;
1964 num_temp_gprs = 4;
1965 num_gs_gprs = 31;
1966 num_es_gprs = 31;
1967 num_hs_gprs = 23;
1968 num_ls_gprs = 23;
1969 num_ps_threads = 96;
1970 num_vs_threads = 16;
1971 num_gs_threads = 16;
1972 num_es_threads = 16;
1973 num_hs_threads = 16;
1974 num_ls_threads = 16;
1975 num_ps_stack_entries = 42;
1976 num_vs_stack_entries = 42;
1977 num_gs_stack_entries = 42;
1978 num_es_stack_entries = 42;
1979 num_hs_stack_entries = 42;
1980 num_ls_stack_entries = 42;
1981 break;
1982 case CHIP_REDWOOD:
1983 num_ps_gprs = 93;
1984 num_vs_gprs = 46;
1985 num_temp_gprs = 4;
1986 num_gs_gprs = 31;
1987 num_es_gprs = 31;
1988 num_hs_gprs = 23;
1989 num_ls_gprs = 23;
1990 num_ps_threads = 128;
1991 num_vs_threads = 20;
1992 num_gs_threads = 20;
1993 num_es_threads = 20;
1994 num_hs_threads = 20;
1995 num_ls_threads = 20;
1996 num_ps_stack_entries = 42;
1997 num_vs_stack_entries = 42;
1998 num_gs_stack_entries = 42;
1999 num_es_stack_entries = 42;
2000 num_hs_stack_entries = 42;
2001 num_ls_stack_entries = 42;
2002 break;
2003 case CHIP_JUNIPER:
2004 num_ps_gprs = 93;
2005 num_vs_gprs = 46;
2006 num_temp_gprs = 4;
2007 num_gs_gprs = 31;
2008 num_es_gprs = 31;
2009 num_hs_gprs = 23;
2010 num_ls_gprs = 23;
2011 num_ps_threads = 128;
2012 num_vs_threads = 20;
2013 num_gs_threads = 20;
2014 num_es_threads = 20;
2015 num_hs_threads = 20;
2016 num_ls_threads = 20;
2017 num_ps_stack_entries = 85;
2018 num_vs_stack_entries = 85;
2019 num_gs_stack_entries = 85;
2020 num_es_stack_entries = 85;
2021 num_hs_stack_entries = 85;
2022 num_ls_stack_entries = 85;
2023 break;
2024 case CHIP_CYPRESS:
2025 case CHIP_HEMLOCK:
2026 num_ps_gprs = 93;
2027 num_vs_gprs = 46;
2028 num_temp_gprs = 4;
2029 num_gs_gprs = 31;
2030 num_es_gprs = 31;
2031 num_hs_gprs = 23;
2032 num_ls_gprs = 23;
2033 num_ps_threads = 128;
2034 num_vs_threads = 20;
2035 num_gs_threads = 20;
2036 num_es_threads = 20;
2037 num_hs_threads = 20;
2038 num_ls_threads = 20;
2039 num_ps_stack_entries = 85;
2040 num_vs_stack_entries = 85;
2041 num_gs_stack_entries = 85;
2042 num_es_stack_entries = 85;
2043 num_hs_stack_entries = 85;
2044 num_ls_stack_entries = 85;
2045 break;
2046 case CHIP_PALM:
2047 num_ps_gprs = 93;
2048 num_vs_gprs = 46;
2049 num_temp_gprs = 4;
2050 num_gs_gprs = 31;
2051 num_es_gprs = 31;
2052 num_hs_gprs = 23;
2053 num_ls_gprs = 23;
2054 num_ps_threads = 96;
2055 num_vs_threads = 16;
2056 num_gs_threads = 16;
2057 num_es_threads = 16;
2058 num_hs_threads = 16;
2059 num_ls_threads = 16;
2060 num_ps_stack_entries = 42;
2061 num_vs_stack_entries = 42;
2062 num_gs_stack_entries = 42;
2063 num_es_stack_entries = 42;
2064 num_hs_stack_entries = 42;
2065 num_ls_stack_entries = 42;
2066 break;
2067 case CHIP_SUMO:
2068 num_ps_gprs = 93;
2069 num_vs_gprs = 46;
2070 num_temp_gprs = 4;
2071 num_gs_gprs = 31;
2072 num_es_gprs = 31;
2073 num_hs_gprs = 23;
2074 num_ls_gprs = 23;
2075 num_ps_threads = 96;
2076 num_vs_threads = 25;
2077 num_gs_threads = 25;
2078 num_es_threads = 25;
2079 num_hs_threads = 25;
2080 num_ls_threads = 25;
2081 num_ps_stack_entries = 42;
2082 num_vs_stack_entries = 42;
2083 num_gs_stack_entries = 42;
2084 num_es_stack_entries = 42;
2085 num_hs_stack_entries = 42;
2086 num_ls_stack_entries = 42;
2087 break;
2088 case CHIP_SUMO2:
2089 num_ps_gprs = 93;
2090 num_vs_gprs = 46;
2091 num_temp_gprs = 4;
2092 num_gs_gprs = 31;
2093 num_es_gprs = 31;
2094 num_hs_gprs = 23;
2095 num_ls_gprs = 23;
2096 num_ps_threads = 96;
2097 num_vs_threads = 25;
2098 num_gs_threads = 25;
2099 num_es_threads = 25;
2100 num_hs_threads = 25;
2101 num_ls_threads = 25;
2102 num_ps_stack_entries = 85;
2103 num_vs_stack_entries = 85;
2104 num_gs_stack_entries = 85;
2105 num_es_stack_entries = 85;
2106 num_hs_stack_entries = 85;
2107 num_ls_stack_entries = 85;
2108 break;
2109 case CHIP_BARTS:
2110 num_ps_gprs = 93;
2111 num_vs_gprs = 46;
2112 num_temp_gprs = 4;
2113 num_gs_gprs = 31;
2114 num_es_gprs = 31;
2115 num_hs_gprs = 23;
2116 num_ls_gprs = 23;
2117 num_ps_threads = 128;
2118 num_vs_threads = 20;
2119 num_gs_threads = 20;
2120 num_es_threads = 20;
2121 num_hs_threads = 20;
2122 num_ls_threads = 20;
2123 num_ps_stack_entries = 85;
2124 num_vs_stack_entries = 85;
2125 num_gs_stack_entries = 85;
2126 num_es_stack_entries = 85;
2127 num_hs_stack_entries = 85;
2128 num_ls_stack_entries = 85;
2129 break;
2130 case CHIP_TURKS:
2131 num_ps_gprs = 93;
2132 num_vs_gprs = 46;
2133 num_temp_gprs = 4;
2134 num_gs_gprs = 31;
2135 num_es_gprs = 31;
2136 num_hs_gprs = 23;
2137 num_ls_gprs = 23;
2138 num_ps_threads = 128;
2139 num_vs_threads = 20;
2140 num_gs_threads = 20;
2141 num_es_threads = 20;
2142 num_hs_threads = 20;
2143 num_ls_threads = 20;
2144 num_ps_stack_entries = 42;
2145 num_vs_stack_entries = 42;
2146 num_gs_stack_entries = 42;
2147 num_es_stack_entries = 42;
2148 num_hs_stack_entries = 42;
2149 num_ls_stack_entries = 42;
2150 break;
2151 case CHIP_CAICOS:
2152 num_ps_gprs = 93;
2153 num_vs_gprs = 46;
2154 num_temp_gprs = 4;
2155 num_gs_gprs = 31;
2156 num_es_gprs = 31;
2157 num_hs_gprs = 23;
2158 num_ls_gprs = 23;
2159 num_ps_threads = 128;
2160 num_vs_threads = 10;
2161 num_gs_threads = 10;
2162 num_es_threads = 10;
2163 num_hs_threads = 10;
2164 num_ls_threads = 10;
2165 num_ps_stack_entries = 42;
2166 num_vs_stack_entries = 42;
2167 num_gs_stack_entries = 42;
2168 num_es_stack_entries = 42;
2169 num_hs_stack_entries = 42;
2170 num_ls_stack_entries = 42;
2171 break;
2172 }
2173
2174 tmp = 0;
2175 switch (family) {
2176 case CHIP_CEDAR:
2177 case CHIP_PALM:
2178 case CHIP_SUMO:
2179 case CHIP_SUMO2:
2180 case CHIP_CAICOS:
2181 break;
2182 default:
2183 tmp |= S_008C00_VC_ENABLE(1);
2184 break;
2185 }
2186 tmp |= S_008C00_EXPORT_SRC_C(1);
2187 tmp |= S_008C00_CS_PRIO(cs_prio);
2188 tmp |= S_008C00_LS_PRIO(ls_prio);
2189 tmp |= S_008C00_HS_PRIO(hs_prio);
2190 tmp |= S_008C00_PS_PRIO(ps_prio);
2191 tmp |= S_008C00_VS_PRIO(vs_prio);
2192 tmp |= S_008C00_GS_PRIO(gs_prio);
2193 tmp |= S_008C00_ES_PRIO(es_prio);
2194
2195 /* enable dynamic GPR resource management */
2196 if (rctx->screen->info.drm_minor >= 7) {
2197 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2198 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2199 /* always set temp clauses */
2200 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2201 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2202 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2203 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2204 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2205 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2206 S_028838_PS_GPRS(0x1e) |
2207 S_028838_VS_GPRS(0x1e) |
2208 S_028838_GS_GPRS(0x1e) |
2209 S_028838_ES_GPRS(0x1e) |
2210 S_028838_HS_GPRS(0x1e) |
2211 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2212 } else {
2213 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2214 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2215
2216 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2217 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2218 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2219 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2220
2221 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2222 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2223 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2224
2225 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2226 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2227 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2228 }
2229
2230 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2231 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2232 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2233 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2234 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2235 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2236
2237 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2238 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2239 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2240
2241 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2242 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2243 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2244
2245 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2246 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2247 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2248
2249 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2250 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2251 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2252
2253 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2254 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2255
2256 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2257 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2258
2259 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2260
2261 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2262 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2263 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2264 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2265 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2266 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2267 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2268
2269 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2270 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2271 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2272 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2273 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2274
2275 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2276 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2277 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2278 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2279 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2280 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2281 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2282 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2283 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2284 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2285 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2286 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2287 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2288 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2289
2290 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2291 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2292 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2293
2294 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2295 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2296 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2297
2298 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2299
2300 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2301 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2302 r600_store_value(cb, 0);
2303 r600_store_value(cb, 0);
2304 r600_store_value(cb, 0);
2305 r600_store_value(cb, 0);
2306 r600_store_value(cb, 0);
2307 r600_store_value(cb, 0);
2308 r600_store_value(cb, 0);
2309 r600_store_value(cb, 0);
2310 r600_store_value(cb, 0);
2311 r600_store_value(cb, 0);
2312 r600_store_value(cb, 0);
2313 r600_store_value(cb, 0);
2314 r600_store_value(cb, 0);
2315 r600_store_value(cb, 0);
2316 r600_store_value(cb, 0);
2317 r600_store_value(cb, 0);
2318 r600_store_value(cb, 0);
2319 r600_store_value(cb, 0);
2320 r600_store_value(cb, 0);
2321 r600_store_value(cb, 0);
2322 r600_store_value(cb, 0);
2323 r600_store_value(cb, 0);
2324 r600_store_value(cb, 0);
2325 r600_store_value(cb, 0);
2326 r600_store_value(cb, 0);
2327 r600_store_value(cb, 0);
2328 r600_store_value(cb, 0);
2329 r600_store_value(cb, 0);
2330 r600_store_value(cb, 0);
2331 r600_store_value(cb, 0);
2332 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2333 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2334 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2335
2336 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2337
2338 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2339 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2340 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2341
2342 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2343 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2344
2345 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2346 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2347 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2348
2349 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2350 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2351 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2352
2353 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2354 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2355 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2356 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2357
2358 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2359
2360 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2361 r600_store_value(cb, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
2362 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2363
2364 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 5);
2365 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2366 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2367 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2368 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2369 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
2370
2371 r600_store_context_reg(cb, R_028C3C_PA_SC_AA_MASK, ~0);
2372
2373 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
2374 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
2375 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2376
2377 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2378 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2379 }
2380
2381 void evergreen_polygon_offset_update(struct r600_context *rctx)
2382 {
2383 struct r600_pipe_state state;
2384
2385 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2386 state.nregs = 0;
2387 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2388 float offset_units = rctx->rasterizer->offset_units;
2389 unsigned offset_db_fmt_cntl = 0, depth;
2390
2391 switch (rctx->framebuffer.zsbuf->texture->format) {
2392 case PIPE_FORMAT_Z24X8_UNORM:
2393 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2394 depth = -24;
2395 offset_units *= 2.0f;
2396 break;
2397 case PIPE_FORMAT_Z32_FLOAT:
2398 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2399 depth = -23;
2400 offset_units *= 1.0f;
2401 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2402 break;
2403 case PIPE_FORMAT_Z16_UNORM:
2404 depth = -16;
2405 offset_units *= 4.0f;
2406 break;
2407 default:
2408 return;
2409 }
2410 /* XXX some of those reg can be computed with cso */
2411 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2412 r600_pipe_state_add_reg(&state,
2413 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2414 fui(rctx->rasterizer->offset_scale), NULL, 0);
2415 r600_pipe_state_add_reg(&state,
2416 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2417 fui(offset_units), NULL, 0);
2418 r600_pipe_state_add_reg(&state,
2419 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2420 fui(rctx->rasterizer->offset_scale), NULL, 0);
2421 r600_pipe_state_add_reg(&state,
2422 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2423 fui(offset_units), NULL, 0);
2424 r600_pipe_state_add_reg(&state,
2425 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2426 offset_db_fmt_cntl, NULL, 0);
2427 r600_context_pipe_state_set(rctx, &state);
2428 }
2429 }
2430
2431 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2432 {
2433 struct r600_context *rctx = (struct r600_context *)ctx;
2434 struct r600_pipe_state *rstate = &shader->rstate;
2435 struct r600_shader *rshader = &shader->shader;
2436 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2437 int pos_index = -1, face_index = -1;
2438 int ninterp = 0;
2439 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2440 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2441
2442 rstate->nregs = 0;
2443
2444 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2445 for (i = 0; i < rshader->ninput; i++) {
2446 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2447 POSITION goes via GPRs from the SC so isn't counted */
2448 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2449 pos_index = i;
2450 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2451 face_index = i;
2452 else {
2453 ninterp++;
2454 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2455 have_linear = TRUE;
2456 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2457 have_perspective = TRUE;
2458 if (rshader->input[i].centroid)
2459 have_centroid = TRUE;
2460 }
2461
2462 sid = rshader->input[i].spi_sid;
2463
2464 if (sid) {
2465
2466 tmp = S_028644_SEMANTIC(sid);
2467
2468 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2469 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2470 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2471 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2472 tmp |= S_028644_FLAT_SHADE(1);
2473 }
2474
2475 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2476 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2477 tmp |= S_028644_PT_SPRITE_TEX(1);
2478 }
2479
2480 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2481 tmp, NULL, 0);
2482
2483 idx++;
2484 }
2485 }
2486
2487 for (i = 0; i < rshader->noutput; i++) {
2488 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2489 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2490 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2491 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2492 }
2493 if (rshader->uses_kill)
2494 db_shader_control |= S_02880C_KILL_ENABLE(1);
2495
2496 exports_ps = 0;
2497 num_cout = 0;
2498 for (i = 0; i < rshader->noutput; i++) {
2499 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2500 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2501 exports_ps |= 1;
2502 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2503 if (rshader->fs_write_all)
2504 num_cout = rshader->nr_cbufs;
2505 else
2506 num_cout++;
2507 }
2508 }
2509 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2510 if (!exports_ps) {
2511 /* always at least export 1 component per pixel */
2512 exports_ps = 2;
2513 }
2514
2515 if (ninterp == 0) {
2516 ninterp = 1;
2517 have_perspective = TRUE;
2518 }
2519
2520 if (!have_perspective && !have_linear)
2521 have_perspective = TRUE;
2522
2523 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2524 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2525 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2526 spi_input_z = 0;
2527 if (pos_index != -1) {
2528 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2529 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2530 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2531 spi_input_z |= 1;
2532 }
2533
2534 spi_ps_in_control_1 = 0;
2535 if (face_index != -1) {
2536 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2537 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2538 }
2539
2540 spi_baryc_cntl = 0;
2541 if (have_perspective)
2542 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2543 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2544 if (have_linear)
2545 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2546 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2547
2548 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2549 spi_ps_in_control_0, NULL, 0);
2550 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2551 spi_ps_in_control_1, NULL, 0);
2552 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2553 0, NULL, 0);
2554 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0);
2555 r600_pipe_state_add_reg(rstate,
2556 R_0286E0_SPI_BARYC_CNTL,
2557 spi_baryc_cntl,
2558 NULL, 0);
2559
2560 r600_pipe_state_add_reg(rstate,
2561 R_028840_SQ_PGM_START_PS,
2562 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2563 shader->bo, RADEON_USAGE_READ);
2564 r600_pipe_state_add_reg(rstate,
2565 R_028844_SQ_PGM_RESOURCES_PS,
2566 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2567 S_028844_PRIME_CACHE_ON_DRAW(1) |
2568 S_028844_STACK_SIZE(rshader->bc.nstack),
2569 NULL, 0);
2570 r600_pipe_state_add_reg(rstate,
2571 R_02884C_SQ_PGM_EXPORTS_PS,
2572 exports_ps, NULL, 0);
2573 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2574 db_shader_control,
2575 NULL, 0);
2576
2577 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2578 if (rctx->rasterizer)
2579 shader->flatshade = rctx->rasterizer->flatshade;
2580 }
2581
2582 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2583 {
2584 struct r600_context *rctx = (struct r600_context *)ctx;
2585 struct r600_pipe_state *rstate = &shader->rstate;
2586 struct r600_shader *rshader = &shader->shader;
2587 unsigned spi_vs_out_id[10] = {};
2588 unsigned i, tmp, nparams = 0;
2589
2590 /* clear previous register */
2591 rstate->nregs = 0;
2592
2593 for (i = 0; i < rshader->noutput; i++) {
2594 if (rshader->output[i].spi_sid) {
2595 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2596 spi_vs_out_id[nparams / 4] |= tmp;
2597 nparams++;
2598 }
2599 }
2600
2601 for (i = 0; i < 10; i++) {
2602 r600_pipe_state_add_reg(rstate,
2603 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2604 spi_vs_out_id[i], NULL, 0);
2605 }
2606
2607 /* Certain attributes (position, psize, etc.) don't count as params.
2608 * VS is required to export at least one param and r600_shader_from_tgsi()
2609 * takes care of adding a dummy export.
2610 */
2611 if (nparams < 1)
2612 nparams = 1;
2613
2614 r600_pipe_state_add_reg(rstate,
2615 R_0286C4_SPI_VS_OUT_CONFIG,
2616 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2617 NULL, 0);
2618 r600_pipe_state_add_reg(rstate,
2619 R_028860_SQ_PGM_RESOURCES_VS,
2620 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2621 S_028860_STACK_SIZE(rshader->bc.nstack),
2622 NULL, 0);
2623 r600_pipe_state_add_reg(rstate,
2624 R_02885C_SQ_PGM_START_VS,
2625 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2626 shader->bo, RADEON_USAGE_READ);
2627
2628 shader->pa_cl_vs_out_cntl =
2629 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2630 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2631 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2632 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2633 }
2634
2635 void evergreen_fetch_shader(struct pipe_context *ctx,
2636 struct r600_vertex_element *ve)
2637 {
2638 struct r600_context *rctx = (struct r600_context *)ctx;
2639 struct r600_pipe_state *rstate = &ve->rstate;
2640 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2641 rstate->nregs = 0;
2642 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2643 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2644 ve->fetch_shader, RADEON_USAGE_READ);
2645 }
2646
2647 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2648 {
2649 struct pipe_depth_stencil_alpha_state dsa;
2650 struct r600_pipe_state *rstate;
2651
2652 memset(&dsa, 0, sizeof(dsa));
2653
2654 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2655 r600_pipe_state_add_reg(rstate,
2656 R_028000_DB_RENDER_CONTROL,
2657 S_028000_DEPTH_COPY_ENABLE(1) |
2658 S_028000_STENCIL_COPY_ENABLE(1) |
2659 S_028000_COPY_CENTROID(1),
2660 NULL, 0);
2661 /* Don't set the 'is_flush' flag in r600_pipe_dsa, evergreen doesn't need it. */
2662 return rstate;
2663 }
2664
2665 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
2666 struct r600_pipe_resource_state *rstate)
2667 {
2668 rstate->id = R600_PIPE_STATE_RESOURCE;
2669
2670 rstate->val[0] = 0;
2671 rstate->bo[0] = NULL;
2672 rstate->val[1] = 0;
2673 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2674 rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2675 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2676 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2677 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2678 rstate->val[4] = 0;
2679 rstate->val[5] = 0;
2680 rstate->val[6] = 0;
2681 rstate->val[7] = 0xc0000000;
2682 }
2683
2684
2685 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
2686 struct r600_pipe_resource_state *rstate,
2687 struct r600_resource *rbuffer,
2688 unsigned offset, unsigned stride,
2689 enum radeon_bo_usage usage)
2690 {
2691 uint64_t va;
2692
2693 va = r600_resource_va(ctx->screen, (void *)rbuffer);
2694 rstate->bo[0] = rbuffer;
2695 rstate->bo_usage[0] = usage;
2696 rstate->val[0] = (offset + va) & 0xFFFFFFFFUL;
2697 rstate->val[1] = rbuffer->buf->size - offset - 1;
2698 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2699 S_030008_STRIDE(stride) |
2700 (((va + offset) >> 32UL) & 0xFF);
2701 }