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[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <stdio.h>
25 #include <errno.h>
26 #include "pipe/p_defines.h"
27 #include "pipe/p_state.h"
28 #include "pipe/p_context.h"
29 #include "tgsi/tgsi_scan.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "tgsi/tgsi_util.h"
32 #include "util/u_blitter.h"
33 #include "util/u_double_list.h"
34 #include "util/u_transfer.h"
35 #include "util/u_surface.h"
36 #include "util/u_pack_color.h"
37 #include "util/u_memory.h"
38 #include "util/u_inlines.h"
39 #include "util/u_framebuffer.h"
40 #include "pipebuffer/pb_buffer.h"
41 #include "r600.h"
42 #include "evergreend.h"
43 #include "r600_resource.h"
44 #include "r600_shader.h"
45 #include "r600_pipe.h"
46 #include "r600_formats.h"
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(unsigned dim)
174 {
175 switch (dim) {
176 default:
177 case PIPE_TEXTURE_1D:
178 return V_030000_SQ_TEX_DIM_1D;
179 case PIPE_TEXTURE_1D_ARRAY:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY;
181 case PIPE_TEXTURE_2D:
182 case PIPE_TEXTURE_RECT:
183 return V_030000_SQ_TEX_DIM_2D;
184 case PIPE_TEXTURE_2D_ARRAY:
185 return V_030000_SQ_TEX_DIM_2D_ARRAY;
186 case PIPE_TEXTURE_3D:
187 return V_030000_SQ_TEX_DIM_3D;
188 case PIPE_TEXTURE_CUBE:
189 return V_030000_SQ_TEX_DIM_CUBEMAP;
190 }
191 }
192
193 static uint32_t r600_translate_dbformat(enum pipe_format format)
194 {
195 switch (format) {
196 case PIPE_FORMAT_Z16_UNORM:
197 return V_028040_Z_16;
198 case PIPE_FORMAT_Z24X8_UNORM:
199 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
200 return V_028040_Z_24;
201 case PIPE_FORMAT_Z32_FLOAT:
202 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
203 return V_028040_Z_32_FLOAT;
204 default:
205 return ~0U;
206 }
207 }
208
209 static uint32_t r600_translate_colorswap(enum pipe_format format)
210 {
211 switch (format) {
212 /* 8-bit buffers. */
213 case PIPE_FORMAT_L4A4_UNORM:
214 case PIPE_FORMAT_A4R4_UNORM:
215 return V_028C70_SWAP_ALT;
216
217 case PIPE_FORMAT_A8_UNORM:
218 case PIPE_FORMAT_A8_UINT:
219 case PIPE_FORMAT_A8_SINT:
220 case PIPE_FORMAT_R4A4_UNORM:
221 return V_028C70_SWAP_ALT_REV;
222 case PIPE_FORMAT_I8_UNORM:
223 case PIPE_FORMAT_L8_UNORM:
224 case PIPE_FORMAT_I8_UINT:
225 case PIPE_FORMAT_I8_SINT:
226 case PIPE_FORMAT_L8_UINT:
227 case PIPE_FORMAT_L8_SINT:
228 case PIPE_FORMAT_L8_SRGB:
229 case PIPE_FORMAT_R8_UNORM:
230 case PIPE_FORMAT_R8_SNORM:
231 case PIPE_FORMAT_R8_UINT:
232 case PIPE_FORMAT_R8_SINT:
233 return V_028C70_SWAP_STD;
234
235 /* 16-bit buffers. */
236 case PIPE_FORMAT_B5G6R5_UNORM:
237 return V_028C70_SWAP_STD_REV;
238
239 case PIPE_FORMAT_B5G5R5A1_UNORM:
240 case PIPE_FORMAT_B5G5R5X1_UNORM:
241 return V_028C70_SWAP_ALT;
242
243 case PIPE_FORMAT_B4G4R4A4_UNORM:
244 case PIPE_FORMAT_B4G4R4X4_UNORM:
245 return V_028C70_SWAP_ALT;
246
247 case PIPE_FORMAT_Z16_UNORM:
248 return V_028C70_SWAP_STD;
249
250 case PIPE_FORMAT_L8A8_UNORM:
251 case PIPE_FORMAT_L8A8_UINT:
252 case PIPE_FORMAT_L8A8_SINT:
253 case PIPE_FORMAT_L8A8_SRGB:
254 return V_028C70_SWAP_ALT;
255 case PIPE_FORMAT_R8G8_UNORM:
256 case PIPE_FORMAT_R8G8_UINT:
257 case PIPE_FORMAT_R8G8_SINT:
258 return V_028C70_SWAP_STD;
259
260 case PIPE_FORMAT_R16_UNORM:
261 case PIPE_FORMAT_R16_UINT:
262 case PIPE_FORMAT_R16_SINT:
263 case PIPE_FORMAT_R16_FLOAT:
264 return V_028C70_SWAP_STD;
265
266 /* 32-bit buffers. */
267 case PIPE_FORMAT_A8B8G8R8_SRGB:
268 return V_028C70_SWAP_STD_REV;
269 case PIPE_FORMAT_B8G8R8A8_SRGB:
270 return V_028C70_SWAP_ALT;
271
272 case PIPE_FORMAT_B8G8R8A8_UNORM:
273 case PIPE_FORMAT_B8G8R8X8_UNORM:
274 return V_028C70_SWAP_ALT;
275
276 case PIPE_FORMAT_A8R8G8B8_UNORM:
277 case PIPE_FORMAT_X8R8G8B8_UNORM:
278 return V_028C70_SWAP_ALT_REV;
279 case PIPE_FORMAT_R8G8B8A8_SNORM:
280 case PIPE_FORMAT_R8G8B8A8_UNORM:
281 case PIPE_FORMAT_R8G8B8A8_SSCALED:
282 case PIPE_FORMAT_R8G8B8A8_USCALED:
283 case PIPE_FORMAT_R8G8B8A8_SINT:
284 case PIPE_FORMAT_R8G8B8A8_UINT:
285 case PIPE_FORMAT_R8G8B8X8_UNORM:
286 return V_028C70_SWAP_STD;
287
288 case PIPE_FORMAT_A8B8G8R8_UNORM:
289 case PIPE_FORMAT_X8B8G8R8_UNORM:
290 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
291 return V_028C70_SWAP_STD_REV;
292
293 case PIPE_FORMAT_Z24X8_UNORM:
294 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
295 return V_028C70_SWAP_STD;
296
297 case PIPE_FORMAT_X8Z24_UNORM:
298 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
299 return V_028C70_SWAP_STD;
300
301 case PIPE_FORMAT_R10G10B10A2_UNORM:
302 case PIPE_FORMAT_R10G10B10X2_SNORM:
303 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
304 return V_028C70_SWAP_STD;
305
306 case PIPE_FORMAT_B10G10R10A2_UNORM:
307 case PIPE_FORMAT_B10G10R10A2_UINT:
308 return V_028C70_SWAP_ALT;
309
310 case PIPE_FORMAT_R11G11B10_FLOAT:
311 case PIPE_FORMAT_R32_FLOAT:
312 case PIPE_FORMAT_R32_UINT:
313 case PIPE_FORMAT_R32_SINT:
314 case PIPE_FORMAT_Z32_FLOAT:
315 case PIPE_FORMAT_R16G16_FLOAT:
316 case PIPE_FORMAT_R16G16_UNORM:
317 case PIPE_FORMAT_R16G16_UINT:
318 case PIPE_FORMAT_R16G16_SINT:
319 return V_028C70_SWAP_STD;
320
321 /* 64-bit buffers. */
322 case PIPE_FORMAT_R32G32_FLOAT:
323 case PIPE_FORMAT_R32G32_UINT:
324 case PIPE_FORMAT_R32G32_SINT:
325 case PIPE_FORMAT_R16G16B16A16_UNORM:
326 case PIPE_FORMAT_R16G16B16A16_SNORM:
327 case PIPE_FORMAT_R16G16B16A16_USCALED:
328 case PIPE_FORMAT_R16G16B16A16_SSCALED:
329 case PIPE_FORMAT_R16G16B16A16_UINT:
330 case PIPE_FORMAT_R16G16B16A16_SINT:
331 case PIPE_FORMAT_R16G16B16A16_FLOAT:
332 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
333
334 /* 128-bit buffers. */
335 case PIPE_FORMAT_R32G32B32A32_FLOAT:
336 case PIPE_FORMAT_R32G32B32A32_SNORM:
337 case PIPE_FORMAT_R32G32B32A32_UNORM:
338 case PIPE_FORMAT_R32G32B32A32_SSCALED:
339 case PIPE_FORMAT_R32G32B32A32_USCALED:
340 case PIPE_FORMAT_R32G32B32A32_SINT:
341 case PIPE_FORMAT_R32G32B32A32_UINT:
342 return V_028C70_SWAP_STD;
343 default:
344 R600_ERR("unsupported colorswap format %d\n", format);
345 return ~0U;
346 }
347 return ~0U;
348 }
349
350 static uint32_t r600_translate_colorformat(enum pipe_format format)
351 {
352 switch (format) {
353 /* 8-bit buffers. */
354 case PIPE_FORMAT_A8_UNORM:
355 case PIPE_FORMAT_A8_UINT:
356 case PIPE_FORMAT_A8_SINT:
357 case PIPE_FORMAT_I8_UNORM:
358 case PIPE_FORMAT_I8_UINT:
359 case PIPE_FORMAT_I8_SINT:
360 case PIPE_FORMAT_L8_UNORM:
361 case PIPE_FORMAT_L8_UINT:
362 case PIPE_FORMAT_L8_SINT:
363 case PIPE_FORMAT_L8_SRGB:
364 case PIPE_FORMAT_R8_UNORM:
365 case PIPE_FORMAT_R8_SNORM:
366 case PIPE_FORMAT_R8_UINT:
367 case PIPE_FORMAT_R8_SINT:
368 return V_028C70_COLOR_8;
369
370 /* 16-bit buffers. */
371 case PIPE_FORMAT_B5G6R5_UNORM:
372 return V_028C70_COLOR_5_6_5;
373
374 case PIPE_FORMAT_B5G5R5A1_UNORM:
375 case PIPE_FORMAT_B5G5R5X1_UNORM:
376 return V_028C70_COLOR_1_5_5_5;
377
378 case PIPE_FORMAT_B4G4R4A4_UNORM:
379 case PIPE_FORMAT_B4G4R4X4_UNORM:
380 return V_028C70_COLOR_4_4_4_4;
381
382 case PIPE_FORMAT_Z16_UNORM:
383 return V_028C70_COLOR_16;
384
385 case PIPE_FORMAT_L8A8_UNORM:
386 case PIPE_FORMAT_L8A8_UINT:
387 case PIPE_FORMAT_L8A8_SINT:
388 case PIPE_FORMAT_L8A8_SRGB:
389 case PIPE_FORMAT_R8G8_UNORM:
390 case PIPE_FORMAT_R8G8_UINT:
391 case PIPE_FORMAT_R8G8_SINT:
392 return V_028C70_COLOR_8_8;
393
394 case PIPE_FORMAT_R16_UNORM:
395 case PIPE_FORMAT_R16_UINT:
396 case PIPE_FORMAT_R16_SINT:
397 return V_028C70_COLOR_16;
398
399 case PIPE_FORMAT_R16_FLOAT:
400 return V_028C70_COLOR_16_FLOAT;
401
402 /* 32-bit buffers. */
403 case PIPE_FORMAT_A8B8G8R8_SRGB:
404 case PIPE_FORMAT_A8B8G8R8_UNORM:
405 case PIPE_FORMAT_A8R8G8B8_UNORM:
406 case PIPE_FORMAT_B8G8R8A8_SRGB:
407 case PIPE_FORMAT_B8G8R8A8_UNORM:
408 case PIPE_FORMAT_B8G8R8X8_UNORM:
409 case PIPE_FORMAT_R8G8B8A8_SNORM:
410 case PIPE_FORMAT_R8G8B8A8_UNORM:
411 case PIPE_FORMAT_R8G8B8X8_UNORM:
412 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
413 case PIPE_FORMAT_X8B8G8R8_UNORM:
414 case PIPE_FORMAT_X8R8G8B8_UNORM:
415 case PIPE_FORMAT_R8G8B8_UNORM:
416 case PIPE_FORMAT_R8G8B8A8_SSCALED:
417 case PIPE_FORMAT_R8G8B8A8_USCALED:
418 case PIPE_FORMAT_R8G8B8A8_SINT:
419 case PIPE_FORMAT_R8G8B8A8_UINT:
420 return V_028C70_COLOR_8_8_8_8;
421
422 case PIPE_FORMAT_R10G10B10A2_UNORM:
423 case PIPE_FORMAT_R10G10B10X2_SNORM:
424 case PIPE_FORMAT_B10G10R10A2_UNORM:
425 case PIPE_FORMAT_B10G10R10A2_UINT:
426 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
427 return V_028C70_COLOR_2_10_10_10;
428
429 case PIPE_FORMAT_Z24X8_UNORM:
430 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
431 return V_028C70_COLOR_8_24;
432
433 case PIPE_FORMAT_X8Z24_UNORM:
434 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
435 return V_028C70_COLOR_24_8;
436
437 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
438 return V_028C70_COLOR_X24_8_32_FLOAT;
439
440 case PIPE_FORMAT_R32_UINT:
441 case PIPE_FORMAT_R32_SINT:
442 return V_028C70_COLOR_32;
443
444 case PIPE_FORMAT_R32_FLOAT:
445 case PIPE_FORMAT_Z32_FLOAT:
446 return V_028C70_COLOR_32_FLOAT;
447
448 case PIPE_FORMAT_R16G16_FLOAT:
449 return V_028C70_COLOR_16_16_FLOAT;
450
451 case PIPE_FORMAT_R16G16_SSCALED:
452 case PIPE_FORMAT_R16G16_UNORM:
453 case PIPE_FORMAT_R16G16_UINT:
454 case PIPE_FORMAT_R16G16_SINT:
455 return V_028C70_COLOR_16_16;
456
457 case PIPE_FORMAT_R11G11B10_FLOAT:
458 return V_028C70_COLOR_10_11_11_FLOAT;
459
460 /* 64-bit buffers. */
461 case PIPE_FORMAT_R16G16B16_USCALED:
462 case PIPE_FORMAT_R16G16B16_SSCALED:
463 case PIPE_FORMAT_R16G16B16A16_UINT:
464 case PIPE_FORMAT_R16G16B16A16_SINT:
465 case PIPE_FORMAT_R16G16B16A16_USCALED:
466 case PIPE_FORMAT_R16G16B16A16_SSCALED:
467 case PIPE_FORMAT_R16G16B16A16_UNORM:
468 case PIPE_FORMAT_R16G16B16A16_SNORM:
469 return V_028C70_COLOR_16_16_16_16;
470
471 case PIPE_FORMAT_R16G16B16_FLOAT:
472 case PIPE_FORMAT_R16G16B16A16_FLOAT:
473 return V_028C70_COLOR_16_16_16_16_FLOAT;
474
475 case PIPE_FORMAT_R32G32_FLOAT:
476 return V_028C70_COLOR_32_32_FLOAT;
477
478 case PIPE_FORMAT_R32G32_USCALED:
479 case PIPE_FORMAT_R32G32_SSCALED:
480 case PIPE_FORMAT_R32G32_SINT:
481 case PIPE_FORMAT_R32G32_UINT:
482 return V_028C70_COLOR_32_32;
483
484 /* 96-bit buffers. */
485 case PIPE_FORMAT_R32G32B32_FLOAT:
486 return V_028C70_COLOR_32_32_32_FLOAT;
487
488 /* 128-bit buffers. */
489 case PIPE_FORMAT_R32G32B32A32_SNORM:
490 case PIPE_FORMAT_R32G32B32A32_UNORM:
491 case PIPE_FORMAT_R32G32B32A32_SSCALED:
492 case PIPE_FORMAT_R32G32B32A32_USCALED:
493 case PIPE_FORMAT_R32G32B32A32_SINT:
494 case PIPE_FORMAT_R32G32B32A32_UINT:
495 return V_028C70_COLOR_32_32_32_32;
496 case PIPE_FORMAT_R32G32B32A32_FLOAT:
497 return V_028C70_COLOR_32_32_32_32_FLOAT;
498
499 /* YUV buffers. */
500 case PIPE_FORMAT_UYVY:
501 case PIPE_FORMAT_YUYV:
502 default:
503 return ~0U; /* Unsupported. */
504 }
505 }
506
507 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
508 {
509 if (R600_BIG_ENDIAN) {
510 switch(colorformat) {
511
512 /* 8-bit buffers. */
513 case V_028C70_COLOR_8:
514 return ENDIAN_NONE;
515
516 /* 16-bit buffers. */
517 case V_028C70_COLOR_5_6_5:
518 case V_028C70_COLOR_1_5_5_5:
519 case V_028C70_COLOR_4_4_4_4:
520 case V_028C70_COLOR_16:
521 case V_028C70_COLOR_8_8:
522 return ENDIAN_8IN16;
523
524 /* 32-bit buffers. */
525 case V_028C70_COLOR_8_8_8_8:
526 case V_028C70_COLOR_2_10_10_10:
527 case V_028C70_COLOR_8_24:
528 case V_028C70_COLOR_24_8:
529 case V_028C70_COLOR_32_FLOAT:
530 case V_028C70_COLOR_16_16_FLOAT:
531 case V_028C70_COLOR_16_16:
532 return ENDIAN_8IN32;
533
534 /* 64-bit buffers. */
535 case V_028C70_COLOR_16_16_16_16:
536 case V_028C70_COLOR_16_16_16_16_FLOAT:
537 return ENDIAN_8IN16;
538
539 case V_028C70_COLOR_32_32_FLOAT:
540 case V_028C70_COLOR_32_32:
541 case V_028C70_COLOR_X24_8_32_FLOAT:
542 return ENDIAN_8IN32;
543
544 /* 96-bit buffers. */
545 case V_028C70_COLOR_32_32_32_FLOAT:
546 /* 128-bit buffers. */
547 case V_028C70_COLOR_32_32_32_32_FLOAT:
548 case V_028C70_COLOR_32_32_32_32:
549 return ENDIAN_8IN32;
550 default:
551 return ENDIAN_NONE; /* Unsupported. */
552 }
553 } else {
554 return ENDIAN_NONE;
555 }
556 }
557
558 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
559 {
560 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
561 }
562
563 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
564 {
565 return r600_translate_colorformat(format) != ~0U &&
566 r600_translate_colorswap(format) != ~0U;
567 }
568
569 static bool r600_is_zs_format_supported(enum pipe_format format)
570 {
571 return r600_translate_dbformat(format) != ~0U;
572 }
573
574 boolean evergreen_is_format_supported(struct pipe_screen *screen,
575 enum pipe_format format,
576 enum pipe_texture_target target,
577 unsigned sample_count,
578 unsigned usage)
579 {
580 unsigned retval = 0;
581
582 if (target >= PIPE_MAX_TEXTURE_TYPES) {
583 R600_ERR("r600: unsupported texture type %d\n", target);
584 return FALSE;
585 }
586
587 if (!util_format_is_supported(format, usage))
588 return FALSE;
589
590 /* Multisample */
591 if (sample_count > 1)
592 return FALSE;
593
594 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
595 r600_is_sampler_format_supported(screen, format)) {
596 retval |= PIPE_BIND_SAMPLER_VIEW;
597 }
598
599 if ((usage & (PIPE_BIND_RENDER_TARGET |
600 PIPE_BIND_DISPLAY_TARGET |
601 PIPE_BIND_SCANOUT |
602 PIPE_BIND_SHARED)) &&
603 r600_is_colorbuffer_format_supported(format)) {
604 retval |= usage &
605 (PIPE_BIND_RENDER_TARGET |
606 PIPE_BIND_DISPLAY_TARGET |
607 PIPE_BIND_SCANOUT |
608 PIPE_BIND_SHARED);
609 }
610
611 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
612 r600_is_zs_format_supported(format)) {
613 retval |= PIPE_BIND_DEPTH_STENCIL;
614 }
615
616 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
617 r600_is_vertex_format_supported(format)) {
618 retval |= PIPE_BIND_VERTEX_BUFFER;
619 }
620
621 if (usage & PIPE_BIND_TRANSFER_READ)
622 retval |= PIPE_BIND_TRANSFER_READ;
623 if (usage & PIPE_BIND_TRANSFER_WRITE)
624 retval |= PIPE_BIND_TRANSFER_WRITE;
625
626 return retval == usage;
627 }
628
629 static void *evergreen_create_blend_state(struct pipe_context *ctx,
630 const struct pipe_blend_state *state)
631 {
632 struct r600_context *rctx = (struct r600_context *)ctx;
633 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
634 struct r600_pipe_state *rstate;
635 uint32_t color_control, target_mask;
636 /* XXX there is more then 8 framebuffer */
637 unsigned blend_cntl[8];
638
639 if (blend == NULL) {
640 return NULL;
641 }
642
643 rstate = &blend->rstate;
644
645 rstate->id = R600_PIPE_STATE_BLEND;
646
647 target_mask = 0;
648 color_control = S_028808_MODE(1);
649 if (state->logicop_enable) {
650 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
651 } else {
652 color_control |= (0xcc << 16);
653 }
654 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
655 if (state->independent_blend_enable) {
656 for (int i = 0; i < 8; i++) {
657 target_mask |= (state->rt[i].colormask << (4 * i));
658 }
659 } else {
660 for (int i = 0; i < 8; i++) {
661 target_mask |= (state->rt[0].colormask << (4 * i));
662 }
663 }
664 blend->cb_target_mask = target_mask;
665
666 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
667 color_control, NULL, 0);
668
669 for (int i = 0; i < 8; i++) {
670 /* state->rt entries > 0 only written if independent blending */
671 const int j = state->independent_blend_enable ? i : 0;
672
673 unsigned eqRGB = state->rt[j].rgb_func;
674 unsigned srcRGB = state->rt[j].rgb_src_factor;
675 unsigned dstRGB = state->rt[j].rgb_dst_factor;
676 unsigned eqA = state->rt[j].alpha_func;
677 unsigned srcA = state->rt[j].alpha_src_factor;
678 unsigned dstA = state->rt[j].alpha_dst_factor;
679
680 blend_cntl[i] = 0;
681 if (!state->rt[j].blend_enable)
682 continue;
683
684 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
685 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
686 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
687 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
688
689 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
690 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
691 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
692 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
693 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
694 }
695 }
696 for (int i = 0; i < 8; i++) {
697 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], NULL, 0);
698 }
699
700 return rstate;
701 }
702
703 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
704 const struct pipe_depth_stencil_alpha_state *state)
705 {
706 struct r600_context *rctx = (struct r600_context *)ctx;
707 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
708 unsigned db_depth_control, alpha_test_control, alpha_ref;
709 unsigned db_render_control;
710 struct r600_pipe_state *rstate;
711
712 if (dsa == NULL) {
713 return NULL;
714 }
715
716 dsa->valuemask[0] = state->stencil[0].valuemask;
717 dsa->valuemask[1] = state->stencil[1].valuemask;
718 dsa->writemask[0] = state->stencil[0].writemask;
719 dsa->writemask[1] = state->stencil[1].writemask;
720
721 rstate = &dsa->rstate;
722
723 rstate->id = R600_PIPE_STATE_DSA;
724 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
725 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
726 S_028800_ZFUNC(state->depth.func);
727
728 /* stencil */
729 if (state->stencil[0].enabled) {
730 db_depth_control |= S_028800_STENCIL_ENABLE(1);
731 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
732 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
733 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
734 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
735
736 if (state->stencil[1].enabled) {
737 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
738 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
739 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
740 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
741 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
742 }
743 }
744
745 /* alpha */
746 alpha_test_control = 0;
747 alpha_ref = 0;
748 if (state->alpha.enabled) {
749 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
750 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
751 alpha_ref = fui(state->alpha.ref_value);
752 }
753 dsa->alpha_ref = alpha_ref;
754
755 /* misc */
756 db_render_control = 0;
757 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
758 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
759 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0);
760 return rstate;
761 }
762
763 static void *evergreen_create_rs_state(struct pipe_context *ctx,
764 const struct pipe_rasterizer_state *state)
765 {
766 struct r600_context *rctx = (struct r600_context *)ctx;
767 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
768 struct r600_pipe_state *rstate;
769 unsigned tmp;
770 unsigned prov_vtx = 1, polygon_dual_mode;
771 float psize_min, psize_max;
772
773 if (rs == NULL) {
774 return NULL;
775 }
776
777 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
778 state->fill_back != PIPE_POLYGON_MODE_FILL);
779
780 if (state->flatshade_first)
781 prov_vtx = 0;
782
783 rstate = &rs->rstate;
784 rs->rasterizer_discard = state->rasterizer_discard;
785 rs->flatshade = state->flatshade;
786 rs->sprite_coord_enable = state->sprite_coord_enable;
787 rs->two_side = state->light_twoside;
788 rs->clip_plane_enable = state->clip_plane_enable;
789 rs->pa_sc_line_stipple = state->line_stipple_enable ?
790 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
791 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
792 rs->pa_cl_clip_cntl =
793 S_028810_PS_UCP_MODE(3) |
794 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
795 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
796 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
797
798 /* offset */
799 rs->offset_units = state->offset_units;
800 rs->offset_scale = state->offset_scale * 12.0f;
801
802 rstate->id = R600_PIPE_STATE_RASTERIZER;
803 tmp = S_0286D4_FLAT_SHADE_ENA(1);
804 if (state->sprite_coord_enable) {
805 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
806 S_0286D4_PNT_SPRITE_OVRD_X(2) |
807 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
808 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
809 S_0286D4_PNT_SPRITE_OVRD_W(1);
810 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
811 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
812 }
813 }
814 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
815
816 /* point size 12.4 fixed point */
817 tmp = (unsigned)(state->point_size * 8.0);
818 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
819
820 if (state->point_size_per_vertex) {
821 psize_min = util_get_min_point_size(state);
822 psize_max = 8192;
823 } else {
824 /* Force the point size to be as if the vertex output was disabled. */
825 psize_min = state->point_size;
826 psize_max = state->point_size;
827 }
828 /* Divide by two, because 0.5 = 1 pixel. */
829 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
830 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
831 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
832 NULL, 0);
833
834 tmp = (unsigned)state->line_width * 8;
835 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
836 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
837 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
838 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
839 NULL, 0);
840
841 if (rctx->chip_class == CAYMAN) {
842 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
843 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
844 NULL, 0);
845 } else {
846 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
847 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
848 NULL, 0);
849 }
850 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
851 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
852 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
853 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
854 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
855 S_028814_FACE(!state->front_ccw) |
856 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
857 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
858 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
859 S_028814_POLY_MODE(polygon_dual_mode) |
860 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
861 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)),
862 NULL, 0);
863 return rstate;
864 }
865
866 void evergreen_set_rasterizer_discard(struct pipe_context *ctx, boolean discard)
867 {
868 struct r600_context *rctx = (struct r600_context*)ctx;
869
870 if (discard != rctx->atom_eg_strmout_config.rasterizer_discard) {
871 rctx->atom_eg_strmout_config.rasterizer_discard = discard;
872 r600_atom_dirty(rctx, &rctx->atom_eg_strmout_config.atom);
873 }
874 }
875
876 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
877 const struct pipe_sampler_state *state)
878 {
879 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
880 union util_color uc;
881 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
882
883 if (rstate == NULL) {
884 return NULL;
885 }
886
887 rstate->id = R600_PIPE_STATE_SAMPLER;
888 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
889 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
890 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
891 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
892 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
893 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
894 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
895 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
896 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
897 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
898 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
899 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
900 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
901 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
902 NULL, 0);
903 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
904 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
905 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
906 S_03C008_TYPE(1),
907 NULL, 0);
908
909 if (uc.ui) {
910 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
911 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
912 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
913 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
914 }
915 return rstate;
916 }
917
918 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
919 struct pipe_resource *texture,
920 const struct pipe_sampler_view *state)
921 {
922 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
923 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
924 struct r600_pipe_resource_state *rstate;
925 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
926 unsigned format, endian;
927 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
928 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
929 unsigned height, depth, width;
930 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
931
932 if (view == NULL)
933 return NULL;
934 rstate = &view->state;
935
936 /* initialize base object */
937 view->base = *state;
938 view->base.texture = NULL;
939 pipe_reference(NULL, &texture->reference);
940 view->base.texture = texture;
941 view->base.reference.count = 1;
942 view->base.context = ctx;
943
944 swizzle[0] = state->swizzle_r;
945 swizzle[1] = state->swizzle_g;
946 swizzle[2] = state->swizzle_b;
947 swizzle[3] = state->swizzle_a;
948
949 format = r600_translate_texformat(ctx->screen, state->format,
950 swizzle,
951 &word4, &yuv_format);
952 if (format == ~0) {
953 format = 0;
954 }
955
956 if (tmp->is_depth && !tmp->is_flushing_texture) {
957 r600_texture_depth_flush(ctx, texture, TRUE);
958 tmp = tmp->flushed_depth_texture;
959 }
960
961 endian = r600_colorformat_endian_swap(format);
962
963 if (!rscreen->use_surface_alloc) {
964 height = texture->height0;
965 depth = texture->depth0;
966 width = texture->width0;
967 pitch = align(tmp->pitch_in_blocks[0] *
968 util_format_get_blockwidth(state->format), 8);
969 array_mode = tmp->array_mode[0];
970 tile_type = tmp->tile_type;
971 tile_split = 0;
972 macro_aspect = 0;
973 bankw = 0;
974 bankh = 0;
975 } else {
976 width = tmp->surface.level[0].npix_x;
977 height = tmp->surface.level[0].npix_y;
978 depth = tmp->surface.level[0].npix_z;
979 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
980 tile_type = tmp->tile_type;
981
982 switch (tmp->surface.level[0].mode) {
983 case RADEON_SURF_MODE_LINEAR_ALIGNED:
984 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
985 break;
986 case RADEON_SURF_MODE_2D:
987 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
988 break;
989 case RADEON_SURF_MODE_1D:
990 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
991 break;
992 case RADEON_SURF_MODE_LINEAR:
993 default:
994 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
995 break;
996 }
997 tile_split = tmp->surface.tile_split;
998 macro_aspect = tmp->surface.mtilea;
999 bankw = tmp->surface.bankw;
1000 bankh = tmp->surface.bankh;
1001 tile_split = eg_tile_split(tile_split);
1002 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1003 bankw = eg_bank_wh(bankw);
1004 bankh = eg_bank_wh(bankh);
1005 }
1006 /* 128 bit formats require tile type = 1 */
1007 if (rscreen->chip_class == CAYMAN) {
1008 if (util_format_get_blocksize(state->format) >= 16)
1009 tile_type = 1;
1010 }
1011 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1012
1013 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1014 height = 1;
1015 depth = texture->array_size;
1016 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1017 depth = texture->array_size;
1018 }
1019
1020 rstate->bo[0] = &tmp->resource;
1021 rstate->bo[1] = &tmp->resource;
1022 rstate->bo_usage[0] = RADEON_USAGE_READ;
1023 rstate->bo_usage[1] = RADEON_USAGE_READ;
1024
1025 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1026 S_030000_PITCH((pitch / 8) - 1) |
1027 S_030000_TEX_WIDTH(width - 1));
1028 if (rscreen->chip_class == CAYMAN)
1029 rstate->val[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1030 else
1031 rstate->val[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1032 rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1033 S_030004_TEX_DEPTH(depth - 1) |
1034 S_030004_ARRAY_MODE(array_mode));
1035 rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1036 if (state->u.tex.last_level) {
1037 rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1038 } else {
1039 rstate->val[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1040 }
1041 rstate->val[4] = (word4 |
1042 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1043 S_030010_ENDIAN_SWAP(endian) |
1044 S_030010_BASE_LEVEL(state->u.tex.first_level));
1045 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1046 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1047 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1048 /* aniso max 16 samples */
1049 rstate->val[6] = (S_030018_MAX_ANISO(4)) |
1050 (S_030018_TILE_SPLIT(tile_split));
1051 rstate->val[7] = S_03001C_DATA_FORMAT(format) |
1052 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1053 S_03001C_BANK_WIDTH(bankw) |
1054 S_03001C_BANK_HEIGHT(bankh) |
1055 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1056 S_03001C_NUM_BANKS(nbanks);
1057
1058 return &view->base;
1059 }
1060
1061 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1062 struct pipe_sampler_view **views)
1063 {
1064 struct r600_context *rctx = (struct r600_context *)ctx;
1065 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1066
1067 for (int i = 0; i < count; i++) {
1068 if (resource[i]) {
1069 r600_context_pipe_state_set_vs_resource(rctx, &resource[i]->state,
1070 i + R600_MAX_CONST_BUFFERS);
1071 }
1072 }
1073 }
1074
1075 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1076 struct pipe_sampler_view **views)
1077 {
1078 struct r600_context *rctx = (struct r600_context *)ctx;
1079 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1080 int i;
1081 int has_depth = 0;
1082
1083 for (i = 0; i < count; i++) {
1084 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1085 if (resource[i]) {
1086 if (((struct r600_resource_texture *)resource[i]->base.texture)->is_depth)
1087 has_depth = 1;
1088 r600_context_pipe_state_set_ps_resource(rctx, &resource[i]->state,
1089 i + R600_MAX_CONST_BUFFERS);
1090 } else
1091 r600_context_pipe_state_set_ps_resource(rctx, NULL,
1092 i + R600_MAX_CONST_BUFFERS);
1093
1094 pipe_sampler_view_reference(
1095 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1096 views[i]);
1097 } else {
1098 if (resource[i]) {
1099 if (((struct r600_resource_texture *)resource[i]->base.texture)->is_depth)
1100 has_depth = 1;
1101 }
1102 }
1103 }
1104 for (i = count; i < NUM_TEX_UNITS; i++) {
1105 if (rctx->ps_samplers.views[i]) {
1106 r600_context_pipe_state_set_ps_resource(rctx, NULL,
1107 i + R600_MAX_CONST_BUFFERS);
1108 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1109 }
1110 }
1111 rctx->have_depth_texture = has_depth;
1112 rctx->ps_samplers.n_views = count;
1113 }
1114
1115 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1116 {
1117 struct r600_context *rctx = (struct r600_context *)ctx;
1118 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1119
1120 if (count)
1121 r600_inval_texture_cache(rctx);
1122
1123 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1124 rctx->ps_samplers.n_samplers = count;
1125
1126 for (int i = 0; i < count; i++) {
1127 evergreen_context_pipe_state_set_ps_sampler(rctx, rstates[i], i);
1128 }
1129 }
1130
1131 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1132 {
1133 struct r600_context *rctx = (struct r600_context *)ctx;
1134 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1135
1136 if (count)
1137 r600_inval_texture_cache(rctx);
1138
1139 for (int i = 0; i < count; i++) {
1140 evergreen_context_pipe_state_set_vs_sampler(rctx, rstates[i], i);
1141 }
1142 }
1143
1144 static void evergreen_set_clip_state(struct pipe_context *ctx,
1145 const struct pipe_clip_state *state)
1146 {
1147 struct r600_context *rctx = (struct r600_context *)ctx;
1148 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1149 struct pipe_resource *cbuf;
1150
1151 if (rstate == NULL)
1152 return;
1153
1154 rctx->clip = *state;
1155 rstate->id = R600_PIPE_STATE_CLIP;
1156 for (int i = 0; i < 6; i++) {
1157 r600_pipe_state_add_reg(rstate,
1158 R_0285BC_PA_CL_UCP0_X + i * 16,
1159 fui(state->ucp[i][0]), NULL, 0);
1160 r600_pipe_state_add_reg(rstate,
1161 R_0285C0_PA_CL_UCP0_Y + i * 16,
1162 fui(state->ucp[i][1]) , NULL, 0);
1163 r600_pipe_state_add_reg(rstate,
1164 R_0285C4_PA_CL_UCP0_Z + i * 16,
1165 fui(state->ucp[i][2]), NULL, 0);
1166 r600_pipe_state_add_reg(rstate,
1167 R_0285C8_PA_CL_UCP0_W + i * 16,
1168 fui(state->ucp[i][3]), NULL, 0);
1169 }
1170
1171 free(rctx->states[R600_PIPE_STATE_CLIP]);
1172 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1173 r600_context_pipe_state_set(rctx, rstate);
1174
1175 cbuf = pipe_user_buffer_create(ctx->screen,
1176 state->ucp,
1177 4*4*8, /* 8*4 floats */
1178 PIPE_BIND_CONSTANT_BUFFER);
1179 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
1180 pipe_resource_reference(&cbuf, NULL);
1181 }
1182
1183 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1184 const struct pipe_poly_stipple *state)
1185 {
1186 }
1187
1188 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1189 {
1190 }
1191
1192 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1193 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1194 uint32_t *tl, uint32_t *br)
1195 {
1196 /* EG hw workaround */
1197 if (br_x == 0)
1198 tl_x = 1;
1199 if (br_y == 0)
1200 tl_y = 1;
1201
1202 /* cayman hw workaround */
1203 if (rctx->chip_class == CAYMAN) {
1204 if (br_x == 1 && br_y == 1)
1205 br_x = 2;
1206 }
1207
1208 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1209 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1210 }
1211
1212 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1213 const struct pipe_scissor_state *state)
1214 {
1215 struct r600_context *rctx = (struct r600_context *)ctx;
1216 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1217 uint32_t tl, br;
1218
1219 if (rstate == NULL)
1220 return;
1221
1222 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1223
1224 rstate->id = R600_PIPE_STATE_SCISSOR;
1225 r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl, NULL, 0);
1226 r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br, NULL, 0);
1227
1228 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1229 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1230 r600_context_pipe_state_set(rctx, rstate);
1231 }
1232
1233 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1234 const struct pipe_viewport_state *state)
1235 {
1236 struct r600_context *rctx = (struct r600_context *)ctx;
1237 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1238
1239 if (rstate == NULL)
1240 return;
1241
1242 rctx->viewport = *state;
1243 rstate->id = R600_PIPE_STATE_VIEWPORT;
1244 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
1245 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
1246 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
1247 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
1248 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
1249 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
1250
1251 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1252 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1253 r600_context_pipe_state_set(rctx, rstate);
1254 }
1255
1256 static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1257 const struct pipe_framebuffer_state *state, int cb)
1258 {
1259 struct r600_screen *rscreen = rctx->screen;
1260 struct r600_resource_texture *rtex;
1261 struct r600_surface *surf;
1262 unsigned level = state->cbufs[cb]->u.tex.level;
1263 unsigned pitch, slice;
1264 unsigned color_info, color_attrib;
1265 unsigned format, swap, ntype, endian;
1266 uint64_t offset;
1267 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1268 const struct util_format_description *desc;
1269 int i;
1270 unsigned blend_clamp = 0, blend_bypass = 0;
1271
1272 surf = (struct r600_surface *)state->cbufs[cb];
1273 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1274
1275 if (rtex->is_depth)
1276 rctx->have_depth_fb = TRUE;
1277
1278 if (rtex->is_depth && !rtex->is_flushing_texture) {
1279 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1280 rtex = rtex->flushed_depth_texture;
1281 }
1282
1283 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1284 if (!rscreen->use_surface_alloc) {
1285 offset = r600_texture_get_offset(rtex,
1286 level, state->cbufs[cb]->u.tex.first_layer);
1287 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1288 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1289 if (slice) {
1290 slice = slice - 1;
1291 }
1292 color_info = S_028C70_ARRAY_MODE(rtex->array_mode[level]);
1293 tile_split = 0;
1294 macro_aspect = 0;
1295 bankw = 0;
1296 bankh = 0;
1297 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1298 tile_type = rtex->tile_type;
1299 } else {
1300 /* workaround for linear buffers */
1301 tile_type = 1;
1302 }
1303 } else {
1304 offset = rtex->surface.level[level].offset;
1305 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1306 offset += rtex->surface.level[level].slice_size *
1307 state->cbufs[cb]->u.tex.first_layer;
1308 }
1309 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1310 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1311 if (slice) {
1312 slice = slice - 1;
1313 }
1314 color_info = 0;
1315 switch (rtex->surface.level[level].mode) {
1316 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1317 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1318 tile_type = 1;
1319 break;
1320 case RADEON_SURF_MODE_1D:
1321 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1322 tile_type = rtex->tile_type;
1323 break;
1324 case RADEON_SURF_MODE_2D:
1325 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1326 tile_type = rtex->tile_type;
1327 break;
1328 case RADEON_SURF_MODE_LINEAR:
1329 default:
1330 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1331 tile_type = 1;
1332 break;
1333 }
1334 tile_split = rtex->surface.tile_split;
1335 macro_aspect = rtex->surface.mtilea;
1336 bankw = rtex->surface.bankw;
1337 bankh = rtex->surface.bankh;
1338 tile_split = eg_tile_split(tile_split);
1339 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1340 bankw = eg_bank_wh(bankw);
1341 bankh = eg_bank_wh(bankh);
1342 }
1343 /* 128 bit formats require tile type = 1 */
1344 if (rscreen->chip_class == CAYMAN) {
1345 if (util_format_get_blocksize(surf->base.format) >= 16)
1346 tile_type = 1;
1347 }
1348 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1349 desc = util_format_description(surf->base.format);
1350 for (i = 0; i < 4; i++) {
1351 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1352 break;
1353 }
1354 }
1355
1356 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1357 S_028C74_NUM_BANKS(nbanks) |
1358 S_028C74_BANK_WIDTH(bankw) |
1359 S_028C74_BANK_HEIGHT(bankh) |
1360 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1361 S_028C74_NON_DISP_TILING_ORDER(tile_type);
1362
1363 ntype = V_028C70_NUMBER_UNORM;
1364 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1365 ntype = V_028C70_NUMBER_SRGB;
1366 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1367 if (desc->channel[i].normalized)
1368 ntype = V_028C70_NUMBER_SNORM;
1369 else if (desc->channel[i].pure_integer)
1370 ntype = V_028C70_NUMBER_SINT;
1371 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1372 if (desc->channel[i].normalized)
1373 ntype = V_028C70_NUMBER_UNORM;
1374 else if (desc->channel[i].pure_integer)
1375 ntype = V_028C70_NUMBER_UINT;
1376 }
1377
1378 format = r600_translate_colorformat(surf->base.format);
1379 swap = r600_translate_colorswap(surf->base.format);
1380 if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1381 endian = ENDIAN_NONE;
1382 } else {
1383 endian = r600_colorformat_endian_swap(format);
1384 }
1385
1386 /* blend clamp should be set for all NORM/SRGB types */
1387 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1388 ntype == V_028C70_NUMBER_SRGB)
1389 blend_clamp = 1;
1390
1391 /* set blend bypass according to docs if SINT/UINT or
1392 8/24 COLOR variants */
1393 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1394 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1395 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1396 blend_clamp = 0;
1397 blend_bypass = 1;
1398 }
1399
1400 color_info |= S_028C70_FORMAT(format) |
1401 S_028C70_COMP_SWAP(swap) |
1402 S_028C70_BLEND_CLAMP(blend_clamp) |
1403 S_028C70_BLEND_BYPASS(blend_bypass) |
1404 S_028C70_NUMBER_TYPE(ntype) |
1405 S_028C70_ENDIAN(endian);
1406
1407 /* EXPORT_NORM is an optimzation that can be enabled for better
1408 * performance in certain cases.
1409 * EXPORT_NORM can be enabled if:
1410 * - 11-bit or smaller UNORM/SNORM/SRGB
1411 * - 16-bit or smaller FLOAT
1412 */
1413 /* XXX: This should probably be the same for all CBs if we want
1414 * useful alpha tests. */
1415 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1416 ((desc->channel[i].size < 12 &&
1417 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1418 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1419 (desc->channel[i].size < 17 &&
1420 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1421 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1422 rctx->export_16bpc = true;
1423 } else {
1424 rctx->export_16bpc = false;
1425 }
1426 rctx->alpha_ref_dirty = true;
1427
1428
1429 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1430 offset >>= 8;
1431
1432 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1433 r600_pipe_state_add_reg(rstate,
1434 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1435 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1436 r600_pipe_state_add_reg(rstate,
1437 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1438 0x0, NULL, 0);
1439 r600_pipe_state_add_reg(rstate,
1440 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1441 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1442 r600_pipe_state_add_reg(rstate,
1443 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1444 S_028C64_PITCH_TILE_MAX(pitch),
1445 NULL, 0);
1446 r600_pipe_state_add_reg(rstate,
1447 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1448 S_028C68_SLICE_TILE_MAX(slice),
1449 NULL, 0);
1450 if (!rscreen->use_surface_alloc) {
1451 r600_pipe_state_add_reg(rstate,
1452 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1453 0x00000000, NULL, 0);
1454 } else {
1455 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1456 r600_pipe_state_add_reg(rstate,
1457 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1458 0x00000000, NULL, 0);
1459 } else {
1460 r600_pipe_state_add_reg(rstate,
1461 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1462 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1463 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
1464 NULL, 0);
1465 }
1466 }
1467 r600_pipe_state_add_reg(rstate,
1468 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1469 color_attrib,
1470 &rtex->resource, RADEON_USAGE_READWRITE);
1471 }
1472
1473 static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1474 const struct pipe_framebuffer_state *state)
1475 {
1476 struct r600_screen *rscreen = rctx->screen;
1477 struct r600_resource_texture *rtex;
1478 struct r600_surface *surf;
1479 uint64_t offset;
1480 unsigned level, first_layer, pitch, slice, format, array_mode;
1481 unsigned macro_aspect, tile_split, bankh, bankw, z_info, nbanks;
1482
1483 if (state->zsbuf == NULL)
1484 return;
1485
1486 surf = (struct r600_surface *)state->zsbuf;
1487 level = surf->base.u.tex.level;
1488 rtex = (struct r600_resource_texture*)surf->base.texture;
1489 first_layer = surf->base.u.tex.first_layer;
1490 format = r600_translate_dbformat(rtex->real_format);
1491
1492 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1493 /* XXX remove this once tiling is properly supported */
1494 if (!rscreen->use_surface_alloc) {
1495 /* XXX remove this once tiling is properly supported */
1496 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1497 V_028C70_ARRAY_1D_TILED_THIN1;
1498
1499 offset += r600_texture_get_offset(rtex, level, first_layer);
1500 pitch = (rtex->pitch_in_blocks[level] / 8) - 1;
1501 slice = ((rtex->pitch_in_blocks[level] * surf->aligned_height) / 64);
1502 if (slice) {
1503 slice = slice - 1;
1504 }
1505 tile_split = 0;
1506 macro_aspect = 0;
1507 bankw = 0;
1508 bankh = 0;
1509 } else {
1510 offset += rtex->surface.level[level].offset;
1511 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1512 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1513 if (slice) {
1514 slice = slice - 1;
1515 }
1516 switch (rtex->surface.level[level].mode) {
1517 case RADEON_SURF_MODE_2D:
1518 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1519 break;
1520 case RADEON_SURF_MODE_1D:
1521 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1522 case RADEON_SURF_MODE_LINEAR:
1523 default:
1524 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1525 break;
1526 }
1527 tile_split = rtex->surface.tile_split;
1528 macro_aspect = rtex->surface.mtilea;
1529 bankw = rtex->surface.bankw;
1530 bankh = rtex->surface.bankh;
1531 tile_split = eg_tile_split(tile_split);
1532 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1533 bankw = eg_bank_wh(bankw);
1534 bankh = eg_bank_wh(bankh);
1535 }
1536 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1537 offset >>= 8;
1538
1539 z_info = S_028040_ARRAY_MODE(array_mode) |
1540 S_028040_FORMAT(format) |
1541 S_028040_TILE_SPLIT(tile_split)|
1542 S_028040_NUM_BANKS(nbanks) |
1543 S_028040_BANK_WIDTH(bankw) |
1544 S_028040_BANK_HEIGHT(bankh) |
1545 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1546
1547 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1548 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1549 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1550 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1551 if (!rscreen->use_surface_alloc) {
1552 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1553 0x00000000, NULL, 0);
1554 } else {
1555 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1556 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1557 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer),
1558 NULL, 0);
1559 }
1560
1561 if (rtex->stencil) {
1562 uint64_t stencil_offset =
1563 r600_texture_get_offset(rtex->stencil, level, first_layer);
1564 unsigned stile_split;
1565
1566 stile_split = eg_tile_split(rtex->stencil->surface.tile_split);
1567 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1568 stencil_offset >>= 8;
1569
1570 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1571 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1572 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1573 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1574 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1575 1 | S_028044_TILE_SPLIT(stile_split),
1576 &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1577 } else {
1578 if (rscreen->use_surface_alloc && rtex->surface.flags & RADEON_SURF_SBUFFER) {
1579 uint64_t stencil_offset = rtex->surface.stencil_offset;
1580 unsigned stile_split = rtex->surface.stencil_tile_split;
1581
1582 stile_split = eg_tile_split(stile_split);
1583 stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1584 stencil_offset += rtex->surface.level[level].offset / 4;
1585 stencil_offset >>= 8;
1586
1587 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1588 stencil_offset, &rtex->resource,
1589 RADEON_USAGE_READWRITE);
1590 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1591 stencil_offset, &rtex->resource,
1592 RADEON_USAGE_READWRITE);
1593 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1594 1 | S_028044_TILE_SPLIT(stile_split),
1595 &rtex->resource,
1596 RADEON_USAGE_READWRITE);
1597 } else {
1598 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1599 offset, &rtex->resource,
1600 RADEON_USAGE_READWRITE);
1601 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1602 offset, &rtex->resource,
1603 RADEON_USAGE_READWRITE);
1604 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1605 0, NULL, RADEON_USAGE_READWRITE);
1606 }
1607 }
1608
1609 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, z_info,
1610 &rtex->resource, RADEON_USAGE_READWRITE);
1611 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1612 S_028058_PITCH_TILE_MAX(pitch),
1613 NULL, 0);
1614 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1615 S_02805C_SLICE_TILE_MAX(slice),
1616 NULL, 0);
1617 }
1618
1619 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1620 const struct pipe_framebuffer_state *state)
1621 {
1622 struct r600_context *rctx = (struct r600_context *)ctx;
1623 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1624 uint32_t shader_mask, tl, br;
1625
1626 if (rstate == NULL)
1627 return;
1628
1629 r600_flush_framebuffer(rctx, false);
1630
1631 /* unreference old buffer and reference new one */
1632 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1633
1634 util_copy_framebuffer_state(&rctx->framebuffer, state);
1635
1636 /* build states */
1637 rctx->have_depth_fb = 0;
1638 rctx->nr_cbufs = state->nr_cbufs;
1639 for (int i = 0; i < state->nr_cbufs; i++) {
1640 evergreen_cb(rctx, rstate, state, i);
1641 }
1642 if (state->zsbuf) {
1643 evergreen_db(rctx, rstate, state);
1644 }
1645
1646 shader_mask = 0;
1647 for (int i = 0; i < state->nr_cbufs; i++) {
1648 shader_mask |= 0xf << (i * 4);
1649 }
1650
1651 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1652
1653 r600_pipe_state_add_reg(rstate,
1654 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1655 NULL, 0);
1656 r600_pipe_state_add_reg(rstate,
1657 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1658 NULL, 0);
1659 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1660 shader_mask, NULL, 0);
1661
1662 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1663 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1664 r600_context_pipe_state_set(rctx, rstate);
1665
1666 if (state->zsbuf) {
1667 evergreen_polygon_offset_update(rctx);
1668 }
1669 }
1670
1671 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1672 {
1673 struct radeon_winsys_cs *cs = rctx->cs;
1674 struct r600_atom_db_misc_state *a = (struct r600_atom_db_misc_state*)atom;
1675 unsigned db_count_control = 0;
1676 unsigned db_render_override =
1677 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1678 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1679 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1680
1681 if (a->occlusion_query_enabled) {
1682 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1683 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1684 }
1685
1686 r600_write_context_reg(cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1687 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1688 }
1689
1690 static void evergreen_emit_streamout_config(struct r600_context *rctx, struct r600_atom *atom)
1691 {
1692 struct radeon_winsys_cs *cs = rctx->cs;
1693 struct r600_atom_eg_strmout_config *a = (struct r600_atom_eg_strmout_config*)atom;
1694
1695 r600_write_context_reg(cs, R_028B94_VGT_STRMOUT_CONFIG,
1696 S_028B94_STREAMOUT_0_EN(a->stream0_enable) |
1697 S_028B94_RAST_STREAM(a->rasterizer_discard ? 4 : 0));
1698 }
1699
1700 void evergreen_init_state_functions(struct r600_context *rctx)
1701 {
1702 r600_init_atom(&rctx->atom_db_misc_state.atom, evergreen_emit_db_misc_state, 6, 0);
1703 r600_atom_dirty(rctx, &rctx->atom_db_misc_state.atom);
1704 r600_init_atom(&rctx->atom_eg_strmout_config.atom, evergreen_emit_streamout_config, 6, 0);
1705 r600_atom_dirty(rctx, &rctx->atom_eg_strmout_config.atom);
1706
1707 rctx->context.create_blend_state = evergreen_create_blend_state;
1708 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1709 rctx->context.create_fs_state = r600_create_shader_state;
1710 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1711 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1712 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1713 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1714 rctx->context.create_vs_state = r600_create_shader_state;
1715 rctx->context.bind_blend_state = r600_bind_blend_state;
1716 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1717 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1718 rctx->context.bind_fs_state = r600_bind_ps_shader;
1719 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1720 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1721 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1722 rctx->context.bind_vs_state = r600_bind_vs_shader;
1723 rctx->context.delete_blend_state = r600_delete_state;
1724 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1725 rctx->context.delete_fs_state = r600_delete_ps_shader;
1726 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1727 rctx->context.delete_sampler_state = r600_delete_state;
1728 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1729 rctx->context.delete_vs_state = r600_delete_vs_shader;
1730 rctx->context.set_blend_color = r600_set_blend_color;
1731 rctx->context.set_clip_state = evergreen_set_clip_state;
1732 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1733 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1734 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1735 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1736 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1737 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1738 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1739 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1740 rctx->context.set_index_buffer = r600_set_index_buffer;
1741 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1742 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1743 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1744 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1745 rctx->context.texture_barrier = r600_texture_barrier;
1746 rctx->context.create_stream_output_target = r600_create_so_target;
1747 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1748 rctx->context.set_stream_output_targets = r600_set_so_targets;
1749 }
1750
1751 static void cayman_init_atom_start_cs(struct r600_context *rctx)
1752 {
1753 struct r600_command_buffer *cb = &rctx->atom_start_cs;
1754
1755 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1756
1757 /* This must be first. */
1758 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1759 r600_store_value(cb, 0x80000000);
1760 r600_store_value(cb, 0x80000000);
1761
1762 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
1763 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
1764 /* always set the temp clauses */
1765 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
1766
1767 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
1768 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
1769 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
1770
1771 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
1772
1773 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
1774
1775 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
1776 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
1777 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
1778 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
1779 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
1780 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
1781 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
1782 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
1783 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
1784 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
1785 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
1786 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
1787 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
1788 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
1789
1790 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
1791
1792 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
1793 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
1794 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
1795
1796 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
1797
1798 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
1799
1800 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1801 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
1802 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
1803
1804 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
1805 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
1806 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
1807
1808 r600_store_context_reg(cb, CM_R_028804_DB_EQAA, 0x110000);
1809
1810 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
1811 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
1812 r600_store_value(cb, 0);
1813 r600_store_value(cb, 0);
1814 r600_store_value(cb, 0);
1815 r600_store_value(cb, 0);
1816 r600_store_value(cb, 0);
1817 r600_store_value(cb, 0);
1818 r600_store_value(cb, 0);
1819 r600_store_value(cb, 0);
1820 r600_store_value(cb, 0);
1821 r600_store_value(cb, 0);
1822 r600_store_value(cb, 0);
1823 r600_store_value(cb, 0);
1824 r600_store_value(cb, 0);
1825 r600_store_value(cb, 0);
1826 r600_store_value(cb, 0);
1827 r600_store_value(cb, 0);
1828 r600_store_value(cb, 0);
1829 r600_store_value(cb, 0);
1830 r600_store_value(cb, 0);
1831 r600_store_value(cb, 0);
1832 r600_store_value(cb, 0);
1833 r600_store_value(cb, 0);
1834 r600_store_value(cb, 0);
1835 r600_store_value(cb, 0);
1836 r600_store_value(cb, 0);
1837 r600_store_value(cb, 0);
1838 r600_store_value(cb, 0);
1839 r600_store_value(cb, 0);
1840 r600_store_value(cb, 0);
1841 r600_store_value(cb, 0);
1842 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
1843 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
1844 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
1845
1846 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
1847
1848 r600_store_context_reg_seq(cb, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
1849 r600_store_value(cb, ~0); /* CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 */
1850 r600_store_value(cb, ~0); /* CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 */
1851
1852 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
1853 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
1854 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
1855
1856 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
1857
1858 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
1859 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
1860 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
1861 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
1862
1863 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
1864 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
1865
1866 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
1867 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
1868 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
1869
1870 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1871 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
1872 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
1873 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
1874
1875 r600_store_context_reg_seq(cb, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
1876 r600_store_value(cb, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1877 r600_store_value(cb, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1878
1879 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
1880 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
1881 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
1882 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
1883 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
1884
1885 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
1886 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
1887 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
1888
1889 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
1890 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
1891 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
1892
1893 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
1894 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
1895 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
1896
1897 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
1898 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
1899 }
1900
1901 void evergreen_init_atom_start_cs(struct r600_context *rctx)
1902 {
1903 struct r600_command_buffer *cb = &rctx->atom_start_cs;
1904 int ps_prio;
1905 int vs_prio;
1906 int gs_prio;
1907 int es_prio;
1908 int hs_prio, cs_prio, ls_prio;
1909 int num_ps_gprs;
1910 int num_vs_gprs;
1911 int num_gs_gprs;
1912 int num_es_gprs;
1913 int num_hs_gprs;
1914 int num_ls_gprs;
1915 int num_temp_gprs;
1916 int num_ps_threads;
1917 int num_vs_threads;
1918 int num_gs_threads;
1919 int num_es_threads;
1920 int num_hs_threads;
1921 int num_ls_threads;
1922 int num_ps_stack_entries;
1923 int num_vs_stack_entries;
1924 int num_gs_stack_entries;
1925 int num_es_stack_entries;
1926 int num_hs_stack_entries;
1927 int num_ls_stack_entries;
1928 enum radeon_family family;
1929 unsigned tmp;
1930
1931 if (rctx->chip_class == CAYMAN) {
1932 cayman_init_atom_start_cs(rctx);
1933 return;
1934 }
1935
1936 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1937
1938 /* This must be first. */
1939 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1940 r600_store_value(cb, 0x80000000);
1941 r600_store_value(cb, 0x80000000);
1942
1943 family = rctx->family;
1944 ps_prio = 0;
1945 vs_prio = 1;
1946 gs_prio = 2;
1947 es_prio = 3;
1948 hs_prio = 0;
1949 ls_prio = 0;
1950 cs_prio = 0;
1951
1952 switch (family) {
1953 case CHIP_CEDAR:
1954 default:
1955 num_ps_gprs = 93;
1956 num_vs_gprs = 46;
1957 num_temp_gprs = 4;
1958 num_gs_gprs = 31;
1959 num_es_gprs = 31;
1960 num_hs_gprs = 23;
1961 num_ls_gprs = 23;
1962 num_ps_threads = 96;
1963 num_vs_threads = 16;
1964 num_gs_threads = 16;
1965 num_es_threads = 16;
1966 num_hs_threads = 16;
1967 num_ls_threads = 16;
1968 num_ps_stack_entries = 42;
1969 num_vs_stack_entries = 42;
1970 num_gs_stack_entries = 42;
1971 num_es_stack_entries = 42;
1972 num_hs_stack_entries = 42;
1973 num_ls_stack_entries = 42;
1974 break;
1975 case CHIP_REDWOOD:
1976 num_ps_gprs = 93;
1977 num_vs_gprs = 46;
1978 num_temp_gprs = 4;
1979 num_gs_gprs = 31;
1980 num_es_gprs = 31;
1981 num_hs_gprs = 23;
1982 num_ls_gprs = 23;
1983 num_ps_threads = 128;
1984 num_vs_threads = 20;
1985 num_gs_threads = 20;
1986 num_es_threads = 20;
1987 num_hs_threads = 20;
1988 num_ls_threads = 20;
1989 num_ps_stack_entries = 42;
1990 num_vs_stack_entries = 42;
1991 num_gs_stack_entries = 42;
1992 num_es_stack_entries = 42;
1993 num_hs_stack_entries = 42;
1994 num_ls_stack_entries = 42;
1995 break;
1996 case CHIP_JUNIPER:
1997 num_ps_gprs = 93;
1998 num_vs_gprs = 46;
1999 num_temp_gprs = 4;
2000 num_gs_gprs = 31;
2001 num_es_gprs = 31;
2002 num_hs_gprs = 23;
2003 num_ls_gprs = 23;
2004 num_ps_threads = 128;
2005 num_vs_threads = 20;
2006 num_gs_threads = 20;
2007 num_es_threads = 20;
2008 num_hs_threads = 20;
2009 num_ls_threads = 20;
2010 num_ps_stack_entries = 85;
2011 num_vs_stack_entries = 85;
2012 num_gs_stack_entries = 85;
2013 num_es_stack_entries = 85;
2014 num_hs_stack_entries = 85;
2015 num_ls_stack_entries = 85;
2016 break;
2017 case CHIP_CYPRESS:
2018 case CHIP_HEMLOCK:
2019 num_ps_gprs = 93;
2020 num_vs_gprs = 46;
2021 num_temp_gprs = 4;
2022 num_gs_gprs = 31;
2023 num_es_gprs = 31;
2024 num_hs_gprs = 23;
2025 num_ls_gprs = 23;
2026 num_ps_threads = 128;
2027 num_vs_threads = 20;
2028 num_gs_threads = 20;
2029 num_es_threads = 20;
2030 num_hs_threads = 20;
2031 num_ls_threads = 20;
2032 num_ps_stack_entries = 85;
2033 num_vs_stack_entries = 85;
2034 num_gs_stack_entries = 85;
2035 num_es_stack_entries = 85;
2036 num_hs_stack_entries = 85;
2037 num_ls_stack_entries = 85;
2038 break;
2039 case CHIP_PALM:
2040 num_ps_gprs = 93;
2041 num_vs_gprs = 46;
2042 num_temp_gprs = 4;
2043 num_gs_gprs = 31;
2044 num_es_gprs = 31;
2045 num_hs_gprs = 23;
2046 num_ls_gprs = 23;
2047 num_ps_threads = 96;
2048 num_vs_threads = 16;
2049 num_gs_threads = 16;
2050 num_es_threads = 16;
2051 num_hs_threads = 16;
2052 num_ls_threads = 16;
2053 num_ps_stack_entries = 42;
2054 num_vs_stack_entries = 42;
2055 num_gs_stack_entries = 42;
2056 num_es_stack_entries = 42;
2057 num_hs_stack_entries = 42;
2058 num_ls_stack_entries = 42;
2059 break;
2060 case CHIP_SUMO:
2061 num_ps_gprs = 93;
2062 num_vs_gprs = 46;
2063 num_temp_gprs = 4;
2064 num_gs_gprs = 31;
2065 num_es_gprs = 31;
2066 num_hs_gprs = 23;
2067 num_ls_gprs = 23;
2068 num_ps_threads = 96;
2069 num_vs_threads = 25;
2070 num_gs_threads = 25;
2071 num_es_threads = 25;
2072 num_hs_threads = 25;
2073 num_ls_threads = 25;
2074 num_ps_stack_entries = 42;
2075 num_vs_stack_entries = 42;
2076 num_gs_stack_entries = 42;
2077 num_es_stack_entries = 42;
2078 num_hs_stack_entries = 42;
2079 num_ls_stack_entries = 42;
2080 break;
2081 case CHIP_SUMO2:
2082 num_ps_gprs = 93;
2083 num_vs_gprs = 46;
2084 num_temp_gprs = 4;
2085 num_gs_gprs = 31;
2086 num_es_gprs = 31;
2087 num_hs_gprs = 23;
2088 num_ls_gprs = 23;
2089 num_ps_threads = 96;
2090 num_vs_threads = 25;
2091 num_gs_threads = 25;
2092 num_es_threads = 25;
2093 num_hs_threads = 25;
2094 num_ls_threads = 25;
2095 num_ps_stack_entries = 85;
2096 num_vs_stack_entries = 85;
2097 num_gs_stack_entries = 85;
2098 num_es_stack_entries = 85;
2099 num_hs_stack_entries = 85;
2100 num_ls_stack_entries = 85;
2101 break;
2102 case CHIP_BARTS:
2103 num_ps_gprs = 93;
2104 num_vs_gprs = 46;
2105 num_temp_gprs = 4;
2106 num_gs_gprs = 31;
2107 num_es_gprs = 31;
2108 num_hs_gprs = 23;
2109 num_ls_gprs = 23;
2110 num_ps_threads = 128;
2111 num_vs_threads = 20;
2112 num_gs_threads = 20;
2113 num_es_threads = 20;
2114 num_hs_threads = 20;
2115 num_ls_threads = 20;
2116 num_ps_stack_entries = 85;
2117 num_vs_stack_entries = 85;
2118 num_gs_stack_entries = 85;
2119 num_es_stack_entries = 85;
2120 num_hs_stack_entries = 85;
2121 num_ls_stack_entries = 85;
2122 break;
2123 case CHIP_TURKS:
2124 num_ps_gprs = 93;
2125 num_vs_gprs = 46;
2126 num_temp_gprs = 4;
2127 num_gs_gprs = 31;
2128 num_es_gprs = 31;
2129 num_hs_gprs = 23;
2130 num_ls_gprs = 23;
2131 num_ps_threads = 128;
2132 num_vs_threads = 20;
2133 num_gs_threads = 20;
2134 num_es_threads = 20;
2135 num_hs_threads = 20;
2136 num_ls_threads = 20;
2137 num_ps_stack_entries = 42;
2138 num_vs_stack_entries = 42;
2139 num_gs_stack_entries = 42;
2140 num_es_stack_entries = 42;
2141 num_hs_stack_entries = 42;
2142 num_ls_stack_entries = 42;
2143 break;
2144 case CHIP_CAICOS:
2145 num_ps_gprs = 93;
2146 num_vs_gprs = 46;
2147 num_temp_gprs = 4;
2148 num_gs_gprs = 31;
2149 num_es_gprs = 31;
2150 num_hs_gprs = 23;
2151 num_ls_gprs = 23;
2152 num_ps_threads = 128;
2153 num_vs_threads = 10;
2154 num_gs_threads = 10;
2155 num_es_threads = 10;
2156 num_hs_threads = 10;
2157 num_ls_threads = 10;
2158 num_ps_stack_entries = 42;
2159 num_vs_stack_entries = 42;
2160 num_gs_stack_entries = 42;
2161 num_es_stack_entries = 42;
2162 num_hs_stack_entries = 42;
2163 num_ls_stack_entries = 42;
2164 break;
2165 }
2166
2167 tmp = 0;
2168 switch (family) {
2169 case CHIP_CEDAR:
2170 case CHIP_PALM:
2171 case CHIP_SUMO:
2172 case CHIP_SUMO2:
2173 case CHIP_CAICOS:
2174 break;
2175 default:
2176 tmp |= S_008C00_VC_ENABLE(1);
2177 break;
2178 }
2179 tmp |= S_008C00_EXPORT_SRC_C(1);
2180 tmp |= S_008C00_CS_PRIO(cs_prio);
2181 tmp |= S_008C00_LS_PRIO(ls_prio);
2182 tmp |= S_008C00_HS_PRIO(hs_prio);
2183 tmp |= S_008C00_PS_PRIO(ps_prio);
2184 tmp |= S_008C00_VS_PRIO(vs_prio);
2185 tmp |= S_008C00_GS_PRIO(gs_prio);
2186 tmp |= S_008C00_ES_PRIO(es_prio);
2187
2188 /* enable dynamic GPR resource management */
2189 if (rctx->screen->info.drm_minor >= 7) {
2190 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2191 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2192 /* always set temp clauses */
2193 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2194 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2195 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2196 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2197 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2198 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2199 S_028838_PS_GPRS(0x1e) |
2200 S_028838_VS_GPRS(0x1e) |
2201 S_028838_GS_GPRS(0x1e) |
2202 S_028838_ES_GPRS(0x1e) |
2203 S_028838_HS_GPRS(0x1e) |
2204 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2205 } else {
2206 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2207 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2208
2209 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2210 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2211 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2212 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2213
2214 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2215 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2216 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2217
2218 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2219 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2220 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2221 }
2222
2223 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2224 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2225 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2226 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2227 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2228 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2229
2230 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2231 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2232 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2233
2234 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2235 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2236 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2237
2238 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2239 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2240 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2241
2242 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2243 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2244 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2245
2246 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2247 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2248
2249 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2250 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2251
2252 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2253
2254 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2255 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2256 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2257 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2258 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2259 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2260 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2261
2262 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2263 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2264 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2265 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2266 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2267
2268 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2269 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2270 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2271 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2272 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2273 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2274 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2275 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2276 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2277 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2278 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2279 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2280 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2281 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2282
2283 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2284
2285 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2286 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2287 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2288
2289 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2290
2291 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2292 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2293 r600_store_value(cb, 0);
2294 r600_store_value(cb, 0);
2295 r600_store_value(cb, 0);
2296 r600_store_value(cb, 0);
2297 r600_store_value(cb, 0);
2298 r600_store_value(cb, 0);
2299 r600_store_value(cb, 0);
2300 r600_store_value(cb, 0);
2301 r600_store_value(cb, 0);
2302 r600_store_value(cb, 0);
2303 r600_store_value(cb, 0);
2304 r600_store_value(cb, 0);
2305 r600_store_value(cb, 0);
2306 r600_store_value(cb, 0);
2307 r600_store_value(cb, 0);
2308 r600_store_value(cb, 0);
2309 r600_store_value(cb, 0);
2310 r600_store_value(cb, 0);
2311 r600_store_value(cb, 0);
2312 r600_store_value(cb, 0);
2313 r600_store_value(cb, 0);
2314 r600_store_value(cb, 0);
2315 r600_store_value(cb, 0);
2316 r600_store_value(cb, 0);
2317 r600_store_value(cb, 0);
2318 r600_store_value(cb, 0);
2319 r600_store_value(cb, 0);
2320 r600_store_value(cb, 0);
2321 r600_store_value(cb, 0);
2322 r600_store_value(cb, 0);
2323 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2324 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2325 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2326
2327 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2328
2329 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2330 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2331 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2332
2333 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2334 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2335 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2336
2337 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2338 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2339 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2340
2341 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2342 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2343 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2344
2345 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2346 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2347 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2348 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2349
2350 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2351
2352 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2353 r600_store_value(cb, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
2354 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2355
2356 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 5);
2357 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2358 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2359 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2360 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2361 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
2362
2363 r600_store_context_reg(cb, R_028C3C_PA_SC_AA_MASK, ~0);
2364
2365 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2366 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2367 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2368
2369 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2370 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2371 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2372
2373 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
2374 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
2375 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2376
2377 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2378 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2379 }
2380
2381 void evergreen_polygon_offset_update(struct r600_context *rctx)
2382 {
2383 struct r600_pipe_state state;
2384
2385 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2386 state.nregs = 0;
2387 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2388 float offset_units = rctx->rasterizer->offset_units;
2389 unsigned offset_db_fmt_cntl = 0, depth;
2390
2391 switch (rctx->framebuffer.zsbuf->texture->format) {
2392 case PIPE_FORMAT_Z24X8_UNORM:
2393 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2394 depth = -24;
2395 offset_units *= 2.0f;
2396 break;
2397 case PIPE_FORMAT_Z32_FLOAT:
2398 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2399 depth = -23;
2400 offset_units *= 1.0f;
2401 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2402 break;
2403 case PIPE_FORMAT_Z16_UNORM:
2404 depth = -16;
2405 offset_units *= 4.0f;
2406 break;
2407 default:
2408 return;
2409 }
2410 /* XXX some of those reg can be computed with cso */
2411 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2412 r600_pipe_state_add_reg(&state,
2413 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2414 fui(rctx->rasterizer->offset_scale), NULL, 0);
2415 r600_pipe_state_add_reg(&state,
2416 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2417 fui(offset_units), NULL, 0);
2418 r600_pipe_state_add_reg(&state,
2419 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2420 fui(rctx->rasterizer->offset_scale), NULL, 0);
2421 r600_pipe_state_add_reg(&state,
2422 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2423 fui(offset_units), NULL, 0);
2424 r600_pipe_state_add_reg(&state,
2425 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2426 offset_db_fmt_cntl, NULL, 0);
2427 r600_context_pipe_state_set(rctx, &state);
2428 }
2429 }
2430
2431 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2432 {
2433 struct r600_context *rctx = (struct r600_context *)ctx;
2434 struct r600_pipe_state *rstate = &shader->rstate;
2435 struct r600_shader *rshader = &shader->shader;
2436 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2437 int pos_index = -1, face_index = -1;
2438 int ninterp = 0;
2439 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2440 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2441
2442 rstate->nregs = 0;
2443
2444 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2445 for (i = 0; i < rshader->ninput; i++) {
2446 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2447 POSITION goes via GPRs from the SC so isn't counted */
2448 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2449 pos_index = i;
2450 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2451 face_index = i;
2452 else {
2453 ninterp++;
2454 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2455 have_linear = TRUE;
2456 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2457 have_perspective = TRUE;
2458 if (rshader->input[i].centroid)
2459 have_centroid = TRUE;
2460 }
2461
2462 sid = rshader->input[i].spi_sid;
2463
2464 if (sid) {
2465
2466 tmp = S_028644_SEMANTIC(sid);
2467
2468 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2469 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2470 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2471 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2472 tmp |= S_028644_FLAT_SHADE(1);
2473 }
2474
2475 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2476 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2477 tmp |= S_028644_PT_SPRITE_TEX(1);
2478 }
2479
2480 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2481 tmp, NULL, 0);
2482
2483 idx++;
2484 }
2485 }
2486
2487 for (i = 0; i < rshader->noutput; i++) {
2488 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2489 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2490 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2491 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2492 }
2493 if (rshader->uses_kill)
2494 db_shader_control |= S_02880C_KILL_ENABLE(1);
2495
2496 exports_ps = 0;
2497 num_cout = 0;
2498 for (i = 0; i < rshader->noutput; i++) {
2499 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2500 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2501 exports_ps |= 1;
2502 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2503 if (rshader->fs_write_all)
2504 num_cout = rshader->nr_cbufs;
2505 else
2506 num_cout++;
2507 }
2508 }
2509 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2510 if (!exports_ps) {
2511 /* always at least export 1 component per pixel */
2512 exports_ps = 2;
2513 }
2514
2515 if (ninterp == 0) {
2516 ninterp = 1;
2517 have_perspective = TRUE;
2518 }
2519
2520 if (!have_perspective && !have_linear)
2521 have_perspective = TRUE;
2522
2523 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2524 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2525 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2526 spi_input_z = 0;
2527 if (pos_index != -1) {
2528 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2529 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2530 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2531 spi_input_z |= 1;
2532 }
2533
2534 spi_ps_in_control_1 = 0;
2535 if (face_index != -1) {
2536 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2537 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2538 }
2539
2540 spi_baryc_cntl = 0;
2541 if (have_perspective)
2542 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2543 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2544 if (have_linear)
2545 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2546 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2547
2548 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2549 spi_ps_in_control_0, NULL, 0);
2550 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2551 spi_ps_in_control_1, NULL, 0);
2552 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2553 0, NULL, 0);
2554 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0);
2555 r600_pipe_state_add_reg(rstate,
2556 R_0286E0_SPI_BARYC_CNTL,
2557 spi_baryc_cntl,
2558 NULL, 0);
2559
2560 r600_pipe_state_add_reg(rstate,
2561 R_028840_SQ_PGM_START_PS,
2562 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2563 shader->bo, RADEON_USAGE_READ);
2564 r600_pipe_state_add_reg(rstate,
2565 R_028844_SQ_PGM_RESOURCES_PS,
2566 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2567 S_028844_PRIME_CACHE_ON_DRAW(1) |
2568 S_028844_STACK_SIZE(rshader->bc.nstack),
2569 NULL, 0);
2570 r600_pipe_state_add_reg(rstate,
2571 R_02884C_SQ_PGM_EXPORTS_PS,
2572 exports_ps, NULL, 0);
2573 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2574 db_shader_control,
2575 NULL, 0);
2576
2577 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2578 if (rctx->rasterizer)
2579 shader->flatshade = rctx->rasterizer->flatshade;
2580 }
2581
2582 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2583 {
2584 struct r600_context *rctx = (struct r600_context *)ctx;
2585 struct r600_pipe_state *rstate = &shader->rstate;
2586 struct r600_shader *rshader = &shader->shader;
2587 unsigned spi_vs_out_id[10] = {};
2588 unsigned i, tmp, nparams = 0;
2589
2590 /* clear previous register */
2591 rstate->nregs = 0;
2592
2593 for (i = 0; i < rshader->noutput; i++) {
2594 if (rshader->output[i].spi_sid) {
2595 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2596 spi_vs_out_id[nparams / 4] |= tmp;
2597 nparams++;
2598 }
2599 }
2600
2601 for (i = 0; i < 10; i++) {
2602 r600_pipe_state_add_reg(rstate,
2603 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2604 spi_vs_out_id[i], NULL, 0);
2605 }
2606
2607 /* Certain attributes (position, psize, etc.) don't count as params.
2608 * VS is required to export at least one param and r600_shader_from_tgsi()
2609 * takes care of adding a dummy export.
2610 */
2611 if (nparams < 1)
2612 nparams = 1;
2613
2614 r600_pipe_state_add_reg(rstate,
2615 R_0286C4_SPI_VS_OUT_CONFIG,
2616 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2617 NULL, 0);
2618 r600_pipe_state_add_reg(rstate,
2619 R_028860_SQ_PGM_RESOURCES_VS,
2620 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2621 S_028860_STACK_SIZE(rshader->bc.nstack),
2622 NULL, 0);
2623 r600_pipe_state_add_reg(rstate,
2624 R_02885C_SQ_PGM_START_VS,
2625 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2626 shader->bo, RADEON_USAGE_READ);
2627
2628 shader->pa_cl_vs_out_cntl =
2629 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2630 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2631 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2632 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2633 }
2634
2635 void evergreen_fetch_shader(struct pipe_context *ctx,
2636 struct r600_vertex_element *ve)
2637 {
2638 struct r600_context *rctx = (struct r600_context *)ctx;
2639 struct r600_pipe_state *rstate = &ve->rstate;
2640 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2641 rstate->nregs = 0;
2642 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2643 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2644 ve->fetch_shader, RADEON_USAGE_READ);
2645 }
2646
2647 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2648 {
2649 struct pipe_depth_stencil_alpha_state dsa;
2650 struct r600_pipe_state *rstate;
2651
2652 memset(&dsa, 0, sizeof(dsa));
2653
2654 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2655 r600_pipe_state_add_reg(rstate,
2656 R_028000_DB_RENDER_CONTROL,
2657 S_028000_DEPTH_COPY_ENABLE(1) |
2658 S_028000_STENCIL_COPY_ENABLE(1) |
2659 S_028000_COPY_CENTROID(1),
2660 NULL, 0);
2661 /* Don't set the 'is_flush' flag in r600_pipe_dsa, evergreen doesn't need it. */
2662 return rstate;
2663 }
2664
2665 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
2666 struct r600_pipe_resource_state *rstate)
2667 {
2668 rstate->id = R600_PIPE_STATE_RESOURCE;
2669
2670 rstate->val[0] = 0;
2671 rstate->bo[0] = NULL;
2672 rstate->val[1] = 0;
2673 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2674 rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2675 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2676 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2677 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2678 rstate->val[4] = 0;
2679 rstate->val[5] = 0;
2680 rstate->val[6] = 0;
2681 rstate->val[7] = 0xc0000000;
2682 }
2683
2684
2685 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
2686 struct r600_pipe_resource_state *rstate,
2687 struct r600_resource *rbuffer,
2688 unsigned offset, unsigned stride,
2689 enum radeon_bo_usage usage)
2690 {
2691 uint64_t va;
2692
2693 va = r600_resource_va(ctx->screen, (void *)rbuffer);
2694 rstate->bo[0] = rbuffer;
2695 rstate->bo_usage[0] = usage;
2696 rstate->val[0] = (offset + va) & 0xFFFFFFFFUL;
2697 rstate->val[1] = rbuffer->buf->size - offset - 1;
2698 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2699 S_030008_STRIDE(stride) |
2700 (((va + offset) >> 32UL) & 0xFF);
2701 }