projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: atomize clip state
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "evergreend.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31 #include "evergreen_compute.h"
32
33 static uint32_t eg_num_banks(uint32_t nbanks)
34 {
35 switch (nbanks) {
36 case 2:
37 return 0;
38 case 4:
39 return 1;
40 case 8:
41 default:
42 return 2;
43 case 16:
44 return 3;
45 }
46 }
47
48
49 static unsigned eg_tile_split(unsigned tile_split)
50 {
51 switch (tile_split) {
52 case 64: tile_split = 0; break;
53 case 128: tile_split = 1; break;
54 case 256: tile_split = 2; break;
55 case 512: tile_split = 3; break;
56 default:
57 case 1024: tile_split = 4; break;
58 case 2048: tile_split = 5; break;
59 case 4096: tile_split = 6; break;
60 }
61 return tile_split;
62 }
63
64 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65 {
66 switch (macro_tile_aspect) {
67 default:
68 case 1: macro_tile_aspect = 0; break;
69 case 2: macro_tile_aspect = 1; break;
70 case 4: macro_tile_aspect = 2; break;
71 case 8: macro_tile_aspect = 3; break;
72 }
73 return macro_tile_aspect;
74 }
75
76 static unsigned eg_bank_wh(unsigned bankwh)
77 {
78 switch (bankwh) {
79 default:
80 case 1: bankwh = 0; break;
81 case 2: bankwh = 1; break;
82 case 4: bankwh = 2; break;
83 case 8: bankwh = 3; break;
84 }
85 return bankwh;
86 }
87
88 static uint32_t r600_translate_blend_function(int blend_func)
89 {
90 switch (blend_func) {
91 case PIPE_BLEND_ADD:
92 return V_028780_COMB_DST_PLUS_SRC;
93 case PIPE_BLEND_SUBTRACT:
94 return V_028780_COMB_SRC_MINUS_DST;
95 case PIPE_BLEND_REVERSE_SUBTRACT:
96 return V_028780_COMB_DST_MINUS_SRC;
97 case PIPE_BLEND_MIN:
98 return V_028780_COMB_MIN_DST_SRC;
99 case PIPE_BLEND_MAX:
100 return V_028780_COMB_MAX_DST_SRC;
101 default:
102 R600_ERR("Unknown blend function %d\n", blend_func);
103 assert(0);
104 break;
105 }
106 return 0;
107 }
108
109 static uint32_t r600_translate_blend_factor(int blend_fact)
110 {
111 switch (blend_fact) {
112 case PIPE_BLENDFACTOR_ONE:
113 return V_028780_BLEND_ONE;
114 case PIPE_BLENDFACTOR_SRC_COLOR:
115 return V_028780_BLEND_SRC_COLOR;
116 case PIPE_BLENDFACTOR_SRC_ALPHA:
117 return V_028780_BLEND_SRC_ALPHA;
118 case PIPE_BLENDFACTOR_DST_ALPHA:
119 return V_028780_BLEND_DST_ALPHA;
120 case PIPE_BLENDFACTOR_DST_COLOR:
121 return V_028780_BLEND_DST_COLOR;
122 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123 return V_028780_BLEND_SRC_ALPHA_SATURATE;
124 case PIPE_BLENDFACTOR_CONST_COLOR:
125 return V_028780_BLEND_CONST_COLOR;
126 case PIPE_BLENDFACTOR_CONST_ALPHA:
127 return V_028780_BLEND_CONST_ALPHA;
128 case PIPE_BLENDFACTOR_ZERO:
129 return V_028780_BLEND_ZERO;
130 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136 case PIPE_BLENDFACTOR_INV_DST_COLOR:
137 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_SRC1_COLOR:
143 return V_028780_BLEND_SRC1_COLOR;
144 case PIPE_BLENDFACTOR_SRC1_ALPHA:
145 return V_028780_BLEND_SRC1_ALPHA;
146 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147 return V_028780_BLEND_INV_SRC1_COLOR;
148 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149 return V_028780_BLEND_INV_SRC1_ALPHA;
150 default:
151 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152 assert(0);
153 break;
154 }
155 return 0;
156 }
157
158 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
159 {
160 switch (dim) {
161 default:
162 case PIPE_TEXTURE_1D:
163 return V_030000_SQ_TEX_DIM_1D;
164 case PIPE_TEXTURE_1D_ARRAY:
165 return V_030000_SQ_TEX_DIM_1D_ARRAY;
166 case PIPE_TEXTURE_2D:
167 case PIPE_TEXTURE_RECT:
168 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
169 V_030000_SQ_TEX_DIM_2D;
170 case PIPE_TEXTURE_2D_ARRAY:
171 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
172 V_030000_SQ_TEX_DIM_2D_ARRAY;
173 case PIPE_TEXTURE_3D:
174 return V_030000_SQ_TEX_DIM_3D;
175 case PIPE_TEXTURE_CUBE:
176 return V_030000_SQ_TEX_DIM_CUBEMAP;
177 }
178 }
179
180 static uint32_t r600_translate_dbformat(enum pipe_format format)
181 {
182 switch (format) {
183 case PIPE_FORMAT_Z16_UNORM:
184 return V_028040_Z_16;
185 case PIPE_FORMAT_Z24X8_UNORM:
186 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
187 return V_028040_Z_24;
188 case PIPE_FORMAT_Z32_FLOAT:
189 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
190 return V_028040_Z_32_FLOAT;
191 default:
192 return ~0U;
193 }
194 }
195
196 static uint32_t r600_translate_colorswap(enum pipe_format format)
197 {
198 switch (format) {
199 /* 8-bit buffers. */
200 case PIPE_FORMAT_L4A4_UNORM:
201 case PIPE_FORMAT_A4R4_UNORM:
202 return V_028C70_SWAP_ALT;
203
204 case PIPE_FORMAT_A8_UNORM:
205 case PIPE_FORMAT_A8_SNORM:
206 case PIPE_FORMAT_A8_UINT:
207 case PIPE_FORMAT_A8_SINT:
208 case PIPE_FORMAT_A16_UNORM:
209 case PIPE_FORMAT_A16_SNORM:
210 case PIPE_FORMAT_A16_UINT:
211 case PIPE_FORMAT_A16_SINT:
212 case PIPE_FORMAT_A16_FLOAT:
213 case PIPE_FORMAT_A32_UINT:
214 case PIPE_FORMAT_A32_SINT:
215 case PIPE_FORMAT_A32_FLOAT:
216 case PIPE_FORMAT_R4A4_UNORM:
217 return V_028C70_SWAP_ALT_REV;
218 case PIPE_FORMAT_I8_UNORM:
219 case PIPE_FORMAT_I8_SNORM:
220 case PIPE_FORMAT_I8_UINT:
221 case PIPE_FORMAT_I8_SINT:
222 case PIPE_FORMAT_I16_UNORM:
223 case PIPE_FORMAT_I16_SNORM:
224 case PIPE_FORMAT_I16_UINT:
225 case PIPE_FORMAT_I16_SINT:
226 case PIPE_FORMAT_I16_FLOAT:
227 case PIPE_FORMAT_I32_UINT:
228 case PIPE_FORMAT_I32_SINT:
229 case PIPE_FORMAT_I32_FLOAT:
230 case PIPE_FORMAT_L8_UNORM:
231 case PIPE_FORMAT_L8_SNORM:
232 case PIPE_FORMAT_L8_UINT:
233 case PIPE_FORMAT_L8_SINT:
234 case PIPE_FORMAT_L8_SRGB:
235 case PIPE_FORMAT_L16_UNORM:
236 case PIPE_FORMAT_L16_SNORM:
237 case PIPE_FORMAT_L16_UINT:
238 case PIPE_FORMAT_L16_SINT:
239 case PIPE_FORMAT_L16_FLOAT:
240 case PIPE_FORMAT_L32_UINT:
241 case PIPE_FORMAT_L32_SINT:
242 case PIPE_FORMAT_L32_FLOAT:
243 case PIPE_FORMAT_R8_UNORM:
244 case PIPE_FORMAT_R8_SNORM:
245 case PIPE_FORMAT_R8_UINT:
246 case PIPE_FORMAT_R8_SINT:
247 return V_028C70_SWAP_STD;
248
249 /* 16-bit buffers. */
250 case PIPE_FORMAT_B5G6R5_UNORM:
251 return V_028C70_SWAP_STD_REV;
252
253 case PIPE_FORMAT_B5G5R5A1_UNORM:
254 case PIPE_FORMAT_B5G5R5X1_UNORM:
255 return V_028C70_SWAP_ALT;
256
257 case PIPE_FORMAT_B4G4R4A4_UNORM:
258 case PIPE_FORMAT_B4G4R4X4_UNORM:
259 return V_028C70_SWAP_ALT;
260
261 case PIPE_FORMAT_Z16_UNORM:
262 return V_028C70_SWAP_STD;
263
264 case PIPE_FORMAT_L8A8_UNORM:
265 case PIPE_FORMAT_L8A8_SNORM:
266 case PIPE_FORMAT_L8A8_UINT:
267 case PIPE_FORMAT_L8A8_SINT:
268 case PIPE_FORMAT_L8A8_SRGB:
269 case PIPE_FORMAT_L16A16_UNORM:
270 case PIPE_FORMAT_L16A16_SNORM:
271 case PIPE_FORMAT_L16A16_UINT:
272 case PIPE_FORMAT_L16A16_SINT:
273 case PIPE_FORMAT_L16A16_FLOAT:
274 case PIPE_FORMAT_L32A32_UINT:
275 case PIPE_FORMAT_L32A32_SINT:
276 case PIPE_FORMAT_L32A32_FLOAT:
277 return V_028C70_SWAP_ALT;
278 case PIPE_FORMAT_R8G8_UNORM:
279 case PIPE_FORMAT_R8G8_SNORM:
280 case PIPE_FORMAT_R8G8_UINT:
281 case PIPE_FORMAT_R8G8_SINT:
282 return V_028C70_SWAP_STD;
283
284 case PIPE_FORMAT_R16_UNORM:
285 case PIPE_FORMAT_R16_SNORM:
286 case PIPE_FORMAT_R16_UINT:
287 case PIPE_FORMAT_R16_SINT:
288 case PIPE_FORMAT_R16_FLOAT:
289 return V_028C70_SWAP_STD;
290
291 /* 32-bit buffers. */
292 case PIPE_FORMAT_A8B8G8R8_SRGB:
293 return V_028C70_SWAP_STD_REV;
294 case PIPE_FORMAT_B8G8R8A8_SRGB:
295 return V_028C70_SWAP_ALT;
296
297 case PIPE_FORMAT_B8G8R8A8_UNORM:
298 case PIPE_FORMAT_B8G8R8X8_UNORM:
299 return V_028C70_SWAP_ALT;
300
301 case PIPE_FORMAT_A8R8G8B8_UNORM:
302 case PIPE_FORMAT_X8R8G8B8_UNORM:
303 return V_028C70_SWAP_ALT_REV;
304 case PIPE_FORMAT_R8G8B8A8_SNORM:
305 case PIPE_FORMAT_R8G8B8A8_UNORM:
306 case PIPE_FORMAT_R8G8B8A8_SINT:
307 case PIPE_FORMAT_R8G8B8A8_UINT:
308 case PIPE_FORMAT_R8G8B8X8_UNORM:
309 return V_028C70_SWAP_STD;
310
311 case PIPE_FORMAT_A8B8G8R8_UNORM:
312 case PIPE_FORMAT_X8B8G8R8_UNORM:
313 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
314 return V_028C70_SWAP_STD_REV;
315
316 case PIPE_FORMAT_Z24X8_UNORM:
317 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
318 return V_028C70_SWAP_STD;
319
320 case PIPE_FORMAT_X8Z24_UNORM:
321 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
322 return V_028C70_SWAP_STD;
323
324 case PIPE_FORMAT_R10G10B10A2_UNORM:
325 case PIPE_FORMAT_R10G10B10X2_SNORM:
326 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
327 return V_028C70_SWAP_STD;
328
329 case PIPE_FORMAT_B10G10R10A2_UNORM:
330 case PIPE_FORMAT_B10G10R10A2_UINT:
331 return V_028C70_SWAP_ALT;
332
333 case PIPE_FORMAT_R11G11B10_FLOAT:
334 case PIPE_FORMAT_R32_FLOAT:
335 case PIPE_FORMAT_R32_UINT:
336 case PIPE_FORMAT_R32_SINT:
337 case PIPE_FORMAT_Z32_FLOAT:
338 case PIPE_FORMAT_R16G16_FLOAT:
339 case PIPE_FORMAT_R16G16_UNORM:
340 case PIPE_FORMAT_R16G16_SNORM:
341 case PIPE_FORMAT_R16G16_UINT:
342 case PIPE_FORMAT_R16G16_SINT:
343 return V_028C70_SWAP_STD;
344
345 /* 64-bit buffers. */
346 case PIPE_FORMAT_R32G32_FLOAT:
347 case PIPE_FORMAT_R32G32_UINT:
348 case PIPE_FORMAT_R32G32_SINT:
349 case PIPE_FORMAT_R16G16B16A16_UNORM:
350 case PIPE_FORMAT_R16G16B16A16_SNORM:
351 case PIPE_FORMAT_R16G16B16A16_UINT:
352 case PIPE_FORMAT_R16G16B16A16_SINT:
353 case PIPE_FORMAT_R16G16B16A16_FLOAT:
354 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
355
356 /* 128-bit buffers. */
357 case PIPE_FORMAT_R32G32B32A32_FLOAT:
358 case PIPE_FORMAT_R32G32B32A32_SNORM:
359 case PIPE_FORMAT_R32G32B32A32_UNORM:
360 case PIPE_FORMAT_R32G32B32A32_SINT:
361 case PIPE_FORMAT_R32G32B32A32_UINT:
362 return V_028C70_SWAP_STD;
363 default:
364 R600_ERR("unsupported colorswap format %d\n", format);
365 return ~0U;
366 }
367 return ~0U;
368 }
369
370 static uint32_t r600_translate_colorformat(enum pipe_format format)
371 {
372 switch (format) {
373 /* 8-bit buffers. */
374 case PIPE_FORMAT_A8_UNORM:
375 case PIPE_FORMAT_A8_SNORM:
376 case PIPE_FORMAT_A8_UINT:
377 case PIPE_FORMAT_A8_SINT:
378 case PIPE_FORMAT_I8_UNORM:
379 case PIPE_FORMAT_I8_SNORM:
380 case PIPE_FORMAT_I8_UINT:
381 case PIPE_FORMAT_I8_SINT:
382 case PIPE_FORMAT_L8_UNORM:
383 case PIPE_FORMAT_L8_SNORM:
384 case PIPE_FORMAT_L8_UINT:
385 case PIPE_FORMAT_L8_SINT:
386 case PIPE_FORMAT_L8_SRGB:
387 case PIPE_FORMAT_R8_UNORM:
388 case PIPE_FORMAT_R8_SNORM:
389 case PIPE_FORMAT_R8_UINT:
390 case PIPE_FORMAT_R8_SINT:
391 return V_028C70_COLOR_8;
392
393 /* 16-bit buffers. */
394 case PIPE_FORMAT_B5G6R5_UNORM:
395 return V_028C70_COLOR_5_6_5;
396
397 case PIPE_FORMAT_B5G5R5A1_UNORM:
398 case PIPE_FORMAT_B5G5R5X1_UNORM:
399 return V_028C70_COLOR_1_5_5_5;
400
401 case PIPE_FORMAT_B4G4R4A4_UNORM:
402 case PIPE_FORMAT_B4G4R4X4_UNORM:
403 return V_028C70_COLOR_4_4_4_4;
404
405 case PIPE_FORMAT_Z16_UNORM:
406 return V_028C70_COLOR_16;
407
408 case PIPE_FORMAT_L8A8_UNORM:
409 case PIPE_FORMAT_L8A8_SNORM:
410 case PIPE_FORMAT_L8A8_UINT:
411 case PIPE_FORMAT_L8A8_SINT:
412 case PIPE_FORMAT_L8A8_SRGB:
413 case PIPE_FORMAT_R8G8_UNORM:
414 case PIPE_FORMAT_R8G8_SNORM:
415 case PIPE_FORMAT_R8G8_UINT:
416 case PIPE_FORMAT_R8G8_SINT:
417 return V_028C70_COLOR_8_8;
418
419 case PIPE_FORMAT_R16_UNORM:
420 case PIPE_FORMAT_R16_SNORM:
421 case PIPE_FORMAT_R16_UINT:
422 case PIPE_FORMAT_R16_SINT:
423 case PIPE_FORMAT_A16_UNORM:
424 case PIPE_FORMAT_A16_SNORM:
425 case PIPE_FORMAT_A16_UINT:
426 case PIPE_FORMAT_A16_SINT:
427 case PIPE_FORMAT_L16_UNORM:
428 case PIPE_FORMAT_L16_SNORM:
429 case PIPE_FORMAT_L16_UINT:
430 case PIPE_FORMAT_L16_SINT:
431 case PIPE_FORMAT_I16_UNORM:
432 case PIPE_FORMAT_I16_SNORM:
433 case PIPE_FORMAT_I16_UINT:
434 case PIPE_FORMAT_I16_SINT:
435 return V_028C70_COLOR_16;
436
437 case PIPE_FORMAT_R16_FLOAT:
438 case PIPE_FORMAT_A16_FLOAT:
439 case PIPE_FORMAT_L16_FLOAT:
440 case PIPE_FORMAT_I16_FLOAT:
441 return V_028C70_COLOR_16_FLOAT;
442
443 /* 32-bit buffers. */
444 case PIPE_FORMAT_A8B8G8R8_SRGB:
445 case PIPE_FORMAT_A8B8G8R8_UNORM:
446 case PIPE_FORMAT_A8R8G8B8_UNORM:
447 case PIPE_FORMAT_B8G8R8A8_SRGB:
448 case PIPE_FORMAT_B8G8R8A8_UNORM:
449 case PIPE_FORMAT_B8G8R8X8_UNORM:
450 case PIPE_FORMAT_R8G8B8A8_SNORM:
451 case PIPE_FORMAT_R8G8B8A8_UNORM:
452 case PIPE_FORMAT_R8G8B8X8_UNORM:
453 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
454 case PIPE_FORMAT_X8B8G8R8_UNORM:
455 case PIPE_FORMAT_X8R8G8B8_UNORM:
456 case PIPE_FORMAT_R8G8B8_UNORM:
457 case PIPE_FORMAT_R8G8B8A8_SINT:
458 case PIPE_FORMAT_R8G8B8A8_UINT:
459 return V_028C70_COLOR_8_8_8_8;
460
461 case PIPE_FORMAT_R10G10B10A2_UNORM:
462 case PIPE_FORMAT_R10G10B10X2_SNORM:
463 case PIPE_FORMAT_B10G10R10A2_UNORM:
464 case PIPE_FORMAT_B10G10R10A2_UINT:
465 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
466 return V_028C70_COLOR_2_10_10_10;
467
468 case PIPE_FORMAT_Z24X8_UNORM:
469 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
470 return V_028C70_COLOR_8_24;
471
472 case PIPE_FORMAT_X8Z24_UNORM:
473 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
474 return V_028C70_COLOR_24_8;
475
476 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
477 return V_028C70_COLOR_X24_8_32_FLOAT;
478
479 case PIPE_FORMAT_R32_UINT:
480 case PIPE_FORMAT_R32_SINT:
481 case PIPE_FORMAT_A32_UINT:
482 case PIPE_FORMAT_A32_SINT:
483 case PIPE_FORMAT_L32_UINT:
484 case PIPE_FORMAT_L32_SINT:
485 case PIPE_FORMAT_I32_UINT:
486 case PIPE_FORMAT_I32_SINT:
487 return V_028C70_COLOR_32;
488
489 case PIPE_FORMAT_R32_FLOAT:
490 case PIPE_FORMAT_A32_FLOAT:
491 case PIPE_FORMAT_L32_FLOAT:
492 case PIPE_FORMAT_I32_FLOAT:
493 case PIPE_FORMAT_Z32_FLOAT:
494 return V_028C70_COLOR_32_FLOAT;
495
496 case PIPE_FORMAT_R16G16_FLOAT:
497 case PIPE_FORMAT_L16A16_FLOAT:
498 return V_028C70_COLOR_16_16_FLOAT;
499
500 case PIPE_FORMAT_R16G16_UNORM:
501 case PIPE_FORMAT_R16G16_SNORM:
502 case PIPE_FORMAT_R16G16_UINT:
503 case PIPE_FORMAT_R16G16_SINT:
504 case PIPE_FORMAT_L16A16_UNORM:
505 case PIPE_FORMAT_L16A16_SNORM:
506 case PIPE_FORMAT_L16A16_UINT:
507 case PIPE_FORMAT_L16A16_SINT:
508 return V_028C70_COLOR_16_16;
509
510 case PIPE_FORMAT_R11G11B10_FLOAT:
511 return V_028C70_COLOR_10_11_11_FLOAT;
512
513 /* 64-bit buffers. */
514 case PIPE_FORMAT_R16G16B16A16_UINT:
515 case PIPE_FORMAT_R16G16B16A16_SINT:
516 case PIPE_FORMAT_R16G16B16A16_UNORM:
517 case PIPE_FORMAT_R16G16B16A16_SNORM:
518 return V_028C70_COLOR_16_16_16_16;
519
520 case PIPE_FORMAT_R16G16B16A16_FLOAT:
521 return V_028C70_COLOR_16_16_16_16_FLOAT;
522
523 case PIPE_FORMAT_R32G32_FLOAT:
524 case PIPE_FORMAT_L32A32_FLOAT:
525 return V_028C70_COLOR_32_32_FLOAT;
526
527 case PIPE_FORMAT_R32G32_SINT:
528 case PIPE_FORMAT_R32G32_UINT:
529 case PIPE_FORMAT_L32A32_UINT:
530 case PIPE_FORMAT_L32A32_SINT:
531 return V_028C70_COLOR_32_32;
532
533 /* 128-bit buffers. */
534 case PIPE_FORMAT_R32G32B32A32_SNORM:
535 case PIPE_FORMAT_R32G32B32A32_UNORM:
536 case PIPE_FORMAT_R32G32B32A32_SINT:
537 case PIPE_FORMAT_R32G32B32A32_UINT:
538 return V_028C70_COLOR_32_32_32_32;
539 case PIPE_FORMAT_R32G32B32A32_FLOAT:
540 return V_028C70_COLOR_32_32_32_32_FLOAT;
541
542 /* YUV buffers. */
543 case PIPE_FORMAT_UYVY:
544 case PIPE_FORMAT_YUYV:
545 default:
546 return ~0U; /* Unsupported. */
547 }
548 }
549
550 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
551 {
552 if (R600_BIG_ENDIAN) {
553 switch(colorformat) {
554
555 /* 8-bit buffers. */
556 case V_028C70_COLOR_8:
557 return ENDIAN_NONE;
558
559 /* 16-bit buffers. */
560 case V_028C70_COLOR_5_6_5:
561 case V_028C70_COLOR_1_5_5_5:
562 case V_028C70_COLOR_4_4_4_4:
563 case V_028C70_COLOR_16:
564 case V_028C70_COLOR_8_8:
565 return ENDIAN_8IN16;
566
567 /* 32-bit buffers. */
568 case V_028C70_COLOR_8_8_8_8:
569 case V_028C70_COLOR_2_10_10_10:
570 case V_028C70_COLOR_8_24:
571 case V_028C70_COLOR_24_8:
572 case V_028C70_COLOR_32_FLOAT:
573 case V_028C70_COLOR_16_16_FLOAT:
574 case V_028C70_COLOR_16_16:
575 return ENDIAN_8IN32;
576
577 /* 64-bit buffers. */
578 case V_028C70_COLOR_16_16_16_16:
579 case V_028C70_COLOR_16_16_16_16_FLOAT:
580 return ENDIAN_8IN16;
581
582 case V_028C70_COLOR_32_32_FLOAT:
583 case V_028C70_COLOR_32_32:
584 case V_028C70_COLOR_X24_8_32_FLOAT:
585 return ENDIAN_8IN32;
586
587 /* 96-bit buffers. */
588 case V_028C70_COLOR_32_32_32_FLOAT:
589 /* 128-bit buffers. */
590 case V_028C70_COLOR_32_32_32_32_FLOAT:
591 case V_028C70_COLOR_32_32_32_32:
592 return ENDIAN_8IN32;
593 default:
594 return ENDIAN_NONE; /* Unsupported. */
595 }
596 } else {
597 return ENDIAN_NONE;
598 }
599 }
600
601 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
602 {
603 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
604 }
605
606 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
607 {
608 return r600_translate_colorformat(format) != ~0U &&
609 r600_translate_colorswap(format) != ~0U;
610 }
611
612 static bool r600_is_zs_format_supported(enum pipe_format format)
613 {
614 return r600_translate_dbformat(format) != ~0U;
615 }
616
617 boolean evergreen_is_format_supported(struct pipe_screen *screen,
618 enum pipe_format format,
619 enum pipe_texture_target target,
620 unsigned sample_count,
621 unsigned usage)
622 {
623 struct r600_screen *rscreen = (struct r600_screen*)screen;
624 unsigned retval = 0;
625
626 if (target >= PIPE_MAX_TEXTURE_TYPES) {
627 R600_ERR("r600: unsupported texture type %d\n", target);
628 return FALSE;
629 }
630
631 if (!util_format_is_supported(format, usage))
632 return FALSE;
633
634 if (sample_count > 1) {
635 if (rscreen->info.drm_minor < 19)
636 return FALSE;
637
638 switch (sample_count) {
639 case 2:
640 case 4:
641 case 8:
642 break;
643 default:
644 return FALSE;
645 }
646
647 /* require render-target support for multisample resources */
648 if (util_format_is_depth_or_stencil(format)) {
649 usage |= PIPE_BIND_DEPTH_STENCIL;
650 } else {
651 usage |= PIPE_BIND_RENDER_TARGET;
652 }
653 }
654
655 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
656 r600_is_sampler_format_supported(screen, format)) {
657 retval |= PIPE_BIND_SAMPLER_VIEW;
658 }
659
660 if ((usage & (PIPE_BIND_RENDER_TARGET |
661 PIPE_BIND_DISPLAY_TARGET |
662 PIPE_BIND_SCANOUT |
663 PIPE_BIND_SHARED)) &&
664 r600_is_colorbuffer_format_supported(format)) {
665 retval |= usage &
666 (PIPE_BIND_RENDER_TARGET |
667 PIPE_BIND_DISPLAY_TARGET |
668 PIPE_BIND_SCANOUT |
669 PIPE_BIND_SHARED);
670 }
671
672 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
673 r600_is_zs_format_supported(format)) {
674 retval |= PIPE_BIND_DEPTH_STENCIL;
675 }
676
677 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
678 r600_is_vertex_format_supported(format)) {
679 retval |= PIPE_BIND_VERTEX_BUFFER;
680 }
681
682 if (usage & PIPE_BIND_TRANSFER_READ)
683 retval |= PIPE_BIND_TRANSFER_READ;
684 if (usage & PIPE_BIND_TRANSFER_WRITE)
685 retval |= PIPE_BIND_TRANSFER_WRITE;
686
687 return retval == usage;
688 }
689
690 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
691 const struct pipe_blend_state *state, int mode)
692 {
693 struct r600_context *rctx = (struct r600_context *)ctx;
694 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
695 struct r600_pipe_state *rstate;
696 uint32_t color_control = 0, target_mask;
697 /* XXX there is more then 8 framebuffer */
698 unsigned blend_cntl[8];
699
700 if (blend == NULL) {
701 return NULL;
702 }
703
704 rstate = &blend->rstate;
705
706 rstate->id = R600_PIPE_STATE_BLEND;
707
708 target_mask = 0;
709 if (state->logicop_enable) {
710 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
711 } else {
712 color_control |= (0xcc << 16);
713 }
714 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
715 if (state->independent_blend_enable) {
716 for (int i = 0; i < 8; i++) {
717 target_mask |= (state->rt[i].colormask << (4 * i));
718 }
719 } else {
720 for (int i = 0; i < 8; i++) {
721 target_mask |= (state->rt[0].colormask << (4 * i));
722 }
723 }
724 blend->cb_target_mask = target_mask;
725
726 if (target_mask)
727 color_control |= S_028808_MODE(mode);
728 else
729 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
730
731 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
732 color_control);
733 /* only have dual source on MRT0 */
734 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
735 for (int i = 0; i < 8; i++) {
736 /* state->rt entries > 0 only written if independent blending */
737 const int j = state->independent_blend_enable ? i : 0;
738
739 unsigned eqRGB = state->rt[j].rgb_func;
740 unsigned srcRGB = state->rt[j].rgb_src_factor;
741 unsigned dstRGB = state->rt[j].rgb_dst_factor;
742 unsigned eqA = state->rt[j].alpha_func;
743 unsigned srcA = state->rt[j].alpha_src_factor;
744 unsigned dstA = state->rt[j].alpha_dst_factor;
745
746 blend_cntl[i] = 0;
747 if (!state->rt[j].blend_enable)
748 continue;
749
750 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
751 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
752 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
753 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
754
755 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
756 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
757 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
758 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
759 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
760 }
761 }
762 for (int i = 0; i < 8; i++) {
763 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
764 }
765
766 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK,
767 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
768 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
769 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
770 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
771 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
772
773 blend->alpha_to_one = state->alpha_to_one;
774 return rstate;
775 }
776
777 static void *evergreen_create_blend_state(struct pipe_context *ctx,
778 const struct pipe_blend_state *state)
779 {
780
781 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
782 }
783
784 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
785 const struct pipe_depth_stencil_alpha_state *state)
786 {
787 struct r600_context *rctx = (struct r600_context *)ctx;
788 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
789 unsigned db_depth_control, alpha_test_control, alpha_ref;
790 struct r600_pipe_state *rstate;
791
792 if (dsa == NULL) {
793 return NULL;
794 }
795
796 dsa->valuemask[0] = state->stencil[0].valuemask;
797 dsa->valuemask[1] = state->stencil[1].valuemask;
798 dsa->writemask[0] = state->stencil[0].writemask;
799 dsa->writemask[1] = state->stencil[1].writemask;
800
801 rstate = &dsa->rstate;
802
803 rstate->id = R600_PIPE_STATE_DSA;
804 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
805 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
806 S_028800_ZFUNC(state->depth.func);
807
808 /* stencil */
809 if (state->stencil[0].enabled) {
810 db_depth_control |= S_028800_STENCIL_ENABLE(1);
811 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
812 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
813 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
814 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
815
816 if (state->stencil[1].enabled) {
817 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
818 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
819 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
820 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
821 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
822 }
823 }
824
825 /* alpha */
826 alpha_test_control = 0;
827 alpha_ref = 0;
828 if (state->alpha.enabled) {
829 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
830 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
831 alpha_ref = fui(state->alpha.ref_value);
832 }
833 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
834 dsa->alpha_ref = alpha_ref;
835
836 /* misc */
837 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
838 return rstate;
839 }
840
841 static void *evergreen_create_rs_state(struct pipe_context *ctx,
842 const struct pipe_rasterizer_state *state)
843 {
844 struct r600_context *rctx = (struct r600_context *)ctx;
845 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
846 struct r600_pipe_state *rstate;
847 unsigned tmp;
848 unsigned prov_vtx = 1, polygon_dual_mode;
849 float psize_min, psize_max;
850
851 if (rs == NULL) {
852 return NULL;
853 }
854
855 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
856 state->fill_back != PIPE_POLYGON_MODE_FILL);
857
858 if (state->flatshade_first)
859 prov_vtx = 0;
860
861 rstate = &rs->rstate;
862 rs->flatshade = state->flatshade;
863 rs->sprite_coord_enable = state->sprite_coord_enable;
864 rs->two_side = state->light_twoside;
865 rs->clip_plane_enable = state->clip_plane_enable;
866 rs->pa_sc_line_stipple = state->line_stipple_enable ?
867 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
868 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
869 rs->pa_cl_clip_cntl =
870 S_028810_PS_UCP_MODE(3) |
871 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
872 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
873 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
874 rs->multisample_enable = state->multisample;
875
876 /* offset */
877 rs->offset_units = state->offset_units;
878 rs->offset_scale = state->offset_scale * 12.0f;
879
880 rstate->id = R600_PIPE_STATE_RASTERIZER;
881 tmp = S_0286D4_FLAT_SHADE_ENA(1);
882 if (state->sprite_coord_enable) {
883 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
884 S_0286D4_PNT_SPRITE_OVRD_X(2) |
885 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
886 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
887 S_0286D4_PNT_SPRITE_OVRD_W(1);
888 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
889 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
890 }
891 }
892 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
893
894 /* point size 12.4 fixed point */
895 tmp = (unsigned)(state->point_size * 8.0);
896 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
897
898 if (state->point_size_per_vertex) {
899 psize_min = util_get_min_point_size(state);
900 psize_max = 8192;
901 } else {
902 /* Force the point size to be as if the vertex output was disabled. */
903 psize_min = state->point_size;
904 psize_max = state->point_size;
905 }
906 /* Divide by two, because 0.5 = 1 pixel. */
907 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
908 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
909 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
910
911 tmp = (unsigned)state->line_width * 8;
912 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
913 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
914 S_028A48_MSAA_ENABLE(state->multisample) |
915 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
916 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
917
918 if (rctx->chip_class == CAYMAN) {
919 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
920 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
921 } else {
922 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
923 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
924 S_028C08_QUANT_MODE(V_028C08_X_1_4096TH));
925 }
926 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
927 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
928 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
929 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
930 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
931 S_028814_FACE(!state->front_ccw) |
932 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
933 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
934 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
935 S_028814_POLY_MODE(polygon_dual_mode) |
936 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
937 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
938 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
939 return rstate;
940 }
941
942 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
943 const struct pipe_sampler_state *state)
944 {
945 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
946 union util_color uc;
947 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
948
949 if (ss == NULL) {
950 return NULL;
951 }
952
953 /* directly into sampler avoid r6xx code to emit useless reg */
954 ss->seamless_cube_map = false;
955 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
956 ss->border_color_use = false;
957 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
958 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
959 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
960 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
961 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
962 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
963 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
964 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
965 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
966 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
967 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
968 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
969 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
970 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
971 ss->tex_sampler_words[2] = S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
972 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
973 S_03C008_TYPE(1);
974 if (uc.ui) {
975 ss->border_color_use = true;
976 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
977 ss->border_color[0] = fui(state->border_color.f[0]);
978 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
979 ss->border_color[1] = fui(state->border_color.f[1]);
980 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
981 ss->border_color[2] = fui(state->border_color.f[2]);
982 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
983 ss->border_color[3] = fui(state->border_color.f[3]);
984 }
985 return ss;
986 }
987
988 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
989 struct pipe_resource *texture,
990 const struct pipe_sampler_view *state)
991 {
992 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
993 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
994 struct r600_texture *tmp = (struct r600_texture*)texture;
995 unsigned format, endian;
996 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
997 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
998 unsigned height, depth, width;
999 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1000
1001 if (view == NULL)
1002 return NULL;
1003
1004 /* initialize base object */
1005 view->base = *state;
1006 view->base.texture = NULL;
1007 pipe_reference(NULL, &texture->reference);
1008 view->base.texture = texture;
1009 view->base.reference.count = 1;
1010 view->base.context = ctx;
1011
1012 swizzle[0] = state->swizzle_r;
1013 swizzle[1] = state->swizzle_g;
1014 swizzle[2] = state->swizzle_b;
1015 swizzle[3] = state->swizzle_a;
1016
1017 format = r600_translate_texformat(ctx->screen, state->format,
1018 swizzle,
1019 &word4, &yuv_format);
1020 assert(format != ~0);
1021 if (format == ~0) {
1022 FREE(view);
1023 return NULL;
1024 }
1025
1026 if (tmp->is_depth && !tmp->is_flushing_texture) {
1027 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1028 FREE(view);
1029 return NULL;
1030 }
1031 tmp = tmp->flushed_depth_texture;
1032 }
1033
1034 endian = r600_colorformat_endian_swap(format);
1035
1036 width = tmp->surface.level[0].npix_x;
1037 height = tmp->surface.level[0].npix_y;
1038 depth = tmp->surface.level[0].npix_z;
1039 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1040 tile_type = tmp->tile_type;
1041
1042 switch (tmp->surface.level[0].mode) {
1043 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1044 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1045 break;
1046 case RADEON_SURF_MODE_2D:
1047 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1048 break;
1049 case RADEON_SURF_MODE_1D:
1050 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1051 break;
1052 case RADEON_SURF_MODE_LINEAR:
1053 default:
1054 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1055 break;
1056 }
1057 tile_split = tmp->surface.tile_split;
1058 macro_aspect = tmp->surface.mtilea;
1059 bankw = tmp->surface.bankw;
1060 bankh = tmp->surface.bankh;
1061 tile_split = eg_tile_split(tile_split);
1062 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1063 bankw = eg_bank_wh(bankw);
1064 bankh = eg_bank_wh(bankh);
1065
1066 /* 128 bit formats require tile type = 1 */
1067 if (rscreen->chip_class == CAYMAN) {
1068 if (util_format_get_blocksize(state->format) >= 16)
1069 tile_type = 1;
1070 }
1071 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1072
1073 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1074 height = 1;
1075 depth = texture->array_size;
1076 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1077 depth = texture->array_size;
1078 }
1079
1080 view->tex_resource = &tmp->resource;
1081 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1082 S_030000_PITCH((pitch / 8) - 1) |
1083 S_030000_TEX_WIDTH(width - 1));
1084 if (rscreen->chip_class == CAYMAN)
1085 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1086 else
1087 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1088 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1089 S_030004_TEX_DEPTH(depth - 1) |
1090 S_030004_ARRAY_MODE(array_mode));
1091 view->tex_resource_words[2] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1092 if (state->u.tex.last_level && texture->nr_samples <= 1) {
1093 view->tex_resource_words[3] = (tmp->surface.level[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1094 } else {
1095 view->tex_resource_words[3] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1096 }
1097 view->tex_resource_words[4] = (word4 |
1098 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1099 S_030010_ENDIAN_SWAP(endian));
1100 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1101 S_030014_LAST_ARRAY(state->u.tex.last_layer);
1102 if (texture->nr_samples > 1) {
1103 unsigned log_samples = util_logbase2(texture->nr_samples);
1104 if (rscreen->chip_class == CAYMAN) {
1105 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
1106 }
1107 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1108 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
1109 } else {
1110 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(state->u.tex.first_level);
1111 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(state->u.tex.last_level);
1112 }
1113 /* aniso max 16 samples */
1114 view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
1115 (S_030018_TILE_SPLIT(tile_split));
1116 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1117 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1118 S_03001C_BANK_WIDTH(bankw) |
1119 S_03001C_BANK_HEIGHT(bankh) |
1120 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1121 S_03001C_NUM_BANKS(nbanks);
1122 return &view->base;
1123 }
1124
1125 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1126 {
1127 struct radeon_winsys_cs *cs = rctx->cs;
1128 struct pipe_clip_state *state = &rctx->clip_state.state;
1129
1130 r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
1131 r600_write_array(cs, 6*4, (unsigned*)state);
1132 }
1133
1134 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1135 const struct pipe_poly_stipple *state)
1136 {
1137 }
1138
1139 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1140 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1141 uint32_t *tl, uint32_t *br)
1142 {
1143 /* EG hw workaround */
1144 if (br_x == 0)
1145 tl_x = 1;
1146 if (br_y == 0)
1147 tl_y = 1;
1148
1149 /* cayman hw workaround */
1150 if (rctx->chip_class == CAYMAN) {
1151 if (br_x == 1 && br_y == 1)
1152 br_x = 2;
1153 }
1154
1155 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1156 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1157 }
1158
1159 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1160 const struct pipe_scissor_state *state)
1161 {
1162 struct r600_context *rctx = (struct r600_context *)ctx;
1163 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1164 uint32_t tl, br;
1165
1166 if (rstate == NULL)
1167 return;
1168
1169 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1170
1171 rstate->id = R600_PIPE_STATE_SCISSOR;
1172 r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1173 r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1174
1175 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1176 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1177 r600_context_pipe_state_set(rctx, rstate);
1178 }
1179
1180 void evergreen_init_color_surface(struct r600_context *rctx,
1181 struct r600_surface *surf)
1182 {
1183 struct r600_screen *rscreen = rctx->screen;
1184 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1185 struct pipe_resource *pipe_tex = surf->base.texture;
1186 unsigned level = surf->base.u.tex.level;
1187 unsigned pitch, slice;
1188 unsigned color_info, color_attrib, color_dim = 0;
1189 unsigned format, swap, ntype, endian;
1190 uint64_t offset, base_offset;
1191 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1192 const struct util_format_description *desc;
1193 int i;
1194 bool blend_clamp = 0, blend_bypass = 0;
1195
1196 if (rtex->is_depth && !rtex->is_flushing_texture) {
1197 r600_init_flushed_depth_texture(&rctx->context, pipe_tex, NULL);
1198 rtex = rtex->flushed_depth_texture;
1199 assert(rtex);
1200 }
1201
1202 offset = rtex->surface.level[level].offset;
1203 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1204 offset += rtex->surface.level[level].slice_size *
1205 surf->base.u.tex.first_layer;
1206 }
1207 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1208 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1209 if (slice) {
1210 slice = slice - 1;
1211 }
1212 color_info = 0;
1213 switch (rtex->surface.level[level].mode) {
1214 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1215 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1216 tile_type = 1;
1217 break;
1218 case RADEON_SURF_MODE_1D:
1219 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1220 tile_type = rtex->tile_type;
1221 break;
1222 case RADEON_SURF_MODE_2D:
1223 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1224 tile_type = rtex->tile_type;
1225 break;
1226 case RADEON_SURF_MODE_LINEAR:
1227 default:
1228 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1229 tile_type = 1;
1230 break;
1231 }
1232 tile_split = rtex->surface.tile_split;
1233 macro_aspect = rtex->surface.mtilea;
1234 bankw = rtex->surface.bankw;
1235 bankh = rtex->surface.bankh;
1236 fmask_bankh = rtex->fmask_bank_height;
1237 tile_split = eg_tile_split(tile_split);
1238 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1239 bankw = eg_bank_wh(bankw);
1240 bankh = eg_bank_wh(bankh);
1241 fmask_bankh = eg_bank_wh(fmask_bankh);
1242
1243 /* 128 bit formats require tile type = 1 */
1244 if (rscreen->chip_class == CAYMAN) {
1245 if (util_format_get_blocksize(surf->base.format) >= 16)
1246 tile_type = 1;
1247 }
1248 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1249 desc = util_format_description(surf->base.format);
1250 for (i = 0; i < 4; i++) {
1251 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1252 break;
1253 }
1254 }
1255
1256 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1257 S_028C74_NUM_BANKS(nbanks) |
1258 S_028C74_BANK_WIDTH(bankw) |
1259 S_028C74_BANK_HEIGHT(bankh) |
1260 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1261 S_028C74_NON_DISP_TILING_ORDER(tile_type) |
1262 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1263
1264 if (rctx->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1265 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1266 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1267 S_028C74_NUM_FRAGMENTS(log_samples);
1268 }
1269
1270 ntype = V_028C70_NUMBER_UNORM;
1271 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1272 ntype = V_028C70_NUMBER_SRGB;
1273 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1274 if (desc->channel[i].normalized)
1275 ntype = V_028C70_NUMBER_SNORM;
1276 else if (desc->channel[i].pure_integer)
1277 ntype = V_028C70_NUMBER_SINT;
1278 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1279 if (desc->channel[i].normalized)
1280 ntype = V_028C70_NUMBER_UNORM;
1281 else if (desc->channel[i].pure_integer)
1282 ntype = V_028C70_NUMBER_UINT;
1283 }
1284
1285 format = r600_translate_colorformat(surf->base.format);
1286 assert(format != ~0);
1287
1288 swap = r600_translate_colorswap(surf->base.format);
1289 assert(swap != ~0);
1290
1291 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1292 endian = ENDIAN_NONE;
1293 } else {
1294 endian = r600_colorformat_endian_swap(format);
1295 }
1296
1297 /* blend clamp should be set for all NORM/SRGB types */
1298 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1299 ntype == V_028C70_NUMBER_SRGB)
1300 blend_clamp = 1;
1301
1302 /* set blend bypass according to docs if SINT/UINT or
1303 8/24 COLOR variants */
1304 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1305 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1306 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1307 blend_clamp = 0;
1308 blend_bypass = 1;
1309 }
1310
1311 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1312
1313 color_info |= S_028C70_FORMAT(format) |
1314 S_028C70_COMP_SWAP(swap) |
1315 S_028C70_BLEND_CLAMP(blend_clamp) |
1316 S_028C70_BLEND_BYPASS(blend_bypass) |
1317 S_028C70_NUMBER_TYPE(ntype) |
1318 S_028C70_ENDIAN(endian);
1319
1320 if (rtex->is_rat) {
1321 color_info |= S_028C70_RAT(1);
1322 color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0)
1323 | S_028C78_HEIGHT_MAX(pipe_tex->height0);
1324 }
1325
1326 /* EXPORT_NORM is an optimzation that can be enabled for better
1327 * performance in certain cases.
1328 * EXPORT_NORM can be enabled if:
1329 * - 11-bit or smaller UNORM/SNORM/SRGB
1330 * - 16-bit or smaller FLOAT
1331 */
1332 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1333 ((desc->channel[i].size < 12 &&
1334 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1335 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1336 (desc->channel[i].size < 17 &&
1337 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1338 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1339 surf->export_16bpc = true;
1340 }
1341
1342 if (rtex->fmask_size && rtex->cmask_size) {
1343 color_info |= S_028C70_COMPRESSION(1) | S_028C70_FAST_CLEAR(1);
1344 }
1345
1346 base_offset = r600_resource_va(rctx->context.screen, pipe_tex);
1347
1348 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1349 surf->cb_color_base = (base_offset + offset) >> 8;
1350 surf->cb_color_dim = color_dim;
1351 surf->cb_color_info = color_info;
1352 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1353 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1354 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1355 surf->cb_color_view = 0;
1356 } else {
1357 surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1358 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1359 }
1360 surf->cb_color_attrib = color_attrib;
1361 if (rtex->fmask_size && rtex->cmask_size) {
1362 surf->cb_color_fmask = (base_offset + rtex->fmask_offset) >> 8;
1363 surf->cb_color_cmask = (base_offset + rtex->cmask_offset) >> 8;
1364 } else {
1365 surf->cb_color_fmask = surf->cb_color_base;
1366 surf->cb_color_cmask = surf->cb_color_base;
1367 }
1368 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1369 surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask_slice_tile_max);
1370
1371 surf->color_initialized = true;
1372 }
1373
1374 static void evergreen_init_depth_surface(struct r600_context *rctx,
1375 struct r600_surface *surf)
1376 {
1377 struct r600_screen *rscreen = rctx->screen;
1378 struct pipe_screen *screen = &rscreen->screen;
1379 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1380 uint64_t offset;
1381 unsigned level, pitch, slice, format, array_mode;
1382 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1383
1384 level = surf->base.u.tex.level;
1385 format = r600_translate_dbformat(surf->base.format);
1386 assert(format != ~0);
1387
1388 offset = r600_resource_va(screen, surf->base.texture);
1389 offset += rtex->surface.level[level].offset;
1390 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1391 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1392 if (slice) {
1393 slice = slice - 1;
1394 }
1395 switch (rtex->surface.level[level].mode) {
1396 case RADEON_SURF_MODE_2D:
1397 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1398 break;
1399 case RADEON_SURF_MODE_1D:
1400 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1401 case RADEON_SURF_MODE_LINEAR:
1402 default:
1403 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1404 break;
1405 }
1406 tile_split = rtex->surface.tile_split;
1407 macro_aspect = rtex->surface.mtilea;
1408 bankw = rtex->surface.bankw;
1409 bankh = rtex->surface.bankh;
1410 tile_split = eg_tile_split(tile_split);
1411 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1412 bankw = eg_bank_wh(bankw);
1413 bankh = eg_bank_wh(bankh);
1414 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1415 offset >>= 8;
1416
1417 surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1418 S_028040_FORMAT(format) |
1419 S_028040_TILE_SPLIT(tile_split)|
1420 S_028040_NUM_BANKS(nbanks) |
1421 S_028040_BANK_WIDTH(bankw) |
1422 S_028040_BANK_HEIGHT(bankh) |
1423 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1424 if (rscreen->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1425 surf->db_depth_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1426 }
1427 surf->db_depth_base = offset;
1428 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1429 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1430 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1431 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1432
1433 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1434 uint64_t stencil_offset = rtex->surface.stencil_offset;
1435 unsigned stile_split = rtex->surface.stencil_tile_split;
1436
1437 stile_split = eg_tile_split(stile_split);
1438 stencil_offset += r600_resource_va(screen, surf->base.texture);
1439 stencil_offset += rtex->surface.level[level].offset / 4;
1440 stencil_offset >>= 8;
1441
1442 surf->db_stencil_base = stencil_offset;
1443 surf->db_stencil_info = 1 | S_028044_TILE_SPLIT(stile_split);
1444 } else {
1445 surf->db_stencil_base = offset;
1446 surf->db_stencil_info = 1;
1447 }
1448
1449 surf->depth_initialized = true;
1450 }
1451
1452 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1453 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1454 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1455 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1456 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1457
1458 static uint32_t evergreen_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1459 {
1460 /* 2xMSAA
1461 * There are two locations (-4, 4), (4, -4). */
1462 static uint32_t sample_locs_2x[] = {
1463 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1464 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1465 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1466 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1467 };
1468 static unsigned max_dist_2x = 4;
1469 /* 4xMSAA
1470 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1471 static uint32_t sample_locs_4x[] = {
1472 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1473 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1474 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1475 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1476 };
1477 static unsigned max_dist_4x = 6;
1478 /* 8xMSAA */
1479 static uint32_t sample_locs_8x[] = {
1480 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1481 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1482 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1483 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1484 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1485 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1486 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1487 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1488 };
1489 static unsigned max_dist_8x = 8;
1490 struct r600_context *rctx = (struct r600_context *)ctx;
1491 unsigned i;
1492
1493 switch (nsample) {
1494 case 2:
1495 for (i = 0; i < Elements(sample_locs_2x); i++) {
1496 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
1497 sample_locs_2x[i]);
1498 }
1499 return max_dist_2x;
1500 case 4:
1501 for (i = 0; i < Elements(sample_locs_4x); i++) {
1502 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
1503 sample_locs_4x[i]);
1504 }
1505 return max_dist_4x;
1506 case 8:
1507 for (i = 0; i < Elements(sample_locs_8x); i++) {
1508 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
1509 sample_locs_8x[i]);
1510 }
1511 return max_dist_8x;
1512 default:
1513 R600_ERR("Invalid nr_samples %i\n", nsample);
1514 return 0;
1515 }
1516 }
1517
1518 static uint32_t cayman_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1519 {
1520 /* 2xMSAA
1521 * There are two locations (-4, 4), (4, -4). */
1522 static uint32_t sample_locs_2x[] = {
1523 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1524 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1525 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1526 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1527 };
1528 static unsigned max_dist_2x = 4;
1529 /* 4xMSAA
1530 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1531 static uint32_t sample_locs_4x[] = {
1532 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1533 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1534 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1535 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1536 };
1537 static unsigned max_dist_4x = 6;
1538 /* 8xMSAA */
1539 static uint32_t sample_locs_8x[] = {
1540 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1541 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1542 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1543 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1544 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1545 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1546 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1547 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1548 };
1549 static unsigned max_dist_8x = 8;
1550 /* 16xMSAA */
1551 static uint32_t sample_locs_16x[] = {
1552 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1553 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1554 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1555 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1556 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1557 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1558 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1559 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1560 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1561 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1562 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1563 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1564 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1565 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1566 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1567 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1568 };
1569 static unsigned max_dist_16x = 8;
1570 struct r600_context *rctx = (struct r600_context *)ctx;
1571 uint32_t max_dist, num_regs, *sample_locs;
1572
1573 switch (nsample) {
1574 case 2:
1575 sample_locs = sample_locs_2x;
1576 num_regs = Elements(sample_locs_2x);
1577 max_dist = max_dist_2x;
1578 break;
1579 case 4:
1580 sample_locs = sample_locs_4x;
1581 num_regs = Elements(sample_locs_4x);
1582 max_dist = max_dist_4x;
1583 break;
1584 case 8:
1585 sample_locs = sample_locs_8x;
1586 num_regs = Elements(sample_locs_8x);
1587 max_dist = max_dist_8x;
1588 break;
1589 case 16:
1590 sample_locs = sample_locs_16x;
1591 num_regs = Elements(sample_locs_16x);
1592 max_dist = max_dist_16x;
1593 break;
1594 default:
1595 R600_ERR("Invalid nr_samples %i\n", nsample);
1596 return 0;
1597 }
1598
1599 r600_pipe_state_add_reg(rstate, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs[0]);
1600 r600_pipe_state_add_reg(rstate, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs[1]);
1601 r600_pipe_state_add_reg(rstate, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs[2]);
1602 r600_pipe_state_add_reg(rstate, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs[3]);
1603 if (num_regs <= 8) {
1604 r600_pipe_state_add_reg(rstate, CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs[4]);
1605 r600_pipe_state_add_reg(rstate, CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs[5]);
1606 r600_pipe_state_add_reg(rstate, CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs[6]);
1607 r600_pipe_state_add_reg(rstate, CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs[7]);
1608 }
1609 if (num_regs <= 16) {
1610 r600_pipe_state_add_reg(rstate, CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, sample_locs[8]);
1611 r600_pipe_state_add_reg(rstate, CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, sample_locs[9]);
1612 r600_pipe_state_add_reg(rstate, CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, sample_locs[10]);
1613 r600_pipe_state_add_reg(rstate, CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, sample_locs[11]);
1614 r600_pipe_state_add_reg(rstate, CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, sample_locs[12]);
1615 r600_pipe_state_add_reg(rstate, CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, sample_locs[13]);
1616 r600_pipe_state_add_reg(rstate, CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, sample_locs[14]);
1617 r600_pipe_state_add_reg(rstate, CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, sample_locs[15]);
1618 }
1619 return max_dist;
1620 }
1621
1622 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1623 const struct pipe_framebuffer_state *state)
1624 {
1625 struct r600_context *rctx = (struct r600_context *)ctx;
1626 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1627 struct r600_surface *surf;
1628 struct r600_resource *res;
1629 struct r600_texture *rtex;
1630 uint32_t tl, br, i, nr_samples, log_samples;
1631
1632 if (rstate == NULL)
1633 return;
1634
1635 if (rctx->framebuffer.nr_cbufs) {
1636 rctx->flags |= R600_CONTEXT_CB_FLUSH;
1637 }
1638 if (rctx->framebuffer.zsbuf) {
1639 rctx->flags |= R600_CONTEXT_DB_FLUSH;
1640 }
1641
1642 /* unreference old buffer and reference new one */
1643 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1644
1645 util_copy_framebuffer_state(&rctx->framebuffer, state);
1646
1647 /* Colorbuffers. */
1648 rctx->export_16bpc = true;
1649 rctx->nr_cbufs = state->nr_cbufs;
1650 rctx->cb0_is_integer = state->nr_cbufs &&
1651 util_format_is_pure_integer(state->cbufs[0]->format);
1652 rctx->compressed_cb_mask = 0;
1653
1654 for (i = 0; i < state->nr_cbufs; i++) {
1655 surf = (struct r600_surface*)state->cbufs[i];
1656 res = (struct r600_resource*)surf->base.texture;
1657 rtex = (struct r600_texture*)res;
1658
1659 if (!surf->color_initialized) {
1660 evergreen_init_color_surface(rctx, surf);
1661 }
1662
1663 if (!surf->export_16bpc) {
1664 rctx->export_16bpc = false;
1665 }
1666
1667 r600_pipe_state_add_reg_bo(rstate, R_028C60_CB_COLOR0_BASE + i * 0x3C,
1668 surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1669 r600_pipe_state_add_reg(rstate, R_028C78_CB_COLOR0_DIM + i * 0x3C,
1670 surf->cb_color_dim);
1671 r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1672 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1673 r600_pipe_state_add_reg(rstate, R_028C64_CB_COLOR0_PITCH + i * 0x3C,
1674 surf->cb_color_pitch);
1675 r600_pipe_state_add_reg(rstate, R_028C68_CB_COLOR0_SLICE + i * 0x3C,
1676 surf->cb_color_slice);
1677 r600_pipe_state_add_reg(rstate, R_028C6C_CB_COLOR0_VIEW + i * 0x3C,
1678 surf->cb_color_view);
1679 r600_pipe_state_add_reg_bo(rstate, R_028C74_CB_COLOR0_ATTRIB + i * 0x3C,
1680 surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
1681 r600_pipe_state_add_reg_bo(rstate, R_028C7C_CB_COLOR0_CMASK + i * 0x3c,
1682 surf->cb_color_cmask, res, RADEON_USAGE_READWRITE);
1683 r600_pipe_state_add_reg(rstate, R_028C80_CB_COLOR0_CMASK_SLICE + i * 0x3c,
1684 surf->cb_color_cmask_slice);
1685 r600_pipe_state_add_reg_bo(rstate, R_028C84_CB_COLOR0_FMASK + i * 0x3c,
1686 surf->cb_color_fmask, res, RADEON_USAGE_READWRITE);
1687 r600_pipe_state_add_reg(rstate, R_028C88_CB_COLOR0_FMASK_SLICE + i * 0x3c,
1688 surf->cb_color_fmask_slice);
1689
1690 /* Cayman can fetch from a compressed MSAA colorbuffer,
1691 * so it's pointless to track them. */
1692 if (rctx->chip_class != CAYMAN && rtex->fmask_size && rtex->cmask_size) {
1693 rctx->compressed_cb_mask |= 1 << i;
1694 }
1695 }
1696 /* set CB_COLOR1_INFO for possible dual-src blending */
1697 if (i == 1 && !((struct r600_texture*)res)->is_rat) {
1698 r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1699 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1700 i++;
1701 }
1702 for (; i < 8 ; i++) {
1703 r600_pipe_state_add_reg(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1704 }
1705
1706 /* Update alpha-test state dependencies.
1707 * Alpha-test is done on the first colorbuffer only. */
1708 if (state->nr_cbufs) {
1709 surf = (struct r600_surface*)state->cbufs[0];
1710 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1711 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1712 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1713 }
1714 if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
1715 rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
1716 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1717 }
1718 }
1719
1720 /* ZS buffer. */
1721 if (state->zsbuf) {
1722 surf = (struct r600_surface*)state->zsbuf;
1723 res = (struct r600_resource*)surf->base.texture;
1724
1725 if (!surf->depth_initialized) {
1726 evergreen_init_depth_surface(rctx, surf);
1727 }
1728
1729 r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE, surf->db_depth_base,
1730 res, RADEON_USAGE_READWRITE);
1731 r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base,
1732 res, RADEON_USAGE_READWRITE);
1733 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, surf->db_depth_view);
1734
1735 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base,
1736 res, RADEON_USAGE_READWRITE);
1737 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE, surf->db_stencil_base,
1738 res, RADEON_USAGE_READWRITE);
1739 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO, surf->db_stencil_info,
1740 res, RADEON_USAGE_READWRITE);
1741
1742 r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, surf->db_depth_info,
1743 res, RADEON_USAGE_READWRITE);
1744 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE, surf->db_depth_size);
1745 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, surf->db_depth_slice);
1746 }
1747
1748 /* Framebuffer dimensions. */
1749 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1750
1751 r600_pipe_state_add_reg(rstate,
1752 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1753 r600_pipe_state_add_reg(rstate,
1754 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1755
1756 /* Multisampling */
1757 if (state->nr_cbufs)
1758 nr_samples = state->cbufs[0]->texture->nr_samples;
1759 else if (state->zsbuf)
1760 nr_samples = state->zsbuf->texture->nr_samples;
1761 else
1762 nr_samples = 0;
1763
1764 if (nr_samples > 1) {
1765 unsigned line_cntl = S_028C00_LAST_PIXEL(1) |
1766 S_028C00_EXPAND_LINE_WIDTH(1);
1767 log_samples = util_logbase2(nr_samples);
1768
1769 if (rctx->chip_class == CAYMAN) {
1770 unsigned max_dist = cayman_set_ms_pos(ctx, rstate, nr_samples);
1771
1772 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, line_cntl);
1773 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1774 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1775 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
1776 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
1777 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA,
1778 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1779 S_028804_PS_ITER_SAMPLES(log_samples) |
1780 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1781 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
1782 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1783 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1784 } else {
1785 unsigned max_dist = evergreen_set_ms_pos(ctx, rstate, nr_samples);
1786
1787 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, line_cntl);
1788 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1789 S_028C04_MSAA_NUM_SAMPLES(log_samples) |
1790 S_028C04_MAX_SAMPLE_DIST(max_dist));
1791 }
1792 } else {
1793 log_samples = 0;
1794
1795 if (rctx->chip_class == CAYMAN) {
1796 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1797 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG, 0);
1798 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA,
1799 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1800 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1801
1802 } else {
1803 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1804 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
1805 }
1806 }
1807
1808 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1809 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1810 r600_context_pipe_state_set(rctx, rstate);
1811
1812 if (state->zsbuf) {
1813 evergreen_polygon_offset_update(rctx);
1814 }
1815
1816 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1817 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1818 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1819 }
1820
1821 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1822 rctx->alphatest_state.bypass = false;
1823 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1824 }
1825
1826 if (rctx->chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) {
1827 rctx->db_misc_state.log_samples = log_samples;
1828 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1829 }
1830 }
1831
1832 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1833 {
1834 struct radeon_winsys_cs *cs = rctx->cs;
1835 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1836 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1837 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1838
1839 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1840 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1841 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
1842 * will assure that the alpha-test will work even if there is
1843 * no colorbuffer bound. */
1844 r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1845 }
1846
1847 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1848 {
1849 struct radeon_winsys_cs *cs = rctx->cs;
1850 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1851 unsigned db_render_control = 0;
1852 unsigned db_count_control = 0;
1853 unsigned db_render_override =
1854 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1855 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1856 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1857
1858 if (a->occlusion_query_enabled) {
1859 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1860 if (rctx->chip_class == CAYMAN) {
1861 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1862 }
1863 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1864 }
1865
1866 if (a->flush_depthstencil_through_cb) {
1867 assert(a->copy_depth || a->copy_stencil);
1868
1869 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1870 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1871 S_028000_COPY_CENTROID(1) |
1872 S_028000_COPY_SAMPLE(a->copy_sample);
1873 }
1874
1875 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1876 r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1877 r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1878 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1879 }
1880
1881 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1882 struct r600_vertexbuf_state *state,
1883 unsigned resource_offset,
1884 unsigned pkt_flags)
1885 {
1886 struct radeon_winsys_cs *cs = rctx->cs;
1887 uint32_t dirty_mask = state->dirty_mask;
1888
1889 while (dirty_mask) {
1890 struct pipe_vertex_buffer *vb;
1891 struct r600_resource *rbuffer;
1892 uint64_t va;
1893 unsigned buffer_index = u_bit_scan(&dirty_mask);
1894
1895 vb = &state->vb[buffer_index];
1896 rbuffer = (struct r600_resource*)vb->buffer;
1897 assert(rbuffer);
1898
1899 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1900 va += vb->buffer_offset;
1901
1902 /* fetch resources start at index 992 */
1903 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1904 r600_write_value(cs, (resource_offset + buffer_index) * 8);
1905 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1906 r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1907 r600_write_value(cs, /* RESOURCEi_WORD2 */
1908 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1909 S_030008_STRIDE(vb->stride) |
1910 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1911 r600_write_value(cs, /* RESOURCEi_WORD3 */
1912 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1913 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1914 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1915 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1916 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1917 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1918 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1919 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1920
1921 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1922 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1923 }
1924 state->dirty_mask = 0;
1925 }
1926
1927 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1928 {
1929 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
1930 }
1931
1932 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1933 {
1934 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
1935 RADEON_CP_PACKET3_COMPUTE_MODE);
1936 }
1937
1938 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1939 struct r600_constbuf_state *state,
1940 unsigned buffer_id_base,
1941 unsigned reg_alu_constbuf_size,
1942 unsigned reg_alu_const_cache)
1943 {
1944 struct radeon_winsys_cs *cs = rctx->cs;
1945 uint32_t dirty_mask = state->dirty_mask;
1946
1947 while (dirty_mask) {
1948 struct pipe_constant_buffer *cb;
1949 struct r600_resource *rbuffer;
1950 uint64_t va;
1951 unsigned buffer_index = ffs(dirty_mask) - 1;
1952
1953 cb = &state->cb[buffer_index];
1954 rbuffer = (struct r600_resource*)cb->buffer;
1955 assert(rbuffer);
1956
1957 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1958 va += cb->buffer_offset;
1959
1960 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1961 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1962 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
1963
1964 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1965 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1966
1967 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1968 r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
1969 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1970 r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1971 r600_write_value(cs, /* RESOURCEi_WORD2 */
1972 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1973 S_030008_STRIDE(16) |
1974 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1975 r600_write_value(cs, /* RESOURCEi_WORD3 */
1976 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1977 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1978 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1979 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1980 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1981 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1982 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1983 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1984
1985 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1986 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1987
1988 dirty_mask &= ~(1 << buffer_index);
1989 }
1990 state->dirty_mask = 0;
1991 }
1992
1993 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1994 {
1995 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 176,
1996 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1997 R_028980_ALU_CONST_CACHE_VS_0);
1998 }
1999
2000 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2001 {
2002 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
2003 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2004 R_0289C0_ALU_CONST_CACHE_GS_0);
2005 }
2006
2007 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2008 {
2009 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
2010 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2011 R_028940_ALU_CONST_CACHE_PS_0);
2012 }
2013
2014 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2015 struct r600_samplerview_state *state,
2016 unsigned resource_id_base)
2017 {
2018 struct radeon_winsys_cs *cs = rctx->cs;
2019 uint32_t dirty_mask = state->dirty_mask;
2020
2021 while (dirty_mask) {
2022 struct r600_pipe_sampler_view *rview;
2023 unsigned resource_index = u_bit_scan(&dirty_mask);
2024 unsigned reloc;
2025
2026 rview = state->views[resource_index];
2027 assert(rview);
2028
2029 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2030 r600_write_value(cs, (resource_id_base + resource_index) * 8);
2031 r600_write_array(cs, 8, rview->tex_resource_words);
2032
2033 /* XXX The kernel needs two relocations. This is stupid. */
2034 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
2035 RADEON_USAGE_READ);
2036 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2037 r600_write_value(cs, reloc);
2038 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2039 r600_write_value(cs, reloc);
2040 }
2041 state->dirty_mask = 0;
2042 }
2043
2044 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2045 {
2046 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 176 + R600_MAX_CONST_BUFFERS);
2047 }
2048
2049 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2050 {
2051 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2052 }
2053
2054 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2055 {
2056 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2057 }
2058
2059 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2060 struct r600_textures_info *texinfo,
2061 unsigned resource_id_base,
2062 unsigned border_index_reg)
2063 {
2064 struct radeon_winsys_cs *cs = rctx->cs;
2065 uint32_t dirty_mask = texinfo->states.dirty_mask;
2066
2067 while (dirty_mask) {
2068 struct r600_pipe_sampler_state *rstate;
2069 unsigned i = u_bit_scan(&dirty_mask);
2070
2071 rstate = texinfo->states.states[i];
2072 assert(rstate);
2073
2074 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2075 r600_write_value(cs, (resource_id_base + i) * 3);
2076 r600_write_array(cs, 3, rstate->tex_sampler_words);
2077
2078 if (rstate->border_color_use) {
2079 r600_write_config_reg_seq(cs, border_index_reg, 5);
2080 r600_write_value(cs, i);
2081 r600_write_array(cs, 4, rstate->border_color);
2082 }
2083 }
2084 texinfo->states.dirty_mask = 0;
2085 }
2086
2087 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2088 {
2089 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
2090 }
2091
2092 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2093 {
2094 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX);
2095 }
2096
2097 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2098 {
2099 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
2100 }
2101
2102 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2103 {
2104 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2105 uint8_t mask = s->sample_mask;
2106
2107 r600_write_context_reg(rctx->cs, R_028C3C_PA_SC_AA_MASK,
2108 mask | (mask << 8) | (mask << 16) | (mask << 24));
2109 }
2110
2111 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2112 {
2113 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2114 struct radeon_winsys_cs *cs = rctx->cs;
2115 uint16_t mask = s->sample_mask;
2116
2117 r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2118 r600_write_value(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2119 r600_write_value(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2120 }
2121
2122 void evergreen_init_state_functions(struct r600_context *rctx)
2123 {
2124 unsigned id = 4;
2125
2126 /* !!!
2127 * To avoid GPU lockup registers must be emited in a specific order
2128 * (no kidding ...). The order below is important and have been
2129 * partialy infered from analyzing fglrx command stream.
2130 *
2131 * Don't reorder atom without carefully checking the effect (GPU lockup
2132 * or piglit regression).
2133 * !!!
2134 */
2135
2136 /* shader const */
2137 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
2138 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
2139 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
2140 /* shader program */
2141 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
2142 /* sampler */
2143 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
2144 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
2145 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
2146 /* resources */
2147 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
2148 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
2149 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
2150 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
2151 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
2152
2153 if (rctx->chip_class == EVERGREEN) {
2154 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
2155 } else {
2156 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
2157 }
2158 rctx->sample_mask.sample_mask = ~0;
2159
2160 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2161 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2162 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 0);
2163 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
2164 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 7);
2165 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2166 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2167
2168 rctx->context.create_blend_state = evergreen_create_blend_state;
2169 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
2170 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
2171 rctx->context.create_sampler_state = evergreen_create_sampler_state;
2172 rctx->context.create_sampler_view = evergreen_create_sampler_view;
2173 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
2174 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
2175 rctx->context.set_scissor_state = evergreen_set_scissor_state;
2176 evergreen_init_compute_state_functions(rctx);
2177 }
2178
2179 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2180 {
2181 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2182
2183 r600_init_command_buffer(rctx, cb, 0, 256);
2184
2185 /* This must be first. */
2186 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2187 r600_store_value(cb, 0x80000000);
2188 r600_store_value(cb, 0x80000000);
2189
2190 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2191 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2192 /* always set the temp clauses */
2193 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2194
2195 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2196 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2197 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2198
2199 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2200
2201 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2202
2203 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2204 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2205 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2206 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2207 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2208 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2209 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2210 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2211 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2212 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2213 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2214 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2215 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2216 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2217
2218 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2219 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2220 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2221
2222 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2223 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2224 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2225
2226 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2227
2228 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2229
2230 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2231 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2232 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2233
2234 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
2235 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2236 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2237
2238 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2239 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2240 r600_store_value(cb, 0);
2241 r600_store_value(cb, 0);
2242 r600_store_value(cb, 0);
2243 r600_store_value(cb, 0);
2244 r600_store_value(cb, 0);
2245 r600_store_value(cb, 0);
2246 r600_store_value(cb, 0);
2247 r600_store_value(cb, 0);
2248 r600_store_value(cb, 0);
2249 r600_store_value(cb, 0);
2250 r600_store_value(cb, 0);
2251 r600_store_value(cb, 0);
2252 r600_store_value(cb, 0);
2253 r600_store_value(cb, 0);
2254 r600_store_value(cb, 0);
2255 r600_store_value(cb, 0);
2256 r600_store_value(cb, 0);
2257 r600_store_value(cb, 0);
2258 r600_store_value(cb, 0);
2259 r600_store_value(cb, 0);
2260 r600_store_value(cb, 0);
2261 r600_store_value(cb, 0);
2262 r600_store_value(cb, 0);
2263 r600_store_value(cb, 0);
2264 r600_store_value(cb, 0);
2265 r600_store_value(cb, 0);
2266 r600_store_value(cb, 0);
2267 r600_store_value(cb, 0);
2268 r600_store_value(cb, 0);
2269 r600_store_value(cb, 0);
2270 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2271 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2272 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2273
2274 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2275
2276 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2277 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2278 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2279
2280 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2281
2282 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2283 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2284 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2285 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2286
2287 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2288 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2289
2290 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2291 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2292 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2293
2294 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2295 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2296 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2297
2298 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2299 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2300 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2301 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2302 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2303
2304 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2305 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2306 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2307
2308 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2309 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2310 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2311
2312 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2313 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2314 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2315
2316 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2317 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2318 if (rctx->screen->has_streamout) {
2319 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2320 }
2321
2322 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2323 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2324 }
2325
2326 void evergreen_init_common_regs(struct r600_command_buffer *cb,
2327 enum chip_class ctx_chip_class,
2328 enum radeon_family ctx_family,
2329 int ctx_drm_minor)
2330 {
2331 int ps_prio;
2332 int vs_prio;
2333 int gs_prio;
2334 int es_prio;
2335
2336 int hs_prio;
2337 int cs_prio;
2338 int ls_prio;
2339
2340 int num_ps_gprs;
2341 int num_vs_gprs;
2342 int num_gs_gprs;
2343 int num_es_gprs;
2344 int num_hs_gprs;
2345 int num_ls_gprs;
2346 int num_temp_gprs;
2347
2348 unsigned tmp;
2349
2350 ps_prio = 0;
2351 vs_prio = 1;
2352 gs_prio = 2;
2353 es_prio = 3;
2354 hs_prio = 0;
2355 ls_prio = 0;
2356 cs_prio = 0;
2357
2358 switch (ctx_family) {
2359 case CHIP_CEDAR:
2360 default:
2361 num_ps_gprs = 93;
2362 num_vs_gprs = 46;
2363 num_temp_gprs = 4;
2364 num_gs_gprs = 31;
2365 num_es_gprs = 31;
2366 num_hs_gprs = 23;
2367 num_ls_gprs = 23;
2368 break;
2369 case CHIP_REDWOOD:
2370 num_ps_gprs = 93;
2371 num_vs_gprs = 46;
2372 num_temp_gprs = 4;
2373 num_gs_gprs = 31;
2374 num_es_gprs = 31;
2375 num_hs_gprs = 23;
2376 num_ls_gprs = 23;
2377 break;
2378 case CHIP_JUNIPER:
2379 num_ps_gprs = 93;
2380 num_vs_gprs = 46;
2381 num_temp_gprs = 4;
2382 num_gs_gprs = 31;
2383 num_es_gprs = 31;
2384 num_hs_gprs = 23;
2385 num_ls_gprs = 23;
2386 break;
2387 case CHIP_CYPRESS:
2388 case CHIP_HEMLOCK:
2389 num_ps_gprs = 93;
2390 num_vs_gprs = 46;
2391 num_temp_gprs = 4;
2392 num_gs_gprs = 31;
2393 num_es_gprs = 31;
2394 num_hs_gprs = 23;
2395 num_ls_gprs = 23;
2396 break;
2397 case CHIP_PALM:
2398 num_ps_gprs = 93;
2399 num_vs_gprs = 46;
2400 num_temp_gprs = 4;
2401 num_gs_gprs = 31;
2402 num_es_gprs = 31;
2403 num_hs_gprs = 23;
2404 num_ls_gprs = 23;
2405 break;
2406 case CHIP_SUMO:
2407 num_ps_gprs = 93;
2408 num_vs_gprs = 46;
2409 num_temp_gprs = 4;
2410 num_gs_gprs = 31;
2411 num_es_gprs = 31;
2412 num_hs_gprs = 23;
2413 num_ls_gprs = 23;
2414 break;
2415 case CHIP_SUMO2:
2416 num_ps_gprs = 93;
2417 num_vs_gprs = 46;
2418 num_temp_gprs = 4;
2419 num_gs_gprs = 31;
2420 num_es_gprs = 31;
2421 num_hs_gprs = 23;
2422 num_ls_gprs = 23;
2423 break;
2424 case CHIP_BARTS:
2425 num_ps_gprs = 93;
2426 num_vs_gprs = 46;
2427 num_temp_gprs = 4;
2428 num_gs_gprs = 31;
2429 num_es_gprs = 31;
2430 num_hs_gprs = 23;
2431 num_ls_gprs = 23;
2432 break;
2433 case CHIP_TURKS:
2434 num_ps_gprs = 93;
2435 num_vs_gprs = 46;
2436 num_temp_gprs = 4;
2437 num_gs_gprs = 31;
2438 num_es_gprs = 31;
2439 num_hs_gprs = 23;
2440 num_ls_gprs = 23;
2441 break;
2442 case CHIP_CAICOS:
2443 num_ps_gprs = 93;
2444 num_vs_gprs = 46;
2445 num_temp_gprs = 4;
2446 num_gs_gprs = 31;
2447 num_es_gprs = 31;
2448 num_hs_gprs = 23;
2449 num_ls_gprs = 23;
2450 break;
2451 }
2452
2453 tmp = 0;
2454 switch (ctx_family) {
2455 case CHIP_CEDAR:
2456 case CHIP_PALM:
2457 case CHIP_SUMO:
2458 case CHIP_SUMO2:
2459 case CHIP_CAICOS:
2460 break;
2461 default:
2462 tmp |= S_008C00_VC_ENABLE(1);
2463 break;
2464 }
2465 tmp |= S_008C00_EXPORT_SRC_C(1);
2466 tmp |= S_008C00_CS_PRIO(cs_prio);
2467 tmp |= S_008C00_LS_PRIO(ls_prio);
2468 tmp |= S_008C00_HS_PRIO(hs_prio);
2469 tmp |= S_008C00_PS_PRIO(ps_prio);
2470 tmp |= S_008C00_VS_PRIO(vs_prio);
2471 tmp |= S_008C00_GS_PRIO(gs_prio);
2472 tmp |= S_008C00_ES_PRIO(es_prio);
2473
2474 /* enable dynamic GPR resource management */
2475 if (ctx_drm_minor >= 7) {
2476 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2477 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2478 /* always set temp clauses */
2479 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2480 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2481 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2482 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2483 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2484 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2485 S_028838_PS_GPRS(0x1e) |
2486 S_028838_VS_GPRS(0x1e) |
2487 S_028838_GS_GPRS(0x1e) |
2488 S_028838_ES_GPRS(0x1e) |
2489 S_028838_HS_GPRS(0x1e) |
2490 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2491 } else {
2492 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2493 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2494
2495 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2496 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2497 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2498 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2499
2500 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2501 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2502 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2503
2504 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2505 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2506 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2507 }
2508
2509 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2510 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2511
2512 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2513
2514 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2515 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2516 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2517
2518 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2519
2520 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2521 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2522 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2523
2524 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2525 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2526 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2527 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2528
2529 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2530 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2531
2532 /* to avoid GPU doing any preloading of constant from random address */
2533 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2534 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2535 r600_store_value(cb, 0);
2536 r600_store_value(cb, 0);
2537 r600_store_value(cb, 0);
2538 r600_store_value(cb, 0);
2539 r600_store_value(cb, 0);
2540 r600_store_value(cb, 0);
2541 r600_store_value(cb, 0);
2542 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2543 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2544 r600_store_value(cb, 0);
2545 r600_store_value(cb, 0);
2546 r600_store_value(cb, 0);
2547 r600_store_value(cb, 0);
2548 r600_store_value(cb, 0);
2549 r600_store_value(cb, 0);
2550 r600_store_value(cb, 0);
2551
2552 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2553
2554 return;
2555 }
2556
2557 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2558 {
2559 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2560 int num_ps_threads;
2561 int num_vs_threads;
2562 int num_gs_threads;
2563 int num_es_threads;
2564 int num_hs_threads;
2565 int num_ls_threads;
2566
2567 int num_ps_stack_entries;
2568 int num_vs_stack_entries;
2569 int num_gs_stack_entries;
2570 int num_es_stack_entries;
2571 int num_hs_stack_entries;
2572 int num_ls_stack_entries;
2573 enum radeon_family family;
2574 unsigned tmp;
2575
2576 if (rctx->chip_class == CAYMAN) {
2577 cayman_init_atom_start_cs(rctx);
2578 return;
2579 }
2580
2581 r600_init_command_buffer(rctx, cb, 0, 256);
2582
2583 /* This must be first. */
2584 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2585 r600_store_value(cb, 0x80000000);
2586 r600_store_value(cb, 0x80000000);
2587
2588 evergreen_init_common_regs(cb, rctx->chip_class
2589 , rctx->family, rctx->screen->info.drm_minor);
2590
2591 family = rctx->family;
2592 switch (family) {
2593 case CHIP_CEDAR:
2594 default:
2595 num_ps_threads = 96;
2596 num_vs_threads = 16;
2597 num_gs_threads = 16;
2598 num_es_threads = 16;
2599 num_hs_threads = 16;
2600 num_ls_threads = 16;
2601 num_ps_stack_entries = 42;
2602 num_vs_stack_entries = 42;
2603 num_gs_stack_entries = 42;
2604 num_es_stack_entries = 42;
2605 num_hs_stack_entries = 42;
2606 num_ls_stack_entries = 42;
2607 break;
2608 case CHIP_REDWOOD:
2609 num_ps_threads = 128;
2610 num_vs_threads = 20;
2611 num_gs_threads = 20;
2612 num_es_threads = 20;
2613 num_hs_threads = 20;
2614 num_ls_threads = 20;
2615 num_ps_stack_entries = 42;
2616 num_vs_stack_entries = 42;
2617 num_gs_stack_entries = 42;
2618 num_es_stack_entries = 42;
2619 num_hs_stack_entries = 42;
2620 num_ls_stack_entries = 42;
2621 break;
2622 case CHIP_JUNIPER:
2623 num_ps_threads = 128;
2624 num_vs_threads = 20;
2625 num_gs_threads = 20;
2626 num_es_threads = 20;
2627 num_hs_threads = 20;
2628 num_ls_threads = 20;
2629 num_ps_stack_entries = 85;
2630 num_vs_stack_entries = 85;
2631 num_gs_stack_entries = 85;
2632 num_es_stack_entries = 85;
2633 num_hs_stack_entries = 85;
2634 num_ls_stack_entries = 85;
2635 break;
2636 case CHIP_CYPRESS:
2637 case CHIP_HEMLOCK:
2638 num_ps_threads = 128;
2639 num_vs_threads = 20;
2640 num_gs_threads = 20;
2641 num_es_threads = 20;
2642 num_hs_threads = 20;
2643 num_ls_threads = 20;
2644 num_ps_stack_entries = 85;
2645 num_vs_stack_entries = 85;
2646 num_gs_stack_entries = 85;
2647 num_es_stack_entries = 85;
2648 num_hs_stack_entries = 85;
2649 num_ls_stack_entries = 85;
2650 break;
2651 case CHIP_PALM:
2652 num_ps_threads = 96;
2653 num_vs_threads = 16;
2654 num_gs_threads = 16;
2655 num_es_threads = 16;
2656 num_hs_threads = 16;
2657 num_ls_threads = 16;
2658 num_ps_stack_entries = 42;
2659 num_vs_stack_entries = 42;
2660 num_gs_stack_entries = 42;
2661 num_es_stack_entries = 42;
2662 num_hs_stack_entries = 42;
2663 num_ls_stack_entries = 42;
2664 break;
2665 case CHIP_SUMO:
2666 num_ps_threads = 96;
2667 num_vs_threads = 25;
2668 num_gs_threads = 25;
2669 num_es_threads = 25;
2670 num_hs_threads = 25;
2671 num_ls_threads = 25;
2672 num_ps_stack_entries = 42;
2673 num_vs_stack_entries = 42;
2674 num_gs_stack_entries = 42;
2675 num_es_stack_entries = 42;
2676 num_hs_stack_entries = 42;
2677 num_ls_stack_entries = 42;
2678 break;
2679 case CHIP_SUMO2:
2680 num_ps_threads = 96;
2681 num_vs_threads = 25;
2682 num_gs_threads = 25;
2683 num_es_threads = 25;
2684 num_hs_threads = 25;
2685 num_ls_threads = 25;
2686 num_ps_stack_entries = 85;
2687 num_vs_stack_entries = 85;
2688 num_gs_stack_entries = 85;
2689 num_es_stack_entries = 85;
2690 num_hs_stack_entries = 85;
2691 num_ls_stack_entries = 85;
2692 break;
2693 case CHIP_BARTS:
2694 num_ps_threads = 128;
2695 num_vs_threads = 20;
2696 num_gs_threads = 20;
2697 num_es_threads = 20;
2698 num_hs_threads = 20;
2699 num_ls_threads = 20;
2700 num_ps_stack_entries = 85;
2701 num_vs_stack_entries = 85;
2702 num_gs_stack_entries = 85;
2703 num_es_stack_entries = 85;
2704 num_hs_stack_entries = 85;
2705 num_ls_stack_entries = 85;
2706 break;
2707 case CHIP_TURKS:
2708 num_ps_threads = 128;
2709 num_vs_threads = 20;
2710 num_gs_threads = 20;
2711 num_es_threads = 20;
2712 num_hs_threads = 20;
2713 num_ls_threads = 20;
2714 num_ps_stack_entries = 42;
2715 num_vs_stack_entries = 42;
2716 num_gs_stack_entries = 42;
2717 num_es_stack_entries = 42;
2718 num_hs_stack_entries = 42;
2719 num_ls_stack_entries = 42;
2720 break;
2721 case CHIP_CAICOS:
2722 num_ps_threads = 128;
2723 num_vs_threads = 10;
2724 num_gs_threads = 10;
2725 num_es_threads = 10;
2726 num_hs_threads = 10;
2727 num_ls_threads = 10;
2728 num_ps_stack_entries = 42;
2729 num_vs_stack_entries = 42;
2730 num_gs_stack_entries = 42;
2731 num_es_stack_entries = 42;
2732 num_hs_stack_entries = 42;
2733 num_ls_stack_entries = 42;
2734 break;
2735 }
2736
2737 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2738 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2739 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2740 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2741
2742 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2743 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2744
2745 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2746 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2747 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2748
2749 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2750 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2751 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2752
2753 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2754 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2755 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2756
2757 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2758 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2759 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2760
2761 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2762 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2763
2764 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2765 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2766 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2767 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2768 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2769 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2770 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2771
2772 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2773 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2774 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2775 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2776 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2777
2778 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2779 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2780 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2781 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2782 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2783 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2784 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2785 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2786 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2787 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2788 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2789 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2790 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2791 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2792
2793 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2794 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2795 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2796
2797 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2798
2799 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2800 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2801 r600_store_value(cb, 0);
2802 r600_store_value(cb, 0);
2803 r600_store_value(cb, 0);
2804 r600_store_value(cb, 0);
2805 r600_store_value(cb, 0);
2806 r600_store_value(cb, 0);
2807 r600_store_value(cb, 0);
2808 r600_store_value(cb, 0);
2809 r600_store_value(cb, 0);
2810 r600_store_value(cb, 0);
2811 r600_store_value(cb, 0);
2812 r600_store_value(cb, 0);
2813 r600_store_value(cb, 0);
2814 r600_store_value(cb, 0);
2815 r600_store_value(cb, 0);
2816 r600_store_value(cb, 0);
2817 r600_store_value(cb, 0);
2818 r600_store_value(cb, 0);
2819 r600_store_value(cb, 0);
2820 r600_store_value(cb, 0);
2821 r600_store_value(cb, 0);
2822 r600_store_value(cb, 0);
2823 r600_store_value(cb, 0);
2824 r600_store_value(cb, 0);
2825 r600_store_value(cb, 0);
2826 r600_store_value(cb, 0);
2827 r600_store_value(cb, 0);
2828 r600_store_value(cb, 0);
2829 r600_store_value(cb, 0);
2830 r600_store_value(cb, 0);
2831 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2832 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2833 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2834
2835 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2836
2837 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2838 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2839 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2840
2841 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2842 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2843
2844 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2845 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2846 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2847
2848 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2849 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2850 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2851 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2852
2853 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2854 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2855 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2856 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2857 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2858
2859 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2860 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2861 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2862
2863 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2864 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2865 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2866
2867 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2868
2869 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2870 if (rctx->screen->has_streamout) {
2871 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2872 }
2873
2874 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2875 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2876 }
2877
2878 void evergreen_polygon_offset_update(struct r600_context *rctx)
2879 {
2880 struct r600_pipe_state state;
2881
2882 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2883 state.nregs = 0;
2884 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2885 float offset_units = rctx->rasterizer->offset_units;
2886 unsigned offset_db_fmt_cntl = 0, depth;
2887
2888 switch (rctx->framebuffer.zsbuf->format) {
2889 case PIPE_FORMAT_Z24X8_UNORM:
2890 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2891 depth = -24;
2892 offset_units *= 2.0f;
2893 break;
2894 case PIPE_FORMAT_Z32_FLOAT:
2895 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2896 depth = -23;
2897 offset_units *= 1.0f;
2898 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2899 break;
2900 case PIPE_FORMAT_Z16_UNORM:
2901 depth = -16;
2902 offset_units *= 4.0f;
2903 break;
2904 default:
2905 return;
2906 }
2907 /* XXX some of those reg can be computed with cso */
2908 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2909 r600_pipe_state_add_reg(&state,
2910 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2911 fui(rctx->rasterizer->offset_scale));
2912 r600_pipe_state_add_reg(&state,
2913 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2914 fui(offset_units));
2915 r600_pipe_state_add_reg(&state,
2916 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2917 fui(rctx->rasterizer->offset_scale));
2918 r600_pipe_state_add_reg(&state,
2919 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2920 fui(offset_units));
2921 r600_pipe_state_add_reg(&state,
2922 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2923 offset_db_fmt_cntl);
2924 r600_context_pipe_state_set(rctx, &state);
2925 }
2926 }
2927
2928 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2929 {
2930 struct r600_context *rctx = (struct r600_context *)ctx;
2931 struct r600_pipe_state *rstate = &shader->rstate;
2932 struct r600_shader *rshader = &shader->shader;
2933 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2934 int pos_index = -1, face_index = -1;
2935 int ninterp = 0;
2936 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2937 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2938 unsigned z_export = 0, stencil_export = 0;
2939
2940 rstate->nregs = 0;
2941
2942 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2943 for (i = 0; i < rshader->ninput; i++) {
2944 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2945 POSITION goes via GPRs from the SC so isn't counted */
2946 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2947 pos_index = i;
2948 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2949 face_index = i;
2950 else {
2951 ninterp++;
2952 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2953 have_linear = TRUE;
2954 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2955 have_perspective = TRUE;
2956 if (rshader->input[i].centroid)
2957 have_centroid = TRUE;
2958 }
2959
2960 sid = rshader->input[i].spi_sid;
2961
2962 if (sid) {
2963
2964 tmp = S_028644_SEMANTIC(sid);
2965
2966 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2967 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2968 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2969 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2970 tmp |= S_028644_FLAT_SHADE(1);
2971 }
2972
2973 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2974 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2975 tmp |= S_028644_PT_SPRITE_TEX(1);
2976 }
2977
2978 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2979 tmp);
2980
2981 idx++;
2982 }
2983 }
2984
2985 for (i = 0; i < rshader->noutput; i++) {
2986 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2987 z_export = 1;
2988 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2989 stencil_export = 1;
2990 }
2991 if (rshader->uses_kill)
2992 db_shader_control |= S_02880C_KILL_ENABLE(1);
2993
2994 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2995 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
2996
2997 exports_ps = 0;
2998 for (i = 0; i < rshader->noutput; i++) {
2999 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3000 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3001 exports_ps |= 1;
3002 }
3003
3004 num_cout = rshader->nr_ps_color_exports;
3005
3006 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3007 if (!exports_ps) {
3008 /* always at least export 1 component per pixel */
3009 exports_ps = 2;
3010 }
3011 shader->nr_ps_color_outputs = num_cout;
3012 if (ninterp == 0) {
3013 ninterp = 1;
3014 have_perspective = TRUE;
3015 }
3016
3017 if (!have_perspective && !have_linear)
3018 have_perspective = TRUE;
3019
3020 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3021 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3022 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3023 spi_input_z = 0;
3024 if (pos_index != -1) {
3025 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3026 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
3027 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3028 spi_input_z |= 1;
3029 }
3030
3031 spi_ps_in_control_1 = 0;
3032 if (face_index != -1) {
3033 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3034 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3035 }
3036
3037 spi_baryc_cntl = 0;
3038 if (have_perspective)
3039 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
3040 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
3041 if (have_linear)
3042 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
3043 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
3044
3045 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
3046 spi_ps_in_control_0);
3047 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
3048 spi_ps_in_control_1);
3049 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
3050 0);
3051 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
3052 r600_pipe_state_add_reg(rstate,
3053 R_0286E0_SPI_BARYC_CNTL,
3054 spi_baryc_cntl);
3055
3056 r600_pipe_state_add_reg_bo(rstate,
3057 R_028840_SQ_PGM_START_PS,
3058 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3059 shader->bo, RADEON_USAGE_READ);
3060 r600_pipe_state_add_reg(rstate,
3061 R_028844_SQ_PGM_RESOURCES_PS,
3062 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3063 S_028844_PRIME_CACHE_ON_DRAW(1) |
3064 S_028844_STACK_SIZE(rshader->bc.nstack));
3065 r600_pipe_state_add_reg(rstate,
3066 R_02884C_SQ_PGM_EXPORTS_PS,
3067 exports_ps);
3068
3069 shader->db_shader_control = db_shader_control;
3070 shader->ps_depth_export = z_export | stencil_export;
3071
3072 shader->sprite_coord_enable = rctx->sprite_coord_enable;
3073 if (rctx->rasterizer)
3074 shader->flatshade = rctx->rasterizer->flatshade;
3075 }
3076
3077 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3078 {
3079 struct r600_context *rctx = (struct r600_context *)ctx;
3080 struct r600_pipe_state *rstate = &shader->rstate;
3081 struct r600_shader *rshader = &shader->shader;
3082 unsigned spi_vs_out_id[10] = {};
3083 unsigned i, tmp, nparams = 0;
3084
3085 /* clear previous register */
3086 rstate->nregs = 0;
3087
3088 for (i = 0; i < rshader->noutput; i++) {
3089 if (rshader->output[i].spi_sid) {
3090 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3091 spi_vs_out_id[nparams / 4] |= tmp;
3092 nparams++;
3093 }
3094 }
3095
3096 for (i = 0; i < 10; i++) {
3097 r600_pipe_state_add_reg(rstate,
3098 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
3099 spi_vs_out_id[i]);
3100 }
3101
3102 /* Certain attributes (position, psize, etc.) don't count as params.
3103 * VS is required to export at least one param and r600_shader_from_tgsi()
3104 * takes care of adding a dummy export.
3105 */
3106 if (nparams < 1)
3107 nparams = 1;
3108
3109 r600_pipe_state_add_reg(rstate,
3110 R_0286C4_SPI_VS_OUT_CONFIG,
3111 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3112 r600_pipe_state_add_reg(rstate,
3113 R_028860_SQ_PGM_RESOURCES_VS,
3114 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3115 S_028860_STACK_SIZE(rshader->bc.nstack));
3116 r600_pipe_state_add_reg_bo(rstate,
3117 R_02885C_SQ_PGM_START_VS,
3118 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3119 shader->bo, RADEON_USAGE_READ);
3120
3121 shader->pa_cl_vs_out_cntl =
3122 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3123 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3124 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3125 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
3126 }
3127
3128 void evergreen_fetch_shader(struct pipe_context *ctx,
3129 struct r600_vertex_element *ve)
3130 {
3131 struct r600_context *rctx = (struct r600_context *)ctx;
3132 struct r600_pipe_state *rstate = &ve->rstate;
3133 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
3134 rstate->nregs = 0;
3135 r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
3136 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
3137 ve->fetch_shader, RADEON_USAGE_READ);
3138 }
3139
3140 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3141 {
3142 struct pipe_blend_state blend;
3143 struct r600_pipe_state *rstate;
3144
3145 memset(&blend, 0, sizeof(blend));
3146 blend.independent_blend_enable = true;
3147 blend.rt[0].colormask = 0xf;
3148 rstate = evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_RESOLVE);
3149 return rstate;
3150 }
3151
3152 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3153 {
3154 struct pipe_blend_state blend;
3155 struct r600_pipe_state *rstate;
3156
3157 memset(&blend, 0, sizeof(blend));
3158 blend.independent_blend_enable = true;
3159 blend.rt[0].colormask = 0xf;
3160 rstate = evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_DECOMPRESS);
3161 return rstate;
3162 }
3163
3164 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3165 {
3166 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3167
3168 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
3169 }
3170
3171 void evergreen_update_dual_export_state(struct r600_context * rctx)
3172 {
3173 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
3174 !rctx->ps_shader->current->ps_depth_export;
3175
3176 unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
3177 V_02880C_EXPORT_DB_FULL;
3178
3179 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
3180 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3181 S_02880C_DB_SOURCE_FORMAT(db_source_format) |
3182 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->cb0_is_integer);
3183
3184 if (db_shader_control != rctx->db_shader_control) {
3185 struct r600_pipe_state rstate;
3186
3187 rctx->db_shader_control = db_shader_control;
3188
3189 rstate.nregs = 0;
3190 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
3191 r600_context_pipe_state_set(rctx, &rstate);
3192 }
3193 }