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r600g: merge more of the common r600/evergreen state handling
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "eg_state_inlines.h"
50
51 static void evergreen_set_blend_color(struct pipe_context *ctx,
52 const struct pipe_blend_color *state)
53 {
54 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
55 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
56
57 if (rstate == NULL)
58 return;
59
60 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
61 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
62 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
63 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
65
66 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
67 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
68 r600_context_pipe_state_set(&rctx->ctx, rstate);
69 }
70
71 static void *evergreen_create_blend_state(struct pipe_context *ctx,
72 const struct pipe_blend_state *state)
73 {
74 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
75 struct r600_pipe_state *rstate;
76 u32 color_control, target_mask;
77 /* FIXME there is more then 8 framebuffer */
78 unsigned blend_cntl[8];
79
80 if (blend == NULL) {
81 return NULL;
82 }
83 rstate = &blend->rstate;
84
85 rstate->id = R600_PIPE_STATE_BLEND;
86
87 target_mask = 0;
88 color_control = S_028808_MODE(1);
89 if (state->logicop_enable) {
90 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
91 } else {
92 color_control |= (0xcc << 16);
93 }
94 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
95 if (state->independent_blend_enable) {
96 for (int i = 0; i < 8; i++) {
97 target_mask |= (state->rt[i].colormask << (4 * i));
98 }
99 } else {
100 for (int i = 0; i < 8; i++) {
101 target_mask |= (state->rt[0].colormask << (4 * i));
102 }
103 }
104 blend->cb_target_mask = target_mask;
105 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
106 color_control, 0xFFFFFFFF, NULL);
107 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
108
109 for (int i = 0; i < 8; i++) {
110 unsigned eqRGB = state->rt[i].rgb_func;
111 unsigned srcRGB = state->rt[i].rgb_src_factor;
112 unsigned dstRGB = state->rt[i].rgb_dst_factor;
113 unsigned eqA = state->rt[i].alpha_func;
114 unsigned srcA = state->rt[i].alpha_src_factor;
115 unsigned dstA = state->rt[i].alpha_dst_factor;
116
117 blend_cntl[i] = 0;
118 if (!state->rt[i].blend_enable)
119 continue;
120
121 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
122 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
123 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
124 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
125
126 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
127 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
128 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
129 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
130 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
131 }
132 }
133 for (int i = 0; i < 8; i++) {
134 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
135 }
136
137 return rstate;
138 }
139
140 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
141 const struct pipe_depth_stencil_alpha_state *state)
142 {
143 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
144 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
145 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
146
147 if (rstate == NULL) {
148 return NULL;
149 }
150
151 rstate->id = R600_PIPE_STATE_DSA;
152 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
153 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
154 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
155 * be set if shader use texkill instruction
156 */
157 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
158 stencil_ref_mask = 0;
159 stencil_ref_mask_bf = 0;
160 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
161 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
162 S_028800_ZFUNC(state->depth.func);
163
164 /* stencil */
165 if (state->stencil[0].enabled) {
166 db_depth_control |= S_028800_STENCIL_ENABLE(1);
167 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
168 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
169 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
170 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
171
172
173 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
174 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
175 if (state->stencil[1].enabled) {
176 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
177 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
178 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
179 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
180 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
181 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
182 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
183 }
184 }
185
186 /* alpha */
187 alpha_test_control = 0;
188 alpha_ref = 0;
189 if (state->alpha.enabled) {
190 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
191 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
192 alpha_ref = fui(state->alpha.ref_value);
193 }
194
195 /* misc */
196 db_render_control = 0;
197 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
198 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
199 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
200 /* TODO db_render_override depends on query */
201 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
202 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
203 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
204 r600_pipe_state_add_reg(rstate,
205 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
206 0xFFFFFFFF & C_028430_STENCILREF, NULL);
207 r600_pipe_state_add_reg(rstate,
208 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
209 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
210 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
211 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
212 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
213 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
214 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
215 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
216 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
217 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
218 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
219 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
220
221 return rstate;
222 }
223
224 static void *evergreen_create_rs_state(struct pipe_context *ctx,
225 const struct pipe_rasterizer_state *state)
226 {
227 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
228 struct r600_pipe_state *rstate;
229 unsigned tmp;
230 unsigned prov_vtx = 1, polygon_dual_mode;
231 unsigned clip_rule;
232
233 if (rs == NULL) {
234 return NULL;
235 }
236
237 rstate = &rs->rstate;
238 rs->flatshade = state->flatshade;
239 rs->sprite_coord_enable = state->sprite_coord_enable;
240
241 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
242
243 /* offset */
244 rs->offset_units = state->offset_units;
245 rs->offset_scale = state->offset_scale * 12.0f;
246
247 rstate->id = R600_PIPE_STATE_RASTERIZER;
248 if (state->flatshade_first)
249 prov_vtx = 0;
250 tmp = 0x00000001;
251 if (state->sprite_coord_enable) {
252 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
253 S_0286D4_PNT_SPRITE_OVRD_X(2) |
254 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
255 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
256 S_0286D4_PNT_SPRITE_OVRD_W(1);
257 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
258 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
259 }
260 }
261 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
262
263 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
264 state->fill_back != PIPE_POLYGON_MODE_FILL);
265 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
266 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
267 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
268 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
269 S_028814_FACE(!state->front_ccw) |
270 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
271 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
272 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
273 S_028814_POLY_MODE(polygon_dual_mode) |
274 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
275 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
276 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
277 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
278 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
279 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
280 /* point size 12.4 fixed point */
281 tmp = (unsigned)(state->point_size * 8.0);
282 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
283 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
284 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
285 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
286 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
287 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
288 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
289 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
290 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
291 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 0x00000005, 0xFFFFFFFF, NULL);
292 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
293 return rstate;
294 }
295
296 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
297 const struct pipe_sampler_state *state)
298 {
299 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
300 union util_color uc;
301
302 if (rstate == NULL) {
303 return NULL;
304 }
305
306 rstate->id = R600_PIPE_STATE_SAMPLER;
307 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
308 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
309 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
310 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
311 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
312 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
313 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
314 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
315 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
316 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
317 /* FIXME LOD it depends on texture base level ... */
318 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
319 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
320 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)),
321 0xFFFFFFFF, NULL);
322 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
323 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
324 S_03C008_TYPE(1),
325 0xFFFFFFFF, NULL);
326
327 if (uc.ui) {
328 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
329 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
330 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
331 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
332 }
333 return rstate;
334 }
335
336 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
337 struct pipe_resource *texture,
338 const struct pipe_sampler_view *state)
339 {
340 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
341 struct r600_pipe_state *rstate;
342 const struct util_format_description *desc;
343 struct r600_resource_texture *tmp;
344 struct r600_resource *rbuffer;
345 unsigned format;
346 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
347 unsigned char swizzle[4];
348 struct r600_bo *bo[2];
349
350 if (resource == NULL)
351 return NULL;
352 rstate = &resource->state;
353
354 /* initialize base object */
355 resource->base = *state;
356 resource->base.texture = NULL;
357 pipe_reference(NULL, &texture->reference);
358 resource->base.texture = texture;
359 resource->base.reference.count = 1;
360 resource->base.context = ctx;
361
362 swizzle[0] = state->swizzle_r;
363 swizzle[1] = state->swizzle_g;
364 swizzle[2] = state->swizzle_b;
365 swizzle[3] = state->swizzle_a;
366 format = r600_translate_texformat(state->format,
367 swizzle,
368 &word4, &yuv_format);
369 if (format == ~0) {
370 format = 0;
371 }
372 desc = util_format_description(state->format);
373 if (desc == NULL) {
374 R600_ERR("unknow format %d\n", state->format);
375 }
376 tmp = (struct r600_resource_texture*)texture;
377 rbuffer = &tmp->resource;
378 bo[0] = rbuffer->bo;
379 bo[1] = rbuffer->bo;
380 /* FIXME depth texture decompression */
381 if (tmp->depth) {
382 r600_texture_depth_flush(ctx, texture);
383 tmp = (struct r600_resource_texture*)texture;
384 rbuffer = &tmp->flushed_depth_texture->resource;
385 bo[0] = rbuffer->bo;
386 bo[1] = rbuffer->bo;
387 }
388 pitch = align(tmp->pitch_in_pixels[0], 8);
389
390 /* FIXME properly handle first level != 0 */
391 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
392 S_030000_DIM(r600_tex_dim(texture->target)) |
393 S_030000_PITCH((pitch / 8) - 1) |
394 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
395 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
396 S_030004_TEX_HEIGHT(texture->height0 - 1) |
397 S_030004_TEX_DEPTH(texture->depth0 - 1),
398 0xFFFFFFFF, NULL);
399 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
400 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
401 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
402 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
403 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
404 word4 | S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
405 S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
406 S_030010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
407 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
408 S_030014_LAST_LEVEL(state->last_level) |
409 S_030014_BASE_ARRAY(0) |
410 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
411 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
412 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
413 S_03001C_DATA_FORMAT(format) |
414 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
415
416 return &resource->base;
417 }
418
419 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
420 struct pipe_sampler_view **views)
421 {
422 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
423 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
424
425 for (int i = 0; i < count; i++) {
426 if (resource[i]) {
427 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i + PIPE_MAX_ATTRIBS);
428 }
429 }
430 }
431
432 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
433 struct pipe_sampler_view **views)
434 {
435 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
436 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
437 int i;
438
439 for (i = 0; i < count; i++) {
440 if (&rctx->ps_samplers.views[i]->base != views[i]) {
441 if (resource[i])
442 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
443 else
444 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
445
446 pipe_sampler_view_reference(
447 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
448 views[i]);
449 }
450 }
451 for (i = count; i < NUM_TEX_UNITS; i++) {
452 if (rctx->ps_samplers.views[i]) {
453 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
454 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
455 }
456 }
457 rctx->ps_samplers.n_views = count;
458 }
459
460 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
461 {
462 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
463 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
464
465
466 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
467 rctx->ps_samplers.n_samplers = count;
468
469 for (int i = 0; i < count; i++) {
470 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
471 }
472 }
473
474 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
475 {
476 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
477 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
478
479 for (int i = 0; i < count; i++) {
480 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
481 }
482 }
483
484 static void evergreen_delete_state(struct pipe_context *ctx, void *state)
485 {
486 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
487 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
488
489 if (rctx->states[rstate->id] == rstate) {
490 rctx->states[rstate->id] = NULL;
491 }
492 for (int i = 0; i < rstate->nregs; i++) {
493 r600_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
494 }
495 free(rstate);
496 }
497
498 static void evergreen_set_clip_state(struct pipe_context *ctx,
499 const struct pipe_clip_state *state)
500 {
501 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
502 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
503
504 if (rstate == NULL)
505 return;
506
507 rctx->clip = *state;
508 rstate->id = R600_PIPE_STATE_CLIP;
509 for (int i = 0; i < state->nr; i++) {
510 r600_pipe_state_add_reg(rstate,
511 R_0285BC_PA_CL_UCP0_X + i * 4,
512 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
513 r600_pipe_state_add_reg(rstate,
514 R_0285C0_PA_CL_UCP0_Y + i * 4,
515 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
516 r600_pipe_state_add_reg(rstate,
517 R_0285C4_PA_CL_UCP0_Z + i * 4,
518 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
519 r600_pipe_state_add_reg(rstate,
520 R_0285C8_PA_CL_UCP0_W + i * 4,
521 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
522 }
523 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
524 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
525 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
526 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
527
528 free(rctx->states[R600_PIPE_STATE_CLIP]);
529 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
530 r600_context_pipe_state_set(&rctx->ctx, rstate);
531 }
532
533 static void evergreen_bind_vertex_elements(struct pipe_context *ctx, void *state)
534 {
535 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
536 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
537
538 rctx->vertex_elements = v;
539 if (v) {
540 // rctx->vs_rebuild = TRUE;
541 }
542 }
543
544 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
545 const struct pipe_poly_stipple *state)
546 {
547 }
548
549 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
550 {
551 }
552
553 static void evergreen_set_scissor_state(struct pipe_context *ctx,
554 const struct pipe_scissor_state *state)
555 {
556 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
557 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
558 u32 tl, br;
559
560 if (rstate == NULL)
561 return;
562
563 rstate->id = R600_PIPE_STATE_SCISSOR;
564 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
565 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
566 r600_pipe_state_add_reg(rstate,
567 R_028210_PA_SC_CLIPRECT_0_TL, tl,
568 0xFFFFFFFF, NULL);
569 r600_pipe_state_add_reg(rstate,
570 R_028214_PA_SC_CLIPRECT_0_BR, br,
571 0xFFFFFFFF, NULL);
572 r600_pipe_state_add_reg(rstate,
573 R_028218_PA_SC_CLIPRECT_1_TL, tl,
574 0xFFFFFFFF, NULL);
575 r600_pipe_state_add_reg(rstate,
576 R_02821C_PA_SC_CLIPRECT_1_BR, br,
577 0xFFFFFFFF, NULL);
578 r600_pipe_state_add_reg(rstate,
579 R_028220_PA_SC_CLIPRECT_2_TL, tl,
580 0xFFFFFFFF, NULL);
581 r600_pipe_state_add_reg(rstate,
582 R_028224_PA_SC_CLIPRECT_2_BR, br,
583 0xFFFFFFFF, NULL);
584 r600_pipe_state_add_reg(rstate,
585 R_028228_PA_SC_CLIPRECT_3_TL, tl,
586 0xFFFFFFFF, NULL);
587 r600_pipe_state_add_reg(rstate,
588 R_02822C_PA_SC_CLIPRECT_3_BR, br,
589 0xFFFFFFFF, NULL);
590
591 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
592 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
593 r600_context_pipe_state_set(&rctx->ctx, rstate);
594 }
595
596 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
597 const struct pipe_stencil_ref *state)
598 {
599 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
600 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
601 u32 tmp;
602
603 if (rstate == NULL)
604 return;
605
606 rctx->stencil_ref = *state;
607 rstate->id = R600_PIPE_STATE_STENCIL_REF;
608 tmp = S_028430_STENCILREF(state->ref_value[0]);
609 r600_pipe_state_add_reg(rstate,
610 R_028430_DB_STENCILREFMASK, tmp,
611 ~C_028430_STENCILREF, NULL);
612 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
613 r600_pipe_state_add_reg(rstate,
614 R_028434_DB_STENCILREFMASK_BF, tmp,
615 ~C_028434_STENCILREF_BF, NULL);
616
617 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
618 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
619 r600_context_pipe_state_set(&rctx->ctx, rstate);
620 }
621
622 static void evergreen_set_viewport_state(struct pipe_context *ctx,
623 const struct pipe_viewport_state *state)
624 {
625 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
626 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
627
628 if (rstate == NULL)
629 return;
630
631 rctx->viewport = *state;
632 rstate->id = R600_PIPE_STATE_VIEWPORT;
633 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
634 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
635 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
636 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
637 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
638 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
639 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
640 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
641 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
642
643 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
644 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
645 r600_context_pipe_state_set(&rctx->ctx, rstate);
646 }
647
648 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
649 const struct pipe_framebuffer_state *state, int cb)
650 {
651 struct r600_resource_texture *rtex;
652 struct r600_resource *rbuffer;
653 struct r600_surface *surf;
654 unsigned level = state->cbufs[cb]->level;
655 unsigned pitch, slice;
656 unsigned color_info;
657 unsigned format, swap, ntype;
658 const struct util_format_description *desc;
659 struct r600_bo *bo[3];
660
661 surf = (struct r600_surface *)state->cbufs[cb];
662 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
663 rbuffer = &rtex->resource;
664 bo[0] = rbuffer->bo;
665 bo[1] = rbuffer->bo;
666 bo[2] = rbuffer->bo;
667
668 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
669 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
670 ntype = 0;
671 desc = util_format_description(rtex->resource.base.b.format);
672 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
673 ntype = V_028C70_NUMBER_SRGB;
674
675 format = r600_translate_colorformat(rtex->resource.base.b.format);
676 swap = r600_translate_colorswap(rtex->resource.base.b.format);
677 color_info = S_028C70_FORMAT(format) |
678 S_028C70_COMP_SWAP(swap) |
679 S_028C70_BLEND_CLAMP(1) |
680 S_028C70_NUMBER_TYPE(ntype);
681 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
682 color_info |= S_028C70_SOURCE_FORMAT(1);
683
684 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
685 r600_pipe_state_add_reg(rstate,
686 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
687 (state->cbufs[cb]->offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
688 r600_pipe_state_add_reg(rstate,
689 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
690 0x0, 0xFFFFFFFF, NULL);
691 r600_pipe_state_add_reg(rstate,
692 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
693 color_info, 0xFFFFFFFF, bo[0]);
694 r600_pipe_state_add_reg(rstate,
695 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
696 S_028C64_PITCH_TILE_MAX(pitch),
697 0xFFFFFFFF, NULL);
698 r600_pipe_state_add_reg(rstate,
699 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
700 S_028C68_SLICE_TILE_MAX(slice),
701 0xFFFFFFFF, NULL);
702 r600_pipe_state_add_reg(rstate,
703 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
704 0x00000000, 0xFFFFFFFF, NULL);
705 r600_pipe_state_add_reg(rstate,
706 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
707 S_028C74_NON_DISP_TILING_ORDER(1),
708 0xFFFFFFFF, bo[0]);
709 }
710
711 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
712 const struct pipe_framebuffer_state *state)
713 {
714 struct r600_resource_texture *rtex;
715 struct r600_resource *rbuffer;
716 struct r600_surface *surf;
717 unsigned level;
718 unsigned pitch, slice, format, stencil_format;
719
720 if (state->zsbuf == NULL)
721 return;
722
723 level = state->zsbuf->level;
724
725 surf = (struct r600_surface *)state->zsbuf;
726 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
727 rtex->tiled = 1;
728 rtex->array_mode[level] = 2;
729 rtex->tile_type = 1;
730 rtex->depth = 1;
731 rbuffer = &rtex->resource;
732
733 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
734 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
735 format = r600_translate_dbformat(state->zsbuf->texture->format);
736 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
737
738 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
739 (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
740 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
741 (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
742
743 if (stencil_format) {
744 uint32_t stencil_offset;
745
746 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
747 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
748 (state->zsbuf->offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
749 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
750 (state->zsbuf->offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
751 }
752
753 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
754 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
755 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
756
757 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
758 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
759 0xFFFFFFFF, rbuffer->bo);
760 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
761 S_028058_PITCH_TILE_MAX(pitch),
762 0xFFFFFFFF, NULL);
763 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
764 S_02805C_SLICE_TILE_MAX(slice),
765 0xFFFFFFFF, NULL);
766 }
767
768 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
769 const struct pipe_framebuffer_state *state)
770 {
771 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
772 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
773 u32 shader_mask, tl, br, target_mask;
774
775 if (rstate == NULL)
776 return;
777
778 /* unreference old buffer and reference new one */
779 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
780
781 util_copy_framebuffer_state(&rctx->framebuffer, state);
782
783 rctx->pframebuffer = &rctx->framebuffer;
784
785 /* build states */
786 for (int i = 0; i < state->nr_cbufs; i++) {
787 evergreen_cb(rctx, rstate, state, i);
788 }
789 if (state->zsbuf) {
790 evergreen_db(rctx, rstate, state);
791 }
792
793 target_mask = 0x00000000;
794 target_mask = 0xFFFFFFFF;
795 shader_mask = 0;
796 for (int i = 0; i < state->nr_cbufs; i++) {
797 target_mask ^= 0xf << (i * 4);
798 shader_mask |= 0xf << (i * 4);
799 }
800 tl = S_028240_TL_X(0) | S_028240_TL_Y(0);
801 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
802
803 r600_pipe_state_add_reg(rstate,
804 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
805 0xFFFFFFFF, NULL);
806 r600_pipe_state_add_reg(rstate,
807 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
808 0xFFFFFFFF, NULL);
809 r600_pipe_state_add_reg(rstate,
810 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
811 0xFFFFFFFF, NULL);
812 r600_pipe_state_add_reg(rstate,
813 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
814 0xFFFFFFFF, NULL);
815 r600_pipe_state_add_reg(rstate,
816 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
817 0xFFFFFFFF, NULL);
818 r600_pipe_state_add_reg(rstate,
819 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
820 0xFFFFFFFF, NULL);
821 r600_pipe_state_add_reg(rstate,
822 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
823 0xFFFFFFFF, NULL);
824 r600_pipe_state_add_reg(rstate,
825 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
826 0xFFFFFFFF, NULL);
827 r600_pipe_state_add_reg(rstate,
828 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
829 0xFFFFFFFF, NULL);
830 r600_pipe_state_add_reg(rstate,
831 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
832 0xFFFFFFFF, NULL);
833
834 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
835 0x00000000, target_mask, NULL);
836 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
837 shader_mask, 0xFFFFFFFF, NULL);
838 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
839 0x00000000, 0xFFFFFFFF, NULL);
840 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
841 0x00000000, 0xFFFFFFFF, NULL);
842
843 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
844 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
845 r600_context_pipe_state_set(&rctx->ctx, rstate);
846 }
847
848 static void evergreen_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
849 struct pipe_resource *buffer)
850 {
851 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
852 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
853
854 switch (shader) {
855 case PIPE_SHADER_VERTEX:
856 rctx->vs_const_buffer.nregs = 0;
857 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
858 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
859 ALIGN_DIVUP(buffer->width0 >> 4, 16),
860 0xFFFFFFFF, NULL);
861 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
862 R_028980_ALU_CONST_CACHE_VS_0,
863 (r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
864 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
865 break;
866 case PIPE_SHADER_FRAGMENT:
867 rctx->ps_const_buffer.nregs = 0;
868 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
869 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
870 ALIGN_DIVUP(buffer->width0 >> 4, 16),
871 0xFFFFFFFF, NULL);
872 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
873 R_028940_ALU_CONST_CACHE_PS_0,
874 (r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
875 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
876 break;
877 default:
878 R600_ERR("unsupported %d\n", shader);
879 return;
880 }
881 }
882
883 static void *evergreen_create_shader_state(struct pipe_context *ctx,
884 const struct pipe_shader_state *state)
885 {
886 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
887 int r;
888
889 r = r600_pipe_shader_create(ctx, shader, state->tokens);
890 if (r) {
891 return NULL;
892 }
893 return shader;
894 }
895
896 static void evergreen_bind_ps_shader(struct pipe_context *ctx, void *state)
897 {
898 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
899
900 /* TODO delete old shader */
901 rctx->ps_shader = (struct r600_pipe_shader *)state;
902 }
903
904 static void evergreen_bind_vs_shader(struct pipe_context *ctx, void *state)
905 {
906 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
907
908 /* TODO delete old shader */
909 rctx->vs_shader = (struct r600_pipe_shader *)state;
910 }
911
912 static void evergreen_delete_ps_shader(struct pipe_context *ctx, void *state)
913 {
914 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
915 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
916
917 if (rctx->ps_shader == shader) {
918 rctx->ps_shader = NULL;
919 }
920 /* TODO proper delete */
921 free(shader);
922 }
923
924 static void evergreen_delete_vs_shader(struct pipe_context *ctx, void *state)
925 {
926 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
927 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
928
929 if (rctx->vs_shader == shader) {
930 rctx->vs_shader = NULL;
931 }
932 /* TODO proper delete */
933 free(shader);
934 }
935
936 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
937 {
938 rctx->context.create_blend_state = evergreen_create_blend_state;
939 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
940 rctx->context.create_fs_state = evergreen_create_shader_state;
941 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
942 rctx->context.create_sampler_state = evergreen_create_sampler_state;
943 rctx->context.create_sampler_view = evergreen_create_sampler_view;
944 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
945 rctx->context.create_vs_state = evergreen_create_shader_state;
946 rctx->context.bind_blend_state = r600_bind_blend_state;
947 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
948 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
949 rctx->context.bind_fs_state = evergreen_bind_ps_shader;
950 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
951 rctx->context.bind_vertex_elements_state = evergreen_bind_vertex_elements;
952 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
953 rctx->context.bind_vs_state = evergreen_bind_vs_shader;
954 rctx->context.delete_blend_state = r600_delete_state;
955 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
956 rctx->context.delete_fs_state = evergreen_delete_ps_shader;
957 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
958 rctx->context.delete_sampler_state = r600_delete_state;
959 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
960 rctx->context.delete_vs_state = evergreen_delete_vs_shader;
961 rctx->context.set_blend_color = evergreen_set_blend_color;
962 rctx->context.set_clip_state = evergreen_set_clip_state;
963 rctx->context.set_constant_buffer = evergreen_set_constant_buffer;
964 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
965 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
966 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
967 rctx->context.set_sample_mask = evergreen_set_sample_mask;
968 rctx->context.set_scissor_state = evergreen_set_scissor_state;
969 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
970 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
971 rctx->context.set_index_buffer = r600_set_index_buffer;
972 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
973 rctx->context.set_viewport_state = evergreen_set_viewport_state;
974 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
975 }
976
977 void evergreen_init_config(struct r600_pipe_context *rctx)
978 {
979 struct r600_pipe_state *rstate = &rctx->config;
980 int ps_prio;
981 int vs_prio;
982 int gs_prio;
983 int es_prio;
984 int hs_prio, cs_prio, ls_prio;
985 int num_ps_gprs;
986 int num_vs_gprs;
987 int num_gs_gprs;
988 int num_es_gprs;
989 int num_hs_gprs;
990 int num_ls_gprs;
991 int num_temp_gprs;
992 int num_ps_threads;
993 int num_vs_threads;
994 int num_gs_threads;
995 int num_es_threads;
996 int num_hs_threads;
997 int num_ls_threads;
998 int num_ps_stack_entries;
999 int num_vs_stack_entries;
1000 int num_gs_stack_entries;
1001 int num_es_stack_entries;
1002 int num_hs_stack_entries;
1003 int num_ls_stack_entries;
1004 enum radeon_family family;
1005 unsigned tmp;
1006
1007 family = r600_get_family(rctx->radeon);
1008 ps_prio = 0;
1009 vs_prio = 1;
1010 gs_prio = 2;
1011 es_prio = 3;
1012 hs_prio = 0;
1013 ls_prio = 0;
1014 cs_prio = 0;
1015
1016 switch (family) {
1017 case CHIP_CEDAR:
1018 default:
1019 num_ps_gprs = 93;
1020 num_vs_gprs = 46;
1021 num_temp_gprs = 4;
1022 num_gs_gprs = 31;
1023 num_es_gprs = 31;
1024 num_hs_gprs = 23;
1025 num_ls_gprs = 23;
1026 num_ps_threads = 96;
1027 num_vs_threads = 16;
1028 num_gs_threads = 16;
1029 num_es_threads = 16;
1030 num_hs_threads = 16;
1031 num_ls_threads = 16;
1032 num_ps_stack_entries = 42;
1033 num_vs_stack_entries = 42;
1034 num_gs_stack_entries = 42;
1035 num_es_stack_entries = 42;
1036 num_hs_stack_entries = 42;
1037 num_ls_stack_entries = 42;
1038 break;
1039 case CHIP_REDWOOD:
1040 num_ps_gprs = 93;
1041 num_vs_gprs = 46;
1042 num_temp_gprs = 4;
1043 num_gs_gprs = 31;
1044 num_es_gprs = 31;
1045 num_hs_gprs = 23;
1046 num_ls_gprs = 23;
1047 num_ps_threads = 128;
1048 num_vs_threads = 20;
1049 num_gs_threads = 20;
1050 num_es_threads = 20;
1051 num_hs_threads = 20;
1052 num_ls_threads = 20;
1053 num_ps_stack_entries = 42;
1054 num_vs_stack_entries = 42;
1055 num_gs_stack_entries = 42;
1056 num_es_stack_entries = 42;
1057 num_hs_stack_entries = 42;
1058 num_ls_stack_entries = 42;
1059 break;
1060 case CHIP_JUNIPER:
1061 num_ps_gprs = 93;
1062 num_vs_gprs = 46;
1063 num_temp_gprs = 4;
1064 num_gs_gprs = 31;
1065 num_es_gprs = 31;
1066 num_hs_gprs = 23;
1067 num_ls_gprs = 23;
1068 num_ps_threads = 128;
1069 num_vs_threads = 20;
1070 num_gs_threads = 20;
1071 num_es_threads = 20;
1072 num_hs_threads = 20;
1073 num_ls_threads = 20;
1074 num_ps_stack_entries = 85;
1075 num_vs_stack_entries = 85;
1076 num_gs_stack_entries = 85;
1077 num_es_stack_entries = 85;
1078 num_hs_stack_entries = 85;
1079 num_ls_stack_entries = 85;
1080 break;
1081 case CHIP_CYPRESS:
1082 case CHIP_HEMLOCK:
1083 num_ps_gprs = 93;
1084 num_vs_gprs = 46;
1085 num_temp_gprs = 4;
1086 num_gs_gprs = 31;
1087 num_es_gprs = 31;
1088 num_hs_gprs = 23;
1089 num_ls_gprs = 23;
1090 num_ps_threads = 128;
1091 num_vs_threads = 20;
1092 num_gs_threads = 20;
1093 num_es_threads = 20;
1094 num_hs_threads = 20;
1095 num_ls_threads = 20;
1096 num_ps_stack_entries = 85;
1097 num_vs_stack_entries = 85;
1098 num_gs_stack_entries = 85;
1099 num_es_stack_entries = 85;
1100 num_hs_stack_entries = 85;
1101 num_ls_stack_entries = 85;
1102 break;
1103 }
1104
1105 tmp = 0x00000000;
1106 switch (family) {
1107 case CHIP_CEDAR:
1108 break;
1109 default:
1110 tmp |= S_008C00_VC_ENABLE(1);
1111 break;
1112 }
1113 tmp |= S_008C00_EXPORT_SRC_C(1);
1114 tmp |= S_008C00_CS_PRIO(cs_prio);
1115 tmp |= S_008C00_LS_PRIO(ls_prio);
1116 tmp |= S_008C00_HS_PRIO(hs_prio);
1117 tmp |= S_008C00_PS_PRIO(ps_prio);
1118 tmp |= S_008C00_VS_PRIO(vs_prio);
1119 tmp |= S_008C00_GS_PRIO(gs_prio);
1120 tmp |= S_008C00_ES_PRIO(es_prio);
1121 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1122
1123 tmp = 0;
1124 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1125 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1126 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1127 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1128
1129 tmp = 0;
1130 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1131 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1132 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1133
1134 tmp = 0;
1135 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1136 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1137 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1138
1139 tmp = 0;
1140 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1141 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1142 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1143 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1144 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1145
1146 tmp = 0;
1147 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1148 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1149 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1150
1151 tmp = 0;
1152 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1153 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1154 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1155
1156 tmp = 0;
1157 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1158 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1159 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1160
1161 tmp = 0;
1162 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1163 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1164 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1165
1166 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1167 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1168
1169 // r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1170
1171 // r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1172 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1173 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1174
1175 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1176 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1177 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1178 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1179 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1180 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1181
1182 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1183 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1184 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1185 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1186
1187 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1188 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1189 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1190 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1191 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1192 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1193 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1194 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1195 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1196 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1197 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1198 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1199 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1200 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1201 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1202 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1203 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1204 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1205
1206 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1207 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1208 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1209 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1210 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1211 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1212 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1213 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1214 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1215 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1216 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1217 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1218 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1219 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1220 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1221 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1222 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1223 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1224 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1225 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1226 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1227 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1228 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1229 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1230 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1231 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1232 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1233 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1234 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1235 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1236 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1237 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1238
1239 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1240 0x0, 0xFFFFFFFF, NULL);
1241
1242 r600_context_pipe_state_set(&rctx->ctx, rstate);
1243 }
1244
1245 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
1246 void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
1247 {
1248 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1249 struct r600_pipe_state *rstate;
1250 struct r600_resource *rbuffer;
1251 unsigned i, j, offset, prim;
1252 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
1253 struct pipe_vertex_buffer *vertex_buffer;
1254 struct r600_draw rdraw;
1255 struct r600_pipe_state vgt;
1256 struct r600_drawl draw;
1257 boolean translate = FALSE;
1258
1259 if (rctx->vertex_elements->incompatible_layout) {
1260 r600_begin_vertex_translate(rctx);
1261 translate = TRUE;
1262 }
1263
1264 if (rctx->any_user_vbs) {
1265 r600_upload_user_buffers(rctx);
1266 rctx->any_user_vbs = FALSE;
1267 }
1268
1269 memset(&draw, 0, sizeof(struct r600_drawl));
1270 draw.ctx = ctx;
1271 draw.mode = info->mode;
1272 draw.start = info->start;
1273 draw.count = info->count;
1274 if (info->indexed && rctx->index_buffer.buffer) {
1275 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
1276 draw.min_index = info->min_index;
1277 draw.max_index = info->max_index;
1278 draw.index_bias = info->index_bias;
1279
1280 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
1281 &rctx->index_buffer.index_size,
1282 &draw.start,
1283 info->count);
1284
1285 draw.index_size = rctx->index_buffer.index_size;
1286 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
1287 draw.index_buffer_offset = draw.start * draw.index_size;
1288 draw.start = 0;
1289 r600_upload_index_buffer(rctx, &draw);
1290 } else {
1291 draw.index_size = 0;
1292 draw.index_buffer = NULL;
1293 draw.min_index = info->min_index;
1294 draw.max_index = info->max_index;
1295 draw.index_bias = info->start;
1296 }
1297
1298 switch (draw.index_size) {
1299 case 2:
1300 vgt_draw_initiator = 0;
1301 vgt_dma_index_type = 0;
1302 break;
1303 case 4:
1304 vgt_draw_initiator = 0;
1305 vgt_dma_index_type = 1;
1306 break;
1307 case 0:
1308 vgt_draw_initiator = 2;
1309 vgt_dma_index_type = 0;
1310 break;
1311 default:
1312 R600_ERR("unsupported index size %d\n", draw.index_size);
1313 return;
1314 }
1315 if (r600_conv_pipe_prim(draw.mode, &prim))
1316 return;
1317
1318 /* rebuild vertex shader if input format changed */
1319 if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
1320 return;
1321 if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
1322 return;
1323
1324 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
1325 uint32_t word3, word2;
1326 uint32_t format;
1327 rstate = &rctx->vs_resource[i];
1328
1329 rstate->id = R600_PIPE_STATE_RESOURCE;
1330 rstate->nregs = 0;
1331
1332 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
1333 vertex_buffer = &rctx->vertex_buffer[j];
1334 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
1335 offset = rctx->vertex_elements->elements[i].src_offset +
1336 vertex_buffer->buffer_offset +
1337 r600_bo_offset(rbuffer->bo);
1338
1339 format = r600_translate_vertex_data_type(rctx->vertex_elements->hw_format[i]);
1340
1341 word2 = format | S_030008_STRIDE(vertex_buffer->stride);
1342
1343 word3 = r600_translate_vertex_data_swizzle(rctx->vertex_elements->hw_format[i]);
1344
1345 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
1346 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
1347 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
1348 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3, word3, 0xFFFFFFFF, NULL);
1349 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
1350 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
1351 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x00000000, 0xFFFFFFFF, NULL);
1352 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7, 0xC0000000, 0xFFFFFFFF, NULL);
1353 evergreen_vs_resource_set(&rctx->ctx, rstate, i);
1354 }
1355
1356 mask = 0;
1357 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
1358 mask |= (0xF << (i * 4));
1359 }
1360
1361 vgt.id = R600_PIPE_STATE_VGT;
1362 vgt.nregs = 0;
1363 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
1364 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw.index_bias, 0xFFFFFFFF, NULL);
1365 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
1366 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw.max_index, 0xFFFFFFFF, NULL);
1367 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw.min_index, 0xFFFFFFFF, NULL);
1368 r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
1369 r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
1370
1371 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1372 float offset_units = rctx->rasterizer->offset_units;
1373 unsigned offset_db_fmt_cntl = 0, depth;
1374
1375 switch (rctx->framebuffer.zsbuf->texture->format) {
1376 case PIPE_FORMAT_Z24X8_UNORM:
1377 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1378 depth = -24;
1379 offset_units *= 2.0f;
1380 break;
1381 case PIPE_FORMAT_Z32_FLOAT:
1382 depth = -23;
1383 offset_units *= 1.0f;
1384 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1385 break;
1386 case PIPE_FORMAT_Z16_UNORM:
1387 depth = -16;
1388 offset_units *= 4.0f;
1389 break;
1390 default:
1391 return;
1392 }
1393 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1394 r600_pipe_state_add_reg(&vgt,
1395 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1396 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1397 r600_pipe_state_add_reg(&vgt,
1398 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1399 fui(offset_units), 0xFFFFFFFF, NULL);
1400 r600_pipe_state_add_reg(&vgt,
1401 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1402 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1403 r600_pipe_state_add_reg(&vgt,
1404 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1405 fui(offset_units), 0xFFFFFFFF, NULL);
1406 r600_pipe_state_add_reg(&vgt,
1407 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1408 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1409 }
1410 r600_context_pipe_state_set(&rctx->ctx, &vgt);
1411
1412 rdraw.vgt_num_indices = draw.count;
1413 rdraw.vgt_num_instances = 1;
1414 rdraw.vgt_index_type = vgt_dma_index_type;
1415 rdraw.vgt_draw_initiator = vgt_draw_initiator;
1416 rdraw.indices = NULL;
1417 if (draw.index_buffer) {
1418 rbuffer = (struct r600_resource*)draw.index_buffer;
1419 rdraw.indices = rbuffer->bo;
1420 rdraw.indices_bo_offset = draw.index_buffer_offset;
1421 }
1422 evergreen_context_draw(&rctx->ctx, &rdraw);
1423
1424 if (translate)
1425 r600_end_vertex_translate(rctx);
1426
1427 pipe_resource_reference(&draw.index_buffer, NULL);
1428 }
1429
1430 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1431 {
1432 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1433 struct r600_pipe_state *rstate = &shader->rstate;
1434 struct r600_shader *rshader = &shader->shader;
1435 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
1436 int pos_index = -1, face_index = -1;
1437 int ninterp = 0;
1438 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1439 unsigned spi_baryc_cntl;
1440
1441 /* clear previous register */
1442 rstate->nregs = 0;
1443
1444 for (i = 0; i < rshader->ninput; i++) {
1445 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
1446 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1447 POSITION goes via GPRs from the SC so isn't counted */
1448 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1449 pos_index = i;
1450 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1451 face_index = i;
1452 else {
1453 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
1454 rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1455 ninterp++;
1456 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1457 have_linear = TRUE;
1458 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1459 have_perspective = TRUE;
1460 if (rshader->input[i].centroid)
1461 have_centroid = TRUE;
1462 }
1463 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
1464 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
1465 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
1466 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
1467 }
1468 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
1469 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
1470 tmp |= S_028644_PT_SPRITE_TEX(1);
1471 }
1472 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
1473 }
1474 for (i = 0; i < rshader->noutput; i++) {
1475 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1476 r600_pipe_state_add_reg(rstate,
1477 R_02880C_DB_SHADER_CONTROL,
1478 S_02880C_Z_EXPORT_ENABLE(1),
1479 S_02880C_Z_EXPORT_ENABLE(1), NULL);
1480 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1481 r600_pipe_state_add_reg(rstate,
1482 R_02880C_DB_SHADER_CONTROL,
1483 S_02880C_STENCIL_EXPORT_ENABLE(1),
1484 S_02880C_STENCIL_EXPORT_ENABLE(1), NULL);
1485 }
1486
1487 exports_ps = 0;
1488 num_cout = 0;
1489 for (i = 0; i < rshader->noutput; i++) {
1490 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1491 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1492 exports_ps |= 1;
1493 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1494 num_cout++;
1495 }
1496 }
1497 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1498 if (!exports_ps) {
1499 /* always at least export 1 component per pixel */
1500 exports_ps = 2;
1501 }
1502
1503 if (ninterp == 0) {
1504 ninterp = 1;
1505 have_perspective = TRUE;
1506 }
1507
1508 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
1509 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
1510 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
1511 spi_input_z = 0;
1512 if (pos_index != -1) {
1513 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
1514 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1515 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
1516 spi_input_z |= 1;
1517 }
1518
1519 spi_ps_in_control_1 = 0;
1520 if (face_index != -1) {
1521 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1522 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1523 }
1524
1525 spi_baryc_cntl = 0;
1526 if (have_perspective)
1527 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
1528 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
1529 if (have_linear)
1530 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
1531 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
1532
1533 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1534 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1535 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1536 spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1537 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
1538 0, 0xFFFFFFFF, NULL);
1539 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1540 r600_pipe_state_add_reg(rstate,
1541 R_0286E0_SPI_BARYC_CNTL,
1542 spi_baryc_cntl,
1543 0xFFFFFFFF, NULL);
1544
1545 r600_pipe_state_add_reg(rstate,
1546 R_028840_SQ_PGM_START_PS,
1547 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1548 r600_pipe_state_add_reg(rstate,
1549 R_028844_SQ_PGM_RESOURCES_PS,
1550 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1551 S_028844_PRIME_CACHE_ON_DRAW(1) |
1552 S_028844_STACK_SIZE(rshader->bc.nstack),
1553 0xFFFFFFFF, NULL);
1554 r600_pipe_state_add_reg(rstate,
1555 R_028848_SQ_PGM_RESOURCES_2_PS,
1556 0x0, 0xFFFFFFFF, NULL);
1557 r600_pipe_state_add_reg(rstate,
1558 R_02884C_SQ_PGM_EXPORTS_PS,
1559 exports_ps, 0xFFFFFFFF, NULL);
1560
1561 if (rshader->uses_kill) {
1562 /* only set some bits here, the other bits are set in the dsa state */
1563 r600_pipe_state_add_reg(rstate,
1564 R_02880C_DB_SHADER_CONTROL,
1565 S_02880C_KILL_ENABLE(1),
1566 S_02880C_KILL_ENABLE(1), NULL);
1567 }
1568
1569 r600_pipe_state_add_reg(rstate,
1570 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
1571 0xFFFFFFFF, NULL);
1572 }
1573
1574 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1575 {
1576 struct r600_pipe_state *rstate = &shader->rstate;
1577 struct r600_shader *rshader = &shader->shader;
1578 unsigned spi_vs_out_id[10];
1579 unsigned i, tmp;
1580
1581 /* clear previous register */
1582 rstate->nregs = 0;
1583
1584 /* so far never got proper semantic id from tgsi */
1585 for (i = 0; i < 10; i++) {
1586 spi_vs_out_id[i] = 0;
1587 }
1588 for (i = 0; i < 32; i++) {
1589 tmp = i << ((i & 3) * 8);
1590 spi_vs_out_id[i / 4] |= tmp;
1591 }
1592 for (i = 0; i < 10; i++) {
1593 r600_pipe_state_add_reg(rstate,
1594 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1595 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1596 }
1597
1598 r600_pipe_state_add_reg(rstate,
1599 R_0286C4_SPI_VS_OUT_CONFIG,
1600 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1601 0xFFFFFFFF, NULL);
1602 r600_pipe_state_add_reg(rstate,
1603 R_028860_SQ_PGM_RESOURCES_VS,
1604 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1605 S_028860_STACK_SIZE(rshader->bc.nstack),
1606 0xFFFFFFFF, NULL);
1607 r600_pipe_state_add_reg(rstate,
1608 R_028864_SQ_PGM_RESOURCES_2_VS,
1609 0x0, 0xFFFFFFFF, NULL);
1610 r600_pipe_state_add_reg(rstate,
1611 R_0288A8_SQ_PGM_RESOURCES_FS,
1612 0x00000000, 0xFFFFFFFF, NULL);
1613 r600_pipe_state_add_reg(rstate,
1614 R_02885C_SQ_PGM_START_VS,
1615 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1616 r600_pipe_state_add_reg(rstate,
1617 R_0288A4_SQ_PGM_START_FS,
1618 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1619
1620 r600_pipe_state_add_reg(rstate,
1621 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1622 0xFFFFFFFF, NULL);
1623 }
1624
1625 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1626 {
1627 struct pipe_depth_stencil_alpha_state dsa;
1628 struct r600_pipe_state *rstate;
1629
1630 memset(&dsa, 0, sizeof(dsa));
1631
1632 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1633 r600_pipe_state_add_reg(rstate,
1634 R_02880C_DB_SHADER_CONTROL,
1635 0x0,
1636 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1637 r600_pipe_state_add_reg(rstate,
1638 R_028000_DB_RENDER_CONTROL,
1639 S_028000_DEPTH_COPY_ENABLE(1) |
1640 S_028000_STENCIL_COPY_ENABLE(1) |
1641 S_028000_COPY_CENTROID(1),
1642 S_028000_DEPTH_COPY_ENABLE(1) |
1643 S_028000_STENCIL_COPY_ENABLE(1) |
1644 S_028000_COPY_CENTROID(1), NULL);
1645 return rstate;
1646 }