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r600g: consolidate set_sampler_views functions
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "evergreend.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31 #include "evergreen_compute.h"
32
33 static uint32_t eg_num_banks(uint32_t nbanks)
34 {
35 switch (nbanks) {
36 case 2:
37 return 0;
38 case 4:
39 return 1;
40 case 8:
41 default:
42 return 2;
43 case 16:
44 return 3;
45 }
46 }
47
48
49 static unsigned eg_tile_split(unsigned tile_split)
50 {
51 switch (tile_split) {
52 case 64: tile_split = 0; break;
53 case 128: tile_split = 1; break;
54 case 256: tile_split = 2; break;
55 case 512: tile_split = 3; break;
56 default:
57 case 1024: tile_split = 4; break;
58 case 2048: tile_split = 5; break;
59 case 4096: tile_split = 6; break;
60 }
61 return tile_split;
62 }
63
64 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65 {
66 switch (macro_tile_aspect) {
67 default:
68 case 1: macro_tile_aspect = 0; break;
69 case 2: macro_tile_aspect = 1; break;
70 case 4: macro_tile_aspect = 2; break;
71 case 8: macro_tile_aspect = 3; break;
72 }
73 return macro_tile_aspect;
74 }
75
76 static unsigned eg_bank_wh(unsigned bankwh)
77 {
78 switch (bankwh) {
79 default:
80 case 1: bankwh = 0; break;
81 case 2: bankwh = 1; break;
82 case 4: bankwh = 2; break;
83 case 8: bankwh = 3; break;
84 }
85 return bankwh;
86 }
87
88 static uint32_t r600_translate_blend_function(int blend_func)
89 {
90 switch (blend_func) {
91 case PIPE_BLEND_ADD:
92 return V_028780_COMB_DST_PLUS_SRC;
93 case PIPE_BLEND_SUBTRACT:
94 return V_028780_COMB_SRC_MINUS_DST;
95 case PIPE_BLEND_REVERSE_SUBTRACT:
96 return V_028780_COMB_DST_MINUS_SRC;
97 case PIPE_BLEND_MIN:
98 return V_028780_COMB_MIN_DST_SRC;
99 case PIPE_BLEND_MAX:
100 return V_028780_COMB_MAX_DST_SRC;
101 default:
102 R600_ERR("Unknown blend function %d\n", blend_func);
103 assert(0);
104 break;
105 }
106 return 0;
107 }
108
109 static uint32_t r600_translate_blend_factor(int blend_fact)
110 {
111 switch (blend_fact) {
112 case PIPE_BLENDFACTOR_ONE:
113 return V_028780_BLEND_ONE;
114 case PIPE_BLENDFACTOR_SRC_COLOR:
115 return V_028780_BLEND_SRC_COLOR;
116 case PIPE_BLENDFACTOR_SRC_ALPHA:
117 return V_028780_BLEND_SRC_ALPHA;
118 case PIPE_BLENDFACTOR_DST_ALPHA:
119 return V_028780_BLEND_DST_ALPHA;
120 case PIPE_BLENDFACTOR_DST_COLOR:
121 return V_028780_BLEND_DST_COLOR;
122 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123 return V_028780_BLEND_SRC_ALPHA_SATURATE;
124 case PIPE_BLENDFACTOR_CONST_COLOR:
125 return V_028780_BLEND_CONST_COLOR;
126 case PIPE_BLENDFACTOR_CONST_ALPHA:
127 return V_028780_BLEND_CONST_ALPHA;
128 case PIPE_BLENDFACTOR_ZERO:
129 return V_028780_BLEND_ZERO;
130 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136 case PIPE_BLENDFACTOR_INV_DST_COLOR:
137 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_SRC1_COLOR:
143 return V_028780_BLEND_SRC1_COLOR;
144 case PIPE_BLENDFACTOR_SRC1_ALPHA:
145 return V_028780_BLEND_SRC1_ALPHA;
146 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147 return V_028780_BLEND_INV_SRC1_COLOR;
148 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149 return V_028780_BLEND_INV_SRC1_ALPHA;
150 default:
151 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152 assert(0);
153 break;
154 }
155 return 0;
156 }
157
158 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
159 {
160 switch (dim) {
161 default:
162 case PIPE_TEXTURE_1D:
163 return V_030000_SQ_TEX_DIM_1D;
164 case PIPE_TEXTURE_1D_ARRAY:
165 return V_030000_SQ_TEX_DIM_1D_ARRAY;
166 case PIPE_TEXTURE_2D:
167 case PIPE_TEXTURE_RECT:
168 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
169 V_030000_SQ_TEX_DIM_2D;
170 case PIPE_TEXTURE_2D_ARRAY:
171 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
172 V_030000_SQ_TEX_DIM_2D_ARRAY;
173 case PIPE_TEXTURE_3D:
174 return V_030000_SQ_TEX_DIM_3D;
175 case PIPE_TEXTURE_CUBE:
176 return V_030000_SQ_TEX_DIM_CUBEMAP;
177 }
178 }
179
180 static uint32_t r600_translate_dbformat(enum pipe_format format)
181 {
182 switch (format) {
183 case PIPE_FORMAT_Z16_UNORM:
184 return V_028040_Z_16;
185 case PIPE_FORMAT_Z24X8_UNORM:
186 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
187 return V_028040_Z_24;
188 case PIPE_FORMAT_Z32_FLOAT:
189 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
190 return V_028040_Z_32_FLOAT;
191 default:
192 return ~0U;
193 }
194 }
195
196 static uint32_t r600_translate_colorswap(enum pipe_format format)
197 {
198 switch (format) {
199 /* 8-bit buffers. */
200 case PIPE_FORMAT_L4A4_UNORM:
201 case PIPE_FORMAT_A4R4_UNORM:
202 return V_028C70_SWAP_ALT;
203
204 case PIPE_FORMAT_A8_UNORM:
205 case PIPE_FORMAT_A8_SNORM:
206 case PIPE_FORMAT_A8_UINT:
207 case PIPE_FORMAT_A8_SINT:
208 case PIPE_FORMAT_A16_UNORM:
209 case PIPE_FORMAT_A16_SNORM:
210 case PIPE_FORMAT_A16_UINT:
211 case PIPE_FORMAT_A16_SINT:
212 case PIPE_FORMAT_A16_FLOAT:
213 case PIPE_FORMAT_A32_UINT:
214 case PIPE_FORMAT_A32_SINT:
215 case PIPE_FORMAT_A32_FLOAT:
216 case PIPE_FORMAT_R4A4_UNORM:
217 return V_028C70_SWAP_ALT_REV;
218 case PIPE_FORMAT_I8_UNORM:
219 case PIPE_FORMAT_I8_SNORM:
220 case PIPE_FORMAT_I8_UINT:
221 case PIPE_FORMAT_I8_SINT:
222 case PIPE_FORMAT_I16_UNORM:
223 case PIPE_FORMAT_I16_SNORM:
224 case PIPE_FORMAT_I16_UINT:
225 case PIPE_FORMAT_I16_SINT:
226 case PIPE_FORMAT_I16_FLOAT:
227 case PIPE_FORMAT_I32_UINT:
228 case PIPE_FORMAT_I32_SINT:
229 case PIPE_FORMAT_I32_FLOAT:
230 case PIPE_FORMAT_L8_UNORM:
231 case PIPE_FORMAT_L8_SNORM:
232 case PIPE_FORMAT_L8_UINT:
233 case PIPE_FORMAT_L8_SINT:
234 case PIPE_FORMAT_L8_SRGB:
235 case PIPE_FORMAT_L16_UNORM:
236 case PIPE_FORMAT_L16_SNORM:
237 case PIPE_FORMAT_L16_UINT:
238 case PIPE_FORMAT_L16_SINT:
239 case PIPE_FORMAT_L16_FLOAT:
240 case PIPE_FORMAT_L32_UINT:
241 case PIPE_FORMAT_L32_SINT:
242 case PIPE_FORMAT_L32_FLOAT:
243 case PIPE_FORMAT_R8_UNORM:
244 case PIPE_FORMAT_R8_SNORM:
245 case PIPE_FORMAT_R8_UINT:
246 case PIPE_FORMAT_R8_SINT:
247 return V_028C70_SWAP_STD;
248
249 /* 16-bit buffers. */
250 case PIPE_FORMAT_B5G6R5_UNORM:
251 return V_028C70_SWAP_STD_REV;
252
253 case PIPE_FORMAT_B5G5R5A1_UNORM:
254 case PIPE_FORMAT_B5G5R5X1_UNORM:
255 return V_028C70_SWAP_ALT;
256
257 case PIPE_FORMAT_B4G4R4A4_UNORM:
258 case PIPE_FORMAT_B4G4R4X4_UNORM:
259 return V_028C70_SWAP_ALT;
260
261 case PIPE_FORMAT_Z16_UNORM:
262 return V_028C70_SWAP_STD;
263
264 case PIPE_FORMAT_L8A8_UNORM:
265 case PIPE_FORMAT_L8A8_SNORM:
266 case PIPE_FORMAT_L8A8_UINT:
267 case PIPE_FORMAT_L8A8_SINT:
268 case PIPE_FORMAT_L8A8_SRGB:
269 case PIPE_FORMAT_L16A16_UNORM:
270 case PIPE_FORMAT_L16A16_SNORM:
271 case PIPE_FORMAT_L16A16_UINT:
272 case PIPE_FORMAT_L16A16_SINT:
273 case PIPE_FORMAT_L16A16_FLOAT:
274 case PIPE_FORMAT_L32A32_UINT:
275 case PIPE_FORMAT_L32A32_SINT:
276 case PIPE_FORMAT_L32A32_FLOAT:
277 return V_028C70_SWAP_ALT;
278 case PIPE_FORMAT_R8G8_UNORM:
279 case PIPE_FORMAT_R8G8_SNORM:
280 case PIPE_FORMAT_R8G8_UINT:
281 case PIPE_FORMAT_R8G8_SINT:
282 return V_028C70_SWAP_STD;
283
284 case PIPE_FORMAT_R16_UNORM:
285 case PIPE_FORMAT_R16_SNORM:
286 case PIPE_FORMAT_R16_UINT:
287 case PIPE_FORMAT_R16_SINT:
288 case PIPE_FORMAT_R16_FLOAT:
289 return V_028C70_SWAP_STD;
290
291 /* 32-bit buffers. */
292 case PIPE_FORMAT_A8B8G8R8_SRGB:
293 return V_028C70_SWAP_STD_REV;
294 case PIPE_FORMAT_B8G8R8A8_SRGB:
295 return V_028C70_SWAP_ALT;
296
297 case PIPE_FORMAT_B8G8R8A8_UNORM:
298 case PIPE_FORMAT_B8G8R8X8_UNORM:
299 return V_028C70_SWAP_ALT;
300
301 case PIPE_FORMAT_A8R8G8B8_UNORM:
302 case PIPE_FORMAT_X8R8G8B8_UNORM:
303 return V_028C70_SWAP_ALT_REV;
304 case PIPE_FORMAT_R8G8B8A8_SNORM:
305 case PIPE_FORMAT_R8G8B8A8_UNORM:
306 case PIPE_FORMAT_R8G8B8A8_SINT:
307 case PIPE_FORMAT_R8G8B8A8_UINT:
308 case PIPE_FORMAT_R8G8B8X8_UNORM:
309 return V_028C70_SWAP_STD;
310
311 case PIPE_FORMAT_A8B8G8R8_UNORM:
312 case PIPE_FORMAT_X8B8G8R8_UNORM:
313 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
314 return V_028C70_SWAP_STD_REV;
315
316 case PIPE_FORMAT_Z24X8_UNORM:
317 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
318 return V_028C70_SWAP_STD;
319
320 case PIPE_FORMAT_X8Z24_UNORM:
321 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
322 return V_028C70_SWAP_STD;
323
324 case PIPE_FORMAT_R10G10B10A2_UNORM:
325 case PIPE_FORMAT_R10G10B10X2_SNORM:
326 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
327 return V_028C70_SWAP_STD;
328
329 case PIPE_FORMAT_B10G10R10A2_UNORM:
330 case PIPE_FORMAT_B10G10R10A2_UINT:
331 return V_028C70_SWAP_ALT;
332
333 case PIPE_FORMAT_R11G11B10_FLOAT:
334 case PIPE_FORMAT_R32_FLOAT:
335 case PIPE_FORMAT_R32_UINT:
336 case PIPE_FORMAT_R32_SINT:
337 case PIPE_FORMAT_Z32_FLOAT:
338 case PIPE_FORMAT_R16G16_FLOAT:
339 case PIPE_FORMAT_R16G16_UNORM:
340 case PIPE_FORMAT_R16G16_SNORM:
341 case PIPE_FORMAT_R16G16_UINT:
342 case PIPE_FORMAT_R16G16_SINT:
343 return V_028C70_SWAP_STD;
344
345 /* 64-bit buffers. */
346 case PIPE_FORMAT_R32G32_FLOAT:
347 case PIPE_FORMAT_R32G32_UINT:
348 case PIPE_FORMAT_R32G32_SINT:
349 case PIPE_FORMAT_R16G16B16A16_UNORM:
350 case PIPE_FORMAT_R16G16B16A16_SNORM:
351 case PIPE_FORMAT_R16G16B16A16_UINT:
352 case PIPE_FORMAT_R16G16B16A16_SINT:
353 case PIPE_FORMAT_R16G16B16A16_FLOAT:
354 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
355
356 /* 128-bit buffers. */
357 case PIPE_FORMAT_R32G32B32A32_FLOAT:
358 case PIPE_FORMAT_R32G32B32A32_SNORM:
359 case PIPE_FORMAT_R32G32B32A32_UNORM:
360 case PIPE_FORMAT_R32G32B32A32_SINT:
361 case PIPE_FORMAT_R32G32B32A32_UINT:
362 return V_028C70_SWAP_STD;
363 default:
364 R600_ERR("unsupported colorswap format %d\n", format);
365 return ~0U;
366 }
367 return ~0U;
368 }
369
370 static uint32_t r600_translate_colorformat(enum pipe_format format)
371 {
372 switch (format) {
373 /* 8-bit buffers. */
374 case PIPE_FORMAT_A8_UNORM:
375 case PIPE_FORMAT_A8_SNORM:
376 case PIPE_FORMAT_A8_UINT:
377 case PIPE_FORMAT_A8_SINT:
378 case PIPE_FORMAT_I8_UNORM:
379 case PIPE_FORMAT_I8_SNORM:
380 case PIPE_FORMAT_I8_UINT:
381 case PIPE_FORMAT_I8_SINT:
382 case PIPE_FORMAT_L8_UNORM:
383 case PIPE_FORMAT_L8_SNORM:
384 case PIPE_FORMAT_L8_UINT:
385 case PIPE_FORMAT_L8_SINT:
386 case PIPE_FORMAT_L8_SRGB:
387 case PIPE_FORMAT_R8_UNORM:
388 case PIPE_FORMAT_R8_SNORM:
389 case PIPE_FORMAT_R8_UINT:
390 case PIPE_FORMAT_R8_SINT:
391 return V_028C70_COLOR_8;
392
393 /* 16-bit buffers. */
394 case PIPE_FORMAT_B5G6R5_UNORM:
395 return V_028C70_COLOR_5_6_5;
396
397 case PIPE_FORMAT_B5G5R5A1_UNORM:
398 case PIPE_FORMAT_B5G5R5X1_UNORM:
399 return V_028C70_COLOR_1_5_5_5;
400
401 case PIPE_FORMAT_B4G4R4A4_UNORM:
402 case PIPE_FORMAT_B4G4R4X4_UNORM:
403 return V_028C70_COLOR_4_4_4_4;
404
405 case PIPE_FORMAT_Z16_UNORM:
406 return V_028C70_COLOR_16;
407
408 case PIPE_FORMAT_L8A8_UNORM:
409 case PIPE_FORMAT_L8A8_SNORM:
410 case PIPE_FORMAT_L8A8_UINT:
411 case PIPE_FORMAT_L8A8_SINT:
412 case PIPE_FORMAT_L8A8_SRGB:
413 case PIPE_FORMAT_R8G8_UNORM:
414 case PIPE_FORMAT_R8G8_SNORM:
415 case PIPE_FORMAT_R8G8_UINT:
416 case PIPE_FORMAT_R8G8_SINT:
417 return V_028C70_COLOR_8_8;
418
419 case PIPE_FORMAT_R16_UNORM:
420 case PIPE_FORMAT_R16_SNORM:
421 case PIPE_FORMAT_R16_UINT:
422 case PIPE_FORMAT_R16_SINT:
423 case PIPE_FORMAT_A16_UNORM:
424 case PIPE_FORMAT_A16_SNORM:
425 case PIPE_FORMAT_A16_UINT:
426 case PIPE_FORMAT_A16_SINT:
427 case PIPE_FORMAT_L16_UNORM:
428 case PIPE_FORMAT_L16_SNORM:
429 case PIPE_FORMAT_L16_UINT:
430 case PIPE_FORMAT_L16_SINT:
431 case PIPE_FORMAT_I16_UNORM:
432 case PIPE_FORMAT_I16_SNORM:
433 case PIPE_FORMAT_I16_UINT:
434 case PIPE_FORMAT_I16_SINT:
435 return V_028C70_COLOR_16;
436
437 case PIPE_FORMAT_R16_FLOAT:
438 case PIPE_FORMAT_A16_FLOAT:
439 case PIPE_FORMAT_L16_FLOAT:
440 case PIPE_FORMAT_I16_FLOAT:
441 return V_028C70_COLOR_16_FLOAT;
442
443 /* 32-bit buffers. */
444 case PIPE_FORMAT_A8B8G8R8_SRGB:
445 case PIPE_FORMAT_A8B8G8R8_UNORM:
446 case PIPE_FORMAT_A8R8G8B8_UNORM:
447 case PIPE_FORMAT_B8G8R8A8_SRGB:
448 case PIPE_FORMAT_B8G8R8A8_UNORM:
449 case PIPE_FORMAT_B8G8R8X8_UNORM:
450 case PIPE_FORMAT_R8G8B8A8_SNORM:
451 case PIPE_FORMAT_R8G8B8A8_UNORM:
452 case PIPE_FORMAT_R8G8B8X8_UNORM:
453 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
454 case PIPE_FORMAT_X8B8G8R8_UNORM:
455 case PIPE_FORMAT_X8R8G8B8_UNORM:
456 case PIPE_FORMAT_R8G8B8_UNORM:
457 case PIPE_FORMAT_R8G8B8A8_SINT:
458 case PIPE_FORMAT_R8G8B8A8_UINT:
459 return V_028C70_COLOR_8_8_8_8;
460
461 case PIPE_FORMAT_R10G10B10A2_UNORM:
462 case PIPE_FORMAT_R10G10B10X2_SNORM:
463 case PIPE_FORMAT_B10G10R10A2_UNORM:
464 case PIPE_FORMAT_B10G10R10A2_UINT:
465 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
466 return V_028C70_COLOR_2_10_10_10;
467
468 case PIPE_FORMAT_Z24X8_UNORM:
469 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
470 return V_028C70_COLOR_8_24;
471
472 case PIPE_FORMAT_X8Z24_UNORM:
473 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
474 return V_028C70_COLOR_24_8;
475
476 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
477 return V_028C70_COLOR_X24_8_32_FLOAT;
478
479 case PIPE_FORMAT_R32_UINT:
480 case PIPE_FORMAT_R32_SINT:
481 case PIPE_FORMAT_A32_UINT:
482 case PIPE_FORMAT_A32_SINT:
483 case PIPE_FORMAT_L32_UINT:
484 case PIPE_FORMAT_L32_SINT:
485 case PIPE_FORMAT_I32_UINT:
486 case PIPE_FORMAT_I32_SINT:
487 return V_028C70_COLOR_32;
488
489 case PIPE_FORMAT_R32_FLOAT:
490 case PIPE_FORMAT_A32_FLOAT:
491 case PIPE_FORMAT_L32_FLOAT:
492 case PIPE_FORMAT_I32_FLOAT:
493 case PIPE_FORMAT_Z32_FLOAT:
494 return V_028C70_COLOR_32_FLOAT;
495
496 case PIPE_FORMAT_R16G16_FLOAT:
497 case PIPE_FORMAT_L16A16_FLOAT:
498 return V_028C70_COLOR_16_16_FLOAT;
499
500 case PIPE_FORMAT_R16G16_UNORM:
501 case PIPE_FORMAT_R16G16_SNORM:
502 case PIPE_FORMAT_R16G16_UINT:
503 case PIPE_FORMAT_R16G16_SINT:
504 case PIPE_FORMAT_L16A16_UNORM:
505 case PIPE_FORMAT_L16A16_SNORM:
506 case PIPE_FORMAT_L16A16_UINT:
507 case PIPE_FORMAT_L16A16_SINT:
508 return V_028C70_COLOR_16_16;
509
510 case PIPE_FORMAT_R11G11B10_FLOAT:
511 return V_028C70_COLOR_10_11_11_FLOAT;
512
513 /* 64-bit buffers. */
514 case PIPE_FORMAT_R16G16B16A16_UINT:
515 case PIPE_FORMAT_R16G16B16A16_SINT:
516 case PIPE_FORMAT_R16G16B16A16_UNORM:
517 case PIPE_FORMAT_R16G16B16A16_SNORM:
518 return V_028C70_COLOR_16_16_16_16;
519
520 case PIPE_FORMAT_R16G16B16A16_FLOAT:
521 return V_028C70_COLOR_16_16_16_16_FLOAT;
522
523 case PIPE_FORMAT_R32G32_FLOAT:
524 case PIPE_FORMAT_L32A32_FLOAT:
525 return V_028C70_COLOR_32_32_FLOAT;
526
527 case PIPE_FORMAT_R32G32_SINT:
528 case PIPE_FORMAT_R32G32_UINT:
529 case PIPE_FORMAT_L32A32_UINT:
530 case PIPE_FORMAT_L32A32_SINT:
531 return V_028C70_COLOR_32_32;
532
533 /* 128-bit buffers. */
534 case PIPE_FORMAT_R32G32B32A32_SNORM:
535 case PIPE_FORMAT_R32G32B32A32_UNORM:
536 case PIPE_FORMAT_R32G32B32A32_SINT:
537 case PIPE_FORMAT_R32G32B32A32_UINT:
538 return V_028C70_COLOR_32_32_32_32;
539 case PIPE_FORMAT_R32G32B32A32_FLOAT:
540 return V_028C70_COLOR_32_32_32_32_FLOAT;
541
542 /* YUV buffers. */
543 case PIPE_FORMAT_UYVY:
544 case PIPE_FORMAT_YUYV:
545 default:
546 return ~0U; /* Unsupported. */
547 }
548 }
549
550 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
551 {
552 if (R600_BIG_ENDIAN) {
553 switch(colorformat) {
554
555 /* 8-bit buffers. */
556 case V_028C70_COLOR_8:
557 return ENDIAN_NONE;
558
559 /* 16-bit buffers. */
560 case V_028C70_COLOR_5_6_5:
561 case V_028C70_COLOR_1_5_5_5:
562 case V_028C70_COLOR_4_4_4_4:
563 case V_028C70_COLOR_16:
564 case V_028C70_COLOR_8_8:
565 return ENDIAN_8IN16;
566
567 /* 32-bit buffers. */
568 case V_028C70_COLOR_8_8_8_8:
569 case V_028C70_COLOR_2_10_10_10:
570 case V_028C70_COLOR_8_24:
571 case V_028C70_COLOR_24_8:
572 case V_028C70_COLOR_32_FLOAT:
573 case V_028C70_COLOR_16_16_FLOAT:
574 case V_028C70_COLOR_16_16:
575 return ENDIAN_8IN32;
576
577 /* 64-bit buffers. */
578 case V_028C70_COLOR_16_16_16_16:
579 case V_028C70_COLOR_16_16_16_16_FLOAT:
580 return ENDIAN_8IN16;
581
582 case V_028C70_COLOR_32_32_FLOAT:
583 case V_028C70_COLOR_32_32:
584 case V_028C70_COLOR_X24_8_32_FLOAT:
585 return ENDIAN_8IN32;
586
587 /* 96-bit buffers. */
588 case V_028C70_COLOR_32_32_32_FLOAT:
589 /* 128-bit buffers. */
590 case V_028C70_COLOR_32_32_32_32_FLOAT:
591 case V_028C70_COLOR_32_32_32_32:
592 return ENDIAN_8IN32;
593 default:
594 return ENDIAN_NONE; /* Unsupported. */
595 }
596 } else {
597 return ENDIAN_NONE;
598 }
599 }
600
601 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
602 {
603 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
604 }
605
606 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
607 {
608 return r600_translate_colorformat(format) != ~0U &&
609 r600_translate_colorswap(format) != ~0U;
610 }
611
612 static bool r600_is_zs_format_supported(enum pipe_format format)
613 {
614 return r600_translate_dbformat(format) != ~0U;
615 }
616
617 boolean evergreen_is_format_supported(struct pipe_screen *screen,
618 enum pipe_format format,
619 enum pipe_texture_target target,
620 unsigned sample_count,
621 unsigned usage)
622 {
623 struct r600_screen *rscreen = (struct r600_screen*)screen;
624 unsigned retval = 0;
625
626 if (target >= PIPE_MAX_TEXTURE_TYPES) {
627 R600_ERR("r600: unsupported texture type %d\n", target);
628 return FALSE;
629 }
630
631 if (!util_format_is_supported(format, usage))
632 return FALSE;
633
634 if (sample_count > 1) {
635 if (rscreen->info.drm_minor < 19)
636 return FALSE;
637
638 switch (sample_count) {
639 case 2:
640 case 4:
641 case 8:
642 break;
643 default:
644 return FALSE;
645 }
646
647 /* require render-target support for multisample resources */
648 if (util_format_is_depth_or_stencil(format)) {
649 usage |= PIPE_BIND_DEPTH_STENCIL;
650 } else {
651 usage |= PIPE_BIND_RENDER_TARGET;
652 }
653 }
654
655 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
656 r600_is_sampler_format_supported(screen, format)) {
657 retval |= PIPE_BIND_SAMPLER_VIEW;
658 }
659
660 if ((usage & (PIPE_BIND_RENDER_TARGET |
661 PIPE_BIND_DISPLAY_TARGET |
662 PIPE_BIND_SCANOUT |
663 PIPE_BIND_SHARED)) &&
664 r600_is_colorbuffer_format_supported(format)) {
665 retval |= usage &
666 (PIPE_BIND_RENDER_TARGET |
667 PIPE_BIND_DISPLAY_TARGET |
668 PIPE_BIND_SCANOUT |
669 PIPE_BIND_SHARED);
670 }
671
672 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
673 r600_is_zs_format_supported(format)) {
674 retval |= PIPE_BIND_DEPTH_STENCIL;
675 }
676
677 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
678 r600_is_vertex_format_supported(format)) {
679 retval |= PIPE_BIND_VERTEX_BUFFER;
680 }
681
682 if (usage & PIPE_BIND_TRANSFER_READ)
683 retval |= PIPE_BIND_TRANSFER_READ;
684 if (usage & PIPE_BIND_TRANSFER_WRITE)
685 retval |= PIPE_BIND_TRANSFER_WRITE;
686
687 return retval == usage;
688 }
689
690 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
691 const struct pipe_blend_state *state, int mode)
692 {
693 struct r600_context *rctx = (struct r600_context *)ctx;
694 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
695 struct r600_pipe_state *rstate;
696 uint32_t color_control = 0, target_mask;
697 /* XXX there is more then 8 framebuffer */
698 unsigned blend_cntl[8];
699
700 if (blend == NULL) {
701 return NULL;
702 }
703
704 rstate = &blend->rstate;
705
706 rstate->id = R600_PIPE_STATE_BLEND;
707
708 target_mask = 0;
709 if (state->logicop_enable) {
710 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
711 } else {
712 color_control |= (0xcc << 16);
713 }
714 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
715 if (state->independent_blend_enable) {
716 for (int i = 0; i < 8; i++) {
717 target_mask |= (state->rt[i].colormask << (4 * i));
718 }
719 } else {
720 for (int i = 0; i < 8; i++) {
721 target_mask |= (state->rt[0].colormask << (4 * i));
722 }
723 }
724 blend->cb_target_mask = target_mask;
725
726 if (target_mask)
727 color_control |= S_028808_MODE(mode);
728 else
729 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
730
731 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
732 color_control);
733 /* only have dual source on MRT0 */
734 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
735 for (int i = 0; i < 8; i++) {
736 /* state->rt entries > 0 only written if independent blending */
737 const int j = state->independent_blend_enable ? i : 0;
738
739 unsigned eqRGB = state->rt[j].rgb_func;
740 unsigned srcRGB = state->rt[j].rgb_src_factor;
741 unsigned dstRGB = state->rt[j].rgb_dst_factor;
742 unsigned eqA = state->rt[j].alpha_func;
743 unsigned srcA = state->rt[j].alpha_src_factor;
744 unsigned dstA = state->rt[j].alpha_dst_factor;
745
746 blend_cntl[i] = 0;
747 if (!state->rt[j].blend_enable)
748 continue;
749
750 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
751 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
752 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
753 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
754
755 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
756 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
757 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
758 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
759 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
760 }
761 }
762 for (int i = 0; i < 8; i++) {
763 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
764 }
765
766 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK,
767 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
768 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
769 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
770 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
771 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
772
773 blend->alpha_to_one = state->alpha_to_one;
774 return rstate;
775 }
776
777 static void *evergreen_create_blend_state(struct pipe_context *ctx,
778 const struct pipe_blend_state *state)
779 {
780
781 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
782 }
783
784 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
785 const struct pipe_depth_stencil_alpha_state *state)
786 {
787 struct r600_context *rctx = (struct r600_context *)ctx;
788 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
789 unsigned db_depth_control, alpha_test_control, alpha_ref;
790 struct r600_pipe_state *rstate;
791
792 if (dsa == NULL) {
793 return NULL;
794 }
795
796 dsa->valuemask[0] = state->stencil[0].valuemask;
797 dsa->valuemask[1] = state->stencil[1].valuemask;
798 dsa->writemask[0] = state->stencil[0].writemask;
799 dsa->writemask[1] = state->stencil[1].writemask;
800
801 rstate = &dsa->rstate;
802
803 rstate->id = R600_PIPE_STATE_DSA;
804 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
805 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
806 S_028800_ZFUNC(state->depth.func);
807
808 /* stencil */
809 if (state->stencil[0].enabled) {
810 db_depth_control |= S_028800_STENCIL_ENABLE(1);
811 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
812 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
813 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
814 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
815
816 if (state->stencil[1].enabled) {
817 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
818 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
819 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
820 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
821 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
822 }
823 }
824
825 /* alpha */
826 alpha_test_control = 0;
827 alpha_ref = 0;
828 if (state->alpha.enabled) {
829 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
830 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
831 alpha_ref = fui(state->alpha.ref_value);
832 }
833 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
834 dsa->alpha_ref = alpha_ref;
835
836 /* misc */
837 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
838 return rstate;
839 }
840
841 static void *evergreen_create_rs_state(struct pipe_context *ctx,
842 const struct pipe_rasterizer_state *state)
843 {
844 struct r600_context *rctx = (struct r600_context *)ctx;
845 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
846 struct r600_pipe_state *rstate;
847 unsigned tmp;
848 unsigned prov_vtx = 1, polygon_dual_mode;
849 float psize_min, psize_max;
850
851 if (rs == NULL) {
852 return NULL;
853 }
854
855 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
856 state->fill_back != PIPE_POLYGON_MODE_FILL);
857
858 if (state->flatshade_first)
859 prov_vtx = 0;
860
861 rstate = &rs->rstate;
862 rs->flatshade = state->flatshade;
863 rs->sprite_coord_enable = state->sprite_coord_enable;
864 rs->two_side = state->light_twoside;
865 rs->clip_plane_enable = state->clip_plane_enable;
866 rs->pa_sc_line_stipple = state->line_stipple_enable ?
867 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
868 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
869 rs->pa_cl_clip_cntl =
870 S_028810_PS_UCP_MODE(3) |
871 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
872 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
873 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
874 rs->multisample_enable = state->multisample;
875
876 /* offset */
877 rs->offset_units = state->offset_units;
878 rs->offset_scale = state->offset_scale * 12.0f;
879
880 rstate->id = R600_PIPE_STATE_RASTERIZER;
881 tmp = S_0286D4_FLAT_SHADE_ENA(1);
882 if (state->sprite_coord_enable) {
883 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
884 S_0286D4_PNT_SPRITE_OVRD_X(2) |
885 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
886 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
887 S_0286D4_PNT_SPRITE_OVRD_W(1);
888 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
889 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
890 }
891 }
892 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
893
894 /* point size 12.4 fixed point */
895 tmp = (unsigned)(state->point_size * 8.0);
896 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
897
898 if (state->point_size_per_vertex) {
899 psize_min = util_get_min_point_size(state);
900 psize_max = 8192;
901 } else {
902 /* Force the point size to be as if the vertex output was disabled. */
903 psize_min = state->point_size;
904 psize_max = state->point_size;
905 }
906 /* Divide by two, because 0.5 = 1 pixel. */
907 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
908 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
909 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
910
911 tmp = (unsigned)state->line_width * 8;
912 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
913 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
914 S_028A48_MSAA_ENABLE(state->multisample) |
915 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
916 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
917
918 if (rctx->chip_class == CAYMAN) {
919 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
920 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
921 } else {
922 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
923 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
924 S_028C08_QUANT_MODE(V_028C08_X_1_4096TH));
925 }
926 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
927 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
928 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
929 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
930 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
931 S_028814_FACE(!state->front_ccw) |
932 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
933 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
934 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
935 S_028814_POLY_MODE(polygon_dual_mode) |
936 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
937 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
938 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
939 return rstate;
940 }
941
942 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
943 const struct pipe_sampler_state *state)
944 {
945 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
946 union util_color uc;
947 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
948
949 if (ss == NULL) {
950 return NULL;
951 }
952
953 /* directly into sampler avoid r6xx code to emit useless reg */
954 ss->seamless_cube_map = false;
955 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
956 ss->border_color_use = false;
957 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
958 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
959 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
960 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
961 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
962 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
963 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
964 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
965 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
966 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
967 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
968 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
969 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
970 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
971 ss->tex_sampler_words[2] = S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
972 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
973 S_03C008_TYPE(1);
974 if (uc.ui) {
975 ss->border_color_use = true;
976 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
977 ss->border_color[0] = fui(state->border_color.f[0]);
978 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
979 ss->border_color[1] = fui(state->border_color.f[1]);
980 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
981 ss->border_color[2] = fui(state->border_color.f[2]);
982 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
983 ss->border_color[3] = fui(state->border_color.f[3]);
984 }
985 return ss;
986 }
987
988 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
989 struct pipe_resource *texture,
990 const struct pipe_sampler_view *state)
991 {
992 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
993 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
994 struct r600_texture *tmp = (struct r600_texture*)texture;
995 unsigned format, endian;
996 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
997 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
998 unsigned height, depth, width;
999 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1000
1001 if (view == NULL)
1002 return NULL;
1003
1004 /* initialize base object */
1005 view->base = *state;
1006 view->base.texture = NULL;
1007 pipe_reference(NULL, &texture->reference);
1008 view->base.texture = texture;
1009 view->base.reference.count = 1;
1010 view->base.context = ctx;
1011
1012 swizzle[0] = state->swizzle_r;
1013 swizzle[1] = state->swizzle_g;
1014 swizzle[2] = state->swizzle_b;
1015 swizzle[3] = state->swizzle_a;
1016
1017 format = r600_translate_texformat(ctx->screen, state->format,
1018 swizzle,
1019 &word4, &yuv_format);
1020 assert(format != ~0);
1021 if (format == ~0) {
1022 FREE(view);
1023 return NULL;
1024 }
1025
1026 if (tmp->is_depth && !tmp->is_flushing_texture) {
1027 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1028 FREE(view);
1029 return NULL;
1030 }
1031 tmp = tmp->flushed_depth_texture;
1032 }
1033
1034 endian = r600_colorformat_endian_swap(format);
1035
1036 width = tmp->surface.level[0].npix_x;
1037 height = tmp->surface.level[0].npix_y;
1038 depth = tmp->surface.level[0].npix_z;
1039 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1040 tile_type = tmp->tile_type;
1041
1042 switch (tmp->surface.level[0].mode) {
1043 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1044 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1045 break;
1046 case RADEON_SURF_MODE_2D:
1047 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1048 break;
1049 case RADEON_SURF_MODE_1D:
1050 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1051 break;
1052 case RADEON_SURF_MODE_LINEAR:
1053 default:
1054 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1055 break;
1056 }
1057 tile_split = tmp->surface.tile_split;
1058 macro_aspect = tmp->surface.mtilea;
1059 bankw = tmp->surface.bankw;
1060 bankh = tmp->surface.bankh;
1061 tile_split = eg_tile_split(tile_split);
1062 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1063 bankw = eg_bank_wh(bankw);
1064 bankh = eg_bank_wh(bankh);
1065
1066 /* 128 bit formats require tile type = 1 */
1067 if (rscreen->chip_class == CAYMAN) {
1068 if (util_format_get_blocksize(state->format) >= 16)
1069 tile_type = 1;
1070 }
1071 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1072
1073 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1074 height = 1;
1075 depth = texture->array_size;
1076 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1077 depth = texture->array_size;
1078 }
1079
1080 view->tex_resource = &tmp->resource;
1081 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1082 S_030000_PITCH((pitch / 8) - 1) |
1083 S_030000_TEX_WIDTH(width - 1));
1084 if (rscreen->chip_class == CAYMAN)
1085 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1086 else
1087 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1088 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1089 S_030004_TEX_DEPTH(depth - 1) |
1090 S_030004_ARRAY_MODE(array_mode));
1091 view->tex_resource_words[2] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1092 if (state->u.tex.last_level && texture->nr_samples <= 1) {
1093 view->tex_resource_words[3] = (tmp->surface.level[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1094 } else {
1095 view->tex_resource_words[3] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1096 }
1097 view->tex_resource_words[4] = (word4 |
1098 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1099 S_030010_ENDIAN_SWAP(endian));
1100 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1101 S_030014_LAST_ARRAY(state->u.tex.last_layer);
1102 if (texture->nr_samples > 1) {
1103 unsigned log_samples = util_logbase2(texture->nr_samples);
1104 if (rscreen->chip_class == CAYMAN) {
1105 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
1106 }
1107 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1108 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
1109 } else {
1110 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(state->u.tex.first_level);
1111 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(state->u.tex.last_level);
1112 }
1113 /* aniso max 16 samples */
1114 view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
1115 (S_030018_TILE_SPLIT(tile_split));
1116 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1117 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1118 S_03001C_BANK_WIDTH(bankw) |
1119 S_03001C_BANK_HEIGHT(bankh) |
1120 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1121 S_03001C_NUM_BANKS(nbanks);
1122 return &view->base;
1123 }
1124
1125 static void evergreen_set_clip_state(struct pipe_context *ctx,
1126 const struct pipe_clip_state *state)
1127 {
1128 struct r600_context *rctx = (struct r600_context *)ctx;
1129 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1130 struct pipe_constant_buffer cb;
1131
1132 if (rstate == NULL)
1133 return;
1134
1135 rctx->clip = *state;
1136 rstate->id = R600_PIPE_STATE_CLIP;
1137 for (int i = 0; i < 6; i++) {
1138 r600_pipe_state_add_reg(rstate,
1139 R_0285BC_PA_CL_UCP0_X + i * 16,
1140 fui(state->ucp[i][0]));
1141 r600_pipe_state_add_reg(rstate,
1142 R_0285C0_PA_CL_UCP0_Y + i * 16,
1143 fui(state->ucp[i][1]) );
1144 r600_pipe_state_add_reg(rstate,
1145 R_0285C4_PA_CL_UCP0_Z + i * 16,
1146 fui(state->ucp[i][2]));
1147 r600_pipe_state_add_reg(rstate,
1148 R_0285C8_PA_CL_UCP0_W + i * 16,
1149 fui(state->ucp[i][3]));
1150 }
1151
1152 free(rctx->states[R600_PIPE_STATE_CLIP]);
1153 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1154 r600_context_pipe_state_set(rctx, rstate);
1155
1156 cb.buffer = NULL;
1157 cb.user_buffer = state->ucp;
1158 cb.buffer_offset = 0;
1159 cb.buffer_size = 4*4*8;
1160 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1161 pipe_resource_reference(&cb.buffer, NULL);
1162 }
1163
1164 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1165 const struct pipe_poly_stipple *state)
1166 {
1167 }
1168
1169 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1170 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1171 uint32_t *tl, uint32_t *br)
1172 {
1173 /* EG hw workaround */
1174 if (br_x == 0)
1175 tl_x = 1;
1176 if (br_y == 0)
1177 tl_y = 1;
1178
1179 /* cayman hw workaround */
1180 if (rctx->chip_class == CAYMAN) {
1181 if (br_x == 1 && br_y == 1)
1182 br_x = 2;
1183 }
1184
1185 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1186 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1187 }
1188
1189 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1190 const struct pipe_scissor_state *state)
1191 {
1192 struct r600_context *rctx = (struct r600_context *)ctx;
1193 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1194 uint32_t tl, br;
1195
1196 if (rstate == NULL)
1197 return;
1198
1199 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1200
1201 rstate->id = R600_PIPE_STATE_SCISSOR;
1202 r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1203 r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1204
1205 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1206 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1207 r600_context_pipe_state_set(rctx, rstate);
1208 }
1209
1210 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1211 const struct pipe_viewport_state *state)
1212 {
1213 struct r600_context *rctx = (struct r600_context *)ctx;
1214 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1215
1216 if (rstate == NULL)
1217 return;
1218
1219 rctx->viewport = *state;
1220 rstate->id = R600_PIPE_STATE_VIEWPORT;
1221 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1222 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1223 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1224 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1225 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1226 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1227
1228 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1229 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1230 r600_context_pipe_state_set(rctx, rstate);
1231 }
1232
1233 void evergreen_init_color_surface(struct r600_context *rctx,
1234 struct r600_surface *surf)
1235 {
1236 struct r600_screen *rscreen = rctx->screen;
1237 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1238 struct pipe_resource *pipe_tex = surf->base.texture;
1239 unsigned level = surf->base.u.tex.level;
1240 unsigned pitch, slice;
1241 unsigned color_info, color_attrib, color_dim = 0;
1242 unsigned format, swap, ntype, endian;
1243 uint64_t offset, base_offset;
1244 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1245 const struct util_format_description *desc;
1246 int i;
1247 bool blend_clamp = 0, blend_bypass = 0;
1248
1249 if (rtex->is_depth && !rtex->is_flushing_texture) {
1250 r600_init_flushed_depth_texture(&rctx->context, pipe_tex, NULL);
1251 rtex = rtex->flushed_depth_texture;
1252 assert(rtex);
1253 }
1254
1255 offset = rtex->surface.level[level].offset;
1256 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1257 offset += rtex->surface.level[level].slice_size *
1258 surf->base.u.tex.first_layer;
1259 }
1260 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1261 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1262 if (slice) {
1263 slice = slice - 1;
1264 }
1265 color_info = 0;
1266 switch (rtex->surface.level[level].mode) {
1267 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1268 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1269 tile_type = 1;
1270 break;
1271 case RADEON_SURF_MODE_1D:
1272 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1273 tile_type = rtex->tile_type;
1274 break;
1275 case RADEON_SURF_MODE_2D:
1276 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1277 tile_type = rtex->tile_type;
1278 break;
1279 case RADEON_SURF_MODE_LINEAR:
1280 default:
1281 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1282 tile_type = 1;
1283 break;
1284 }
1285 tile_split = rtex->surface.tile_split;
1286 macro_aspect = rtex->surface.mtilea;
1287 bankw = rtex->surface.bankw;
1288 bankh = rtex->surface.bankh;
1289 fmask_bankh = rtex->fmask_bank_height;
1290 tile_split = eg_tile_split(tile_split);
1291 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1292 bankw = eg_bank_wh(bankw);
1293 bankh = eg_bank_wh(bankh);
1294 fmask_bankh = eg_bank_wh(fmask_bankh);
1295
1296 /* 128 bit formats require tile type = 1 */
1297 if (rscreen->chip_class == CAYMAN) {
1298 if (util_format_get_blocksize(surf->base.format) >= 16)
1299 tile_type = 1;
1300 }
1301 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1302 desc = util_format_description(surf->base.format);
1303 for (i = 0; i < 4; i++) {
1304 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1305 break;
1306 }
1307 }
1308
1309 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1310 S_028C74_NUM_BANKS(nbanks) |
1311 S_028C74_BANK_WIDTH(bankw) |
1312 S_028C74_BANK_HEIGHT(bankh) |
1313 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1314 S_028C74_NON_DISP_TILING_ORDER(tile_type) |
1315 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1316
1317 if (rctx->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1318 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1319 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1320 S_028C74_NUM_FRAGMENTS(log_samples);
1321 }
1322
1323 ntype = V_028C70_NUMBER_UNORM;
1324 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1325 ntype = V_028C70_NUMBER_SRGB;
1326 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1327 if (desc->channel[i].normalized)
1328 ntype = V_028C70_NUMBER_SNORM;
1329 else if (desc->channel[i].pure_integer)
1330 ntype = V_028C70_NUMBER_SINT;
1331 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1332 if (desc->channel[i].normalized)
1333 ntype = V_028C70_NUMBER_UNORM;
1334 else if (desc->channel[i].pure_integer)
1335 ntype = V_028C70_NUMBER_UINT;
1336 }
1337
1338 format = r600_translate_colorformat(surf->base.format);
1339 assert(format != ~0);
1340
1341 swap = r600_translate_colorswap(surf->base.format);
1342 assert(swap != ~0);
1343
1344 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1345 endian = ENDIAN_NONE;
1346 } else {
1347 endian = r600_colorformat_endian_swap(format);
1348 }
1349
1350 /* blend clamp should be set for all NORM/SRGB types */
1351 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1352 ntype == V_028C70_NUMBER_SRGB)
1353 blend_clamp = 1;
1354
1355 /* set blend bypass according to docs if SINT/UINT or
1356 8/24 COLOR variants */
1357 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1358 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1359 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1360 blend_clamp = 0;
1361 blend_bypass = 1;
1362 }
1363
1364 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1365
1366 color_info |= S_028C70_FORMAT(format) |
1367 S_028C70_COMP_SWAP(swap) |
1368 S_028C70_BLEND_CLAMP(blend_clamp) |
1369 S_028C70_BLEND_BYPASS(blend_bypass) |
1370 S_028C70_NUMBER_TYPE(ntype) |
1371 S_028C70_ENDIAN(endian);
1372
1373 if (rtex->is_rat) {
1374 color_info |= S_028C70_RAT(1);
1375 color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0)
1376 | S_028C78_HEIGHT_MAX(pipe_tex->height0);
1377 }
1378
1379 /* EXPORT_NORM is an optimzation that can be enabled for better
1380 * performance in certain cases.
1381 * EXPORT_NORM can be enabled if:
1382 * - 11-bit or smaller UNORM/SNORM/SRGB
1383 * - 16-bit or smaller FLOAT
1384 */
1385 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1386 ((desc->channel[i].size < 12 &&
1387 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1388 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1389 (desc->channel[i].size < 17 &&
1390 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1391 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1392 surf->export_16bpc = true;
1393 }
1394
1395 if (rtex->fmask_size && rtex->cmask_size) {
1396 color_info |= S_028C70_COMPRESSION(1) | S_028C70_FAST_CLEAR(1);
1397 }
1398
1399 base_offset = r600_resource_va(rctx->context.screen, pipe_tex);
1400
1401 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1402 surf->cb_color_base = (base_offset + offset) >> 8;
1403 surf->cb_color_dim = color_dim;
1404 surf->cb_color_info = color_info;
1405 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1406 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1407 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1408 surf->cb_color_view = 0;
1409 } else {
1410 surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1411 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1412 }
1413 surf->cb_color_attrib = color_attrib;
1414 if (rtex->fmask_size && rtex->cmask_size) {
1415 surf->cb_color_fmask = (base_offset + rtex->fmask_offset) >> 8;
1416 surf->cb_color_cmask = (base_offset + rtex->cmask_offset) >> 8;
1417 } else {
1418 surf->cb_color_fmask = surf->cb_color_base;
1419 surf->cb_color_cmask = surf->cb_color_base;
1420 }
1421 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1422 surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask_slice_tile_max);
1423
1424 surf->color_initialized = true;
1425 }
1426
1427 static void evergreen_init_depth_surface(struct r600_context *rctx,
1428 struct r600_surface *surf)
1429 {
1430 struct r600_screen *rscreen = rctx->screen;
1431 struct pipe_screen *screen = &rscreen->screen;
1432 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1433 uint64_t offset;
1434 unsigned level, pitch, slice, format, array_mode;
1435 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1436
1437 level = surf->base.u.tex.level;
1438 format = r600_translate_dbformat(surf->base.format);
1439 assert(format != ~0);
1440
1441 offset = r600_resource_va(screen, surf->base.texture);
1442 offset += rtex->surface.level[level].offset;
1443 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1444 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1445 if (slice) {
1446 slice = slice - 1;
1447 }
1448 switch (rtex->surface.level[level].mode) {
1449 case RADEON_SURF_MODE_2D:
1450 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1451 break;
1452 case RADEON_SURF_MODE_1D:
1453 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1454 case RADEON_SURF_MODE_LINEAR:
1455 default:
1456 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1457 break;
1458 }
1459 tile_split = rtex->surface.tile_split;
1460 macro_aspect = rtex->surface.mtilea;
1461 bankw = rtex->surface.bankw;
1462 bankh = rtex->surface.bankh;
1463 tile_split = eg_tile_split(tile_split);
1464 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1465 bankw = eg_bank_wh(bankw);
1466 bankh = eg_bank_wh(bankh);
1467 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1468 offset >>= 8;
1469
1470 surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1471 S_028040_FORMAT(format) |
1472 S_028040_TILE_SPLIT(tile_split)|
1473 S_028040_NUM_BANKS(nbanks) |
1474 S_028040_BANK_WIDTH(bankw) |
1475 S_028040_BANK_HEIGHT(bankh) |
1476 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1477 if (rscreen->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1478 surf->db_depth_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1479 }
1480 surf->db_depth_base = offset;
1481 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1482 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1483 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1484 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1485
1486 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1487 uint64_t stencil_offset = rtex->surface.stencil_offset;
1488 unsigned stile_split = rtex->surface.stencil_tile_split;
1489
1490 stile_split = eg_tile_split(stile_split);
1491 stencil_offset += r600_resource_va(screen, surf->base.texture);
1492 stencil_offset += rtex->surface.level[level].offset / 4;
1493 stencil_offset >>= 8;
1494
1495 surf->db_stencil_base = stencil_offset;
1496 surf->db_stencil_info = 1 | S_028044_TILE_SPLIT(stile_split);
1497 } else {
1498 surf->db_stencil_base = offset;
1499 surf->db_stencil_info = 1;
1500 }
1501
1502 surf->depth_initialized = true;
1503 }
1504
1505 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1506 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1507 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1508 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1509 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1510
1511 static uint32_t evergreen_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1512 {
1513 /* 2xMSAA
1514 * There are two locations (-4, 4), (4, -4). */
1515 static uint32_t sample_locs_2x[] = {
1516 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1517 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1518 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1519 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1520 };
1521 static unsigned max_dist_2x = 4;
1522 /* 4xMSAA
1523 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1524 static uint32_t sample_locs_4x[] = {
1525 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1526 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1527 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1528 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1529 };
1530 static unsigned max_dist_4x = 6;
1531 /* 8xMSAA */
1532 static uint32_t sample_locs_8x[] = {
1533 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1534 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1535 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1536 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1537 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1538 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1539 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1540 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1541 };
1542 static unsigned max_dist_8x = 8;
1543 struct r600_context *rctx = (struct r600_context *)ctx;
1544 unsigned i;
1545
1546 switch (nsample) {
1547 case 2:
1548 for (i = 0; i < Elements(sample_locs_2x); i++) {
1549 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
1550 sample_locs_2x[i]);
1551 }
1552 return max_dist_2x;
1553 case 4:
1554 for (i = 0; i < Elements(sample_locs_4x); i++) {
1555 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
1556 sample_locs_4x[i]);
1557 }
1558 return max_dist_4x;
1559 case 8:
1560 for (i = 0; i < Elements(sample_locs_8x); i++) {
1561 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
1562 sample_locs_8x[i]);
1563 }
1564 return max_dist_8x;
1565 default:
1566 R600_ERR("Invalid nr_samples %i\n", nsample);
1567 return 0;
1568 }
1569 }
1570
1571 static uint32_t cayman_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1572 {
1573 /* 2xMSAA
1574 * There are two locations (-4, 4), (4, -4). */
1575 static uint32_t sample_locs_2x[] = {
1576 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1577 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1578 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1579 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1580 };
1581 static unsigned max_dist_2x = 4;
1582 /* 4xMSAA
1583 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1584 static uint32_t sample_locs_4x[] = {
1585 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1586 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1587 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1588 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1589 };
1590 static unsigned max_dist_4x = 6;
1591 /* 8xMSAA */
1592 static uint32_t sample_locs_8x[] = {
1593 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1594 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1595 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1596 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1597 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1598 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1599 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1600 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1601 };
1602 static unsigned max_dist_8x = 8;
1603 /* 16xMSAA */
1604 static uint32_t sample_locs_16x[] = {
1605 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1606 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1607 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1608 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1609 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1610 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1611 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1612 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1613 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1614 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1615 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1616 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1617 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1618 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1619 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1620 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1621 };
1622 static unsigned max_dist_16x = 8;
1623 struct r600_context *rctx = (struct r600_context *)ctx;
1624 uint32_t max_dist, num_regs, *sample_locs;
1625
1626 switch (nsample) {
1627 case 2:
1628 sample_locs = sample_locs_2x;
1629 num_regs = Elements(sample_locs_2x);
1630 max_dist = max_dist_2x;
1631 break;
1632 case 4:
1633 sample_locs = sample_locs_4x;
1634 num_regs = Elements(sample_locs_4x);
1635 max_dist = max_dist_4x;
1636 break;
1637 case 8:
1638 sample_locs = sample_locs_8x;
1639 num_regs = Elements(sample_locs_8x);
1640 max_dist = max_dist_8x;
1641 break;
1642 case 16:
1643 sample_locs = sample_locs_16x;
1644 num_regs = Elements(sample_locs_16x);
1645 max_dist = max_dist_16x;
1646 break;
1647 default:
1648 R600_ERR("Invalid nr_samples %i\n", nsample);
1649 return 0;
1650 }
1651
1652 r600_pipe_state_add_reg(rstate, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs[0]);
1653 r600_pipe_state_add_reg(rstate, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs[1]);
1654 r600_pipe_state_add_reg(rstate, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs[2]);
1655 r600_pipe_state_add_reg(rstate, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs[3]);
1656 if (num_regs <= 8) {
1657 r600_pipe_state_add_reg(rstate, CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs[4]);
1658 r600_pipe_state_add_reg(rstate, CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs[5]);
1659 r600_pipe_state_add_reg(rstate, CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs[6]);
1660 r600_pipe_state_add_reg(rstate, CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs[7]);
1661 }
1662 if (num_regs <= 16) {
1663 r600_pipe_state_add_reg(rstate, CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, sample_locs[8]);
1664 r600_pipe_state_add_reg(rstate, CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, sample_locs[9]);
1665 r600_pipe_state_add_reg(rstate, CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, sample_locs[10]);
1666 r600_pipe_state_add_reg(rstate, CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, sample_locs[11]);
1667 r600_pipe_state_add_reg(rstate, CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, sample_locs[12]);
1668 r600_pipe_state_add_reg(rstate, CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, sample_locs[13]);
1669 r600_pipe_state_add_reg(rstate, CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, sample_locs[14]);
1670 r600_pipe_state_add_reg(rstate, CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, sample_locs[15]);
1671 }
1672 return max_dist;
1673 }
1674
1675 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1676 const struct pipe_framebuffer_state *state)
1677 {
1678 struct r600_context *rctx = (struct r600_context *)ctx;
1679 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1680 struct r600_surface *surf;
1681 struct r600_resource *res;
1682 struct r600_texture *rtex;
1683 uint32_t tl, br, i, nr_samples, log_samples;
1684
1685 if (rstate == NULL)
1686 return;
1687
1688 if (rctx->framebuffer.nr_cbufs) {
1689 rctx->flags |= R600_CONTEXT_CB_FLUSH;
1690 }
1691 if (rctx->framebuffer.zsbuf) {
1692 rctx->flags |= R600_CONTEXT_DB_FLUSH;
1693 }
1694
1695 /* unreference old buffer and reference new one */
1696 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1697
1698 util_copy_framebuffer_state(&rctx->framebuffer, state);
1699
1700 /* Colorbuffers. */
1701 rctx->export_16bpc = true;
1702 rctx->nr_cbufs = state->nr_cbufs;
1703 rctx->cb0_is_integer = state->nr_cbufs &&
1704 util_format_is_pure_integer(state->cbufs[0]->format);
1705 rctx->compressed_cb_mask = 0;
1706
1707 for (i = 0; i < state->nr_cbufs; i++) {
1708 surf = (struct r600_surface*)state->cbufs[i];
1709 res = (struct r600_resource*)surf->base.texture;
1710 rtex = (struct r600_texture*)res;
1711
1712 if (!surf->color_initialized) {
1713 evergreen_init_color_surface(rctx, surf);
1714 }
1715
1716 if (!surf->export_16bpc) {
1717 rctx->export_16bpc = false;
1718 }
1719
1720 r600_pipe_state_add_reg_bo(rstate, R_028C60_CB_COLOR0_BASE + i * 0x3C,
1721 surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1722 r600_pipe_state_add_reg(rstate, R_028C78_CB_COLOR0_DIM + i * 0x3C,
1723 surf->cb_color_dim);
1724 r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1725 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1726 r600_pipe_state_add_reg(rstate, R_028C64_CB_COLOR0_PITCH + i * 0x3C,
1727 surf->cb_color_pitch);
1728 r600_pipe_state_add_reg(rstate, R_028C68_CB_COLOR0_SLICE + i * 0x3C,
1729 surf->cb_color_slice);
1730 r600_pipe_state_add_reg(rstate, R_028C6C_CB_COLOR0_VIEW + i * 0x3C,
1731 surf->cb_color_view);
1732 r600_pipe_state_add_reg_bo(rstate, R_028C74_CB_COLOR0_ATTRIB + i * 0x3C,
1733 surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
1734 r600_pipe_state_add_reg_bo(rstate, R_028C7C_CB_COLOR0_CMASK + i * 0x3c,
1735 surf->cb_color_cmask, res, RADEON_USAGE_READWRITE);
1736 r600_pipe_state_add_reg(rstate, R_028C80_CB_COLOR0_CMASK_SLICE + i * 0x3c,
1737 surf->cb_color_cmask_slice);
1738 r600_pipe_state_add_reg_bo(rstate, R_028C84_CB_COLOR0_FMASK + i * 0x3c,
1739 surf->cb_color_fmask, res, RADEON_USAGE_READWRITE);
1740 r600_pipe_state_add_reg(rstate, R_028C88_CB_COLOR0_FMASK_SLICE + i * 0x3c,
1741 surf->cb_color_fmask_slice);
1742
1743 /* Cayman can fetch from a compressed MSAA colorbuffer,
1744 * so it's pointless to track them. */
1745 if (rctx->chip_class != CAYMAN && rtex->fmask_size && rtex->cmask_size) {
1746 rctx->compressed_cb_mask |= 1 << i;
1747 }
1748 }
1749 /* set CB_COLOR1_INFO for possible dual-src blending */
1750 if (i == 1 && !((struct r600_texture*)res)->is_rat) {
1751 r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1752 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1753 i++;
1754 }
1755 for (; i < 8 ; i++) {
1756 r600_pipe_state_add_reg(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1757 }
1758
1759 /* Update alpha-test state dependencies.
1760 * Alpha-test is done on the first colorbuffer only. */
1761 if (state->nr_cbufs) {
1762 surf = (struct r600_surface*)state->cbufs[0];
1763 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1764 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1765 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1766 }
1767 if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
1768 rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
1769 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1770 }
1771 }
1772
1773 /* ZS buffer. */
1774 if (state->zsbuf) {
1775 surf = (struct r600_surface*)state->zsbuf;
1776 res = (struct r600_resource*)surf->base.texture;
1777
1778 if (!surf->depth_initialized) {
1779 evergreen_init_depth_surface(rctx, surf);
1780 }
1781
1782 r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE, surf->db_depth_base,
1783 res, RADEON_USAGE_READWRITE);
1784 r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base,
1785 res, RADEON_USAGE_READWRITE);
1786 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, surf->db_depth_view);
1787
1788 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base,
1789 res, RADEON_USAGE_READWRITE);
1790 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE, surf->db_stencil_base,
1791 res, RADEON_USAGE_READWRITE);
1792 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO, surf->db_stencil_info,
1793 res, RADEON_USAGE_READWRITE);
1794
1795 r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, surf->db_depth_info,
1796 res, RADEON_USAGE_READWRITE);
1797 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE, surf->db_depth_size);
1798 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, surf->db_depth_slice);
1799 }
1800
1801 /* Framebuffer dimensions. */
1802 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1803
1804 r600_pipe_state_add_reg(rstate,
1805 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1806 r600_pipe_state_add_reg(rstate,
1807 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1808
1809 /* Multisampling */
1810 if (state->nr_cbufs)
1811 nr_samples = state->cbufs[0]->texture->nr_samples;
1812 else if (state->zsbuf)
1813 nr_samples = state->zsbuf->texture->nr_samples;
1814 else
1815 nr_samples = 0;
1816
1817 if (nr_samples > 1) {
1818 unsigned line_cntl = S_028C00_LAST_PIXEL(1) |
1819 S_028C00_EXPAND_LINE_WIDTH(1);
1820 log_samples = util_logbase2(nr_samples);
1821
1822 if (rctx->chip_class == CAYMAN) {
1823 unsigned max_dist = cayman_set_ms_pos(ctx, rstate, nr_samples);
1824
1825 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, line_cntl);
1826 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1827 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1828 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
1829 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
1830 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA,
1831 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1832 S_028804_PS_ITER_SAMPLES(log_samples) |
1833 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1834 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
1835 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1836 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1837 } else {
1838 unsigned max_dist = evergreen_set_ms_pos(ctx, rstate, nr_samples);
1839
1840 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, line_cntl);
1841 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1842 S_028C04_MSAA_NUM_SAMPLES(log_samples) |
1843 S_028C04_MAX_SAMPLE_DIST(max_dist));
1844 }
1845 } else {
1846 log_samples = 0;
1847
1848 if (rctx->chip_class == CAYMAN) {
1849 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1850 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG, 0);
1851 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA,
1852 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1853 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1854
1855 } else {
1856 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1857 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
1858 }
1859 }
1860
1861 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1862 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1863 r600_context_pipe_state_set(rctx, rstate);
1864
1865 if (state->zsbuf) {
1866 evergreen_polygon_offset_update(rctx);
1867 }
1868
1869 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1870 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1871 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1872 }
1873
1874 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1875 rctx->alphatest_state.bypass = false;
1876 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1877 }
1878
1879 if (rctx->chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) {
1880 rctx->db_misc_state.log_samples = log_samples;
1881 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1882 }
1883 }
1884
1885 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1886 {
1887 struct radeon_winsys_cs *cs = rctx->cs;
1888 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1889 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1890 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1891
1892 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1893 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1894 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
1895 * will assure that the alpha-test will work even if there is
1896 * no colorbuffer bound. */
1897 r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1898 }
1899
1900 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1901 {
1902 struct radeon_winsys_cs *cs = rctx->cs;
1903 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1904 unsigned db_render_control = 0;
1905 unsigned db_count_control = 0;
1906 unsigned db_render_override =
1907 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1908 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1909 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1910
1911 if (a->occlusion_query_enabled) {
1912 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1913 if (rctx->chip_class == CAYMAN) {
1914 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1915 }
1916 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1917 }
1918
1919 if (a->flush_depthstencil_through_cb) {
1920 assert(a->copy_depth || a->copy_stencil);
1921
1922 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1923 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1924 S_028000_COPY_CENTROID(1) |
1925 S_028000_COPY_SAMPLE(a->copy_sample);
1926 }
1927
1928 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1929 r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1930 r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1931 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1932 }
1933
1934 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1935 struct r600_vertexbuf_state *state,
1936 unsigned resource_offset,
1937 unsigned pkt_flags)
1938 {
1939 struct radeon_winsys_cs *cs = rctx->cs;
1940 uint32_t dirty_mask = state->dirty_mask;
1941
1942 while (dirty_mask) {
1943 struct pipe_vertex_buffer *vb;
1944 struct r600_resource *rbuffer;
1945 uint64_t va;
1946 unsigned buffer_index = u_bit_scan(&dirty_mask);
1947
1948 vb = &state->vb[buffer_index];
1949 rbuffer = (struct r600_resource*)vb->buffer;
1950 assert(rbuffer);
1951
1952 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1953 va += vb->buffer_offset;
1954
1955 /* fetch resources start at index 992 */
1956 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1957 r600_write_value(cs, (resource_offset + buffer_index) * 8);
1958 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1959 r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1960 r600_write_value(cs, /* RESOURCEi_WORD2 */
1961 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1962 S_030008_STRIDE(vb->stride) |
1963 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1964 r600_write_value(cs, /* RESOURCEi_WORD3 */
1965 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1966 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1967 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1968 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1969 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1970 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1971 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1972 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1973
1974 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1975 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1976 }
1977 state->dirty_mask = 0;
1978 }
1979
1980 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1981 {
1982 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
1983 }
1984
1985 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1986 {
1987 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
1988 RADEON_CP_PACKET3_COMPUTE_MODE);
1989 }
1990
1991 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1992 struct r600_constbuf_state *state,
1993 unsigned buffer_id_base,
1994 unsigned reg_alu_constbuf_size,
1995 unsigned reg_alu_const_cache)
1996 {
1997 struct radeon_winsys_cs *cs = rctx->cs;
1998 uint32_t dirty_mask = state->dirty_mask;
1999
2000 while (dirty_mask) {
2001 struct pipe_constant_buffer *cb;
2002 struct r600_resource *rbuffer;
2003 uint64_t va;
2004 unsigned buffer_index = ffs(dirty_mask) - 1;
2005
2006 cb = &state->cb[buffer_index];
2007 rbuffer = (struct r600_resource*)cb->buffer;
2008 assert(rbuffer);
2009
2010 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
2011 va += cb->buffer_offset;
2012
2013 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2014 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
2015 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
2016
2017 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2018 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2019
2020 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2021 r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
2022 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
2023 r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2024 r600_write_value(cs, /* RESOURCEi_WORD2 */
2025 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2026 S_030008_STRIDE(16) |
2027 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2028 r600_write_value(cs, /* RESOURCEi_WORD3 */
2029 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2030 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2031 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2032 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2033 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2034 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2035 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
2036 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2037
2038 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2039 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2040
2041 dirty_mask &= ~(1 << buffer_index);
2042 }
2043 state->dirty_mask = 0;
2044 }
2045
2046 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2047 {
2048 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 176,
2049 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2050 R_028980_ALU_CONST_CACHE_VS_0);
2051 }
2052
2053 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2054 {
2055 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
2056 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2057 R_028940_ALU_CONST_CACHE_PS_0);
2058 }
2059
2060 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2061 struct r600_samplerview_state *state,
2062 unsigned resource_id_base)
2063 {
2064 struct radeon_winsys_cs *cs = rctx->cs;
2065 uint32_t dirty_mask = state->dirty_mask;
2066
2067 while (dirty_mask) {
2068 struct r600_pipe_sampler_view *rview;
2069 unsigned resource_index = u_bit_scan(&dirty_mask);
2070 unsigned reloc;
2071
2072 rview = state->views[resource_index];
2073 assert(rview);
2074
2075 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2076 r600_write_value(cs, (resource_id_base + resource_index) * 8);
2077 r600_write_array(cs, 8, rview->tex_resource_words);
2078
2079 /* XXX The kernel needs two relocations. This is stupid. */
2080 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
2081 RADEON_USAGE_READ);
2082 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2083 r600_write_value(cs, reloc);
2084 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2085 r600_write_value(cs, reloc);
2086 }
2087 state->dirty_mask = 0;
2088 }
2089
2090 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2091 {
2092 evergreen_emit_sampler_views(rctx, &rctx->vs_samplers.views, 176 + R600_MAX_CONST_BUFFERS);
2093 }
2094
2095 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2096 {
2097 evergreen_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
2098 }
2099
2100 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2101 struct r600_textures_info *texinfo,
2102 unsigned resource_id_base,
2103 unsigned border_index_reg)
2104 {
2105 struct radeon_winsys_cs *cs = rctx->cs;
2106 unsigned i;
2107
2108 for (i = 0; i < texinfo->n_samplers; i++) {
2109
2110 if (texinfo->samplers[i] == NULL) {
2111 continue;
2112 }
2113 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2114 r600_write_value(cs, (resource_id_base + i) * 3);
2115 r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words);
2116
2117 if (texinfo->samplers[i]->border_color_use) {
2118 r600_write_config_reg_seq(cs, border_index_reg, 5);
2119 r600_write_value(cs, i);
2120 r600_write_array(cs, 4, texinfo->samplers[i]->border_color);
2121 }
2122 }
2123 }
2124
2125 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2126 {
2127 evergreen_emit_sampler_states(rctx, &rctx->vs_samplers, 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
2128 }
2129
2130 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2131 {
2132 evergreen_emit_sampler_states(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
2133 }
2134
2135 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2136 {
2137 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2138 uint8_t mask = s->sample_mask;
2139
2140 r600_write_context_reg(rctx->cs, R_028C3C_PA_SC_AA_MASK,
2141 mask | (mask << 8) | (mask << 16) | (mask << 24));
2142 }
2143
2144 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2145 {
2146 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2147 struct radeon_winsys_cs *cs = rctx->cs;
2148 uint16_t mask = s->sample_mask;
2149
2150 r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2151 r600_write_value(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2152 r600_write_value(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2153 }
2154
2155 void evergreen_init_state_functions(struct r600_context *rctx)
2156 {
2157 unsigned id = 4;
2158
2159 /* !!!
2160 * To avoid GPU lockup registers must be emited in a specific order
2161 * (no kidding ...). The order below is important and have been
2162 * partialy infered from analyzing fglrx command stream.
2163 *
2164 * Don't reorder atom without carefully checking the effect (GPU lockup
2165 * or piglit regression).
2166 * !!!
2167 */
2168
2169 /* shader const */
2170 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
2171 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
2172 /* shader program */
2173 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
2174 /* sampler */
2175 r600_init_atom(rctx, &rctx->vs_samplers.atom_sampler, id++, evergreen_emit_vs_sampler_states, 0);
2176 r600_init_atom(rctx, &rctx->ps_samplers.atom_sampler, id++, evergreen_emit_ps_sampler_states, 0);
2177 /* resources */
2178 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
2179 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
2180 r600_init_atom(rctx, &rctx->vs_samplers.views.atom, id++, evergreen_emit_vs_sampler_views, 0);
2181 r600_init_atom(rctx, &rctx->ps_samplers.views.atom, id++, evergreen_emit_ps_sampler_views, 0);
2182
2183 if (rctx->chip_class == EVERGREEN) {
2184 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
2185 } else {
2186 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
2187 }
2188 rctx->sample_mask.sample_mask = ~0;
2189 r600_atom_dirty(rctx, &rctx->sample_mask.atom);
2190
2191 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 0);
2192 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2193
2194 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2195 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
2196
2197 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 7);
2198 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
2199
2200 rctx->context.create_blend_state = evergreen_create_blend_state;
2201 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
2202 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
2203 rctx->context.create_sampler_state = evergreen_create_sampler_state;
2204 rctx->context.create_sampler_view = evergreen_create_sampler_view;
2205 rctx->context.set_clip_state = evergreen_set_clip_state;
2206 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
2207 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
2208 rctx->context.set_scissor_state = evergreen_set_scissor_state;
2209 rctx->context.set_viewport_state = evergreen_set_viewport_state;
2210 evergreen_init_compute_state_functions(rctx);
2211 }
2212
2213 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2214 {
2215 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2216
2217 r600_init_command_buffer(rctx, cb, 0, 256);
2218
2219 /* This must be first. */
2220 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2221 r600_store_value(cb, 0x80000000);
2222 r600_store_value(cb, 0x80000000);
2223
2224 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2225 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2226 /* always set the temp clauses */
2227 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2228
2229 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2230 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2231 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2232
2233 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2234
2235 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2236
2237 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2238 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2239 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2240 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2241 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2242 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2243 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2244 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2245 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2246 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2247 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2248 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2249 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2250 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2251
2252 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2253 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2254 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2255
2256 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2257 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2258 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2259
2260 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2261
2262 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2263
2264 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2265 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2266 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2267
2268 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
2269 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2270 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2271
2272 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2273 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2274 r600_store_value(cb, 0);
2275 r600_store_value(cb, 0);
2276 r600_store_value(cb, 0);
2277 r600_store_value(cb, 0);
2278 r600_store_value(cb, 0);
2279 r600_store_value(cb, 0);
2280 r600_store_value(cb, 0);
2281 r600_store_value(cb, 0);
2282 r600_store_value(cb, 0);
2283 r600_store_value(cb, 0);
2284 r600_store_value(cb, 0);
2285 r600_store_value(cb, 0);
2286 r600_store_value(cb, 0);
2287 r600_store_value(cb, 0);
2288 r600_store_value(cb, 0);
2289 r600_store_value(cb, 0);
2290 r600_store_value(cb, 0);
2291 r600_store_value(cb, 0);
2292 r600_store_value(cb, 0);
2293 r600_store_value(cb, 0);
2294 r600_store_value(cb, 0);
2295 r600_store_value(cb, 0);
2296 r600_store_value(cb, 0);
2297 r600_store_value(cb, 0);
2298 r600_store_value(cb, 0);
2299 r600_store_value(cb, 0);
2300 r600_store_value(cb, 0);
2301 r600_store_value(cb, 0);
2302 r600_store_value(cb, 0);
2303 r600_store_value(cb, 0);
2304 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2305 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2306 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2307
2308 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2309
2310 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2311 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2312 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2313
2314 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2315
2316 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2317 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2318 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2319 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2320
2321 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2322 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2323
2324 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2325 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2326 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2327
2328 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2329 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2330 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2331
2332 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2333 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2334 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2335 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2336 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2337
2338 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2339 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2340 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2341
2342 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2343 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2344 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2345
2346 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2347 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2348 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2349
2350 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2351 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2352 if (rctx->screen->has_streamout) {
2353 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2354 }
2355
2356 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2357 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2358 }
2359
2360 void evergreen_init_common_regs(struct r600_command_buffer *cb,
2361 enum chip_class ctx_chip_class,
2362 enum radeon_family ctx_family,
2363 int ctx_drm_minor)
2364 {
2365 int ps_prio;
2366 int vs_prio;
2367 int gs_prio;
2368 int es_prio;
2369
2370 int hs_prio;
2371 int cs_prio;
2372 int ls_prio;
2373
2374 int num_ps_gprs;
2375 int num_vs_gprs;
2376 int num_gs_gprs;
2377 int num_es_gprs;
2378 int num_hs_gprs;
2379 int num_ls_gprs;
2380 int num_temp_gprs;
2381
2382 unsigned tmp;
2383
2384 ps_prio = 0;
2385 vs_prio = 1;
2386 gs_prio = 2;
2387 es_prio = 3;
2388 hs_prio = 0;
2389 ls_prio = 0;
2390 cs_prio = 0;
2391
2392 switch (ctx_family) {
2393 case CHIP_CEDAR:
2394 default:
2395 num_ps_gprs = 93;
2396 num_vs_gprs = 46;
2397 num_temp_gprs = 4;
2398 num_gs_gprs = 31;
2399 num_es_gprs = 31;
2400 num_hs_gprs = 23;
2401 num_ls_gprs = 23;
2402 break;
2403 case CHIP_REDWOOD:
2404 num_ps_gprs = 93;
2405 num_vs_gprs = 46;
2406 num_temp_gprs = 4;
2407 num_gs_gprs = 31;
2408 num_es_gprs = 31;
2409 num_hs_gprs = 23;
2410 num_ls_gprs = 23;
2411 break;
2412 case CHIP_JUNIPER:
2413 num_ps_gprs = 93;
2414 num_vs_gprs = 46;
2415 num_temp_gprs = 4;
2416 num_gs_gprs = 31;
2417 num_es_gprs = 31;
2418 num_hs_gprs = 23;
2419 num_ls_gprs = 23;
2420 break;
2421 case CHIP_CYPRESS:
2422 case CHIP_HEMLOCK:
2423 num_ps_gprs = 93;
2424 num_vs_gprs = 46;
2425 num_temp_gprs = 4;
2426 num_gs_gprs = 31;
2427 num_es_gprs = 31;
2428 num_hs_gprs = 23;
2429 num_ls_gprs = 23;
2430 break;
2431 case CHIP_PALM:
2432 num_ps_gprs = 93;
2433 num_vs_gprs = 46;
2434 num_temp_gprs = 4;
2435 num_gs_gprs = 31;
2436 num_es_gprs = 31;
2437 num_hs_gprs = 23;
2438 num_ls_gprs = 23;
2439 break;
2440 case CHIP_SUMO:
2441 num_ps_gprs = 93;
2442 num_vs_gprs = 46;
2443 num_temp_gprs = 4;
2444 num_gs_gprs = 31;
2445 num_es_gprs = 31;
2446 num_hs_gprs = 23;
2447 num_ls_gprs = 23;
2448 break;
2449 case CHIP_SUMO2:
2450 num_ps_gprs = 93;
2451 num_vs_gprs = 46;
2452 num_temp_gprs = 4;
2453 num_gs_gprs = 31;
2454 num_es_gprs = 31;
2455 num_hs_gprs = 23;
2456 num_ls_gprs = 23;
2457 break;
2458 case CHIP_BARTS:
2459 num_ps_gprs = 93;
2460 num_vs_gprs = 46;
2461 num_temp_gprs = 4;
2462 num_gs_gprs = 31;
2463 num_es_gprs = 31;
2464 num_hs_gprs = 23;
2465 num_ls_gprs = 23;
2466 break;
2467 case CHIP_TURKS:
2468 num_ps_gprs = 93;
2469 num_vs_gprs = 46;
2470 num_temp_gprs = 4;
2471 num_gs_gprs = 31;
2472 num_es_gprs = 31;
2473 num_hs_gprs = 23;
2474 num_ls_gprs = 23;
2475 break;
2476 case CHIP_CAICOS:
2477 num_ps_gprs = 93;
2478 num_vs_gprs = 46;
2479 num_temp_gprs = 4;
2480 num_gs_gprs = 31;
2481 num_es_gprs = 31;
2482 num_hs_gprs = 23;
2483 num_ls_gprs = 23;
2484 break;
2485 }
2486
2487 tmp = 0;
2488 switch (ctx_family) {
2489 case CHIP_CEDAR:
2490 case CHIP_PALM:
2491 case CHIP_SUMO:
2492 case CHIP_SUMO2:
2493 case CHIP_CAICOS:
2494 break;
2495 default:
2496 tmp |= S_008C00_VC_ENABLE(1);
2497 break;
2498 }
2499 tmp |= S_008C00_EXPORT_SRC_C(1);
2500 tmp |= S_008C00_CS_PRIO(cs_prio);
2501 tmp |= S_008C00_LS_PRIO(ls_prio);
2502 tmp |= S_008C00_HS_PRIO(hs_prio);
2503 tmp |= S_008C00_PS_PRIO(ps_prio);
2504 tmp |= S_008C00_VS_PRIO(vs_prio);
2505 tmp |= S_008C00_GS_PRIO(gs_prio);
2506 tmp |= S_008C00_ES_PRIO(es_prio);
2507
2508 /* enable dynamic GPR resource management */
2509 if (ctx_drm_minor >= 7) {
2510 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2511 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2512 /* always set temp clauses */
2513 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2514 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2515 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2516 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2517 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2518 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2519 S_028838_PS_GPRS(0x1e) |
2520 S_028838_VS_GPRS(0x1e) |
2521 S_028838_GS_GPRS(0x1e) |
2522 S_028838_ES_GPRS(0x1e) |
2523 S_028838_HS_GPRS(0x1e) |
2524 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2525 } else {
2526 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2527 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2528
2529 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2530 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2531 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2532 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2533
2534 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2535 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2536 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2537
2538 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2539 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2540 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2541 }
2542
2543 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2544 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2545
2546 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2547
2548 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2549 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2550 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2551
2552 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2553
2554 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2555 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2556 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2557
2558 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2559 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2560 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2561 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2562
2563 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2564 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2565
2566 /* to avoid GPU doing any preloading of constant from random address */
2567 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2568 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2569 r600_store_value(cb, 0);
2570 r600_store_value(cb, 0);
2571 r600_store_value(cb, 0);
2572 r600_store_value(cb, 0);
2573 r600_store_value(cb, 0);
2574 r600_store_value(cb, 0);
2575 r600_store_value(cb, 0);
2576 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2577 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2578 r600_store_value(cb, 0);
2579 r600_store_value(cb, 0);
2580 r600_store_value(cb, 0);
2581 r600_store_value(cb, 0);
2582 r600_store_value(cb, 0);
2583 r600_store_value(cb, 0);
2584 r600_store_value(cb, 0);
2585
2586 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2587
2588 return;
2589 }
2590
2591 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2592 {
2593 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2594 int num_ps_threads;
2595 int num_vs_threads;
2596 int num_gs_threads;
2597 int num_es_threads;
2598 int num_hs_threads;
2599 int num_ls_threads;
2600
2601 int num_ps_stack_entries;
2602 int num_vs_stack_entries;
2603 int num_gs_stack_entries;
2604 int num_es_stack_entries;
2605 int num_hs_stack_entries;
2606 int num_ls_stack_entries;
2607 enum radeon_family family;
2608 unsigned tmp;
2609
2610 if (rctx->chip_class == CAYMAN) {
2611 cayman_init_atom_start_cs(rctx);
2612 return;
2613 }
2614
2615 r600_init_command_buffer(rctx, cb, 0, 256);
2616
2617 /* This must be first. */
2618 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2619 r600_store_value(cb, 0x80000000);
2620 r600_store_value(cb, 0x80000000);
2621
2622 evergreen_init_common_regs(cb, rctx->chip_class
2623 , rctx->family, rctx->screen->info.drm_minor);
2624
2625 family = rctx->family;
2626 switch (family) {
2627 case CHIP_CEDAR:
2628 default:
2629 num_ps_threads = 96;
2630 num_vs_threads = 16;
2631 num_gs_threads = 16;
2632 num_es_threads = 16;
2633 num_hs_threads = 16;
2634 num_ls_threads = 16;
2635 num_ps_stack_entries = 42;
2636 num_vs_stack_entries = 42;
2637 num_gs_stack_entries = 42;
2638 num_es_stack_entries = 42;
2639 num_hs_stack_entries = 42;
2640 num_ls_stack_entries = 42;
2641 break;
2642 case CHIP_REDWOOD:
2643 num_ps_threads = 128;
2644 num_vs_threads = 20;
2645 num_gs_threads = 20;
2646 num_es_threads = 20;
2647 num_hs_threads = 20;
2648 num_ls_threads = 20;
2649 num_ps_stack_entries = 42;
2650 num_vs_stack_entries = 42;
2651 num_gs_stack_entries = 42;
2652 num_es_stack_entries = 42;
2653 num_hs_stack_entries = 42;
2654 num_ls_stack_entries = 42;
2655 break;
2656 case CHIP_JUNIPER:
2657 num_ps_threads = 128;
2658 num_vs_threads = 20;
2659 num_gs_threads = 20;
2660 num_es_threads = 20;
2661 num_hs_threads = 20;
2662 num_ls_threads = 20;
2663 num_ps_stack_entries = 85;
2664 num_vs_stack_entries = 85;
2665 num_gs_stack_entries = 85;
2666 num_es_stack_entries = 85;
2667 num_hs_stack_entries = 85;
2668 num_ls_stack_entries = 85;
2669 break;
2670 case CHIP_CYPRESS:
2671 case CHIP_HEMLOCK:
2672 num_ps_threads = 128;
2673 num_vs_threads = 20;
2674 num_gs_threads = 20;
2675 num_es_threads = 20;
2676 num_hs_threads = 20;
2677 num_ls_threads = 20;
2678 num_ps_stack_entries = 85;
2679 num_vs_stack_entries = 85;
2680 num_gs_stack_entries = 85;
2681 num_es_stack_entries = 85;
2682 num_hs_stack_entries = 85;
2683 num_ls_stack_entries = 85;
2684 break;
2685 case CHIP_PALM:
2686 num_ps_threads = 96;
2687 num_vs_threads = 16;
2688 num_gs_threads = 16;
2689 num_es_threads = 16;
2690 num_hs_threads = 16;
2691 num_ls_threads = 16;
2692 num_ps_stack_entries = 42;
2693 num_vs_stack_entries = 42;
2694 num_gs_stack_entries = 42;
2695 num_es_stack_entries = 42;
2696 num_hs_stack_entries = 42;
2697 num_ls_stack_entries = 42;
2698 break;
2699 case CHIP_SUMO:
2700 num_ps_threads = 96;
2701 num_vs_threads = 25;
2702 num_gs_threads = 25;
2703 num_es_threads = 25;
2704 num_hs_threads = 25;
2705 num_ls_threads = 25;
2706 num_ps_stack_entries = 42;
2707 num_vs_stack_entries = 42;
2708 num_gs_stack_entries = 42;
2709 num_es_stack_entries = 42;
2710 num_hs_stack_entries = 42;
2711 num_ls_stack_entries = 42;
2712 break;
2713 case CHIP_SUMO2:
2714 num_ps_threads = 96;
2715 num_vs_threads = 25;
2716 num_gs_threads = 25;
2717 num_es_threads = 25;
2718 num_hs_threads = 25;
2719 num_ls_threads = 25;
2720 num_ps_stack_entries = 85;
2721 num_vs_stack_entries = 85;
2722 num_gs_stack_entries = 85;
2723 num_es_stack_entries = 85;
2724 num_hs_stack_entries = 85;
2725 num_ls_stack_entries = 85;
2726 break;
2727 case CHIP_BARTS:
2728 num_ps_threads = 128;
2729 num_vs_threads = 20;
2730 num_gs_threads = 20;
2731 num_es_threads = 20;
2732 num_hs_threads = 20;
2733 num_ls_threads = 20;
2734 num_ps_stack_entries = 85;
2735 num_vs_stack_entries = 85;
2736 num_gs_stack_entries = 85;
2737 num_es_stack_entries = 85;
2738 num_hs_stack_entries = 85;
2739 num_ls_stack_entries = 85;
2740 break;
2741 case CHIP_TURKS:
2742 num_ps_threads = 128;
2743 num_vs_threads = 20;
2744 num_gs_threads = 20;
2745 num_es_threads = 20;
2746 num_hs_threads = 20;
2747 num_ls_threads = 20;
2748 num_ps_stack_entries = 42;
2749 num_vs_stack_entries = 42;
2750 num_gs_stack_entries = 42;
2751 num_es_stack_entries = 42;
2752 num_hs_stack_entries = 42;
2753 num_ls_stack_entries = 42;
2754 break;
2755 case CHIP_CAICOS:
2756 num_ps_threads = 128;
2757 num_vs_threads = 10;
2758 num_gs_threads = 10;
2759 num_es_threads = 10;
2760 num_hs_threads = 10;
2761 num_ls_threads = 10;
2762 num_ps_stack_entries = 42;
2763 num_vs_stack_entries = 42;
2764 num_gs_stack_entries = 42;
2765 num_es_stack_entries = 42;
2766 num_hs_stack_entries = 42;
2767 num_ls_stack_entries = 42;
2768 break;
2769 }
2770
2771 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2772 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2773 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2774 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2775
2776 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2777 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2778
2779 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2780 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2781 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2782
2783 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2784 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2785 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2786
2787 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2788 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2789 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2790
2791 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2792 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2793 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2794
2795 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2796 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2797
2798 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2799 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2800 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2801 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2802 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2803 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2804 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2805
2806 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2807 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2808 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2809 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2810 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2811
2812 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2813 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2814 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2815 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2816 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2817 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2818 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2819 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2820 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2821 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2822 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2823 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2824 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2825 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2826
2827 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2828 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2829 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2830
2831 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2832
2833 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2834 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2835 r600_store_value(cb, 0);
2836 r600_store_value(cb, 0);
2837 r600_store_value(cb, 0);
2838 r600_store_value(cb, 0);
2839 r600_store_value(cb, 0);
2840 r600_store_value(cb, 0);
2841 r600_store_value(cb, 0);
2842 r600_store_value(cb, 0);
2843 r600_store_value(cb, 0);
2844 r600_store_value(cb, 0);
2845 r600_store_value(cb, 0);
2846 r600_store_value(cb, 0);
2847 r600_store_value(cb, 0);
2848 r600_store_value(cb, 0);
2849 r600_store_value(cb, 0);
2850 r600_store_value(cb, 0);
2851 r600_store_value(cb, 0);
2852 r600_store_value(cb, 0);
2853 r600_store_value(cb, 0);
2854 r600_store_value(cb, 0);
2855 r600_store_value(cb, 0);
2856 r600_store_value(cb, 0);
2857 r600_store_value(cb, 0);
2858 r600_store_value(cb, 0);
2859 r600_store_value(cb, 0);
2860 r600_store_value(cb, 0);
2861 r600_store_value(cb, 0);
2862 r600_store_value(cb, 0);
2863 r600_store_value(cb, 0);
2864 r600_store_value(cb, 0);
2865 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2866 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2867 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2868
2869 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2870
2871 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2872 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2873 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2874
2875 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2876 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2877
2878 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2879 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2880 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2881
2882 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2883 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2884 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2885 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2886
2887 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2888 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2889 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2890 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2891 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2892
2893 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2894 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2895 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2896
2897 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2898 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2899 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2900
2901 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2902
2903 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2904 if (rctx->screen->has_streamout) {
2905 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2906 }
2907
2908 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2909 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2910 }
2911
2912 void evergreen_polygon_offset_update(struct r600_context *rctx)
2913 {
2914 struct r600_pipe_state state;
2915
2916 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2917 state.nregs = 0;
2918 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2919 float offset_units = rctx->rasterizer->offset_units;
2920 unsigned offset_db_fmt_cntl = 0, depth;
2921
2922 switch (rctx->framebuffer.zsbuf->format) {
2923 case PIPE_FORMAT_Z24X8_UNORM:
2924 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2925 depth = -24;
2926 offset_units *= 2.0f;
2927 break;
2928 case PIPE_FORMAT_Z32_FLOAT:
2929 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2930 depth = -23;
2931 offset_units *= 1.0f;
2932 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2933 break;
2934 case PIPE_FORMAT_Z16_UNORM:
2935 depth = -16;
2936 offset_units *= 4.0f;
2937 break;
2938 default:
2939 return;
2940 }
2941 /* XXX some of those reg can be computed with cso */
2942 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2943 r600_pipe_state_add_reg(&state,
2944 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2945 fui(rctx->rasterizer->offset_scale));
2946 r600_pipe_state_add_reg(&state,
2947 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2948 fui(offset_units));
2949 r600_pipe_state_add_reg(&state,
2950 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2951 fui(rctx->rasterizer->offset_scale));
2952 r600_pipe_state_add_reg(&state,
2953 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2954 fui(offset_units));
2955 r600_pipe_state_add_reg(&state,
2956 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2957 offset_db_fmt_cntl);
2958 r600_context_pipe_state_set(rctx, &state);
2959 }
2960 }
2961
2962 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2963 {
2964 struct r600_context *rctx = (struct r600_context *)ctx;
2965 struct r600_pipe_state *rstate = &shader->rstate;
2966 struct r600_shader *rshader = &shader->shader;
2967 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2968 int pos_index = -1, face_index = -1;
2969 int ninterp = 0;
2970 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2971 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2972 unsigned z_export = 0, stencil_export = 0;
2973
2974 rstate->nregs = 0;
2975
2976 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2977 for (i = 0; i < rshader->ninput; i++) {
2978 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2979 POSITION goes via GPRs from the SC so isn't counted */
2980 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2981 pos_index = i;
2982 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2983 face_index = i;
2984 else {
2985 ninterp++;
2986 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2987 have_linear = TRUE;
2988 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2989 have_perspective = TRUE;
2990 if (rshader->input[i].centroid)
2991 have_centroid = TRUE;
2992 }
2993
2994 sid = rshader->input[i].spi_sid;
2995
2996 if (sid) {
2997
2998 tmp = S_028644_SEMANTIC(sid);
2999
3000 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3001 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3002 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3003 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3004 tmp |= S_028644_FLAT_SHADE(1);
3005 }
3006
3007 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3008 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
3009 tmp |= S_028644_PT_SPRITE_TEX(1);
3010 }
3011
3012 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
3013 tmp);
3014
3015 idx++;
3016 }
3017 }
3018
3019 for (i = 0; i < rshader->noutput; i++) {
3020 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3021 z_export = 1;
3022 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3023 stencil_export = 1;
3024 }
3025 if (rshader->uses_kill)
3026 db_shader_control |= S_02880C_KILL_ENABLE(1);
3027
3028 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3029 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3030
3031 exports_ps = 0;
3032 for (i = 0; i < rshader->noutput; i++) {
3033 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3034 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3035 exports_ps |= 1;
3036 }
3037
3038 num_cout = rshader->nr_ps_color_exports;
3039
3040 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3041 if (!exports_ps) {
3042 /* always at least export 1 component per pixel */
3043 exports_ps = 2;
3044 }
3045 shader->nr_ps_color_outputs = num_cout;
3046 if (ninterp == 0) {
3047 ninterp = 1;
3048 have_perspective = TRUE;
3049 }
3050
3051 if (!have_perspective && !have_linear)
3052 have_perspective = TRUE;
3053
3054 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3055 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3056 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3057 spi_input_z = 0;
3058 if (pos_index != -1) {
3059 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3060 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
3061 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3062 spi_input_z |= 1;
3063 }
3064
3065 spi_ps_in_control_1 = 0;
3066 if (face_index != -1) {
3067 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3068 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3069 }
3070
3071 spi_baryc_cntl = 0;
3072 if (have_perspective)
3073 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
3074 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
3075 if (have_linear)
3076 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
3077 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
3078
3079 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
3080 spi_ps_in_control_0);
3081 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
3082 spi_ps_in_control_1);
3083 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
3084 0);
3085 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
3086 r600_pipe_state_add_reg(rstate,
3087 R_0286E0_SPI_BARYC_CNTL,
3088 spi_baryc_cntl);
3089
3090 r600_pipe_state_add_reg_bo(rstate,
3091 R_028840_SQ_PGM_START_PS,
3092 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3093 shader->bo, RADEON_USAGE_READ);
3094 r600_pipe_state_add_reg(rstate,
3095 R_028844_SQ_PGM_RESOURCES_PS,
3096 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3097 S_028844_PRIME_CACHE_ON_DRAW(1) |
3098 S_028844_STACK_SIZE(rshader->bc.nstack));
3099 r600_pipe_state_add_reg(rstate,
3100 R_02884C_SQ_PGM_EXPORTS_PS,
3101 exports_ps);
3102
3103 shader->db_shader_control = db_shader_control;
3104 shader->ps_depth_export = z_export | stencil_export;
3105
3106 shader->sprite_coord_enable = rctx->sprite_coord_enable;
3107 if (rctx->rasterizer)
3108 shader->flatshade = rctx->rasterizer->flatshade;
3109 }
3110
3111 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3112 {
3113 struct r600_context *rctx = (struct r600_context *)ctx;
3114 struct r600_pipe_state *rstate = &shader->rstate;
3115 struct r600_shader *rshader = &shader->shader;
3116 unsigned spi_vs_out_id[10] = {};
3117 unsigned i, tmp, nparams = 0;
3118
3119 /* clear previous register */
3120 rstate->nregs = 0;
3121
3122 for (i = 0; i < rshader->noutput; i++) {
3123 if (rshader->output[i].spi_sid) {
3124 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3125 spi_vs_out_id[nparams / 4] |= tmp;
3126 nparams++;
3127 }
3128 }
3129
3130 for (i = 0; i < 10; i++) {
3131 r600_pipe_state_add_reg(rstate,
3132 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
3133 spi_vs_out_id[i]);
3134 }
3135
3136 /* Certain attributes (position, psize, etc.) don't count as params.
3137 * VS is required to export at least one param and r600_shader_from_tgsi()
3138 * takes care of adding a dummy export.
3139 */
3140 if (nparams < 1)
3141 nparams = 1;
3142
3143 r600_pipe_state_add_reg(rstate,
3144 R_0286C4_SPI_VS_OUT_CONFIG,
3145 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3146 r600_pipe_state_add_reg(rstate,
3147 R_028860_SQ_PGM_RESOURCES_VS,
3148 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3149 S_028860_STACK_SIZE(rshader->bc.nstack));
3150 r600_pipe_state_add_reg_bo(rstate,
3151 R_02885C_SQ_PGM_START_VS,
3152 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3153 shader->bo, RADEON_USAGE_READ);
3154
3155 shader->pa_cl_vs_out_cntl =
3156 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3157 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3158 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3159 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
3160 }
3161
3162 void evergreen_fetch_shader(struct pipe_context *ctx,
3163 struct r600_vertex_element *ve)
3164 {
3165 struct r600_context *rctx = (struct r600_context *)ctx;
3166 struct r600_pipe_state *rstate = &ve->rstate;
3167 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
3168 rstate->nregs = 0;
3169 r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
3170 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
3171 ve->fetch_shader, RADEON_USAGE_READ);
3172 }
3173
3174 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3175 {
3176 struct pipe_blend_state blend;
3177 struct r600_pipe_state *rstate;
3178
3179 memset(&blend, 0, sizeof(blend));
3180 blend.independent_blend_enable = true;
3181 blend.rt[0].colormask = 0xf;
3182 rstate = evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_RESOLVE);
3183 return rstate;
3184 }
3185
3186 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3187 {
3188 struct pipe_blend_state blend;
3189 struct r600_pipe_state *rstate;
3190
3191 memset(&blend, 0, sizeof(blend));
3192 blend.independent_blend_enable = true;
3193 blend.rt[0].colormask = 0xf;
3194 rstate = evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_DECOMPRESS);
3195 return rstate;
3196 }
3197
3198 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3199 {
3200 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3201
3202 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
3203 }
3204
3205 void evergreen_update_dual_export_state(struct r600_context * rctx)
3206 {
3207 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
3208 !rctx->ps_shader->current->ps_depth_export;
3209
3210 unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
3211 V_02880C_EXPORT_DB_FULL;
3212
3213 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
3214 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3215 S_02880C_DB_SOURCE_FORMAT(db_source_format) |
3216 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->cb0_is_integer);
3217
3218 if (db_shader_control != rctx->db_shader_control) {
3219 struct r600_pipe_state rstate;
3220
3221 rctx->db_shader_control = db_shader_control;
3222
3223 rstate.nregs = 0;
3224 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
3225 r600_context_pipe_state_set(rctx, &rstate);
3226 }
3227 }