2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * - fix mask for depth control & cull for query
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_blitter.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
38 #include "util/u_surface.h"
39 #include "util/u_pack_color.h"
40 #include "util/u_memory.h"
41 #include "util/u_inlines.h"
42 #include "util/u_framebuffer.h"
43 #include "pipebuffer/pb_buffer.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "r600_formats.h"
51 static uint32_t r600_translate_blend_function(int blend_func
)
55 return V_028780_COMB_DST_PLUS_SRC
;
56 case PIPE_BLEND_SUBTRACT
:
57 return V_028780_COMB_SRC_MINUS_DST
;
58 case PIPE_BLEND_REVERSE_SUBTRACT
:
59 return V_028780_COMB_DST_MINUS_SRC
;
61 return V_028780_COMB_MIN_DST_SRC
;
63 return V_028780_COMB_MAX_DST_SRC
;
65 R600_ERR("Unknown blend function %d\n", blend_func
);
72 static uint32_t r600_translate_blend_factor(int blend_fact
)
75 case PIPE_BLENDFACTOR_ONE
:
76 return V_028780_BLEND_ONE
;
77 case PIPE_BLENDFACTOR_SRC_COLOR
:
78 return V_028780_BLEND_SRC_COLOR
;
79 case PIPE_BLENDFACTOR_SRC_ALPHA
:
80 return V_028780_BLEND_SRC_ALPHA
;
81 case PIPE_BLENDFACTOR_DST_ALPHA
:
82 return V_028780_BLEND_DST_ALPHA
;
83 case PIPE_BLENDFACTOR_DST_COLOR
:
84 return V_028780_BLEND_DST_COLOR
;
85 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
86 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
87 case PIPE_BLENDFACTOR_CONST_COLOR
:
88 return V_028780_BLEND_CONST_COLOR
;
89 case PIPE_BLENDFACTOR_CONST_ALPHA
:
90 return V_028780_BLEND_CONST_ALPHA
;
91 case PIPE_BLENDFACTOR_ZERO
:
92 return V_028780_BLEND_ZERO
;
93 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
94 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
95 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
96 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
97 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
98 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
99 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
100 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
101 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
102 return V_028780_BLEND_ONE_MINUS_CONST_COLOR
;
103 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
104 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA
;
105 case PIPE_BLENDFACTOR_SRC1_COLOR
:
106 return V_028780_BLEND_SRC1_COLOR
;
107 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
108 return V_028780_BLEND_SRC1_ALPHA
;
109 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
110 return V_028780_BLEND_INV_SRC1_COLOR
;
111 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
112 return V_028780_BLEND_INV_SRC1_ALPHA
;
114 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
121 static uint32_t r600_translate_stencil_op(int s_op
)
124 case PIPE_STENCIL_OP_KEEP
:
125 return V_028800_STENCIL_KEEP
;
126 case PIPE_STENCIL_OP_ZERO
:
127 return V_028800_STENCIL_ZERO
;
128 case PIPE_STENCIL_OP_REPLACE
:
129 return V_028800_STENCIL_REPLACE
;
130 case PIPE_STENCIL_OP_INCR
:
131 return V_028800_STENCIL_INCR
;
132 case PIPE_STENCIL_OP_DECR
:
133 return V_028800_STENCIL_DECR
;
134 case PIPE_STENCIL_OP_INCR_WRAP
:
135 return V_028800_STENCIL_INCR_WRAP
;
136 case PIPE_STENCIL_OP_DECR_WRAP
:
137 return V_028800_STENCIL_DECR_WRAP
;
138 case PIPE_STENCIL_OP_INVERT
:
139 return V_028800_STENCIL_INVERT
;
141 R600_ERR("Unknown stencil op %d", s_op
);
148 static uint32_t r600_translate_fill(uint32_t func
)
151 case PIPE_POLYGON_MODE_FILL
:
153 case PIPE_POLYGON_MODE_LINE
:
155 case PIPE_POLYGON_MODE_POINT
:
163 /* translates straight */
164 static uint32_t r600_translate_ds_func(int func
)
169 static unsigned r600_tex_wrap(unsigned wrap
)
173 case PIPE_TEX_WRAP_REPEAT
:
174 return V_03C000_SQ_TEX_WRAP
;
175 case PIPE_TEX_WRAP_CLAMP
:
176 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
177 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
178 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
179 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
180 return V_03C000_SQ_TEX_CLAMP_BORDER
;
181 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
182 return V_03C000_SQ_TEX_MIRROR
;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
184 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
186 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
187 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
188 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
192 static unsigned r600_tex_filter(unsigned filter
)
196 case PIPE_TEX_FILTER_NEAREST
:
197 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
198 case PIPE_TEX_FILTER_LINEAR
:
199 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
203 static unsigned r600_tex_mipfilter(unsigned filter
)
206 case PIPE_TEX_MIPFILTER_NEAREST
:
207 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
208 case PIPE_TEX_MIPFILTER_LINEAR
:
209 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
211 case PIPE_TEX_MIPFILTER_NONE
:
212 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
216 static unsigned r600_tex_compare(unsigned compare
)
220 case PIPE_FUNC_NEVER
:
221 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
223 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
224 case PIPE_FUNC_EQUAL
:
225 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
226 case PIPE_FUNC_LEQUAL
:
227 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
228 case PIPE_FUNC_GREATER
:
229 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
230 case PIPE_FUNC_NOTEQUAL
:
231 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
232 case PIPE_FUNC_GEQUAL
:
233 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
234 case PIPE_FUNC_ALWAYS
:
235 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
239 static unsigned r600_tex_dim(unsigned dim
)
243 case PIPE_TEXTURE_1D
:
244 return V_030000_SQ_TEX_DIM_1D
;
245 case PIPE_TEXTURE_1D_ARRAY
:
246 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
247 case PIPE_TEXTURE_2D
:
248 case PIPE_TEXTURE_RECT
:
249 return V_030000_SQ_TEX_DIM_2D
;
250 case PIPE_TEXTURE_2D_ARRAY
:
251 return V_030000_SQ_TEX_DIM_2D_ARRAY
;
252 case PIPE_TEXTURE_3D
:
253 return V_030000_SQ_TEX_DIM_3D
;
254 case PIPE_TEXTURE_CUBE
:
255 return V_030000_SQ_TEX_DIM_CUBEMAP
;
259 static uint32_t r600_translate_dbformat(enum pipe_format format
)
262 case PIPE_FORMAT_Z16_UNORM
:
263 return V_028040_Z_16
;
264 case PIPE_FORMAT_Z24X8_UNORM
:
265 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
266 return V_028040_Z_24
;
267 case PIPE_FORMAT_Z32_FLOAT
:
268 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED
:
269 return V_028040_Z_32_FLOAT
;
275 static uint32_t r600_translate_colorswap(enum pipe_format format
)
279 case PIPE_FORMAT_L4A4_UNORM
:
280 case PIPE_FORMAT_A4R4_UNORM
:
281 return V_028C70_SWAP_ALT
;
283 case PIPE_FORMAT_A8_UNORM
:
284 case PIPE_FORMAT_R4A4_UNORM
:
285 return V_028C70_SWAP_ALT_REV
;
286 case PIPE_FORMAT_I8_UNORM
:
287 case PIPE_FORMAT_L8_UNORM
:
288 case PIPE_FORMAT_L8_SRGB
:
289 case PIPE_FORMAT_R8_UNORM
:
290 case PIPE_FORMAT_R8_SNORM
:
291 return V_028C70_SWAP_STD
;
293 /* 16-bit buffers. */
294 case PIPE_FORMAT_B5G6R5_UNORM
:
295 return V_028C70_SWAP_STD_REV
;
297 case PIPE_FORMAT_B5G5R5A1_UNORM
:
298 case PIPE_FORMAT_B5G5R5X1_UNORM
:
299 return V_028C70_SWAP_ALT
;
301 case PIPE_FORMAT_B4G4R4A4_UNORM
:
302 case PIPE_FORMAT_B4G4R4X4_UNORM
:
303 return V_028C70_SWAP_ALT
;
305 case PIPE_FORMAT_Z16_UNORM
:
306 return V_028C70_SWAP_STD
;
308 case PIPE_FORMAT_L8A8_UNORM
:
309 case PIPE_FORMAT_L8A8_SRGB
:
310 return V_028C70_SWAP_ALT
;
311 case PIPE_FORMAT_R8G8_UNORM
:
312 return V_028C70_SWAP_STD
;
314 case PIPE_FORMAT_R16_UNORM
:
315 case PIPE_FORMAT_R16_FLOAT
:
316 return V_028C70_SWAP_STD
;
318 /* 32-bit buffers. */
319 case PIPE_FORMAT_A8B8G8R8_SRGB
:
320 return V_028C70_SWAP_STD_REV
;
321 case PIPE_FORMAT_B8G8R8A8_SRGB
:
322 return V_028C70_SWAP_ALT
;
324 case PIPE_FORMAT_B8G8R8A8_UNORM
:
325 case PIPE_FORMAT_B8G8R8X8_UNORM
:
326 return V_028C70_SWAP_ALT
;
328 case PIPE_FORMAT_A8R8G8B8_UNORM
:
329 case PIPE_FORMAT_X8R8G8B8_UNORM
:
330 return V_028C70_SWAP_ALT_REV
;
331 case PIPE_FORMAT_R8G8B8A8_SNORM
:
332 case PIPE_FORMAT_R8G8B8A8_UNORM
:
333 case PIPE_FORMAT_R8G8B8X8_UNORM
:
334 return V_028C70_SWAP_STD
;
336 case PIPE_FORMAT_A8B8G8R8_UNORM
:
337 case PIPE_FORMAT_X8B8G8R8_UNORM
:
338 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
339 return V_028C70_SWAP_STD_REV
;
341 case PIPE_FORMAT_Z24X8_UNORM
:
342 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
343 return V_028C70_SWAP_STD
;
345 case PIPE_FORMAT_X8Z24_UNORM
:
346 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
347 return V_028C70_SWAP_STD
;
349 case PIPE_FORMAT_R10G10B10A2_UNORM
:
350 case PIPE_FORMAT_R10G10B10X2_SNORM
:
351 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
352 return V_028C70_SWAP_STD
;
354 case PIPE_FORMAT_B10G10R10A2_UNORM
:
355 return V_028C70_SWAP_ALT
;
357 case PIPE_FORMAT_R11G11B10_FLOAT
:
358 case PIPE_FORMAT_R32_FLOAT
:
359 case PIPE_FORMAT_Z32_FLOAT
:
360 case PIPE_FORMAT_R16G16_FLOAT
:
361 case PIPE_FORMAT_R16G16_UNORM
:
362 return V_028C70_SWAP_STD
;
364 /* 64-bit buffers. */
365 case PIPE_FORMAT_R32G32_FLOAT
:
366 case PIPE_FORMAT_R16G16B16A16_UNORM
:
367 case PIPE_FORMAT_R16G16B16A16_SNORM
:
368 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
369 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED
:
371 /* 128-bit buffers. */
372 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
373 case PIPE_FORMAT_R32G32B32A32_SNORM
:
374 case PIPE_FORMAT_R32G32B32A32_UNORM
:
375 return V_028C70_SWAP_STD
;
377 R600_ERR("unsupported colorswap format %d\n", format
);
383 static uint32_t r600_translate_colorformat(enum pipe_format format
)
387 case PIPE_FORMAT_L4A4_UNORM
:
388 case PIPE_FORMAT_R4A4_UNORM
:
389 case PIPE_FORMAT_A4R4_UNORM
:
390 return V_028C70_COLOR_4_4
;
392 case PIPE_FORMAT_A8_UNORM
:
393 case PIPE_FORMAT_I8_UNORM
:
394 case PIPE_FORMAT_L8_UNORM
:
395 case PIPE_FORMAT_L8_SRGB
:
396 case PIPE_FORMAT_R8_UNORM
:
397 case PIPE_FORMAT_R8_SNORM
:
398 return V_028C70_COLOR_8
;
400 /* 16-bit buffers. */
401 case PIPE_FORMAT_B5G6R5_UNORM
:
402 return V_028C70_COLOR_5_6_5
;
404 case PIPE_FORMAT_B5G5R5A1_UNORM
:
405 case PIPE_FORMAT_B5G5R5X1_UNORM
:
406 return V_028C70_COLOR_1_5_5_5
;
408 case PIPE_FORMAT_B4G4R4A4_UNORM
:
409 case PIPE_FORMAT_B4G4R4X4_UNORM
:
410 return V_028C70_COLOR_4_4_4_4
;
412 case PIPE_FORMAT_Z16_UNORM
:
413 return V_028C70_COLOR_16
;
415 case PIPE_FORMAT_L8A8_UNORM
:
416 case PIPE_FORMAT_L8A8_SRGB
:
417 case PIPE_FORMAT_R8G8_UNORM
:
418 return V_028C70_COLOR_8_8
;
420 case PIPE_FORMAT_R16_UNORM
:
421 return V_028C70_COLOR_16
;
423 case PIPE_FORMAT_R16_FLOAT
:
424 return V_028C70_COLOR_16_FLOAT
;
426 /* 32-bit buffers. */
427 case PIPE_FORMAT_A8B8G8R8_SRGB
:
428 case PIPE_FORMAT_A8B8G8R8_UNORM
:
429 case PIPE_FORMAT_A8R8G8B8_UNORM
:
430 case PIPE_FORMAT_B8G8R8A8_SRGB
:
431 case PIPE_FORMAT_B8G8R8A8_UNORM
:
432 case PIPE_FORMAT_B8G8R8X8_UNORM
:
433 case PIPE_FORMAT_R8G8B8A8_SNORM
:
434 case PIPE_FORMAT_R8G8B8A8_UNORM
:
435 case PIPE_FORMAT_R8G8B8X8_UNORM
:
436 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
437 case PIPE_FORMAT_X8B8G8R8_UNORM
:
438 case PIPE_FORMAT_X8R8G8B8_UNORM
:
439 case PIPE_FORMAT_R8G8B8_UNORM
:
440 return V_028C70_COLOR_8_8_8_8
;
442 case PIPE_FORMAT_R10G10B10A2_UNORM
:
443 case PIPE_FORMAT_R10G10B10X2_SNORM
:
444 case PIPE_FORMAT_B10G10R10A2_UNORM
:
445 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
446 return V_028C70_COLOR_2_10_10_10
;
448 case PIPE_FORMAT_Z24X8_UNORM
:
449 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
450 return V_028C70_COLOR_8_24
;
452 case PIPE_FORMAT_X8Z24_UNORM
:
453 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
454 return V_028C70_COLOR_24_8
;
456 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED
:
457 return V_028C70_COLOR_X24_8_32_FLOAT
;
459 case PIPE_FORMAT_R32_FLOAT
:
460 case PIPE_FORMAT_Z32_FLOAT
:
461 return V_028C70_COLOR_32_FLOAT
;
463 case PIPE_FORMAT_R16G16_FLOAT
:
464 return V_028C70_COLOR_16_16_FLOAT
;
466 case PIPE_FORMAT_R16G16_SSCALED
:
467 case PIPE_FORMAT_R16G16_UNORM
:
468 return V_028C70_COLOR_16_16
;
470 case PIPE_FORMAT_R11G11B10_FLOAT
:
471 return V_028C70_COLOR_10_11_11_FLOAT
;
473 /* 64-bit buffers. */
474 case PIPE_FORMAT_R16G16B16_USCALED
:
475 case PIPE_FORMAT_R16G16B16A16_USCALED
:
476 case PIPE_FORMAT_R16G16B16_SSCALED
:
477 case PIPE_FORMAT_R16G16B16A16_SSCALED
:
478 case PIPE_FORMAT_R16G16B16A16_UNORM
:
479 case PIPE_FORMAT_R16G16B16A16_SNORM
:
480 return V_028C70_COLOR_16_16_16_16
;
482 case PIPE_FORMAT_R16G16B16_FLOAT
:
483 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
484 return V_028C70_COLOR_16_16_16_16_FLOAT
;
486 case PIPE_FORMAT_R32G32_FLOAT
:
487 return V_028C70_COLOR_32_32_FLOAT
;
489 case PIPE_FORMAT_R32G32_USCALED
:
490 case PIPE_FORMAT_R32G32_SSCALED
:
491 return V_028C70_COLOR_32_32
;
493 /* 96-bit buffers. */
494 case PIPE_FORMAT_R32G32B32_FLOAT
:
495 return V_028C70_COLOR_32_32_32_FLOAT
;
497 /* 128-bit buffers. */
498 case PIPE_FORMAT_R32G32B32A32_SNORM
:
499 case PIPE_FORMAT_R32G32B32A32_UNORM
:
500 return V_028C70_COLOR_32_32_32_32
;
501 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
502 return V_028C70_COLOR_32_32_32_32_FLOAT
;
505 case PIPE_FORMAT_UYVY
:
506 case PIPE_FORMAT_YUYV
:
508 return ~0U; /* Unsupported. */
512 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
514 if (R600_BIG_ENDIAN
) {
515 switch(colorformat
) {
516 case V_028C70_COLOR_4_4
:
520 case V_028C70_COLOR_8
:
523 /* 16-bit buffers. */
524 case V_028C70_COLOR_5_6_5
:
525 case V_028C70_COLOR_1_5_5_5
:
526 case V_028C70_COLOR_4_4_4_4
:
527 case V_028C70_COLOR_16
:
528 case V_028C70_COLOR_8_8
:
531 /* 32-bit buffers. */
532 case V_028C70_COLOR_8_8_8_8
:
533 case V_028C70_COLOR_2_10_10_10
:
534 case V_028C70_COLOR_8_24
:
535 case V_028C70_COLOR_24_8
:
536 case V_028C70_COLOR_32_FLOAT
:
537 case V_028C70_COLOR_16_16_FLOAT
:
538 case V_028C70_COLOR_16_16
:
541 /* 64-bit buffers. */
542 case V_028C70_COLOR_16_16_16_16
:
543 case V_028C70_COLOR_16_16_16_16_FLOAT
:
546 case V_028C70_COLOR_32_32_FLOAT
:
547 case V_028C70_COLOR_32_32
:
548 case V_028C70_COLOR_X24_8_32_FLOAT
:
551 /* 96-bit buffers. */
552 case V_028C70_COLOR_32_32_32_FLOAT
:
553 /* 128-bit buffers. */
554 case V_028C70_COLOR_32_32_32_32_FLOAT
:
555 case V_028C70_COLOR_32_32_32_32
:
558 return ENDIAN_NONE
; /* Unsupported. */
565 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
567 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
570 static bool r600_is_colorbuffer_format_supported(enum pipe_format format
)
572 return r600_translate_colorformat(format
) != ~0U &&
573 r600_translate_colorswap(format
) != ~0U;
576 static bool r600_is_zs_format_supported(enum pipe_format format
)
578 return r600_translate_dbformat(format
) != ~0U;
581 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
582 enum pipe_format format
,
583 enum pipe_texture_target target
,
584 unsigned sample_count
,
589 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
590 R600_ERR("r600: unsupported texture type %d\n", target
);
594 if (!util_format_is_supported(format
, usage
))
598 if (sample_count
> 1)
601 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
602 r600_is_sampler_format_supported(screen
, format
)) {
603 retval
|= PIPE_BIND_SAMPLER_VIEW
;
606 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
607 PIPE_BIND_DISPLAY_TARGET
|
609 PIPE_BIND_SHARED
)) &&
610 r600_is_colorbuffer_format_supported(format
)) {
612 (PIPE_BIND_RENDER_TARGET
|
613 PIPE_BIND_DISPLAY_TARGET
|
618 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
619 r600_is_zs_format_supported(format
)) {
620 retval
|= PIPE_BIND_DEPTH_STENCIL
;
623 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
624 r600_is_vertex_format_supported(format
)) {
625 retval
|= PIPE_BIND_VERTEX_BUFFER
;
628 if (usage
& PIPE_BIND_TRANSFER_READ
)
629 retval
|= PIPE_BIND_TRANSFER_READ
;
630 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
631 retval
|= PIPE_BIND_TRANSFER_WRITE
;
633 return retval
== usage
;
636 static void evergreen_set_blend_color(struct pipe_context
*ctx
,
637 const struct pipe_blend_color
*state
)
639 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
640 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
645 rstate
->id
= R600_PIPE_STATE_BLEND_COLOR
;
646 r600_pipe_state_add_reg(rstate
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]), 0xFFFFFFFF, NULL
, 0);
647 r600_pipe_state_add_reg(rstate
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]), 0xFFFFFFFF, NULL
, 0);
648 r600_pipe_state_add_reg(rstate
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]), 0xFFFFFFFF, NULL
, 0);
649 r600_pipe_state_add_reg(rstate
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]), 0xFFFFFFFF, NULL
, 0);
651 free(rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
]);
652 rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
] = rstate
;
653 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
656 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
657 const struct pipe_blend_state
*state
)
659 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
660 struct r600_pipe_blend
*blend
= CALLOC_STRUCT(r600_pipe_blend
);
661 struct r600_pipe_state
*rstate
;
662 u32 color_control
, target_mask
;
663 /* FIXME there is more then 8 framebuffer */
664 unsigned blend_cntl
[8];
670 rstate
= &blend
->rstate
;
672 rstate
->id
= R600_PIPE_STATE_BLEND
;
675 color_control
= S_028808_MODE(1);
676 if (state
->logicop_enable
) {
677 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
679 color_control
|= (0xcc << 16);
681 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
682 if (state
->independent_blend_enable
) {
683 for (int i
= 0; i
< 8; i
++) {
684 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
687 for (int i
= 0; i
< 8; i
++) {
688 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
691 blend
->cb_target_mask
= target_mask
;
693 r600_pipe_state_add_reg(rstate
, R_028808_CB_COLOR_CONTROL
,
694 color_control
, 0xFFFFFFFD, NULL
, 0);
696 if (rctx
->chip_class
!= CAYMAN
)
697 r600_pipe_state_add_reg(rstate
, R_028C3C_PA_SC_AA_MASK
, 0xFFFFFFFF, 0xFFFFFFFF, NULL
, 0);
699 r600_pipe_state_add_reg(rstate
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 0xFFFFFFFF, 0xFFFFFFFF, NULL
, 0);
700 r600_pipe_state_add_reg(rstate
, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1
, 0xFFFFFFFF, 0xFFFFFFFF, NULL
, 0);
703 for (int i
= 0; i
< 8; i
++) {
704 /* state->rt entries > 0 only written if independent blending */
705 const int j
= state
->independent_blend_enable
? i
: 0;
707 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
708 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
709 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
710 unsigned eqA
= state
->rt
[j
].alpha_func
;
711 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
712 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
715 if (!state
->rt
[j
].blend_enable
)
718 blend_cntl
[i
] |= S_028780_BLEND_CONTROL_ENABLE(1);
719 blend_cntl
[i
] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
720 blend_cntl
[i
] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
721 blend_cntl
[i
] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
723 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
724 blend_cntl
[i
] |= S_028780_SEPARATE_ALPHA_BLEND(1);
725 blend_cntl
[i
] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
726 blend_cntl
[i
] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
727 blend_cntl
[i
] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
730 for (int i
= 0; i
< 8; i
++) {
731 r600_pipe_state_add_reg(rstate
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
[i
], 0xFFFFFFFF, NULL
, 0);
737 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
738 const struct pipe_depth_stencil_alpha_state
*state
)
740 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
741 struct r600_pipe_dsa
*dsa
= CALLOC_STRUCT(r600_pipe_dsa
);
742 unsigned db_depth_control
, alpha_test_control
, alpha_ref
, db_shader_control
;
743 unsigned stencil_ref_mask
, stencil_ref_mask_bf
, db_render_override
, db_render_control
;
744 struct r600_pipe_state
*rstate
;
750 rstate
= &dsa
->rstate
;
752 rstate
->id
= R600_PIPE_STATE_DSA
;
753 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
754 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
755 stencil_ref_mask
= 0;
756 stencil_ref_mask_bf
= 0;
757 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
758 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
759 S_028800_ZFUNC(state
->depth
.func
);
762 if (state
->stencil
[0].enabled
) {
763 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
764 db_depth_control
|= S_028800_STENCILFUNC(r600_translate_ds_func(state
->stencil
[0].func
));
765 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
766 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
767 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
770 stencil_ref_mask
= S_028430_STENCILMASK(state
->stencil
[0].valuemask
) |
771 S_028430_STENCILWRITEMASK(state
->stencil
[0].writemask
);
772 if (state
->stencil
[1].enabled
) {
773 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
774 db_depth_control
|= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state
->stencil
[1].func
));
775 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
776 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
777 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
778 stencil_ref_mask_bf
= S_028434_STENCILMASK_BF(state
->stencil
[1].valuemask
) |
779 S_028434_STENCILWRITEMASK_BF(state
->stencil
[1].writemask
);
784 alpha_test_control
= 0;
786 if (state
->alpha
.enabled
) {
787 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
788 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
789 alpha_ref
= fui(state
->alpha
.ref_value
);
791 dsa
->alpha_ref
= alpha_ref
;
794 db_render_control
= 0;
795 db_render_override
= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
) |
796 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
797 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
798 /* TODO db_render_override depends on query */
799 r600_pipe_state_add_reg(rstate
, R_028028_DB_STENCIL_CLEAR
, 0x00000000, 0xFFFFFFFF, NULL
, 0);
800 r600_pipe_state_add_reg(rstate
, R_02802C_DB_DEPTH_CLEAR
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
801 r600_pipe_state_add_reg(rstate
, R_028410_SX_ALPHA_TEST_CONTROL
, alpha_test_control
, 0xFFFFFFFF, NULL
, 0);
802 r600_pipe_state_add_reg(rstate
,
803 R_028430_DB_STENCILREFMASK
, stencil_ref_mask
,
804 0xFFFFFFFF & C_028430_STENCILREF
, NULL
, 0);
805 r600_pipe_state_add_reg(rstate
,
806 R_028434_DB_STENCILREFMASK_BF
, stencil_ref_mask_bf
,
807 0xFFFFFFFF & C_028434_STENCILREF_BF
, NULL
, 0);
808 r600_pipe_state_add_reg(rstate
, R_0286DC_SPI_FOG_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
, 0);
809 r600_pipe_state_add_reg(rstate
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
, 0xFFFFFFFF, NULL
, 0);
810 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
811 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
812 * evergreen_pipe_shader_ps().*/
813 r600_pipe_state_add_reg(rstate
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
, 0xFFFFFFBC, NULL
, 0);
814 r600_pipe_state_add_reg(rstate
, R_028000_DB_RENDER_CONTROL
, db_render_control
, 0xFFFFFFFF, NULL
, 0);
815 r600_pipe_state_add_reg(rstate
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
, 0xFFFFFFFF, NULL
, 0);
816 r600_pipe_state_add_reg(rstate
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0, 0xFFFFFFFF, NULL
, 0);
817 r600_pipe_state_add_reg(rstate
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0, 0xFFFFFFFF, NULL
, 0);
818 r600_pipe_state_add_reg(rstate
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0, 0xFFFFFFFF, NULL
, 0);
819 r600_pipe_state_add_reg(rstate
, R_028B70_DB_ALPHA_TO_MASK
, 0x0000AA00, 0xFFFFFFFF, NULL
, 0);
824 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
825 const struct pipe_rasterizer_state
*state
)
827 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
828 struct r600_pipe_rasterizer
*rs
= CALLOC_STRUCT(r600_pipe_rasterizer
);
829 struct r600_pipe_state
*rstate
;
831 unsigned prov_vtx
= 1, polygon_dual_mode
;
838 rstate
= &rs
->rstate
;
839 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
840 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
841 rs
->flatshade
= state
->flatshade
;
842 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
844 clip_rule
= state
->scissor
? 0xAAAA : 0xFFFF;
847 rs
->offset_units
= state
->offset_units
;
848 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
850 rstate
->id
= R600_PIPE_STATE_RASTERIZER
;
851 if (state
->flatshade_first
)
853 tmp
= S_0286D4_FLAT_SHADE_ENA(1);
854 if (state
->sprite_coord_enable
) {
855 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
856 S_0286D4_PNT_SPRITE_OVRD_X(2) |
857 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
858 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
859 S_0286D4_PNT_SPRITE_OVRD_W(1);
860 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
861 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
864 r600_pipe_state_add_reg(rstate
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
, 0xFFFFFFFF, NULL
, 0);
866 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
867 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
868 r600_pipe_state_add_reg(rstate
, R_028814_PA_SU_SC_MODE_CNTL
,
869 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
870 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
871 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
872 S_028814_FACE(!state
->front_ccw
) |
873 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
874 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
875 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
876 S_028814_POLY_MODE(polygon_dual_mode
) |
877 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
878 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)), 0xFFFFFFFF, NULL
, 0);
879 r600_pipe_state_add_reg(rstate
, R_02881C_PA_CL_VS_OUT_CNTL
,
880 S_02881C_USE_VTX_POINT_SIZE(state
->point_size_per_vertex
) |
881 S_02881C_VS_OUT_MISC_VEC_ENA(state
->point_size_per_vertex
), 0xFFFFFFFF, NULL
, 0);
882 r600_pipe_state_add_reg(rstate
, R_028820_PA_CL_NANINF_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
, 0);
883 /* point size 12.4 fixed point */
884 tmp
= (unsigned)(state
->point_size
* 8.0);
885 r600_pipe_state_add_reg(rstate
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
), 0xFFFFFFFF, NULL
, 0);
886 r600_pipe_state_add_reg(rstate
, R_028A04_PA_SU_POINT_MINMAX
, 0x80000000, 0xFFFFFFFF, NULL
, 0);
888 tmp
= (unsigned)state
->line_width
* 8;
889 r600_pipe_state_add_reg(rstate
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
), 0xFFFFFFFF, NULL
, 0);
891 if (rctx
->chip_class
== CAYMAN
) {
892 r600_pipe_state_add_reg(rstate
, CM_R_028BDC_PA_SC_LINE_CNTL
, 0x00000400, 0xFFFFFFFF, NULL
, 0);
893 r600_pipe_state_add_reg(rstate
, CM_R_028BE4_PA_SU_VTX_CNTL
,
894 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
),
895 0xFFFFFFFF, NULL
, 0);
896 r600_pipe_state_add_reg(rstate
, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
897 r600_pipe_state_add_reg(rstate
, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
898 r600_pipe_state_add_reg(rstate
, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
899 r600_pipe_state_add_reg(rstate
, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
903 r600_pipe_state_add_reg(rstate
, R_028C00_PA_SC_LINE_CNTL
, 0x00000400, 0xFFFFFFFF, NULL
, 0);
905 r600_pipe_state_add_reg(rstate
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
906 r600_pipe_state_add_reg(rstate
, R_028C10_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
907 r600_pipe_state_add_reg(rstate
, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
908 r600_pipe_state_add_reg(rstate
, R_028C18_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
910 r600_pipe_state_add_reg(rstate
, R_028C08_PA_SU_VTX_CNTL
,
911 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
),
912 0xFFFFFFFF, NULL
, 0);
914 r600_pipe_state_add_reg(rstate
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 0x0, 0xFFFFFFFF, NULL
, 0);
915 r600_pipe_state_add_reg(rstate
, R_02820C_PA_SC_CLIPRECT_RULE
, clip_rule
, 0xFFFFFFFF, NULL
, 0);
919 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
920 const struct pipe_sampler_state
*state
)
922 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
924 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
926 if (rstate
== NULL
) {
930 rstate
->id
= R600_PIPE_STATE_SAMPLER
;
931 util_pack_color(state
->border_color
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
932 r600_pipe_state_add_reg_noblock(rstate
, R_03C000_SQ_TEX_SAMPLER_WORD0_0
,
933 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
934 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
935 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
936 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
937 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
938 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
939 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
940 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
941 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0), 0xFFFFFFFF, NULL
, 0);
942 r600_pipe_state_add_reg_noblock(rstate
, R_03C004_SQ_TEX_SAMPLER_WORD1_0
,
943 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
944 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)),
945 0xFFFFFFFF, NULL
, 0);
946 r600_pipe_state_add_reg_noblock(rstate
, R_03C008_SQ_TEX_SAMPLER_WORD2_0
,
947 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
948 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
950 0xFFFFFFFF, NULL
, 0);
953 r600_pipe_state_add_reg_noblock(rstate
, R_00A404_TD_PS_SAMPLER0_BORDER_RED
, fui(state
->border_color
[0]), 0xFFFFFFFF, NULL
, 0);
954 r600_pipe_state_add_reg_noblock(rstate
, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN
, fui(state
->border_color
[1]), 0xFFFFFFFF, NULL
, 0);
955 r600_pipe_state_add_reg_noblock(rstate
, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE
, fui(state
->border_color
[2]), 0xFFFFFFFF, NULL
, 0);
956 r600_pipe_state_add_reg_noblock(rstate
, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA
, fui(state
->border_color
[3]), 0xFFFFFFFF, NULL
, 0);
961 static struct pipe_sampler_view
*evergreen_create_sampler_view(struct pipe_context
*ctx
,
962 struct pipe_resource
*texture
,
963 const struct pipe_sampler_view
*state
)
965 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
966 struct r600_pipe_resource_state
*rstate
;
967 struct r600_resource_texture
*tmp
= (struct r600_resource_texture
*)texture
;
968 struct r600_resource
*rbuffer
;
969 unsigned format
, endian
;
970 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
971 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
972 struct r600_bo
*bo
[2];
976 rstate
= &view
->state
;
978 /* initialize base object */
980 view
->base
.texture
= NULL
;
981 pipe_reference(NULL
, &texture
->reference
);
982 view
->base
.texture
= texture
;
983 view
->base
.reference
.count
= 1;
984 view
->base
.context
= ctx
;
986 swizzle
[0] = state
->swizzle_r
;
987 swizzle
[1] = state
->swizzle_g
;
988 swizzle
[2] = state
->swizzle_b
;
989 swizzle
[3] = state
->swizzle_a
;
991 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
993 &word4
, &yuv_format
);
998 if (tmp
->depth
&& !tmp
->is_flushing_texture
) {
999 r600_texture_depth_flush(ctx
, texture
, TRUE
);
1000 tmp
= tmp
->flushed_depth_texture
;
1003 endian
= r600_colorformat_endian_swap(format
);
1005 if (tmp
->force_int_type
) {
1006 word4
&= C_030010_NUM_FORMAT_ALL
;
1007 word4
|= S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_INT
);
1010 rbuffer
= &tmp
->resource
;
1011 bo
[0] = rbuffer
->bo
;
1012 bo
[1] = rbuffer
->bo
;
1014 pitch
= align(tmp
->pitch_in_blocks
[0] * util_format_get_blockwidth(state
->format
), 8);
1015 array_mode
= tmp
->array_mode
[0];
1016 tile_type
= tmp
->tile_type
;
1018 rstate
->bo
[0] = bo
[0];
1019 rstate
->bo
[1] = bo
[1];
1020 rstate
->bo_usage
[0] = RADEON_USAGE_READ
;
1021 rstate
->bo_usage
[1] = RADEON_USAGE_READ
;
1022 rstate
->val
[0] = (S_030000_DIM(r600_tex_dim(texture
->target
)) |
1023 S_030000_PITCH((pitch
/ 8) - 1) |
1024 S_030000_NON_DISP_TILING_ORDER(tile_type
) |
1025 S_030000_TEX_WIDTH(texture
->width0
- 1));
1026 rstate
->val
[1] = (S_030004_TEX_HEIGHT(texture
->height0
- 1) |
1027 S_030004_TEX_DEPTH(texture
->depth0
- 1) |
1028 S_030004_ARRAY_MODE(array_mode
));
1029 rstate
->val
[2] = tmp
->offset
[0] >> 8;
1030 rstate
->val
[3] = tmp
->offset
[1] >> 8;
1031 rstate
->val
[4] = (word4
|
1032 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
1033 S_030010_ENDIAN_SWAP(endian
) |
1034 S_030010_BASE_LEVEL(state
->u
.tex
.first_level
));
1035 rstate
->val
[5] = (S_030014_LAST_LEVEL(state
->u
.tex
.last_level
) |
1036 S_030014_BASE_ARRAY(0) |
1037 S_030014_LAST_ARRAY(0));
1038 rstate
->val
[6] = (S_030018_MAX_ANISO(4 /* max 16 samples */));
1039 rstate
->val
[7] = (S_03001C_DATA_FORMAT(format
) |
1040 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
));
1045 static void evergreen_set_vs_sampler_view(struct pipe_context
*ctx
, unsigned count
,
1046 struct pipe_sampler_view
**views
)
1048 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1049 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
1051 for (int i
= 0; i
< count
; i
++) {
1053 evergreen_context_pipe_state_set_vs_resource(&rctx
->ctx
, &resource
[i
]->state
,
1054 i
+ R600_MAX_CONST_BUFFERS
);
1059 static void evergreen_set_ps_sampler_view(struct pipe_context
*ctx
, unsigned count
,
1060 struct pipe_sampler_view
**views
)
1062 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1063 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
1067 for (i
= 0; i
< count
; i
++) {
1068 if (&rctx
->ps_samplers
.views
[i
]->base
!= views
[i
]) {
1070 if (((struct r600_resource_texture
*)resource
[i
]->base
.texture
)->depth
)
1072 evergreen_context_pipe_state_set_ps_resource(&rctx
->ctx
, &resource
[i
]->state
,
1073 i
+ R600_MAX_CONST_BUFFERS
);
1075 evergreen_context_pipe_state_set_ps_resource(&rctx
->ctx
, NULL
,
1076 i
+ R600_MAX_CONST_BUFFERS
);
1078 pipe_sampler_view_reference(
1079 (struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
],
1083 if (((struct r600_resource_texture
*)resource
[i
]->base
.texture
)->depth
)
1088 for (i
= count
; i
< NUM_TEX_UNITS
; i
++) {
1089 if (rctx
->ps_samplers
.views
[i
]) {
1090 evergreen_context_pipe_state_set_ps_resource(&rctx
->ctx
, NULL
,
1091 i
+ R600_MAX_CONST_BUFFERS
);
1092 pipe_sampler_view_reference((struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
], NULL
);
1095 rctx
->have_depth_texture
= has_depth
;
1096 rctx
->ps_samplers
.n_views
= count
;
1099 static void evergreen_bind_ps_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
1101 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1102 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
1105 memcpy(rctx
->ps_samplers
.samplers
, states
, sizeof(void*) * count
);
1106 rctx
->ps_samplers
.n_samplers
= count
;
1108 for (int i
= 0; i
< count
; i
++) {
1109 evergreen_context_pipe_state_set_ps_sampler(&rctx
->ctx
, rstates
[i
], i
);
1113 static void evergreen_bind_vs_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
1115 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1116 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
1118 for (int i
= 0; i
< count
; i
++) {
1119 evergreen_context_pipe_state_set_vs_sampler(&rctx
->ctx
, rstates
[i
], i
);
1123 static void evergreen_set_clip_state(struct pipe_context
*ctx
,
1124 const struct pipe_clip_state
*state
)
1126 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1127 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1132 rctx
->clip
= *state
;
1133 rstate
->id
= R600_PIPE_STATE_CLIP
;
1134 for (int i
= 0; i
< state
->nr
; i
++) {
1135 r600_pipe_state_add_reg(rstate
,
1136 R_0285BC_PA_CL_UCP0_X
+ i
* 16,
1137 fui(state
->ucp
[i
][0]), 0xFFFFFFFF, NULL
, 0);
1138 r600_pipe_state_add_reg(rstate
,
1139 R_0285C0_PA_CL_UCP0_Y
+ i
* 16,
1140 fui(state
->ucp
[i
][1]) , 0xFFFFFFFF, NULL
, 0);
1141 r600_pipe_state_add_reg(rstate
,
1142 R_0285C4_PA_CL_UCP0_Z
+ i
* 16,
1143 fui(state
->ucp
[i
][2]), 0xFFFFFFFF, NULL
, 0);
1144 r600_pipe_state_add_reg(rstate
,
1145 R_0285C8_PA_CL_UCP0_W
+ i
* 16,
1146 fui(state
->ucp
[i
][3]), 0xFFFFFFFF, NULL
, 0);
1148 r600_pipe_state_add_reg(rstate
, R_028810_PA_CL_CLIP_CNTL
,
1149 S_028810_PS_UCP_MODE(3) | ((1 << state
->nr
) - 1) |
1150 S_028810_ZCLIP_NEAR_DISABLE(state
->depth_clamp
) |
1151 S_028810_ZCLIP_FAR_DISABLE(state
->depth_clamp
), 0xFFFFFFFF, NULL
, 0);
1153 free(rctx
->states
[R600_PIPE_STATE_CLIP
]);
1154 rctx
->states
[R600_PIPE_STATE_CLIP
] = rstate
;
1155 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1158 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
1159 const struct pipe_poly_stipple
*state
)
1163 static void evergreen_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1167 static void evergreen_set_scissor_state(struct pipe_context
*ctx
,
1168 const struct pipe_scissor_state
*state
)
1170 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1171 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1177 rstate
->id
= R600_PIPE_STATE_SCISSOR
;
1178 tl
= S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
);
1179 br
= S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
);
1180 r600_pipe_state_add_reg(rstate
,
1181 R_028210_PA_SC_CLIPRECT_0_TL
, tl
,
1182 0xFFFFFFFF, NULL
, 0);
1183 r600_pipe_state_add_reg(rstate
,
1184 R_028214_PA_SC_CLIPRECT_0_BR
, br
,
1185 0xFFFFFFFF, NULL
, 0);
1186 r600_pipe_state_add_reg(rstate
,
1187 R_028218_PA_SC_CLIPRECT_1_TL
, tl
,
1188 0xFFFFFFFF, NULL
, 0);
1189 r600_pipe_state_add_reg(rstate
,
1190 R_02821C_PA_SC_CLIPRECT_1_BR
, br
,
1191 0xFFFFFFFF, NULL
, 0);
1192 r600_pipe_state_add_reg(rstate
,
1193 R_028220_PA_SC_CLIPRECT_2_TL
, tl
,
1194 0xFFFFFFFF, NULL
, 0);
1195 r600_pipe_state_add_reg(rstate
,
1196 R_028224_PA_SC_CLIPRECT_2_BR
, br
,
1197 0xFFFFFFFF, NULL
, 0);
1198 r600_pipe_state_add_reg(rstate
,
1199 R_028228_PA_SC_CLIPRECT_3_TL
, tl
,
1200 0xFFFFFFFF, NULL
, 0);
1201 r600_pipe_state_add_reg(rstate
,
1202 R_02822C_PA_SC_CLIPRECT_3_BR
, br
,
1203 0xFFFFFFFF, NULL
, 0);
1205 free(rctx
->states
[R600_PIPE_STATE_SCISSOR
]);
1206 rctx
->states
[R600_PIPE_STATE_SCISSOR
] = rstate
;
1207 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1210 static void evergreen_set_stencil_ref(struct pipe_context
*ctx
,
1211 const struct pipe_stencil_ref
*state
)
1213 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1214 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1220 rctx
->stencil_ref
= *state
;
1221 rstate
->id
= R600_PIPE_STATE_STENCIL_REF
;
1222 tmp
= S_028430_STENCILREF(state
->ref_value
[0]);
1223 r600_pipe_state_add_reg(rstate
,
1224 R_028430_DB_STENCILREFMASK
, tmp
,
1225 ~C_028430_STENCILREF
, NULL
, 0);
1226 tmp
= S_028434_STENCILREF_BF(state
->ref_value
[1]);
1227 r600_pipe_state_add_reg(rstate
,
1228 R_028434_DB_STENCILREFMASK_BF
, tmp
,
1229 ~C_028434_STENCILREF_BF
, NULL
, 0);
1231 free(rctx
->states
[R600_PIPE_STATE_STENCIL_REF
]);
1232 rctx
->states
[R600_PIPE_STATE_STENCIL_REF
] = rstate
;
1233 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1236 static void evergreen_set_viewport_state(struct pipe_context
*ctx
,
1237 const struct pipe_viewport_state
*state
)
1239 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1240 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1245 rctx
->viewport
= *state
;
1246 rstate
->id
= R600_PIPE_STATE_VIEWPORT
;
1247 r600_pipe_state_add_reg(rstate
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 0x00000000, 0xFFFFFFFF, NULL
, 0);
1248 r600_pipe_state_add_reg(rstate
, R_0282D4_PA_SC_VPORT_ZMAX_0
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
1249 r600_pipe_state_add_reg(rstate
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]), 0xFFFFFFFF, NULL
, 0);
1250 r600_pipe_state_add_reg(rstate
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]), 0xFFFFFFFF, NULL
, 0);
1251 r600_pipe_state_add_reg(rstate
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]), 0xFFFFFFFF, NULL
, 0);
1252 r600_pipe_state_add_reg(rstate
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]), 0xFFFFFFFF, NULL
, 0);
1253 r600_pipe_state_add_reg(rstate
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]), 0xFFFFFFFF, NULL
, 0);
1254 r600_pipe_state_add_reg(rstate
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]), 0xFFFFFFFF, NULL
, 0);
1255 r600_pipe_state_add_reg(rstate
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F, 0xFFFFFFFF, NULL
, 0);
1257 free(rctx
->states
[R600_PIPE_STATE_VIEWPORT
]);
1258 rctx
->states
[R600_PIPE_STATE_VIEWPORT
] = rstate
;
1259 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1262 static void evergreen_cb(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
1263 const struct pipe_framebuffer_state
*state
, int cb
)
1265 struct r600_resource_texture
*rtex
;
1266 struct r600_resource
*rbuffer
;
1267 struct r600_surface
*surf
;
1268 unsigned level
= state
->cbufs
[cb
]->u
.tex
.level
;
1269 unsigned pitch
, slice
;
1270 unsigned color_info
;
1271 unsigned format
, swap
, ntype
, endian
;
1274 const struct util_format_description
*desc
;
1275 struct r600_bo
*bo
[3];
1278 surf
= (struct r600_surface
*)state
->cbufs
[cb
];
1279 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
1282 rctx
->have_depth_fb
= TRUE
;
1284 if (rtex
->depth
&& !rtex
->is_flushing_texture
) {
1285 r600_texture_depth_flush(&rctx
->context
, state
->cbufs
[cb
]->texture
, TRUE
);
1286 rtex
= rtex
->flushed_depth_texture
;
1289 rbuffer
= &rtex
->resource
;
1290 bo
[0] = rbuffer
->bo
;
1291 bo
[1] = rbuffer
->bo
;
1292 bo
[2] = rbuffer
->bo
;
1294 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1295 offset
= r600_texture_get_offset((struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
,
1296 level
, state
->cbufs
[cb
]->u
.tex
.first_layer
);
1297 pitch
= rtex
->pitch_in_blocks
[level
] / 8 - 1;
1298 slice
= rtex
->pitch_in_blocks
[level
] * surf
->aligned_height
/ 64 - 1;
1299 desc
= util_format_description(surf
->base
.format
);
1300 for (i
= 0; i
< 4; i
++) {
1301 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1305 ntype
= V_028C70_NUMBER_UNORM
;
1306 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1307 ntype
= V_028C70_NUMBER_SRGB
;
1308 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
)
1309 ntype
= V_028C70_NUMBER_SNORM
;
1311 format
= r600_translate_colorformat(surf
->base
.format
);
1312 swap
= r600_translate_colorswap(surf
->base
.format
);
1313 if (rbuffer
->b
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1314 endian
= ENDIAN_NONE
;
1316 endian
= r600_colorformat_endian_swap(format
);
1319 /* disable when gallium grows int textures */
1320 if ((format
== FMT_32_32_32_32
|| format
== FMT_16_16_16_16
) && rtex
->force_int_type
)
1321 ntype
= V_028C70_NUMBER_UINT
;
1323 color_info
= S_028C70_FORMAT(format
) |
1324 S_028C70_COMP_SWAP(swap
) |
1325 S_028C70_ARRAY_MODE(rtex
->array_mode
[level
]) |
1326 S_028C70_BLEND_CLAMP(1) |
1327 S_028C70_NUMBER_TYPE(ntype
) |
1328 S_028C70_ENDIAN(endian
);
1331 /* EXPORT_NORM is an optimzation that can be enabled for better
1332 * performance in certain cases.
1333 * EXPORT_NORM can be enabled if:
1334 * - 11-bit or smaller UNORM/SNORM/SRGB
1335 * - 16-bit or smaller FLOAT
1337 /* FIXME: This should probably be the same for all CBs if we want
1338 * useful alpha tests. */
1339 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1340 ((desc
->channel
[i
].size
< 12 &&
1341 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1342 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
1343 (desc
->channel
[i
].size
< 17 &&
1344 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1345 color_info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
1346 rctx
->export_16bpc
= true;
1348 rctx
->export_16bpc
= false;
1350 rctx
->alpha_ref_dirty
= true;
1352 if (rtex
->array_mode
[level
] > V_028C70_ARRAY_LINEAR_ALIGNED
) {
1353 tile_type
= rtex
->tile_type
;
1354 } else /* workaround for linear buffers */
1357 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1358 r600_pipe_state_add_reg(rstate
,
1359 R_028C60_CB_COLOR0_BASE
+ cb
* 0x3C,
1360 offset
>> 8, 0xFFFFFFFF, bo
[0], RADEON_USAGE_READWRITE
);
1361 r600_pipe_state_add_reg(rstate
,
1362 R_028C78_CB_COLOR0_DIM
+ cb
* 0x3C,
1363 0x0, 0xFFFFFFFF, NULL
, 0);
1364 r600_pipe_state_add_reg(rstate
,
1365 R_028C70_CB_COLOR0_INFO
+ cb
* 0x3C,
1366 color_info
, 0xFFFFFFFF, bo
[0], RADEON_USAGE_READWRITE
);
1367 r600_pipe_state_add_reg(rstate
,
1368 R_028C64_CB_COLOR0_PITCH
+ cb
* 0x3C,
1369 S_028C64_PITCH_TILE_MAX(pitch
),
1370 0xFFFFFFFF, NULL
, 0);
1371 r600_pipe_state_add_reg(rstate
,
1372 R_028C68_CB_COLOR0_SLICE
+ cb
* 0x3C,
1373 S_028C68_SLICE_TILE_MAX(slice
),
1374 0xFFFFFFFF, NULL
, 0);
1375 r600_pipe_state_add_reg(rstate
,
1376 R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C,
1377 0x00000000, 0xFFFFFFFF, NULL
, 0);
1378 r600_pipe_state_add_reg(rstate
,
1379 R_028C74_CB_COLOR0_ATTRIB
+ cb
* 0x3C,
1380 S_028C74_NON_DISP_TILING_ORDER(tile_type
),
1381 0xFFFFFFFF, bo
[0], RADEON_USAGE_READWRITE
);
1384 static void evergreen_db(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
1385 const struct pipe_framebuffer_state
*state
)
1387 struct r600_resource_texture
*rtex
;
1388 struct r600_surface
*surf
;
1389 unsigned level
, first_layer
;
1390 unsigned pitch
, slice
, format
;
1393 if (state
->zsbuf
== NULL
)
1396 surf
= (struct r600_surface
*)state
->zsbuf
;
1397 rtex
= (struct r600_resource_texture
*)surf
->base
.texture
;
1399 level
= surf
->base
.u
.tex
.level
;
1400 first_layer
= surf
->base
.u
.tex
.first_layer
;
1401 offset
= r600_texture_get_offset(rtex
, level
, first_layer
);
1402 pitch
= rtex
->pitch_in_blocks
[level
] / 8 - 1;
1403 slice
= rtex
->pitch_in_blocks
[level
] * surf
->aligned_height
/ 64 - 1;
1404 format
= r600_translate_dbformat(rtex
->real_format
);
1406 r600_pipe_state_add_reg(rstate
, R_028048_DB_Z_READ_BASE
,
1407 offset
>> 8, 0xFFFFFFFF, rtex
->resource
.bo
, RADEON_USAGE_READWRITE
);
1408 r600_pipe_state_add_reg(rstate
, R_028050_DB_Z_WRITE_BASE
,
1409 offset
>> 8, 0xFFFFFFFF, rtex
->resource
.bo
, RADEON_USAGE_READWRITE
);
1410 r600_pipe_state_add_reg(rstate
, R_028008_DB_DEPTH_VIEW
, 0x00000000, 0xFFFFFFFF, NULL
, 0);
1412 if (rtex
->stencil
) {
1413 uint32_t stencil_offset
=
1414 r600_texture_get_offset(rtex
->stencil
, level
, first_layer
);
1416 r600_pipe_state_add_reg(rstate
, R_02804C_DB_STENCIL_READ_BASE
,
1417 stencil_offset
>> 8, 0xFFFFFFFF, rtex
->stencil
->resource
.bo
, RADEON_USAGE_READWRITE
);
1418 r600_pipe_state_add_reg(rstate
, R_028054_DB_STENCIL_WRITE_BASE
,
1419 stencil_offset
>> 8, 0xFFFFFFFF, rtex
->stencil
->resource
.bo
, RADEON_USAGE_READWRITE
);
1420 r600_pipe_state_add_reg(rstate
, R_028044_DB_STENCIL_INFO
,
1421 1, 0xFFFFFFFF, rtex
->stencil
->resource
.bo
, RADEON_USAGE_READWRITE
);
1423 r600_pipe_state_add_reg(rstate
, R_028044_DB_STENCIL_INFO
,
1424 0, 0xFFFFFFFF, NULL
, RADEON_USAGE_READWRITE
);
1427 r600_pipe_state_add_reg(rstate
, R_028040_DB_Z_INFO
,
1428 S_028040_ARRAY_MODE(rtex
->array_mode
[level
]) | S_028040_FORMAT(format
),
1429 0xFFFFFFFF, rtex
->resource
.bo
, RADEON_USAGE_READWRITE
);
1430 r600_pipe_state_add_reg(rstate
, R_028058_DB_DEPTH_SIZE
,
1431 S_028058_PITCH_TILE_MAX(pitch
),
1432 0xFFFFFFFF, NULL
, 0);
1433 r600_pipe_state_add_reg(rstate
, R_02805C_DB_DEPTH_SLICE
,
1434 S_02805C_SLICE_TILE_MAX(slice
),
1435 0xFFFFFFFF, NULL
, 0);
1438 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
1439 const struct pipe_framebuffer_state
*state
)
1441 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1442 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1443 u32 shader_mask
, tl
, br
, target_mask
;
1444 int tl_x
, tl_y
, br_x
, br_y
;
1449 evergreen_context_flush_dest_caches(&rctx
->ctx
);
1450 rctx
->ctx
.num_dest_buffers
= state
->nr_cbufs
;
1452 /* unreference old buffer and reference new one */
1453 rstate
->id
= R600_PIPE_STATE_FRAMEBUFFER
;
1455 util_copy_framebuffer_state(&rctx
->framebuffer
, state
);
1458 rctx
->have_depth_fb
= 0;
1459 rctx
->nr_cbufs
= state
->nr_cbufs
;
1460 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1461 evergreen_cb(rctx
, rstate
, state
, i
);
1464 evergreen_db(rctx
, rstate
, state
);
1465 rctx
->ctx
.num_dest_buffers
++;
1468 target_mask
= 0x00000000;
1469 target_mask
= 0xFFFFFFFF;
1471 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1472 target_mask
^= 0xf << (i
* 4);
1473 shader_mask
|= 0xf << (i
* 4);
1477 br_x
= state
->width
;
1478 br_y
= state
->height
;
1479 /* EG hw workaround */
1484 /* cayman hw workaround */
1485 if (rctx
->chip_class
== CAYMAN
) {
1486 if (br_x
== 1 && br_y
== 1)
1489 tl
= S_028240_TL_X(tl_x
) | S_028240_TL_Y(tl_y
);
1490 br
= S_028244_BR_X(br_x
) | S_028244_BR_Y(br_y
);
1492 r600_pipe_state_add_reg(rstate
,
1493 R_028240_PA_SC_GENERIC_SCISSOR_TL
, tl
,
1494 0xFFFFFFFF, NULL
, 0);
1495 r600_pipe_state_add_reg(rstate
,
1496 R_028244_PA_SC_GENERIC_SCISSOR_BR
, br
,
1497 0xFFFFFFFF, NULL
, 0);
1498 r600_pipe_state_add_reg(rstate
,
1499 R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
,
1500 0xFFFFFFFF, NULL
, 0);
1501 r600_pipe_state_add_reg(rstate
,
1502 R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
,
1503 0xFFFFFFFF, NULL
, 0);
1504 r600_pipe_state_add_reg(rstate
,
1505 R_028030_PA_SC_SCREEN_SCISSOR_TL
, tl
,
1506 0xFFFFFFFF, NULL
, 0);
1507 r600_pipe_state_add_reg(rstate
,
1508 R_028034_PA_SC_SCREEN_SCISSOR_BR
, br
,
1509 0xFFFFFFFF, NULL
, 0);
1510 r600_pipe_state_add_reg(rstate
,
1511 R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
,
1512 0xFFFFFFFF, NULL
, 0);
1513 r600_pipe_state_add_reg(rstate
,
1514 R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
,
1515 0xFFFFFFFF, NULL
, 0);
1516 r600_pipe_state_add_reg(rstate
,
1517 R_028200_PA_SC_WINDOW_OFFSET
, 0x00000000,
1518 0xFFFFFFFF, NULL
, 0);
1519 r600_pipe_state_add_reg(rstate
,
1520 R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA,
1521 0xFFFFFFFF, NULL
, 0);
1523 r600_pipe_state_add_reg(rstate
, R_028238_CB_TARGET_MASK
,
1524 0x00000000, target_mask
, NULL
, 0);
1525 r600_pipe_state_add_reg(rstate
, R_02823C_CB_SHADER_MASK
,
1526 shader_mask
, 0xFFFFFFFF, NULL
, 0);
1529 if (rctx
->chip_class
== CAYMAN
) {
1530 r600_pipe_state_add_reg(rstate
, CM_R_028BE0_PA_SC_AA_CONFIG
,
1531 0x00000000, 0xFFFFFFFF, NULL
, 0);
1533 r600_pipe_state_add_reg(rstate
, R_028C04_PA_SC_AA_CONFIG
,
1534 0x00000000, 0xFFFFFFFF, NULL
, 0);
1535 r600_pipe_state_add_reg(rstate
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
,
1536 0x00000000, 0xFFFFFFFF, NULL
, 0);
1539 free(rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
]);
1540 rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
] = rstate
;
1541 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1544 evergreen_polygon_offset_update(rctx
);
1548 static void evergreen_texture_barrier(struct pipe_context
*ctx
)
1550 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1552 r600_context_flush_all(&rctx
->ctx
, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1553 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1554 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1555 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1556 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
1557 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
1558 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
1561 void evergreen_init_state_functions(struct r600_pipe_context
*rctx
)
1563 rctx
->context
.create_blend_state
= evergreen_create_blend_state
;
1564 rctx
->context
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
1565 rctx
->context
.create_fs_state
= r600_create_shader_state
;
1566 rctx
->context
.create_rasterizer_state
= evergreen_create_rs_state
;
1567 rctx
->context
.create_sampler_state
= evergreen_create_sampler_state
;
1568 rctx
->context
.create_sampler_view
= evergreen_create_sampler_view
;
1569 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
1570 rctx
->context
.create_vs_state
= r600_create_shader_state
;
1571 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1572 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
1573 rctx
->context
.bind_fragment_sampler_states
= evergreen_bind_ps_sampler
;
1574 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
1575 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1576 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1577 rctx
->context
.bind_vertex_sampler_states
= evergreen_bind_vs_sampler
;
1578 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
1579 rctx
->context
.delete_blend_state
= r600_delete_state
;
1580 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
1581 rctx
->context
.delete_fs_state
= r600_delete_ps_shader
;
1582 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1583 rctx
->context
.delete_sampler_state
= r600_delete_state
;
1584 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
1585 rctx
->context
.delete_vs_state
= r600_delete_vs_shader
;
1586 rctx
->context
.set_blend_color
= evergreen_set_blend_color
;
1587 rctx
->context
.set_clip_state
= evergreen_set_clip_state
;
1588 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1589 rctx
->context
.set_fragment_sampler_views
= evergreen_set_ps_sampler_view
;
1590 rctx
->context
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
1591 rctx
->context
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
1592 rctx
->context
.set_sample_mask
= evergreen_set_sample_mask
;
1593 rctx
->context
.set_scissor_state
= evergreen_set_scissor_state
;
1594 rctx
->context
.set_stencil_ref
= evergreen_set_stencil_ref
;
1595 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1596 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1597 rctx
->context
.set_vertex_sampler_views
= evergreen_set_vs_sampler_view
;
1598 rctx
->context
.set_viewport_state
= evergreen_set_viewport_state
;
1599 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1600 rctx
->context
.redefine_user_buffer
= u_default_redefine_user_buffer
;
1601 rctx
->context
.texture_barrier
= evergreen_texture_barrier
;
1604 static void cayman_init_config(struct r600_pipe_context
*rctx
)
1606 struct r600_pipe_state
*rstate
= &rctx
->config
;
1610 tmp
|= S_008C00_EXPORT_SRC_C(1);
1611 r600_pipe_state_add_reg(rstate
, R_008C00_SQ_CONFIG
, tmp
, 0xFFFFFFFF, NULL
, 0);
1613 /* always set the temp clauses */
1614 r600_pipe_state_add_reg(rstate
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), 0xFFFFFFFF, NULL
, 0);
1615 r600_pipe_state_add_reg(rstate
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 0, 0xFFFFFFFF, NULL
, 0);
1616 r600_pipe_state_add_reg(rstate
, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2
, 0, 0xFFFFFFFF, NULL
, 0);
1617 r600_pipe_state_add_reg(rstate
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8), 0xFFFFFFFF, NULL
, 0);
1619 r600_pipe_state_add_reg(rstate
, R_028A48_PA_SC_MODE_CNTL_0
, 0x0, 0xFFFFFFFF, NULL
, 0);
1620 r600_pipe_state_add_reg(rstate
, R_028A4C_PA_SC_MODE_CNTL_1
, 0x0, 0xFFFFFFFF, NULL
, 0);
1622 r600_pipe_state_add_reg(rstate
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1623 r600_pipe_state_add_reg(rstate
, R_028A14_VGT_HOS_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1624 r600_pipe_state_add_reg(rstate
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1625 r600_pipe_state_add_reg(rstate
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1626 r600_pipe_state_add_reg(rstate
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x0, 0xFFFFFFFF, NULL
, 0);
1627 r600_pipe_state_add_reg(rstate
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x0, 0xFFFFFFFF, NULL
, 0);
1628 r600_pipe_state_add_reg(rstate
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x0, 0xFFFFFFFF, NULL
, 0);
1629 r600_pipe_state_add_reg(rstate
, R_028A2C_VGT_GROUP_DECR
, 0x0, 0xFFFFFFFF, NULL
, 0);
1630 r600_pipe_state_add_reg(rstate
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1631 r600_pipe_state_add_reg(rstate
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1632 r600_pipe_state_add_reg(rstate
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1633 r600_pipe_state_add_reg(rstate
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1634 r600_pipe_state_add_reg(rstate
, R_028A40_VGT_GS_MODE
, 0x0, 0xFFFFFFFF, NULL
, 0);
1635 r600_pipe_state_add_reg(rstate
, R_028B94_VGT_STRMOUT_CONFIG
, 0x0, 0xFFFFFFFF, NULL
, 0);
1636 r600_pipe_state_add_reg(rstate
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0, 0xFFFFFFFF, NULL
, 0);
1637 r600_pipe_state_add_reg(rstate
, R_028AB4_VGT_REUSE_OFF
, 0x00000000, 0xFFFFFFFF, NULL
, 0);
1638 r600_pipe_state_add_reg(rstate
, R_028AB8_VGT_VTX_CNT_EN
, 0x0, 0xFFFFFFFF, NULL
, 0);
1639 r600_pipe_state_add_reg(rstate
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1, 0xFFFFFFFF, NULL
, 0);
1641 r600_pipe_state_add_reg(rstate
, R_028380_SQ_VTX_SEMANTIC_0
, 0x0, 0xFFFFFFFF, NULL
, 0);
1642 r600_pipe_state_add_reg(rstate
, R_028384_SQ_VTX_SEMANTIC_1
, 0x0, 0xFFFFFFFF, NULL
, 0);
1643 r600_pipe_state_add_reg(rstate
, R_028388_SQ_VTX_SEMANTIC_2
, 0x0, 0xFFFFFFFF, NULL
, 0);
1644 r600_pipe_state_add_reg(rstate
, R_02838C_SQ_VTX_SEMANTIC_3
, 0x0, 0xFFFFFFFF, NULL
, 0);
1645 r600_pipe_state_add_reg(rstate
, R_028390_SQ_VTX_SEMANTIC_4
, 0x0, 0xFFFFFFFF, NULL
, 0);
1646 r600_pipe_state_add_reg(rstate
, R_028394_SQ_VTX_SEMANTIC_5
, 0x0, 0xFFFFFFFF, NULL
, 0);
1647 r600_pipe_state_add_reg(rstate
, R_028398_SQ_VTX_SEMANTIC_6
, 0x0, 0xFFFFFFFF, NULL
, 0);
1648 r600_pipe_state_add_reg(rstate
, R_02839C_SQ_VTX_SEMANTIC_7
, 0x0, 0xFFFFFFFF, NULL
, 0);
1649 r600_pipe_state_add_reg(rstate
, R_0283A0_SQ_VTX_SEMANTIC_8
, 0x0, 0xFFFFFFFF, NULL
, 0);
1650 r600_pipe_state_add_reg(rstate
, R_0283A4_SQ_VTX_SEMANTIC_9
, 0x0, 0xFFFFFFFF, NULL
, 0);
1651 r600_pipe_state_add_reg(rstate
, R_0283A8_SQ_VTX_SEMANTIC_10
, 0x0, 0xFFFFFFFF, NULL
, 0);
1652 r600_pipe_state_add_reg(rstate
, R_0283AC_SQ_VTX_SEMANTIC_11
, 0x0, 0xFFFFFFFF, NULL
, 0);
1653 r600_pipe_state_add_reg(rstate
, R_0283B0_SQ_VTX_SEMANTIC_12
, 0x0, 0xFFFFFFFF, NULL
, 0);
1654 r600_pipe_state_add_reg(rstate
, R_0283B4_SQ_VTX_SEMANTIC_13
, 0x0, 0xFFFFFFFF, NULL
, 0);
1655 r600_pipe_state_add_reg(rstate
, R_0283B8_SQ_VTX_SEMANTIC_14
, 0x0, 0xFFFFFFFF, NULL
, 0);
1656 r600_pipe_state_add_reg(rstate
, R_0283BC_SQ_VTX_SEMANTIC_15
, 0x0, 0xFFFFFFFF, NULL
, 0);
1657 r600_pipe_state_add_reg(rstate
, R_0283C0_SQ_VTX_SEMANTIC_16
, 0x0, 0xFFFFFFFF, NULL
, 0);
1658 r600_pipe_state_add_reg(rstate
, R_0283C4_SQ_VTX_SEMANTIC_17
, 0x0, 0xFFFFFFFF, NULL
, 0);
1659 r600_pipe_state_add_reg(rstate
, R_0283C8_SQ_VTX_SEMANTIC_18
, 0x0, 0xFFFFFFFF, NULL
, 0);
1660 r600_pipe_state_add_reg(rstate
, R_0283CC_SQ_VTX_SEMANTIC_19
, 0x0, 0xFFFFFFFF, NULL
, 0);
1661 r600_pipe_state_add_reg(rstate
, R_0283D0_SQ_VTX_SEMANTIC_20
, 0x0, 0xFFFFFFFF, NULL
, 0);
1662 r600_pipe_state_add_reg(rstate
, R_0283D4_SQ_VTX_SEMANTIC_21
, 0x0, 0xFFFFFFFF, NULL
, 0);
1663 r600_pipe_state_add_reg(rstate
, R_0283D8_SQ_VTX_SEMANTIC_22
, 0x0, 0xFFFFFFFF, NULL
, 0);
1664 r600_pipe_state_add_reg(rstate
, R_0283DC_SQ_VTX_SEMANTIC_23
, 0x0, 0xFFFFFFFF, NULL
, 0);
1665 r600_pipe_state_add_reg(rstate
, R_0283E0_SQ_VTX_SEMANTIC_24
, 0x0, 0xFFFFFFFF, NULL
, 0);
1666 r600_pipe_state_add_reg(rstate
, R_0283E4_SQ_VTX_SEMANTIC_25
, 0x0, 0xFFFFFFFF, NULL
, 0);
1667 r600_pipe_state_add_reg(rstate
, R_0283E8_SQ_VTX_SEMANTIC_26
, 0x0, 0xFFFFFFFF, NULL
, 0);
1668 r600_pipe_state_add_reg(rstate
, R_0283EC_SQ_VTX_SEMANTIC_27
, 0x0, 0xFFFFFFFF, NULL
, 0);
1669 r600_pipe_state_add_reg(rstate
, R_0283F0_SQ_VTX_SEMANTIC_28
, 0x0, 0xFFFFFFFF, NULL
, 0);
1670 r600_pipe_state_add_reg(rstate
, R_0283F4_SQ_VTX_SEMANTIC_29
, 0x0, 0xFFFFFFFF, NULL
, 0);
1671 r600_pipe_state_add_reg(rstate
, R_0283F8_SQ_VTX_SEMANTIC_30
, 0x0, 0xFFFFFFFF, NULL
, 0);
1672 r600_pipe_state_add_reg(rstate
, R_0283FC_SQ_VTX_SEMANTIC_31
, 0x0, 0xFFFFFFFF, NULL
, 0);
1674 r600_pipe_state_add_reg(rstate
, R_028810_PA_CL_CLIP_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1676 r600_pipe_state_add_reg(rstate
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210, 0xffffffff, NULL
, 0);
1677 r600_pipe_state_add_reg(rstate
, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98, 0xffffffff, NULL
, 0);
1679 r600_pipe_state_add_reg(rstate
, CM_R_0288E8_SQ_LDS_ALLOC
, 0, 0xFFFFFFFF, NULL
, 0);
1680 r600_pipe_state_add_reg(rstate
, R_0288EC_SQ_LDS_ALLOC_PS
, 0, 0xFFFFFFFF, NULL
, 0);
1682 r600_pipe_state_add_reg(rstate
, CM_R_028804_DB_EQAA
, 0x110000, 0xFFFFFFFF, NULL
, 0);
1683 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1686 void evergreen_init_config(struct r600_pipe_context
*rctx
)
1688 struct r600_pipe_state
*rstate
= &rctx
->config
;
1693 int hs_prio
, cs_prio
, ls_prio
;
1707 int num_ps_stack_entries
;
1708 int num_vs_stack_entries
;
1709 int num_gs_stack_entries
;
1710 int num_es_stack_entries
;
1711 int num_hs_stack_entries
;
1712 int num_ls_stack_entries
;
1713 enum radeon_family family
;
1716 family
= rctx
->family
;
1718 if (rctx
->chip_class
== CAYMAN
) {
1719 cayman_init_config(rctx
);
1741 num_ps_threads
= 96;
1742 num_vs_threads
= 16;
1743 num_gs_threads
= 16;
1744 num_es_threads
= 16;
1745 num_hs_threads
= 16;
1746 num_ls_threads
= 16;
1747 num_ps_stack_entries
= 42;
1748 num_vs_stack_entries
= 42;
1749 num_gs_stack_entries
= 42;
1750 num_es_stack_entries
= 42;
1751 num_hs_stack_entries
= 42;
1752 num_ls_stack_entries
= 42;
1762 num_ps_threads
= 128;
1763 num_vs_threads
= 20;
1764 num_gs_threads
= 20;
1765 num_es_threads
= 20;
1766 num_hs_threads
= 20;
1767 num_ls_threads
= 20;
1768 num_ps_stack_entries
= 42;
1769 num_vs_stack_entries
= 42;
1770 num_gs_stack_entries
= 42;
1771 num_es_stack_entries
= 42;
1772 num_hs_stack_entries
= 42;
1773 num_ls_stack_entries
= 42;
1783 num_ps_threads
= 128;
1784 num_vs_threads
= 20;
1785 num_gs_threads
= 20;
1786 num_es_threads
= 20;
1787 num_hs_threads
= 20;
1788 num_ls_threads
= 20;
1789 num_ps_stack_entries
= 85;
1790 num_vs_stack_entries
= 85;
1791 num_gs_stack_entries
= 85;
1792 num_es_stack_entries
= 85;
1793 num_hs_stack_entries
= 85;
1794 num_ls_stack_entries
= 85;
1805 num_ps_threads
= 128;
1806 num_vs_threads
= 20;
1807 num_gs_threads
= 20;
1808 num_es_threads
= 20;
1809 num_hs_threads
= 20;
1810 num_ls_threads
= 20;
1811 num_ps_stack_entries
= 85;
1812 num_vs_stack_entries
= 85;
1813 num_gs_stack_entries
= 85;
1814 num_es_stack_entries
= 85;
1815 num_hs_stack_entries
= 85;
1816 num_ls_stack_entries
= 85;
1826 num_ps_threads
= 96;
1827 num_vs_threads
= 16;
1828 num_gs_threads
= 16;
1829 num_es_threads
= 16;
1830 num_hs_threads
= 16;
1831 num_ls_threads
= 16;
1832 num_ps_stack_entries
= 42;
1833 num_vs_stack_entries
= 42;
1834 num_gs_stack_entries
= 42;
1835 num_es_stack_entries
= 42;
1836 num_hs_stack_entries
= 42;
1837 num_ls_stack_entries
= 42;
1847 num_ps_threads
= 96;
1848 num_vs_threads
= 25;
1849 num_gs_threads
= 25;
1850 num_es_threads
= 25;
1851 num_hs_threads
= 25;
1852 num_ls_threads
= 25;
1853 num_ps_stack_entries
= 42;
1854 num_vs_stack_entries
= 42;
1855 num_gs_stack_entries
= 42;
1856 num_es_stack_entries
= 42;
1857 num_hs_stack_entries
= 42;
1858 num_ls_stack_entries
= 42;
1868 num_ps_threads
= 96;
1869 num_vs_threads
= 25;
1870 num_gs_threads
= 25;
1871 num_es_threads
= 25;
1872 num_hs_threads
= 25;
1873 num_ls_threads
= 25;
1874 num_ps_stack_entries
= 85;
1875 num_vs_stack_entries
= 85;
1876 num_gs_stack_entries
= 85;
1877 num_es_stack_entries
= 85;
1878 num_hs_stack_entries
= 85;
1879 num_ls_stack_entries
= 85;
1889 num_ps_threads
= 128;
1890 num_vs_threads
= 20;
1891 num_gs_threads
= 20;
1892 num_es_threads
= 20;
1893 num_hs_threads
= 20;
1894 num_ls_threads
= 20;
1895 num_ps_stack_entries
= 85;
1896 num_vs_stack_entries
= 85;
1897 num_gs_stack_entries
= 85;
1898 num_es_stack_entries
= 85;
1899 num_hs_stack_entries
= 85;
1900 num_ls_stack_entries
= 85;
1910 num_ps_threads
= 128;
1911 num_vs_threads
= 20;
1912 num_gs_threads
= 20;
1913 num_es_threads
= 20;
1914 num_hs_threads
= 20;
1915 num_ls_threads
= 20;
1916 num_ps_stack_entries
= 42;
1917 num_vs_stack_entries
= 42;
1918 num_gs_stack_entries
= 42;
1919 num_es_stack_entries
= 42;
1920 num_hs_stack_entries
= 42;
1921 num_ls_stack_entries
= 42;
1931 num_ps_threads
= 128;
1932 num_vs_threads
= 10;
1933 num_gs_threads
= 10;
1934 num_es_threads
= 10;
1935 num_hs_threads
= 10;
1936 num_ls_threads
= 10;
1937 num_ps_stack_entries
= 42;
1938 num_vs_stack_entries
= 42;
1939 num_gs_stack_entries
= 42;
1940 num_es_stack_entries
= 42;
1941 num_hs_stack_entries
= 42;
1942 num_ls_stack_entries
= 42;
1955 tmp
|= S_008C00_VC_ENABLE(1);
1958 tmp
|= S_008C00_EXPORT_SRC_C(1);
1959 tmp
|= S_008C00_CS_PRIO(cs_prio
);
1960 tmp
|= S_008C00_LS_PRIO(ls_prio
);
1961 tmp
|= S_008C00_HS_PRIO(hs_prio
);
1962 tmp
|= S_008C00_PS_PRIO(ps_prio
);
1963 tmp
|= S_008C00_VS_PRIO(vs_prio
);
1964 tmp
|= S_008C00_GS_PRIO(gs_prio
);
1965 tmp
|= S_008C00_ES_PRIO(es_prio
);
1966 r600_pipe_state_add_reg(rstate
, R_008C00_SQ_CONFIG
, tmp
, 0xFFFFFFFF, NULL
, 0);
1968 /* enable dynamic GPR resource management */
1969 if (r600_get_minor_version(rctx
->radeon
) >= 7) {
1970 /* always set temp clauses */
1971 r600_pipe_state_add_reg(rstate
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
,
1972 S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
), 0xFFFFFFFF, NULL
, 0);
1973 r600_pipe_state_add_reg(rstate
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 0, 0xFFFFFFFF, NULL
, 0);
1974 r600_pipe_state_add_reg(rstate
, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2
, 0, 0xFFFFFFFF, NULL
, 0);
1975 r600_pipe_state_add_reg(rstate
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8), 0xFFFFFFFF, NULL
, 0);
1976 r600_pipe_state_add_reg(rstate
, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
,
1977 S_028838_PS_GPRS(0x1e) |
1978 S_028838_VS_GPRS(0x1e) |
1979 S_028838_GS_GPRS(0x1e) |
1980 S_028838_ES_GPRS(0x1e) |
1981 S_028838_HS_GPRS(0x1e) |
1982 S_028838_LS_GPRS(0x1e), 0xFFFFFFFF, NULL
, 0); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
1985 tmp
|= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
1986 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
1987 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
1988 r600_pipe_state_add_reg(rstate
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
, 0);
1991 tmp
|= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
1992 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
1993 r600_pipe_state_add_reg(rstate
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
, 0);
1996 tmp
|= S_008C0C_NUM_HS_GPRS(num_hs_gprs
);
1997 tmp
|= S_008C0C_NUM_HS_GPRS(num_ls_gprs
);
1998 r600_pipe_state_add_reg(rstate
, R_008C0C_SQ_GPR_RESOURCE_MGMT_3
, tmp
, 0xFFFFFFFF, NULL
, 0);
2002 tmp
|= S_008C18_NUM_PS_THREADS(num_ps_threads
);
2003 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
2004 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
2005 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
2006 r600_pipe_state_add_reg(rstate
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
, 0);
2009 tmp
|= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
2010 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
2011 r600_pipe_state_add_reg(rstate
, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
, 0);
2014 tmp
|= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2015 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2016 r600_pipe_state_add_reg(rstate
, R_008C20_SQ_STACK_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
, 0);
2019 tmp
|= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2020 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2021 r600_pipe_state_add_reg(rstate
, R_008C24_SQ_STACK_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
, 0);
2024 tmp
|= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
2025 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
2026 r600_pipe_state_add_reg(rstate
, R_008C28_SQ_STACK_RESOURCE_MGMT_3
, tmp
, 0xFFFFFFFF, NULL
, 0);
2029 tmp
|= S_008E2C_NUM_PS_LDS(0x1000);
2030 tmp
|= S_008E2C_NUM_LS_LDS(0x1000);
2031 r600_pipe_state_add_reg(rstate
, R_008E2C_SQ_LDS_RESOURCE_MGMT
, tmp
, 0xFFFFFFFF, NULL
, 0);
2033 r600_pipe_state_add_reg(rstate
, R_009100_SPI_CONFIG_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2034 r600_pipe_state_add_reg(rstate
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL
, 0);
2037 r600_pipe_state_add_reg(rstate
, R_028350_SX_MISC
, 0x0, 0xFFFFFFFF, NULL
, 0);
2039 r600_pipe_state_add_reg(rstate
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x0, 0xFFFFFFFF, NULL
, 0);
2041 r600_pipe_state_add_reg(rstate
, R_028A48_PA_SC_MODE_CNTL_0
, 0x0, 0xFFFFFFFF, NULL
, 0);
2042 r600_pipe_state_add_reg(rstate
, R_028A4C_PA_SC_MODE_CNTL_1
, 0x0, 0xFFFFFFFF, NULL
, 0);
2044 r600_pipe_state_add_reg(rstate
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2045 r600_pipe_state_add_reg(rstate
, R_028904_SQ_GSVS_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2046 r600_pipe_state_add_reg(rstate
, R_028908_SQ_ESTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2047 r600_pipe_state_add_reg(rstate
, R_02890C_SQ_GSTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2048 r600_pipe_state_add_reg(rstate
, R_028910_SQ_VSTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2049 r600_pipe_state_add_reg(rstate
, R_028914_SQ_PSTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2051 r600_pipe_state_add_reg(rstate
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2052 r600_pipe_state_add_reg(rstate
, R_028920_SQ_GS_VERT_ITEMSIZE_1
, 0x0, 0xFFFFFFFF, NULL
, 0);
2053 r600_pipe_state_add_reg(rstate
, R_028924_SQ_GS_VERT_ITEMSIZE_2
, 0x0, 0xFFFFFFFF, NULL
, 0);
2054 r600_pipe_state_add_reg(rstate
, R_028928_SQ_GS_VERT_ITEMSIZE_3
, 0x0, 0xFFFFFFFF, NULL
, 0);
2056 r600_pipe_state_add_reg(rstate
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2057 r600_pipe_state_add_reg(rstate
, R_028A14_VGT_HOS_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2058 r600_pipe_state_add_reg(rstate
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2059 r600_pipe_state_add_reg(rstate
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2060 r600_pipe_state_add_reg(rstate
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x0, 0xFFFFFFFF, NULL
, 0);
2061 r600_pipe_state_add_reg(rstate
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2062 r600_pipe_state_add_reg(rstate
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x0, 0xFFFFFFFF, NULL
, 0);
2063 r600_pipe_state_add_reg(rstate
, R_028A2C_VGT_GROUP_DECR
, 0x0, 0xFFFFFFFF, NULL
, 0);
2064 r600_pipe_state_add_reg(rstate
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2065 r600_pipe_state_add_reg(rstate
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2066 r600_pipe_state_add_reg(rstate
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2067 r600_pipe_state_add_reg(rstate
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2068 r600_pipe_state_add_reg(rstate
, R_028A40_VGT_GS_MODE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2069 r600_pipe_state_add_reg(rstate
, R_028B94_VGT_STRMOUT_CONFIG
, 0x0, 0xFFFFFFFF, NULL
, 0);
2070 r600_pipe_state_add_reg(rstate
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0, 0xFFFFFFFF, NULL
, 0);
2071 r600_pipe_state_add_reg(rstate
, R_028AB4_VGT_REUSE_OFF
, 0x00000000, 0xFFFFFFFF, NULL
, 0);
2072 r600_pipe_state_add_reg(rstate
, R_028AB8_VGT_VTX_CNT_EN
, 0x0, 0xFFFFFFFF, NULL
, 0);
2073 r600_pipe_state_add_reg(rstate
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1, 0xFFFFFFFF, NULL
, 0);
2075 r600_pipe_state_add_reg(rstate
, R_028380_SQ_VTX_SEMANTIC_0
, 0x0, 0xFFFFFFFF, NULL
, 0);
2076 r600_pipe_state_add_reg(rstate
, R_028384_SQ_VTX_SEMANTIC_1
, 0x0, 0xFFFFFFFF, NULL
, 0);
2077 r600_pipe_state_add_reg(rstate
, R_028388_SQ_VTX_SEMANTIC_2
, 0x0, 0xFFFFFFFF, NULL
, 0);
2078 r600_pipe_state_add_reg(rstate
, R_02838C_SQ_VTX_SEMANTIC_3
, 0x0, 0xFFFFFFFF, NULL
, 0);
2079 r600_pipe_state_add_reg(rstate
, R_028390_SQ_VTX_SEMANTIC_4
, 0x0, 0xFFFFFFFF, NULL
, 0);
2080 r600_pipe_state_add_reg(rstate
, R_028394_SQ_VTX_SEMANTIC_5
, 0x0, 0xFFFFFFFF, NULL
, 0);
2081 r600_pipe_state_add_reg(rstate
, R_028398_SQ_VTX_SEMANTIC_6
, 0x0, 0xFFFFFFFF, NULL
, 0);
2082 r600_pipe_state_add_reg(rstate
, R_02839C_SQ_VTX_SEMANTIC_7
, 0x0, 0xFFFFFFFF, NULL
, 0);
2083 r600_pipe_state_add_reg(rstate
, R_0283A0_SQ_VTX_SEMANTIC_8
, 0x0, 0xFFFFFFFF, NULL
, 0);
2084 r600_pipe_state_add_reg(rstate
, R_0283A4_SQ_VTX_SEMANTIC_9
, 0x0, 0xFFFFFFFF, NULL
, 0);
2085 r600_pipe_state_add_reg(rstate
, R_0283A8_SQ_VTX_SEMANTIC_10
, 0x0, 0xFFFFFFFF, NULL
, 0);
2086 r600_pipe_state_add_reg(rstate
, R_0283AC_SQ_VTX_SEMANTIC_11
, 0x0, 0xFFFFFFFF, NULL
, 0);
2087 r600_pipe_state_add_reg(rstate
, R_0283B0_SQ_VTX_SEMANTIC_12
, 0x0, 0xFFFFFFFF, NULL
, 0);
2088 r600_pipe_state_add_reg(rstate
, R_0283B4_SQ_VTX_SEMANTIC_13
, 0x0, 0xFFFFFFFF, NULL
, 0);
2089 r600_pipe_state_add_reg(rstate
, R_0283B8_SQ_VTX_SEMANTIC_14
, 0x0, 0xFFFFFFFF, NULL
, 0);
2090 r600_pipe_state_add_reg(rstate
, R_0283BC_SQ_VTX_SEMANTIC_15
, 0x0, 0xFFFFFFFF, NULL
, 0);
2091 r600_pipe_state_add_reg(rstate
, R_0283C0_SQ_VTX_SEMANTIC_16
, 0x0, 0xFFFFFFFF, NULL
, 0);
2092 r600_pipe_state_add_reg(rstate
, R_0283C4_SQ_VTX_SEMANTIC_17
, 0x0, 0xFFFFFFFF, NULL
, 0);
2093 r600_pipe_state_add_reg(rstate
, R_0283C8_SQ_VTX_SEMANTIC_18
, 0x0, 0xFFFFFFFF, NULL
, 0);
2094 r600_pipe_state_add_reg(rstate
, R_0283CC_SQ_VTX_SEMANTIC_19
, 0x0, 0xFFFFFFFF, NULL
, 0);
2095 r600_pipe_state_add_reg(rstate
, R_0283D0_SQ_VTX_SEMANTIC_20
, 0x0, 0xFFFFFFFF, NULL
, 0);
2096 r600_pipe_state_add_reg(rstate
, R_0283D4_SQ_VTX_SEMANTIC_21
, 0x0, 0xFFFFFFFF, NULL
, 0);
2097 r600_pipe_state_add_reg(rstate
, R_0283D8_SQ_VTX_SEMANTIC_22
, 0x0, 0xFFFFFFFF, NULL
, 0);
2098 r600_pipe_state_add_reg(rstate
, R_0283DC_SQ_VTX_SEMANTIC_23
, 0x0, 0xFFFFFFFF, NULL
, 0);
2099 r600_pipe_state_add_reg(rstate
, R_0283E0_SQ_VTX_SEMANTIC_24
, 0x0, 0xFFFFFFFF, NULL
, 0);
2100 r600_pipe_state_add_reg(rstate
, R_0283E4_SQ_VTX_SEMANTIC_25
, 0x0, 0xFFFFFFFF, NULL
, 0);
2101 r600_pipe_state_add_reg(rstate
, R_0283E8_SQ_VTX_SEMANTIC_26
, 0x0, 0xFFFFFFFF, NULL
, 0);
2102 r600_pipe_state_add_reg(rstate
, R_0283EC_SQ_VTX_SEMANTIC_27
, 0x0, 0xFFFFFFFF, NULL
, 0);
2103 r600_pipe_state_add_reg(rstate
, R_0283F0_SQ_VTX_SEMANTIC_28
, 0x0, 0xFFFFFFFF, NULL
, 0);
2104 r600_pipe_state_add_reg(rstate
, R_0283F4_SQ_VTX_SEMANTIC_29
, 0x0, 0xFFFFFFFF, NULL
, 0);
2105 r600_pipe_state_add_reg(rstate
, R_0283F8_SQ_VTX_SEMANTIC_30
, 0x0, 0xFFFFFFFF, NULL
, 0);
2106 r600_pipe_state_add_reg(rstate
, R_0283FC_SQ_VTX_SEMANTIC_31
, 0x0, 0xFFFFFFFF, NULL
, 0);
2108 r600_pipe_state_add_reg(rstate
, R_028810_PA_CL_CLIP_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2110 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
2113 void evergreen_polygon_offset_update(struct r600_pipe_context
*rctx
)
2115 struct r600_pipe_state state
;
2117 state
.id
= R600_PIPE_STATE_POLYGON_OFFSET
;
2119 if (rctx
->rasterizer
&& rctx
->framebuffer
.zsbuf
) {
2120 float offset_units
= rctx
->rasterizer
->offset_units
;
2121 unsigned offset_db_fmt_cntl
= 0, depth
;
2123 switch (rctx
->framebuffer
.zsbuf
->texture
->format
) {
2124 case PIPE_FORMAT_Z24X8_UNORM
:
2125 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
2127 offset_units
*= 2.0f
;
2129 case PIPE_FORMAT_Z32_FLOAT
:
2130 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED
:
2132 offset_units
*= 1.0f
;
2133 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2135 case PIPE_FORMAT_Z16_UNORM
:
2137 offset_units
*= 4.0f
;
2142 /* FIXME some of those reg can be computed with cso */
2143 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
2144 r600_pipe_state_add_reg(&state
,
2145 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
2146 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
, 0);
2147 r600_pipe_state_add_reg(&state
,
2148 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
2149 fui(offset_units
), 0xFFFFFFFF, NULL
, 0);
2150 r600_pipe_state_add_reg(&state
,
2151 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
2152 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
, 0);
2153 r600_pipe_state_add_reg(&state
,
2154 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
2155 fui(offset_units
), 0xFFFFFFFF, NULL
, 0);
2156 r600_pipe_state_add_reg(&state
,
2157 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
2158 offset_db_fmt_cntl
, 0xFFFFFFFF, NULL
, 0);
2159 r600_context_pipe_state_set(&rctx
->ctx
, &state
);
2163 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2165 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
2166 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2167 struct r600_shader
*rshader
= &shader
->shader
;
2168 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
2169 int pos_index
= -1, face_index
= -1;
2171 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
2172 unsigned spi_baryc_cntl
;
2176 db_shader_control
= 0;
2177 for (i
= 0; i
< rshader
->ninput
; i
++) {
2178 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2179 POSITION goes via GPRs from the SC so isn't counted */
2180 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2182 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
2185 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
||
2186 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
2188 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
2190 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
2191 have_perspective
= TRUE
;
2192 if (rshader
->input
[i
].centroid
)
2193 have_centroid
= TRUE
;
2196 for (i
= 0; i
< rshader
->noutput
; i
++) {
2197 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2198 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(1);
2199 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2200 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(1);
2202 if (rshader
->uses_kill
)
2203 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2207 for (i
= 0; i
< rshader
->noutput
; i
++) {
2208 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2209 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2211 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
2212 if (rshader
->fs_write_all
)
2213 num_cout
= rshader
->nr_cbufs
;
2218 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
2220 /* always at least export 1 component per pixel */
2226 have_perspective
= TRUE
;
2229 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
2230 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
2231 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
2233 if (pos_index
!= -1) {
2234 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
2235 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
2236 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
2240 spi_ps_in_control_1
= 0;
2241 if (face_index
!= -1) {
2242 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2243 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2247 if (have_perspective
)
2248 spi_baryc_cntl
|= S_0286E0_PERSP_CENTER_ENA(1) |
2249 S_0286E0_PERSP_CENTROID_ENA(have_centroid
);
2251 spi_baryc_cntl
|= S_0286E0_LINEAR_CENTER_ENA(1) |
2252 S_0286E0_LINEAR_CENTROID_ENA(have_centroid
);
2254 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
,
2255 spi_ps_in_control_0
, 0xFFFFFFFF, NULL
, 0);
2256 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
,
2257 spi_ps_in_control_1
, 0xFFFFFFFF, NULL
, 0);
2258 r600_pipe_state_add_reg(rstate
, R_0286E4_SPI_PS_IN_CONTROL_2
,
2259 0, 0xFFFFFFFF, NULL
, 0);
2260 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
, 0xFFFFFFFF, NULL
, 0);
2261 r600_pipe_state_add_reg(rstate
,
2262 R_0286E0_SPI_BARYC_CNTL
,
2264 0xFFFFFFFF, NULL
, 0);
2266 r600_pipe_state_add_reg(rstate
,
2267 R_028840_SQ_PGM_START_PS
,
2268 0, 0xFFFFFFFF, shader
->bo
, RADEON_USAGE_READ
);
2269 r600_pipe_state_add_reg(rstate
,
2270 R_028844_SQ_PGM_RESOURCES_PS
,
2271 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
2272 S_028844_PRIME_CACHE_ON_DRAW(1) |
2273 S_028844_STACK_SIZE(rshader
->bc
.nstack
),
2274 0xFFFFFFFF, NULL
, 0);
2275 r600_pipe_state_add_reg(rstate
,
2276 R_028848_SQ_PGM_RESOURCES_2_PS
,
2277 0x0, 0xFFFFFFFF, NULL
, 0);
2278 r600_pipe_state_add_reg(rstate
,
2279 R_02884C_SQ_PGM_EXPORTS_PS
,
2280 exports_ps
, 0xFFFFFFFF, NULL
, 0);
2281 /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */
2282 /* only set some bits here, the other bits are set in the dsa state */
2283 r600_pipe_state_add_reg(rstate
,
2284 R_02880C_DB_SHADER_CONTROL
,
2286 S_02880C_Z_EXPORT_ENABLE(1) |
2287 S_02880C_STENCIL_EXPORT_ENABLE(1) |
2288 S_02880C_KILL_ENABLE(1),
2290 r600_pipe_state_add_reg(rstate
,
2291 R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF,
2292 0xFFFFFFFF, NULL
, 0);
2295 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2297 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
2298 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2299 struct r600_shader
*rshader
= &shader
->shader
;
2300 unsigned spi_vs_out_id
[10];
2301 unsigned i
, tmp
, nparams
;
2303 /* clear previous register */
2306 /* so far never got proper semantic id from tgsi */
2307 for (i
= 0; i
< 10; i
++) {
2308 spi_vs_out_id
[i
] = 0;
2310 for (i
= 0; i
< 32; i
++) {
2311 tmp
= i
<< ((i
& 3) * 8);
2312 spi_vs_out_id
[i
/ 4] |= tmp
;
2314 for (i
= 0; i
< 10; i
++) {
2315 r600_pipe_state_add_reg(rstate
,
2316 R_02861C_SPI_VS_OUT_ID_0
+ i
* 4,
2317 spi_vs_out_id
[i
], 0xFFFFFFFF, NULL
, 0);
2320 /* Certain attributes (position, psize, etc.) don't count as params.
2321 * VS is required to export at least one param and r600_shader_from_tgsi()
2322 * takes care of adding a dummy export.
2324 nparams
= rshader
->noutput
- rshader
->npos
;
2328 r600_pipe_state_add_reg(rstate
,
2329 R_0286C4_SPI_VS_OUT_CONFIG
,
2330 S_0286C4_VS_EXPORT_COUNT(nparams
- 1),
2331 0xFFFFFFFF, NULL
, 0);
2332 r600_pipe_state_add_reg(rstate
,
2333 R_028860_SQ_PGM_RESOURCES_VS
,
2334 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
2335 S_028860_STACK_SIZE(rshader
->bc
.nstack
),
2336 0xFFFFFFFF, NULL
, 0);
2337 r600_pipe_state_add_reg(rstate
,
2338 R_028864_SQ_PGM_RESOURCES_2_VS
,
2339 0x0, 0xFFFFFFFF, NULL
, 0);
2340 r600_pipe_state_add_reg(rstate
,
2341 R_02885C_SQ_PGM_START_VS
,
2342 0, 0xFFFFFFFF, shader
->bo
, RADEON_USAGE_READ
);
2344 r600_pipe_state_add_reg(rstate
,
2345 R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF,
2346 0xFFFFFFFF, NULL
, 0);
2349 void evergreen_fetch_shader(struct pipe_context
*ctx
,
2350 struct r600_vertex_element
*ve
)
2352 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
2353 struct r600_pipe_state
*rstate
= &ve
->rstate
;
2354 rstate
->id
= R600_PIPE_STATE_FETCH_SHADER
;
2356 r600_pipe_state_add_reg(rstate
, R_0288A8_SQ_PGM_RESOURCES_FS
,
2357 0x00000000, 0xFFFFFFFF, NULL
, 0);
2358 r600_pipe_state_add_reg(rstate
, R_0288A4_SQ_PGM_START_FS
,
2360 0xFFFFFFFF, ve
->fetch_shader
, RADEON_USAGE_READ
);
2363 void *evergreen_create_db_flush_dsa(struct r600_pipe_context
*rctx
)
2365 struct pipe_depth_stencil_alpha_state dsa
;
2366 struct r600_pipe_state
*rstate
;
2368 memset(&dsa
, 0, sizeof(dsa
));
2370 rstate
= rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
2371 r600_pipe_state_add_reg(rstate
,
2372 R_02880C_DB_SHADER_CONTROL
,
2374 S_02880C_DUAL_EXPORT_ENABLE(1), NULL
, 0);
2375 r600_pipe_state_add_reg(rstate
,
2376 R_028000_DB_RENDER_CONTROL
,
2377 S_028000_DEPTH_COPY_ENABLE(1) |
2378 S_028000_STENCIL_COPY_ENABLE(1) |
2379 S_028000_COPY_CENTROID(1),
2380 S_028000_DEPTH_COPY_ENABLE(1) |
2381 S_028000_STENCIL_COPY_ENABLE(1) |
2382 S_028000_COPY_CENTROID(1), NULL
, 0);
2386 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context
*rctx
,
2387 struct r600_pipe_resource_state
*rstate
)
2389 rstate
->id
= R600_PIPE_STATE_RESOURCE
;
2392 rstate
->bo
[0] = NULL
;
2394 rstate
->val
[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2395 rstate
->val
[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
2396 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
2397 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
2398 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
);
2402 rstate
->val
[7] = 0xc0000000;
2406 void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state
*rstate
,
2407 struct r600_resource
*rbuffer
,
2408 unsigned offset
, unsigned stride
,
2409 enum radeon_bo_usage usage
)
2411 rstate
->bo
[0] = rbuffer
->bo
;
2412 rstate
->bo_usage
[0] = usage
;
2413 rstate
->val
[0] = offset
;
2414 rstate
->val
[1] = rbuffer
->bo_size
- offset
- 1;
2415 rstate
->val
[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2416 S_030008_STRIDE(stride
);