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r600g: indentation fix
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "eg_state_inlines.h"
50
51 static void evergreen_set_blend_color(struct pipe_context *ctx,
52 const struct pipe_blend_color *state)
53 {
54 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
55 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
56
57 if (rstate == NULL)
58 return;
59
60 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
61 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
62 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
63 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
65
66 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
67 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
68 r600_context_pipe_state_set(&rctx->ctx, rstate);
69 }
70
71 static void *evergreen_create_blend_state(struct pipe_context *ctx,
72 const struct pipe_blend_state *state)
73 {
74 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
75 struct r600_pipe_state *rstate;
76 u32 color_control, target_mask;
77 /* FIXME there is more then 8 framebuffer */
78 unsigned blend_cntl[8];
79
80 if (blend == NULL) {
81 return NULL;
82 }
83 rstate = &blend->rstate;
84
85 rstate->id = R600_PIPE_STATE_BLEND;
86
87 target_mask = 0;
88 color_control = S_028808_MODE(1);
89 if (state->logicop_enable) {
90 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
91 } else {
92 color_control |= (0xcc << 16);
93 }
94 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
95 if (state->independent_blend_enable) {
96 for (int i = 0; i < 8; i++) {
97 target_mask |= (state->rt[i].colormask << (4 * i));
98 }
99 } else {
100 for (int i = 0; i < 8; i++) {
101 target_mask |= (state->rt[0].colormask << (4 * i));
102 }
103 }
104 blend->cb_target_mask = target_mask;
105 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
106 color_control, 0xFFFFFFFF, NULL);
107 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
108
109 for (int i = 0; i < 8; i++) {
110 unsigned eqRGB = state->rt[i].rgb_func;
111 unsigned srcRGB = state->rt[i].rgb_src_factor;
112 unsigned dstRGB = state->rt[i].rgb_dst_factor;
113 unsigned eqA = state->rt[i].alpha_func;
114 unsigned srcA = state->rt[i].alpha_src_factor;
115 unsigned dstA = state->rt[i].alpha_dst_factor;
116
117 blend_cntl[i] = 0;
118 if (!state->rt[i].blend_enable)
119 continue;
120
121 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
122 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
123 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
124 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
125
126 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
127 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
128 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
129 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
130 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
131 }
132 }
133 for (int i = 0; i < 8; i++) {
134 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
135 }
136
137 return rstate;
138 }
139
140 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
141 const struct pipe_depth_stencil_alpha_state *state)
142 {
143 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
144 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
145 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
146
147 if (rstate == NULL) {
148 return NULL;
149 }
150
151 rstate->id = R600_PIPE_STATE_DSA;
152 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
153 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
154 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
155 * be set if shader use texkill instruction
156 */
157 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
158 stencil_ref_mask = 0;
159 stencil_ref_mask_bf = 0;
160 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
161 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
162 S_028800_ZFUNC(state->depth.func);
163
164 /* stencil */
165 if (state->stencil[0].enabled) {
166 db_depth_control |= S_028800_STENCIL_ENABLE(1);
167 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
168 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
169 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
170 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
171
172
173 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
174 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
175 if (state->stencil[1].enabled) {
176 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
177 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
178 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
179 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
180 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
181 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
182 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
183 }
184 }
185
186 /* alpha */
187 alpha_test_control = 0;
188 alpha_ref = 0;
189 if (state->alpha.enabled) {
190 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
191 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
192 alpha_ref = fui(state->alpha.ref_value);
193 }
194
195 /* misc */
196 db_render_control = 0;
197 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
198 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
199 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
200 /* TODO db_render_override depends on query */
201 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
202 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
203 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
204 r600_pipe_state_add_reg(rstate,
205 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
206 0xFFFFFFFF & C_028430_STENCILREF, NULL);
207 r600_pipe_state_add_reg(rstate,
208 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
209 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
210 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
211 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
212 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
213 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
214 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
215 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
216 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
217 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
218 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
219 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
220
221 return rstate;
222 }
223
224 static void *evergreen_create_rs_state(struct pipe_context *ctx,
225 const struct pipe_rasterizer_state *state)
226 {
227 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
228 struct r600_pipe_state *rstate;
229 unsigned tmp;
230 unsigned prov_vtx = 1, polygon_dual_mode;
231 unsigned clip_rule;
232
233 if (rs == NULL) {
234 return NULL;
235 }
236
237 rstate = &rs->rstate;
238 rs->flatshade = state->flatshade;
239 rs->sprite_coord_enable = state->sprite_coord_enable;
240
241 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
242
243 /* offset */
244 rs->offset_units = state->offset_units;
245 rs->offset_scale = state->offset_scale * 12.0f;
246
247 rstate->id = R600_PIPE_STATE_RASTERIZER;
248 if (state->flatshade_first)
249 prov_vtx = 0;
250 tmp = S_0286D4_FLAT_SHADE_ENA(1);
251 if (state->sprite_coord_enable) {
252 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
253 S_0286D4_PNT_SPRITE_OVRD_X(2) |
254 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
255 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
256 S_0286D4_PNT_SPRITE_OVRD_W(1);
257 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
258 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
259 }
260 }
261 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
262
263 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
264 state->fill_back != PIPE_POLYGON_MODE_FILL);
265 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
266 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
267 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
268 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
269 S_028814_FACE(!state->front_ccw) |
270 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
271 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
272 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
273 S_028814_POLY_MODE(polygon_dual_mode) |
274 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
275 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
276 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
277 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
278 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
279 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
280 /* point size 12.4 fixed point */
281 tmp = (unsigned)(state->point_size * 8.0);
282 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
283 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
284
285 tmp = (unsigned)state->line_width * 8;
286 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
287
288 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
289 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
290 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
291 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
292 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
293 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
294
295 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
296 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
297 0xFFFFFFFF, NULL);
298
299 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
300 return rstate;
301 }
302
303 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
304 const struct pipe_sampler_state *state)
305 {
306 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
307 union util_color uc;
308
309 if (rstate == NULL) {
310 return NULL;
311 }
312
313 rstate->id = R600_PIPE_STATE_SAMPLER;
314 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
315 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
316 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
317 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
318 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
319 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
320 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
321 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
322 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
323 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
324 /* FIXME LOD it depends on texture base level ... */
325 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
326 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
327 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
328 0xFFFFFFFF, NULL);
329 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
330 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
331 S_03C008_TYPE(1),
332 0xFFFFFFFF, NULL);
333
334 if (uc.ui) {
335 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
336 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
337 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
338 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
339 }
340 return rstate;
341 }
342
343 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
344 struct pipe_resource *texture,
345 const struct pipe_sampler_view *state)
346 {
347 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
348 struct r600_pipe_state *rstate;
349 const struct util_format_description *desc;
350 struct r600_resource_texture *tmp;
351 struct r600_resource *rbuffer;
352 unsigned format;
353 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
354 unsigned char swizzle[4];
355 struct r600_bo *bo[2];
356
357 if (resource == NULL)
358 return NULL;
359 rstate = &resource->state;
360
361 /* initialize base object */
362 resource->base = *state;
363 resource->base.texture = NULL;
364 pipe_reference(NULL, &texture->reference);
365 resource->base.texture = texture;
366 resource->base.reference.count = 1;
367 resource->base.context = ctx;
368
369 swizzle[0] = state->swizzle_r;
370 swizzle[1] = state->swizzle_g;
371 swizzle[2] = state->swizzle_b;
372 swizzle[3] = state->swizzle_a;
373 format = r600_translate_texformat(state->format,
374 swizzle,
375 &word4, &yuv_format);
376 if (format == ~0) {
377 format = 0;
378 }
379 desc = util_format_description(state->format);
380 if (desc == NULL) {
381 R600_ERR("unknow format %d\n", state->format);
382 }
383 tmp = (struct r600_resource_texture*)texture;
384 rbuffer = &tmp->resource;
385 bo[0] = rbuffer->bo;
386 bo[1] = rbuffer->bo;
387 /* FIXME depth texture decompression */
388 if (tmp->depth) {
389 r600_texture_depth_flush(ctx, texture);
390 tmp = (struct r600_resource_texture*)texture;
391 rbuffer = &tmp->flushed_depth_texture->resource;
392 bo[0] = rbuffer->bo;
393 bo[1] = rbuffer->bo;
394 }
395 pitch = align(tmp->pitch_in_pixels[0], 8);
396
397 /* FIXME properly handle first level != 0 */
398 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
399 S_030000_DIM(r600_tex_dim(texture->target)) |
400 S_030000_PITCH((pitch / 8) - 1) |
401 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
402 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
403 S_030004_TEX_HEIGHT(texture->height0 - 1) |
404 S_030004_TEX_DEPTH(texture->depth0 - 1),
405 0xFFFFFFFF, NULL);
406 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
407 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
408 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
409 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
410 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
411 word4 | S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
412 S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
413 S_030010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
414 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
415 S_030014_LAST_LEVEL(state->u.tex.last_level) |
416 S_030014_BASE_ARRAY(0) |
417 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
418 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
419 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
420 S_03001C_DATA_FORMAT(format) |
421 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
422
423 return &resource->base;
424 }
425
426 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
427 struct pipe_sampler_view **views)
428 {
429 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
430 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
431
432 for (int i = 0; i < count; i++) {
433 if (resource[i]) {
434 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i);
435 }
436 }
437 }
438
439 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
440 struct pipe_sampler_view **views)
441 {
442 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
443 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
444 int i;
445
446 for (i = 0; i < count; i++) {
447 if (&rctx->ps_samplers.views[i]->base != views[i]) {
448 if (resource[i])
449 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
450 else
451 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
452
453 pipe_sampler_view_reference(
454 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
455 views[i]);
456 }
457 }
458 for (i = count; i < NUM_TEX_UNITS; i++) {
459 if (rctx->ps_samplers.views[i]) {
460 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
461 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
462 }
463 }
464 rctx->ps_samplers.n_views = count;
465 }
466
467 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
468 {
469 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
470 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
471
472
473 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
474 rctx->ps_samplers.n_samplers = count;
475
476 for (int i = 0; i < count; i++) {
477 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
478 }
479 }
480
481 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
482 {
483 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
484 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
485
486 for (int i = 0; i < count; i++) {
487 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
488 }
489 }
490
491 static void evergreen_set_clip_state(struct pipe_context *ctx,
492 const struct pipe_clip_state *state)
493 {
494 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
495 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
496
497 if (rstate == NULL)
498 return;
499
500 rctx->clip = *state;
501 rstate->id = R600_PIPE_STATE_CLIP;
502 for (int i = 0; i < state->nr; i++) {
503 r600_pipe_state_add_reg(rstate,
504 R_0285BC_PA_CL_UCP0_X + i * 16,
505 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
506 r600_pipe_state_add_reg(rstate,
507 R_0285C0_PA_CL_UCP0_Y + i * 16,
508 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
509 r600_pipe_state_add_reg(rstate,
510 R_0285C4_PA_CL_UCP0_Z + i * 16,
511 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
512 r600_pipe_state_add_reg(rstate,
513 R_0285C8_PA_CL_UCP0_W + i * 16,
514 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
515 }
516 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
517 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
518 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
519 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
520
521 free(rctx->states[R600_PIPE_STATE_CLIP]);
522 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
523 r600_context_pipe_state_set(&rctx->ctx, rstate);
524 }
525
526 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
527 const struct pipe_poly_stipple *state)
528 {
529 }
530
531 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
532 {
533 }
534
535 static void evergreen_set_scissor_state(struct pipe_context *ctx,
536 const struct pipe_scissor_state *state)
537 {
538 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
539 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
540 u32 tl, br;
541
542 if (rstate == NULL)
543 return;
544
545 rstate->id = R600_PIPE_STATE_SCISSOR;
546 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
547 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
548 r600_pipe_state_add_reg(rstate,
549 R_028210_PA_SC_CLIPRECT_0_TL, tl,
550 0xFFFFFFFF, NULL);
551 r600_pipe_state_add_reg(rstate,
552 R_028214_PA_SC_CLIPRECT_0_BR, br,
553 0xFFFFFFFF, NULL);
554 r600_pipe_state_add_reg(rstate,
555 R_028218_PA_SC_CLIPRECT_1_TL, tl,
556 0xFFFFFFFF, NULL);
557 r600_pipe_state_add_reg(rstate,
558 R_02821C_PA_SC_CLIPRECT_1_BR, br,
559 0xFFFFFFFF, NULL);
560 r600_pipe_state_add_reg(rstate,
561 R_028220_PA_SC_CLIPRECT_2_TL, tl,
562 0xFFFFFFFF, NULL);
563 r600_pipe_state_add_reg(rstate,
564 R_028224_PA_SC_CLIPRECT_2_BR, br,
565 0xFFFFFFFF, NULL);
566 r600_pipe_state_add_reg(rstate,
567 R_028228_PA_SC_CLIPRECT_3_TL, tl,
568 0xFFFFFFFF, NULL);
569 r600_pipe_state_add_reg(rstate,
570 R_02822C_PA_SC_CLIPRECT_3_BR, br,
571 0xFFFFFFFF, NULL);
572
573 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
574 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
575 r600_context_pipe_state_set(&rctx->ctx, rstate);
576 }
577
578 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
579 const struct pipe_stencil_ref *state)
580 {
581 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
582 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
583 u32 tmp;
584
585 if (rstate == NULL)
586 return;
587
588 rctx->stencil_ref = *state;
589 rstate->id = R600_PIPE_STATE_STENCIL_REF;
590 tmp = S_028430_STENCILREF(state->ref_value[0]);
591 r600_pipe_state_add_reg(rstate,
592 R_028430_DB_STENCILREFMASK, tmp,
593 ~C_028430_STENCILREF, NULL);
594 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
595 r600_pipe_state_add_reg(rstate,
596 R_028434_DB_STENCILREFMASK_BF, tmp,
597 ~C_028434_STENCILREF_BF, NULL);
598
599 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
600 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
601 r600_context_pipe_state_set(&rctx->ctx, rstate);
602 }
603
604 static void evergreen_set_viewport_state(struct pipe_context *ctx,
605 const struct pipe_viewport_state *state)
606 {
607 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
608 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
609
610 if (rstate == NULL)
611 return;
612
613 rctx->viewport = *state;
614 rstate->id = R600_PIPE_STATE_VIEWPORT;
615 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
616 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
617 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
618 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
619 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
620 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
621 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
622 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
623 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
624
625 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
626 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
627 r600_context_pipe_state_set(&rctx->ctx, rstate);
628 }
629
630 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
631 const struct pipe_framebuffer_state *state, int cb)
632 {
633 struct r600_resource_texture *rtex;
634 struct r600_resource *rbuffer;
635 struct r600_surface *surf;
636 unsigned level = state->cbufs[cb]->u.tex.level;
637 unsigned pitch, slice;
638 unsigned color_info;
639 unsigned format, swap, ntype;
640 unsigned offset;
641 const struct util_format_description *desc;
642 struct r600_bo *bo[3];
643
644 surf = (struct r600_surface *)state->cbufs[cb];
645 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
646 rbuffer = &rtex->resource;
647 bo[0] = rbuffer->bo;
648 bo[1] = rbuffer->bo;
649 bo[2] = rbuffer->bo;
650
651 /* XXX quite sure for dx10+ hw don't need any offset hacks */
652 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
653 level, state->cbufs[cb]->u.tex.first_layer);
654 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
655 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
656 ntype = 0;
657 desc = util_format_description(rtex->resource.base.b.format);
658 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
659 ntype = V_028C70_NUMBER_SRGB;
660
661 format = r600_translate_colorformat(rtex->resource.base.b.format);
662 swap = r600_translate_colorswap(rtex->resource.base.b.format);
663 color_info = S_028C70_FORMAT(format) |
664 S_028C70_COMP_SWAP(swap) |
665 S_028C70_BLEND_CLAMP(1) |
666 S_028C70_NUMBER_TYPE(ntype);
667 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
668 color_info |= S_028C70_SOURCE_FORMAT(1);
669
670 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
671 r600_pipe_state_add_reg(rstate,
672 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
673 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
674 r600_pipe_state_add_reg(rstate,
675 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
676 0x0, 0xFFFFFFFF, NULL);
677 r600_pipe_state_add_reg(rstate,
678 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
679 color_info, 0xFFFFFFFF, bo[0]);
680 r600_pipe_state_add_reg(rstate,
681 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
682 S_028C64_PITCH_TILE_MAX(pitch),
683 0xFFFFFFFF, NULL);
684 r600_pipe_state_add_reg(rstate,
685 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
686 S_028C68_SLICE_TILE_MAX(slice),
687 0xFFFFFFFF, NULL);
688 r600_pipe_state_add_reg(rstate,
689 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
690 0x00000000, 0xFFFFFFFF, NULL);
691 r600_pipe_state_add_reg(rstate,
692 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
693 S_028C74_NON_DISP_TILING_ORDER(1),
694 0xFFFFFFFF, bo[0]);
695 }
696
697 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
698 const struct pipe_framebuffer_state *state)
699 {
700 struct r600_resource_texture *rtex;
701 struct r600_resource *rbuffer;
702 struct r600_surface *surf;
703 unsigned level;
704 unsigned pitch, slice, format, stencil_format;
705 unsigned offset;
706
707 if (state->zsbuf == NULL)
708 return;
709
710 level = state->zsbuf->u.tex.level;
711
712 surf = (struct r600_surface *)state->zsbuf;
713 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
714 rtex->tiled = 1;
715 rtex->array_mode[level] = 2;
716 rtex->tile_type = 1;
717 rtex->depth = 1;
718 rbuffer = &rtex->resource;
719
720 /* XXX quite sure for dx10+ hw don't need any offset hacks */
721 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
722 level, state->zsbuf->u.tex.first_layer);
723 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
724 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
725 format = r600_translate_dbformat(state->zsbuf->texture->format);
726 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
727
728 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
729 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
730 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
731 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
732
733 if (stencil_format) {
734 uint32_t stencil_offset;
735
736 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
737 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
738 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
739 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
740 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
741 }
742
743 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
744 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
745 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
746
747 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
748 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
749 0xFFFFFFFF, rbuffer->bo);
750 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
751 S_028058_PITCH_TILE_MAX(pitch),
752 0xFFFFFFFF, NULL);
753 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
754 S_02805C_SLICE_TILE_MAX(slice),
755 0xFFFFFFFF, NULL);
756 }
757
758 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
759 const struct pipe_framebuffer_state *state)
760 {
761 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
762 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
763 u32 shader_mask, tl, br, target_mask;
764
765 if (rstate == NULL)
766 return;
767
768 /* unreference old buffer and reference new one */
769 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
770
771 util_copy_framebuffer_state(&rctx->framebuffer, state);
772
773 rctx->pframebuffer = &rctx->framebuffer;
774
775 /* build states */
776 for (int i = 0; i < state->nr_cbufs; i++) {
777 evergreen_cb(rctx, rstate, state, i);
778 }
779 if (state->zsbuf) {
780 evergreen_db(rctx, rstate, state);
781 }
782
783 target_mask = 0x00000000;
784 target_mask = 0xFFFFFFFF;
785 shader_mask = 0;
786 for (int i = 0; i < state->nr_cbufs; i++) {
787 target_mask ^= 0xf << (i * 4);
788 shader_mask |= 0xf << (i * 4);
789 }
790 tl = S_028240_TL_X(0) | S_028240_TL_Y(0);
791 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
792
793 r600_pipe_state_add_reg(rstate,
794 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
795 0xFFFFFFFF, NULL);
796 r600_pipe_state_add_reg(rstate,
797 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
798 0xFFFFFFFF, NULL);
799 r600_pipe_state_add_reg(rstate,
800 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
801 0xFFFFFFFF, NULL);
802 r600_pipe_state_add_reg(rstate,
803 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
804 0xFFFFFFFF, NULL);
805 r600_pipe_state_add_reg(rstate,
806 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
807 0xFFFFFFFF, NULL);
808 r600_pipe_state_add_reg(rstate,
809 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
810 0xFFFFFFFF, NULL);
811 r600_pipe_state_add_reg(rstate,
812 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
813 0xFFFFFFFF, NULL);
814 r600_pipe_state_add_reg(rstate,
815 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
816 0xFFFFFFFF, NULL);
817 r600_pipe_state_add_reg(rstate,
818 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
819 0xFFFFFFFF, NULL);
820 r600_pipe_state_add_reg(rstate,
821 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
822 0xFFFFFFFF, NULL);
823
824 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
825 0x00000000, target_mask, NULL);
826 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
827 shader_mask, 0xFFFFFFFF, NULL);
828 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
829 0x00000000, 0xFFFFFFFF, NULL);
830 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
831 0x00000000, 0xFFFFFFFF, NULL);
832
833 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
834 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
835 r600_context_pipe_state_set(&rctx->ctx, rstate);
836
837 if (state->zsbuf) {
838 evergreen_polygon_offset_update(rctx);
839 }
840 }
841
842 static void evergreen_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
843 struct pipe_resource *buffer)
844 {
845 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
846 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
847
848 /* Note that the state tracker can unbind constant buffers by
849 * passing NULL here.
850 */
851 if (buffer == NULL) {
852 return;
853 }
854
855 switch (shader) {
856 case PIPE_SHADER_VERTEX:
857 rctx->vs_const_buffer.nregs = 0;
858 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
859 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
860 ALIGN_DIVUP(buffer->width0 >> 4, 16),
861 0xFFFFFFFF, NULL);
862 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
863 R_028980_ALU_CONST_CACHE_VS_0,
864 (r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
865 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
866 break;
867 case PIPE_SHADER_FRAGMENT:
868 rctx->ps_const_buffer.nregs = 0;
869 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
870 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
871 ALIGN_DIVUP(buffer->width0 >> 4, 16),
872 0xFFFFFFFF, NULL);
873 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
874 R_028940_ALU_CONST_CACHE_PS_0,
875 (r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
876 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
877 break;
878 default:
879 R600_ERR("unsupported %d\n", shader);
880 return;
881 }
882 }
883
884 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
885 {
886 rctx->context.create_blend_state = evergreen_create_blend_state;
887 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
888 rctx->context.create_fs_state = r600_create_shader_state;
889 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
890 rctx->context.create_sampler_state = evergreen_create_sampler_state;
891 rctx->context.create_sampler_view = evergreen_create_sampler_view;
892 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
893 rctx->context.create_vs_state = r600_create_shader_state;
894 rctx->context.bind_blend_state = r600_bind_blend_state;
895 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
896 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
897 rctx->context.bind_fs_state = r600_bind_ps_shader;
898 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
899 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
900 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
901 rctx->context.bind_vs_state = r600_bind_vs_shader;
902 rctx->context.delete_blend_state = r600_delete_state;
903 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
904 rctx->context.delete_fs_state = r600_delete_ps_shader;
905 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
906 rctx->context.delete_sampler_state = r600_delete_state;
907 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
908 rctx->context.delete_vs_state = r600_delete_vs_shader;
909 rctx->context.set_blend_color = evergreen_set_blend_color;
910 rctx->context.set_clip_state = evergreen_set_clip_state;
911 rctx->context.set_constant_buffer = evergreen_set_constant_buffer;
912 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
913 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
914 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
915 rctx->context.set_sample_mask = evergreen_set_sample_mask;
916 rctx->context.set_scissor_state = evergreen_set_scissor_state;
917 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
918 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
919 rctx->context.set_index_buffer = r600_set_index_buffer;
920 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
921 rctx->context.set_viewport_state = evergreen_set_viewport_state;
922 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
923 }
924
925 void evergreen_init_config(struct r600_pipe_context *rctx)
926 {
927 struct r600_pipe_state *rstate = &rctx->config;
928 int ps_prio;
929 int vs_prio;
930 int gs_prio;
931 int es_prio;
932 int hs_prio, cs_prio, ls_prio;
933 int num_ps_gprs;
934 int num_vs_gprs;
935 int num_gs_gprs;
936 int num_es_gprs;
937 int num_hs_gprs;
938 int num_ls_gprs;
939 int num_temp_gprs;
940 int num_ps_threads;
941 int num_vs_threads;
942 int num_gs_threads;
943 int num_es_threads;
944 int num_hs_threads;
945 int num_ls_threads;
946 int num_ps_stack_entries;
947 int num_vs_stack_entries;
948 int num_gs_stack_entries;
949 int num_es_stack_entries;
950 int num_hs_stack_entries;
951 int num_ls_stack_entries;
952 enum radeon_family family;
953 unsigned tmp;
954
955 family = r600_get_family(rctx->radeon);
956 ps_prio = 0;
957 vs_prio = 1;
958 gs_prio = 2;
959 es_prio = 3;
960 hs_prio = 0;
961 ls_prio = 0;
962 cs_prio = 0;
963
964 switch (family) {
965 case CHIP_CEDAR:
966 default:
967 num_ps_gprs = 93;
968 num_vs_gprs = 46;
969 num_temp_gprs = 4;
970 num_gs_gprs = 31;
971 num_es_gprs = 31;
972 num_hs_gprs = 23;
973 num_ls_gprs = 23;
974 num_ps_threads = 96;
975 num_vs_threads = 16;
976 num_gs_threads = 16;
977 num_es_threads = 16;
978 num_hs_threads = 16;
979 num_ls_threads = 16;
980 num_ps_stack_entries = 42;
981 num_vs_stack_entries = 42;
982 num_gs_stack_entries = 42;
983 num_es_stack_entries = 42;
984 num_hs_stack_entries = 42;
985 num_ls_stack_entries = 42;
986 break;
987 case CHIP_REDWOOD:
988 num_ps_gprs = 93;
989 num_vs_gprs = 46;
990 num_temp_gprs = 4;
991 num_gs_gprs = 31;
992 num_es_gprs = 31;
993 num_hs_gprs = 23;
994 num_ls_gprs = 23;
995 num_ps_threads = 128;
996 num_vs_threads = 20;
997 num_gs_threads = 20;
998 num_es_threads = 20;
999 num_hs_threads = 20;
1000 num_ls_threads = 20;
1001 num_ps_stack_entries = 42;
1002 num_vs_stack_entries = 42;
1003 num_gs_stack_entries = 42;
1004 num_es_stack_entries = 42;
1005 num_hs_stack_entries = 42;
1006 num_ls_stack_entries = 42;
1007 break;
1008 case CHIP_JUNIPER:
1009 num_ps_gprs = 93;
1010 num_vs_gprs = 46;
1011 num_temp_gprs = 4;
1012 num_gs_gprs = 31;
1013 num_es_gprs = 31;
1014 num_hs_gprs = 23;
1015 num_ls_gprs = 23;
1016 num_ps_threads = 128;
1017 num_vs_threads = 20;
1018 num_gs_threads = 20;
1019 num_es_threads = 20;
1020 num_hs_threads = 20;
1021 num_ls_threads = 20;
1022 num_ps_stack_entries = 85;
1023 num_vs_stack_entries = 85;
1024 num_gs_stack_entries = 85;
1025 num_es_stack_entries = 85;
1026 num_hs_stack_entries = 85;
1027 num_ls_stack_entries = 85;
1028 break;
1029 case CHIP_CYPRESS:
1030 case CHIP_HEMLOCK:
1031 num_ps_gprs = 93;
1032 num_vs_gprs = 46;
1033 num_temp_gprs = 4;
1034 num_gs_gprs = 31;
1035 num_es_gprs = 31;
1036 num_hs_gprs = 23;
1037 num_ls_gprs = 23;
1038 num_ps_threads = 128;
1039 num_vs_threads = 20;
1040 num_gs_threads = 20;
1041 num_es_threads = 20;
1042 num_hs_threads = 20;
1043 num_ls_threads = 20;
1044 num_ps_stack_entries = 85;
1045 num_vs_stack_entries = 85;
1046 num_gs_stack_entries = 85;
1047 num_es_stack_entries = 85;
1048 num_hs_stack_entries = 85;
1049 num_ls_stack_entries = 85;
1050 break;
1051 case CHIP_PALM:
1052 num_ps_gprs = 93;
1053 num_vs_gprs = 46;
1054 num_temp_gprs = 4;
1055 num_gs_gprs = 31;
1056 num_es_gprs = 31;
1057 num_hs_gprs = 23;
1058 num_ls_gprs = 23;
1059 num_ps_threads = 96;
1060 num_vs_threads = 16;
1061 num_gs_threads = 16;
1062 num_es_threads = 16;
1063 num_hs_threads = 16;
1064 num_ls_threads = 16;
1065 num_ps_stack_entries = 42;
1066 num_vs_stack_entries = 42;
1067 num_gs_stack_entries = 42;
1068 num_es_stack_entries = 42;
1069 num_hs_stack_entries = 42;
1070 num_ls_stack_entries = 42;
1071 break;
1072 }
1073
1074 tmp = 0x00000000;
1075 switch (family) {
1076 case CHIP_CEDAR:
1077 case CHIP_PALM:
1078 break;
1079 default:
1080 tmp |= S_008C00_VC_ENABLE(1);
1081 break;
1082 }
1083 tmp |= S_008C00_EXPORT_SRC_C(1);
1084 tmp |= S_008C00_CS_PRIO(cs_prio);
1085 tmp |= S_008C00_LS_PRIO(ls_prio);
1086 tmp |= S_008C00_HS_PRIO(hs_prio);
1087 tmp |= S_008C00_PS_PRIO(ps_prio);
1088 tmp |= S_008C00_VS_PRIO(vs_prio);
1089 tmp |= S_008C00_GS_PRIO(gs_prio);
1090 tmp |= S_008C00_ES_PRIO(es_prio);
1091 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1092
1093 tmp = 0;
1094 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1095 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1096 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1097 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1098
1099 tmp = 0;
1100 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1101 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1102 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1103
1104 tmp = 0;
1105 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1106 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1107 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1108
1109 tmp = 0;
1110 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1111 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1112 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1113 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1114 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1115
1116 tmp = 0;
1117 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1118 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1119 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1120
1121 tmp = 0;
1122 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1123 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1124 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1125
1126 tmp = 0;
1127 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1128 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1129 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1130
1131 tmp = 0;
1132 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1133 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1134 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1135
1136 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1137 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1138
1139 // r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1140
1141 // r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1142 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1143 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1144
1145 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1146 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1147 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1148 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1149 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1150 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1151
1152 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1153 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1154 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1155 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1156
1157 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1158 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1159 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1160 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1161 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1162 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1163 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1164 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1165 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1166 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1167 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1168 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1169 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1170 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1171 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1172 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1173 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1174 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1175
1176 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1177 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1178 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1179 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1180 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1181 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1182 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1183 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1184 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1185 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1186 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1187 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1188 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1189 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1190 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1191 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1192 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1193 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1194 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1195 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1196 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1197 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1198 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1199 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1200 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1201 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1202 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1203 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1204 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1205 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1206 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1207 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1208
1209 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
1210
1211 r600_context_pipe_state_set(&rctx->ctx, rstate);
1212 }
1213
1214 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
1215 {
1216 struct r600_pipe_state state;
1217
1218 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
1219 state.nregs = 0;
1220 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1221 float offset_units = rctx->rasterizer->offset_units;
1222 unsigned offset_db_fmt_cntl = 0, depth;
1223
1224 switch (rctx->framebuffer.zsbuf->texture->format) {
1225 case PIPE_FORMAT_Z24X8_UNORM:
1226 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1227 depth = -24;
1228 offset_units *= 2.0f;
1229 break;
1230 case PIPE_FORMAT_Z32_FLOAT:
1231 depth = -23;
1232 offset_units *= 1.0f;
1233 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1234 break;
1235 case PIPE_FORMAT_Z16_UNORM:
1236 depth = -16;
1237 offset_units *= 4.0f;
1238 break;
1239 default:
1240 return;
1241 }
1242 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1243 r600_pipe_state_add_reg(&state,
1244 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1245 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1246 r600_pipe_state_add_reg(&state,
1247 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1248 fui(offset_units), 0xFFFFFFFF, NULL);
1249 r600_pipe_state_add_reg(&state,
1250 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1251 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1252 r600_pipe_state_add_reg(&state,
1253 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1254 fui(offset_units), 0xFFFFFFFF, NULL);
1255 r600_pipe_state_add_reg(&state,
1256 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1257 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1258 r600_context_pipe_state_set(&rctx->ctx, &state);
1259 }
1260 }
1261
1262 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
1263 void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
1264 {
1265 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1266 struct r600_pipe_state *rstate;
1267 struct r600_resource *rbuffer;
1268 unsigned i, j, offset, prim;
1269 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
1270 struct pipe_vertex_buffer *vertex_buffer;
1271 struct r600_draw rdraw;
1272 struct r600_pipe_state vgt;
1273 struct r600_drawl draw;
1274 boolean translate = FALSE;
1275
1276 if (rctx->vertex_elements->incompatible_layout) {
1277 r600_begin_vertex_translate(rctx);
1278 translate = TRUE;
1279 }
1280
1281 if (rctx->any_user_vbs) {
1282 r600_upload_user_buffers(rctx);
1283 rctx->any_user_vbs = FALSE;
1284 }
1285
1286 memset(&draw, 0, sizeof(struct r600_drawl));
1287 draw.ctx = ctx;
1288 draw.mode = info->mode;
1289 draw.start = info->start;
1290 draw.count = info->count;
1291 if (info->indexed && rctx->index_buffer.buffer) {
1292 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
1293 draw.min_index = info->min_index;
1294 draw.max_index = info->max_index;
1295 draw.index_bias = info->index_bias;
1296
1297 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
1298 &rctx->index_buffer.index_size,
1299 &draw.start,
1300 info->count);
1301
1302 draw.index_size = rctx->index_buffer.index_size;
1303 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
1304 draw.index_buffer_offset = draw.start * draw.index_size;
1305 draw.start = 0;
1306 r600_upload_index_buffer(rctx, &draw);
1307 } else {
1308 draw.index_size = 0;
1309 draw.index_buffer = NULL;
1310 draw.min_index = info->min_index;
1311 draw.max_index = info->max_index;
1312 draw.index_bias = info->start;
1313 }
1314
1315 switch (draw.index_size) {
1316 case 2:
1317 vgt_draw_initiator = 0;
1318 vgt_dma_index_type = 0;
1319 break;
1320 case 4:
1321 vgt_draw_initiator = 0;
1322 vgt_dma_index_type = 1;
1323 break;
1324 case 0:
1325 vgt_draw_initiator = 2;
1326 vgt_dma_index_type = 0;
1327 break;
1328 default:
1329 R600_ERR("unsupported index size %d\n", draw.index_size);
1330 return;
1331 }
1332 if (r600_conv_pipe_prim(draw.mode, &prim))
1333 return;
1334
1335 /* rebuild vertex shader if input format changed */
1336 if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
1337 return;
1338 if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
1339 return;
1340
1341 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
1342 uint32_t word3, word2;
1343 uint32_t format;
1344 rstate = &rctx->vs_resource[i];
1345
1346 rstate->id = R600_PIPE_STATE_RESOURCE;
1347 rstate->nregs = 0;
1348
1349 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
1350 vertex_buffer = &rctx->vertex_buffer[j];
1351 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
1352 offset = rctx->vertex_elements->elements[i].src_offset +
1353 vertex_buffer->buffer_offset +
1354 r600_bo_offset(rbuffer->bo);
1355
1356 format = r600_translate_vertex_data_type(rctx->vertex_elements->hw_format[i]);
1357
1358 word2 = format | S_030008_STRIDE(vertex_buffer->stride);
1359
1360 word3 = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1361 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1362 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1363 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
1364
1365 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
1366 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
1367 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
1368 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3, word3, 0xFFFFFFFF, NULL);
1369 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
1370 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
1371 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x00000000, 0xFFFFFFFF, NULL);
1372 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7, 0xC0000000, 0xFFFFFFFF, NULL);
1373 evergreen_fs_resource_set(&rctx->ctx, rstate, i);
1374 }
1375
1376 mask = 0;
1377 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
1378 mask |= (0xF << (i * 4));
1379 }
1380
1381 vgt.id = R600_PIPE_STATE_VGT;
1382 vgt.nregs = 0;
1383 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
1384 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw.index_bias, 0xFFFFFFFF, NULL);
1385 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
1386 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw.max_index, 0xFFFFFFFF, NULL);
1387 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw.min_index, 0xFFFFFFFF, NULL);
1388 r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
1389 r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
1390 r600_context_pipe_state_set(&rctx->ctx, &vgt);
1391
1392 rdraw.vgt_num_indices = draw.count;
1393 rdraw.vgt_num_instances = 1;
1394 rdraw.vgt_index_type = vgt_dma_index_type;
1395 rdraw.vgt_draw_initiator = vgt_draw_initiator;
1396 rdraw.indices = NULL;
1397 if (draw.index_buffer) {
1398 rbuffer = (struct r600_resource*)draw.index_buffer;
1399 rdraw.indices = rbuffer->bo;
1400 rdraw.indices_bo_offset = draw.index_buffer_offset;
1401 }
1402 evergreen_context_draw(&rctx->ctx, &rdraw);
1403
1404 if (translate)
1405 r600_end_vertex_translate(rctx);
1406
1407 pipe_resource_reference(&draw.index_buffer, NULL);
1408 }
1409
1410 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1411 {
1412 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1413 struct r600_pipe_state *rstate = &shader->rstate;
1414 struct r600_shader *rshader = &shader->shader;
1415 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
1416 int pos_index = -1, face_index = -1;
1417 int ninterp = 0;
1418 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1419 unsigned spi_baryc_cntl;
1420
1421 /* clear previous register */
1422 rstate->nregs = 0;
1423
1424 for (i = 0; i < rshader->ninput; i++) {
1425 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
1426 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1427 POSITION goes via GPRs from the SC so isn't counted */
1428 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1429 pos_index = i;
1430 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1431 face_index = i;
1432 else {
1433 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
1434 rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1435 ninterp++;
1436 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1437 have_linear = TRUE;
1438 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1439 have_perspective = TRUE;
1440 if (rshader->input[i].centroid)
1441 have_centroid = TRUE;
1442 }
1443 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
1444 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
1445 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
1446 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
1447 }
1448 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
1449 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
1450 tmp |= S_028644_PT_SPRITE_TEX(1);
1451 }
1452 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
1453 }
1454 for (i = 0; i < rshader->noutput; i++) {
1455 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1456 r600_pipe_state_add_reg(rstate,
1457 R_02880C_DB_SHADER_CONTROL,
1458 S_02880C_Z_EXPORT_ENABLE(1),
1459 S_02880C_Z_EXPORT_ENABLE(1), NULL);
1460 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1461 r600_pipe_state_add_reg(rstate,
1462 R_02880C_DB_SHADER_CONTROL,
1463 S_02880C_STENCIL_EXPORT_ENABLE(1),
1464 S_02880C_STENCIL_EXPORT_ENABLE(1), NULL);
1465 }
1466
1467 exports_ps = 0;
1468 num_cout = 0;
1469 for (i = 0; i < rshader->noutput; i++) {
1470 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1471 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1472 exports_ps |= 1;
1473 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1474 num_cout++;
1475 }
1476 }
1477 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1478 if (!exports_ps) {
1479 /* always at least export 1 component per pixel */
1480 exports_ps = 2;
1481 }
1482
1483 if (ninterp == 0) {
1484 ninterp = 1;
1485 have_perspective = TRUE;
1486 }
1487
1488 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
1489 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
1490 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
1491 spi_input_z = 0;
1492 if (pos_index != -1) {
1493 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
1494 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1495 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
1496 spi_input_z |= 1;
1497 }
1498
1499 spi_ps_in_control_1 = 0;
1500 if (face_index != -1) {
1501 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1502 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1503 }
1504
1505 spi_baryc_cntl = 0;
1506 if (have_perspective)
1507 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
1508 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
1509 if (have_linear)
1510 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
1511 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
1512
1513 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1514 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1515 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1516 spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1517 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
1518 0, 0xFFFFFFFF, NULL);
1519 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1520 r600_pipe_state_add_reg(rstate,
1521 R_0286E0_SPI_BARYC_CNTL,
1522 spi_baryc_cntl,
1523 0xFFFFFFFF, NULL);
1524
1525 r600_pipe_state_add_reg(rstate,
1526 R_028840_SQ_PGM_START_PS,
1527 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1528 r600_pipe_state_add_reg(rstate,
1529 R_028844_SQ_PGM_RESOURCES_PS,
1530 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1531 S_028844_PRIME_CACHE_ON_DRAW(1) |
1532 S_028844_STACK_SIZE(rshader->bc.nstack),
1533 0xFFFFFFFF, NULL);
1534 r600_pipe_state_add_reg(rstate,
1535 R_028848_SQ_PGM_RESOURCES_2_PS,
1536 0x0, 0xFFFFFFFF, NULL);
1537 r600_pipe_state_add_reg(rstate,
1538 R_02884C_SQ_PGM_EXPORTS_PS,
1539 exports_ps, 0xFFFFFFFF, NULL);
1540
1541 if (rshader->uses_kill) {
1542 /* only set some bits here, the other bits are set in the dsa state */
1543 r600_pipe_state_add_reg(rstate,
1544 R_02880C_DB_SHADER_CONTROL,
1545 S_02880C_KILL_ENABLE(1),
1546 S_02880C_KILL_ENABLE(1), NULL);
1547 }
1548
1549 r600_pipe_state_add_reg(rstate,
1550 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
1551 0xFFFFFFFF, NULL);
1552 }
1553
1554 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1555 {
1556 struct r600_pipe_state *rstate = &shader->rstate;
1557 struct r600_shader *rshader = &shader->shader;
1558 unsigned spi_vs_out_id[10];
1559 unsigned i, tmp;
1560
1561 /* clear previous register */
1562 rstate->nregs = 0;
1563
1564 /* so far never got proper semantic id from tgsi */
1565 for (i = 0; i < 10; i++) {
1566 spi_vs_out_id[i] = 0;
1567 }
1568 for (i = 0; i < 32; i++) {
1569 tmp = i << ((i & 3) * 8);
1570 spi_vs_out_id[i / 4] |= tmp;
1571 }
1572 for (i = 0; i < 10; i++) {
1573 r600_pipe_state_add_reg(rstate,
1574 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1575 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1576 }
1577
1578 r600_pipe_state_add_reg(rstate,
1579 R_0286C4_SPI_VS_OUT_CONFIG,
1580 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1581 0xFFFFFFFF, NULL);
1582 r600_pipe_state_add_reg(rstate,
1583 R_028860_SQ_PGM_RESOURCES_VS,
1584 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1585 S_028860_STACK_SIZE(rshader->bc.nstack),
1586 0xFFFFFFFF, NULL);
1587 r600_pipe_state_add_reg(rstate,
1588 R_028864_SQ_PGM_RESOURCES_2_VS,
1589 0x0, 0xFFFFFFFF, NULL);
1590 r600_pipe_state_add_reg(rstate,
1591 R_0288A8_SQ_PGM_RESOURCES_FS,
1592 0x00000000, 0xFFFFFFFF, NULL);
1593 r600_pipe_state_add_reg(rstate,
1594 R_02885C_SQ_PGM_START_VS,
1595 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1596 r600_pipe_state_add_reg(rstate,
1597 R_0288A4_SQ_PGM_START_FS,
1598 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo_fetch);
1599
1600 r600_pipe_state_add_reg(rstate,
1601 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1602 0xFFFFFFFF, NULL);
1603 }
1604
1605 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1606 {
1607 struct pipe_depth_stencil_alpha_state dsa;
1608 struct r600_pipe_state *rstate;
1609
1610 memset(&dsa, 0, sizeof(dsa));
1611
1612 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1613 r600_pipe_state_add_reg(rstate,
1614 R_02880C_DB_SHADER_CONTROL,
1615 0x0,
1616 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1617 r600_pipe_state_add_reg(rstate,
1618 R_028000_DB_RENDER_CONTROL,
1619 S_028000_DEPTH_COPY_ENABLE(1) |
1620 S_028000_STENCIL_COPY_ENABLE(1) |
1621 S_028000_COPY_CENTROID(1),
1622 S_028000_DEPTH_COPY_ENABLE(1) |
1623 S_028000_STENCIL_COPY_ENABLE(1) |
1624 S_028000_COPY_CENTROID(1), NULL);
1625 return rstate;
1626 }