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r600g: start splitting out common code from eg/r600.
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "eg_state_inlines.h"
50
51 static void evergreen_set_blend_color(struct pipe_context *ctx,
52 const struct pipe_blend_color *state)
53 {
54 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
55 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
56
57 if (rstate == NULL)
58 return;
59
60 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
61 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
62 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
63 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
65
66 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
67 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
68 r600_context_pipe_state_set(&rctx->ctx, rstate);
69 }
70
71 static void *evergreen_create_blend_state(struct pipe_context *ctx,
72 const struct pipe_blend_state *state)
73 {
74 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
75 struct r600_pipe_state *rstate;
76 u32 color_control, target_mask;
77 /* FIXME there is more then 8 framebuffer */
78 unsigned blend_cntl[8];
79
80 if (blend == NULL) {
81 return NULL;
82 }
83 rstate = &blend->rstate;
84
85 rstate->id = R600_PIPE_STATE_BLEND;
86
87 target_mask = 0;
88 color_control = S_028808_MODE(1);
89 if (state->logicop_enable) {
90 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
91 } else {
92 color_control |= (0xcc << 16);
93 }
94 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
95 if (state->independent_blend_enable) {
96 for (int i = 0; i < 8; i++) {
97 target_mask |= (state->rt[i].colormask << (4 * i));
98 }
99 } else {
100 for (int i = 0; i < 8; i++) {
101 target_mask |= (state->rt[0].colormask << (4 * i));
102 }
103 }
104 blend->cb_target_mask = target_mask;
105 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
106 color_control, 0xFFFFFFFF, NULL);
107 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
108
109 for (int i = 0; i < 8; i++) {
110 unsigned eqRGB = state->rt[i].rgb_func;
111 unsigned srcRGB = state->rt[i].rgb_src_factor;
112 unsigned dstRGB = state->rt[i].rgb_dst_factor;
113 unsigned eqA = state->rt[i].alpha_func;
114 unsigned srcA = state->rt[i].alpha_src_factor;
115 unsigned dstA = state->rt[i].alpha_dst_factor;
116
117 blend_cntl[i] = 0;
118 if (!state->rt[i].blend_enable)
119 continue;
120
121 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
122 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
123 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
124 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
125
126 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
127 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
128 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
129 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
130 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
131 }
132 }
133 for (int i = 0; i < 8; i++) {
134 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
135 }
136
137 return rstate;
138 }
139
140 static void evergreen_bind_blend_state(struct pipe_context *ctx, void *state)
141 {
142 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
143 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
144 struct r600_pipe_state *rstate;
145
146 if (state == NULL)
147 return;
148 rstate = &blend->rstate;
149 rctx->states[rstate->id] = rstate;
150 rctx->cb_target_mask = blend->cb_target_mask;
151 r600_context_pipe_state_set(&rctx->ctx, rstate);
152 }
153
154 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
155 const struct pipe_depth_stencil_alpha_state *state)
156 {
157 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
158 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
159 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
160
161 if (rstate == NULL) {
162 return NULL;
163 }
164
165 rstate->id = R600_PIPE_STATE_DSA;
166 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
167 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
168 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
169 * be set if shader use texkill instruction
170 */
171 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
172 stencil_ref_mask = 0;
173 stencil_ref_mask_bf = 0;
174 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
175 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
176 S_028800_ZFUNC(state->depth.func);
177
178 /* stencil */
179 if (state->stencil[0].enabled) {
180 db_depth_control |= S_028800_STENCIL_ENABLE(1);
181 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
182 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
183 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
184 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
185
186
187 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
188 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
189 if (state->stencil[1].enabled) {
190 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
191 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
192 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
193 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
194 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
195 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
196 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
197 }
198 }
199
200 /* alpha */
201 alpha_test_control = 0;
202 alpha_ref = 0;
203 if (state->alpha.enabled) {
204 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
205 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
206 alpha_ref = fui(state->alpha.ref_value);
207 }
208
209 /* misc */
210 db_render_control = 0;
211 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
212 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
213 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
214 /* TODO db_render_override depends on query */
215 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
216 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
217 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
218 r600_pipe_state_add_reg(rstate,
219 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
220 0xFFFFFFFF & C_028430_STENCILREF, NULL);
221 r600_pipe_state_add_reg(rstate,
222 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
223 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
224 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
225 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
226 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
227 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
228 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
229 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
230 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
231 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
232 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
233 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
234
235 return rstate;
236 }
237
238 static void *evergreen_create_rs_state(struct pipe_context *ctx,
239 const struct pipe_rasterizer_state *state)
240 {
241 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
242 struct r600_pipe_state *rstate;
243 unsigned tmp;
244 unsigned prov_vtx = 1, polygon_dual_mode;
245 unsigned clip_rule;
246
247 if (rs == NULL) {
248 return NULL;
249 }
250
251 rstate = &rs->rstate;
252 rs->flatshade = state->flatshade;
253 rs->sprite_coord_enable = state->sprite_coord_enable;
254
255 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
256
257 /* offset */
258 rs->offset_units = state->offset_units;
259 rs->offset_scale = state->offset_scale * 12.0f;
260
261 rstate->id = R600_PIPE_STATE_RASTERIZER;
262 if (state->flatshade_first)
263 prov_vtx = 0;
264 tmp = 0x00000001;
265 if (state->sprite_coord_enable) {
266 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
267 S_0286D4_PNT_SPRITE_OVRD_X(2) |
268 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
269 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
270 S_0286D4_PNT_SPRITE_OVRD_W(1);
271 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
272 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
273 }
274 }
275 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
276
277 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
278 state->fill_back != PIPE_POLYGON_MODE_FILL);
279 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
280 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
281 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
282 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
283 S_028814_FACE(!state->front_ccw) |
284 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
285 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
286 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
287 S_028814_POLY_MODE(polygon_dual_mode) |
288 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
289 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
290 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
291 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
292 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
293 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
294 /* point size 12.4 fixed point */
295 tmp = (unsigned)(state->point_size * 8.0);
296 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
297 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
298 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
299 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
300 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
301 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
302 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
303 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
304 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
305 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 0x00000005, 0xFFFFFFFF, NULL);
306 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
307 return rstate;
308 }
309
310 static void evergreen_bind_rs_state(struct pipe_context *ctx, void *state)
311 {
312 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
313 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
314
315 if (state == NULL)
316 return;
317
318 rctx->flatshade = rs->flatshade;
319 rctx->sprite_coord_enable = rs->sprite_coord_enable;
320 rctx->rasterizer = rs;
321
322 rctx->states[rs->rstate.id] = &rs->rstate;
323 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
324 }
325
326 static void evergreen_delete_rs_state(struct pipe_context *ctx, void *state)
327 {
328 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
329 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
330
331 if (rctx->rasterizer == rs) {
332 rctx->rasterizer = NULL;
333 }
334 if (rctx->states[rs->rstate.id] == &rs->rstate) {
335 rctx->states[rs->rstate.id] = NULL;
336 }
337 free(rs);
338 }
339
340 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
341 const struct pipe_sampler_state *state)
342 {
343 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
344 union util_color uc;
345
346 if (rstate == NULL) {
347 return NULL;
348 }
349
350 rstate->id = R600_PIPE_STATE_SAMPLER;
351 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
352 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
353 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
354 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
355 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
356 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
357 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
358 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
359 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
360 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
361 /* FIXME LOD it depends on texture base level ... */
362 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
363 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
364 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)),
365 0xFFFFFFFF, NULL);
366 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
367 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
368 S_03C008_TYPE(1),
369 0xFFFFFFFF, NULL);
370
371 if (uc.ui) {
372 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
373 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
374 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
375 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
376 }
377 return rstate;
378 }
379
380 static void evergreen_sampler_view_destroy(struct pipe_context *ctx,
381 struct pipe_sampler_view *state)
382 {
383 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
384
385 pipe_resource_reference(&state->texture, NULL);
386 FREE(resource);
387 }
388
389 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
390 struct pipe_resource *texture,
391 const struct pipe_sampler_view *state)
392 {
393 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
394 struct r600_pipe_state *rstate;
395 const struct util_format_description *desc;
396 struct r600_resource_texture *tmp;
397 struct r600_resource *rbuffer;
398 unsigned format;
399 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
400 unsigned char swizzle[4];
401 struct r600_bo *bo[2];
402
403 if (resource == NULL)
404 return NULL;
405 rstate = &resource->state;
406
407 /* initialize base object */
408 resource->base = *state;
409 resource->base.texture = NULL;
410 pipe_reference(NULL, &texture->reference);
411 resource->base.texture = texture;
412 resource->base.reference.count = 1;
413 resource->base.context = ctx;
414
415 swizzle[0] = state->swizzle_r;
416 swizzle[1] = state->swizzle_g;
417 swizzle[2] = state->swizzle_b;
418 swizzle[3] = state->swizzle_a;
419 format = r600_translate_texformat(state->format,
420 swizzle,
421 &word4, &yuv_format);
422 if (format == ~0) {
423 format = 0;
424 }
425 desc = util_format_description(state->format);
426 if (desc == NULL) {
427 R600_ERR("unknow format %d\n", state->format);
428 }
429 tmp = (struct r600_resource_texture*)texture;
430 rbuffer = &tmp->resource;
431 bo[0] = rbuffer->bo;
432 bo[1] = rbuffer->bo;
433 /* FIXME depth texture decompression */
434 if (tmp->depth) {
435 r600_texture_depth_flush(ctx, texture);
436 tmp = (struct r600_resource_texture*)texture;
437 rbuffer = &tmp->flushed_depth_texture->resource;
438 bo[0] = rbuffer->bo;
439 bo[1] = rbuffer->bo;
440 }
441 pitch = align(tmp->pitch_in_pixels[0], 8);
442
443 /* FIXME properly handle first level != 0 */
444 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
445 S_030000_DIM(r600_tex_dim(texture->target)) |
446 S_030000_PITCH((pitch / 8) - 1) |
447 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
448 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
449 S_030004_TEX_HEIGHT(texture->height0 - 1) |
450 S_030004_TEX_DEPTH(texture->depth0 - 1),
451 0xFFFFFFFF, NULL);
452 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
453 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
454 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
455 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
456 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
457 word4 | S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
458 S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
459 S_030010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
460 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
461 S_030014_LAST_LEVEL(state->last_level) |
462 S_030014_BASE_ARRAY(0) |
463 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
464 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
465 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
466 S_03001C_DATA_FORMAT(format) |
467 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
468
469 return &resource->base;
470 }
471
472 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
473 struct pipe_sampler_view **views)
474 {
475 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
476 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
477
478 for (int i = 0; i < count; i++) {
479 if (resource[i]) {
480 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i + PIPE_MAX_ATTRIBS);
481 }
482 }
483 }
484
485 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
486 struct pipe_sampler_view **views)
487 {
488 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
489 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
490 int i;
491
492 for (i = 0; i < count; i++) {
493 if (&rctx->ps_samplers.views[i]->base != views[i]) {
494 if (resource[i])
495 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
496 else
497 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
498
499 pipe_sampler_view_reference(
500 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
501 views[i]);
502 }
503 }
504 for (i = count; i < NUM_TEX_UNITS; i++) {
505 if (rctx->ps_samplers.views[i]) {
506 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
507 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
508 }
509 }
510 rctx->ps_samplers.n_views = count;
511 }
512
513 static void evergreen_bind_state(struct pipe_context *ctx, void *state)
514 {
515 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
516 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
517
518 if (state == NULL)
519 return;
520 rctx->states[rstate->id] = rstate;
521 r600_context_pipe_state_set(&rctx->ctx, rstate);
522 }
523
524 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
525 {
526 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
527 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
528
529
530 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
531 rctx->ps_samplers.n_samplers = count;
532
533 for (int i = 0; i < count; i++) {
534 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
535 }
536 }
537
538 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
539 {
540 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
541 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
542
543 for (int i = 0; i < count; i++) {
544 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
545 }
546 }
547
548 static void evergreen_delete_state(struct pipe_context *ctx, void *state)
549 {
550 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
551 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
552
553 if (rctx->states[rstate->id] == rstate) {
554 rctx->states[rstate->id] = NULL;
555 }
556 for (int i = 0; i < rstate->nregs; i++) {
557 r600_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
558 }
559 free(rstate);
560 }
561
562 static void evergreen_delete_vertex_element(struct pipe_context *ctx, void *state)
563 {
564 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
565
566 if (v == NULL)
567 return;
568 if (--v->refcount)
569 return;
570 free(v);
571 }
572
573 static void evergreen_set_clip_state(struct pipe_context *ctx,
574 const struct pipe_clip_state *state)
575 {
576 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
577 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
578
579 if (rstate == NULL)
580 return;
581
582 rctx->clip = *state;
583 rstate->id = R600_PIPE_STATE_CLIP;
584 for (int i = 0; i < state->nr; i++) {
585 r600_pipe_state_add_reg(rstate,
586 R_0285BC_PA_CL_UCP0_X + i * 4,
587 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
588 r600_pipe_state_add_reg(rstate,
589 R_0285C0_PA_CL_UCP0_Y + i * 4,
590 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
591 r600_pipe_state_add_reg(rstate,
592 R_0285C4_PA_CL_UCP0_Z + i * 4,
593 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
594 r600_pipe_state_add_reg(rstate,
595 R_0285C8_PA_CL_UCP0_W + i * 4,
596 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
597 }
598 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
599 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
600 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
601 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
602
603 free(rctx->states[R600_PIPE_STATE_CLIP]);
604 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
605 r600_context_pipe_state_set(&rctx->ctx, rstate);
606 }
607
608 static void evergreen_bind_vertex_elements(struct pipe_context *ctx, void *state)
609 {
610 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
611 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
612
613 evergreen_delete_vertex_element(ctx, rctx->vertex_elements);
614 rctx->vertex_elements = v;
615 if (v) {
616 v->refcount++;
617 // rctx->vs_rebuild = TRUE;
618 }
619 }
620
621 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
622 const struct pipe_poly_stipple *state)
623 {
624 }
625
626 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
627 {
628 }
629
630 static void evergreen_set_scissor_state(struct pipe_context *ctx,
631 const struct pipe_scissor_state *state)
632 {
633 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
634 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
635 u32 tl, br;
636
637 if (rstate == NULL)
638 return;
639
640 rstate->id = R600_PIPE_STATE_SCISSOR;
641 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
642 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
643 r600_pipe_state_add_reg(rstate,
644 R_028210_PA_SC_CLIPRECT_0_TL, tl,
645 0xFFFFFFFF, NULL);
646 r600_pipe_state_add_reg(rstate,
647 R_028214_PA_SC_CLIPRECT_0_BR, br,
648 0xFFFFFFFF, NULL);
649 r600_pipe_state_add_reg(rstate,
650 R_028218_PA_SC_CLIPRECT_1_TL, tl,
651 0xFFFFFFFF, NULL);
652 r600_pipe_state_add_reg(rstate,
653 R_02821C_PA_SC_CLIPRECT_1_BR, br,
654 0xFFFFFFFF, NULL);
655 r600_pipe_state_add_reg(rstate,
656 R_028220_PA_SC_CLIPRECT_2_TL, tl,
657 0xFFFFFFFF, NULL);
658 r600_pipe_state_add_reg(rstate,
659 R_028224_PA_SC_CLIPRECT_2_BR, br,
660 0xFFFFFFFF, NULL);
661 r600_pipe_state_add_reg(rstate,
662 R_028228_PA_SC_CLIPRECT_3_TL, tl,
663 0xFFFFFFFF, NULL);
664 r600_pipe_state_add_reg(rstate,
665 R_02822C_PA_SC_CLIPRECT_3_BR, br,
666 0xFFFFFFFF, NULL);
667
668 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
669 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
670 r600_context_pipe_state_set(&rctx->ctx, rstate);
671 }
672
673 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
674 const struct pipe_stencil_ref *state)
675 {
676 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
677 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
678 u32 tmp;
679
680 if (rstate == NULL)
681 return;
682
683 rctx->stencil_ref = *state;
684 rstate->id = R600_PIPE_STATE_STENCIL_REF;
685 tmp = S_028430_STENCILREF(state->ref_value[0]);
686 r600_pipe_state_add_reg(rstate,
687 R_028430_DB_STENCILREFMASK, tmp,
688 ~C_028430_STENCILREF, NULL);
689 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
690 r600_pipe_state_add_reg(rstate,
691 R_028434_DB_STENCILREFMASK_BF, tmp,
692 ~C_028434_STENCILREF_BF, NULL);
693
694 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
695 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
696 r600_context_pipe_state_set(&rctx->ctx, rstate);
697 }
698
699 static void evergreen_set_viewport_state(struct pipe_context *ctx,
700 const struct pipe_viewport_state *state)
701 {
702 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
703 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
704
705 if (rstate == NULL)
706 return;
707
708 rctx->viewport = *state;
709 rstate->id = R600_PIPE_STATE_VIEWPORT;
710 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
711 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
712 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
713 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
714 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
715 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
716 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
717 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
718 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
719
720 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
721 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
722 r600_context_pipe_state_set(&rctx->ctx, rstate);
723 }
724
725 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
726 const struct pipe_framebuffer_state *state, int cb)
727 {
728 struct r600_resource_texture *rtex;
729 struct r600_resource *rbuffer;
730 struct r600_surface *surf;
731 unsigned level = state->cbufs[cb]->level;
732 unsigned pitch, slice;
733 unsigned color_info;
734 unsigned format, swap, ntype;
735 const struct util_format_description *desc;
736 struct r600_bo *bo[3];
737
738 surf = (struct r600_surface *)state->cbufs[cb];
739 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
740 rbuffer = &rtex->resource;
741 bo[0] = rbuffer->bo;
742 bo[1] = rbuffer->bo;
743 bo[2] = rbuffer->bo;
744
745 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
746 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
747 ntype = 0;
748 desc = util_format_description(rtex->resource.base.b.format);
749 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
750 ntype = V_028C70_NUMBER_SRGB;
751
752 format = r600_translate_colorformat(rtex->resource.base.b.format);
753 swap = r600_translate_colorswap(rtex->resource.base.b.format);
754 color_info = S_028C70_FORMAT(format) |
755 S_028C70_COMP_SWAP(swap) |
756 S_028C70_BLEND_CLAMP(1) |
757 S_028C70_NUMBER_TYPE(ntype);
758 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
759 color_info |= S_028C70_SOURCE_FORMAT(1);
760
761 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
762 r600_pipe_state_add_reg(rstate,
763 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
764 (state->cbufs[cb]->offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
765 r600_pipe_state_add_reg(rstate,
766 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
767 0x0, 0xFFFFFFFF, NULL);
768 r600_pipe_state_add_reg(rstate,
769 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
770 color_info, 0xFFFFFFFF, bo[0]);
771 r600_pipe_state_add_reg(rstate,
772 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
773 S_028C64_PITCH_TILE_MAX(pitch),
774 0xFFFFFFFF, NULL);
775 r600_pipe_state_add_reg(rstate,
776 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
777 S_028C68_SLICE_TILE_MAX(slice),
778 0xFFFFFFFF, NULL);
779 r600_pipe_state_add_reg(rstate,
780 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
781 0x00000000, 0xFFFFFFFF, NULL);
782 r600_pipe_state_add_reg(rstate,
783 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
784 S_028C74_NON_DISP_TILING_ORDER(1),
785 0xFFFFFFFF, bo[0]);
786 }
787
788 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
789 const struct pipe_framebuffer_state *state)
790 {
791 struct r600_resource_texture *rtex;
792 struct r600_resource *rbuffer;
793 struct r600_surface *surf;
794 unsigned level;
795 unsigned pitch, slice, format, stencil_format;
796
797 if (state->zsbuf == NULL)
798 return;
799
800 level = state->zsbuf->level;
801
802 surf = (struct r600_surface *)state->zsbuf;
803 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
804 rtex->tiled = 1;
805 rtex->array_mode[level] = 2;
806 rtex->tile_type = 1;
807 rtex->depth = 1;
808 rbuffer = &rtex->resource;
809
810 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
811 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
812 format = r600_translate_dbformat(state->zsbuf->texture->format);
813 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
814
815 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
816 (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
817 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
818 (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
819
820 if (stencil_format) {
821 uint32_t stencil_offset;
822
823 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
824 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
825 (state->zsbuf->offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
826 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
827 (state->zsbuf->offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
828 }
829
830 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
831 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
832 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
833
834 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
835 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
836 0xFFFFFFFF, rbuffer->bo);
837 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
838 S_028058_PITCH_TILE_MAX(pitch),
839 0xFFFFFFFF, NULL);
840 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
841 S_02805C_SLICE_TILE_MAX(slice),
842 0xFFFFFFFF, NULL);
843 }
844
845 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
846 const struct pipe_framebuffer_state *state)
847 {
848 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
849 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
850 u32 shader_mask, tl, br, target_mask;
851
852 if (rstate == NULL)
853 return;
854
855 /* unreference old buffer and reference new one */
856 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
857
858 util_copy_framebuffer_state(&rctx->framebuffer, state);
859
860 rctx->pframebuffer = &rctx->framebuffer;
861
862 /* build states */
863 for (int i = 0; i < state->nr_cbufs; i++) {
864 evergreen_cb(rctx, rstate, state, i);
865 }
866 if (state->zsbuf) {
867 evergreen_db(rctx, rstate, state);
868 }
869
870 target_mask = 0x00000000;
871 target_mask = 0xFFFFFFFF;
872 shader_mask = 0;
873 for (int i = 0; i < state->nr_cbufs; i++) {
874 target_mask ^= 0xf << (i * 4);
875 shader_mask |= 0xf << (i * 4);
876 }
877 tl = S_028240_TL_X(0) | S_028240_TL_Y(0);
878 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
879
880 r600_pipe_state_add_reg(rstate,
881 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
882 0xFFFFFFFF, NULL);
883 r600_pipe_state_add_reg(rstate,
884 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
885 0xFFFFFFFF, NULL);
886 r600_pipe_state_add_reg(rstate,
887 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
888 0xFFFFFFFF, NULL);
889 r600_pipe_state_add_reg(rstate,
890 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
891 0xFFFFFFFF, NULL);
892 r600_pipe_state_add_reg(rstate,
893 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
894 0xFFFFFFFF, NULL);
895 r600_pipe_state_add_reg(rstate,
896 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
897 0xFFFFFFFF, NULL);
898 r600_pipe_state_add_reg(rstate,
899 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
900 0xFFFFFFFF, NULL);
901 r600_pipe_state_add_reg(rstate,
902 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
903 0xFFFFFFFF, NULL);
904 r600_pipe_state_add_reg(rstate,
905 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
906 0xFFFFFFFF, NULL);
907 r600_pipe_state_add_reg(rstate,
908 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
909 0xFFFFFFFF, NULL);
910
911 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
912 0x00000000, target_mask, NULL);
913 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
914 shader_mask, 0xFFFFFFFF, NULL);
915 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
916 0x00000000, 0xFFFFFFFF, NULL);
917 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
918 0x00000000, 0xFFFFFFFF, NULL);
919
920 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
921 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
922 r600_context_pipe_state_set(&rctx->ctx, rstate);
923 }
924
925 static void evergreen_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
926 struct pipe_resource *buffer)
927 {
928 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
929 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
930
931 switch (shader) {
932 case PIPE_SHADER_VERTEX:
933 rctx->vs_const_buffer.nregs = 0;
934 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
935 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
936 ALIGN_DIVUP(buffer->width0 >> 4, 16),
937 0xFFFFFFFF, NULL);
938 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
939 R_028980_ALU_CONST_CACHE_VS_0,
940 (r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
941 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
942 break;
943 case PIPE_SHADER_FRAGMENT:
944 rctx->ps_const_buffer.nregs = 0;
945 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
946 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
947 ALIGN_DIVUP(buffer->width0 >> 4, 16),
948 0xFFFFFFFF, NULL);
949 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
950 R_028940_ALU_CONST_CACHE_PS_0,
951 (r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
952 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
953 break;
954 default:
955 R600_ERR("unsupported %d\n", shader);
956 return;
957 }
958 }
959
960 static void *evergreen_create_shader_state(struct pipe_context *ctx,
961 const struct pipe_shader_state *state)
962 {
963 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
964 int r;
965
966 r = r600_pipe_shader_create(ctx, shader, state->tokens);
967 if (r) {
968 return NULL;
969 }
970 return shader;
971 }
972
973 static void evergreen_bind_ps_shader(struct pipe_context *ctx, void *state)
974 {
975 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
976
977 /* TODO delete old shader */
978 rctx->ps_shader = (struct r600_pipe_shader *)state;
979 }
980
981 static void evergreen_bind_vs_shader(struct pipe_context *ctx, void *state)
982 {
983 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
984
985 /* TODO delete old shader */
986 rctx->vs_shader = (struct r600_pipe_shader *)state;
987 }
988
989 static void evergreen_delete_ps_shader(struct pipe_context *ctx, void *state)
990 {
991 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
992 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
993
994 if (rctx->ps_shader == shader) {
995 rctx->ps_shader = NULL;
996 }
997 /* TODO proper delete */
998 free(shader);
999 }
1000
1001 static void evergreen_delete_vs_shader(struct pipe_context *ctx, void *state)
1002 {
1003 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1004 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1005
1006 if (rctx->vs_shader == shader) {
1007 rctx->vs_shader = NULL;
1008 }
1009 /* TODO proper delete */
1010 free(shader);
1011 }
1012
1013 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
1014 {
1015 rctx->context.create_blend_state = evergreen_create_blend_state;
1016 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1017 rctx->context.create_fs_state = evergreen_create_shader_state;
1018 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1019 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1020 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1021 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1022 rctx->context.create_vs_state = evergreen_create_shader_state;
1023 rctx->context.bind_blend_state = evergreen_bind_blend_state;
1024 rctx->context.bind_depth_stencil_alpha_state = evergreen_bind_state;
1025 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1026 rctx->context.bind_fs_state = evergreen_bind_ps_shader;
1027 rctx->context.bind_rasterizer_state = evergreen_bind_rs_state;
1028 rctx->context.bind_vertex_elements_state = evergreen_bind_vertex_elements;
1029 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1030 rctx->context.bind_vs_state = evergreen_bind_vs_shader;
1031 rctx->context.delete_blend_state = evergreen_delete_state;
1032 rctx->context.delete_depth_stencil_alpha_state = evergreen_delete_state;
1033 rctx->context.delete_fs_state = evergreen_delete_ps_shader;
1034 rctx->context.delete_rasterizer_state = evergreen_delete_rs_state;
1035 rctx->context.delete_sampler_state = evergreen_delete_state;
1036 rctx->context.delete_vertex_elements_state = evergreen_delete_vertex_element;
1037 rctx->context.delete_vs_state = evergreen_delete_vs_shader;
1038 rctx->context.set_blend_color = evergreen_set_blend_color;
1039 rctx->context.set_clip_state = evergreen_set_clip_state;
1040 rctx->context.set_constant_buffer = evergreen_set_constant_buffer;
1041 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1042 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1043 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1044 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1045 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1046 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1047 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1048 rctx->context.set_index_buffer = r600_set_index_buffer;
1049 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1050 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1051 rctx->context.sampler_view_destroy = evergreen_sampler_view_destroy;
1052 }
1053
1054 void evergreen_init_config(struct r600_pipe_context *rctx)
1055 {
1056 struct r600_pipe_state *rstate = &rctx->config;
1057 int ps_prio;
1058 int vs_prio;
1059 int gs_prio;
1060 int es_prio;
1061 int hs_prio, cs_prio, ls_prio;
1062 int num_ps_gprs;
1063 int num_vs_gprs;
1064 int num_gs_gprs;
1065 int num_es_gprs;
1066 int num_hs_gprs;
1067 int num_ls_gprs;
1068 int num_temp_gprs;
1069 int num_ps_threads;
1070 int num_vs_threads;
1071 int num_gs_threads;
1072 int num_es_threads;
1073 int num_hs_threads;
1074 int num_ls_threads;
1075 int num_ps_stack_entries;
1076 int num_vs_stack_entries;
1077 int num_gs_stack_entries;
1078 int num_es_stack_entries;
1079 int num_hs_stack_entries;
1080 int num_ls_stack_entries;
1081 enum radeon_family family;
1082 unsigned tmp;
1083
1084 family = r600_get_family(rctx->radeon);
1085 ps_prio = 0;
1086 vs_prio = 1;
1087 gs_prio = 2;
1088 es_prio = 3;
1089 hs_prio = 0;
1090 ls_prio = 0;
1091 cs_prio = 0;
1092
1093 switch (family) {
1094 case CHIP_CEDAR:
1095 default:
1096 num_ps_gprs = 93;
1097 num_vs_gprs = 46;
1098 num_temp_gprs = 4;
1099 num_gs_gprs = 31;
1100 num_es_gprs = 31;
1101 num_hs_gprs = 23;
1102 num_ls_gprs = 23;
1103 num_ps_threads = 96;
1104 num_vs_threads = 16;
1105 num_gs_threads = 16;
1106 num_es_threads = 16;
1107 num_hs_threads = 16;
1108 num_ls_threads = 16;
1109 num_ps_stack_entries = 42;
1110 num_vs_stack_entries = 42;
1111 num_gs_stack_entries = 42;
1112 num_es_stack_entries = 42;
1113 num_hs_stack_entries = 42;
1114 num_ls_stack_entries = 42;
1115 break;
1116 case CHIP_REDWOOD:
1117 num_ps_gprs = 93;
1118 num_vs_gprs = 46;
1119 num_temp_gprs = 4;
1120 num_gs_gprs = 31;
1121 num_es_gprs = 31;
1122 num_hs_gprs = 23;
1123 num_ls_gprs = 23;
1124 num_ps_threads = 128;
1125 num_vs_threads = 20;
1126 num_gs_threads = 20;
1127 num_es_threads = 20;
1128 num_hs_threads = 20;
1129 num_ls_threads = 20;
1130 num_ps_stack_entries = 42;
1131 num_vs_stack_entries = 42;
1132 num_gs_stack_entries = 42;
1133 num_es_stack_entries = 42;
1134 num_hs_stack_entries = 42;
1135 num_ls_stack_entries = 42;
1136 break;
1137 case CHIP_JUNIPER:
1138 num_ps_gprs = 93;
1139 num_vs_gprs = 46;
1140 num_temp_gprs = 4;
1141 num_gs_gprs = 31;
1142 num_es_gprs = 31;
1143 num_hs_gprs = 23;
1144 num_ls_gprs = 23;
1145 num_ps_threads = 128;
1146 num_vs_threads = 20;
1147 num_gs_threads = 20;
1148 num_es_threads = 20;
1149 num_hs_threads = 20;
1150 num_ls_threads = 20;
1151 num_ps_stack_entries = 85;
1152 num_vs_stack_entries = 85;
1153 num_gs_stack_entries = 85;
1154 num_es_stack_entries = 85;
1155 num_hs_stack_entries = 85;
1156 num_ls_stack_entries = 85;
1157 break;
1158 case CHIP_CYPRESS:
1159 case CHIP_HEMLOCK:
1160 num_ps_gprs = 93;
1161 num_vs_gprs = 46;
1162 num_temp_gprs = 4;
1163 num_gs_gprs = 31;
1164 num_es_gprs = 31;
1165 num_hs_gprs = 23;
1166 num_ls_gprs = 23;
1167 num_ps_threads = 128;
1168 num_vs_threads = 20;
1169 num_gs_threads = 20;
1170 num_es_threads = 20;
1171 num_hs_threads = 20;
1172 num_ls_threads = 20;
1173 num_ps_stack_entries = 85;
1174 num_vs_stack_entries = 85;
1175 num_gs_stack_entries = 85;
1176 num_es_stack_entries = 85;
1177 num_hs_stack_entries = 85;
1178 num_ls_stack_entries = 85;
1179 break;
1180 }
1181
1182 tmp = 0x00000000;
1183 switch (family) {
1184 case CHIP_CEDAR:
1185 break;
1186 default:
1187 tmp |= S_008C00_VC_ENABLE(1);
1188 break;
1189 }
1190 tmp |= S_008C00_EXPORT_SRC_C(1);
1191 tmp |= S_008C00_CS_PRIO(cs_prio);
1192 tmp |= S_008C00_LS_PRIO(ls_prio);
1193 tmp |= S_008C00_HS_PRIO(hs_prio);
1194 tmp |= S_008C00_PS_PRIO(ps_prio);
1195 tmp |= S_008C00_VS_PRIO(vs_prio);
1196 tmp |= S_008C00_GS_PRIO(gs_prio);
1197 tmp |= S_008C00_ES_PRIO(es_prio);
1198 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1199
1200 tmp = 0;
1201 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1202 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1203 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1204 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1205
1206 tmp = 0;
1207 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1208 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1209 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1210
1211 tmp = 0;
1212 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1213 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1214 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1215
1216 tmp = 0;
1217 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1218 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1219 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1220 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1221 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1222
1223 tmp = 0;
1224 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1225 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1226 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1227
1228 tmp = 0;
1229 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1230 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1231 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1232
1233 tmp = 0;
1234 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1235 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1236 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1237
1238 tmp = 0;
1239 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1240 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1241 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1242
1243 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1244 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1245
1246 // r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1247
1248 // r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1249 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1250 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1251
1252 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1253 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1254 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1255 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1256 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1257 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1258
1259 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1260 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1261 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1262 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1263
1264 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1265 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1266 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1267 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1268 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1269 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1270 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1271 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1272 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1273 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1274 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1275 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1276 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1277 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1278 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1279 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1280 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1281 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1282
1283 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1284 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1285 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1286 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1287 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1288 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1289 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1290 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1291 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1292 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1293 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1294 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1295 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1296 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1297 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1298 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1299 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1300 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1301 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1302 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1303 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1304 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1305 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1306 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1307 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1308 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1309 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1310 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1311 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1312 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1313 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1314 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1315
1316 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1317 0x0, 0xFFFFFFFF, NULL);
1318
1319 r600_context_pipe_state_set(&rctx->ctx, rstate);
1320 }
1321
1322 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
1323 void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
1324 {
1325 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1326 struct r600_pipe_state *rstate;
1327 struct r600_resource *rbuffer;
1328 unsigned i, j, offset, prim;
1329 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
1330 struct pipe_vertex_buffer *vertex_buffer;
1331 struct r600_draw rdraw;
1332 struct r600_pipe_state vgt;
1333 struct r600_drawl draw;
1334 boolean translate = FALSE;
1335
1336 if (rctx->vertex_elements->incompatible_layout) {
1337 r600_begin_vertex_translate(rctx);
1338 translate = TRUE;
1339 }
1340
1341 if (rctx->any_user_vbs) {
1342 r600_upload_user_buffers(rctx);
1343 rctx->any_user_vbs = FALSE;
1344 }
1345
1346 memset(&draw, 0, sizeof(struct r600_drawl));
1347 draw.ctx = ctx;
1348 draw.mode = info->mode;
1349 draw.start = info->start;
1350 draw.count = info->count;
1351 if (info->indexed && rctx->index_buffer.buffer) {
1352 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
1353 draw.min_index = info->min_index;
1354 draw.max_index = info->max_index;
1355 draw.index_bias = info->index_bias;
1356
1357 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
1358 &rctx->index_buffer.index_size,
1359 &draw.start,
1360 info->count);
1361
1362 draw.index_size = rctx->index_buffer.index_size;
1363 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
1364 draw.index_buffer_offset = draw.start * draw.index_size;
1365 draw.start = 0;
1366 r600_upload_index_buffer(rctx, &draw);
1367 } else {
1368 draw.index_size = 0;
1369 draw.index_buffer = NULL;
1370 draw.min_index = info->min_index;
1371 draw.max_index = info->max_index;
1372 draw.index_bias = info->start;
1373 }
1374
1375 switch (draw.index_size) {
1376 case 2:
1377 vgt_draw_initiator = 0;
1378 vgt_dma_index_type = 0;
1379 break;
1380 case 4:
1381 vgt_draw_initiator = 0;
1382 vgt_dma_index_type = 1;
1383 break;
1384 case 0:
1385 vgt_draw_initiator = 2;
1386 vgt_dma_index_type = 0;
1387 break;
1388 default:
1389 R600_ERR("unsupported index size %d\n", draw.index_size);
1390 return;
1391 }
1392 if (r600_conv_pipe_prim(draw.mode, &prim))
1393 return;
1394
1395 /* rebuild vertex shader if input format changed */
1396 if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
1397 return;
1398 if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
1399 return;
1400
1401 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
1402 uint32_t word3, word2;
1403 uint32_t format;
1404 rstate = &rctx->vs_resource[i];
1405
1406 rstate->id = R600_PIPE_STATE_RESOURCE;
1407 rstate->nregs = 0;
1408
1409 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
1410 vertex_buffer = &rctx->vertex_buffer[j];
1411 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
1412 offset = rctx->vertex_elements->elements[i].src_offset +
1413 vertex_buffer->buffer_offset +
1414 r600_bo_offset(rbuffer->bo);
1415
1416 format = r600_translate_vertex_data_type(rctx->vertex_elements->hw_format[i]);
1417
1418 word2 = format | S_030008_STRIDE(vertex_buffer->stride);
1419
1420 word3 = r600_translate_vertex_data_swizzle(rctx->vertex_elements->hw_format[i]);
1421
1422 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
1423 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
1424 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
1425 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3, word3, 0xFFFFFFFF, NULL);
1426 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
1427 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
1428 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x00000000, 0xFFFFFFFF, NULL);
1429 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7, 0xC0000000, 0xFFFFFFFF, NULL);
1430 evergreen_vs_resource_set(&rctx->ctx, rstate, i);
1431 }
1432
1433 mask = 0;
1434 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
1435 mask |= (0xF << (i * 4));
1436 }
1437
1438 vgt.id = R600_PIPE_STATE_VGT;
1439 vgt.nregs = 0;
1440 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
1441 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw.index_bias, 0xFFFFFFFF, NULL);
1442 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
1443 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw.max_index, 0xFFFFFFFF, NULL);
1444 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw.min_index, 0xFFFFFFFF, NULL);
1445 r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
1446 r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
1447
1448 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1449 float offset_units = rctx->rasterizer->offset_units;
1450 unsigned offset_db_fmt_cntl = 0, depth;
1451
1452 switch (rctx->framebuffer.zsbuf->texture->format) {
1453 case PIPE_FORMAT_Z24X8_UNORM:
1454 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1455 depth = -24;
1456 offset_units *= 2.0f;
1457 break;
1458 case PIPE_FORMAT_Z32_FLOAT:
1459 depth = -23;
1460 offset_units *= 1.0f;
1461 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1462 break;
1463 case PIPE_FORMAT_Z16_UNORM:
1464 depth = -16;
1465 offset_units *= 4.0f;
1466 break;
1467 default:
1468 return;
1469 }
1470 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1471 r600_pipe_state_add_reg(&vgt,
1472 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1473 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1474 r600_pipe_state_add_reg(&vgt,
1475 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1476 fui(offset_units), 0xFFFFFFFF, NULL);
1477 r600_pipe_state_add_reg(&vgt,
1478 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1479 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1480 r600_pipe_state_add_reg(&vgt,
1481 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1482 fui(offset_units), 0xFFFFFFFF, NULL);
1483 r600_pipe_state_add_reg(&vgt,
1484 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1485 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1486 }
1487 r600_context_pipe_state_set(&rctx->ctx, &vgt);
1488
1489 rdraw.vgt_num_indices = draw.count;
1490 rdraw.vgt_num_instances = 1;
1491 rdraw.vgt_index_type = vgt_dma_index_type;
1492 rdraw.vgt_draw_initiator = vgt_draw_initiator;
1493 rdraw.indices = NULL;
1494 if (draw.index_buffer) {
1495 rbuffer = (struct r600_resource*)draw.index_buffer;
1496 rdraw.indices = rbuffer->bo;
1497 rdraw.indices_bo_offset = draw.index_buffer_offset;
1498 }
1499 evergreen_context_draw(&rctx->ctx, &rdraw);
1500
1501 if (translate)
1502 r600_end_vertex_translate(rctx);
1503
1504 pipe_resource_reference(&draw.index_buffer, NULL);
1505 }
1506
1507 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1508 {
1509 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1510 struct r600_pipe_state *rstate = &shader->rstate;
1511 struct r600_shader *rshader = &shader->shader;
1512 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
1513 int pos_index = -1, face_index = -1;
1514 int ninterp = 0;
1515 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1516 unsigned spi_baryc_cntl;
1517
1518 /* clear previous register */
1519 rstate->nregs = 0;
1520
1521 for (i = 0; i < rshader->ninput; i++) {
1522 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
1523 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1524 POSITION goes via GPRs from the SC so isn't counted */
1525 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1526 pos_index = i;
1527 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1528 face_index = i;
1529 else {
1530 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
1531 rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1532 ninterp++;
1533 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1534 have_linear = TRUE;
1535 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1536 have_perspective = TRUE;
1537 if (rshader->input[i].centroid)
1538 have_centroid = TRUE;
1539 }
1540 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
1541 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
1542 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
1543 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
1544 }
1545 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
1546 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
1547 tmp |= S_028644_PT_SPRITE_TEX(1);
1548 }
1549 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
1550 }
1551 for (i = 0; i < rshader->noutput; i++) {
1552 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1553 r600_pipe_state_add_reg(rstate,
1554 R_02880C_DB_SHADER_CONTROL,
1555 S_02880C_Z_EXPORT_ENABLE(1),
1556 S_02880C_Z_EXPORT_ENABLE(1), NULL);
1557 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1558 r600_pipe_state_add_reg(rstate,
1559 R_02880C_DB_SHADER_CONTROL,
1560 S_02880C_STENCIL_EXPORT_ENABLE(1),
1561 S_02880C_STENCIL_EXPORT_ENABLE(1), NULL);
1562 }
1563
1564 exports_ps = 0;
1565 num_cout = 0;
1566 for (i = 0; i < rshader->noutput; i++) {
1567 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1568 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1569 exports_ps |= 1;
1570 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1571 num_cout++;
1572 }
1573 }
1574 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1575 if (!exports_ps) {
1576 /* always at least export 1 component per pixel */
1577 exports_ps = 2;
1578 }
1579
1580 if (ninterp == 0) {
1581 ninterp = 1;
1582 have_perspective = TRUE;
1583 }
1584
1585 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
1586 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
1587 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
1588 spi_input_z = 0;
1589 if (pos_index != -1) {
1590 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
1591 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1592 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
1593 spi_input_z |= 1;
1594 }
1595
1596 spi_ps_in_control_1 = 0;
1597 if (face_index != -1) {
1598 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1599 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1600 }
1601
1602 spi_baryc_cntl = 0;
1603 if (have_perspective)
1604 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
1605 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
1606 if (have_linear)
1607 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
1608 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
1609
1610 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1611 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1612 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1613 spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1614 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
1615 0, 0xFFFFFFFF, NULL);
1616 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1617 r600_pipe_state_add_reg(rstate,
1618 R_0286E0_SPI_BARYC_CNTL,
1619 spi_baryc_cntl,
1620 0xFFFFFFFF, NULL);
1621
1622 r600_pipe_state_add_reg(rstate,
1623 R_028840_SQ_PGM_START_PS,
1624 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1625 r600_pipe_state_add_reg(rstate,
1626 R_028844_SQ_PGM_RESOURCES_PS,
1627 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1628 S_028844_PRIME_CACHE_ON_DRAW(1) |
1629 S_028844_STACK_SIZE(rshader->bc.nstack),
1630 0xFFFFFFFF, NULL);
1631 r600_pipe_state_add_reg(rstate,
1632 R_028848_SQ_PGM_RESOURCES_2_PS,
1633 0x0, 0xFFFFFFFF, NULL);
1634 r600_pipe_state_add_reg(rstate,
1635 R_02884C_SQ_PGM_EXPORTS_PS,
1636 exports_ps, 0xFFFFFFFF, NULL);
1637
1638 if (rshader->uses_kill) {
1639 /* only set some bits here, the other bits are set in the dsa state */
1640 r600_pipe_state_add_reg(rstate,
1641 R_02880C_DB_SHADER_CONTROL,
1642 S_02880C_KILL_ENABLE(1),
1643 S_02880C_KILL_ENABLE(1), NULL);
1644 }
1645
1646 r600_pipe_state_add_reg(rstate,
1647 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
1648 0xFFFFFFFF, NULL);
1649 }
1650
1651 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1652 {
1653 struct r600_pipe_state *rstate = &shader->rstate;
1654 struct r600_shader *rshader = &shader->shader;
1655 unsigned spi_vs_out_id[10];
1656 unsigned i, tmp;
1657
1658 /* clear previous register */
1659 rstate->nregs = 0;
1660
1661 /* so far never got proper semantic id from tgsi */
1662 for (i = 0; i < 10; i++) {
1663 spi_vs_out_id[i] = 0;
1664 }
1665 for (i = 0; i < 32; i++) {
1666 tmp = i << ((i & 3) * 8);
1667 spi_vs_out_id[i / 4] |= tmp;
1668 }
1669 for (i = 0; i < 10; i++) {
1670 r600_pipe_state_add_reg(rstate,
1671 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1672 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1673 }
1674
1675 r600_pipe_state_add_reg(rstate,
1676 R_0286C4_SPI_VS_OUT_CONFIG,
1677 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1678 0xFFFFFFFF, NULL);
1679 r600_pipe_state_add_reg(rstate,
1680 R_028860_SQ_PGM_RESOURCES_VS,
1681 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1682 S_028860_STACK_SIZE(rshader->bc.nstack),
1683 0xFFFFFFFF, NULL);
1684 r600_pipe_state_add_reg(rstate,
1685 R_028864_SQ_PGM_RESOURCES_2_VS,
1686 0x0, 0xFFFFFFFF, NULL);
1687 r600_pipe_state_add_reg(rstate,
1688 R_0288A8_SQ_PGM_RESOURCES_FS,
1689 0x00000000, 0xFFFFFFFF, NULL);
1690 r600_pipe_state_add_reg(rstate,
1691 R_02885C_SQ_PGM_START_VS,
1692 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1693 r600_pipe_state_add_reg(rstate,
1694 R_0288A4_SQ_PGM_START_FS,
1695 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1696
1697 r600_pipe_state_add_reg(rstate,
1698 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1699 0xFFFFFFFF, NULL);
1700 }
1701
1702 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1703 {
1704 struct pipe_depth_stencil_alpha_state dsa;
1705 struct r600_pipe_state *rstate;
1706
1707 memset(&dsa, 0, sizeof(dsa));
1708
1709 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1710 r600_pipe_state_add_reg(rstate,
1711 R_02880C_DB_SHADER_CONTROL,
1712 0x0,
1713 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1714 r600_pipe_state_add_reg(rstate,
1715 R_028000_DB_RENDER_CONTROL,
1716 S_028000_DEPTH_COPY_ENABLE(1) |
1717 S_028000_STENCIL_COPY_ENABLE(1) |
1718 S_028000_COPY_CENTROID(1),
1719 S_028000_DEPTH_COPY_ENABLE(1) |
1720 S_028000_STENCIL_COPY_ENABLE(1) |
1721 S_028000_COPY_CENTROID(1), NULL);
1722 return rstate;
1723 }