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r600g: put the rest of CS overflow checks in r600_need_cs_space
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_blitter.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
38 #include "util/u_surface.h"
39 #include "util/u_pack_color.h"
40 #include "util/u_memory.h"
41 #include "util/u_inlines.h"
42 #include "util/u_framebuffer.h"
43 #include "pipebuffer/pb_buffer.h"
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "r600_formats.h"
50
51 static uint32_t r600_translate_blend_function(int blend_func)
52 {
53 switch (blend_func) {
54 case PIPE_BLEND_ADD:
55 return V_028780_COMB_DST_PLUS_SRC;
56 case PIPE_BLEND_SUBTRACT:
57 return V_028780_COMB_SRC_MINUS_DST;
58 case PIPE_BLEND_REVERSE_SUBTRACT:
59 return V_028780_COMB_DST_MINUS_SRC;
60 case PIPE_BLEND_MIN:
61 return V_028780_COMB_MIN_DST_SRC;
62 case PIPE_BLEND_MAX:
63 return V_028780_COMB_MAX_DST_SRC;
64 default:
65 R600_ERR("Unknown blend function %d\n", blend_func);
66 assert(0);
67 break;
68 }
69 return 0;
70 }
71
72 static uint32_t r600_translate_blend_factor(int blend_fact)
73 {
74 switch (blend_fact) {
75 case PIPE_BLENDFACTOR_ONE:
76 return V_028780_BLEND_ONE;
77 case PIPE_BLENDFACTOR_SRC_COLOR:
78 return V_028780_BLEND_SRC_COLOR;
79 case PIPE_BLENDFACTOR_SRC_ALPHA:
80 return V_028780_BLEND_SRC_ALPHA;
81 case PIPE_BLENDFACTOR_DST_ALPHA:
82 return V_028780_BLEND_DST_ALPHA;
83 case PIPE_BLENDFACTOR_DST_COLOR:
84 return V_028780_BLEND_DST_COLOR;
85 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
86 return V_028780_BLEND_SRC_ALPHA_SATURATE;
87 case PIPE_BLENDFACTOR_CONST_COLOR:
88 return V_028780_BLEND_CONST_COLOR;
89 case PIPE_BLENDFACTOR_CONST_ALPHA:
90 return V_028780_BLEND_CONST_ALPHA;
91 case PIPE_BLENDFACTOR_ZERO:
92 return V_028780_BLEND_ZERO;
93 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
94 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
95 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
96 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
97 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
98 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
99 case PIPE_BLENDFACTOR_INV_DST_COLOR:
100 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
101 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
102 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
103 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
104 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
105 case PIPE_BLENDFACTOR_SRC1_COLOR:
106 return V_028780_BLEND_SRC1_COLOR;
107 case PIPE_BLENDFACTOR_SRC1_ALPHA:
108 return V_028780_BLEND_SRC1_ALPHA;
109 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
110 return V_028780_BLEND_INV_SRC1_COLOR;
111 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
112 return V_028780_BLEND_INV_SRC1_ALPHA;
113 default:
114 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
115 assert(0);
116 break;
117 }
118 return 0;
119 }
120
121 static uint32_t r600_translate_stencil_op(int s_op)
122 {
123 switch (s_op) {
124 case PIPE_STENCIL_OP_KEEP:
125 return V_028800_STENCIL_KEEP;
126 case PIPE_STENCIL_OP_ZERO:
127 return V_028800_STENCIL_ZERO;
128 case PIPE_STENCIL_OP_REPLACE:
129 return V_028800_STENCIL_REPLACE;
130 case PIPE_STENCIL_OP_INCR:
131 return V_028800_STENCIL_INCR;
132 case PIPE_STENCIL_OP_DECR:
133 return V_028800_STENCIL_DECR;
134 case PIPE_STENCIL_OP_INCR_WRAP:
135 return V_028800_STENCIL_INCR_WRAP;
136 case PIPE_STENCIL_OP_DECR_WRAP:
137 return V_028800_STENCIL_DECR_WRAP;
138 case PIPE_STENCIL_OP_INVERT:
139 return V_028800_STENCIL_INVERT;
140 default:
141 R600_ERR("Unknown stencil op %d", s_op);
142 assert(0);
143 break;
144 }
145 return 0;
146 }
147
148 static uint32_t r600_translate_fill(uint32_t func)
149 {
150 switch(func) {
151 case PIPE_POLYGON_MODE_FILL:
152 return 2;
153 case PIPE_POLYGON_MODE_LINE:
154 return 1;
155 case PIPE_POLYGON_MODE_POINT:
156 return 0;
157 default:
158 assert(0);
159 return 0;
160 }
161 }
162
163 /* translates straight */
164 static uint32_t r600_translate_ds_func(int func)
165 {
166 return func;
167 }
168
169 static unsigned r600_tex_wrap(unsigned wrap)
170 {
171 switch (wrap) {
172 default:
173 case PIPE_TEX_WRAP_REPEAT:
174 return V_03C000_SQ_TEX_WRAP;
175 case PIPE_TEX_WRAP_CLAMP:
176 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
177 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
178 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
179 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
180 return V_03C000_SQ_TEX_CLAMP_BORDER;
181 case PIPE_TEX_WRAP_MIRROR_REPEAT:
182 return V_03C000_SQ_TEX_MIRROR;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP:
184 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
186 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
187 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
188 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
189 }
190 }
191
192 static unsigned r600_tex_filter(unsigned filter)
193 {
194 switch (filter) {
195 default:
196 case PIPE_TEX_FILTER_NEAREST:
197 return V_03C000_SQ_TEX_XY_FILTER_POINT;
198 case PIPE_TEX_FILTER_LINEAR:
199 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
200 }
201 }
202
203 static unsigned r600_tex_mipfilter(unsigned filter)
204 {
205 switch (filter) {
206 case PIPE_TEX_MIPFILTER_NEAREST:
207 return V_03C000_SQ_TEX_Z_FILTER_POINT;
208 case PIPE_TEX_MIPFILTER_LINEAR:
209 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
210 default:
211 case PIPE_TEX_MIPFILTER_NONE:
212 return V_03C000_SQ_TEX_Z_FILTER_NONE;
213 }
214 }
215
216 static unsigned r600_tex_compare(unsigned compare)
217 {
218 switch (compare) {
219 default:
220 case PIPE_FUNC_NEVER:
221 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
222 case PIPE_FUNC_LESS:
223 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
224 case PIPE_FUNC_EQUAL:
225 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
226 case PIPE_FUNC_LEQUAL:
227 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
228 case PIPE_FUNC_GREATER:
229 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
230 case PIPE_FUNC_NOTEQUAL:
231 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
232 case PIPE_FUNC_GEQUAL:
233 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
234 case PIPE_FUNC_ALWAYS:
235 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
236 }
237 }
238
239 static unsigned r600_tex_dim(unsigned dim)
240 {
241 switch (dim) {
242 default:
243 case PIPE_TEXTURE_1D:
244 return V_030000_SQ_TEX_DIM_1D;
245 case PIPE_TEXTURE_1D_ARRAY:
246 return V_030000_SQ_TEX_DIM_1D_ARRAY;
247 case PIPE_TEXTURE_2D:
248 case PIPE_TEXTURE_RECT:
249 return V_030000_SQ_TEX_DIM_2D;
250 case PIPE_TEXTURE_2D_ARRAY:
251 return V_030000_SQ_TEX_DIM_2D_ARRAY;
252 case PIPE_TEXTURE_3D:
253 return V_030000_SQ_TEX_DIM_3D;
254 case PIPE_TEXTURE_CUBE:
255 return V_030000_SQ_TEX_DIM_CUBEMAP;
256 }
257 }
258
259 static uint32_t r600_translate_dbformat(enum pipe_format format)
260 {
261 switch (format) {
262 case PIPE_FORMAT_Z16_UNORM:
263 return V_028040_Z_16;
264 case PIPE_FORMAT_Z24X8_UNORM:
265 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
266 return V_028040_Z_24;
267 case PIPE_FORMAT_Z32_FLOAT:
268 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
269 return V_028040_Z_32_FLOAT;
270 default:
271 return ~0U;
272 }
273 }
274
275 static uint32_t r600_translate_colorswap(enum pipe_format format)
276 {
277 switch (format) {
278 /* 8-bit buffers. */
279 case PIPE_FORMAT_L4A4_UNORM:
280 case PIPE_FORMAT_A4R4_UNORM:
281 return V_028C70_SWAP_ALT;
282
283 case PIPE_FORMAT_A8_UNORM:
284 case PIPE_FORMAT_A8_UINT:
285 case PIPE_FORMAT_A8_SINT:
286 case PIPE_FORMAT_R4A4_UNORM:
287 return V_028C70_SWAP_ALT_REV;
288 case PIPE_FORMAT_I8_UNORM:
289 case PIPE_FORMAT_L8_UNORM:
290 case PIPE_FORMAT_I8_UINT:
291 case PIPE_FORMAT_I8_SINT:
292 case PIPE_FORMAT_L8_UINT:
293 case PIPE_FORMAT_L8_SINT:
294 case PIPE_FORMAT_L8_SRGB:
295 case PIPE_FORMAT_R8_UNORM:
296 case PIPE_FORMAT_R8_SNORM:
297 return V_028C70_SWAP_STD;
298
299 /* 16-bit buffers. */
300 case PIPE_FORMAT_B5G6R5_UNORM:
301 return V_028C70_SWAP_STD_REV;
302
303 case PIPE_FORMAT_B5G5R5A1_UNORM:
304 case PIPE_FORMAT_B5G5R5X1_UNORM:
305 return V_028C70_SWAP_ALT;
306
307 case PIPE_FORMAT_B4G4R4A4_UNORM:
308 case PIPE_FORMAT_B4G4R4X4_UNORM:
309 return V_028C70_SWAP_ALT;
310
311 case PIPE_FORMAT_Z16_UNORM:
312 return V_028C70_SWAP_STD;
313
314 case PIPE_FORMAT_L8A8_UNORM:
315 case PIPE_FORMAT_L8A8_UINT:
316 case PIPE_FORMAT_L8A8_SINT:
317 case PIPE_FORMAT_L8A8_SRGB:
318 return V_028C70_SWAP_ALT;
319 case PIPE_FORMAT_R8G8_UNORM:
320 case PIPE_FORMAT_R8G8_UINT:
321 case PIPE_FORMAT_R8G8_SINT:
322 return V_028C70_SWAP_STD;
323
324 case PIPE_FORMAT_R16_UNORM:
325 case PIPE_FORMAT_R16_UINT:
326 case PIPE_FORMAT_R16_SINT:
327 case PIPE_FORMAT_R16_FLOAT:
328 return V_028C70_SWAP_STD;
329
330 /* 32-bit buffers. */
331 case PIPE_FORMAT_A8B8G8R8_SRGB:
332 return V_028C70_SWAP_STD_REV;
333 case PIPE_FORMAT_B8G8R8A8_SRGB:
334 return V_028C70_SWAP_ALT;
335
336 case PIPE_FORMAT_B8G8R8A8_UNORM:
337 case PIPE_FORMAT_B8G8R8X8_UNORM:
338 return V_028C70_SWAP_ALT;
339
340 case PIPE_FORMAT_A8R8G8B8_UNORM:
341 case PIPE_FORMAT_X8R8G8B8_UNORM:
342 return V_028C70_SWAP_ALT_REV;
343 case PIPE_FORMAT_R8G8B8A8_SNORM:
344 case PIPE_FORMAT_R8G8B8A8_UNORM:
345 case PIPE_FORMAT_R8G8B8A8_SSCALED:
346 case PIPE_FORMAT_R8G8B8A8_USCALED:
347 case PIPE_FORMAT_R8G8B8A8_SINT:
348 case PIPE_FORMAT_R8G8B8A8_UINT:
349 case PIPE_FORMAT_R8G8B8X8_UNORM:
350 return V_028C70_SWAP_STD;
351
352 case PIPE_FORMAT_A8B8G8R8_UNORM:
353 case PIPE_FORMAT_X8B8G8R8_UNORM:
354 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
355 return V_028C70_SWAP_STD_REV;
356
357 case PIPE_FORMAT_Z24X8_UNORM:
358 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
359 return V_028C70_SWAP_STD;
360
361 case PIPE_FORMAT_X8Z24_UNORM:
362 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
363 return V_028C70_SWAP_STD;
364
365 case PIPE_FORMAT_R10G10B10A2_UNORM:
366 case PIPE_FORMAT_R10G10B10X2_SNORM:
367 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
368 return V_028C70_SWAP_STD;
369
370 case PIPE_FORMAT_B10G10R10A2_UNORM:
371 return V_028C70_SWAP_ALT;
372
373 case PIPE_FORMAT_R11G11B10_FLOAT:
374 case PIPE_FORMAT_R32_FLOAT:
375 case PIPE_FORMAT_R32_UINT:
376 case PIPE_FORMAT_R32_SINT:
377 case PIPE_FORMAT_Z32_FLOAT:
378 case PIPE_FORMAT_R16G16_FLOAT:
379 case PIPE_FORMAT_R16G16_UNORM:
380 case PIPE_FORMAT_R16G16_UINT:
381 case PIPE_FORMAT_R16G16_SINT:
382 return V_028C70_SWAP_STD;
383
384 /* 64-bit buffers. */
385 case PIPE_FORMAT_R32G32_FLOAT:
386 case PIPE_FORMAT_R32G32_UINT:
387 case PIPE_FORMAT_R32G32_SINT:
388 case PIPE_FORMAT_R16G16B16A16_UNORM:
389 case PIPE_FORMAT_R16G16B16A16_SNORM:
390 case PIPE_FORMAT_R16G16B16A16_USCALED:
391 case PIPE_FORMAT_R16G16B16A16_SSCALED:
392 case PIPE_FORMAT_R16G16B16A16_UINT:
393 case PIPE_FORMAT_R16G16B16A16_SINT:
394 case PIPE_FORMAT_R16G16B16A16_FLOAT:
395 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
396
397 /* 128-bit buffers. */
398 case PIPE_FORMAT_R32G32B32A32_FLOAT:
399 case PIPE_FORMAT_R32G32B32A32_SNORM:
400 case PIPE_FORMAT_R32G32B32A32_UNORM:
401 case PIPE_FORMAT_R32G32B32A32_SSCALED:
402 case PIPE_FORMAT_R32G32B32A32_USCALED:
403 case PIPE_FORMAT_R32G32B32A32_SINT:
404 case PIPE_FORMAT_R32G32B32A32_UINT:
405 return V_028C70_SWAP_STD;
406 default:
407 R600_ERR("unsupported colorswap format %d\n", format);
408 return ~0U;
409 }
410 return ~0U;
411 }
412
413 static uint32_t r600_translate_colorformat(enum pipe_format format)
414 {
415 switch (format) {
416 /* 8-bit buffers. */
417 case PIPE_FORMAT_L4A4_UNORM:
418 case PIPE_FORMAT_R4A4_UNORM:
419 case PIPE_FORMAT_A4R4_UNORM:
420 return V_028C70_COLOR_4_4;
421
422 case PIPE_FORMAT_A8_UNORM:
423 case PIPE_FORMAT_A8_UINT:
424 case PIPE_FORMAT_A8_SINT:
425 case PIPE_FORMAT_I8_UNORM:
426 case PIPE_FORMAT_I8_UINT:
427 case PIPE_FORMAT_I8_SINT:
428 case PIPE_FORMAT_L8_UNORM:
429 case PIPE_FORMAT_L8_UINT:
430 case PIPE_FORMAT_L8_SINT:
431 case PIPE_FORMAT_L8_SRGB:
432 case PIPE_FORMAT_R8_UNORM:
433 case PIPE_FORMAT_R8_SNORM:
434 case PIPE_FORMAT_R8_UINT:
435 case PIPE_FORMAT_R8_SINT:
436 return V_028C70_COLOR_8;
437
438 /* 16-bit buffers. */
439 case PIPE_FORMAT_B5G6R5_UNORM:
440 return V_028C70_COLOR_5_6_5;
441
442 case PIPE_FORMAT_B5G5R5A1_UNORM:
443 case PIPE_FORMAT_B5G5R5X1_UNORM:
444 return V_028C70_COLOR_1_5_5_5;
445
446 case PIPE_FORMAT_B4G4R4A4_UNORM:
447 case PIPE_FORMAT_B4G4R4X4_UNORM:
448 return V_028C70_COLOR_4_4_4_4;
449
450 case PIPE_FORMAT_Z16_UNORM:
451 return V_028C70_COLOR_16;
452
453 case PIPE_FORMAT_L8A8_UNORM:
454 case PIPE_FORMAT_L8A8_UINT:
455 case PIPE_FORMAT_L8A8_SINT:
456 case PIPE_FORMAT_L8A8_SRGB:
457 case PIPE_FORMAT_R8G8_UNORM:
458 case PIPE_FORMAT_R8G8_UINT:
459 case PIPE_FORMAT_R8G8_SINT:
460 return V_028C70_COLOR_8_8;
461
462 case PIPE_FORMAT_R16_UNORM:
463 case PIPE_FORMAT_R16_UINT:
464 case PIPE_FORMAT_R16_SINT:
465 return V_028C70_COLOR_16;
466
467 case PIPE_FORMAT_R16_FLOAT:
468 return V_028C70_COLOR_16_FLOAT;
469
470 /* 32-bit buffers. */
471 case PIPE_FORMAT_A8B8G8R8_SRGB:
472 case PIPE_FORMAT_A8B8G8R8_UNORM:
473 case PIPE_FORMAT_A8R8G8B8_UNORM:
474 case PIPE_FORMAT_B8G8R8A8_SRGB:
475 case PIPE_FORMAT_B8G8R8A8_UNORM:
476 case PIPE_FORMAT_B8G8R8X8_UNORM:
477 case PIPE_FORMAT_R8G8B8A8_SNORM:
478 case PIPE_FORMAT_R8G8B8A8_UNORM:
479 case PIPE_FORMAT_R8G8B8X8_UNORM:
480 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
481 case PIPE_FORMAT_X8B8G8R8_UNORM:
482 case PIPE_FORMAT_X8R8G8B8_UNORM:
483 case PIPE_FORMAT_R8G8B8_UNORM:
484 case PIPE_FORMAT_R8G8B8A8_SSCALED:
485 case PIPE_FORMAT_R8G8B8A8_USCALED:
486 case PIPE_FORMAT_R8G8B8A8_SINT:
487 case PIPE_FORMAT_R8G8B8A8_UINT:
488 return V_028C70_COLOR_8_8_8_8;
489
490 case PIPE_FORMAT_R10G10B10A2_UNORM:
491 case PIPE_FORMAT_R10G10B10X2_SNORM:
492 case PIPE_FORMAT_B10G10R10A2_UNORM:
493 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
494 return V_028C70_COLOR_2_10_10_10;
495
496 case PIPE_FORMAT_Z24X8_UNORM:
497 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
498 return V_028C70_COLOR_8_24;
499
500 case PIPE_FORMAT_X8Z24_UNORM:
501 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
502 return V_028C70_COLOR_24_8;
503
504 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
505 return V_028C70_COLOR_X24_8_32_FLOAT;
506
507 case PIPE_FORMAT_R32_FLOAT:
508 case PIPE_FORMAT_Z32_FLOAT:
509 return V_028C70_COLOR_32_FLOAT;
510
511 case PIPE_FORMAT_R16G16_FLOAT:
512 return V_028C70_COLOR_16_16_FLOAT;
513
514 case PIPE_FORMAT_R16G16_SSCALED:
515 case PIPE_FORMAT_R16G16_UNORM:
516 case PIPE_FORMAT_R16G16_UINT:
517 case PIPE_FORMAT_R16G16_SINT:
518 return V_028C70_COLOR_16_16;
519
520 case PIPE_FORMAT_R11G11B10_FLOAT:
521 return V_028C70_COLOR_10_11_11_FLOAT;
522
523 /* 64-bit buffers. */
524 case PIPE_FORMAT_R16G16B16_USCALED:
525 case PIPE_FORMAT_R16G16B16_SSCALED:
526 case PIPE_FORMAT_R16G16B16A16_UINT:
527 case PIPE_FORMAT_R16G16B16A16_SINT:
528 case PIPE_FORMAT_R16G16B16A16_USCALED:
529 case PIPE_FORMAT_R16G16B16A16_SSCALED:
530 case PIPE_FORMAT_R16G16B16A16_UNORM:
531 case PIPE_FORMAT_R16G16B16A16_SNORM:
532 return V_028C70_COLOR_16_16_16_16;
533
534 case PIPE_FORMAT_R16G16B16_FLOAT:
535 case PIPE_FORMAT_R16G16B16A16_FLOAT:
536 return V_028C70_COLOR_16_16_16_16_FLOAT;
537
538 case PIPE_FORMAT_R32G32_FLOAT:
539 return V_028C70_COLOR_32_32_FLOAT;
540
541 case PIPE_FORMAT_R32G32_USCALED:
542 case PIPE_FORMAT_R32G32_SSCALED:
543 case PIPE_FORMAT_R32G32_SINT:
544 case PIPE_FORMAT_R32G32_UINT:
545 return V_028C70_COLOR_32_32;
546
547 /* 96-bit buffers. */
548 case PIPE_FORMAT_R32G32B32_FLOAT:
549 return V_028C70_COLOR_32_32_32_FLOAT;
550
551 /* 128-bit buffers. */
552 case PIPE_FORMAT_R32G32B32A32_SNORM:
553 case PIPE_FORMAT_R32G32B32A32_UNORM:
554 case PIPE_FORMAT_R32G32B32A32_SSCALED:
555 case PIPE_FORMAT_R32G32B32A32_USCALED:
556 case PIPE_FORMAT_R32G32B32A32_SINT:
557 case PIPE_FORMAT_R32G32B32A32_UINT:
558 return V_028C70_COLOR_32_32_32_32;
559 case PIPE_FORMAT_R32G32B32A32_FLOAT:
560 return V_028C70_COLOR_32_32_32_32_FLOAT;
561
562 /* YUV buffers. */
563 case PIPE_FORMAT_UYVY:
564 case PIPE_FORMAT_YUYV:
565 default:
566 return ~0U; /* Unsupported. */
567 }
568 }
569
570 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
571 {
572 if (R600_BIG_ENDIAN) {
573 switch(colorformat) {
574 case V_028C70_COLOR_4_4:
575 return ENDIAN_NONE;
576
577 /* 8-bit buffers. */
578 case V_028C70_COLOR_8:
579 return ENDIAN_NONE;
580
581 /* 16-bit buffers. */
582 case V_028C70_COLOR_5_6_5:
583 case V_028C70_COLOR_1_5_5_5:
584 case V_028C70_COLOR_4_4_4_4:
585 case V_028C70_COLOR_16:
586 case V_028C70_COLOR_8_8:
587 return ENDIAN_8IN16;
588
589 /* 32-bit buffers. */
590 case V_028C70_COLOR_8_8_8_8:
591 case V_028C70_COLOR_2_10_10_10:
592 case V_028C70_COLOR_8_24:
593 case V_028C70_COLOR_24_8:
594 case V_028C70_COLOR_32_FLOAT:
595 case V_028C70_COLOR_16_16_FLOAT:
596 case V_028C70_COLOR_16_16:
597 return ENDIAN_8IN32;
598
599 /* 64-bit buffers. */
600 case V_028C70_COLOR_16_16_16_16:
601 case V_028C70_COLOR_16_16_16_16_FLOAT:
602 return ENDIAN_8IN16;
603
604 case V_028C70_COLOR_32_32_FLOAT:
605 case V_028C70_COLOR_32_32:
606 case V_028C70_COLOR_X24_8_32_FLOAT:
607 return ENDIAN_8IN32;
608
609 /* 96-bit buffers. */
610 case V_028C70_COLOR_32_32_32_FLOAT:
611 /* 128-bit buffers. */
612 case V_028C70_COLOR_32_32_32_32_FLOAT:
613 case V_028C70_COLOR_32_32_32_32:
614 return ENDIAN_8IN32;
615 default:
616 return ENDIAN_NONE; /* Unsupported. */
617 }
618 } else {
619 return ENDIAN_NONE;
620 }
621 }
622
623 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
624 {
625 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
626 }
627
628 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
629 {
630 return r600_translate_colorformat(format) != ~0U &&
631 r600_translate_colorswap(format) != ~0U;
632 }
633
634 static bool r600_is_zs_format_supported(enum pipe_format format)
635 {
636 return r600_translate_dbformat(format) != ~0U;
637 }
638
639 boolean evergreen_is_format_supported(struct pipe_screen *screen,
640 enum pipe_format format,
641 enum pipe_texture_target target,
642 unsigned sample_count,
643 unsigned usage)
644 {
645 unsigned retval = 0;
646
647 if (target >= PIPE_MAX_TEXTURE_TYPES) {
648 R600_ERR("r600: unsupported texture type %d\n", target);
649 return FALSE;
650 }
651
652 if (!util_format_is_supported(format, usage))
653 return FALSE;
654
655 /* Multisample */
656 if (sample_count > 1)
657 return FALSE;
658
659 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
660 r600_is_sampler_format_supported(screen, format)) {
661 retval |= PIPE_BIND_SAMPLER_VIEW;
662 }
663
664 if ((usage & (PIPE_BIND_RENDER_TARGET |
665 PIPE_BIND_DISPLAY_TARGET |
666 PIPE_BIND_SCANOUT |
667 PIPE_BIND_SHARED)) &&
668 r600_is_colorbuffer_format_supported(format)) {
669 retval |= usage &
670 (PIPE_BIND_RENDER_TARGET |
671 PIPE_BIND_DISPLAY_TARGET |
672 PIPE_BIND_SCANOUT |
673 PIPE_BIND_SHARED);
674 }
675
676 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
677 r600_is_zs_format_supported(format)) {
678 retval |= PIPE_BIND_DEPTH_STENCIL;
679 }
680
681 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
682 r600_is_vertex_format_supported(format)) {
683 retval |= PIPE_BIND_VERTEX_BUFFER;
684 }
685
686 if (usage & PIPE_BIND_TRANSFER_READ)
687 retval |= PIPE_BIND_TRANSFER_READ;
688 if (usage & PIPE_BIND_TRANSFER_WRITE)
689 retval |= PIPE_BIND_TRANSFER_WRITE;
690
691 return retval == usage;
692 }
693
694 static void evergreen_set_blend_color(struct pipe_context *ctx,
695 const struct pipe_blend_color *state)
696 {
697 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
698 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
699
700 if (rstate == NULL)
701 return;
702
703 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
704 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL, 0);
705 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL, 0);
706 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL, 0);
707 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL, 0);
708
709 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
710 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
711 r600_context_pipe_state_set(&rctx->ctx, rstate);
712 }
713
714 static void *evergreen_create_blend_state(struct pipe_context *ctx,
715 const struct pipe_blend_state *state)
716 {
717 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
718 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
719 struct r600_pipe_state *rstate;
720 u32 color_control, target_mask;
721 /* FIXME there is more then 8 framebuffer */
722 unsigned blend_cntl[8];
723
724 if (blend == NULL) {
725 return NULL;
726 }
727
728 rstate = &blend->rstate;
729
730 rstate->id = R600_PIPE_STATE_BLEND;
731
732 target_mask = 0;
733 color_control = S_028808_MODE(1);
734 if (state->logicop_enable) {
735 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
736 } else {
737 color_control |= (0xcc << 16);
738 }
739 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
740 if (state->independent_blend_enable) {
741 for (int i = 0; i < 8; i++) {
742 target_mask |= (state->rt[i].colormask << (4 * i));
743 }
744 } else {
745 for (int i = 0; i < 8; i++) {
746 target_mask |= (state->rt[0].colormask << (4 * i));
747 }
748 }
749 blend->cb_target_mask = target_mask;
750
751 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
752 color_control, 0xFFFFFFFD, NULL, 0);
753
754 if (rctx->chip_class != CAYMAN)
755 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
756 else {
757 r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
758 r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
759 }
760
761 for (int i = 0; i < 8; i++) {
762 /* state->rt entries > 0 only written if independent blending */
763 const int j = state->independent_blend_enable ? i : 0;
764
765 unsigned eqRGB = state->rt[j].rgb_func;
766 unsigned srcRGB = state->rt[j].rgb_src_factor;
767 unsigned dstRGB = state->rt[j].rgb_dst_factor;
768 unsigned eqA = state->rt[j].alpha_func;
769 unsigned srcA = state->rt[j].alpha_src_factor;
770 unsigned dstA = state->rt[j].alpha_dst_factor;
771
772 blend_cntl[i] = 0;
773 if (!state->rt[j].blend_enable)
774 continue;
775
776 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
777 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
778 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
779 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
780
781 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
782 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
783 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
784 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
785 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
786 }
787 }
788 for (int i = 0; i < 8; i++) {
789 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL, 0);
790 }
791
792 return rstate;
793 }
794
795 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
796 const struct pipe_depth_stencil_alpha_state *state)
797 {
798 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
799 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
800 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
801 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
802 struct r600_pipe_state *rstate;
803
804 if (dsa == NULL) {
805 return NULL;
806 }
807
808 rstate = &dsa->rstate;
809
810 rstate->id = R600_PIPE_STATE_DSA;
811 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
812 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
813 stencil_ref_mask = 0;
814 stencil_ref_mask_bf = 0;
815 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
816 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
817 S_028800_ZFUNC(state->depth.func);
818
819 /* stencil */
820 if (state->stencil[0].enabled) {
821 db_depth_control |= S_028800_STENCIL_ENABLE(1);
822 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
823 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
824 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
825 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
826
827
828 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
829 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
830 if (state->stencil[1].enabled) {
831 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
832 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
833 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
834 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
835 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
836 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
837 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
838 }
839 }
840
841 /* alpha */
842 alpha_test_control = 0;
843 alpha_ref = 0;
844 if (state->alpha.enabled) {
845 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
846 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
847 alpha_ref = fui(state->alpha.ref_value);
848 }
849 dsa->alpha_ref = alpha_ref;
850
851 /* misc */
852 db_render_control = 0;
853 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
854 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
855 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
856 /* TODO db_render_override depends on query */
857 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
858 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
859 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
860 r600_pipe_state_add_reg(rstate,
861 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
862 0xFFFFFFFF & C_028430_STENCILREF, NULL, 0);
863 r600_pipe_state_add_reg(rstate,
864 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
865 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL, 0);
866 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
867 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL, 0);
868 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
869 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
870 * evergreen_pipe_shader_ps().*/
871 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL, 0);
872 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL, 0);
873 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL, 0);
874 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL, 0);
875 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL, 0);
876 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL, 0);
877 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL, 0);
878
879 return rstate;
880 }
881
882 static void *evergreen_create_rs_state(struct pipe_context *ctx,
883 const struct pipe_rasterizer_state *state)
884 {
885 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
886 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
887 struct r600_pipe_state *rstate;
888 unsigned tmp;
889 unsigned prov_vtx = 1, polygon_dual_mode;
890 unsigned clip_rule;
891
892 if (rs == NULL) {
893 return NULL;
894 }
895
896 rstate = &rs->rstate;
897 rs->clamp_vertex_color = state->clamp_vertex_color;
898 rs->clamp_fragment_color = state->clamp_fragment_color;
899 rs->flatshade = state->flatshade;
900 rs->sprite_coord_enable = state->sprite_coord_enable;
901
902 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
903
904 /* offset */
905 rs->offset_units = state->offset_units;
906 rs->offset_scale = state->offset_scale * 12.0f;
907
908 rstate->id = R600_PIPE_STATE_RASTERIZER;
909 if (state->flatshade_first)
910 prov_vtx = 0;
911 tmp = S_0286D4_FLAT_SHADE_ENA(state->flatshade);
912 if (state->sprite_coord_enable) {
913 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
914 S_0286D4_PNT_SPRITE_OVRD_X(2) |
915 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
916 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
917 S_0286D4_PNT_SPRITE_OVRD_W(1);
918 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
919 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
920 }
921 }
922 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL, 0);
923
924 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
925 state->fill_back != PIPE_POLYGON_MODE_FILL);
926 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
927 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
928 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
929 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
930 S_028814_FACE(!state->front_ccw) |
931 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
932 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
933 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
934 S_028814_POLY_MODE(polygon_dual_mode) |
935 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
936 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL, 0);
937 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
938 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
939 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL, 0);
940 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
941 /* point size 12.4 fixed point */
942 tmp = (unsigned)(state->point_size * 8.0);
943 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
944 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL, 0);
945
946 tmp = (unsigned)state->line_width * 8;
947 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
948
949 if (state->line_stipple_enable) {
950 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE,
951 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
952 S_028A0C_REPEAT_COUNT(state->line_stipple_factor),
953 0x9FFFFFFF, NULL, 0);
954 }
955
956 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
957 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
958 0xFFFFFFFF, NULL, 0);
959
960 if (rctx->chip_class == CAYMAN) {
961 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
962 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
963 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
964 0xFFFFFFFF, NULL, 0);
965 r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
966 r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
967 r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
968 r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
969
970
971 } else {
972 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
973
974 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
975 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
976 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
977 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
978
979 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
980 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
981 0xFFFFFFFF, NULL, 0);
982 }
983 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), 0xFFFFFFFF, NULL, 0);
984 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0);
985 return rstate;
986 }
987
988 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
989 const struct pipe_sampler_state *state)
990 {
991 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
992 union util_color uc;
993 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
994
995 if (rstate == NULL) {
996 return NULL;
997 }
998
999 rstate->id = R600_PIPE_STATE_SAMPLER;
1000 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1001 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1002 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1003 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1004 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1005 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1006 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1007 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1008 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1009 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1010 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL, 0);
1011 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1012 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
1013 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
1014 0xFFFFFFFF, NULL, 0);
1015 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
1016 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
1017 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
1018 S_03C008_TYPE(1),
1019 0xFFFFFFFF, NULL, 0);
1020
1021 if (uc.ui) {
1022 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), 0xFFFFFFFF, NULL, 0);
1023 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), 0xFFFFFFFF, NULL, 0);
1024 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), 0xFFFFFFFF, NULL, 0);
1025 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), 0xFFFFFFFF, NULL, 0);
1026 }
1027 return rstate;
1028 }
1029
1030 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
1031 struct pipe_resource *texture,
1032 const struct pipe_sampler_view *state)
1033 {
1034 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1035 struct r600_pipe_resource_state *rstate;
1036 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1037 unsigned format, endian;
1038 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1039 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1040 unsigned height, depth;
1041
1042 if (view == NULL)
1043 return NULL;
1044 rstate = &view->state;
1045
1046 /* initialize base object */
1047 view->base = *state;
1048 view->base.texture = NULL;
1049 pipe_reference(NULL, &texture->reference);
1050 view->base.texture = texture;
1051 view->base.reference.count = 1;
1052 view->base.context = ctx;
1053
1054 swizzle[0] = state->swizzle_r;
1055 swizzle[1] = state->swizzle_g;
1056 swizzle[2] = state->swizzle_b;
1057 swizzle[3] = state->swizzle_a;
1058
1059 format = r600_translate_texformat(ctx->screen, state->format,
1060 swizzle,
1061 &word4, &yuv_format);
1062 if (format == ~0) {
1063 format = 0;
1064 }
1065
1066 if (tmp->depth && !tmp->is_flushing_texture) {
1067 r600_texture_depth_flush(ctx, texture, TRUE);
1068 tmp = tmp->flushed_depth_texture;
1069 }
1070
1071 endian = r600_colorformat_endian_swap(format);
1072
1073 height = texture->height0;
1074 depth = texture->depth0;
1075
1076 pitch = align(tmp->pitch_in_blocks[0] *
1077 util_format_get_blockwidth(state->format), 8);
1078 array_mode = tmp->array_mode[0];
1079 tile_type = tmp->tile_type;
1080
1081 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1082 height = 1;
1083 depth = texture->array_size;
1084 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1085 depth = texture->array_size;
1086 }
1087
1088 rstate->bo[0] = &tmp->resource;
1089 rstate->bo[1] = &tmp->resource;
1090 rstate->bo_usage[0] = RADEON_USAGE_READ;
1091 rstate->bo_usage[1] = RADEON_USAGE_READ;
1092
1093 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1094 S_030000_PITCH((pitch / 8) - 1) |
1095 S_030000_NON_DISP_TILING_ORDER(tile_type) |
1096 S_030000_TEX_WIDTH(texture->width0 - 1));
1097 rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1098 S_030004_TEX_DEPTH(depth - 1) |
1099 S_030004_ARRAY_MODE(array_mode));
1100 rstate->val[2] = tmp->offset[0] >> 8;
1101 rstate->val[3] = tmp->offset[1] >> 8;
1102 rstate->val[4] = (word4 |
1103 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1104 S_030010_ENDIAN_SWAP(endian) |
1105 S_030010_BASE_LEVEL(state->u.tex.first_level));
1106 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1107 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1108 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1109 rstate->val[6] = (S_030018_MAX_ANISO(4 /* max 16 samples */));
1110 rstate->val[7] = (S_03001C_DATA_FORMAT(format) |
1111 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE));
1112
1113 return &view->base;
1114 }
1115
1116 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1117 struct pipe_sampler_view **views)
1118 {
1119 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1120 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1121
1122 for (int i = 0; i < count; i++) {
1123 if (resource[i]) {
1124 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
1125 i + R600_MAX_CONST_BUFFERS);
1126 }
1127 }
1128 }
1129
1130 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1131 struct pipe_sampler_view **views)
1132 {
1133 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1134 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1135 int i;
1136 int has_depth = 0;
1137
1138 for (i = 0; i < count; i++) {
1139 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1140 if (resource[i]) {
1141 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1142 has_depth = 1;
1143 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
1144 i + R600_MAX_CONST_BUFFERS);
1145 } else
1146 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1147 i + R600_MAX_CONST_BUFFERS);
1148
1149 pipe_sampler_view_reference(
1150 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1151 views[i]);
1152 } else {
1153 if (resource[i]) {
1154 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1155 has_depth = 1;
1156 }
1157 }
1158 }
1159 for (i = count; i < NUM_TEX_UNITS; i++) {
1160 if (rctx->ps_samplers.views[i]) {
1161 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1162 i + R600_MAX_CONST_BUFFERS);
1163 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1164 }
1165 }
1166 rctx->have_depth_texture = has_depth;
1167 rctx->ps_samplers.n_views = count;
1168 }
1169
1170 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1171 {
1172 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1173 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1174
1175
1176 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1177 rctx->ps_samplers.n_samplers = count;
1178
1179 for (int i = 0; i < count; i++) {
1180 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
1181 }
1182 }
1183
1184 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1185 {
1186 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1187 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1188
1189 for (int i = 0; i < count; i++) {
1190 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
1191 }
1192 }
1193
1194 static void evergreen_set_clip_state(struct pipe_context *ctx,
1195 const struct pipe_clip_state *state)
1196 {
1197 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1198 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1199
1200 if (rstate == NULL)
1201 return;
1202
1203 rctx->clip = *state;
1204 rstate->id = R600_PIPE_STATE_CLIP;
1205 for (int i = 0; i < state->nr; i++) {
1206 r600_pipe_state_add_reg(rstate,
1207 R_0285BC_PA_CL_UCP0_X + i * 16,
1208 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL, 0);
1209 r600_pipe_state_add_reg(rstate,
1210 R_0285C0_PA_CL_UCP0_Y + i * 16,
1211 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL, 0);
1212 r600_pipe_state_add_reg(rstate,
1213 R_0285C4_PA_CL_UCP0_Z + i * 16,
1214 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL, 0);
1215 r600_pipe_state_add_reg(rstate,
1216 R_0285C8_PA_CL_UCP0_W + i * 16,
1217 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL, 0);
1218 }
1219 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1220 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
1221 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
1222 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL, 0);
1223
1224 free(rctx->states[R600_PIPE_STATE_CLIP]);
1225 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1226 r600_context_pipe_state_set(&rctx->ctx, rstate);
1227 }
1228
1229 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1230 const struct pipe_poly_stipple *state)
1231 {
1232 }
1233
1234 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1235 {
1236 }
1237
1238 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1239 const struct pipe_scissor_state *state)
1240 {
1241 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1242 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1243 u32 tl, br;
1244
1245 if (rstate == NULL)
1246 return;
1247
1248 rstate->id = R600_PIPE_STATE_SCISSOR;
1249 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1250 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1251 r600_pipe_state_add_reg(rstate,
1252 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1253 0xFFFFFFFF, NULL, 0);
1254 r600_pipe_state_add_reg(rstate,
1255 R_028214_PA_SC_CLIPRECT_0_BR, br,
1256 0xFFFFFFFF, NULL, 0);
1257 r600_pipe_state_add_reg(rstate,
1258 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1259 0xFFFFFFFF, NULL, 0);
1260 r600_pipe_state_add_reg(rstate,
1261 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1262 0xFFFFFFFF, NULL, 0);
1263 r600_pipe_state_add_reg(rstate,
1264 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1265 0xFFFFFFFF, NULL, 0);
1266 r600_pipe_state_add_reg(rstate,
1267 R_028224_PA_SC_CLIPRECT_2_BR, br,
1268 0xFFFFFFFF, NULL, 0);
1269 r600_pipe_state_add_reg(rstate,
1270 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1271 0xFFFFFFFF, NULL, 0);
1272 r600_pipe_state_add_reg(rstate,
1273 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1274 0xFFFFFFFF, NULL, 0);
1275
1276 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1277 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1278 r600_context_pipe_state_set(&rctx->ctx, rstate);
1279 }
1280
1281 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
1282 const struct pipe_stencil_ref *state)
1283 {
1284 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1285 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1286 u32 tmp;
1287
1288 if (rstate == NULL)
1289 return;
1290
1291 rctx->stencil_ref = *state;
1292 rstate->id = R600_PIPE_STATE_STENCIL_REF;
1293 tmp = S_028430_STENCILREF(state->ref_value[0]);
1294 r600_pipe_state_add_reg(rstate,
1295 R_028430_DB_STENCILREFMASK, tmp,
1296 ~C_028430_STENCILREF, NULL, 0);
1297 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1298 r600_pipe_state_add_reg(rstate,
1299 R_028434_DB_STENCILREFMASK_BF, tmp,
1300 ~C_028434_STENCILREF_BF, NULL, 0);
1301
1302 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1303 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1304 r600_context_pipe_state_set(&rctx->ctx, rstate);
1305 }
1306
1307 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1308 const struct pipe_viewport_state *state)
1309 {
1310 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1311 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1312
1313 if (rstate == NULL)
1314 return;
1315
1316 rctx->viewport = *state;
1317 rstate->id = R600_PIPE_STATE_VIEWPORT;
1318 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
1319 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1320 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL, 0);
1321 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL, 0);
1322 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL, 0);
1323 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL, 0);
1324 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL, 0);
1325 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL, 0);
1326 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL, 0);
1327
1328 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1329 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1330 r600_context_pipe_state_set(&rctx->ctx, rstate);
1331 }
1332
1333 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1334 const struct pipe_framebuffer_state *state, int cb)
1335 {
1336 struct r600_resource_texture *rtex;
1337 struct r600_surface *surf;
1338 unsigned level = state->cbufs[cb]->u.tex.level;
1339 unsigned pitch, slice;
1340 unsigned color_info;
1341 unsigned format, swap, ntype, endian;
1342 unsigned offset;
1343 unsigned tile_type;
1344 const struct util_format_description *desc;
1345 int i;
1346 unsigned blend_clamp = 0, blend_bypass = 0;
1347
1348 surf = (struct r600_surface *)state->cbufs[cb];
1349 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1350
1351 if (rtex->depth)
1352 rctx->have_depth_fb = TRUE;
1353
1354 if (rtex->depth && !rtex->is_flushing_texture) {
1355 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1356 rtex = rtex->flushed_depth_texture;
1357 }
1358
1359 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1360 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
1361 level, state->cbufs[cb]->u.tex.first_layer);
1362 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1363 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1364 desc = util_format_description(surf->base.format);
1365 for (i = 0; i < 4; i++) {
1366 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1367 break;
1368 }
1369 }
1370
1371 ntype = V_028C70_NUMBER_UNORM;
1372 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1373 ntype = V_028C70_NUMBER_SRGB;
1374 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1375 if (desc->channel[i].normalized)
1376 ntype = V_028C70_NUMBER_SNORM;
1377 else if (desc->channel[i].pure_integer)
1378 ntype = V_028C70_NUMBER_SINT;
1379 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1380 if (desc->channel[i].normalized)
1381 ntype = V_028C70_NUMBER_UNORM;
1382 else if (desc->channel[i].pure_integer)
1383 ntype = V_028C70_NUMBER_UINT;
1384 }
1385
1386 format = r600_translate_colorformat(surf->base.format);
1387 swap = r600_translate_colorswap(surf->base.format);
1388 if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1389 endian = ENDIAN_NONE;
1390 } else {
1391 endian = r600_colorformat_endian_swap(format);
1392 }
1393
1394 /* blend clamp should be set for all NORM/SRGB types */
1395 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1396 ntype == V_028C70_NUMBER_SRGB)
1397 blend_clamp = 1;
1398
1399 /* set blend bypass according to docs if SINT/UINT or
1400 8/24 COLOR variants */
1401 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1402 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1403 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1404 blend_clamp = 0;
1405 blend_bypass = 1;
1406 }
1407
1408 color_info = S_028C70_FORMAT(format) |
1409 S_028C70_COMP_SWAP(swap) |
1410 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
1411 S_028C70_BLEND_CLAMP(blend_clamp) |
1412 S_028C70_BLEND_BYPASS(blend_bypass) |
1413 S_028C70_NUMBER_TYPE(ntype) |
1414 S_028C70_ENDIAN(endian);
1415
1416 /* EXPORT_NORM is an optimzation that can be enabled for better
1417 * performance in certain cases.
1418 * EXPORT_NORM can be enabled if:
1419 * - 11-bit or smaller UNORM/SNORM/SRGB
1420 * - 16-bit or smaller FLOAT
1421 */
1422 /* FIXME: This should probably be the same for all CBs if we want
1423 * useful alpha tests. */
1424 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1425 ((desc->channel[i].size < 12 &&
1426 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1427 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1428 (desc->channel[i].size < 17 &&
1429 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1430 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1431 rctx->export_16bpc = true;
1432 } else {
1433 rctx->export_16bpc = false;
1434 }
1435 rctx->alpha_ref_dirty = true;
1436
1437 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1438 tile_type = rtex->tile_type;
1439 } else /* workaround for linear buffers */
1440 tile_type = 1;
1441
1442 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1443 r600_pipe_state_add_reg(rstate,
1444 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1445 offset >> 8, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1446 r600_pipe_state_add_reg(rstate,
1447 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1448 0x0, 0xFFFFFFFF, NULL, 0);
1449 r600_pipe_state_add_reg(rstate,
1450 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1451 color_info, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1452 r600_pipe_state_add_reg(rstate,
1453 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1454 S_028C64_PITCH_TILE_MAX(pitch),
1455 0xFFFFFFFF, NULL, 0);
1456 r600_pipe_state_add_reg(rstate,
1457 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1458 S_028C68_SLICE_TILE_MAX(slice),
1459 0xFFFFFFFF, NULL, 0);
1460 r600_pipe_state_add_reg(rstate,
1461 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1462 0x00000000, 0xFFFFFFFF, NULL, 0);
1463 r600_pipe_state_add_reg(rstate,
1464 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1465 S_028C74_NON_DISP_TILING_ORDER(tile_type),
1466 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1467 }
1468
1469 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1470 const struct pipe_framebuffer_state *state)
1471 {
1472 struct r600_resource_texture *rtex;
1473 struct r600_surface *surf;
1474 unsigned level, first_layer, pitch, slice, format, offset, array_mode;
1475
1476 if (state->zsbuf == NULL)
1477 return;
1478
1479 surf = (struct r600_surface *)state->zsbuf;
1480 level = surf->base.u.tex.level;
1481 rtex = (struct r600_resource_texture*)surf->base.texture;
1482
1483 /* XXX remove this once tiling is properly supported */
1484 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1485 V_028C70_ARRAY_1D_TILED_THIN1;
1486
1487 first_layer = surf->base.u.tex.first_layer;
1488 offset = r600_texture_get_offset(rtex, level, first_layer);
1489 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1490 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1491 format = r600_translate_dbformat(rtex->real_format);
1492
1493 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1494 offset >> 8, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1495 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1496 offset >> 8, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1497 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0);
1498
1499 if (rtex->stencil) {
1500 uint32_t stencil_offset =
1501 r600_texture_get_offset(rtex->stencil, level, first_layer);
1502
1503 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1504 stencil_offset >> 8, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1505 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1506 stencil_offset >> 8, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1507 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1508 1, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1509 } else {
1510 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1511 0, 0xFFFFFFFF, NULL, RADEON_USAGE_READWRITE);
1512 }
1513
1514 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
1515 S_028040_ARRAY_MODE(array_mode) | S_028040_FORMAT(format),
1516 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1517 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1518 S_028058_PITCH_TILE_MAX(pitch),
1519 0xFFFFFFFF, NULL, 0);
1520 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1521 S_02805C_SLICE_TILE_MAX(slice),
1522 0xFFFFFFFF, NULL, 0);
1523 }
1524
1525 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1526 const struct pipe_framebuffer_state *state)
1527 {
1528 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1529 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1530 u32 shader_mask, tl, br, target_mask;
1531 int tl_x, tl_y, br_x, br_y;
1532
1533 if (rstate == NULL)
1534 return;
1535
1536 evergreen_context_flush_dest_caches(&rctx->ctx);
1537 rctx->ctx.num_dest_buffers = state->nr_cbufs;
1538
1539 /* unreference old buffer and reference new one */
1540 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1541
1542 util_copy_framebuffer_state(&rctx->framebuffer, state);
1543
1544 /* build states */
1545 rctx->have_depth_fb = 0;
1546 rctx->nr_cbufs = state->nr_cbufs;
1547 for (int i = 0; i < state->nr_cbufs; i++) {
1548 evergreen_cb(rctx, rstate, state, i);
1549 }
1550 if (state->zsbuf) {
1551 evergreen_db(rctx, rstate, state);
1552 rctx->ctx.num_dest_buffers++;
1553 }
1554
1555 target_mask = 0x00000000;
1556 target_mask = 0xFFFFFFFF;
1557 shader_mask = 0;
1558 for (int i = 0; i < state->nr_cbufs; i++) {
1559 target_mask ^= 0xf << (i * 4);
1560 shader_mask |= 0xf << (i * 4);
1561 }
1562 tl_x = 0;
1563 tl_y = 0;
1564 br_x = state->width;
1565 br_y = state->height;
1566 /* EG hw workaround */
1567 if (br_x == 0)
1568 tl_x = 1;
1569 if (br_y == 0)
1570 tl_y = 1;
1571 /* cayman hw workaround */
1572 if (rctx->chip_class == CAYMAN) {
1573 if (br_x == 1 && br_y == 1)
1574 br_x = 2;
1575 }
1576 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1577 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1578
1579 r600_pipe_state_add_reg(rstate,
1580 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1581 0xFFFFFFFF, NULL, 0);
1582 r600_pipe_state_add_reg(rstate,
1583 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1584 0xFFFFFFFF, NULL, 0);
1585 r600_pipe_state_add_reg(rstate,
1586 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1587 0xFFFFFFFF, NULL, 0);
1588 r600_pipe_state_add_reg(rstate,
1589 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1590 0xFFFFFFFF, NULL, 0);
1591 r600_pipe_state_add_reg(rstate,
1592 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1593 0xFFFFFFFF, NULL, 0);
1594 r600_pipe_state_add_reg(rstate,
1595 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1596 0xFFFFFFFF, NULL, 0);
1597 r600_pipe_state_add_reg(rstate,
1598 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1599 0xFFFFFFFF, NULL, 0);
1600 r600_pipe_state_add_reg(rstate,
1601 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1602 0xFFFFFFFF, NULL, 0);
1603 r600_pipe_state_add_reg(rstate,
1604 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1605 0xFFFFFFFF, NULL, 0);
1606 r600_pipe_state_add_reg(rstate,
1607 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1608 0xFFFFFFFF, NULL, 0);
1609
1610 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1611 0x00000000, target_mask, NULL, 0);
1612 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1613 shader_mask, 0xFFFFFFFF, NULL, 0);
1614
1615
1616 if (rctx->chip_class == CAYMAN) {
1617 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1618 0x00000000, 0xFFFFFFFF, NULL, 0);
1619 } else {
1620 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1621 0x00000000, 0xFFFFFFFF, NULL, 0);
1622 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1623 0x00000000, 0xFFFFFFFF, NULL, 0);
1624 }
1625
1626 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1627 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1628 r600_context_pipe_state_set(&rctx->ctx, rstate);
1629
1630 if (state->zsbuf) {
1631 evergreen_polygon_offset_update(rctx);
1632 }
1633 }
1634
1635 static void evergreen_texture_barrier(struct pipe_context *ctx)
1636 {
1637 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1638
1639 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1640 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1641 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1642 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1643 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
1644 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
1645 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
1646 }
1647
1648 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
1649 {
1650 rctx->context.create_blend_state = evergreen_create_blend_state;
1651 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1652 rctx->context.create_fs_state = r600_create_shader_state;
1653 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1654 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1655 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1656 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1657 rctx->context.create_vs_state = r600_create_shader_state;
1658 rctx->context.bind_blend_state = r600_bind_blend_state;
1659 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1660 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1661 rctx->context.bind_fs_state = r600_bind_ps_shader;
1662 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1663 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1664 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1665 rctx->context.bind_vs_state = r600_bind_vs_shader;
1666 rctx->context.delete_blend_state = r600_delete_state;
1667 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1668 rctx->context.delete_fs_state = r600_delete_ps_shader;
1669 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1670 rctx->context.delete_sampler_state = r600_delete_state;
1671 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1672 rctx->context.delete_vs_state = r600_delete_vs_shader;
1673 rctx->context.set_blend_color = evergreen_set_blend_color;
1674 rctx->context.set_clip_state = evergreen_set_clip_state;
1675 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1676 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1677 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1678 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1679 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1680 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1681 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1682 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1683 rctx->context.set_index_buffer = r600_set_index_buffer;
1684 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1685 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1686 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1687 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1688 rctx->context.texture_barrier = evergreen_texture_barrier;
1689 }
1690
1691 static void cayman_init_config(struct r600_pipe_context *rctx)
1692 {
1693 struct r600_pipe_state *rstate = &rctx->config;
1694 unsigned tmp;
1695
1696 tmp = 0x00000000;
1697 tmp |= S_008C00_EXPORT_SRC_C(1);
1698 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
1699
1700 /* always set the temp clauses */
1701 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), 0xFFFFFFFF, NULL, 0);
1702 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL, 0);
1703 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL, 0);
1704 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL, 0);
1705
1706 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL, 0);
1707
1708 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1709 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1710 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
1711 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
1712 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL, 0);
1713 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL, 0);
1714 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
1715 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
1716 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1717 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1718 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1719 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1720 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL, 0);
1721 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
1722 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
1723 r600_pipe_state_add_reg(rstate, R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), 0xFFFFFFFF, NULL, 0);
1724 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL, 0);
1725 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL, 0);
1726 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL, 0);
1727
1728 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL, 0);
1729 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL, 0);
1730 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL, 0);
1731 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL, 0);
1732 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL, 0);
1733 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL, 0);
1734 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL, 0);
1735 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL, 0);
1736 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL, 0);
1737 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL, 0);
1738 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL, 0);
1739 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL, 0);
1740 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL, 0);
1741 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL, 0);
1742 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL, 0);
1743 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL, 0);
1744 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL, 0);
1745 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL, 0);
1746 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL, 0);
1747 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL, 0);
1748 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL, 0);
1749 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL, 0);
1750 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL, 0);
1751 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL, 0);
1752 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL, 0);
1753 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL, 0);
1754 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL, 0);
1755 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL, 0);
1756 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL, 0);
1757 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL, 0);
1758 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL, 0);
1759 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL, 0);
1760
1761 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1762
1763 r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, 0xffffffff, NULL, 0);
1764 r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, 0xffffffff, NULL, 0);
1765
1766 r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, 0xFFFFFFFF, NULL, 0);
1767 r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0xFFFFFFFF, NULL, 0);
1768
1769 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, 0xFFFFFFFF, NULL, 0);
1770 r600_context_pipe_state_set(&rctx->ctx, rstate);
1771 }
1772
1773 void evergreen_init_config(struct r600_pipe_context *rctx)
1774 {
1775 struct r600_pipe_state *rstate = &rctx->config;
1776 int ps_prio;
1777 int vs_prio;
1778 int gs_prio;
1779 int es_prio;
1780 int hs_prio, cs_prio, ls_prio;
1781 int num_ps_gprs;
1782 int num_vs_gprs;
1783 int num_gs_gprs;
1784 int num_es_gprs;
1785 int num_hs_gprs;
1786 int num_ls_gprs;
1787 int num_temp_gprs;
1788 int num_ps_threads;
1789 int num_vs_threads;
1790 int num_gs_threads;
1791 int num_es_threads;
1792 int num_hs_threads;
1793 int num_ls_threads;
1794 int num_ps_stack_entries;
1795 int num_vs_stack_entries;
1796 int num_gs_stack_entries;
1797 int num_es_stack_entries;
1798 int num_hs_stack_entries;
1799 int num_ls_stack_entries;
1800 enum radeon_family family;
1801 unsigned tmp;
1802
1803 family = rctx->family;
1804
1805 if (rctx->chip_class == CAYMAN) {
1806 cayman_init_config(rctx);
1807 return;
1808 }
1809
1810 ps_prio = 0;
1811 vs_prio = 1;
1812 gs_prio = 2;
1813 es_prio = 3;
1814 hs_prio = 0;
1815 ls_prio = 0;
1816 cs_prio = 0;
1817
1818 switch (family) {
1819 case CHIP_CEDAR:
1820 default:
1821 num_ps_gprs = 93;
1822 num_vs_gprs = 46;
1823 num_temp_gprs = 4;
1824 num_gs_gprs = 31;
1825 num_es_gprs = 31;
1826 num_hs_gprs = 23;
1827 num_ls_gprs = 23;
1828 num_ps_threads = 96;
1829 num_vs_threads = 16;
1830 num_gs_threads = 16;
1831 num_es_threads = 16;
1832 num_hs_threads = 16;
1833 num_ls_threads = 16;
1834 num_ps_stack_entries = 42;
1835 num_vs_stack_entries = 42;
1836 num_gs_stack_entries = 42;
1837 num_es_stack_entries = 42;
1838 num_hs_stack_entries = 42;
1839 num_ls_stack_entries = 42;
1840 break;
1841 case CHIP_REDWOOD:
1842 num_ps_gprs = 93;
1843 num_vs_gprs = 46;
1844 num_temp_gprs = 4;
1845 num_gs_gprs = 31;
1846 num_es_gprs = 31;
1847 num_hs_gprs = 23;
1848 num_ls_gprs = 23;
1849 num_ps_threads = 128;
1850 num_vs_threads = 20;
1851 num_gs_threads = 20;
1852 num_es_threads = 20;
1853 num_hs_threads = 20;
1854 num_ls_threads = 20;
1855 num_ps_stack_entries = 42;
1856 num_vs_stack_entries = 42;
1857 num_gs_stack_entries = 42;
1858 num_es_stack_entries = 42;
1859 num_hs_stack_entries = 42;
1860 num_ls_stack_entries = 42;
1861 break;
1862 case CHIP_JUNIPER:
1863 num_ps_gprs = 93;
1864 num_vs_gprs = 46;
1865 num_temp_gprs = 4;
1866 num_gs_gprs = 31;
1867 num_es_gprs = 31;
1868 num_hs_gprs = 23;
1869 num_ls_gprs = 23;
1870 num_ps_threads = 128;
1871 num_vs_threads = 20;
1872 num_gs_threads = 20;
1873 num_es_threads = 20;
1874 num_hs_threads = 20;
1875 num_ls_threads = 20;
1876 num_ps_stack_entries = 85;
1877 num_vs_stack_entries = 85;
1878 num_gs_stack_entries = 85;
1879 num_es_stack_entries = 85;
1880 num_hs_stack_entries = 85;
1881 num_ls_stack_entries = 85;
1882 break;
1883 case CHIP_CYPRESS:
1884 case CHIP_HEMLOCK:
1885 num_ps_gprs = 93;
1886 num_vs_gprs = 46;
1887 num_temp_gprs = 4;
1888 num_gs_gprs = 31;
1889 num_es_gprs = 31;
1890 num_hs_gprs = 23;
1891 num_ls_gprs = 23;
1892 num_ps_threads = 128;
1893 num_vs_threads = 20;
1894 num_gs_threads = 20;
1895 num_es_threads = 20;
1896 num_hs_threads = 20;
1897 num_ls_threads = 20;
1898 num_ps_stack_entries = 85;
1899 num_vs_stack_entries = 85;
1900 num_gs_stack_entries = 85;
1901 num_es_stack_entries = 85;
1902 num_hs_stack_entries = 85;
1903 num_ls_stack_entries = 85;
1904 break;
1905 case CHIP_PALM:
1906 num_ps_gprs = 93;
1907 num_vs_gprs = 46;
1908 num_temp_gprs = 4;
1909 num_gs_gprs = 31;
1910 num_es_gprs = 31;
1911 num_hs_gprs = 23;
1912 num_ls_gprs = 23;
1913 num_ps_threads = 96;
1914 num_vs_threads = 16;
1915 num_gs_threads = 16;
1916 num_es_threads = 16;
1917 num_hs_threads = 16;
1918 num_ls_threads = 16;
1919 num_ps_stack_entries = 42;
1920 num_vs_stack_entries = 42;
1921 num_gs_stack_entries = 42;
1922 num_es_stack_entries = 42;
1923 num_hs_stack_entries = 42;
1924 num_ls_stack_entries = 42;
1925 break;
1926 case CHIP_SUMO:
1927 num_ps_gprs = 93;
1928 num_vs_gprs = 46;
1929 num_temp_gprs = 4;
1930 num_gs_gprs = 31;
1931 num_es_gprs = 31;
1932 num_hs_gprs = 23;
1933 num_ls_gprs = 23;
1934 num_ps_threads = 96;
1935 num_vs_threads = 25;
1936 num_gs_threads = 25;
1937 num_es_threads = 25;
1938 num_hs_threads = 25;
1939 num_ls_threads = 25;
1940 num_ps_stack_entries = 42;
1941 num_vs_stack_entries = 42;
1942 num_gs_stack_entries = 42;
1943 num_es_stack_entries = 42;
1944 num_hs_stack_entries = 42;
1945 num_ls_stack_entries = 42;
1946 break;
1947 case CHIP_SUMO2:
1948 num_ps_gprs = 93;
1949 num_vs_gprs = 46;
1950 num_temp_gprs = 4;
1951 num_gs_gprs = 31;
1952 num_es_gprs = 31;
1953 num_hs_gprs = 23;
1954 num_ls_gprs = 23;
1955 num_ps_threads = 96;
1956 num_vs_threads = 25;
1957 num_gs_threads = 25;
1958 num_es_threads = 25;
1959 num_hs_threads = 25;
1960 num_ls_threads = 25;
1961 num_ps_stack_entries = 85;
1962 num_vs_stack_entries = 85;
1963 num_gs_stack_entries = 85;
1964 num_es_stack_entries = 85;
1965 num_hs_stack_entries = 85;
1966 num_ls_stack_entries = 85;
1967 break;
1968 case CHIP_BARTS:
1969 num_ps_gprs = 93;
1970 num_vs_gprs = 46;
1971 num_temp_gprs = 4;
1972 num_gs_gprs = 31;
1973 num_es_gprs = 31;
1974 num_hs_gprs = 23;
1975 num_ls_gprs = 23;
1976 num_ps_threads = 128;
1977 num_vs_threads = 20;
1978 num_gs_threads = 20;
1979 num_es_threads = 20;
1980 num_hs_threads = 20;
1981 num_ls_threads = 20;
1982 num_ps_stack_entries = 85;
1983 num_vs_stack_entries = 85;
1984 num_gs_stack_entries = 85;
1985 num_es_stack_entries = 85;
1986 num_hs_stack_entries = 85;
1987 num_ls_stack_entries = 85;
1988 break;
1989 case CHIP_TURKS:
1990 num_ps_gprs = 93;
1991 num_vs_gprs = 46;
1992 num_temp_gprs = 4;
1993 num_gs_gprs = 31;
1994 num_es_gprs = 31;
1995 num_hs_gprs = 23;
1996 num_ls_gprs = 23;
1997 num_ps_threads = 128;
1998 num_vs_threads = 20;
1999 num_gs_threads = 20;
2000 num_es_threads = 20;
2001 num_hs_threads = 20;
2002 num_ls_threads = 20;
2003 num_ps_stack_entries = 42;
2004 num_vs_stack_entries = 42;
2005 num_gs_stack_entries = 42;
2006 num_es_stack_entries = 42;
2007 num_hs_stack_entries = 42;
2008 num_ls_stack_entries = 42;
2009 break;
2010 case CHIP_CAICOS:
2011 num_ps_gprs = 93;
2012 num_vs_gprs = 46;
2013 num_temp_gprs = 4;
2014 num_gs_gprs = 31;
2015 num_es_gprs = 31;
2016 num_hs_gprs = 23;
2017 num_ls_gprs = 23;
2018 num_ps_threads = 128;
2019 num_vs_threads = 10;
2020 num_gs_threads = 10;
2021 num_es_threads = 10;
2022 num_hs_threads = 10;
2023 num_ls_threads = 10;
2024 num_ps_stack_entries = 42;
2025 num_vs_stack_entries = 42;
2026 num_gs_stack_entries = 42;
2027 num_es_stack_entries = 42;
2028 num_hs_stack_entries = 42;
2029 num_ls_stack_entries = 42;
2030 break;
2031 }
2032
2033 tmp = 0x00000000;
2034 switch (family) {
2035 case CHIP_CEDAR:
2036 case CHIP_PALM:
2037 case CHIP_SUMO:
2038 case CHIP_SUMO2:
2039 case CHIP_CAICOS:
2040 break;
2041 default:
2042 tmp |= S_008C00_VC_ENABLE(1);
2043 break;
2044 }
2045 tmp |= S_008C00_EXPORT_SRC_C(1);
2046 tmp |= S_008C00_CS_PRIO(cs_prio);
2047 tmp |= S_008C00_LS_PRIO(ls_prio);
2048 tmp |= S_008C00_HS_PRIO(hs_prio);
2049 tmp |= S_008C00_PS_PRIO(ps_prio);
2050 tmp |= S_008C00_VS_PRIO(vs_prio);
2051 tmp |= S_008C00_GS_PRIO(gs_prio);
2052 tmp |= S_008C00_ES_PRIO(es_prio);
2053 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
2054
2055 /* enable dynamic GPR resource management */
2056 if (rctx->screen->info.drm_minor >= 7) {
2057 /* always set temp clauses */
2058 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
2059 S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), 0xFFFFFFFF, NULL, 0);
2060 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL, 0);
2061 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL, 0);
2062 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL, 0);
2063 r600_pipe_state_add_reg(rstate, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2064 S_028838_PS_GPRS(0x1e) |
2065 S_028838_VS_GPRS(0x1e) |
2066 S_028838_GS_GPRS(0x1e) |
2067 S_028838_ES_GPRS(0x1e) |
2068 S_028838_HS_GPRS(0x1e) |
2069 S_028838_LS_GPRS(0x1e), 0xFFFFFFFF, NULL, 0); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2070 } else {
2071 tmp = 0;
2072 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2073 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2074 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2075 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2076
2077 tmp = 0;
2078 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
2079 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2080 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2081
2082 tmp = 0;
2083 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2084 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2085 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL, 0);
2086 }
2087
2088 tmp = 0;
2089 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
2090 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2091 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2092 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2093 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2094
2095 tmp = 0;
2096 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
2097 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2098 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2099
2100 tmp = 0;
2101 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2102 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2103 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2104
2105 tmp = 0;
2106 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2107 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2108 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2109
2110 tmp = 0;
2111 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2112 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2113 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL, 0);
2114
2115 tmp = 0;
2116 tmp |= S_008E2C_NUM_PS_LDS(0x1000);
2117 tmp |= S_008E2C_NUM_LS_LDS(0x1000);
2118 r600_pipe_state_add_reg(rstate, R_008E2C_SQ_LDS_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL, 0);
2119
2120 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2121 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL, 0);
2122
2123 #if 0
2124 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL, 0);
2125
2126 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL, 0);
2127 #endif
2128 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL, 0);
2129
2130 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2131 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2132 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2133 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2134 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2135 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2136
2137 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2138 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL, 0);
2139 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL, 0);
2140 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL, 0);
2141
2142 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2143 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2144 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
2145 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
2146 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL, 0);
2147 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL, 0);
2148 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
2149 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
2150 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2151 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2152 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2153 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2154 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL, 0);
2155 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
2156 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
2157 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL, 0);
2158 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL, 0);
2159 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL, 0);
2160
2161 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL, 0);
2162 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL, 0);
2163 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL, 0);
2164 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL, 0);
2165 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL, 0);
2166 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL, 0);
2167 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL, 0);
2168 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL, 0);
2169 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL, 0);
2170 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL, 0);
2171 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL, 0);
2172 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL, 0);
2173 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL, 0);
2174 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL, 0);
2175 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL, 0);
2176 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL, 0);
2177 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL, 0);
2178 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL, 0);
2179 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL, 0);
2180 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL, 0);
2181 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL, 0);
2182 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL, 0);
2183 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL, 0);
2184 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL, 0);
2185 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL, 0);
2186 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL, 0);
2187 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL, 0);
2188 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL, 0);
2189 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL, 0);
2190 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL, 0);
2191 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL, 0);
2192 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL, 0);
2193
2194 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2195
2196 r600_context_pipe_state_set(&rctx->ctx, rstate);
2197 }
2198
2199 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
2200 {
2201 struct r600_pipe_state state;
2202
2203 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2204 state.nregs = 0;
2205 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2206 float offset_units = rctx->rasterizer->offset_units;
2207 unsigned offset_db_fmt_cntl = 0, depth;
2208
2209 switch (rctx->framebuffer.zsbuf->texture->format) {
2210 case PIPE_FORMAT_Z24X8_UNORM:
2211 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2212 depth = -24;
2213 offset_units *= 2.0f;
2214 break;
2215 case PIPE_FORMAT_Z32_FLOAT:
2216 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2217 depth = -23;
2218 offset_units *= 1.0f;
2219 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2220 break;
2221 case PIPE_FORMAT_Z16_UNORM:
2222 depth = -16;
2223 offset_units *= 4.0f;
2224 break;
2225 default:
2226 return;
2227 }
2228 /* FIXME some of those reg can be computed with cso */
2229 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2230 r600_pipe_state_add_reg(&state,
2231 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2232 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
2233 r600_pipe_state_add_reg(&state,
2234 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2235 fui(offset_units), 0xFFFFFFFF, NULL, 0);
2236 r600_pipe_state_add_reg(&state,
2237 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2238 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
2239 r600_pipe_state_add_reg(&state,
2240 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2241 fui(offset_units), 0xFFFFFFFF, NULL, 0);
2242 r600_pipe_state_add_reg(&state,
2243 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2244 offset_db_fmt_cntl, 0xFFFFFFFF, NULL, 0);
2245 r600_context_pipe_state_set(&rctx->ctx, &state);
2246 }
2247 }
2248
2249 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2250 {
2251 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2252 struct r600_pipe_state *rstate = &shader->rstate;
2253 struct r600_shader *rshader = &shader->shader;
2254 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2255 int pos_index = -1, face_index = -1;
2256 int ninterp = 0;
2257 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2258 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2259
2260 rstate->nregs = 0;
2261
2262 db_shader_control = 0;
2263 for (i = 0; i < rshader->ninput; i++) {
2264 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2265 POSITION goes via GPRs from the SC so isn't counted */
2266 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2267 pos_index = i;
2268 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2269 face_index = i;
2270 else {
2271 ninterp++;
2272 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2273 have_linear = TRUE;
2274 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2275 have_perspective = TRUE;
2276 if (rshader->input[i].centroid)
2277 have_centroid = TRUE;
2278 }
2279
2280 sid = rshader->input[i].spi_sid;
2281
2282 if (sid) {
2283
2284 tmp = S_028644_SEMANTIC(sid);
2285
2286 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
2287 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
2288 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
2289 tmp |= S_028644_FLAT_SHADE(1);
2290 }
2291
2292 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2293 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2294 tmp |= S_028644_PT_SPRITE_TEX(1);
2295 }
2296
2297 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2298 tmp, 0xFFFFFFFF, NULL, 0);
2299
2300 idx++;
2301 }
2302 }
2303
2304 for (i = 0; i < rshader->noutput; i++) {
2305 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2306 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2307 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2308 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2309 }
2310 if (rshader->uses_kill)
2311 db_shader_control |= S_02880C_KILL_ENABLE(1);
2312
2313 exports_ps = 0;
2314 num_cout = 0;
2315 for (i = 0; i < rshader->noutput; i++) {
2316 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2317 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2318 exports_ps |= 1;
2319 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2320 if (rshader->fs_write_all)
2321 num_cout = rshader->nr_cbufs;
2322 else
2323 num_cout++;
2324 }
2325 }
2326 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2327 if (!exports_ps) {
2328 /* always at least export 1 component per pixel */
2329 exports_ps = 2;
2330 }
2331
2332 if (ninterp == 0) {
2333 ninterp = 1;
2334 have_perspective = TRUE;
2335 }
2336
2337 if (!have_perspective && !have_linear)
2338 have_perspective = TRUE;
2339
2340 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2341 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2342 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2343 spi_input_z = 0;
2344 if (pos_index != -1) {
2345 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2346 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2347 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2348 spi_input_z |= 1;
2349 }
2350
2351 spi_ps_in_control_1 = 0;
2352 if (face_index != -1) {
2353 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2354 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2355 }
2356
2357 spi_baryc_cntl = 0;
2358 if (have_perspective)
2359 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2360 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2361 if (have_linear)
2362 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2363 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2364
2365 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2366 spi_ps_in_control_0, 0xFFFFFFFF, NULL, 0);
2367 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2368 spi_ps_in_control_1, 0xFFFFFFFF, NULL, 0);
2369 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2370 0, 0xFFFFFFFF, NULL, 0);
2371 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL, 0);
2372 r600_pipe_state_add_reg(rstate,
2373 R_0286E0_SPI_BARYC_CNTL,
2374 spi_baryc_cntl,
2375 0xFFFFFFFF, NULL, 0);
2376
2377 r600_pipe_state_add_reg(rstate,
2378 R_028840_SQ_PGM_START_PS,
2379 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2380 r600_pipe_state_add_reg(rstate,
2381 R_028844_SQ_PGM_RESOURCES_PS,
2382 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2383 S_028844_PRIME_CACHE_ON_DRAW(1) |
2384 S_028844_STACK_SIZE(rshader->bc.nstack),
2385 0xFFFFFFFF, NULL, 0);
2386 r600_pipe_state_add_reg(rstate,
2387 R_028848_SQ_PGM_RESOURCES_2_PS,
2388 0x0, 0xFFFFFFFF, NULL, 0);
2389 r600_pipe_state_add_reg(rstate,
2390 R_02884C_SQ_PGM_EXPORTS_PS,
2391 exports_ps, 0xFFFFFFFF, NULL, 0);
2392 /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */
2393 /* only set some bits here, the other bits are set in the dsa state */
2394 r600_pipe_state_add_reg(rstate,
2395 R_02880C_DB_SHADER_CONTROL,
2396 db_shader_control,
2397 S_02880C_Z_EXPORT_ENABLE(1) |
2398 S_02880C_STENCIL_EXPORT_ENABLE(1) |
2399 S_02880C_KILL_ENABLE(1),
2400 NULL, 0);
2401 r600_pipe_state_add_reg(rstate,
2402 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
2403 0xFFFFFFFF, NULL, 0);
2404
2405 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2406 }
2407
2408 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2409 {
2410 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2411 struct r600_pipe_state *rstate = &shader->rstate;
2412 struct r600_shader *rshader = &shader->shader;
2413 unsigned spi_vs_out_id[10] = {};
2414 unsigned i, tmp, nparams = 0;
2415
2416 /* clear previous register */
2417 rstate->nregs = 0;
2418
2419 for (i = 0; i < rshader->noutput; i++) {
2420 if (rshader->output[i].spi_sid) {
2421 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2422 spi_vs_out_id[nparams / 4] |= tmp;
2423 nparams++;
2424 }
2425 }
2426
2427 for (i = 0; i < 10; i++) {
2428 r600_pipe_state_add_reg(rstate,
2429 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2430 spi_vs_out_id[i], 0xFFFFFFFF, NULL, 0);
2431 }
2432
2433 /* Certain attributes (position, psize, etc.) don't count as params.
2434 * VS is required to export at least one param and r600_shader_from_tgsi()
2435 * takes care of adding a dummy export.
2436 */
2437 if (nparams < 1)
2438 nparams = 1;
2439
2440 r600_pipe_state_add_reg(rstate,
2441 R_0286C4_SPI_VS_OUT_CONFIG,
2442 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2443 0xFFFFFFFF, NULL, 0);
2444 r600_pipe_state_add_reg(rstate,
2445 R_028860_SQ_PGM_RESOURCES_VS,
2446 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2447 S_028860_STACK_SIZE(rshader->bc.nstack),
2448 0xFFFFFFFF, NULL, 0);
2449 r600_pipe_state_add_reg(rstate,
2450 R_028864_SQ_PGM_RESOURCES_2_VS,
2451 0x0, 0xFFFFFFFF, NULL, 0);
2452 r600_pipe_state_add_reg(rstate,
2453 R_02885C_SQ_PGM_START_VS,
2454 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2455
2456 r600_pipe_state_add_reg(rstate,
2457 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2458 0xFFFFFFFF, NULL, 0);
2459 }
2460
2461 void evergreen_fetch_shader(struct pipe_context *ctx,
2462 struct r600_vertex_element *ve)
2463 {
2464 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2465 struct r600_pipe_state *rstate = &ve->rstate;
2466 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2467 rstate->nregs = 0;
2468 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
2469 0x00000000, 0xFFFFFFFF, NULL, 0);
2470 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2471 0,
2472 0xFFFFFFFF, ve->fetch_shader, RADEON_USAGE_READ);
2473 }
2474
2475 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
2476 {
2477 struct pipe_depth_stencil_alpha_state dsa;
2478 struct r600_pipe_state *rstate;
2479
2480 memset(&dsa, 0, sizeof(dsa));
2481
2482 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2483 r600_pipe_state_add_reg(rstate,
2484 R_02880C_DB_SHADER_CONTROL,
2485 0x0,
2486 S_02880C_DUAL_EXPORT_ENABLE(1), NULL, 0);
2487 r600_pipe_state_add_reg(rstate,
2488 R_028000_DB_RENDER_CONTROL,
2489 S_028000_DEPTH_COPY_ENABLE(1) |
2490 S_028000_STENCIL_COPY_ENABLE(1) |
2491 S_028000_COPY_CENTROID(1),
2492 S_028000_DEPTH_COPY_ENABLE(1) |
2493 S_028000_STENCIL_COPY_ENABLE(1) |
2494 S_028000_COPY_CENTROID(1), NULL, 0);
2495 return rstate;
2496 }
2497
2498 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
2499 struct r600_pipe_resource_state *rstate)
2500 {
2501 rstate->id = R600_PIPE_STATE_RESOURCE;
2502
2503 rstate->val[0] = 0;
2504 rstate->bo[0] = NULL;
2505 rstate->val[1] = 0;
2506 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2507 rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2508 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2509 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2510 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2511 rstate->val[4] = 0;
2512 rstate->val[5] = 0;
2513 rstate->val[6] = 0;
2514 rstate->val[7] = 0xc0000000;
2515 }
2516
2517
2518 void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
2519 struct r600_resource *rbuffer,
2520 unsigned offset, unsigned stride,
2521 enum radeon_bo_usage usage)
2522 {
2523 rstate->bo[0] = rbuffer;
2524 rstate->bo_usage[0] = usage;
2525 rstate->val[0] = offset;
2526 rstate->val[1] = rbuffer->buf->size - offset - 1;
2527 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2528 S_030008_STRIDE(stride);
2529 }