2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
35 static inline unsigned evergreen_array_mode(unsigned mode
)
39 case RADEON_SURF_MODE_LINEAR_ALIGNED
: return V_028C70_ARRAY_LINEAR_ALIGNED
;
41 case RADEON_SURF_MODE_1D
: return V_028C70_ARRAY_1D_TILED_THIN1
;
43 case RADEON_SURF_MODE_2D
: return V_028C70_ARRAY_2D_TILED_THIN1
;
47 static uint32_t eg_num_banks(uint32_t nbanks
)
63 static unsigned eg_tile_split(unsigned tile_split
)
66 case 64: tile_split
= 0; break;
67 case 128: tile_split
= 1; break;
68 case 256: tile_split
= 2; break;
69 case 512: tile_split
= 3; break;
71 case 1024: tile_split
= 4; break;
72 case 2048: tile_split
= 5; break;
73 case 4096: tile_split
= 6; break;
78 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect
)
80 switch (macro_tile_aspect
) {
82 case 1: macro_tile_aspect
= 0; break;
83 case 2: macro_tile_aspect
= 1; break;
84 case 4: macro_tile_aspect
= 2; break;
85 case 8: macro_tile_aspect
= 3; break;
87 return macro_tile_aspect
;
90 static unsigned eg_bank_wh(unsigned bankwh
)
94 case 1: bankwh
= 0; break;
95 case 2: bankwh
= 1; break;
96 case 4: bankwh
= 2; break;
97 case 8: bankwh
= 3; break;
102 static uint32_t r600_translate_blend_function(int blend_func
)
104 switch (blend_func
) {
106 return V_028780_COMB_DST_PLUS_SRC
;
107 case PIPE_BLEND_SUBTRACT
:
108 return V_028780_COMB_SRC_MINUS_DST
;
109 case PIPE_BLEND_REVERSE_SUBTRACT
:
110 return V_028780_COMB_DST_MINUS_SRC
;
112 return V_028780_COMB_MIN_DST_SRC
;
114 return V_028780_COMB_MAX_DST_SRC
;
116 R600_ERR("Unknown blend function %d\n", blend_func
);
123 static uint32_t r600_translate_blend_factor(int blend_fact
)
125 switch (blend_fact
) {
126 case PIPE_BLENDFACTOR_ONE
:
127 return V_028780_BLEND_ONE
;
128 case PIPE_BLENDFACTOR_SRC_COLOR
:
129 return V_028780_BLEND_SRC_COLOR
;
130 case PIPE_BLENDFACTOR_SRC_ALPHA
:
131 return V_028780_BLEND_SRC_ALPHA
;
132 case PIPE_BLENDFACTOR_DST_ALPHA
:
133 return V_028780_BLEND_DST_ALPHA
;
134 case PIPE_BLENDFACTOR_DST_COLOR
:
135 return V_028780_BLEND_DST_COLOR
;
136 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
137 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
138 case PIPE_BLENDFACTOR_CONST_COLOR
:
139 return V_028780_BLEND_CONST_COLOR
;
140 case PIPE_BLENDFACTOR_CONST_ALPHA
:
141 return V_028780_BLEND_CONST_ALPHA
;
142 case PIPE_BLENDFACTOR_ZERO
:
143 return V_028780_BLEND_ZERO
;
144 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
145 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
146 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
147 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
148 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
149 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
150 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
151 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
152 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
153 return V_028780_BLEND_ONE_MINUS_CONST_COLOR
;
154 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
155 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA
;
156 case PIPE_BLENDFACTOR_SRC1_COLOR
:
157 return V_028780_BLEND_SRC1_COLOR
;
158 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
159 return V_028780_BLEND_SRC1_ALPHA
;
160 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
161 return V_028780_BLEND_INV_SRC1_COLOR
;
162 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
163 return V_028780_BLEND_INV_SRC1_ALPHA
;
165 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
172 static unsigned r600_tex_dim(struct r600_texture
*rtex
,
173 unsigned view_target
, unsigned nr_samples
)
175 unsigned res_target
= rtex
->resource
.b
.b
.target
;
177 if (view_target
== PIPE_TEXTURE_CUBE
||
178 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
179 res_target
= view_target
;
180 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
181 else if (res_target
== PIPE_TEXTURE_CUBE
||
182 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
183 res_target
= PIPE_TEXTURE_2D_ARRAY
;
185 switch (res_target
) {
187 case PIPE_TEXTURE_1D
:
188 return V_030000_SQ_TEX_DIM_1D
;
189 case PIPE_TEXTURE_1D_ARRAY
:
190 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
191 case PIPE_TEXTURE_2D
:
192 case PIPE_TEXTURE_RECT
:
193 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_MSAA
:
194 V_030000_SQ_TEX_DIM_2D
;
195 case PIPE_TEXTURE_2D_ARRAY
:
196 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
197 V_030000_SQ_TEX_DIM_2D_ARRAY
;
198 case PIPE_TEXTURE_3D
:
199 return V_030000_SQ_TEX_DIM_3D
;
200 case PIPE_TEXTURE_CUBE
:
201 case PIPE_TEXTURE_CUBE_ARRAY
:
202 return V_030000_SQ_TEX_DIM_CUBEMAP
;
206 static uint32_t r600_translate_dbformat(enum pipe_format format
)
209 case PIPE_FORMAT_Z16_UNORM
:
210 return V_028040_Z_16
;
211 case PIPE_FORMAT_Z24X8_UNORM
:
212 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
213 case PIPE_FORMAT_X8Z24_UNORM
:
214 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
215 return V_028040_Z_24
;
216 case PIPE_FORMAT_Z32_FLOAT
:
217 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
218 return V_028040_Z_32_FLOAT
;
224 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
226 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
,
230 static bool r600_is_colorbuffer_format_supported(enum chip_class chip
, enum pipe_format format
)
232 return r600_translate_colorformat(chip
, format
, FALSE
) != ~0U &&
233 r600_translate_colorswap(format
, FALSE
) != ~0U;
236 static bool r600_is_zs_format_supported(enum pipe_format format
)
238 return r600_translate_dbformat(format
) != ~0U;
241 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
242 enum pipe_format format
,
243 enum pipe_texture_target target
,
244 unsigned sample_count
,
247 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
250 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
251 R600_ERR("r600: unsupported texture type %d\n", target
);
255 if (!util_format_is_supported(format
, usage
))
258 if (sample_count
> 1) {
259 if (!rscreen
->has_msaa
)
262 switch (sample_count
) {
272 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
273 if (target
== PIPE_BUFFER
) {
274 if (r600_is_vertex_format_supported(format
))
275 retval
|= PIPE_BIND_SAMPLER_VIEW
;
277 if (r600_is_sampler_format_supported(screen
, format
))
278 retval
|= PIPE_BIND_SAMPLER_VIEW
;
282 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
283 PIPE_BIND_DISPLAY_TARGET
|
286 PIPE_BIND_BLENDABLE
)) &&
287 r600_is_colorbuffer_format_supported(rscreen
->b
.chip_class
, format
)) {
289 (PIPE_BIND_RENDER_TARGET
|
290 PIPE_BIND_DISPLAY_TARGET
|
293 if (!util_format_is_pure_integer(format
) &&
294 !util_format_is_depth_or_stencil(format
))
295 retval
|= usage
& PIPE_BIND_BLENDABLE
;
298 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
299 r600_is_zs_format_supported(format
)) {
300 retval
|= PIPE_BIND_DEPTH_STENCIL
;
303 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
304 r600_is_vertex_format_supported(format
)) {
305 retval
|= PIPE_BIND_VERTEX_BUFFER
;
308 if ((usage
& PIPE_BIND_LINEAR
) &&
309 !util_format_is_compressed(format
) &&
310 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
311 retval
|= PIPE_BIND_LINEAR
;
313 return retval
== usage
;
316 static void *evergreen_create_blend_state_mode(struct pipe_context
*ctx
,
317 const struct pipe_blend_state
*state
, int mode
)
319 uint32_t color_control
= 0, target_mask
= 0;
320 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
326 r600_init_command_buffer(&blend
->buffer
, 20);
327 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
329 if (state
->logicop_enable
) {
330 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
332 color_control
|= (0xcc << 16);
334 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
335 if (state
->independent_blend_enable
) {
336 for (int i
= 0; i
< 8; i
++) {
337 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
340 for (int i
= 0; i
< 8; i
++) {
341 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
345 /* only have dual source on MRT0 */
346 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
347 blend
->cb_target_mask
= target_mask
;
348 blend
->alpha_to_one
= state
->alpha_to_one
;
351 color_control
|= S_028808_MODE(mode
);
353 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
356 r600_store_context_reg(&blend
->buffer
, R_028808_CB_COLOR_CONTROL
, color_control
);
357 r600_store_context_reg(&blend
->buffer
, R_028B70_DB_ALPHA_TO_MASK
,
358 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
359 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
360 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
361 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
362 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
363 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
365 /* Copy over the dwords set so far into buffer_no_blend.
366 * Only the CB_BLENDi_CONTROL registers must be set after this. */
367 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
368 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
370 for (int i
= 0; i
< 8; i
++) {
371 /* state->rt entries > 0 only written if independent blending */
372 const int j
= state
->independent_blend_enable
? i
: 0;
374 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
375 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
376 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
377 unsigned eqA
= state
->rt
[j
].alpha_func
;
378 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
379 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
382 r600_store_value(&blend
->buffer_no_blend
, 0);
384 if (!state
->rt
[j
].blend_enable
) {
385 r600_store_value(&blend
->buffer
, 0);
389 bc
|= S_028780_BLEND_CONTROL_ENABLE(1);
390 bc
|= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
391 bc
|= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
392 bc
|= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
394 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
395 bc
|= S_028780_SEPARATE_ALPHA_BLEND(1);
396 bc
|= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
397 bc
|= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
398 bc
|= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
400 r600_store_value(&blend
->buffer
, bc
);
405 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
406 const struct pipe_blend_state
*state
)
409 return evergreen_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
412 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
413 const struct pipe_depth_stencil_alpha_state
*state
)
415 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
416 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
422 r600_init_command_buffer(&dsa
->buffer
, 3);
424 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
425 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
426 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
427 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
428 dsa
->zwritemask
= state
->depth
.writemask
;
430 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
431 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
432 S_028800_ZFUNC(state
->depth
.func
);
435 if (state
->stencil
[0].enabled
) {
436 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
437 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
438 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
439 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
440 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
442 if (state
->stencil
[1].enabled
) {
443 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
444 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
445 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
446 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
447 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
452 alpha_test_control
= 0;
454 if (state
->alpha
.enabled
) {
455 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
456 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
457 alpha_ref
= fui(state
->alpha
.ref_value
);
459 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
460 dsa
->alpha_ref
= alpha_ref
;
463 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
467 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
468 const struct pipe_rasterizer_state
*state
)
470 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
471 unsigned tmp
, spi_interp
;
472 float psize_min
, psize_max
;
473 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
479 r600_init_command_buffer(&rs
->buffer
, 30);
481 rs
->scissor_enable
= state
->scissor
;
482 rs
->clip_halfz
= state
->clip_halfz
;
483 rs
->flatshade
= state
->flatshade
;
484 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
485 rs
->rasterizer_discard
= state
->rasterizer_discard
;
486 rs
->two_side
= state
->light_twoside
;
487 rs
->clip_plane_enable
= state
->clip_plane_enable
;
488 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
489 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
490 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
491 rs
->pa_cl_clip_cntl
=
492 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
493 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
494 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
495 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
496 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
);
497 rs
->multisample_enable
= state
->multisample
;
500 rs
->offset_units
= state
->offset_units
;
501 rs
->offset_scale
= state
->offset_scale
* 16.0f
;
502 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
503 rs
->offset_units_unscaled
= state
->offset_units_unscaled
;
505 if (state
->point_size_per_vertex
) {
506 psize_min
= util_get_min_point_size(state
);
509 /* Force the point size to be as if the vertex output was disabled. */
510 psize_min
= state
->point_size
;
511 psize_max
= state
->point_size
;
514 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
515 if (state
->sprite_coord_enable
) {
516 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
517 S_0286D4_PNT_SPRITE_OVRD_X(2) |
518 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
519 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
520 S_0286D4_PNT_SPRITE_OVRD_W(1);
521 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
522 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
526 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
527 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
528 tmp
= r600_pack_float_12p4(state
->point_size
/2);
529 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
530 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
531 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
532 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
533 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
534 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
535 S_028A08_WIDTH((unsigned)(state
->line_width
* 8)));
537 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
538 r600_store_context_reg(&rs
->buffer
, R_028A48_PA_SC_MODE_CNTL_0
,
539 S_028A48_MSAA_ENABLE(state
->multisample
) |
540 S_028A48_VPORT_SCISSOR_ENABLE(1) |
541 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
));
543 if (rctx
->b
.chip_class
== CAYMAN
) {
544 r600_store_context_reg(&rs
->buffer
, CM_R_028BE4_PA_SU_VTX_CNTL
,
545 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
546 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
548 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
549 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
550 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
553 r600_store_context_reg(&rs
->buffer
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
554 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
,
555 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
556 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
557 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
558 S_028814_FACE(!state
->front_ccw
) |
559 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
560 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
561 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
562 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
563 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
564 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
565 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
569 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
570 const struct pipe_sampler_state
*state
)
572 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)ctx
->screen
;
573 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
574 unsigned max_aniso
= rscreen
->force_aniso
>= 0 ? rscreen
->force_aniso
575 : state
->max_anisotropy
;
576 unsigned max_aniso_ratio
= r600_tex_aniso_filter(max_aniso
);
582 ss
->border_color_use
= sampler_state_needs_border_color(state
);
584 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
585 ss
->tex_sampler_words
[0] =
586 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
587 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
588 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
589 S_03C000_XY_MAG_FILTER(eg_tex_filter(state
->mag_img_filter
, max_aniso
)) |
590 S_03C000_XY_MIN_FILTER(eg_tex_filter(state
->min_img_filter
, max_aniso
)) |
591 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
592 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio
) |
593 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
594 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
595 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
596 ss
->tex_sampler_words
[1] =
597 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
598 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8));
599 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
600 ss
->tex_sampler_words
[2] =
601 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
602 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
605 if (ss
->border_color_use
) {
606 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
611 struct eg_buf_res_params
{
612 enum pipe_format pipe_format
;
615 unsigned char swizzle
[4];
620 static void evergreen_fill_buffer_resource_words(struct r600_context
*rctx
,
621 struct pipe_resource
*buffer
,
622 struct eg_buf_res_params
*params
,
623 bool *skip_mip_address_reloc
,
624 unsigned tex_resource_words
[8])
626 struct r600_texture
*tmp
= (struct r600_texture
*)buffer
;
628 int stride
= util_format_get_blocksize(params
->pipe_format
);
629 unsigned format
, num_format
, format_comp
, endian
;
630 unsigned swizzle_res
;
631 const struct util_format_description
*desc
;
633 r600_vertex_data_type(params
->pipe_format
,
634 &format
, &num_format
, &format_comp
,
637 desc
= util_format_description(params
->pipe_format
);
639 if (params
->force_swizzle
)
640 swizzle_res
= r600_get_swizzle_combined(params
->swizzle
, NULL
, TRUE
);
642 swizzle_res
= r600_get_swizzle_combined(desc
->swizzle
, params
->swizzle
, TRUE
);
644 va
= tmp
->resource
.gpu_address
+ params
->offset
;
645 *skip_mip_address_reloc
= true;
646 tex_resource_words
[0] = va
;
647 tex_resource_words
[1] = params
->size
- 1;
648 tex_resource_words
[2] = S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
649 S_030008_STRIDE(stride
) |
650 S_030008_DATA_FORMAT(format
) |
651 S_030008_NUM_FORMAT_ALL(num_format
) |
652 S_030008_FORMAT_COMP_ALL(format_comp
) |
653 S_030008_ENDIAN_SWAP(endian
);
654 tex_resource_words
[3] = swizzle_res
| S_03000C_UNCACHED(params
->uncached
);
656 * dword 4 is for number of elements, for use with resinfo,
657 * albeit the amd gpu shader analyser
658 * uses a const buffer to store the element sizes for buffer txq
660 tex_resource_words
[4] = params
->size
/ stride
;
662 tex_resource_words
[5] = tex_resource_words
[6] = 0;
663 tex_resource_words
[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
);
666 static struct pipe_sampler_view
*
667 texture_buffer_sampler_view(struct r600_context
*rctx
,
668 struct r600_pipe_sampler_view
*view
,
669 unsigned width0
, unsigned height0
)
671 struct r600_texture
*tmp
= (struct r600_texture
*)view
->base
.texture
;
672 struct eg_buf_res_params params
;
674 memset(¶ms
, 0, sizeof(params
));
676 params
.pipe_format
= view
->base
.format
;
677 params
.offset
= view
->base
.u
.buf
.offset
;
678 params
.size
= view
->base
.u
.buf
.size
;
679 params
.swizzle
[0] = view
->base
.swizzle_r
;
680 params
.swizzle
[1] = view
->base
.swizzle_g
;
681 params
.swizzle
[2] = view
->base
.swizzle_b
;
682 params
.swizzle
[3] = view
->base
.swizzle_a
;
684 evergreen_fill_buffer_resource_words(rctx
, view
->base
.texture
,
685 ¶ms
, &view
->skip_mip_address_reloc
,
686 view
->tex_resource_words
);
687 view
->tex_resource
= &tmp
->resource
;
689 if (tmp
->resource
.gpu_address
)
690 LIST_ADDTAIL(&view
->list
, &rctx
->texture_buffers
);
694 struct eg_tex_res_params
{
695 enum pipe_format pipe_format
;
699 unsigned first_level
;
701 unsigned first_layer
;
704 unsigned char swizzle
[4];
707 static int evergreen_fill_tex_resource_words(struct r600_context
*rctx
,
708 struct pipe_resource
*texture
,
709 struct eg_tex_res_params
*params
,
710 bool *skip_mip_address_reloc
,
711 unsigned tex_resource_words
[8])
713 struct r600_screen
*rscreen
= (struct r600_screen
*)rctx
->b
.b
.screen
;
714 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
715 unsigned format
, endian
;
716 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
717 unsigned char array_mode
= 0, non_disp_tiling
= 0;
718 unsigned height
, depth
, width
;
719 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
, fmask_bankh
;
720 struct legacy_surf_level
*surflevel
;
721 unsigned base_level
, first_level
, last_level
;
722 unsigned dim
, last_layer
;
724 bool do_endian_swap
= FALSE
;
726 tile_split
= tmp
->surface
.u
.legacy
.tile_split
;
727 surflevel
= tmp
->surface
.u
.legacy
.level
;
729 /* Texturing with separate depth and stencil. */
730 if (tmp
->db_compatible
) {
731 switch (params
->pipe_format
) {
732 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
733 params
->pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
735 case PIPE_FORMAT_X8Z24_UNORM
:
736 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
737 /* Z24 is always stored like this for DB
740 params
->pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
742 case PIPE_FORMAT_X24S8_UINT
:
743 case PIPE_FORMAT_S8X24_UINT
:
744 case PIPE_FORMAT_X32_S8X24_UINT
:
745 params
->pipe_format
= PIPE_FORMAT_S8_UINT
;
746 tile_split
= tmp
->surface
.u
.legacy
.stencil_tile_split
;
747 surflevel
= tmp
->surface
.u
.legacy
.stencil_level
;
754 do_endian_swap
= !tmp
->db_compatible
;
756 format
= r600_translate_texformat(rctx
->b
.b
.screen
, params
->pipe_format
,
758 &word4
, &yuv_format
, do_endian_swap
);
759 assert(format
!= ~0);
764 endian
= r600_colorformat_endian_swap(format
, do_endian_swap
);
767 first_level
= params
->first_level
;
768 last_level
= params
->last_level
;
769 width
= params
->width0
;
770 height
= params
->height0
;
771 depth
= texture
->depth0
;
773 if (params
->force_level
) {
774 base_level
= params
->force_level
;
777 width
= u_minify(width
, params
->force_level
);
778 height
= u_minify(height
, params
->force_level
);
779 depth
= u_minify(depth
, params
->force_level
);
782 pitch
= surflevel
[base_level
].nblk_x
* util_format_get_blockwidth(params
->pipe_format
);
783 non_disp_tiling
= tmp
->non_disp_tiling
;
785 switch (surflevel
[base_level
].mode
) {
787 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
788 array_mode
= V_028C70_ARRAY_LINEAR_ALIGNED
;
790 case RADEON_SURF_MODE_2D
:
791 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
793 case RADEON_SURF_MODE_1D
:
794 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
797 macro_aspect
= tmp
->surface
.u
.legacy
.mtilea
;
798 bankw
= tmp
->surface
.u
.legacy
.bankw
;
799 bankh
= tmp
->surface
.u
.legacy
.bankh
;
800 tile_split
= eg_tile_split(tile_split
);
801 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
802 bankw
= eg_bank_wh(bankw
);
803 bankh
= eg_bank_wh(bankh
);
804 fmask_bankh
= eg_bank_wh(tmp
->fmask
.bank_height
);
806 /* 128 bit formats require tile type = 1 */
807 if (rscreen
->b
.chip_class
== CAYMAN
) {
808 if (util_format_get_blocksize(params
->pipe_format
) >= 16)
811 nbanks
= eg_num_banks(rscreen
->b
.info
.r600_num_banks
);
813 if (params
->target
== PIPE_TEXTURE_1D_ARRAY
) {
815 depth
= texture
->array_size
;
816 } else if (params
->target
== PIPE_TEXTURE_2D_ARRAY
) {
817 depth
= texture
->array_size
;
818 } else if (params
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
819 depth
= texture
->array_size
/ 6;
821 va
= tmp
->resource
.gpu_address
;
823 /* array type views and views into array types need to use layer offset */
824 dim
= r600_tex_dim(tmp
, params
->target
, texture
->nr_samples
);
825 tex_resource_words
[0] = (S_030000_DIM(dim
) |
826 S_030000_PITCH((pitch
/ 8) - 1) |
827 S_030000_TEX_WIDTH(width
- 1));
828 if (rscreen
->b
.chip_class
== CAYMAN
)
829 tex_resource_words
[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
831 tex_resource_words
[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
832 tex_resource_words
[1] = (S_030004_TEX_HEIGHT(height
- 1) |
833 S_030004_TEX_DEPTH(depth
- 1) |
834 S_030004_ARRAY_MODE(array_mode
));
835 tex_resource_words
[2] = (surflevel
[base_level
].offset
+ va
) >> 8;
837 *skip_mip_address_reloc
= false;
838 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
839 if (texture
->nr_samples
> 1 && rscreen
->has_compressed_msaa_texturing
) {
841 /* disable FMASK (0 = disabled) */
842 tex_resource_words
[3] = 0;
843 *skip_mip_address_reloc
= true;
845 /* FMASK should be in MIP_ADDRESS for multisample textures */
846 tex_resource_words
[3] = (tmp
->fmask
.offset
+ va
) >> 8;
848 } else if (last_level
&& texture
->nr_samples
<= 1) {
849 tex_resource_words
[3] = (surflevel
[1].offset
+ va
) >> 8;
851 tex_resource_words
[3] = (surflevel
[base_level
].offset
+ va
) >> 8;
854 last_layer
= params
->last_layer
;
855 if (params
->target
!= texture
->target
&& depth
== 1) {
856 last_layer
= params
->first_layer
;
858 tex_resource_words
[4] = (word4
|
859 S_030010_ENDIAN_SWAP(endian
));
860 tex_resource_words
[5] = S_030014_BASE_ARRAY(params
->first_layer
) |
861 S_030014_LAST_ARRAY(last_layer
);
862 tex_resource_words
[6] = S_030018_TILE_SPLIT(tile_split
);
864 if (texture
->nr_samples
> 1) {
865 unsigned log_samples
= util_logbase2(texture
->nr_samples
);
866 if (rscreen
->b
.chip_class
== CAYMAN
) {
867 tex_resource_words
[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples
);
869 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
870 tex_resource_words
[5] |= S_030014_LAST_LEVEL(log_samples
);
871 tex_resource_words
[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh
);
873 bool no_mip
= first_level
== last_level
;
875 tex_resource_words
[4] |= S_030010_BASE_LEVEL(first_level
);
876 tex_resource_words
[5] |= S_030014_LAST_LEVEL(last_level
);
877 /* aniso max 16 samples */
878 tex_resource_words
[6] |= S_030018_MAX_ANISO_RATIO(no_mip
? 0 : 4);
881 tex_resource_words
[7] = S_03001C_DATA_FORMAT(format
) |
882 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
) |
883 S_03001C_BANK_WIDTH(bankw
) |
884 S_03001C_BANK_HEIGHT(bankh
) |
885 S_03001C_MACRO_TILE_ASPECT(macro_aspect
) |
886 S_03001C_NUM_BANKS(nbanks
) |
887 S_03001C_DEPTH_SAMPLE_ORDER(tmp
->db_compatible
);
891 struct pipe_sampler_view
*
892 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
893 struct pipe_resource
*texture
,
894 const struct pipe_sampler_view
*state
,
895 unsigned width0
, unsigned height0
,
896 unsigned force_level
)
898 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
899 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
900 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
901 struct eg_tex_res_params params
;
907 /* initialize base object */
909 view
->base
.texture
= NULL
;
910 pipe_reference(NULL
, &texture
->reference
);
911 view
->base
.texture
= texture
;
912 view
->base
.reference
.count
= 1;
913 view
->base
.context
= ctx
;
915 if (state
->target
== PIPE_BUFFER
)
916 return texture_buffer_sampler_view(rctx
, view
, width0
, height0
);
918 memset(¶ms
, 0, sizeof(params
));
919 params
.pipe_format
= state
->format
;
920 params
.force_level
= force_level
;
921 params
.width0
= width0
;
922 params
.height0
= height0
;
923 params
.first_level
= state
->u
.tex
.first_level
;
924 params
.last_level
= state
->u
.tex
.last_level
;
925 params
.first_layer
= state
->u
.tex
.first_layer
;
926 params
.last_layer
= state
->u
.tex
.last_layer
;
927 params
.target
= state
->target
;
928 params
.swizzle
[0] = state
->swizzle_r
;
929 params
.swizzle
[1] = state
->swizzle_g
;
930 params
.swizzle
[2] = state
->swizzle_b
;
931 params
.swizzle
[3] = state
->swizzle_a
;
933 ret
= evergreen_fill_tex_resource_words(rctx
, texture
, ¶ms
,
934 &view
->skip_mip_address_reloc
,
935 view
->tex_resource_words
);
941 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
942 state
->format
== PIPE_FORMAT_S8X24_UINT
||
943 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
944 state
->format
== PIPE_FORMAT_S8_UINT
)
945 view
->is_stencil_sampler
= true;
947 view
->tex_resource
= &tmp
->resource
;
952 static struct pipe_sampler_view
*
953 evergreen_create_sampler_view(struct pipe_context
*ctx
,
954 struct pipe_resource
*tex
,
955 const struct pipe_sampler_view
*state
)
957 return evergreen_create_sampler_view_custom(ctx
, tex
, state
,
958 tex
->width0
, tex
->height0
, 0);
961 static void evergreen_emit_config_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
963 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
964 struct r600_config_state
*a
= (struct r600_config_state
*)atom
;
966 radeon_set_config_reg_seq(cs
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, 3);
967 if (a
->dyn_gpr_enabled
) {
968 radeon_emit(cs
, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx
->r6xx_num_clause_temp_gprs
));
972 radeon_emit(cs
, a
->sq_gpr_resource_mgmt_1
);
973 radeon_emit(cs
, a
->sq_gpr_resource_mgmt_2
);
974 radeon_emit(cs
, a
->sq_gpr_resource_mgmt_3
);
976 radeon_set_config_reg(cs
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (a
->dyn_gpr_enabled
<< 8));
977 if (a
->dyn_gpr_enabled
) {
978 radeon_set_context_reg(cs
, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
,
979 S_028838_PS_GPRS(0x1e) |
980 S_028838_VS_GPRS(0x1e) |
981 S_028838_GS_GPRS(0x1e) |
982 S_028838_ES_GPRS(0x1e) |
983 S_028838_HS_GPRS(0x1e) |
984 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
988 static void evergreen_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
990 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
991 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
993 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP0_X
, 6*4);
994 radeon_emit_array(cs
, (unsigned*)state
, 6*4);
997 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
998 const struct pipe_poly_stipple
*state
)
1002 static void evergreen_get_scissor_rect(struct r600_context
*rctx
,
1003 unsigned tl_x
, unsigned tl_y
, unsigned br_x
, unsigned br_y
,
1004 uint32_t *tl
, uint32_t *br
)
1006 struct pipe_scissor_state scissor
= {tl_x
, tl_y
, br_x
, br_y
};
1008 evergreen_apply_scissor_bug_workaround(&rctx
->b
, &scissor
);
1010 *tl
= S_028240_TL_X(scissor
.minx
) | S_028240_TL_Y(scissor
.miny
);
1011 *br
= S_028244_BR_X(scissor
.maxx
) | S_028244_BR_Y(scissor
.maxy
);
1014 struct r600_tex_color_info
{
1023 unsigned fmask_slice
;
1025 boolean export_16bpc
;
1028 static void evergreen_set_color_surface_buffer(struct r600_context
*rctx
,
1029 struct r600_resource
*res
,
1030 enum pipe_format pformat
,
1031 unsigned first_element
,
1032 unsigned last_element
,
1033 struct r600_tex_color_info
*color
)
1035 unsigned format
, swap
, ntype
, endian
;
1036 const struct util_format_description
*desc
;
1037 unsigned block_size
= util_format_get_blocksize(res
->b
.b
.format
);
1038 unsigned pitch_alignment
=
1039 MAX2(64, rctx
->screen
->b
.info
.pipe_interleave_bytes
/ block_size
);
1040 unsigned pitch
= align(res
->b
.b
.width0
, pitch_alignment
);
1042 unsigned width_elements
;
1044 width_elements
= last_element
- first_element
+ 1;
1046 format
= r600_translate_colorformat(rctx
->b
.chip_class
, pformat
, FALSE
);
1047 swap
= r600_translate_colorswap(pformat
, FALSE
);
1049 endian
= r600_colorformat_endian_swap(format
, FALSE
);
1051 desc
= util_format_description(pformat
);
1052 for (i
= 0; i
< 4; i
++) {
1053 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1057 ntype
= V_028C70_NUMBER_UNORM
;
1058 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1059 ntype
= V_028C70_NUMBER_SRGB
;
1060 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1061 if (desc
->channel
[i
].normalized
)
1062 ntype
= V_028C70_NUMBER_SNORM
;
1063 else if (desc
->channel
[i
].pure_integer
)
1064 ntype
= V_028C70_NUMBER_SINT
;
1065 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1066 if (desc
->channel
[i
].normalized
)
1067 ntype
= V_028C70_NUMBER_UNORM
;
1068 else if (desc
->channel
[i
].pure_integer
)
1069 ntype
= V_028C70_NUMBER_UINT
;
1070 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
1071 ntype
= V_028C70_NUMBER_FLOAT
;
1074 pitch
= (pitch
/ 8) - 1;
1075 color
->pitch
= S_028C64_PITCH_TILE_MAX(pitch
);
1077 color
->info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1078 color
->info
|= S_028C70_FORMAT(format
) |
1079 S_028C70_COMP_SWAP(swap
) |
1080 S_028C70_BLEND_CLAMP(0) |
1081 S_028C70_BLEND_BYPASS(1) |
1082 S_028C70_NUMBER_TYPE(ntype
) |
1083 S_028C70_ENDIAN(endian
);
1084 color
->attrib
= S_028C74_NON_DISP_TILING_ORDER(1);
1085 color
->ntype
= ntype
;
1086 color
->export_16bpc
= false;
1087 color
->dim
= width_elements
- 1;
1088 color
->slice
= 0; /* (width_elements / 64) - 1;*/
1090 color
->offset
= (res
->gpu_address
+ first_element
) >> 8;
1092 color
->fmask
= color
->offset
;
1093 color
->fmask_slice
= 0;
1096 static void evergreen_set_color_surface_common(struct r600_context
*rctx
,
1097 struct r600_texture
*rtex
,
1099 unsigned first_layer
,
1100 unsigned last_layer
,
1101 enum pipe_format pformat
,
1102 struct r600_tex_color_info
*color
)
1104 struct r600_screen
*rscreen
= rctx
->screen
;
1105 unsigned pitch
, slice
;
1106 unsigned non_disp_tiling
, macro_aspect
, tile_split
, bankh
, bankw
, fmask_bankh
, nbanks
;
1107 unsigned format
, swap
, ntype
, endian
;
1108 const struct util_format_description
*desc
;
1109 bool blend_clamp
= 0, blend_bypass
= 0, do_endian_swap
= FALSE
;
1112 color
->offset
= rtex
->surface
.u
.legacy
.level
[level
].offset
;
1113 color
->view
= S_028C6C_SLICE_START(first_layer
) |
1114 S_028C6C_SLICE_MAX(last_layer
);
1116 color
->offset
+= rtex
->resource
.gpu_address
;
1117 color
->offset
>>= 8;
1120 pitch
= (rtex
->surface
.u
.legacy
.level
[level
].nblk_x
) / 8 - 1;
1121 slice
= (rtex
->surface
.u
.legacy
.level
[level
].nblk_x
* rtex
->surface
.u
.legacy
.level
[level
].nblk_y
) / 64;
1127 switch (rtex
->surface
.u
.legacy
.level
[level
].mode
) {
1129 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1130 color
->info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1131 non_disp_tiling
= 1;
1133 case RADEON_SURF_MODE_1D
:
1134 color
->info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1
);
1135 non_disp_tiling
= rtex
->non_disp_tiling
;
1137 case RADEON_SURF_MODE_2D
:
1138 color
->info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1
);
1139 non_disp_tiling
= rtex
->non_disp_tiling
;
1142 tile_split
= rtex
->surface
.u
.legacy
.tile_split
;
1143 macro_aspect
= rtex
->surface
.u
.legacy
.mtilea
;
1144 bankw
= rtex
->surface
.u
.legacy
.bankw
;
1145 bankh
= rtex
->surface
.u
.legacy
.bankh
;
1146 if (rtex
->fmask
.size
)
1147 fmask_bankh
= rtex
->fmask
.bank_height
;
1149 fmask_bankh
= rtex
->surface
.u
.legacy
.bankh
;
1150 tile_split
= eg_tile_split(tile_split
);
1151 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1152 bankw
= eg_bank_wh(bankw
);
1153 bankh
= eg_bank_wh(bankh
);
1154 fmask_bankh
= eg_bank_wh(fmask_bankh
);
1156 if (rscreen
->b
.chip_class
== CAYMAN
) {
1157 if (util_format_get_blocksize(pformat
) >= 16)
1158 non_disp_tiling
= 1;
1160 nbanks
= eg_num_banks(rscreen
->b
.info
.r600_num_banks
);
1161 desc
= util_format_description(pformat
);
1162 for (i
= 0; i
< 4; i
++) {
1163 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1167 color
->attrib
= S_028C74_TILE_SPLIT(tile_split
)|
1168 S_028C74_NUM_BANKS(nbanks
) |
1169 S_028C74_BANK_WIDTH(bankw
) |
1170 S_028C74_BANK_HEIGHT(bankh
) |
1171 S_028C74_MACRO_TILE_ASPECT(macro_aspect
) |
1172 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling
) |
1173 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
1175 if (rctx
->b
.chip_class
== CAYMAN
) {
1176 color
->attrib
|= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] ==
1179 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1180 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
1181 color
->attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1182 S_028C74_NUM_FRAGMENTS(log_samples
);
1186 ntype
= V_028C70_NUMBER_UNORM
;
1187 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1188 ntype
= V_028C70_NUMBER_SRGB
;
1189 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1190 if (desc
->channel
[i
].normalized
)
1191 ntype
= V_028C70_NUMBER_SNORM
;
1192 else if (desc
->channel
[i
].pure_integer
)
1193 ntype
= V_028C70_NUMBER_SINT
;
1194 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1195 if (desc
->channel
[i
].normalized
)
1196 ntype
= V_028C70_NUMBER_UNORM
;
1197 else if (desc
->channel
[i
].pure_integer
)
1198 ntype
= V_028C70_NUMBER_UINT
;
1199 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
1200 ntype
= V_028C70_NUMBER_FLOAT
;
1203 if (R600_BIG_ENDIAN
)
1204 do_endian_swap
= !rtex
->db_compatible
;
1206 format
= r600_translate_colorformat(rctx
->b
.chip_class
, pformat
, do_endian_swap
);
1207 assert(format
!= ~0);
1208 swap
= r600_translate_colorswap(pformat
, do_endian_swap
);
1211 endian
= r600_colorformat_endian_swap(format
, do_endian_swap
);
1213 /* blend clamp should be set for all NORM/SRGB types */
1214 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
1215 ntype
== V_028C70_NUMBER_SRGB
)
1218 /* set blend bypass according to docs if SINT/UINT or
1219 8/24 COLOR variants */
1220 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1221 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1222 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1227 color
->ntype
= ntype
;
1228 color
->info
|= S_028C70_FORMAT(format
) |
1229 S_028C70_COMP_SWAP(swap
) |
1230 S_028C70_BLEND_CLAMP(blend_clamp
) |
1231 S_028C70_BLEND_BYPASS(blend_bypass
) |
1232 S_028C70_SIMPLE_FLOAT(1) |
1233 S_028C70_NUMBER_TYPE(ntype
) |
1234 S_028C70_ENDIAN(endian
);
1236 if (rtex
->fmask
.size
) {
1237 color
->info
|= S_028C70_COMPRESSION(1);
1240 /* EXPORT_NORM is an optimzation that can be enabled for better
1241 * performance in certain cases.
1242 * EXPORT_NORM can be enabled if:
1243 * - 11-bit or smaller UNORM/SNORM/SRGB
1244 * - 16-bit or smaller FLOAT
1246 color
->export_16bpc
= false;
1247 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1248 ((desc
->channel
[i
].size
< 12 &&
1249 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1250 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
1251 (desc
->channel
[i
].size
< 17 &&
1252 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1253 color
->info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
1254 color
->export_16bpc
= true;
1257 color
->pitch
= S_028C64_PITCH_TILE_MAX(pitch
);
1258 color
->slice
= S_028C68_SLICE_TILE_MAX(slice
);
1260 if (rtex
->fmask
.size
) {
1261 color
->fmask
= (rtex
->resource
.gpu_address
+ rtex
->fmask
.offset
) >> 8;
1262 color
->fmask_slice
= S_028C88_TILE_MAX(rtex
->fmask
.slice_tile_max
);
1264 color
->fmask
= color
->offset
;
1265 color
->fmask_slice
= S_028C88_TILE_MAX(slice
);
1270 * This function intializes the CB* register values for RATs. It is meant
1271 * to be used for 1D aligned buffers that do not have an associated
1274 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
1275 struct r600_surface
*surf
)
1277 struct pipe_resource
*pipe_buffer
= surf
->base
.texture
;
1278 struct r600_tex_color_info color
;
1280 evergreen_set_color_surface_buffer(rctx
, (struct r600_resource
*)surf
->base
.texture
,
1281 surf
->base
.format
, 0, pipe_buffer
->width0
,
1284 surf
->cb_color_base
= color
.offset
;
1285 surf
->cb_color_dim
= color
.dim
;
1286 surf
->cb_color_info
= color
.info
| S_028C70_RAT(1);
1287 surf
->cb_color_pitch
= color
.pitch
;
1288 surf
->cb_color_slice
= color
.slice
;
1289 surf
->cb_color_view
= color
.view
;
1290 surf
->cb_color_attrib
= color
.attrib
;
1291 surf
->cb_color_fmask
= color
.fmask
;
1292 surf
->cb_color_fmask_slice
= color
.fmask_slice
;
1294 surf
->cb_color_view
= 0;
1296 /* Set the buffer range the GPU will have access to: */
1297 util_range_add(&r600_resource(pipe_buffer
)->valid_buffer_range
,
1298 0, pipe_buffer
->width0
);
1302 void evergreen_init_color_surface(struct r600_context
*rctx
,
1303 struct r600_surface
*surf
)
1305 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1306 unsigned level
= surf
->base
.u
.tex
.level
;
1307 struct r600_tex_color_info color
;
1309 evergreen_set_color_surface_common(rctx
, rtex
, level
,
1310 surf
->base
.u
.tex
.first_layer
,
1311 surf
->base
.u
.tex
.last_layer
,
1315 surf
->alphatest_bypass
= color
.ntype
== V_028C70_NUMBER_UINT
||
1316 color
.ntype
== V_028C70_NUMBER_SINT
;
1317 surf
->export_16bpc
= color
.export_16bpc
;
1319 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1320 surf
->cb_color_base
= color
.offset
;
1321 surf
->cb_color_dim
= color
.dim
;
1322 surf
->cb_color_info
= color
.info
;
1323 surf
->cb_color_pitch
= color
.pitch
;
1324 surf
->cb_color_slice
= color
.slice
;
1325 surf
->cb_color_view
= color
.view
;
1326 surf
->cb_color_attrib
= color
.attrib
;
1327 surf
->cb_color_fmask
= color
.fmask
;
1328 surf
->cb_color_fmask_slice
= color
.fmask_slice
;
1330 surf
->color_initialized
= true;
1333 static void evergreen_init_depth_surface(struct r600_context
*rctx
,
1334 struct r600_surface
*surf
)
1336 struct r600_screen
*rscreen
= rctx
->screen
;
1337 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1338 unsigned level
= surf
->base
.u
.tex
.level
;
1339 struct legacy_surf_level
*levelinfo
= &rtex
->surface
.u
.legacy
.level
[level
];
1341 unsigned format
, array_mode
;
1342 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1345 format
= r600_translate_dbformat(surf
->base
.format
);
1346 assert(format
!= ~0);
1348 offset
= rtex
->resource
.gpu_address
;
1349 offset
+= rtex
->surface
.u
.legacy
.level
[level
].offset
;
1351 switch (rtex
->surface
.u
.legacy
.level
[level
].mode
) {
1352 case RADEON_SURF_MODE_2D
:
1353 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1355 case RADEON_SURF_MODE_1D
:
1356 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1358 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1361 tile_split
= rtex
->surface
.u
.legacy
.tile_split
;
1362 macro_aspect
= rtex
->surface
.u
.legacy
.mtilea
;
1363 bankw
= rtex
->surface
.u
.legacy
.bankw
;
1364 bankh
= rtex
->surface
.u
.legacy
.bankh
;
1365 tile_split
= eg_tile_split(tile_split
);
1366 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1367 bankw
= eg_bank_wh(bankw
);
1368 bankh
= eg_bank_wh(bankh
);
1369 nbanks
= eg_num_banks(rscreen
->b
.info
.r600_num_banks
);
1372 surf
->db_z_info
= S_028040_ARRAY_MODE(array_mode
) |
1373 S_028040_FORMAT(format
) |
1374 S_028040_TILE_SPLIT(tile_split
)|
1375 S_028040_NUM_BANKS(nbanks
) |
1376 S_028040_BANK_WIDTH(bankw
) |
1377 S_028040_BANK_HEIGHT(bankh
) |
1378 S_028040_MACRO_TILE_ASPECT(macro_aspect
);
1379 if (rscreen
->b
.chip_class
== CAYMAN
&& rtex
->resource
.b
.b
.nr_samples
> 1) {
1380 surf
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
1383 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
1385 surf
->db_depth_base
= offset
;
1386 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1387 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1388 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX(levelinfo
->nblk_x
/ 8 - 1) |
1389 S_028058_HEIGHT_TILE_MAX(levelinfo
->nblk_y
/ 8 - 1);
1390 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX(levelinfo
->nblk_x
*
1391 levelinfo
->nblk_y
/ 64 - 1);
1393 if (rtex
->surface
.has_stencil
) {
1394 uint64_t stencil_offset
;
1395 unsigned stile_split
= rtex
->surface
.u
.legacy
.stencil_tile_split
;
1397 stile_split
= eg_tile_split(stile_split
);
1399 stencil_offset
= rtex
->surface
.u
.legacy
.stencil_level
[level
].offset
;
1400 stencil_offset
+= rtex
->resource
.gpu_address
;
1402 surf
->db_stencil_base
= stencil_offset
>> 8;
1403 surf
->db_stencil_info
= S_028044_FORMAT(V_028044_STENCIL_8
) |
1404 S_028044_TILE_SPLIT(stile_split
);
1406 surf
->db_stencil_base
= offset
;
1407 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1408 * Older kernels are out of luck. */
1409 surf
->db_stencil_info
= rctx
->screen
->b
.info
.drm_minor
>= 18 ?
1410 S_028044_FORMAT(V_028044_STENCIL_INVALID
) :
1411 S_028044_FORMAT(V_028044_STENCIL_8
);
1414 if (r600_htile_enabled(rtex
, level
)) {
1415 uint64_t va
= rtex
->resource
.gpu_address
+ rtex
->htile_offset
;
1416 surf
->db_htile_data_base
= va
>> 8;
1417 surf
->db_htile_surface
= S_028ABC_HTILE_WIDTH(1) |
1418 S_028ABC_HTILE_HEIGHT(1) |
1419 S_028ABC_FULL_CACHE(1);
1420 surf
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
1421 surf
->db_preload_control
= 0;
1424 surf
->depth_initialized
= true;
1427 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
1428 const struct pipe_framebuffer_state
*state
)
1430 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1431 struct r600_surface
*surf
;
1432 struct r600_texture
*rtex
;
1433 uint32_t i
, log_samples
;
1435 /* Flush TC when changing the framebuffer state, because the only
1436 * client not using TC that can change textures is the framebuffer.
1437 * Other places don't typically have to flush TC.
1439 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
|
1440 R600_CONTEXT_FLUSH_AND_INV
|
1441 R600_CONTEXT_FLUSH_AND_INV_CB
|
1442 R600_CONTEXT_FLUSH_AND_INV_CB_META
|
1443 R600_CONTEXT_FLUSH_AND_INV_DB
|
1444 R600_CONTEXT_FLUSH_AND_INV_DB_META
|
1445 R600_CONTEXT_INV_TEX_CACHE
;
1447 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1450 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1451 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&& state
->cbufs
[0] &&
1452 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1453 rctx
->framebuffer
.compressed_cb_mask
= 0;
1454 rctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
1456 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1457 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1461 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1463 r600_context_add_resource_size(ctx
, state
->cbufs
[i
]->texture
);
1465 if (!surf
->color_initialized
) {
1466 evergreen_init_color_surface(rctx
, surf
);
1469 if (!surf
->export_16bpc
) {
1470 rctx
->framebuffer
.export_16bpc
= false;
1473 if (rtex
->fmask
.size
) {
1474 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1478 /* Update alpha-test state dependencies.
1479 * Alpha-test is done on the first colorbuffer only. */
1480 if (state
->nr_cbufs
) {
1481 bool alphatest_bypass
= false;
1482 bool export_16bpc
= true;
1484 surf
= (struct r600_surface
*)state
->cbufs
[0];
1486 alphatest_bypass
= surf
->alphatest_bypass
;
1487 export_16bpc
= surf
->export_16bpc
;
1490 if (rctx
->alphatest_state
.bypass
!= alphatest_bypass
) {
1491 rctx
->alphatest_state
.bypass
= alphatest_bypass
;
1492 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1494 if (rctx
->alphatest_state
.cb0_export_16bpc
!= export_16bpc
) {
1495 rctx
->alphatest_state
.cb0_export_16bpc
= export_16bpc
;
1496 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1502 surf
= (struct r600_surface
*)state
->zsbuf
;
1504 r600_context_add_resource_size(ctx
, state
->zsbuf
->texture
);
1506 if (!surf
->depth_initialized
) {
1507 evergreen_init_depth_surface(rctx
, surf
);
1510 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1511 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1512 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
1515 if (rctx
->db_state
.rsurf
!= surf
) {
1516 rctx
->db_state
.rsurf
= surf
;
1517 r600_mark_atom_dirty(rctx
, &rctx
->db_state
.atom
);
1518 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1520 } else if (rctx
->db_state
.rsurf
) {
1521 rctx
->db_state
.rsurf
= NULL
;
1522 r600_mark_atom_dirty(rctx
, &rctx
->db_state
.atom
);
1523 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1526 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1527 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1528 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1531 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1532 rctx
->alphatest_state
.bypass
= false;
1533 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1536 log_samples
= util_logbase2(rctx
->framebuffer
.nr_samples
);
1537 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1538 if ((rctx
->b
.chip_class
== CAYMAN
||
1539 rctx
->b
.family
== CHIP_RV770
) &&
1540 rctx
->db_misc_state
.log_samples
!= log_samples
) {
1541 rctx
->db_misc_state
.log_samples
= log_samples
;
1542 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1546 /* Calculate the CS size. */
1547 rctx
->framebuffer
.atom
.num_dw
= 4; /* SCISSOR */
1550 if (rctx
->b
.chip_class
== EVERGREEN
)
1551 rctx
->framebuffer
.atom
.num_dw
+= 17; /* Evergreen */
1553 rctx
->framebuffer
.atom
.num_dw
+= 28; /* Cayman */
1556 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 23;
1557 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 2;
1558 rctx
->framebuffer
.atom
.num_dw
+= (12 - state
->nr_cbufs
) * 3;
1562 rctx
->framebuffer
.atom
.num_dw
+= 24;
1563 rctx
->framebuffer
.atom
.num_dw
+= 2;
1564 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1565 rctx
->framebuffer
.atom
.num_dw
+= 4;
1568 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1570 r600_set_sample_locations_constant_buffer(rctx
);
1571 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
1574 static void evergreen_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
1576 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1578 if (rctx
->ps_iter_samples
== min_samples
)
1581 rctx
->ps_iter_samples
= min_samples
;
1582 if (rctx
->framebuffer
.nr_samples
> 1) {
1583 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1588 static uint32_t sample_locs_8x
[] = {
1589 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1590 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1591 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1592 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1593 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1594 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1595 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1596 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1598 static unsigned max_dist_8x
= 7;
1600 static void evergreen_get_sample_position(struct pipe_context
*ctx
,
1601 unsigned sample_count
,
1602 unsigned sample_index
,
1609 switch (sample_count
) {
1612 out_value
[0] = out_value
[1] = 0.5;
1615 offset
= 4 * (sample_index
* 2);
1616 val
.idx
= (eg_sample_locs_2x
[0] >> offset
) & 0xf;
1617 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1618 val
.idx
= (eg_sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1619 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1622 offset
= 4 * (sample_index
* 2);
1623 val
.idx
= (eg_sample_locs_4x
[0] >> offset
) & 0xf;
1624 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1625 val
.idx
= (eg_sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1626 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1629 offset
= 4 * (sample_index
% 4 * 2);
1630 index
= (sample_index
/ 4);
1631 val
.idx
= (sample_locs_8x
[index
] >> offset
) & 0xf;
1632 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1633 val
.idx
= (sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1634 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1639 static void evergreen_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
, int ps_iter_samples
)
1642 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1643 unsigned max_dist
= 0;
1645 switch (nr_samples
) {
1650 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, ARRAY_SIZE(eg_sample_locs_2x
));
1651 radeon_emit_array(cs
, eg_sample_locs_2x
, ARRAY_SIZE(eg_sample_locs_2x
));
1652 max_dist
= eg_max_dist_2x
;
1655 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, ARRAY_SIZE(eg_sample_locs_4x
));
1656 radeon_emit_array(cs
, eg_sample_locs_4x
, ARRAY_SIZE(eg_sample_locs_4x
));
1657 max_dist
= eg_max_dist_4x
;
1660 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, ARRAY_SIZE(sample_locs_8x
));
1661 radeon_emit_array(cs
, sample_locs_8x
, ARRAY_SIZE(sample_locs_8x
));
1662 max_dist
= max_dist_8x
;
1666 if (nr_samples
> 1) {
1667 radeon_set_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1668 radeon_emit(cs
, S_028C00_LAST_PIXEL(1) |
1669 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1670 radeon_emit(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1671 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1672 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
1673 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1) |
1674 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1675 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1677 radeon_set_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1678 radeon_emit(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1679 radeon_emit(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1680 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
1681 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1682 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1686 static void evergreen_emit_image_state(struct r600_context
*rctx
, struct r600_atom
*atom
,
1687 int immed_id_base
, int res_id_base
, int offset
, uint32_t pkt_flags
)
1689 struct r600_image_state
*state
= (struct r600_image_state
*)atom
;
1690 struct pipe_framebuffer_state
*fb_state
= &rctx
->framebuffer
.state
;
1691 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1692 struct r600_texture
*rtex
;
1693 struct r600_resource
*resource
;
1696 for (i
= 0; i
< R600_MAX_IMAGES
; i
++) {
1697 struct r600_image_view
*image
= &state
->views
[i
];
1698 unsigned reloc
, immed_reloc
;
1699 int idx
= i
+ offset
;
1702 idx
+= fb_state
->nr_cbufs
+ (rctx
->dual_src_blend
? 1 : 0);
1703 if (!image
->base
.resource
)
1706 resource
= (struct r600_resource
*)image
->base
.resource
;
1707 if (resource
->b
.b
.target
!= PIPE_BUFFER
)
1708 rtex
= (struct r600_texture
*)image
->base
.resource
;
1712 reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1715 RADEON_USAGE_READWRITE
,
1716 RADEON_PRIO_SHADER_RW_BUFFER
);
1718 immed_reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1720 resource
->immed_buffer
,
1721 RADEON_USAGE_READWRITE
,
1722 RADEON_PRIO_SHADER_RW_BUFFER
);
1725 radeon_compute_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ idx
* 0x3C, 13);
1727 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ idx
* 0x3C, 13);
1729 radeon_emit(cs
, image
->cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
1730 radeon_emit(cs
, image
->cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
1731 radeon_emit(cs
, image
->cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
1732 radeon_emit(cs
, image
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
1733 radeon_emit(cs
, image
->cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
1734 radeon_emit(cs
, image
->cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
1735 radeon_emit(cs
, image
->cb_color_dim
); /* R_028C78_CB_COLOR0_DIM */
1736 radeon_emit(cs
, rtex
? rtex
->cmask
.base_address_reg
: image
->cb_color_base
); /* R_028C7C_CB_COLOR0_CMASK */
1737 radeon_emit(cs
, rtex
? rtex
->cmask
.slice_tile_max
: 0); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1738 radeon_emit(cs
, image
->cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
1739 radeon_emit(cs
, image
->cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1740 radeon_emit(cs
, rtex
? rtex
->color_clear_value
[0] : 0); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1741 radeon_emit(cs
, rtex
? rtex
->color_clear_value
[1] : 0); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1743 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1744 radeon_emit(cs
, reloc
);
1746 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1747 radeon_emit(cs
, reloc
);
1749 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1750 radeon_emit(cs
, reloc
);
1752 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1753 radeon_emit(cs
, reloc
);
1756 radeon_compute_set_context_reg(cs
, R_028B9C_CB_IMMED0_BASE
+ (idx
* 4), resource
->immed_buffer
->gpu_address
>> 8);
1758 radeon_set_context_reg(cs
, R_028B9C_CB_IMMED0_BASE
+ (idx
* 4), resource
->immed_buffer
->gpu_address
>> 8);
1760 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /**/
1761 radeon_emit(cs
, immed_reloc
);
1763 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
1764 radeon_emit(cs
, (immed_id_base
+ i
+ offset
) * 8);
1765 radeon_emit_array(cs
, image
->immed_resource_words
, 8);
1767 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1768 radeon_emit(cs
, immed_reloc
);
1770 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
1771 radeon_emit(cs
, (res_id_base
+ i
+ offset
) * 8);
1772 radeon_emit_array(cs
, image
->resource_words
, 8);
1774 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1775 radeon_emit(cs
, reloc
);
1777 if (!image
->skip_mip_address_reloc
) {
1778 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1779 radeon_emit(cs
, reloc
);
1784 static void evergreen_emit_fragment_image_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1786 evergreen_emit_image_state(rctx
, atom
,
1787 R600_IMAGE_IMMED_RESOURCE_OFFSET
,
1788 R600_IMAGE_REAL_RESOURCE_OFFSET
, 0, 0);
1791 static void evergreen_emit_compute_image_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1793 evergreen_emit_image_state(rctx
, atom
,
1794 EG_FETCH_CONSTANTS_OFFSET_CS
+ R600_IMAGE_IMMED_RESOURCE_OFFSET
,
1795 EG_FETCH_CONSTANTS_OFFSET_CS
+ R600_IMAGE_REAL_RESOURCE_OFFSET
,
1796 0, RADEON_CP_PACKET3_COMPUTE_MODE
);
1799 static void evergreen_emit_fragment_buffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1801 int offset
= util_bitcount(rctx
->fragment_images
.enabled_mask
);
1802 evergreen_emit_image_state(rctx
, atom
,
1803 R600_IMAGE_IMMED_RESOURCE_OFFSET
,
1804 R600_IMAGE_REAL_RESOURCE_OFFSET
, offset
, 0);
1807 static void evergreen_emit_compute_buffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1809 int offset
= util_bitcount(rctx
->compute_images
.enabled_mask
);
1810 evergreen_emit_image_state(rctx
, atom
,
1811 EG_FETCH_CONSTANTS_OFFSET_CS
+ R600_IMAGE_IMMED_RESOURCE_OFFSET
,
1812 EG_FETCH_CONSTANTS_OFFSET_CS
+ R600_IMAGE_REAL_RESOURCE_OFFSET
,
1813 offset
, RADEON_CP_PACKET3_COMPUTE_MODE
);
1816 static void evergreen_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1818 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1819 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1820 unsigned nr_cbufs
= state
->nr_cbufs
;
1822 struct r600_texture
*tex
= NULL
;
1823 struct r600_surface
*cb
= NULL
;
1825 /* XXX support more colorbuffers once we need them */
1826 assert(nr_cbufs
<= 8);
1831 for (i
= 0; i
< nr_cbufs
; i
++) {
1832 unsigned reloc
, cmask_reloc
;
1834 cb
= (struct r600_surface
*)state
->cbufs
[i
];
1836 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1837 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1841 tex
= (struct r600_texture
*)cb
->base
.texture
;
1842 reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1844 (struct r600_resource
*)cb
->base
.texture
,
1845 RADEON_USAGE_READWRITE
,
1846 tex
->resource
.b
.b
.nr_samples
> 1 ?
1847 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1848 RADEON_PRIO_COLOR_BUFFER
);
1850 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
1851 cmask_reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1852 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
1855 cmask_reloc
= reloc
;
1858 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 13);
1859 radeon_emit(cs
, cb
->cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
1860 radeon_emit(cs
, cb
->cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
1861 radeon_emit(cs
, cb
->cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
1862 radeon_emit(cs
, cb
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
1863 radeon_emit(cs
, cb
->cb_color_info
| tex
->cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
1864 radeon_emit(cs
, cb
->cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
1865 radeon_emit(cs
, cb
->cb_color_dim
); /* R_028C78_CB_COLOR0_DIM */
1866 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* R_028C7C_CB_COLOR0_CMASK */
1867 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1868 radeon_emit(cs
, cb
->cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
1869 radeon_emit(cs
, cb
->cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1870 radeon_emit(cs
, tex
->color_clear_value
[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1871 radeon_emit(cs
, tex
->color_clear_value
[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1873 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1874 radeon_emit(cs
, reloc
);
1876 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1877 radeon_emit(cs
, reloc
);
1879 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1880 radeon_emit(cs
, cmask_reloc
);
1882 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1883 radeon_emit(cs
, reloc
);
1885 /* set CB_COLOR1_INFO for possible dual-src blending */
1886 if (rctx
->framebuffer
.dual_src_blend
&& i
== 1 && state
->cbufs
[0]) {
1887 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C,
1888 cb
->cb_color_info
| tex
->cb_color_info
);
1891 i
+= util_bitcount(rctx
->fragment_images
.enabled_mask
);
1892 i
+= util_bitcount(rctx
->fragment_buffers
.enabled_mask
);
1894 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
1896 radeon_set_context_reg(cs
, R_028E50_CB_COLOR8_INFO
+ (i
- 8) * 0x1C, 0);
1900 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
1901 unsigned reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1903 (struct r600_resource
*)state
->zsbuf
->texture
,
1904 RADEON_USAGE_READWRITE
,
1905 zb
->base
.texture
->nr_samples
> 1 ?
1906 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
1907 RADEON_PRIO_DEPTH_BUFFER
);
1909 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
1911 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 8);
1912 radeon_emit(cs
, zb
->db_z_info
); /* R_028040_DB_Z_INFO */
1913 radeon_emit(cs
, zb
->db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1914 radeon_emit(cs
, zb
->db_depth_base
); /* R_028048_DB_Z_READ_BASE */
1915 radeon_emit(cs
, zb
->db_stencil_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1916 radeon_emit(cs
, zb
->db_depth_base
); /* R_028050_DB_Z_WRITE_BASE */
1917 radeon_emit(cs
, zb
->db_stencil_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1918 radeon_emit(cs
, zb
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1919 radeon_emit(cs
, zb
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1921 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1922 radeon_emit(cs
, reloc
);
1924 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1925 radeon_emit(cs
, reloc
);
1927 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1928 radeon_emit(cs
, reloc
);
1930 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1931 radeon_emit(cs
, reloc
);
1932 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1933 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1934 * Older kernels are out of luck. */
1935 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
1936 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
1937 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
1940 /* Framebuffer dimensions. */
1941 evergreen_get_scissor_rect(rctx
, 0, 0, state
->width
, state
->height
, &tl
, &br
);
1943 radeon_set_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
1944 radeon_emit(cs
, tl
); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1945 radeon_emit(cs
, br
); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1947 if (rctx
->b
.chip_class
== EVERGREEN
) {
1948 evergreen_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
, rctx
->ps_iter_samples
);
1950 unsigned sc_mode_cntl_1
=
1951 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1952 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1954 if (rctx
->framebuffer
.nr_samples
> 1)
1955 cayman_emit_msaa_sample_locs(cs
, rctx
->framebuffer
.nr_samples
);
1956 cayman_emit_msaa_config(cs
, rctx
->framebuffer
.nr_samples
,
1957 rctx
->ps_iter_samples
, 0, sc_mode_cntl_1
);
1961 static void evergreen_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
1963 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1964 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
1965 float offset_units
= state
->offset_units
;
1966 float offset_scale
= state
->offset_scale
;
1967 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
1969 if (!state
->offset_units_unscaled
) {
1970 switch (state
->zs_format
) {
1971 case PIPE_FORMAT_Z24X8_UNORM
:
1972 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1973 case PIPE_FORMAT_X8Z24_UNORM
:
1974 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1975 offset_units
*= 2.0f
;
1976 pa_su_poly_offset_db_fmt_cntl
=
1977 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1979 case PIPE_FORMAT_Z16_UNORM
:
1980 offset_units
*= 4.0f
;
1981 pa_su_poly_offset_db_fmt_cntl
=
1982 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1985 pa_su_poly_offset_db_fmt_cntl
=
1986 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1987 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1991 radeon_set_context_reg_seq(cs
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
1992 radeon_emit(cs
, fui(offset_scale
));
1993 radeon_emit(cs
, fui(offset_units
));
1994 radeon_emit(cs
, fui(offset_scale
));
1995 radeon_emit(cs
, fui(offset_units
));
1997 radeon_set_context_reg(cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1998 pa_su_poly_offset_db_fmt_cntl
);
2001 static void evergreen_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2003 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2004 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
2005 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
2006 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
2007 unsigned rat_colormask
= ((1ULL << ((unsigned)(a
->nr_image_rats
+ a
->nr_buffer_rats
) * 4)) - 1) << (a
->nr_cbufs
* 4);
2008 radeon_set_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
2009 radeon_emit(cs
, (a
->blend_colormask
& fb_colormask
) | rat_colormask
); /* R_028238_CB_TARGET_MASK */
2010 /* This must match the used export instructions exactly.
2011 * Other values may lead to undefined behavior and hangs.
2013 radeon_emit(cs
, ps_colormask
); /* R_02823C_CB_SHADER_MASK */
2016 static void evergreen_emit_db_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2018 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2019 struct r600_db_state
*a
= (struct r600_db_state
*)atom
;
2021 if (a
->rsurf
&& a
->rsurf
->db_htile_surface
) {
2022 struct r600_texture
*rtex
= (struct r600_texture
*)a
->rsurf
->base
.texture
;
2025 radeon_set_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear_value
));
2026 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, a
->rsurf
->db_htile_surface
);
2027 radeon_set_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, a
->rsurf
->db_preload_control
);
2028 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, a
->rsurf
->db_htile_data_base
);
2029 reloc_idx
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, &rtex
->resource
,
2030 RADEON_USAGE_READWRITE
, RADEON_PRIO_HTILE
);
2031 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2032 radeon_emit(cs
, reloc_idx
);
2034 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, 0);
2035 radeon_set_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0);
2039 static void evergreen_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2041 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2042 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
2043 unsigned db_render_control
= 0;
2044 unsigned db_count_control
= 0;
2045 unsigned db_render_override
=
2046 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
2047 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
2049 if (rctx
->b
.num_occlusion_queries
> 0 &&
2050 !a
->occlusion_queries_disabled
) {
2051 db_count_control
|= S_028004_PERFECT_ZPASS_COUNTS(1);
2052 if (rctx
->b
.chip_class
== CAYMAN
) {
2053 db_count_control
|= S_028004_SAMPLE_RATE(a
->log_samples
);
2055 db_render_override
|= S_02800C_NOOP_CULL_DISABLE(1);
2057 db_count_control
|= S_028004_ZPASS_INCREMENT_DISABLE(1);
2060 /* This is to fix a lockup when hyperz and alpha test are enabled at
2061 * the same time somehow GPU get confuse on which order to pick for
2064 if (rctx
->alphatest_state
.sx_alpha_test_control
)
2065 db_render_override
|= S_02800C_FORCE_SHADER_Z_ORDER(1);
2067 if (a
->flush_depthstencil_through_cb
) {
2068 assert(a
->copy_depth
|| a
->copy_stencil
);
2070 db_render_control
|= S_028000_DEPTH_COPY_ENABLE(a
->copy_depth
) |
2071 S_028000_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
2072 S_028000_COPY_CENTROID(1) |
2073 S_028000_COPY_SAMPLE(a
->copy_sample
);
2074 } else if (a
->flush_depth_inplace
|| a
->flush_stencil_inplace
) {
2075 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(a
->flush_depth_inplace
) |
2076 S_028000_STENCIL_COMPRESS_DISABLE(a
->flush_stencil_inplace
);
2077 db_render_override
|= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2079 if (a
->htile_clear
) {
2080 /* FIXME we might want to disable cliprect here */
2081 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(1);
2084 radeon_set_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
2085 radeon_emit(cs
, db_render_control
); /* R_028000_DB_RENDER_CONTROL */
2086 radeon_emit(cs
, db_count_control
); /* R_028004_DB_COUNT_CONTROL */
2087 radeon_set_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
2088 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
2091 static void evergreen_emit_vertex_buffers(struct r600_context
*rctx
,
2092 struct r600_vertexbuf_state
*state
,
2093 unsigned resource_offset
,
2096 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2097 uint32_t dirty_mask
= state
->dirty_mask
;
2099 while (dirty_mask
) {
2100 struct pipe_vertex_buffer
*vb
;
2101 struct r600_resource
*rbuffer
;
2103 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
2105 vb
= &state
->vb
[buffer_index
];
2106 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
2109 va
= rbuffer
->gpu_address
+ vb
->buffer_offset
;
2111 /* fetch resources start at index 992 */
2112 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
2113 radeon_emit(cs
, (resource_offset
+ buffer_index
) * 8);
2114 radeon_emit(cs
, va
); /* RESOURCEi_WORD0 */
2115 radeon_emit(cs
, rbuffer
->b
.b
.width0
- vb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
2116 radeon_emit(cs
, /* RESOURCEi_WORD2 */
2117 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2118 S_030008_STRIDE(vb
->stride
) |
2119 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
2120 radeon_emit(cs
, /* RESOURCEi_WORD3 */
2121 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
2122 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
2123 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
2124 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
2125 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
2126 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
2127 radeon_emit(cs
, 0); /* RESOURCEi_WORD6 */
2128 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
2130 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2131 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2132 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
));
2134 state
->dirty_mask
= 0;
2137 static void evergreen_fs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
2139 evergreen_emit_vertex_buffers(rctx
, &rctx
->vertex_buffer_state
, EG_FETCH_CONSTANTS_OFFSET_FS
, 0);
2142 static void evergreen_cs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
2144 evergreen_emit_vertex_buffers(rctx
, &rctx
->cs_vertex_buffer_state
, EG_FETCH_CONSTANTS_OFFSET_CS
,
2145 RADEON_CP_PACKET3_COMPUTE_MODE
);
2148 static void evergreen_emit_constant_buffers(struct r600_context
*rctx
,
2149 struct r600_constbuf_state
*state
,
2150 unsigned buffer_id_base
,
2151 unsigned reg_alu_constbuf_size
,
2152 unsigned reg_alu_const_cache
,
2155 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2156 uint32_t dirty_mask
= state
->dirty_mask
;
2158 while (dirty_mask
) {
2159 struct pipe_constant_buffer
*cb
;
2160 struct r600_resource
*rbuffer
;
2162 unsigned buffer_index
= ffs(dirty_mask
) - 1;
2163 unsigned gs_ring_buffer
= (buffer_index
== R600_GS_RING_CONST_BUFFER
);
2165 cb
= &state
->cb
[buffer_index
];
2166 rbuffer
= (struct r600_resource
*)cb
->buffer
;
2169 va
= rbuffer
->gpu_address
+ cb
->buffer_offset
;
2171 if (buffer_index
< R600_MAX_HW_CONST_BUFFERS
) {
2172 radeon_set_context_reg_flag(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
2173 DIV_ROUND_UP(cb
->buffer_size
, 256), pkt_flags
);
2174 radeon_set_context_reg_flag(cs
, reg_alu_const_cache
+ buffer_index
* 4, va
>> 8,
2176 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2177 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2178 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
));
2181 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
2182 radeon_emit(cs
, (buffer_id_base
+ buffer_index
) * 8);
2183 radeon_emit(cs
, va
); /* RESOURCEi_WORD0 */
2184 radeon_emit(cs
, rbuffer
->b
.b
.width0
- cb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
2185 radeon_emit(cs
, /* RESOURCEi_WORD2 */
2186 S_030008_ENDIAN_SWAP(gs_ring_buffer
? ENDIAN_NONE
: r600_endian_swap(32)) |
2187 S_030008_STRIDE(gs_ring_buffer
? 4 : 16) |
2188 S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
2189 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT
));
2190 radeon_emit(cs
, /* RESOURCEi_WORD3 */
2191 S_03000C_UNCACHED(gs_ring_buffer
? 1 : 0) |
2192 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
2193 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
2194 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
2195 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
2196 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
2197 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
2198 radeon_emit(cs
, 0); /* RESOURCEi_WORD6 */
2199 radeon_emit(cs
, /* RESOURCEi_WORD7 */
2200 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
));
2202 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2203 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2204 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
));
2206 dirty_mask
&= ~(1 << buffer_index
);
2208 state
->dirty_mask
= 0;
2211 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
2212 static void evergreen_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2214 if (rctx
->vs_shader
->current
->shader
.vs_as_ls
) {
2215 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
],
2216 EG_FETCH_CONSTANTS_OFFSET_LS
,
2217 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
,
2218 R_028F40_ALU_CONST_CACHE_LS_0
,
2219 0 /* PKT3 flags */);
2221 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
],
2222 EG_FETCH_CONSTANTS_OFFSET_VS
,
2223 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
2224 R_028980_ALU_CONST_CACHE_VS_0
,
2225 0 /* PKT3 flags */);
2229 static void evergreen_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2231 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
],
2232 EG_FETCH_CONSTANTS_OFFSET_GS
,
2233 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
2234 R_0289C0_ALU_CONST_CACHE_GS_0
,
2235 0 /* PKT3 flags */);
2238 static void evergreen_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2240 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
],
2241 EG_FETCH_CONSTANTS_OFFSET_PS
,
2242 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
2243 R_028940_ALU_CONST_CACHE_PS_0
,
2244 0 /* PKT3 flags */);
2247 static void evergreen_emit_cs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2249 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_COMPUTE
],
2250 EG_FETCH_CONSTANTS_OFFSET_CS
,
2251 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
,
2252 R_028F40_ALU_CONST_CACHE_LS_0
,
2253 RADEON_CP_PACKET3_COMPUTE_MODE
);
2256 /* tes constants can be emitted to VS or ES - which are common */
2257 static void evergreen_emit_tes_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2259 if (!rctx
->tes_shader
)
2261 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_TESS_EVAL
],
2262 EG_FETCH_CONSTANTS_OFFSET_VS
,
2263 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
2264 R_028980_ALU_CONST_CACHE_VS_0
,
2268 static void evergreen_emit_tcs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2270 if (!rctx
->tes_shader
)
2272 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_TESS_CTRL
],
2273 EG_FETCH_CONSTANTS_OFFSET_HS
,
2274 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0
,
2275 R_028F00_ALU_CONST_CACHE_HS_0
,
2279 static void evergreen_emit_sampler_views(struct r600_context
*rctx
,
2280 struct r600_samplerview_state
*state
,
2281 unsigned resource_id_base
, unsigned pkt_flags
)
2283 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2284 uint32_t dirty_mask
= state
->dirty_mask
;
2286 while (dirty_mask
) {
2287 struct r600_pipe_sampler_view
*rview
;
2288 unsigned resource_index
= u_bit_scan(&dirty_mask
);
2291 rview
= state
->views
[resource_index
];
2294 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
2295 radeon_emit(cs
, (resource_id_base
+ resource_index
) * 8);
2296 radeon_emit_array(cs
, rview
->tex_resource_words
, 8);
2298 reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rview
->tex_resource
,
2300 r600_get_sampler_view_priority(rview
->tex_resource
));
2301 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2302 radeon_emit(cs
, reloc
);
2304 if (!rview
->skip_mip_address_reloc
) {
2305 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2306 radeon_emit(cs
, reloc
);
2309 state
->dirty_mask
= 0;
2312 static void evergreen_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2314 if (rctx
->vs_shader
->current
->shader
.vs_as_ls
) {
2315 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
,
2316 EG_FETCH_CONSTANTS_OFFSET_LS
+ R600_MAX_CONST_BUFFERS
, 0);
2318 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
,
2319 EG_FETCH_CONSTANTS_OFFSET_VS
+ R600_MAX_CONST_BUFFERS
, 0);
2323 static void evergreen_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2325 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
,
2326 EG_FETCH_CONSTANTS_OFFSET_GS
+ R600_MAX_CONST_BUFFERS
, 0);
2329 static void evergreen_emit_tcs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2331 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_CTRL
].views
,
2332 EG_FETCH_CONSTANTS_OFFSET_HS
+ R600_MAX_CONST_BUFFERS
, 0);
2335 static void evergreen_emit_tes_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2337 if (!rctx
->tes_shader
)
2339 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_EVAL
].views
,
2340 EG_FETCH_CONSTANTS_OFFSET_VS
+ R600_MAX_CONST_BUFFERS
, 0);
2343 static void evergreen_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2345 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
,
2346 EG_FETCH_CONSTANTS_OFFSET_PS
+ R600_MAX_CONST_BUFFERS
, 0);
2349 static void evergreen_emit_cs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2351 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
].views
,
2352 EG_FETCH_CONSTANTS_OFFSET_CS
+ R600_MAX_CONST_BUFFERS
, RADEON_CP_PACKET3_COMPUTE_MODE
);
2355 static void evergreen_emit_sampler_states(struct r600_context
*rctx
,
2356 struct r600_textures_info
*texinfo
,
2357 unsigned resource_id_base
,
2358 unsigned border_index_reg
,
2361 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2362 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
2364 while (dirty_mask
) {
2365 struct r600_pipe_sampler_state
*rstate
;
2366 unsigned i
= u_bit_scan(&dirty_mask
);
2368 rstate
= texinfo
->states
.states
[i
];
2371 radeon_emit(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0) | pkt_flags
);
2372 radeon_emit(cs
, (resource_id_base
+ i
) * 3);
2373 radeon_emit_array(cs
, rstate
->tex_sampler_words
, 3);
2375 if (rstate
->border_color_use
) {
2376 radeon_set_config_reg_seq(cs
, border_index_reg
, 5);
2378 radeon_emit_array(cs
, rstate
->border_color
.ui
, 4);
2381 texinfo
->states
.dirty_mask
= 0;
2384 static void evergreen_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2386 if (rctx
->vs_shader
->current
->shader
.vs_as_ls
) {
2387 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 72,
2388 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX
, 0);
2390 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18,
2391 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
, 0);
2395 static void evergreen_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2397 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36,
2398 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX
, 0);
2401 static void evergreen_emit_tcs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2403 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_CTRL
], 54,
2404 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX
, 0);
2407 static void evergreen_emit_tes_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2409 if (!rctx
->tes_shader
)
2411 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_EVAL
], 18,
2412 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
, 0);
2415 static void evergreen_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2417 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0,
2418 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
, 0);
2421 static void evergreen_emit_cs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2423 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
], 90,
2424 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX
,
2425 RADEON_CP_PACKET3_COMPUTE_MODE
);
2428 static void evergreen_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2430 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2431 uint8_t mask
= s
->sample_mask
;
2433 radeon_set_context_reg(rctx
->b
.gfx
.cs
, R_028C3C_PA_SC_AA_MASK
,
2434 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2437 static void cayman_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2439 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2440 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2441 uint16_t mask
= s
->sample_mask
;
2443 radeon_set_context_reg_seq(cs
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2444 radeon_emit(cs
, mask
| (mask
<< 16)); /* X0Y0_X1Y0 */
2445 radeon_emit(cs
, mask
| (mask
<< 16)); /* X0Y1_X1Y1 */
2448 static void evergreen_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2450 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2451 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
2452 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
->cso
;
2457 radeon_set_context_reg(cs
, R_0288A4_SQ_PGM_START_FS
,
2458 (shader
->buffer
->gpu_address
+ shader
->offset
) >> 8);
2459 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2460 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->buffer
,
2462 RADEON_PRIO_SHADER_BINARY
));
2465 static void evergreen_emit_shader_stages(struct r600_context
*rctx
, struct r600_atom
*a
)
2467 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2468 struct r600_shader_stages_state
*state
= (struct r600_shader_stages_state
*)a
;
2470 uint32_t v
= 0, v2
= 0, primid
= 0, tf_param
= 0;
2472 if (rctx
->vs_shader
->current
->shader
.vs_as_gs_a
) {
2473 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
2477 if (state
->geom_enable
) {
2480 if (rctx
->gs_shader
->gs_max_out_vertices
<= 128)
2481 cut_val
= V_028A40_GS_CUT_128
;
2482 else if (rctx
->gs_shader
->gs_max_out_vertices
<= 256)
2483 cut_val
= V_028A40_GS_CUT_256
;
2484 else if (rctx
->gs_shader
->gs_max_out_vertices
<= 512)
2485 cut_val
= V_028A40_GS_CUT_512
;
2487 cut_val
= V_028A40_GS_CUT_1024
;
2489 v
= S_028B54_GS_EN(1) |
2490 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2491 if (!rctx
->tes_shader
)
2492 v
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
2494 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
2495 S_028A40_CUT_MODE(cut_val
);
2497 if (rctx
->gs_shader
->current
->shader
.gs_prim_id_input
)
2501 if (rctx
->tes_shader
) {
2502 uint32_t type
, partitioning
, topology
;
2503 struct tgsi_shader_info
*info
= &rctx
->tes_shader
->current
->selector
->info
;
2504 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
2505 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
2506 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
2507 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
2508 switch (tes_prim_mode
) {
2509 case PIPE_PRIM_LINES
:
2510 type
= V_028B6C_TESS_ISOLINE
;
2512 case PIPE_PRIM_TRIANGLES
:
2513 type
= V_028B6C_TESS_TRIANGLE
;
2515 case PIPE_PRIM_QUADS
:
2516 type
= V_028B6C_TESS_QUAD
;
2523 switch (tes_spacing
) {
2524 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
2525 partitioning
= V_028B6C_PART_FRAC_ODD
;
2527 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
2528 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2530 case PIPE_TESS_SPACING_EQUAL
:
2531 partitioning
= V_028B6C_PART_INTEGER
;
2539 topology
= V_028B6C_OUTPUT_POINT
;
2540 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
2541 topology
= V_028B6C_OUTPUT_LINE
;
2542 else if (tes_vertex_order_cw
)
2543 /* XXX follow radeonsi and invert */
2544 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2546 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2548 tf_param
= S_028B6C_TYPE(type
) |
2549 S_028B6C_PARTITIONING(partitioning
) |
2550 S_028B6C_TOPOLOGY(topology
);
2553 if (rctx
->tes_shader
) {
2554 v
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
2556 if (!state
->geom_enable
)
2557 v
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
2559 v
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
2562 radeon_set_context_reg(cs
, R_028AB8_VGT_VTX_CNT_EN
, v
? 1 : 0 );
2563 radeon_set_context_reg(cs
, R_028B54_VGT_SHADER_STAGES_EN
, v
);
2564 radeon_set_context_reg(cs
, R_028A40_VGT_GS_MODE
, v2
);
2565 radeon_set_context_reg(cs
, R_028A84_VGT_PRIMITIVEID_EN
, primid
);
2566 radeon_set_context_reg(cs
, R_028B6C_VGT_TF_PARAM
, tf_param
);
2569 static void evergreen_emit_gs_rings(struct r600_context
*rctx
, struct r600_atom
*a
)
2571 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2572 struct r600_gs_rings_state
*state
= (struct r600_gs_rings_state
*)a
;
2573 struct r600_resource
*rbuffer
;
2575 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2576 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2577 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
2579 if (state
->enable
) {
2580 rbuffer
=(struct r600_resource
*)state
->esgs_ring
.buffer
;
2581 radeon_set_config_reg(cs
, R_008C40_SQ_ESGS_RING_BASE
,
2582 rbuffer
->gpu_address
>> 8);
2583 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2584 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2585 RADEON_USAGE_READWRITE
,
2586 RADEON_PRIO_SHADER_RINGS
));
2587 radeon_set_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
,
2588 state
->esgs_ring
.buffer_size
>> 8);
2590 rbuffer
=(struct r600_resource
*)state
->gsvs_ring
.buffer
;
2591 radeon_set_config_reg(cs
, R_008C48_SQ_GSVS_RING_BASE
,
2592 rbuffer
->gpu_address
>> 8);
2593 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2594 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2595 RADEON_USAGE_READWRITE
,
2596 RADEON_PRIO_SHADER_RINGS
));
2597 radeon_set_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
,
2598 state
->gsvs_ring
.buffer_size
>> 8);
2600 radeon_set_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
, 0);
2601 radeon_set_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
, 0);
2604 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2605 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2606 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
2609 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
2610 enum chip_class ctx_chip_class
,
2611 enum radeon_family ctx_family
,
2614 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2615 r600_store_value(cb
, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2616 /* always set the temp clauses */
2617 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2619 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2620 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2621 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2623 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2625 r600_store_context_reg_seq(cb
, R_028350_SX_MISC
, 2);
2626 r600_store_value(cb
, 0);
2627 r600_store_value(cb
, S_028354_SURFACE_SYNC_MASK(0xf));
2629 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2632 static void cayman_init_atom_start_cs(struct r600_context
*rctx
)
2634 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2637 r600_init_command_buffer(cb
, 338);
2639 /* This must be first. */
2640 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2641 r600_store_value(cb
, 0x80000000);
2642 r600_store_value(cb
, 0x80000000);
2644 /* We're setting config registers here. */
2645 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2646 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2648 /* This enables pipeline stat & streamout queries.
2649 * They are only disabled by blits.
2651 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2652 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START
) | EVENT_INDEX(0));
2654 cayman_init_common_regs(cb
, rctx
->b
.chip_class
,
2655 rctx
->b
.family
, rctx
->screen
->b
.info
.drm_minor
);
2657 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2658 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2660 /* remove LS/HS from one SIMD for hw workaround */
2661 r600_store_config_reg_seq(cb
, R_008E20_SQ_STATIC_THREAD_MGMT1
, 3);
2662 r600_store_value(cb
, 0xffffffff);
2663 r600_store_value(cb
, 0xffffffff);
2664 r600_store_value(cb
, 0xfffffffe);
2666 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2667 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2668 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2669 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2670 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2671 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2672 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2674 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2675 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2676 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2677 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2678 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2680 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2681 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2682 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2683 r600_store_value(cb
, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2684 r600_store_value(cb
, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2685 r600_store_value(cb
, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2686 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2687 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2688 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2689 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2690 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2691 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2692 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2693 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2695 r600_store_context_reg(cb
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0);
2697 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2699 r600_store_context_reg_seq(cb
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
2700 r600_store_value(cb
, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2701 r600_store_value(cb
, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2703 r600_store_context_reg(cb
, R_028724_GDS_ADDR_SIZE
, 0x3fff);
2704 r600_store_context_reg_seq(cb
, R_0288E8_SQ_LDS_ALLOC
, 2);
2705 r600_store_value(cb
, 0); /* R_0288E8_SQ_LDS_ALLOC */
2706 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2708 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2710 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2711 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2712 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2714 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2716 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2718 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2720 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2721 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2722 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2723 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2725 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2726 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2728 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2729 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2731 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2732 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2733 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2735 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2736 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2737 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2739 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2740 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2741 r600_store_context_reg(cb
, R_02887C_SQ_PGM_RESOURCES_2_GS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2742 r600_store_context_reg(cb
, R_028894_SQ_PGM_RESOURCES_2_ES
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2743 r600_store_context_reg(cb
, R_0288C0_SQ_PGM_RESOURCES_2_HS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2744 r600_store_context_reg(cb
, R_0288D8_SQ_PGM_RESOURCES_2_LS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2746 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2748 /* to avoid GPU doing any preloading of constant from random address */
2749 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2750 for (i
= 0; i
< 16; i
++)
2751 r600_store_value(cb
, 0);
2753 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2754 for (i
= 0; i
< 16; i
++)
2755 r600_store_value(cb
, 0);
2757 r600_store_context_reg_seq(cb
, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
, 16);
2758 for (i
= 0; i
< 16; i
++)
2759 r600_store_value(cb
, 0);
2761 r600_store_context_reg_seq(cb
, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
, 16);
2762 for (i
= 0; i
< 16; i
++)
2763 r600_store_value(cb
, 0);
2765 r600_store_context_reg_seq(cb
, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0
, 16);
2766 for (i
= 0; i
< 16; i
++)
2767 r600_store_value(cb
, 0);
2769 if (rctx
->screen
->b
.has_streamout
) {
2770 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2773 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
2774 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
2775 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2776 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
2777 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2778 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2780 r600_store_context_reg_seq(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 2);
2781 r600_store_value(cb
, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2782 r600_store_value(cb
, 0); /* R028B58_VGT_LS_HS_CONFIG */
2783 r600_store_context_reg(cb
, R_028B6C_VGT_TF_PARAM
, 0);
2784 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2785 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2786 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (64 * 4), 0x01000FFF);
2787 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (96 * 4), 0x01000FFF);
2788 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (128 * 4), 0x01000FFF);
2791 void evergreen_init_common_regs(struct r600_context
*rctx
, struct r600_command_buffer
*cb
,
2792 enum chip_class ctx_chip_class
,
2793 enum radeon_family ctx_family
,
2815 rctx
->default_gprs
[R600_HW_STAGE_PS
] = 93;
2816 rctx
->default_gprs
[R600_HW_STAGE_VS
] = 46;
2817 rctx
->r6xx_num_clause_temp_gprs
= 4;
2818 rctx
->default_gprs
[R600_HW_STAGE_GS
] = 31;
2819 rctx
->default_gprs
[R600_HW_STAGE_ES
] = 31;
2820 rctx
->default_gprs
[EG_HW_STAGE_HS
] = 23;
2821 rctx
->default_gprs
[EG_HW_STAGE_LS
] = 23;
2824 switch (ctx_family
) {
2832 tmp
|= S_008C00_VC_ENABLE(1);
2835 tmp
|= S_008C00_EXPORT_SRC_C(1);
2836 tmp
|= S_008C00_CS_PRIO(cs_prio
);
2837 tmp
|= S_008C00_LS_PRIO(ls_prio
);
2838 tmp
|= S_008C00_HS_PRIO(hs_prio
);
2839 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2840 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2841 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2842 tmp
|= S_008C00_ES_PRIO(es_prio
);
2844 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 1);
2845 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2847 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2848 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2849 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2851 /* The cs checker requires this register to be set. */
2852 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2854 r600_store_context_reg_seq(cb
, R_028350_SX_MISC
, 2);
2855 r600_store_value(cb
, 0);
2856 r600_store_value(cb
, S_028354_SURFACE_SYNC_MASK(0xf));
2861 void evergreen_init_atom_start_cs(struct r600_context
*rctx
)
2863 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2871 int num_ps_stack_entries
;
2872 int num_vs_stack_entries
;
2873 int num_gs_stack_entries
;
2874 int num_es_stack_entries
;
2875 int num_hs_stack_entries
;
2876 int num_ls_stack_entries
;
2877 enum radeon_family family
;
2880 if (rctx
->b
.chip_class
== CAYMAN
) {
2881 cayman_init_atom_start_cs(rctx
);
2885 r600_init_command_buffer(cb
, 338);
2887 /* This must be first. */
2888 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2889 r600_store_value(cb
, 0x80000000);
2890 r600_store_value(cb
, 0x80000000);
2892 /* We're setting config registers here. */
2893 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2894 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2896 /* This enables pipeline stat & streamout queries.
2897 * They are only disabled by blits.
2899 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2900 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START
) | EVENT_INDEX(0));
2902 evergreen_init_common_regs(rctx
, cb
, rctx
->b
.chip_class
,
2903 rctx
->b
.family
, rctx
->screen
->b
.info
.drm_minor
);
2905 family
= rctx
->b
.family
;
2909 num_ps_threads
= 96;
2910 num_vs_threads
= 16;
2911 num_gs_threads
= 16;
2912 num_es_threads
= 16;
2913 num_hs_threads
= 16;
2914 num_ls_threads
= 16;
2915 num_ps_stack_entries
= 42;
2916 num_vs_stack_entries
= 42;
2917 num_gs_stack_entries
= 42;
2918 num_es_stack_entries
= 42;
2919 num_hs_stack_entries
= 42;
2920 num_ls_stack_entries
= 42;
2923 num_ps_threads
= 128;
2924 num_vs_threads
= 20;
2925 num_gs_threads
= 20;
2926 num_es_threads
= 20;
2927 num_hs_threads
= 20;
2928 num_ls_threads
= 20;
2929 num_ps_stack_entries
= 42;
2930 num_vs_stack_entries
= 42;
2931 num_gs_stack_entries
= 42;
2932 num_es_stack_entries
= 42;
2933 num_hs_stack_entries
= 42;
2934 num_ls_stack_entries
= 42;
2937 num_ps_threads
= 128;
2938 num_vs_threads
= 20;
2939 num_gs_threads
= 20;
2940 num_es_threads
= 20;
2941 num_hs_threads
= 20;
2942 num_ls_threads
= 20;
2943 num_ps_stack_entries
= 85;
2944 num_vs_stack_entries
= 85;
2945 num_gs_stack_entries
= 85;
2946 num_es_stack_entries
= 85;
2947 num_hs_stack_entries
= 85;
2948 num_ls_stack_entries
= 85;
2952 num_ps_threads
= 128;
2953 num_vs_threads
= 20;
2954 num_gs_threads
= 20;
2955 num_es_threads
= 20;
2956 num_hs_threads
= 20;
2957 num_ls_threads
= 20;
2958 num_ps_stack_entries
= 85;
2959 num_vs_stack_entries
= 85;
2960 num_gs_stack_entries
= 85;
2961 num_es_stack_entries
= 85;
2962 num_hs_stack_entries
= 85;
2963 num_ls_stack_entries
= 85;
2966 num_ps_threads
= 96;
2967 num_vs_threads
= 16;
2968 num_gs_threads
= 16;
2969 num_es_threads
= 16;
2970 num_hs_threads
= 16;
2971 num_ls_threads
= 16;
2972 num_ps_stack_entries
= 42;
2973 num_vs_stack_entries
= 42;
2974 num_gs_stack_entries
= 42;
2975 num_es_stack_entries
= 42;
2976 num_hs_stack_entries
= 42;
2977 num_ls_stack_entries
= 42;
2980 num_ps_threads
= 96;
2981 num_vs_threads
= 25;
2982 num_gs_threads
= 25;
2983 num_es_threads
= 25;
2984 num_hs_threads
= 16;
2985 num_ls_threads
= 16;
2986 num_ps_stack_entries
= 42;
2987 num_vs_stack_entries
= 42;
2988 num_gs_stack_entries
= 42;
2989 num_es_stack_entries
= 42;
2990 num_hs_stack_entries
= 42;
2991 num_ls_stack_entries
= 42;
2994 num_ps_threads
= 96;
2995 num_vs_threads
= 25;
2996 num_gs_threads
= 25;
2997 num_es_threads
= 25;
2998 num_hs_threads
= 16;
2999 num_ls_threads
= 16;
3000 num_ps_stack_entries
= 85;
3001 num_vs_stack_entries
= 85;
3002 num_gs_stack_entries
= 85;
3003 num_es_stack_entries
= 85;
3004 num_hs_stack_entries
= 85;
3005 num_ls_stack_entries
= 85;
3008 num_ps_threads
= 128;
3009 num_vs_threads
= 20;
3010 num_gs_threads
= 20;
3011 num_es_threads
= 20;
3012 num_hs_threads
= 20;
3013 num_ls_threads
= 20;
3014 num_ps_stack_entries
= 85;
3015 num_vs_stack_entries
= 85;
3016 num_gs_stack_entries
= 85;
3017 num_es_stack_entries
= 85;
3018 num_hs_stack_entries
= 85;
3019 num_ls_stack_entries
= 85;
3022 num_ps_threads
= 128;
3023 num_vs_threads
= 20;
3024 num_gs_threads
= 20;
3025 num_es_threads
= 20;
3026 num_hs_threads
= 20;
3027 num_ls_threads
= 20;
3028 num_ps_stack_entries
= 42;
3029 num_vs_stack_entries
= 42;
3030 num_gs_stack_entries
= 42;
3031 num_es_stack_entries
= 42;
3032 num_hs_stack_entries
= 42;
3033 num_ls_stack_entries
= 42;
3036 num_ps_threads
= 96;
3037 num_vs_threads
= 10;
3038 num_gs_threads
= 10;
3039 num_es_threads
= 10;
3040 num_hs_threads
= 10;
3041 num_ls_threads
= 10;
3042 num_ps_stack_entries
= 42;
3043 num_vs_stack_entries
= 42;
3044 num_gs_stack_entries
= 42;
3045 num_es_stack_entries
= 42;
3046 num_hs_stack_entries
= 42;
3047 num_ls_stack_entries
= 42;
3051 tmp
= S_008C18_NUM_PS_THREADS(num_ps_threads
);
3052 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
3053 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
3054 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
3056 r600_store_config_reg_seq(cb
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, 5);
3057 r600_store_value(cb
, tmp
); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3059 tmp
= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
3060 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
3061 r600_store_value(cb
, tmp
); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3063 tmp
= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
3064 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
3065 r600_store_value(cb
, tmp
); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3067 tmp
= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
3068 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
3069 r600_store_value(cb
, tmp
); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3071 tmp
= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
3072 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
3073 r600_store_value(cb
, tmp
); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3075 r600_store_config_reg(cb
, R_008E2C_SQ_LDS_RESOURCE_MGMT
,
3076 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
3078 /* remove LS/HS from one SIMD for hw workaround */
3079 r600_store_config_reg_seq(cb
, R_008E20_SQ_STATIC_THREAD_MGMT1
, 3);
3080 r600_store_value(cb
, 0xffffffff);
3081 r600_store_value(cb
, 0xffffffff);
3082 r600_store_value(cb
, 0xfffffffe);
3084 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
3085 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
3087 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
3088 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3089 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3090 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3091 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3092 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3093 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3095 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
3096 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3097 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3098 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3099 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3101 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
3102 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3103 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
3104 r600_store_value(cb
, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3105 r600_store_value(cb
, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3106 r600_store_value(cb
, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3107 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3108 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3109 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
3110 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3111 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3112 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3113 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3114 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
3116 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
3118 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
3120 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
3121 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3122 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
3124 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
3126 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
3128 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
3129 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
3130 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
3132 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
3133 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
3135 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
3136 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3137 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3138 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3140 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
3141 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3142 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3144 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
3145 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3146 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3148 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3149 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3150 r600_store_context_reg(cb
, R_02887C_SQ_PGM_RESOURCES_2_GS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3151 r600_store_context_reg(cb
, R_028894_SQ_PGM_RESOURCES_2_ES
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3152 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
3153 r600_store_context_reg(cb
, R_0288C0_SQ_PGM_RESOURCES_2_HS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3154 r600_store_context_reg(cb
, R_0288D8_SQ_PGM_RESOURCES_2_LS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3156 /* to avoid GPU doing any preloading of constant from random address */
3157 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
3158 for (i
= 0; i
< 16; i
++)
3159 r600_store_value(cb
, 0);
3161 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
3162 for (i
= 0; i
< 16; i
++)
3163 r600_store_value(cb
, 0);
3165 r600_store_context_reg_seq(cb
, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
, 16);
3166 for (i
= 0; i
< 16; i
++)
3167 r600_store_value(cb
, 0);
3169 r600_store_context_reg_seq(cb
, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
, 16);
3170 for (i
= 0; i
< 16; i
++)
3171 r600_store_value(cb
, 0);
3173 r600_store_context_reg_seq(cb
, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0
, 16);
3174 for (i
= 0; i
< 16; i
++)
3175 r600_store_value(cb
, 0);
3177 r600_store_context_reg(cb
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0);
3179 if (rctx
->screen
->b
.has_streamout
) {
3180 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
3183 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
3184 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
3185 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
3186 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
3187 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3188 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3190 r600_store_context_reg_seq(cb
, R_0288E8_SQ_LDS_ALLOC
, 2);
3191 r600_store_value(cb
, 0); /* R_0288E8_SQ_LDS_ALLOC */
3192 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
3194 if (rctx
->b
.family
== CHIP_CAICOS
) {
3195 r600_store_context_reg_seq(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 2);
3196 r600_store_value(cb
, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3197 r600_store_value(cb
, 0); /* R028B58_VGT_LS_HS_CONFIG */
3198 r600_store_context_reg(cb
, R_028B6C_VGT_TF_PARAM
, 0);
3200 r600_store_context_reg_seq(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 7);
3201 r600_store_value(cb
, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3202 r600_store_value(cb
, 0); /* R028B58_VGT_LS_HS_CONFIG */
3203 r600_store_value(cb
, 0); /* R028B5C_VGT_LS_SIZE */
3204 r600_store_value(cb
, 0); /* R028B60_VGT_HS_SIZE */
3205 r600_store_value(cb
, 0); /* R028B64_VGT_LS_HS_ALLOC */
3206 r600_store_value(cb
, 0); /* R028B68_VGT_HS_PATCH_CONST */
3207 r600_store_value(cb
, 0); /* R028B68_VGT_TF_PARAM */
3210 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
3211 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
3212 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (64 * 4), 0x01000FFF);
3213 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (96 * 4), 0x01000FFF);
3214 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (128 * 4), 0x01000FFF);
3217 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3219 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3220 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3221 struct r600_shader
*rshader
= &shader
->shader
;
3222 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
= 0;
3223 int pos_index
= -1, face_index
= -1, fixed_pt_position_index
= -1;
3225 boolean have_perspective
= FALSE
, have_linear
= FALSE
;
3226 static const unsigned spi_baryc_enable_bit
[6] = {
3227 S_0286E0_PERSP_SAMPLE_ENA(1),
3228 S_0286E0_PERSP_CENTER_ENA(1),
3229 S_0286E0_PERSP_CENTROID_ENA(1),
3230 S_0286E0_LINEAR_SAMPLE_ENA(1),
3231 S_0286E0_LINEAR_CENTER_ENA(1),
3232 S_0286E0_LINEAR_CENTROID_ENA(1)
3234 unsigned spi_baryc_cntl
= 0, sid
, tmp
, num
= 0;
3235 unsigned z_export
= 0, stencil_export
= 0, mask_export
= 0;
3236 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
3237 uint32_t spi_ps_input_cntl
[32];
3240 r600_init_command_buffer(cb
, 64);
3245 for (i
= 0; i
< rshader
->ninput
; i
++) {
3246 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3247 POSITION goes via GPRs from the SC so isn't counted */
3248 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
3250 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
) {
3251 if (face_index
== -1)
3254 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
) {
3255 if (face_index
== -1)
3256 face_index
= i
; /* lives in same register, same enable bit */
3258 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_SAMPLEID
) {
3259 fixed_pt_position_index
= i
;
3263 int k
= eg_get_interpolator_index(
3264 rshader
->input
[i
].interpolate
,
3265 rshader
->input
[i
].interpolate_location
);
3267 spi_baryc_cntl
|= spi_baryc_enable_bit
[k
];
3268 have_perspective
|= k
< 3;
3269 have_linear
|= !(k
< 3);
3273 sid
= rshader
->input
[i
].spi_sid
;
3276 tmp
= S_028644_SEMANTIC(sid
);
3278 /* D3D 9 behaviour. GL is undefined */
3279 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
&& rshader
->input
[i
].sid
== 0)
3280 tmp
|= S_028644_DEFAULT_VAL(3);
3282 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
3283 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3284 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
3285 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
)) {
3286 tmp
|= S_028644_FLAT_SHADE(1);
3289 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
3290 (sprite_coord_enable
& (1 << rshader
->input
[i
].sid
))) {
3291 tmp
|= S_028644_PT_SPRITE_TEX(1);
3294 spi_ps_input_cntl
[num
++] = tmp
;
3298 r600_store_context_reg_seq(cb
, R_028644_SPI_PS_INPUT_CNTL_0
, num
);
3299 r600_store_array(cb
, num
, spi_ps_input_cntl
);
3301 for (i
= 0; i
< rshader
->noutput
; i
++) {
3302 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
3304 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
3306 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
&&
3307 rctx
->framebuffer
.nr_samples
> 1 && rctx
->ps_iter_samples
> 0)
3310 if (rshader
->uses_kill
)
3311 db_shader_control
|= S_02880C_KILL_ENABLE(1);
3313 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
3314 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export
);
3315 db_shader_control
|= S_02880C_MASK_EXPORT_ENABLE(mask_export
);
3317 if (shader
->selector
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
3318 db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
3319 S_02880C_EXEC_ON_NOOP(shader
->selector
->info
.writes_memory
);
3320 } else if (shader
->selector
->info
.writes_memory
) {
3321 db_shader_control
|= S_02880C_EXEC_ON_HIER_FAIL(1);
3324 switch (rshader
->ps_conservative_z
) {
3325 default: /* fall through */
3326 case TGSI_FS_DEPTH_LAYOUT_ANY
:
3327 db_shader_control
|= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z
);
3329 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
3330 db_shader_control
|= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
3332 case TGSI_FS_DEPTH_LAYOUT_LESS
:
3333 db_shader_control
|= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
3338 for (i
= 0; i
< rshader
->noutput
; i
++) {
3339 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
3340 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
||
3341 rshader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
)
3345 num_cout
= rshader
->nr_ps_color_exports
;
3347 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
3349 /* always at least export 1 component per pixel */
3352 shader
->nr_ps_color_outputs
= num_cout
;
3355 have_perspective
= TRUE
;
3357 if (!spi_baryc_cntl
)
3358 spi_baryc_cntl
|= spi_baryc_enable_bit
[0];
3360 if (!have_perspective
&& !have_linear
)
3361 have_perspective
= TRUE
;
3363 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
3364 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
3365 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
3367 if (pos_index
!= -1) {
3368 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
3369 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].interpolate_location
== TGSI_INTERPOLATE_LOC_CENTROID
) |
3370 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
3371 spi_input_z
|= S_0286D8_PROVIDE_Z_TO_SPI(1);
3374 spi_ps_in_control_1
= 0;
3375 if (face_index
!= -1) {
3376 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
3377 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
3379 if (fixed_pt_position_index
!= -1) {
3380 spi_ps_in_control_1
|= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3381 S_0286D0_FIXED_PT_POSITION_ADDR(rshader
->input
[fixed_pt_position_index
].gpr
);
3384 r600_store_context_reg_seq(cb
, R_0286CC_SPI_PS_IN_CONTROL_0
, 2);
3385 r600_store_value(cb
, spi_ps_in_control_0
); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3386 r600_store_value(cb
, spi_ps_in_control_1
); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3388 r600_store_context_reg(cb
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
3389 r600_store_context_reg(cb
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
3390 r600_store_context_reg(cb
, R_02884C_SQ_PGM_EXPORTS_PS
, exports_ps
);
3392 r600_store_context_reg_seq(cb
, R_028840_SQ_PGM_START_PS
, 2);
3393 r600_store_value(cb
, shader
->bo
->gpu_address
>> 8);
3394 r600_store_value(cb
, /* R_028844_SQ_PGM_RESOURCES_PS */
3395 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
3396 S_028844_PRIME_CACHE_ON_DRAW(1) |
3397 S_028844_DX10_CLAMP(1) |
3398 S_028844_STACK_SIZE(rshader
->bc
.nstack
));
3399 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3401 shader
->db_shader_control
= db_shader_control
;
3402 shader
->ps_depth_export
= z_export
| stencil_export
| mask_export
;
3404 shader
->sprite_coord_enable
= sprite_coord_enable
;
3405 if (rctx
->rasterizer
)
3406 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
3409 void evergreen_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3411 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3412 struct r600_shader
*rshader
= &shader
->shader
;
3414 r600_init_command_buffer(cb
, 32);
3416 r600_store_context_reg(cb
, R_028890_SQ_PGM_RESOURCES_ES
,
3417 S_028890_NUM_GPRS(rshader
->bc
.ngpr
) |
3418 S_028890_DX10_CLAMP(1) |
3419 S_028890_STACK_SIZE(rshader
->bc
.nstack
));
3420 r600_store_context_reg(cb
, R_02888C_SQ_PGM_START_ES
,
3421 shader
->bo
->gpu_address
>> 8);
3422 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3425 void evergreen_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3427 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3428 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3429 struct r600_shader
*rshader
= &shader
->shader
;
3430 struct r600_shader
*cp_shader
= &shader
->gs_copy_shader
->shader
;
3431 unsigned gsvs_itemsizes
[4] = {
3432 (cp_shader
->ring_item_sizes
[0] * shader
->selector
->gs_max_out_vertices
) >> 2,
3433 (cp_shader
->ring_item_sizes
[1] * shader
->selector
->gs_max_out_vertices
) >> 2,
3434 (cp_shader
->ring_item_sizes
[2] * shader
->selector
->gs_max_out_vertices
) >> 2,
3435 (cp_shader
->ring_item_sizes
[3] * shader
->selector
->gs_max_out_vertices
) >> 2
3438 r600_init_command_buffer(cb
, 64);
3440 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3443 r600_store_context_reg(cb
, R_028B38_VGT_GS_MAX_VERT_OUT
,
3444 S_028B38_MAX_VERT_OUT(shader
->selector
->gs_max_out_vertices
));
3445 r600_store_context_reg(cb
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
3446 r600_conv_prim_to_gs_out(shader
->selector
->gs_output_prim
));
3448 if (rctx
->screen
->b
.info
.drm_minor
>= 35) {
3449 r600_store_context_reg(cb
, R_028B90_VGT_GS_INSTANCE_CNT
,
3450 S_028B90_CNT(MIN2(shader
->selector
->gs_num_invocations
, 127)) |
3451 S_028B90_ENABLE(shader
->selector
->gs_num_invocations
> 0));
3453 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
3454 r600_store_value(cb
, cp_shader
->ring_item_sizes
[0] >> 2);
3455 r600_store_value(cb
, cp_shader
->ring_item_sizes
[1] >> 2);
3456 r600_store_value(cb
, cp_shader
->ring_item_sizes
[2] >> 2);
3457 r600_store_value(cb
, cp_shader
->ring_item_sizes
[3] >> 2);
3459 r600_store_context_reg(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
,
3460 (rshader
->ring_item_sizes
[0]) >> 2);
3462 r600_store_context_reg(cb
, R_028904_SQ_GSVS_RING_ITEMSIZE
,
3468 r600_store_context_reg_seq(cb
, R_02892C_SQ_GSVS_RING_OFFSET_1
, 3);
3469 r600_store_value(cb
, gsvs_itemsizes
[0]);
3470 r600_store_value(cb
, gsvs_itemsizes
[0] + gsvs_itemsizes
[1]);
3471 r600_store_value(cb
, gsvs_itemsizes
[0] + gsvs_itemsizes
[1] + gsvs_itemsizes
[2]);
3473 /* FIXME calculate these values somehow ??? */
3474 r600_store_context_reg_seq(cb
, R_028A54_GS_PER_ES
, 3);
3475 r600_store_value(cb
, 0x80); /* GS_PER_ES */
3476 r600_store_value(cb
, 0x100); /* ES_PER_GS */
3477 r600_store_value(cb
, 0x2); /* GS_PER_VS */
3479 r600_store_context_reg(cb
, R_028878_SQ_PGM_RESOURCES_GS
,
3480 S_028878_NUM_GPRS(rshader
->bc
.ngpr
) |
3481 S_028878_DX10_CLAMP(1) |
3482 S_028878_STACK_SIZE(rshader
->bc
.nstack
));
3483 r600_store_context_reg(cb
, R_028874_SQ_PGM_START_GS
,
3484 shader
->bo
->gpu_address
>> 8);
3485 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3489 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3491 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3492 struct r600_shader
*rshader
= &shader
->shader
;
3493 unsigned spi_vs_out_id
[10] = {};
3494 unsigned i
, tmp
, nparams
= 0;
3496 for (i
= 0; i
< rshader
->noutput
; i
++) {
3497 if (rshader
->output
[i
].spi_sid
) {
3498 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
3499 spi_vs_out_id
[nparams
/ 4] |= tmp
;
3504 r600_init_command_buffer(cb
, 32);
3506 r600_store_context_reg_seq(cb
, R_02861C_SPI_VS_OUT_ID_0
, 10);
3507 for (i
= 0; i
< 10; i
++) {
3508 r600_store_value(cb
, spi_vs_out_id
[i
]);
3511 /* Certain attributes (position, psize, etc.) don't count as params.
3512 * VS is required to export at least one param and r600_shader_from_tgsi()
3513 * takes care of adding a dummy export.
3518 r600_store_context_reg(cb
, R_0286C4_SPI_VS_OUT_CONFIG
,
3519 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
3520 r600_store_context_reg(cb
, R_028860_SQ_PGM_RESOURCES_VS
,
3521 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
3522 S_028860_DX10_CLAMP(1) |
3523 S_028860_STACK_SIZE(rshader
->bc
.nstack
));
3524 if (rshader
->vs_position_window_space
) {
3525 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
3526 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3528 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
3529 S_028818_VTX_W0_FMT(1) |
3530 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3531 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3532 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3535 r600_store_context_reg(cb
, R_02885C_SQ_PGM_START_VS
,
3536 shader
->bo
->gpu_address
>> 8);
3537 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3539 shader
->pa_cl_vs_out_cntl
=
3540 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->cc_dist_mask
& 0x0F) != 0) |
3541 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->cc_dist_mask
& 0xF0) != 0) |
3542 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
3543 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
) |
3544 S_02881C_USE_VTX_EDGE_FLAG(rshader
->vs_out_edgeflag
) |
3545 S_02881C_USE_VTX_VIEWPORT_INDX(rshader
->vs_out_viewport
) |
3546 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader
->vs_out_layer
);
3549 void evergreen_update_hs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3551 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3552 struct r600_shader
*rshader
= &shader
->shader
;
3554 r600_init_command_buffer(cb
, 32);
3555 r600_store_context_reg(cb
, R_0288BC_SQ_PGM_RESOURCES_HS
,
3556 S_0288BC_NUM_GPRS(rshader
->bc
.ngpr
) |
3557 S_0288BC_DX10_CLAMP(1) |
3558 S_0288BC_STACK_SIZE(rshader
->bc
.nstack
));
3559 r600_store_context_reg(cb
, R_0288B8_SQ_PGM_START_HS
,
3560 shader
->bo
->gpu_address
>> 8);
3563 void evergreen_update_ls_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3565 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3566 struct r600_shader
*rshader
= &shader
->shader
;
3568 r600_init_command_buffer(cb
, 32);
3569 r600_store_context_reg(cb
, R_0288D4_SQ_PGM_RESOURCES_LS
,
3570 S_0288D4_NUM_GPRS(rshader
->bc
.ngpr
) |
3571 S_0288D4_DX10_CLAMP(1) |
3572 S_0288D4_STACK_SIZE(rshader
->bc
.nstack
));
3573 r600_store_context_reg(cb
, R_0288D0_SQ_PGM_START_LS
,
3574 shader
->bo
->gpu_address
>> 8);
3576 void *evergreen_create_resolve_blend(struct r600_context
*rctx
)
3578 struct pipe_blend_state blend
;
3580 memset(&blend
, 0, sizeof(blend
));
3581 blend
.independent_blend_enable
= true;
3582 blend
.rt
[0].colormask
= 0xf;
3583 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_CB_RESOLVE
);
3586 void *evergreen_create_decompress_blend(struct r600_context
*rctx
)
3588 struct pipe_blend_state blend
;
3589 unsigned mode
= rctx
->screen
->has_compressed_msaa_texturing
?
3590 V_028808_CB_FMASK_DECOMPRESS
: V_028808_CB_DECOMPRESS
;
3592 memset(&blend
, 0, sizeof(blend
));
3593 blend
.independent_blend_enable
= true;
3594 blend
.rt
[0].colormask
= 0xf;
3595 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3598 void *evergreen_create_fastclear_blend(struct r600_context
*rctx
)
3600 struct pipe_blend_state blend
;
3601 unsigned mode
= V_028808_CB_ELIMINATE_FAST_CLEAR
;
3603 memset(&blend
, 0, sizeof(blend
));
3604 blend
.independent_blend_enable
= true;
3605 blend
.rt
[0].colormask
= 0xf;
3606 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3609 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
)
3611 struct pipe_depth_stencil_alpha_state dsa
= {{0}};
3613 return rctx
->b
.b
.create_depth_stencil_alpha_state(&rctx
->b
.b
, &dsa
);
3616 void evergreen_update_db_shader_control(struct r600_context
* rctx
)
3619 unsigned db_shader_control
;
3621 if (!rctx
->ps_shader
) {
3625 dual_export
= rctx
->framebuffer
.export_16bpc
&&
3626 !rctx
->ps_shader
->current
->ps_depth_export
;
3628 db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
3629 S_02880C_DUAL_EXPORT_ENABLE(dual_export
) |
3630 S_02880C_DB_SOURCE_FORMAT(dual_export
? V_02880C_EXPORT_DB_TWO
:
3631 V_02880C_EXPORT_DB_FULL
) |
3632 S_02880C_ALPHA_TO_MASK_DISABLE(rctx
->framebuffer
.cb0_is_integer
);
3634 /* When alpha test is enabled we can't trust the hw to make the proper
3635 * decision on the order in which ztest should be run related to fragment
3638 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3639 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3640 * execution and thus after alpha test so if discarded by the alpha test
3641 * the z value is not written.
3642 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3643 * get a hang unless you flush the DB in between. For now just use
3646 if (rctx
->alphatest_state
.sx_alpha_test_control
|| rctx
->ps_shader
->info
.writes_memory
) {
3647 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
3649 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
3652 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
) {
3653 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
3654 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
3658 static void evergreen_dma_copy_tile(struct r600_context
*rctx
,
3659 struct pipe_resource
*dst
,
3664 struct pipe_resource
*src
,
3669 unsigned copy_height
,
3673 struct radeon_winsys_cs
*cs
= rctx
->b
.dma
.cs
;
3674 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3675 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3676 unsigned array_mode
, lbpp
, pitch_tile_max
, slice_tile_max
, size
;
3677 unsigned ncopy
, height
, cheight
, detile
, i
, x
, y
, z
, src_mode
, dst_mode
;
3678 unsigned sub_cmd
, bank_h
, bank_w
, mt_aspect
, nbanks
, tile_split
, non_disp_tiling
= 0;
3679 uint64_t base
, addr
;
3681 dst_mode
= rdst
->surface
.u
.legacy
.level
[dst_level
].mode
;
3682 src_mode
= rsrc
->surface
.u
.legacy
.level
[src_level
].mode
;
3683 assert(dst_mode
!= src_mode
);
3685 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3686 if (util_format_has_depth(util_format_description(src
->format
)))
3687 non_disp_tiling
= 1;
3690 sub_cmd
= EG_DMA_COPY_TILED
;
3691 lbpp
= util_logbase2(bpp
);
3692 pitch_tile_max
= ((pitch
/ bpp
) / 8) - 1;
3693 nbanks
= eg_num_banks(rctx
->screen
->b
.info
.r600_num_banks
);
3695 if (dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
) {
3697 array_mode
= evergreen_array_mode(src_mode
);
3698 slice_tile_max
= (rsrc
->surface
.u
.legacy
.level
[src_level
].nblk_x
* rsrc
->surface
.u
.legacy
.level
[src_level
].nblk_y
) / (8*8);
3699 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3700 /* linear height must be the same as the slice tile max height, it's ok even
3701 * if the linear destination/source have smaller heigh as the size of the
3702 * dma packet will be using the copy_height which is always smaller or equal
3703 * to the linear height
3705 height
= u_minify(rsrc
->resource
.b
.b
.height0
, src_level
);
3710 base
= rsrc
->surface
.u
.legacy
.level
[src_level
].offset
;
3711 addr
= rdst
->surface
.u
.legacy
.level
[dst_level
].offset
;
3712 addr
+= (uint64_t)rdst
->surface
.u
.legacy
.level
[dst_level
].slice_size_dw
* 4 * dst_z
;
3713 addr
+= dst_y
* pitch
+ dst_x
* bpp
;
3714 bank_h
= eg_bank_wh(rsrc
->surface
.u
.legacy
.bankh
);
3715 bank_w
= eg_bank_wh(rsrc
->surface
.u
.legacy
.bankw
);
3716 mt_aspect
= eg_macro_tile_aspect(rsrc
->surface
.u
.legacy
.mtilea
);
3717 tile_split
= eg_tile_split(rsrc
->surface
.u
.legacy
.tile_split
);
3718 base
+= rsrc
->resource
.gpu_address
;
3719 addr
+= rdst
->resource
.gpu_address
;
3722 array_mode
= evergreen_array_mode(dst_mode
);
3723 slice_tile_max
= (rdst
->surface
.u
.legacy
.level
[dst_level
].nblk_x
* rdst
->surface
.u
.legacy
.level
[dst_level
].nblk_y
) / (8*8);
3724 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3725 /* linear height must be the same as the slice tile max height, it's ok even
3726 * if the linear destination/source have smaller heigh as the size of the
3727 * dma packet will be using the copy_height which is always smaller or equal
3728 * to the linear height
3730 height
= u_minify(rdst
->resource
.b
.b
.height0
, dst_level
);
3735 base
= rdst
->surface
.u
.legacy
.level
[dst_level
].offset
;
3736 addr
= rsrc
->surface
.u
.legacy
.level
[src_level
].offset
;
3737 addr
+= (uint64_t)rsrc
->surface
.u
.legacy
.level
[src_level
].slice_size_dw
* 4 * src_z
;
3738 addr
+= src_y
* pitch
+ src_x
* bpp
;
3739 bank_h
= eg_bank_wh(rdst
->surface
.u
.legacy
.bankh
);
3740 bank_w
= eg_bank_wh(rdst
->surface
.u
.legacy
.bankw
);
3741 mt_aspect
= eg_macro_tile_aspect(rdst
->surface
.u
.legacy
.mtilea
);
3742 tile_split
= eg_tile_split(rdst
->surface
.u
.legacy
.tile_split
);
3743 base
+= rdst
->resource
.gpu_address
;
3744 addr
+= rsrc
->resource
.gpu_address
;
3747 size
= (copy_height
* pitch
) / 4;
3748 ncopy
= (size
/ EG_DMA_COPY_MAX_SIZE
) + !!(size
% EG_DMA_COPY_MAX_SIZE
);
3749 r600_need_dma_space(&rctx
->b
, ncopy
* 9, &rdst
->resource
, &rsrc
->resource
);
3751 for (i
= 0; i
< ncopy
; i
++) {
3752 cheight
= copy_height
;
3753 if (((cheight
* pitch
) / 4) > EG_DMA_COPY_MAX_SIZE
) {
3754 cheight
= (EG_DMA_COPY_MAX_SIZE
* 4) / pitch
;
3756 size
= (cheight
* pitch
) / 4;
3757 /* emit reloc before writing cs so that cs is always in consistent state */
3758 radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.dma
, &rsrc
->resource
,
3759 RADEON_USAGE_READ
, RADEON_PRIO_SDMA_TEXTURE
);
3760 radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.dma
, &rdst
->resource
,
3761 RADEON_USAGE_WRITE
, RADEON_PRIO_SDMA_TEXTURE
);
3762 radeon_emit(cs
, DMA_PACKET(DMA_PACKET_COPY
, sub_cmd
, size
));
3763 radeon_emit(cs
, base
>> 8);
3764 radeon_emit(cs
, (detile
<< 31) | (array_mode
<< 27) |
3765 (lbpp
<< 24) | (bank_h
<< 21) |
3766 (bank_w
<< 18) | (mt_aspect
<< 16));
3767 radeon_emit(cs
, (pitch_tile_max
<< 0) | ((height
- 1) << 16));
3768 radeon_emit(cs
, (slice_tile_max
<< 0));
3769 radeon_emit(cs
, (x
<< 0) | (z
<< 18));
3770 radeon_emit(cs
, (y
<< 0) | (tile_split
<< 21) | (nbanks
<< 25) | (non_disp_tiling
<< 28));
3771 radeon_emit(cs
, addr
& 0xfffffffc);
3772 radeon_emit(cs
, (addr
>> 32UL) & 0xff);
3773 copy_height
-= cheight
;
3774 addr
+= cheight
* pitch
;
3779 static void evergreen_dma_copy(struct pipe_context
*ctx
,
3780 struct pipe_resource
*dst
,
3782 unsigned dstx
, unsigned dsty
, unsigned dstz
,
3783 struct pipe_resource
*src
,
3785 const struct pipe_box
*src_box
)
3787 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3788 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3789 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3790 unsigned dst_pitch
, src_pitch
, bpp
, dst_mode
, src_mode
, copy_height
;
3791 unsigned src_w
, dst_w
;
3792 unsigned src_x
, src_y
;
3793 unsigned dst_x
= dstx
, dst_y
= dsty
, dst_z
= dstz
;
3795 if (rctx
->b
.dma
.cs
== NULL
) {
3799 if (rctx
->cmd_buf_is_compute
) {
3800 rctx
->b
.gfx
.flush(rctx
, PIPE_FLUSH_ASYNC
, NULL
);
3801 rctx
->cmd_buf_is_compute
= false;
3804 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
3805 evergreen_dma_copy_buffer(rctx
, dst
, src
, dst_x
, src_box
->x
, src_box
->width
);
3809 if (src_box
->depth
> 1 ||
3810 !r600_prepare_for_dma_blit(&rctx
->b
, rdst
, dst_level
, dstx
, dsty
,
3811 dstz
, rsrc
, src_level
, src_box
))
3814 src_x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
3815 dst_x
= util_format_get_nblocksx(src
->format
, dst_x
);
3816 src_y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
3817 dst_y
= util_format_get_nblocksy(src
->format
, dst_y
);
3819 bpp
= rdst
->surface
.bpe
;
3820 dst_pitch
= rdst
->surface
.u
.legacy
.level
[dst_level
].nblk_x
* rdst
->surface
.bpe
;
3821 src_pitch
= rsrc
->surface
.u
.legacy
.level
[src_level
].nblk_x
* rsrc
->surface
.bpe
;
3822 src_w
= u_minify(rsrc
->resource
.b
.b
.width0
, src_level
);
3823 dst_w
= u_minify(rdst
->resource
.b
.b
.width0
, dst_level
);
3824 copy_height
= src_box
->height
/ rsrc
->surface
.blk_h
;
3826 dst_mode
= rdst
->surface
.u
.legacy
.level
[dst_level
].mode
;
3827 src_mode
= rsrc
->surface
.u
.legacy
.level
[src_level
].mode
;
3829 if (src_pitch
!= dst_pitch
|| src_box
->x
|| dst_x
|| src_w
!= dst_w
) {
3830 /* FIXME evergreen can do partial blit */
3833 /* the x test here are currently useless (because we don't support partial blit)
3834 * but keep them around so we don't forget about those
3836 if (src_pitch
% 8 || src_box
->x
% 8 || dst_x
% 8 || src_box
->y
% 8 || dst_y
% 8) {
3840 /* 128 bpp surfaces require non_disp_tiling for both
3841 * tiled and linear buffers on cayman. However, async
3842 * DMA only supports it on the tiled side. As such
3843 * the tile order is backwards after a L2T/T2L packet.
3845 if ((rctx
->b
.chip_class
== CAYMAN
) &&
3846 (src_mode
!= dst_mode
) &&
3847 (util_format_get_blocksize(src
->format
) >= 16)) {
3851 if (src_mode
== dst_mode
) {
3852 uint64_t dst_offset
, src_offset
;
3853 /* simple dma blit would do NOTE code here assume :
3856 * dst_pitch == src_pitch
3858 src_offset
= rsrc
->surface
.u
.legacy
.level
[src_level
].offset
;
3859 src_offset
+= (uint64_t)rsrc
->surface
.u
.legacy
.level
[src_level
].slice_size_dw
* 4 * src_box
->z
;
3860 src_offset
+= src_y
* src_pitch
+ src_x
* bpp
;
3861 dst_offset
= rdst
->surface
.u
.legacy
.level
[dst_level
].offset
;
3862 dst_offset
+= (uint64_t)rdst
->surface
.u
.legacy
.level
[dst_level
].slice_size_dw
* 4 * dst_z
;
3863 dst_offset
+= dst_y
* dst_pitch
+ dst_x
* bpp
;
3864 evergreen_dma_copy_buffer(rctx
, dst
, src
, dst_offset
, src_offset
,
3865 src_box
->height
* src_pitch
);
3867 evergreen_dma_copy_tile(rctx
, dst
, dst_level
, dst_x
, dst_y
, dst_z
,
3868 src
, src_level
, src_x
, src_y
, src_box
->z
,
3869 copy_height
, dst_pitch
, bpp
);
3874 r600_resource_copy_region(ctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
3875 src
, src_level
, src_box
);
3878 static void evergreen_set_tess_state(struct pipe_context
*ctx
,
3879 const float default_outer_level
[4],
3880 const float default_inner_level
[2])
3882 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3884 memcpy(rctx
->tess_state
, default_outer_level
, sizeof(float) * 4);
3885 memcpy(rctx
->tess_state
+4, default_inner_level
, sizeof(float) * 2);
3886 rctx
->driver_consts
[PIPE_SHADER_TESS_CTRL
].tcs_default_levels_dirty
= true;
3889 static void evergreen_setup_immed_buffer(struct r600_context
*rctx
,
3890 struct r600_image_view
*rview
,
3891 enum pipe_format pformat
)
3893 struct r600_screen
*rscreen
= (struct r600_screen
*)rctx
->b
.b
.screen
;
3894 uint32_t immed_size
= rscreen
->b
.info
.max_se
* 256 * 64 * util_format_get_blocksize(pformat
);
3895 struct eg_buf_res_params buf_params
;
3896 bool skip_reloc
= false;
3897 struct r600_resource
*resource
= (struct r600_resource
*)rview
->base
.resource
;
3898 if (!resource
->immed_buffer
) {
3899 eg_resource_alloc_immed(&rscreen
->b
, resource
, immed_size
);
3902 memset(&buf_params
, 0, sizeof(buf_params
));
3903 buf_params
.pipe_format
= pformat
;
3904 buf_params
.size
= resource
->immed_buffer
->b
.b
.width0
;
3905 buf_params
.swizzle
[0] = PIPE_SWIZZLE_X
;
3906 buf_params
.swizzle
[1] = PIPE_SWIZZLE_Y
;
3907 buf_params
.swizzle
[2] = PIPE_SWIZZLE_Z
;
3908 buf_params
.swizzle
[3] = PIPE_SWIZZLE_W
;
3909 buf_params
.uncached
= 1;
3910 evergreen_fill_buffer_resource_words(rctx
, &resource
->immed_buffer
->b
.b
,
3911 &buf_params
, &skip_reloc
,
3912 rview
->immed_resource_words
);
3915 static void evergreen_set_hw_atomic_buffers(struct pipe_context
*ctx
,
3916 unsigned start_slot
,
3918 const struct pipe_shader_buffer
*buffers
)
3920 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3921 struct r600_atomic_buffer_state
*astate
;
3924 astate
= &rctx
->atomic_buffer_state
;
3926 /* we'd probably like to expand this to 8 later so put the logic in */
3927 for (i
= start_slot
, idx
= 0; i
< start_slot
+ count
; i
++, idx
++) {
3928 const struct pipe_shader_buffer
*buf
;
3929 struct pipe_shader_buffer
*abuf
;
3931 abuf
= &astate
->buffer
[i
];
3933 if (!buffers
|| !buffers
[idx
].buffer
) {
3934 pipe_resource_reference(&abuf
->buffer
, NULL
);
3935 astate
->enabled_mask
&= ~(1 << i
);
3938 buf
= &buffers
[idx
];
3940 pipe_resource_reference(&abuf
->buffer
, buf
->buffer
);
3941 abuf
->buffer_offset
= buf
->buffer_offset
;
3942 abuf
->buffer_size
= buf
->buffer_size
;
3943 astate
->enabled_mask
|= (1 << i
);
3947 static void evergreen_set_shader_buffers(struct pipe_context
*ctx
,
3948 enum pipe_shader_type shader
, unsigned start_slot
,
3950 const struct pipe_shader_buffer
*buffers
)
3952 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3953 struct r600_image_state
*istate
= NULL
;
3954 struct r600_image_view
*rview
;
3955 struct r600_tex_color_info color
;
3956 struct eg_buf_res_params buf_params
;
3957 struct r600_resource
*resource
;
3961 if (shader
!= PIPE_SHADER_FRAGMENT
&&
3962 shader
!= PIPE_SHADER_COMPUTE
&& count
== 0)
3965 if (shader
== PIPE_SHADER_FRAGMENT
)
3966 istate
= &rctx
->fragment_buffers
;
3967 else if (shader
== PIPE_SHADER_COMPUTE
)
3968 istate
= &rctx
->compute_buffers
;
3970 old_mask
= istate
->enabled_mask
;
3971 for (i
= start_slot
, idx
= 0; i
< start_slot
+ count
; i
++, idx
++) {
3972 const struct pipe_shader_buffer
*buf
;
3975 rview
= &istate
->views
[i
];
3977 if (!buffers
|| !buffers
[idx
].buffer
) {
3978 pipe_resource_reference((struct pipe_resource
**)&rview
->base
.resource
, NULL
);
3979 istate
->enabled_mask
&= ~(1 << i
);
3983 buf
= &buffers
[idx
];
3984 pipe_resource_reference((struct pipe_resource
**)&rview
->base
.resource
, buf
->buffer
);
3986 resource
= (struct r600_resource
*)rview
->base
.resource
;
3988 evergreen_setup_immed_buffer(rctx
, rview
, PIPE_FORMAT_R32_UINT
);
3992 evergreen_set_color_surface_buffer(rctx
, resource
,
3993 PIPE_FORMAT_R32_UINT
,
3995 buf
->buffer_offset
+ buf
->buffer_size
,
3998 res_type
= V_028C70_BUFFER
;
4000 rview
->cb_color_base
= color
.offset
;
4001 rview
->cb_color_dim
= color
.dim
;
4002 rview
->cb_color_info
= color
.info
|
4004 S_028C70_RESOURCE_TYPE(res_type
);
4005 rview
->cb_color_pitch
= color
.pitch
;
4006 rview
->cb_color_slice
= color
.slice
;
4007 rview
->cb_color_view
= color
.view
;
4008 rview
->cb_color_attrib
= color
.attrib
;
4009 rview
->cb_color_fmask
= color
.fmask
;
4010 rview
->cb_color_fmask_slice
= color
.fmask_slice
;
4012 memset(&buf_params
, 0, sizeof(buf_params
));
4013 buf_params
.pipe_format
= PIPE_FORMAT_R32_UINT
;
4014 buf_params
.offset
= buf
->buffer_offset
;
4015 buf_params
.size
= buf
->buffer_size
;
4016 buf_params
.swizzle
[0] = PIPE_SWIZZLE_X
;
4017 buf_params
.swizzle
[1] = PIPE_SWIZZLE_Y
;
4018 buf_params
.swizzle
[2] = PIPE_SWIZZLE_Z
;
4019 buf_params
.swizzle
[3] = PIPE_SWIZZLE_W
;
4020 buf_params
.force_swizzle
= true;
4021 buf_params
.uncached
= 1;
4022 evergreen_fill_buffer_resource_words(rctx
, &resource
->b
.b
,
4024 &rview
->skip_mip_address_reloc
,
4025 rview
->resource_words
);
4027 istate
->enabled_mask
|= (1 << i
);
4030 istate
->atom
.num_dw
= util_bitcount(istate
->enabled_mask
) * 46;
4032 if (old_mask
!= istate
->enabled_mask
)
4033 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
4035 if (rctx
->cb_misc_state
.nr_buffer_rats
!= util_bitcount(istate
->enabled_mask
)) {
4036 rctx
->cb_misc_state
.nr_buffer_rats
= util_bitcount(istate
->enabled_mask
);
4037 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
4040 r600_mark_atom_dirty(rctx
, &istate
->atom
);
4043 static void evergreen_set_shader_images(struct pipe_context
*ctx
,
4044 enum pipe_shader_type shader
, unsigned start_slot
,
4046 const struct pipe_image_view
*images
)
4048 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
4050 struct r600_image_view
*rview
;
4051 struct pipe_resource
*image
;
4052 struct r600_resource
*resource
;
4053 struct r600_tex_color_info color
;
4054 struct eg_buf_res_params buf_params
;
4055 struct eg_tex_res_params tex_params
;
4057 struct r600_image_state
*istate
= NULL
;
4059 if (shader
!= PIPE_SHADER_FRAGMENT
&& shader
!= PIPE_SHADER_COMPUTE
&& count
== 0)
4062 if (shader
== PIPE_SHADER_FRAGMENT
)
4063 istate
= &rctx
->fragment_images
;
4064 else if (shader
== PIPE_SHADER_COMPUTE
)
4065 istate
= &rctx
->compute_images
;
4067 assert (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
);
4069 old_mask
= istate
->enabled_mask
;
4070 for (i
= start_slot
, idx
= 0; i
< start_slot
+ count
; i
++, idx
++) {
4072 const struct pipe_image_view
*iview
;
4073 rview
= &istate
->views
[i
];
4075 if (!images
|| !images
[idx
].resource
) {
4076 pipe_resource_reference((struct pipe_resource
**)&rview
->base
.resource
, NULL
);
4077 istate
->enabled_mask
&= ~(1 << i
);
4078 istate
->compressed_colortex_mask
&= ~(1 << i
);
4079 istate
->compressed_depthtex_mask
&= ~(1 << i
);
4083 iview
= &images
[idx
];
4084 image
= iview
->resource
;
4085 resource
= (struct r600_resource
*)image
;
4087 r600_context_add_resource_size(ctx
, image
);
4089 rview
->base
= *iview
;
4090 rview
->base
.resource
= NULL
;
4091 pipe_resource_reference((struct pipe_resource
**)&rview
->base
.resource
, image
);
4093 evergreen_setup_immed_buffer(rctx
, rview
, iview
->format
);
4095 bool is_buffer
= image
->target
== PIPE_BUFFER
;
4096 struct r600_texture
*rtex
= (struct r600_texture
*)image
;
4097 if (!is_buffer
& rtex
->db_compatible
)
4098 istate
->compressed_depthtex_mask
|= 1 << i
;
4100 istate
->compressed_depthtex_mask
&= ~(1 << i
);
4102 if (!is_buffer
&& rtex
->cmask
.size
)
4103 istate
->compressed_colortex_mask
|= 1 << i
;
4105 istate
->compressed_colortex_mask
&= ~(1 << i
);
4108 evergreen_set_color_surface_common(rctx
, rtex
,
4110 iview
->u
.tex
.first_layer
,
4111 iview
->u
.tex
.last_layer
,
4114 color
.dim
= S_028C78_WIDTH_MAX(u_minify(image
->width0
, iview
->u
.tex
.level
) - 1) |
4115 S_028C78_HEIGHT_MAX(u_minify(image
->height0
, iview
->u
.tex
.level
) - 1);
4119 evergreen_set_color_surface_buffer(rctx
, resource
,
4121 iview
->u
.buf
.offset
,
4126 switch (image
->target
) {
4128 res_type
= V_028C70_BUFFER
;
4130 case PIPE_TEXTURE_1D
:
4131 res_type
= V_028C70_TEXTURE1D
;
4133 case PIPE_TEXTURE_1D_ARRAY
:
4134 res_type
= V_028C70_TEXTURE1DARRAY
;
4136 case PIPE_TEXTURE_2D
:
4137 case PIPE_TEXTURE_RECT
:
4138 res_type
= V_028C70_TEXTURE2D
;
4140 case PIPE_TEXTURE_3D
:
4141 res_type
= V_028C70_TEXTURE3D
;
4143 case PIPE_TEXTURE_2D_ARRAY
:
4144 case PIPE_TEXTURE_CUBE
:
4145 case PIPE_TEXTURE_CUBE_ARRAY
:
4146 res_type
= V_028C70_TEXTURE2DARRAY
;
4154 rview
->cb_color_base
= color
.offset
;
4155 rview
->cb_color_dim
= color
.dim
;
4156 rview
->cb_color_info
= color
.info
|
4158 S_028C70_RESOURCE_TYPE(res_type
);
4159 rview
->cb_color_pitch
= color
.pitch
;
4160 rview
->cb_color_slice
= color
.slice
;
4161 rview
->cb_color_view
= color
.view
;
4162 rview
->cb_color_attrib
= color
.attrib
;
4163 rview
->cb_color_fmask
= color
.fmask
;
4164 rview
->cb_color_fmask_slice
= color
.fmask_slice
;
4166 if (image
->target
!= PIPE_BUFFER
) {
4167 memset(&tex_params
, 0, sizeof(tex_params
));
4168 tex_params
.pipe_format
= iview
->format
;
4169 tex_params
.force_level
= 0;
4170 tex_params
.width0
= image
->width0
;
4171 tex_params
.height0
= image
->height0
;
4172 tex_params
.first_level
= iview
->u
.tex
.level
;
4173 tex_params
.last_level
= iview
->u
.tex
.level
;
4174 tex_params
.first_layer
= iview
->u
.tex
.first_layer
;
4175 tex_params
.last_layer
= iview
->u
.tex
.last_layer
;
4176 tex_params
.target
= image
->target
;
4177 tex_params
.swizzle
[0] = PIPE_SWIZZLE_X
;
4178 tex_params
.swizzle
[1] = PIPE_SWIZZLE_Y
;
4179 tex_params
.swizzle
[2] = PIPE_SWIZZLE_Z
;
4180 tex_params
.swizzle
[3] = PIPE_SWIZZLE_W
;
4181 evergreen_fill_tex_resource_words(rctx
, &resource
->b
.b
, &tex_params
,
4182 &rview
->skip_mip_address_reloc
,
4183 rview
->resource_words
);
4186 memset(&buf_params
, 0, sizeof(buf_params
));
4187 buf_params
.pipe_format
= iview
->format
;
4188 buf_params
.size
= iview
->u
.buf
.size
;
4189 buf_params
.offset
= iview
->u
.buf
.offset
;
4190 buf_params
.swizzle
[0] = PIPE_SWIZZLE_X
;
4191 buf_params
.swizzle
[1] = PIPE_SWIZZLE_Y
;
4192 buf_params
.swizzle
[2] = PIPE_SWIZZLE_Z
;
4193 buf_params
.swizzle
[3] = PIPE_SWIZZLE_W
;
4194 evergreen_fill_buffer_resource_words(rctx
, &resource
->b
.b
,
4196 &rview
->skip_mip_address_reloc
,
4197 rview
->resource_words
);
4199 istate
->enabled_mask
|= (1 << i
);
4202 istate
->atom
.num_dw
= util_bitcount(istate
->enabled_mask
) * 46;
4203 istate
->dirty_buffer_constants
= TRUE
;
4204 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
4205 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_CB
|
4206 R600_CONTEXT_FLUSH_AND_INV_CB_META
;
4208 if (old_mask
!= istate
->enabled_mask
)
4209 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
4211 if (rctx
->cb_misc_state
.nr_image_rats
!= util_bitcount(istate
->enabled_mask
)) {
4212 rctx
->cb_misc_state
.nr_image_rats
= util_bitcount(istate
->enabled_mask
);
4213 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
4216 r600_mark_atom_dirty(rctx
, &istate
->atom
);
4219 void evergreen_init_state_functions(struct r600_context
*rctx
)
4224 * To avoid GPU lockup registers must be emitted in a specific order
4225 * (no kidding ...). The order below is important and have been
4226 * partially inferred from analyzing fglrx command stream.
4228 * Don't reorder atom without carefully checking the effect (GPU lockup
4229 * or piglit regression).
4232 if (rctx
->b
.chip_class
== EVERGREEN
) {
4233 r600_init_atom(rctx
, &rctx
->config_state
.atom
, id
++, evergreen_emit_config_state
, 11);
4234 rctx
->config_state
.dyn_gpr_enabled
= true;
4236 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, evergreen_emit_framebuffer_state
, 0);
4237 r600_init_atom(rctx
, &rctx
->fragment_images
.atom
, id
++, evergreen_emit_fragment_image_state
, 0);
4238 r600_init_atom(rctx
, &rctx
->compute_images
.atom
, id
++, evergreen_emit_compute_image_state
, 0);
4239 r600_init_atom(rctx
, &rctx
->fragment_buffers
.atom
, id
++, evergreen_emit_fragment_buffer_state
, 0);
4240 r600_init_atom(rctx
, &rctx
->compute_buffers
.atom
, id
++, evergreen_emit_compute_buffer_state
, 0);
4242 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, evergreen_emit_vs_constant_buffers
, 0);
4243 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, evergreen_emit_gs_constant_buffers
, 0);
4244 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, evergreen_emit_ps_constant_buffers
, 0);
4245 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_TESS_CTRL
].atom
, id
++, evergreen_emit_tcs_constant_buffers
, 0);
4246 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_TESS_EVAL
].atom
, id
++, evergreen_emit_tes_constant_buffers
, 0);
4247 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_COMPUTE
].atom
, id
++, evergreen_emit_cs_constant_buffers
, 0);
4248 /* shader program */
4249 r600_init_atom(rctx
, &rctx
->cs_shader_state
.atom
, id
++, evergreen_emit_cs_shader
, 0);
4251 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, evergreen_emit_vs_sampler_states
, 0);
4252 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, evergreen_emit_gs_sampler_states
, 0);
4253 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_CTRL
].states
.atom
, id
++, evergreen_emit_tcs_sampler_states
, 0);
4254 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_EVAL
].states
.atom
, id
++, evergreen_emit_tes_sampler_states
, 0);
4255 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, evergreen_emit_ps_sampler_states
, 0);
4256 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
].states
.atom
, id
++, evergreen_emit_cs_sampler_states
, 0);
4258 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, evergreen_fs_emit_vertex_buffers
, 0);
4259 r600_init_atom(rctx
, &rctx
->cs_vertex_buffer_state
.atom
, id
++, evergreen_cs_emit_vertex_buffers
, 0);
4260 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, evergreen_emit_vs_sampler_views
, 0);
4261 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, evergreen_emit_gs_sampler_views
, 0);
4262 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_CTRL
].views
.atom
, id
++, evergreen_emit_tcs_sampler_views
, 0);
4263 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_EVAL
].views
.atom
, id
++, evergreen_emit_tes_sampler_views
, 0);
4264 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, evergreen_emit_ps_sampler_views
, 0);
4265 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
].views
.atom
, id
++, evergreen_emit_cs_sampler_views
, 0);
4267 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 10);
4269 if (rctx
->b
.chip_class
== EVERGREEN
) {
4270 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, evergreen_emit_sample_mask
, 3);
4272 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, cayman_emit_sample_mask
, 4);
4274 rctx
->sample_mask
.sample_mask
= ~0;
4276 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
4277 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
4278 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
4279 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, evergreen_emit_cb_misc_state
, 4);
4280 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 9);
4281 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, evergreen_emit_clip_state
, 26);
4282 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, evergreen_emit_db_misc_state
, 10);
4283 r600_init_atom(rctx
, &rctx
->db_state
.atom
, id
++, evergreen_emit_db_state
, 14);
4284 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
4285 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, evergreen_emit_polygon_offset
, 9);
4286 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
4287 r600_add_atom(rctx
, &rctx
->b
.scissors
.atom
, id
++);
4288 r600_add_atom(rctx
, &rctx
->b
.viewports
.atom
, id
++);
4289 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
4290 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, evergreen_emit_vertex_fetch_shader
, 5);
4291 r600_add_atom(rctx
, &rctx
->b
.render_cond_atom
, id
++);
4292 r600_add_atom(rctx
, &rctx
->b
.streamout
.begin_atom
, id
++);
4293 r600_add_atom(rctx
, &rctx
->b
.streamout
.enable_atom
, id
++);
4294 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++)
4295 r600_init_atom(rctx
, &rctx
->hw_shader_stages
[i
].atom
, id
++, r600_emit_shader
, 0);
4296 r600_init_atom(rctx
, &rctx
->shader_stages
.atom
, id
++, evergreen_emit_shader_stages
, 15);
4297 r600_init_atom(rctx
, &rctx
->gs_rings
.atom
, id
++, evergreen_emit_gs_rings
, 26);
4299 rctx
->b
.b
.create_blend_state
= evergreen_create_blend_state
;
4300 rctx
->b
.b
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
4301 rctx
->b
.b
.create_rasterizer_state
= evergreen_create_rs_state
;
4302 rctx
->b
.b
.create_sampler_state
= evergreen_create_sampler_state
;
4303 rctx
->b
.b
.create_sampler_view
= evergreen_create_sampler_view
;
4304 rctx
->b
.b
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
4305 rctx
->b
.b
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
4306 rctx
->b
.b
.set_min_samples
= evergreen_set_min_samples
;
4307 rctx
->b
.b
.set_tess_state
= evergreen_set_tess_state
;
4308 rctx
->b
.b
.set_hw_atomic_buffers
= evergreen_set_hw_atomic_buffers
;
4309 rctx
->b
.b
.set_shader_images
= evergreen_set_shader_images
;
4310 rctx
->b
.b
.set_shader_buffers
= evergreen_set_shader_buffers
;
4311 if (rctx
->b
.chip_class
== EVERGREEN
)
4312 rctx
->b
.b
.get_sample_position
= evergreen_get_sample_position
;
4314 rctx
->b
.b
.get_sample_position
= cayman_get_sample_position
;
4315 rctx
->b
.dma_copy
= evergreen_dma_copy
;
4317 evergreen_init_compute_state_functions(rctx
);
4321 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
4323 * The information about LDS and other non-compile-time parameters is then
4324 * written to the const buffer.
4326 * const buffer contains -
4327 * uint32_t input_patch_size
4328 * uint32_t input_vertex_size
4329 * uint32_t num_tcs_input_cp
4330 * uint32_t num_tcs_output_cp;
4331 * uint32_t output_patch_size
4332 * uint32_t output_vertex_size
4333 * uint32_t output_patch0_offset
4334 * uint32_t perpatch_output_offset
4335 * and the same constbuf is bound to LS/HS/VS(ES).
4337 void evergreen_setup_tess_constants(struct r600_context
*rctx
, const struct pipe_draw_info
*info
, unsigned *num_patches
)
4339 struct pipe_constant_buffer constbuf
= {0};
4340 struct r600_pipe_shader_selector
*tcs
= rctx
->tcs_shader
? rctx
->tcs_shader
: rctx
->tes_shader
;
4341 struct r600_pipe_shader_selector
*ls
= rctx
->vs_shader
;
4342 unsigned num_tcs_input_cp
= info
->vertices_per_patch
;
4343 unsigned num_tcs_outputs
;
4344 unsigned num_tcs_output_cp
;
4345 unsigned num_tcs_patch_outputs
;
4346 unsigned num_tcs_inputs
;
4347 unsigned input_vertex_size
, output_vertex_size
;
4348 unsigned input_patch_size
, pervertex_output_patch_size
, output_patch_size
;
4349 unsigned output_patch0_offset
, perpatch_output_offset
, lds_size
;
4352 unsigned num_pipes
= rctx
->screen
->b
.info
.r600_max_quad_pipes
;
4353 unsigned wave_divisor
= (16 * num_pipes
);
4357 if (!rctx
->tes_shader
) {
4358 rctx
->lds_alloc
= 0;
4359 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
4360 R600_LDS_INFO_CONST_BUFFER
, NULL
);
4361 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_CTRL
,
4362 R600_LDS_INFO_CONST_BUFFER
, NULL
);
4363 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
4364 R600_LDS_INFO_CONST_BUFFER
, NULL
);
4368 if (rctx
->lds_alloc
!= 0 &&
4369 rctx
->last_ls
== ls
&&
4370 rctx
->last_num_tcs_input_cp
== num_tcs_input_cp
&&
4371 rctx
->last_tcs
== tcs
)
4374 num_tcs_inputs
= util_last_bit64(ls
->lds_outputs_written_mask
);
4376 if (rctx
->tcs_shader
) {
4377 num_tcs_outputs
= util_last_bit64(tcs
->lds_outputs_written_mask
);
4378 num_tcs_output_cp
= tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
4379 num_tcs_patch_outputs
= util_last_bit64(tcs
->lds_patch_outputs_written_mask
);
4381 num_tcs_outputs
= num_tcs_inputs
;
4382 num_tcs_output_cp
= num_tcs_input_cp
;
4383 num_tcs_patch_outputs
= 2; /* TESSINNER + TESSOUTER */
4387 input_vertex_size
= num_tcs_inputs
* 16;
4388 output_vertex_size
= num_tcs_outputs
* 16;
4390 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
4392 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
4393 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
4395 output_patch0_offset
= rctx
->tcs_shader
? input_patch_size
* *num_patches
: 0;
4396 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
4398 lds_size
= output_patch0_offset
+ output_patch_size
* *num_patches
;
4400 values
[0] = input_patch_size
;
4401 values
[1] = input_vertex_size
;
4402 values
[2] = num_tcs_input_cp
;
4403 values
[3] = num_tcs_output_cp
;
4405 values
[4] = output_patch_size
;
4406 values
[5] = output_vertex_size
;
4407 values
[6] = output_patch0_offset
;
4408 values
[7] = perpatch_output_offset
;
4410 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
4411 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
4412 num_waves
= ceilf((float)(*num_patches
* num_tcs_output_cp
) / (float)wave_divisor
);
4414 rctx
->lds_alloc
= (lds_size
| (num_waves
<< 14));
4417 rctx
->last_tcs
= tcs
;
4418 rctx
->last_num_tcs_input_cp
= num_tcs_input_cp
;
4420 constbuf
.user_buffer
= values
;
4421 constbuf
.buffer_size
= 8 * 4;
4423 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
4424 R600_LDS_INFO_CONST_BUFFER
, &constbuf
);
4425 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_CTRL
,
4426 R600_LDS_INFO_CONST_BUFFER
, &constbuf
);
4427 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
4428 R600_LDS_INFO_CONST_BUFFER
, &constbuf
);
4429 pipe_resource_reference(&constbuf
.buffer
, NULL
);
4432 uint32_t evergreen_get_ls_hs_config(struct r600_context
*rctx
,
4433 const struct pipe_draw_info
*info
,
4434 unsigned num_patches
)
4436 unsigned num_output_cp
;
4438 if (!rctx
->tes_shader
)
4441 num_output_cp
= rctx
->tcs_shader
?
4442 rctx
->tcs_shader
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] :
4443 info
->vertices_per_patch
;
4445 return S_028B58_NUM_PATCHES(num_patches
) |
4446 S_028B58_HS_NUM_INPUT_CP(info
->vertices_per_patch
) |
4447 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp
);
4450 void evergreen_set_ls_hs_config(struct r600_context
*rctx
,
4451 struct radeon_winsys_cs
*cs
,
4452 uint32_t ls_hs_config
)
4454 radeon_set_context_reg(cs
, R_028B58_VGT_LS_HS_CONFIG
, ls_hs_config
);
4457 void evergreen_set_lds_alloc(struct r600_context
*rctx
,
4458 struct radeon_winsys_cs
*cs
,
4461 radeon_set_context_reg(cs
, R_0288E8_SQ_LDS_ALLOC
, lds_alloc
);
4464 /* on evergreen if you are running tessellation you need to disable dynamic
4465 GPRs to workaround a hardware bug.*/
4466 bool evergreen_adjust_gprs(struct r600_context
*rctx
)
4468 unsigned num_gprs
[EG_NUM_HW_STAGES
];
4469 unsigned def_gprs
[EG_NUM_HW_STAGES
];
4470 unsigned cur_gprs
[EG_NUM_HW_STAGES
];
4471 unsigned new_gprs
[EG_NUM_HW_STAGES
];
4472 unsigned def_num_clause_temp_gprs
= rctx
->r6xx_num_clause_temp_gprs
;
4475 unsigned total_gprs
;
4477 bool rework
= false, set_default
= false, set_dirty
= false;
4479 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4480 def_gprs
[i
] = rctx
->default_gprs
[i
];
4481 max_gprs
+= def_gprs
[i
];
4483 max_gprs
+= def_num_clause_temp_gprs
* 2;
4485 /* if we have no TESS and dyn gpr is enabled then do nothing. */
4486 if (!rctx
->hw_shader_stages
[EG_HW_STAGE_HS
].shader
) {
4487 if (rctx
->config_state
.dyn_gpr_enabled
)
4490 /* transition back to dyn gpr enabled state */
4491 rctx
->config_state
.dyn_gpr_enabled
= true;
4492 r600_mark_atom_dirty(rctx
, &rctx
->config_state
.atom
);
4493 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
4498 /* gather required shader gprs */
4499 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4500 if (rctx
->hw_shader_stages
[i
].shader
)
4501 num_gprs
[i
] = rctx
->hw_shader_stages
[i
].shader
->shader
.bc
.ngpr
;
4506 cur_gprs
[R600_HW_STAGE_PS
] = G_008C04_NUM_PS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
4507 cur_gprs
[R600_HW_STAGE_VS
] = G_008C04_NUM_VS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
4508 cur_gprs
[R600_HW_STAGE_GS
] = G_008C08_NUM_GS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_2
);
4509 cur_gprs
[R600_HW_STAGE_ES
] = G_008C08_NUM_ES_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_2
);
4510 cur_gprs
[EG_HW_STAGE_LS
] = G_008C0C_NUM_LS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_3
);
4511 cur_gprs
[EG_HW_STAGE_HS
] = G_008C0C_NUM_HS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_3
);
4514 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4515 new_gprs
[i
] = num_gprs
[i
];
4516 total_gprs
+= num_gprs
[i
];
4519 if (total_gprs
> (max_gprs
- (2 * def_num_clause_temp_gprs
)))
4522 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4523 if (new_gprs
[i
] > cur_gprs
[i
]) {
4529 if (rctx
->config_state
.dyn_gpr_enabled
) {
4531 rctx
->config_state
.dyn_gpr_enabled
= false;
4536 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4537 if (new_gprs
[i
] > def_gprs
[i
])
4538 set_default
= false;
4542 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
4543 new_gprs
[i
] = def_gprs
[i
];
4546 unsigned ps_value
= max_gprs
;
4548 ps_value
-= (def_num_clause_temp_gprs
* 2);
4549 for (i
= R600_HW_STAGE_VS
; i
< EG_NUM_HW_STAGES
; i
++)
4550 ps_value
-= new_gprs
[i
];
4552 new_gprs
[R600_HW_STAGE_PS
] = ps_value
;
4555 tmp
[0] = S_008C04_NUM_PS_GPRS(new_gprs
[R600_HW_STAGE_PS
]) |
4556 S_008C04_NUM_VS_GPRS(new_gprs
[R600_HW_STAGE_VS
]) |
4557 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs
);
4559 tmp
[1] = S_008C08_NUM_ES_GPRS(new_gprs
[R600_HW_STAGE_ES
]) |
4560 S_008C08_NUM_GS_GPRS(new_gprs
[R600_HW_STAGE_GS
]);
4562 tmp
[2] = S_008C0C_NUM_HS_GPRS(new_gprs
[EG_HW_STAGE_HS
]) |
4563 S_008C0C_NUM_LS_GPRS(new_gprs
[EG_HW_STAGE_LS
]);
4565 if (rctx
->config_state
.sq_gpr_resource_mgmt_1
!= tmp
[0] ||
4566 rctx
->config_state
.sq_gpr_resource_mgmt_2
!= tmp
[1] ||
4567 rctx
->config_state
.sq_gpr_resource_mgmt_3
!= tmp
[2]) {
4568 rctx
->config_state
.sq_gpr_resource_mgmt_1
= tmp
[0];
4569 rctx
->config_state
.sq_gpr_resource_mgmt_2
= tmp
[1];
4570 rctx
->config_state
.sq_gpr_resource_mgmt_3
= tmp
[2];
4577 r600_mark_atom_dirty(rctx
, &rctx
->config_state
.atom
);
4578 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
4583 #define AC_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
4585 void eg_trace_emit(struct r600_context
*rctx
)
4587 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
4590 if (rctx
->b
.chip_class
< EVERGREEN
)
4593 /* This must be done after r600_need_cs_space. */
4594 reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
4595 (struct r600_resource
*)rctx
->trace_buf
, RADEON_USAGE_WRITE
,
4596 RADEON_PRIO_CP_DMA
);
4599 radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rctx
->trace_buf
,
4600 RADEON_USAGE_READWRITE
, RADEON_PRIO_TRACE
);
4601 radeon_emit(cs
, PKT3(PKT3_MEM_WRITE
, 3, 0));
4602 radeon_emit(cs
, rctx
->trace_buf
->gpu_address
);
4603 radeon_emit(cs
, rctx
->trace_buf
->gpu_address
>> 32 | MEM_WRITE_32_BITS
| MEM_WRITE_CONFIRM
);
4604 radeon_emit(cs
, rctx
->trace_id
);
4606 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
4607 radeon_emit(cs
, reloc
);
4608 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
4609 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(rctx
->trace_id
));
4612 static void evergreen_emit_set_append_cnt(struct r600_context
*rctx
,
4613 struct r600_shader_atomic
*atomic
,
4614 struct r600_resource
*resource
,
4617 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
4618 unsigned reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
4621 RADEON_PRIO_SHADER_RW_BUFFER
);
4622 uint64_t dst_offset
= resource
->gpu_address
+ (atomic
->start
* 4);
4623 uint32_t base_reg_0
= R_02872C_GDS_APPEND_COUNT_0
;
4625 uint32_t reg_val
= (base_reg_0
+ atomic
->hw_idx
* 4 - EVERGREEN_CONTEXT_REG_OFFSET
) >> 2;
4627 radeon_emit(cs
, PKT3(PKT3_SET_APPEND_CNT
, 2, 0) | pkt_flags
);
4628 radeon_emit(cs
, (reg_val
<< 16) | 0x3);
4629 radeon_emit(cs
, dst_offset
& 0xfffffffc);
4630 radeon_emit(cs
, (dst_offset
>> 32) & 0xff);
4631 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
4632 radeon_emit(cs
, reloc
);
4635 static void evergreen_emit_event_write_eos(struct r600_context
*rctx
,
4636 struct r600_shader_atomic
*atomic
,
4637 struct r600_resource
*resource
,
4640 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
4641 uint32_t event
= EVENT_TYPE_PS_DONE
;
4642 uint32_t base_reg_0
= R_02872C_GDS_APPEND_COUNT_0
;
4643 uint32_t reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
4646 RADEON_PRIO_SHADER_RW_BUFFER
);
4647 uint64_t dst_offset
= resource
->gpu_address
+ (atomic
->start
* 4);
4648 uint32_t reg_val
= (base_reg_0
+ atomic
->hw_idx
* 4) >> 2;
4650 if (pkt_flags
== RADEON_CP_PACKET3_COMPUTE_MODE
)
4651 event
= EVENT_TYPE_CS_DONE
;
4653 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOS
, 3, 0) | pkt_flags
);
4654 radeon_emit(cs
, EVENT_TYPE(event
) | EVENT_INDEX(6));
4655 radeon_emit(cs
, (dst_offset
) & 0xffffffff);
4656 radeon_emit(cs
, (0 << 29) | ((dst_offset
>> 32) & 0xff));
4657 radeon_emit(cs
, reg_val
);
4658 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
4659 radeon_emit(cs
, reloc
);
4662 static void cayman_emit_event_write_eos(struct r600_context
*rctx
,
4663 struct r600_shader_atomic
*atomic
,
4664 struct r600_resource
*resource
,
4667 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
4668 uint32_t event
= EVENT_TYPE_PS_DONE
;
4669 uint32_t reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
4672 RADEON_PRIO_SHADER_RW_BUFFER
);
4673 uint64_t dst_offset
= resource
->gpu_address
+ (atomic
->start
* 4);
4675 if (pkt_flags
== RADEON_CP_PACKET3_COMPUTE_MODE
)
4676 event
= EVENT_TYPE_CS_DONE
;
4678 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOS
, 3, 0) | pkt_flags
);
4679 radeon_emit(cs
, EVENT_TYPE(event
) | EVENT_INDEX(6));
4680 radeon_emit(cs
, (dst_offset
) & 0xffffffff);
4681 radeon_emit(cs
, (1 << 29) | ((dst_offset
>> 32) & 0xff));
4682 radeon_emit(cs
, (atomic
->hw_idx
) | (1 << 16));
4683 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
4684 radeon_emit(cs
, reloc
);
4687 /* writes count from a buffer into GDS */
4688 static void cayman_write_count_to_gds(struct r600_context
*rctx
,
4689 struct r600_shader_atomic
*atomic
,
4690 struct r600_resource
*resource
,
4693 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
4694 unsigned reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
4697 RADEON_PRIO_SHADER_RW_BUFFER
);
4698 uint64_t dst_offset
= resource
->gpu_address
+ (atomic
->start
* 4);
4700 radeon_emit(cs
, PKT3(PKT3_CP_DMA
, 4, 0) | pkt_flags
);
4701 radeon_emit(cs
, dst_offset
& 0xffffffff);
4702 radeon_emit(cs
, PKT3_CP_DMA_CP_SYNC
| PKT3_CP_DMA_DST_SEL(1) | ((dst_offset
>> 32) & 0xff));// GDS
4703 radeon_emit(cs
, atomic
->hw_idx
* 4);
4705 radeon_emit(cs
, PKT3_CP_DMA_CMD_DAS
| 4);
4706 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
4707 radeon_emit(cs
, reloc
);
4710 bool evergreen_emit_atomic_buffer_setup(struct r600_context
*rctx
,
4711 struct r600_pipe_shader
*cs_shader
,
4712 struct r600_shader_atomic
*combined_atomics
,
4713 uint8_t *atomic_used_mask_p
)
4715 struct r600_atomic_buffer_state
*astate
= &rctx
->atomic_buffer_state
;
4716 unsigned pkt_flags
= 0;
4717 uint8_t atomic_used_mask
= 0;
4719 bool is_compute
= cs_shader
? true : false;
4722 pkt_flags
= RADEON_CP_PACKET3_COMPUTE_MODE
;
4724 for (i
= 0; i
< (is_compute
? 1 : EG_NUM_HW_STAGES
); i
++) {
4725 uint8_t num_atomic_stage
;
4726 struct r600_pipe_shader
*pshader
;
4729 pshader
= cs_shader
;
4731 pshader
= rctx
->hw_shader_stages
[i
].shader
;
4735 num_atomic_stage
= pshader
->shader
.nhwatomic_ranges
;
4736 if (!num_atomic_stage
)
4739 for (j
= 0; j
< num_atomic_stage
; j
++) {
4740 struct r600_shader_atomic
*atomic
= &pshader
->shader
.atomics
[j
];
4741 int natomics
= atomic
->end
- atomic
->start
+ 1;
4743 for (k
= 0; k
< natomics
; k
++) {
4744 /* seen this in a previous stage */
4745 if (atomic_used_mask
& (1u << (atomic
->hw_idx
+ k
)))
4748 combined_atomics
[atomic
->hw_idx
+ k
].hw_idx
= atomic
->hw_idx
+ k
;
4749 combined_atomics
[atomic
->hw_idx
+ k
].buffer_id
= atomic
->buffer_id
;
4750 combined_atomics
[atomic
->hw_idx
+ k
].start
= atomic
->start
+ k
;
4751 combined_atomics
[atomic
->hw_idx
+ k
].end
= combined_atomics
[atomic
->hw_idx
+ k
].start
+ 1;
4752 atomic_used_mask
|= (1u << (atomic
->hw_idx
+ k
));
4757 uint32_t mask
= atomic_used_mask
;
4759 unsigned atomic_index
= u_bit_scan(&mask
);
4760 struct r600_shader_atomic
*atomic
= &combined_atomics
[atomic_index
];
4761 struct r600_resource
*resource
= r600_resource(astate
->buffer
[atomic
->buffer_id
].buffer
);
4764 if (rctx
->b
.chip_class
== CAYMAN
)
4765 cayman_write_count_to_gds(rctx
, atomic
, resource
, pkt_flags
);
4767 evergreen_emit_set_append_cnt(rctx
, atomic
, resource
, pkt_flags
);
4769 *atomic_used_mask_p
= atomic_used_mask
;
4773 void evergreen_emit_atomic_buffer_save(struct r600_context
*rctx
,
4775 struct r600_shader_atomic
*combined_atomics
,
4776 uint8_t *atomic_used_mask_p
)
4778 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
4779 struct r600_atomic_buffer_state
*astate
= &rctx
->atomic_buffer_state
;
4780 uint32_t pkt_flags
= 0;
4781 uint32_t event
= EVENT_TYPE_PS_DONE
;
4782 uint32_t mask
= astate
->enabled_mask
;
4783 uint64_t dst_offset
;
4787 pkt_flags
= RADEON_CP_PACKET3_COMPUTE_MODE
;
4789 mask
= *atomic_used_mask_p
;
4794 unsigned atomic_index
= u_bit_scan(&mask
);
4795 struct r600_shader_atomic
*atomic
= &combined_atomics
[atomic_index
];
4796 struct r600_resource
*resource
= r600_resource(astate
->buffer
[atomic
->buffer_id
].buffer
);
4799 if (rctx
->b
.chip_class
== CAYMAN
)
4800 cayman_emit_event_write_eos(rctx
, atomic
, resource
, pkt_flags
);
4802 evergreen_emit_event_write_eos(rctx
, atomic
, resource
, pkt_flags
);
4805 if (pkt_flags
== RADEON_CP_PACKET3_COMPUTE_MODE
)
4806 event
= EVENT_TYPE_CS_DONE
;
4808 ++rctx
->append_fence_id
;
4809 reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
4810 r600_resource(rctx
->append_fence
),
4811 RADEON_USAGE_READWRITE
,
4812 RADEON_PRIO_SHADER_RW_BUFFER
);
4813 dst_offset
= r600_resource(rctx
->append_fence
)->gpu_address
;
4814 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOS
, 3, 0) | pkt_flags
);
4815 radeon_emit(cs
, EVENT_TYPE(event
) | EVENT_INDEX(6));
4816 radeon_emit(cs
, dst_offset
& 0xffffffff);
4817 radeon_emit(cs
, (2 << 29) | ((dst_offset
>> 32) & 0xff));
4818 radeon_emit(cs
, rctx
->append_fence_id
);
4819 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
4820 radeon_emit(cs
, reloc
);
4822 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0) | pkt_flags
);
4823 radeon_emit(cs
, WAIT_REG_MEM_GEQUAL
| WAIT_REG_MEM_MEMORY
| (1 << 8));
4824 radeon_emit(cs
, dst_offset
& 0xffffffff);
4825 radeon_emit(cs
, ((dst_offset
>> 32) & 0xff));
4826 radeon_emit(cs
, rctx
->append_fence_id
);
4827 radeon_emit(cs
, 0xffffffff);
4828 radeon_emit(cs
, 0xa);
4829 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
4830 radeon_emit(cs
, reloc
);