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r600: add ARB_query_buffer_object support
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600_query.h"
26 #include "evergreend.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_memory.h"
31 #include "util/u_framebuffer.h"
32 #include "util/u_dual_blend.h"
33 #include "evergreen_compute.h"
34 #include "util/u_math.h"
35
36 static inline unsigned evergreen_array_mode(unsigned mode)
37 {
38 switch (mode) {
39 default:
40 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
41 break;
42 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
43 break;
44 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
45 }
46 }
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(struct r600_texture *rtex,
174 unsigned view_target, unsigned nr_samples)
175 {
176 unsigned res_target = rtex->resource.b.b.target;
177
178 if (view_target == PIPE_TEXTURE_CUBE ||
179 view_target == PIPE_TEXTURE_CUBE_ARRAY)
180 res_target = view_target;
181 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
182 else if (res_target == PIPE_TEXTURE_CUBE ||
183 res_target == PIPE_TEXTURE_CUBE_ARRAY)
184 res_target = PIPE_TEXTURE_2D_ARRAY;
185
186 switch (res_target) {
187 default:
188 case PIPE_TEXTURE_1D:
189 return V_030000_SQ_TEX_DIM_1D;
190 case PIPE_TEXTURE_1D_ARRAY:
191 return V_030000_SQ_TEX_DIM_1D_ARRAY;
192 case PIPE_TEXTURE_2D:
193 case PIPE_TEXTURE_RECT:
194 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
195 V_030000_SQ_TEX_DIM_2D;
196 case PIPE_TEXTURE_2D_ARRAY:
197 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
198 V_030000_SQ_TEX_DIM_2D_ARRAY;
199 case PIPE_TEXTURE_3D:
200 return V_030000_SQ_TEX_DIM_3D;
201 case PIPE_TEXTURE_CUBE:
202 case PIPE_TEXTURE_CUBE_ARRAY:
203 return V_030000_SQ_TEX_DIM_CUBEMAP;
204 }
205 }
206
207 static uint32_t r600_translate_dbformat(enum pipe_format format)
208 {
209 switch (format) {
210 case PIPE_FORMAT_Z16_UNORM:
211 return V_028040_Z_16;
212 case PIPE_FORMAT_Z24X8_UNORM:
213 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
214 case PIPE_FORMAT_X8Z24_UNORM:
215 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
216 return V_028040_Z_24;
217 case PIPE_FORMAT_Z32_FLOAT:
218 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
219 return V_028040_Z_32_FLOAT;
220 default:
221 return ~0U;
222 }
223 }
224
225 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
226 {
227 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
228 FALSE) != ~0U;
229 }
230
231 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
232 {
233 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
234 r600_translate_colorswap(format, FALSE) != ~0U;
235 }
236
237 static bool r600_is_zs_format_supported(enum pipe_format format)
238 {
239 return r600_translate_dbformat(format) != ~0U;
240 }
241
242 boolean evergreen_is_format_supported(struct pipe_screen *screen,
243 enum pipe_format format,
244 enum pipe_texture_target target,
245 unsigned sample_count,
246 unsigned usage)
247 {
248 struct r600_screen *rscreen = (struct r600_screen*)screen;
249 unsigned retval = 0;
250
251 if (target >= PIPE_MAX_TEXTURE_TYPES) {
252 R600_ERR("r600: unsupported texture type %d\n", target);
253 return FALSE;
254 }
255
256 if (!util_format_is_supported(format, usage))
257 return FALSE;
258
259 if (sample_count > 1) {
260 if (!rscreen->has_msaa)
261 return FALSE;
262
263 switch (sample_count) {
264 case 2:
265 case 4:
266 case 8:
267 break;
268 default:
269 return FALSE;
270 }
271 }
272
273 if (usage & PIPE_BIND_SAMPLER_VIEW) {
274 if (target == PIPE_BUFFER) {
275 if (r600_is_vertex_format_supported(format))
276 retval |= PIPE_BIND_SAMPLER_VIEW;
277 } else {
278 if (r600_is_sampler_format_supported(screen, format))
279 retval |= PIPE_BIND_SAMPLER_VIEW;
280 }
281 }
282
283 if ((usage & (PIPE_BIND_RENDER_TARGET |
284 PIPE_BIND_DISPLAY_TARGET |
285 PIPE_BIND_SCANOUT |
286 PIPE_BIND_SHARED |
287 PIPE_BIND_BLENDABLE)) &&
288 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
289 retval |= usage &
290 (PIPE_BIND_RENDER_TARGET |
291 PIPE_BIND_DISPLAY_TARGET |
292 PIPE_BIND_SCANOUT |
293 PIPE_BIND_SHARED);
294 if (!util_format_is_pure_integer(format) &&
295 !util_format_is_depth_or_stencil(format))
296 retval |= usage & PIPE_BIND_BLENDABLE;
297 }
298
299 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
300 r600_is_zs_format_supported(format)) {
301 retval |= PIPE_BIND_DEPTH_STENCIL;
302 }
303
304 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
305 r600_is_vertex_format_supported(format)) {
306 retval |= PIPE_BIND_VERTEX_BUFFER;
307 }
308
309 if ((usage & PIPE_BIND_LINEAR) &&
310 !util_format_is_compressed(format) &&
311 !(usage & PIPE_BIND_DEPTH_STENCIL))
312 retval |= PIPE_BIND_LINEAR;
313
314 return retval == usage;
315 }
316
317 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
318 const struct pipe_blend_state *state, int mode)
319 {
320 uint32_t color_control = 0, target_mask = 0;
321 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
322
323 if (!blend) {
324 return NULL;
325 }
326
327 r600_init_command_buffer(&blend->buffer, 20);
328 r600_init_command_buffer(&blend->buffer_no_blend, 20);
329
330 if (state->logicop_enable) {
331 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
332 } else {
333 color_control |= (0xcc << 16);
334 }
335 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
336 if (state->independent_blend_enable) {
337 for (int i = 0; i < 8; i++) {
338 target_mask |= (state->rt[i].colormask << (4 * i));
339 }
340 } else {
341 for (int i = 0; i < 8; i++) {
342 target_mask |= (state->rt[0].colormask << (4 * i));
343 }
344 }
345
346 /* only have dual source on MRT0 */
347 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
348 blend->cb_target_mask = target_mask;
349 blend->alpha_to_one = state->alpha_to_one;
350
351 if (target_mask)
352 color_control |= S_028808_MODE(mode);
353 else
354 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
355
356
357 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
358 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
359 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
360 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
361 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
362 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
363 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
364 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
365
366 /* Copy over the dwords set so far into buffer_no_blend.
367 * Only the CB_BLENDi_CONTROL registers must be set after this. */
368 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
369 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
370
371 for (int i = 0; i < 8; i++) {
372 /* state->rt entries > 0 only written if independent blending */
373 const int j = state->independent_blend_enable ? i : 0;
374
375 unsigned eqRGB = state->rt[j].rgb_func;
376 unsigned srcRGB = state->rt[j].rgb_src_factor;
377 unsigned dstRGB = state->rt[j].rgb_dst_factor;
378 unsigned eqA = state->rt[j].alpha_func;
379 unsigned srcA = state->rt[j].alpha_src_factor;
380 unsigned dstA = state->rt[j].alpha_dst_factor;
381 uint32_t bc = 0;
382
383 r600_store_value(&blend->buffer_no_blend, 0);
384
385 if (!state->rt[j].blend_enable) {
386 r600_store_value(&blend->buffer, 0);
387 continue;
388 }
389
390 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
391 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
392 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
393 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
394
395 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
396 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
397 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
398 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
399 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
400 }
401 r600_store_value(&blend->buffer, bc);
402 }
403 return blend;
404 }
405
406 static void *evergreen_create_blend_state(struct pipe_context *ctx,
407 const struct pipe_blend_state *state)
408 {
409
410 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
411 }
412
413 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
414 const struct pipe_depth_stencil_alpha_state *state)
415 {
416 unsigned db_depth_control, alpha_test_control, alpha_ref;
417 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
418
419 if (!dsa) {
420 return NULL;
421 }
422
423 r600_init_command_buffer(&dsa->buffer, 3);
424
425 dsa->valuemask[0] = state->stencil[0].valuemask;
426 dsa->valuemask[1] = state->stencil[1].valuemask;
427 dsa->writemask[0] = state->stencil[0].writemask;
428 dsa->writemask[1] = state->stencil[1].writemask;
429 dsa->zwritemask = state->depth.writemask;
430
431 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
432 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
433 S_028800_ZFUNC(state->depth.func);
434
435 /* stencil */
436 if (state->stencil[0].enabled) {
437 db_depth_control |= S_028800_STENCIL_ENABLE(1);
438 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
439 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
440 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
441 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
442
443 if (state->stencil[1].enabled) {
444 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
445 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
446 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
447 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
448 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
449 }
450 }
451
452 /* alpha */
453 alpha_test_control = 0;
454 alpha_ref = 0;
455 if (state->alpha.enabled) {
456 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
457 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
458 alpha_ref = fui(state->alpha.ref_value);
459 }
460 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
461 dsa->alpha_ref = alpha_ref;
462
463 /* misc */
464 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
465 return dsa;
466 }
467
468 static void *evergreen_create_rs_state(struct pipe_context *ctx,
469 const struct pipe_rasterizer_state *state)
470 {
471 struct r600_context *rctx = (struct r600_context *)ctx;
472 unsigned tmp, spi_interp;
473 float psize_min, psize_max;
474 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
475
476 if (!rs) {
477 return NULL;
478 }
479
480 r600_init_command_buffer(&rs->buffer, 30);
481
482 rs->scissor_enable = state->scissor;
483 rs->clip_halfz = state->clip_halfz;
484 rs->flatshade = state->flatshade;
485 rs->sprite_coord_enable = state->sprite_coord_enable;
486 rs->rasterizer_discard = state->rasterizer_discard;
487 rs->two_side = state->light_twoside;
488 rs->clip_plane_enable = state->clip_plane_enable;
489 rs->pa_sc_line_stipple = state->line_stipple_enable ?
490 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
491 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
492 rs->pa_cl_clip_cntl =
493 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
494 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
495 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
496 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
497 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
498 rs->multisample_enable = state->multisample;
499
500 /* offset */
501 rs->offset_units = state->offset_units;
502 rs->offset_scale = state->offset_scale * 16.0f;
503 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
504 rs->offset_units_unscaled = state->offset_units_unscaled;
505
506 if (state->point_size_per_vertex) {
507 psize_min = util_get_min_point_size(state);
508 psize_max = 8192;
509 } else {
510 /* Force the point size to be as if the vertex output was disabled. */
511 psize_min = state->point_size;
512 psize_max = state->point_size;
513 }
514
515 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
516 if (state->sprite_coord_enable) {
517 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
518 S_0286D4_PNT_SPRITE_OVRD_X(2) |
519 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
520 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
521 S_0286D4_PNT_SPRITE_OVRD_W(1);
522 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
523 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
524 }
525 }
526
527 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
528 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
529 tmp = r600_pack_float_12p4(state->point_size/2);
530 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
531 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
532 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
533 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
534 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
535 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
536 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
537
538 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
539 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
540 S_028A48_MSAA_ENABLE(state->multisample) |
541 S_028A48_VPORT_SCISSOR_ENABLE(1) |
542 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
543
544 if (rctx->b.chip_class == CAYMAN) {
545 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
546 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
547 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
548 } else {
549 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
550 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
551 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
552 }
553
554 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
555 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
556 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
557 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
558 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
559 S_028814_FACE(!state->front_ccw) |
560 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
561 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
562 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
563 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
564 state->fill_back != PIPE_POLYGON_MODE_FILL) |
565 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
566 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
567 return rs;
568 }
569
570 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
571 const struct pipe_sampler_state *state)
572 {
573 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
574 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
575 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
576 : state->max_anisotropy;
577 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
578
579 if (!ss) {
580 return NULL;
581 }
582
583 ss->border_color_use = sampler_state_needs_border_color(state);
584
585 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
586 ss->tex_sampler_words[0] =
587 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
588 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
589 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
590 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
591 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
592 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
593 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
594 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
595 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
596 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
597 ss->tex_sampler_words[1] =
598 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
599 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
600 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
601 ss->tex_sampler_words[2] =
602 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
603 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
604 S_03C008_TYPE(1);
605
606 if (ss->border_color_use) {
607 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
608 }
609 return ss;
610 }
611
612 struct eg_buf_res_params {
613 enum pipe_format pipe_format;
614 unsigned offset;
615 unsigned size;
616 unsigned char swizzle[4];
617 bool uncached;
618 bool force_swizzle;
619 };
620
621 static void evergreen_fill_buffer_resource_words(struct r600_context *rctx,
622 struct pipe_resource *buffer,
623 struct eg_buf_res_params *params,
624 bool *skip_mip_address_reloc,
625 unsigned tex_resource_words[8])
626 {
627 struct r600_texture *tmp = (struct r600_texture*)buffer;
628 uint64_t va;
629 int stride = util_format_get_blocksize(params->pipe_format);
630 unsigned format, num_format, format_comp, endian;
631 unsigned swizzle_res;
632 const struct util_format_description *desc;
633
634 r600_vertex_data_type(params->pipe_format,
635 &format, &num_format, &format_comp,
636 &endian);
637
638 desc = util_format_description(params->pipe_format);
639
640 if (params->force_swizzle)
641 swizzle_res = r600_get_swizzle_combined(params->swizzle, NULL, TRUE);
642 else
643 swizzle_res = r600_get_swizzle_combined(desc->swizzle, params->swizzle, TRUE);
644
645 va = tmp->resource.gpu_address + params->offset;
646 *skip_mip_address_reloc = true;
647 tex_resource_words[0] = va;
648 tex_resource_words[1] = params->size - 1;
649 tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
650 S_030008_STRIDE(stride) |
651 S_030008_DATA_FORMAT(format) |
652 S_030008_NUM_FORMAT_ALL(num_format) |
653 S_030008_FORMAT_COMP_ALL(format_comp) |
654 S_030008_ENDIAN_SWAP(endian);
655 tex_resource_words[3] = swizzle_res | S_03000C_UNCACHED(params->uncached);
656 /*
657 * dword 4 is for number of elements, for use with resinfo,
658 * albeit the amd gpu shader analyser
659 * uses a const buffer to store the element sizes for buffer txq
660 */
661 tex_resource_words[4] = params->size / stride;
662
663 tex_resource_words[5] = tex_resource_words[6] = 0;
664 tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
665 }
666
667 static struct pipe_sampler_view *
668 texture_buffer_sampler_view(struct r600_context *rctx,
669 struct r600_pipe_sampler_view *view,
670 unsigned width0, unsigned height0)
671 {
672 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
673 struct eg_buf_res_params params;
674
675 memset(&params, 0, sizeof(params));
676
677 params.pipe_format = view->base.format;
678 params.offset = view->base.u.buf.offset;
679 params.size = view->base.u.buf.size;
680 params.swizzle[0] = view->base.swizzle_r;
681 params.swizzle[1] = view->base.swizzle_g;
682 params.swizzle[2] = view->base.swizzle_b;
683 params.swizzle[3] = view->base.swizzle_a;
684
685 evergreen_fill_buffer_resource_words(rctx, view->base.texture,
686 &params, &view->skip_mip_address_reloc,
687 view->tex_resource_words);
688 view->tex_resource = &tmp->resource;
689
690 if (tmp->resource.gpu_address)
691 LIST_ADDTAIL(&view->list, &rctx->texture_buffers);
692 return &view->base;
693 }
694
695 struct eg_tex_res_params {
696 enum pipe_format pipe_format;
697 int force_level;
698 unsigned width0;
699 unsigned height0;
700 unsigned first_level;
701 unsigned last_level;
702 unsigned first_layer;
703 unsigned last_layer;
704 unsigned target;
705 unsigned char swizzle[4];
706 };
707
708 static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
709 struct pipe_resource *texture,
710 struct eg_tex_res_params *params,
711 bool *skip_mip_address_reloc,
712 unsigned tex_resource_words[8])
713 {
714 struct r600_screen *rscreen = (struct r600_screen*)rctx->b.b.screen;
715 struct r600_texture *tmp = (struct r600_texture*)texture;
716 unsigned format, endian;
717 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
718 unsigned char array_mode = 0, non_disp_tiling = 0;
719 unsigned height, depth, width;
720 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
721 struct legacy_surf_level *surflevel;
722 unsigned base_level, first_level, last_level;
723 unsigned dim, last_layer;
724 uint64_t va;
725 bool do_endian_swap = FALSE;
726
727 tile_split = tmp->surface.u.legacy.tile_split;
728 surflevel = tmp->surface.u.legacy.level;
729
730 /* Texturing with separate depth and stencil. */
731 if (tmp->db_compatible) {
732 switch (params->pipe_format) {
733 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
734 params->pipe_format = PIPE_FORMAT_Z32_FLOAT;
735 break;
736 case PIPE_FORMAT_X8Z24_UNORM:
737 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
738 /* Z24 is always stored like this for DB
739 * compatibility.
740 */
741 params->pipe_format = PIPE_FORMAT_Z24X8_UNORM;
742 break;
743 case PIPE_FORMAT_X24S8_UINT:
744 case PIPE_FORMAT_S8X24_UINT:
745 case PIPE_FORMAT_X32_S8X24_UINT:
746 params->pipe_format = PIPE_FORMAT_S8_UINT;
747 tile_split = tmp->surface.u.legacy.stencil_tile_split;
748 surflevel = tmp->surface.u.legacy.stencil_level;
749 break;
750 default:;
751 }
752 }
753
754 if (R600_BIG_ENDIAN)
755 do_endian_swap = !tmp->db_compatible;
756
757 format = r600_translate_texformat(rctx->b.b.screen, params->pipe_format,
758 params->swizzle,
759 &word4, &yuv_format, do_endian_swap);
760 assert(format != ~0);
761 if (format == ~0) {
762 return -1;
763 }
764
765 endian = r600_colorformat_endian_swap(format, do_endian_swap);
766
767 base_level = 0;
768 first_level = params->first_level;
769 last_level = params->last_level;
770 width = params->width0;
771 height = params->height0;
772 depth = texture->depth0;
773
774 if (params->force_level) {
775 base_level = params->force_level;
776 first_level = 0;
777 last_level = 0;
778 width = u_minify(width, params->force_level);
779 height = u_minify(height, params->force_level);
780 depth = u_minify(depth, params->force_level);
781 }
782
783 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(params->pipe_format);
784 non_disp_tiling = tmp->non_disp_tiling;
785
786 switch (surflevel[base_level].mode) {
787 default:
788 case RADEON_SURF_MODE_LINEAR_ALIGNED:
789 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
790 break;
791 case RADEON_SURF_MODE_2D:
792 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
793 break;
794 case RADEON_SURF_MODE_1D:
795 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
796 break;
797 }
798 macro_aspect = tmp->surface.u.legacy.mtilea;
799 bankw = tmp->surface.u.legacy.bankw;
800 bankh = tmp->surface.u.legacy.bankh;
801 tile_split = eg_tile_split(tile_split);
802 macro_aspect = eg_macro_tile_aspect(macro_aspect);
803 bankw = eg_bank_wh(bankw);
804 bankh = eg_bank_wh(bankh);
805 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
806
807 /* 128 bit formats require tile type = 1 */
808 if (rscreen->b.chip_class == CAYMAN) {
809 if (util_format_get_blocksize(params->pipe_format) >= 16)
810 non_disp_tiling = 1;
811 }
812 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
813
814 if (params->target == PIPE_TEXTURE_1D_ARRAY) {
815 height = 1;
816 depth = texture->array_size;
817 } else if (params->target == PIPE_TEXTURE_2D_ARRAY) {
818 depth = texture->array_size;
819 } else if (params->target == PIPE_TEXTURE_CUBE_ARRAY)
820 depth = texture->array_size / 6;
821
822 va = tmp->resource.gpu_address;
823
824 /* array type views and views into array types need to use layer offset */
825 dim = r600_tex_dim(tmp, params->target, texture->nr_samples);
826 tex_resource_words[0] = (S_030000_DIM(dim) |
827 S_030000_PITCH((pitch / 8) - 1) |
828 S_030000_TEX_WIDTH(width - 1));
829 if (rscreen->b.chip_class == CAYMAN)
830 tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
831 else
832 tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
833 tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
834 S_030004_TEX_DEPTH(depth - 1) |
835 S_030004_ARRAY_MODE(array_mode));
836 tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
837
838 *skip_mip_address_reloc = false;
839 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
840 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
841 if (tmp->is_depth) {
842 /* disable FMASK (0 = disabled) */
843 tex_resource_words[3] = 0;
844 *skip_mip_address_reloc = true;
845 } else {
846 /* FMASK should be in MIP_ADDRESS for multisample textures */
847 tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
848 }
849 } else if (last_level && texture->nr_samples <= 1) {
850 tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
851 } else {
852 tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
853 }
854
855 last_layer = params->last_layer;
856 if (params->target != texture->target && depth == 1) {
857 last_layer = params->first_layer;
858 }
859 tex_resource_words[4] = (word4 |
860 S_030010_ENDIAN_SWAP(endian));
861 tex_resource_words[5] = S_030014_BASE_ARRAY(params->first_layer) |
862 S_030014_LAST_ARRAY(last_layer);
863 tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
864
865 if (texture->nr_samples > 1) {
866 unsigned log_samples = util_logbase2(texture->nr_samples);
867 if (rscreen->b.chip_class == CAYMAN) {
868 tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
869 }
870 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
871 tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
872 tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
873 } else {
874 bool no_mip = first_level == last_level;
875
876 tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
877 tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
878 /* aniso max 16 samples */
879 tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
880 }
881
882 tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
883 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
884 S_03001C_BANK_WIDTH(bankw) |
885 S_03001C_BANK_HEIGHT(bankh) |
886 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
887 S_03001C_NUM_BANKS(nbanks) |
888 S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible);
889 return 0;
890 }
891
892 struct pipe_sampler_view *
893 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
894 struct pipe_resource *texture,
895 const struct pipe_sampler_view *state,
896 unsigned width0, unsigned height0,
897 unsigned force_level)
898 {
899 struct r600_context *rctx = (struct r600_context*)ctx;
900 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
901 struct r600_texture *tmp = (struct r600_texture*)texture;
902 struct eg_tex_res_params params;
903 int ret;
904
905 if (!view)
906 return NULL;
907
908 /* initialize base object */
909 view->base = *state;
910 view->base.texture = NULL;
911 pipe_reference(NULL, &texture->reference);
912 view->base.texture = texture;
913 view->base.reference.count = 1;
914 view->base.context = ctx;
915
916 if (state->target == PIPE_BUFFER)
917 return texture_buffer_sampler_view(rctx, view, width0, height0);
918
919 memset(&params, 0, sizeof(params));
920 params.pipe_format = state->format;
921 params.force_level = force_level;
922 params.width0 = width0;
923 params.height0 = height0;
924 params.first_level = state->u.tex.first_level;
925 params.last_level = state->u.tex.last_level;
926 params.first_layer = state->u.tex.first_layer;
927 params.last_layer = state->u.tex.last_layer;
928 params.target = state->target;
929 params.swizzle[0] = state->swizzle_r;
930 params.swizzle[1] = state->swizzle_g;
931 params.swizzle[2] = state->swizzle_b;
932 params.swizzle[3] = state->swizzle_a;
933
934 ret = evergreen_fill_tex_resource_words(rctx, texture, &params,
935 &view->skip_mip_address_reloc,
936 view->tex_resource_words);
937 if (ret != 0) {
938 FREE(view);
939 return NULL;
940 }
941
942 if (state->format == PIPE_FORMAT_X24S8_UINT ||
943 state->format == PIPE_FORMAT_S8X24_UINT ||
944 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
945 state->format == PIPE_FORMAT_S8_UINT)
946 view->is_stencil_sampler = true;
947
948 view->tex_resource = &tmp->resource;
949
950 return &view->base;
951 }
952
953 static struct pipe_sampler_view *
954 evergreen_create_sampler_view(struct pipe_context *ctx,
955 struct pipe_resource *tex,
956 const struct pipe_sampler_view *state)
957 {
958 return evergreen_create_sampler_view_custom(ctx, tex, state,
959 tex->width0, tex->height0, 0);
960 }
961
962 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
963 {
964 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
965 struct r600_config_state *a = (struct r600_config_state*)atom;
966
967 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
968 if (a->dyn_gpr_enabled) {
969 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
970 radeon_emit(cs, 0);
971 radeon_emit(cs, 0);
972 } else {
973 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
974 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
975 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
976 }
977 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
978 if (a->dyn_gpr_enabled) {
979 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
980 S_028838_PS_GPRS(0x1e) |
981 S_028838_VS_GPRS(0x1e) |
982 S_028838_GS_GPRS(0x1e) |
983 S_028838_ES_GPRS(0x1e) |
984 S_028838_HS_GPRS(0x1e) |
985 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
986 }
987 }
988
989 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
990 {
991 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
992 struct pipe_clip_state *state = &rctx->clip_state.state;
993
994 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
995 radeon_emit_array(cs, (unsigned*)state, 6*4);
996 }
997
998 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
999 const struct pipe_poly_stipple *state)
1000 {
1001 }
1002
1003 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1004 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1005 uint32_t *tl, uint32_t *br)
1006 {
1007 struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
1008
1009 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
1010
1011 *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
1012 *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
1013 }
1014
1015 struct r600_tex_color_info {
1016 unsigned info;
1017 unsigned view;
1018 unsigned dim;
1019 unsigned pitch;
1020 unsigned slice;
1021 unsigned attrib;
1022 unsigned ntype;
1023 unsigned fmask;
1024 unsigned fmask_slice;
1025 uint64_t offset;
1026 boolean export_16bpc;
1027 };
1028
1029 static void evergreen_set_color_surface_buffer(struct r600_context *rctx,
1030 struct r600_resource *res,
1031 enum pipe_format pformat,
1032 unsigned first_element,
1033 unsigned last_element,
1034 struct r600_tex_color_info *color)
1035 {
1036 unsigned format, swap, ntype, endian;
1037 const struct util_format_description *desc;
1038 unsigned block_size = util_format_get_blocksize(res->b.b.format);
1039 unsigned pitch_alignment =
1040 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
1041 unsigned pitch = align(res->b.b.width0, pitch_alignment);
1042 int i;
1043 unsigned width_elements;
1044
1045 width_elements = last_element - first_element + 1;
1046
1047 format = r600_translate_colorformat(rctx->b.chip_class, pformat, FALSE);
1048 swap = r600_translate_colorswap(pformat, FALSE);
1049
1050 endian = r600_colorformat_endian_swap(format, FALSE);
1051
1052 desc = util_format_description(pformat);
1053 for (i = 0; i < 4; i++) {
1054 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1055 break;
1056 }
1057 }
1058 ntype = V_028C70_NUMBER_UNORM;
1059 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1060 ntype = V_028C70_NUMBER_SRGB;
1061 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1062 if (desc->channel[i].normalized)
1063 ntype = V_028C70_NUMBER_SNORM;
1064 else if (desc->channel[i].pure_integer)
1065 ntype = V_028C70_NUMBER_SINT;
1066 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1067 if (desc->channel[i].normalized)
1068 ntype = V_028C70_NUMBER_UNORM;
1069 else if (desc->channel[i].pure_integer)
1070 ntype = V_028C70_NUMBER_UINT;
1071 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1072 ntype = V_028C70_NUMBER_FLOAT;
1073 }
1074
1075 pitch = (pitch / 8) - 1;
1076 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1077
1078 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1079 color->info |= S_028C70_FORMAT(format) |
1080 S_028C70_COMP_SWAP(swap) |
1081 S_028C70_BLEND_CLAMP(0) |
1082 S_028C70_BLEND_BYPASS(1) |
1083 S_028C70_NUMBER_TYPE(ntype) |
1084 S_028C70_ENDIAN(endian);
1085 color->attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1086 color->ntype = ntype;
1087 color->export_16bpc = false;
1088 color->dim = width_elements - 1;
1089 color->slice = 0; /* (width_elements / 64) - 1;*/
1090 color->view = 0;
1091 color->offset = (res->gpu_address + first_element) >> 8;
1092
1093 color->fmask = color->offset;
1094 color->fmask_slice = 0;
1095 }
1096
1097 static void evergreen_set_color_surface_common(struct r600_context *rctx,
1098 struct r600_texture *rtex,
1099 unsigned level,
1100 unsigned first_layer,
1101 unsigned last_layer,
1102 enum pipe_format pformat,
1103 struct r600_tex_color_info *color)
1104 {
1105 struct r600_screen *rscreen = rctx->screen;
1106 unsigned pitch, slice;
1107 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1108 unsigned format, swap, ntype, endian;
1109 const struct util_format_description *desc;
1110 bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
1111 int i;
1112
1113 color->offset = rtex->surface.u.legacy.level[level].offset;
1114 color->view = S_028C6C_SLICE_START(first_layer) |
1115 S_028C6C_SLICE_MAX(last_layer);
1116
1117 color->offset += rtex->resource.gpu_address;
1118 color->offset >>= 8;
1119
1120 color->dim = 0;
1121 pitch = (rtex->surface.u.legacy.level[level].nblk_x) / 8 - 1;
1122 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1123 if (slice) {
1124 slice = slice - 1;
1125 }
1126
1127 color->info = 0;
1128 switch (rtex->surface.u.legacy.level[level].mode) {
1129 default:
1130 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1131 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1132 non_disp_tiling = 1;
1133 break;
1134 case RADEON_SURF_MODE_1D:
1135 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1136 non_disp_tiling = rtex->non_disp_tiling;
1137 break;
1138 case RADEON_SURF_MODE_2D:
1139 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1140 non_disp_tiling = rtex->non_disp_tiling;
1141 break;
1142 }
1143 tile_split = rtex->surface.u.legacy.tile_split;
1144 macro_aspect = rtex->surface.u.legacy.mtilea;
1145 bankw = rtex->surface.u.legacy.bankw;
1146 bankh = rtex->surface.u.legacy.bankh;
1147 if (rtex->fmask.size)
1148 fmask_bankh = rtex->fmask.bank_height;
1149 else
1150 fmask_bankh = rtex->surface.u.legacy.bankh;
1151 tile_split = eg_tile_split(tile_split);
1152 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1153 bankw = eg_bank_wh(bankw);
1154 bankh = eg_bank_wh(bankh);
1155 fmask_bankh = eg_bank_wh(fmask_bankh);
1156
1157 if (rscreen->b.chip_class == CAYMAN) {
1158 if (util_format_get_blocksize(pformat) >= 16)
1159 non_disp_tiling = 1;
1160 }
1161 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1162 desc = util_format_description(pformat);
1163 for (i = 0; i < 4; i++) {
1164 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1165 break;
1166 }
1167 }
1168 color->attrib = S_028C74_TILE_SPLIT(tile_split)|
1169 S_028C74_NUM_BANKS(nbanks) |
1170 S_028C74_BANK_WIDTH(bankw) |
1171 S_028C74_BANK_HEIGHT(bankh) |
1172 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1173 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1174 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1175
1176 if (rctx->b.chip_class == CAYMAN) {
1177 color->attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1178 PIPE_SWIZZLE_1);
1179
1180 if (rtex->resource.b.b.nr_samples > 1) {
1181 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1182 color->attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1183 S_028C74_NUM_FRAGMENTS(log_samples);
1184 }
1185 }
1186
1187 ntype = V_028C70_NUMBER_UNORM;
1188 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1189 ntype = V_028C70_NUMBER_SRGB;
1190 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1191 if (desc->channel[i].normalized)
1192 ntype = V_028C70_NUMBER_SNORM;
1193 else if (desc->channel[i].pure_integer)
1194 ntype = V_028C70_NUMBER_SINT;
1195 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1196 if (desc->channel[i].normalized)
1197 ntype = V_028C70_NUMBER_UNORM;
1198 else if (desc->channel[i].pure_integer)
1199 ntype = V_028C70_NUMBER_UINT;
1200 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1201 ntype = V_028C70_NUMBER_FLOAT;
1202 }
1203
1204 if (R600_BIG_ENDIAN)
1205 do_endian_swap = !rtex->db_compatible;
1206
1207 format = r600_translate_colorformat(rctx->b.chip_class, pformat, do_endian_swap);
1208 assert(format != ~0);
1209 swap = r600_translate_colorswap(pformat, do_endian_swap);
1210 assert(swap != ~0);
1211
1212 endian = r600_colorformat_endian_swap(format, do_endian_swap);
1213
1214 /* blend clamp should be set for all NORM/SRGB types */
1215 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1216 ntype == V_028C70_NUMBER_SRGB)
1217 blend_clamp = 1;
1218
1219 /* set blend bypass according to docs if SINT/UINT or
1220 8/24 COLOR variants */
1221 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1222 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1223 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1224 blend_clamp = 0;
1225 blend_bypass = 1;
1226 }
1227
1228 color->ntype = ntype;
1229 color->info |= S_028C70_FORMAT(format) |
1230 S_028C70_COMP_SWAP(swap) |
1231 S_028C70_BLEND_CLAMP(blend_clamp) |
1232 S_028C70_BLEND_BYPASS(blend_bypass) |
1233 S_028C70_SIMPLE_FLOAT(1) |
1234 S_028C70_NUMBER_TYPE(ntype) |
1235 S_028C70_ENDIAN(endian);
1236
1237 if (rtex->fmask.size) {
1238 color->info |= S_028C70_COMPRESSION(1);
1239 }
1240
1241 /* EXPORT_NORM is an optimzation that can be enabled for better
1242 * performance in certain cases.
1243 * EXPORT_NORM can be enabled if:
1244 * - 11-bit or smaller UNORM/SNORM/SRGB
1245 * - 16-bit or smaller FLOAT
1246 */
1247 color->export_16bpc = false;
1248 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1249 ((desc->channel[i].size < 12 &&
1250 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1251 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1252 (desc->channel[i].size < 17 &&
1253 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1254 color->info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1255 color->export_16bpc = true;
1256 }
1257
1258 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1259 color->slice = S_028C68_SLICE_TILE_MAX(slice);
1260
1261 if (rtex->fmask.size) {
1262 color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8;
1263 color->fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1264 } else {
1265 color->fmask = color->offset;
1266 color->fmask_slice = S_028C88_TILE_MAX(slice);
1267 }
1268 }
1269
1270 /**
1271 * This function intializes the CB* register values for RATs. It is meant
1272 * to be used for 1D aligned buffers that do not have an associated
1273 * radeon_surf.
1274 */
1275 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1276 struct r600_surface *surf)
1277 {
1278 struct pipe_resource *pipe_buffer = surf->base.texture;
1279 struct r600_tex_color_info color;
1280
1281 evergreen_set_color_surface_buffer(rctx, (struct r600_resource *)surf->base.texture,
1282 surf->base.format, 0, pipe_buffer->width0,
1283 &color);
1284
1285 surf->cb_color_base = color.offset;
1286 surf->cb_color_dim = color.dim;
1287 surf->cb_color_info = color.info | S_028C70_RAT(1);
1288 surf->cb_color_pitch = color.pitch;
1289 surf->cb_color_slice = color.slice;
1290 surf->cb_color_view = color.view;
1291 surf->cb_color_attrib = color.attrib;
1292 surf->cb_color_fmask = color.fmask;
1293 surf->cb_color_fmask_slice = color.fmask_slice;
1294
1295 surf->cb_color_view = 0;
1296
1297 /* Set the buffer range the GPU will have access to: */
1298 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
1299 0, pipe_buffer->width0);
1300 }
1301
1302
1303 void evergreen_init_color_surface(struct r600_context *rctx,
1304 struct r600_surface *surf)
1305 {
1306 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1307 unsigned level = surf->base.u.tex.level;
1308 struct r600_tex_color_info color;
1309
1310 evergreen_set_color_surface_common(rctx, rtex, level,
1311 surf->base.u.tex.first_layer,
1312 surf->base.u.tex.last_layer,
1313 surf->base.format,
1314 &color);
1315
1316 surf->alphatest_bypass = color.ntype == V_028C70_NUMBER_UINT ||
1317 color.ntype == V_028C70_NUMBER_SINT;
1318 surf->export_16bpc = color.export_16bpc;
1319
1320 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1321 surf->cb_color_base = color.offset;
1322 surf->cb_color_dim = color.dim;
1323 surf->cb_color_info = color.info;
1324 surf->cb_color_pitch = color.pitch;
1325 surf->cb_color_slice = color.slice;
1326 surf->cb_color_view = color.view;
1327 surf->cb_color_attrib = color.attrib;
1328 surf->cb_color_fmask = color.fmask;
1329 surf->cb_color_fmask_slice = color.fmask_slice;
1330
1331 surf->color_initialized = true;
1332 }
1333
1334 static void evergreen_init_depth_surface(struct r600_context *rctx,
1335 struct r600_surface *surf)
1336 {
1337 struct r600_screen *rscreen = rctx->screen;
1338 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1339 unsigned level = surf->base.u.tex.level;
1340 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
1341 uint64_t offset;
1342 unsigned format, array_mode;
1343 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1344
1345
1346 format = r600_translate_dbformat(surf->base.format);
1347 assert(format != ~0);
1348
1349 offset = rtex->resource.gpu_address;
1350 offset += rtex->surface.u.legacy.level[level].offset;
1351
1352 switch (rtex->surface.u.legacy.level[level].mode) {
1353 case RADEON_SURF_MODE_2D:
1354 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1355 break;
1356 case RADEON_SURF_MODE_1D:
1357 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1358 default:
1359 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1360 break;
1361 }
1362 tile_split = rtex->surface.u.legacy.tile_split;
1363 macro_aspect = rtex->surface.u.legacy.mtilea;
1364 bankw = rtex->surface.u.legacy.bankw;
1365 bankh = rtex->surface.u.legacy.bankh;
1366 tile_split = eg_tile_split(tile_split);
1367 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1368 bankw = eg_bank_wh(bankw);
1369 bankh = eg_bank_wh(bankh);
1370 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1371 offset >>= 8;
1372
1373 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1374 S_028040_FORMAT(format) |
1375 S_028040_TILE_SPLIT(tile_split)|
1376 S_028040_NUM_BANKS(nbanks) |
1377 S_028040_BANK_WIDTH(bankw) |
1378 S_028040_BANK_HEIGHT(bankh) |
1379 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1380 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1381 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1382 }
1383
1384 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1385
1386 surf->db_depth_base = offset;
1387 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1388 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1389 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1390 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1391 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1392 levelinfo->nblk_y / 64 - 1);
1393
1394 if (rtex->surface.has_stencil) {
1395 uint64_t stencil_offset;
1396 unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split;
1397
1398 stile_split = eg_tile_split(stile_split);
1399
1400 stencil_offset = rtex->surface.u.legacy.stencil_level[level].offset;
1401 stencil_offset += rtex->resource.gpu_address;
1402
1403 surf->db_stencil_base = stencil_offset >> 8;
1404 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1405 S_028044_TILE_SPLIT(stile_split);
1406 } else {
1407 surf->db_stencil_base = offset;
1408 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1409 * Older kernels are out of luck. */
1410 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1411 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1412 S_028044_FORMAT(V_028044_STENCIL_8);
1413 }
1414
1415 if (r600_htile_enabled(rtex, level)) {
1416 uint64_t va = rtex->resource.gpu_address + rtex->htile_offset;
1417 surf->db_htile_data_base = va >> 8;
1418 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1419 S_028ABC_HTILE_HEIGHT(1) |
1420 S_028ABC_FULL_CACHE(1);
1421 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1422 surf->db_preload_control = 0;
1423 }
1424
1425 surf->depth_initialized = true;
1426 }
1427
1428 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1429 const struct pipe_framebuffer_state *state)
1430 {
1431 struct r600_context *rctx = (struct r600_context *)ctx;
1432 struct r600_surface *surf;
1433 struct r600_texture *rtex;
1434 uint32_t i, log_samples;
1435
1436 /* Flush TC when changing the framebuffer state, because the only
1437 * client not using TC that can change textures is the framebuffer.
1438 * Other places don't typically have to flush TC.
1439 */
1440 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1441 R600_CONTEXT_FLUSH_AND_INV |
1442 R600_CONTEXT_FLUSH_AND_INV_CB |
1443 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1444 R600_CONTEXT_FLUSH_AND_INV_DB |
1445 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1446 R600_CONTEXT_INV_TEX_CACHE;
1447
1448 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1449
1450 /* Colorbuffers. */
1451 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1452 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1453 util_format_is_pure_integer(state->cbufs[0]->format);
1454 rctx->framebuffer.compressed_cb_mask = 0;
1455 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1456
1457 for (i = 0; i < state->nr_cbufs; i++) {
1458 surf = (struct r600_surface*)state->cbufs[i];
1459 if (!surf)
1460 continue;
1461
1462 rtex = (struct r600_texture*)surf->base.texture;
1463
1464 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1465
1466 if (!surf->color_initialized) {
1467 evergreen_init_color_surface(rctx, surf);
1468 }
1469
1470 if (!surf->export_16bpc) {
1471 rctx->framebuffer.export_16bpc = false;
1472 }
1473
1474 if (rtex->fmask.size) {
1475 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1476 }
1477 }
1478
1479 /* Update alpha-test state dependencies.
1480 * Alpha-test is done on the first colorbuffer only. */
1481 if (state->nr_cbufs) {
1482 bool alphatest_bypass = false;
1483 bool export_16bpc = true;
1484
1485 surf = (struct r600_surface*)state->cbufs[0];
1486 if (surf) {
1487 alphatest_bypass = surf->alphatest_bypass;
1488 export_16bpc = surf->export_16bpc;
1489 }
1490
1491 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1492 rctx->alphatest_state.bypass = alphatest_bypass;
1493 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1494 }
1495 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1496 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1497 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1498 }
1499 }
1500
1501 /* ZS buffer. */
1502 if (state->zsbuf) {
1503 surf = (struct r600_surface*)state->zsbuf;
1504
1505 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1506
1507 if (!surf->depth_initialized) {
1508 evergreen_init_depth_surface(rctx, surf);
1509 }
1510
1511 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1512 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1513 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1514 }
1515
1516 if (rctx->db_state.rsurf != surf) {
1517 rctx->db_state.rsurf = surf;
1518 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1519 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1520 }
1521 } else if (rctx->db_state.rsurf) {
1522 rctx->db_state.rsurf = NULL;
1523 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1524 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1525 }
1526
1527 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1528 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1529 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1530 }
1531
1532 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1533 rctx->alphatest_state.bypass = false;
1534 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1535 }
1536
1537 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1538 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1539 if ((rctx->b.chip_class == CAYMAN ||
1540 rctx->b.family == CHIP_RV770) &&
1541 rctx->db_misc_state.log_samples != log_samples) {
1542 rctx->db_misc_state.log_samples = log_samples;
1543 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1544 }
1545
1546
1547 /* Calculate the CS size. */
1548 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1549
1550 /* MSAA. */
1551 if (rctx->b.chip_class == EVERGREEN)
1552 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1553 else
1554 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1555
1556 /* Colorbuffers. */
1557 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1558 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1559 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1560
1561 /* ZS buffer. */
1562 if (state->zsbuf) {
1563 rctx->framebuffer.atom.num_dw += 24;
1564 rctx->framebuffer.atom.num_dw += 2;
1565 } else if (rctx->screen->b.info.drm_minor >= 18) {
1566 rctx->framebuffer.atom.num_dw += 4;
1567 }
1568
1569 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1570
1571 r600_set_sample_locations_constant_buffer(rctx);
1572 rctx->framebuffer.do_update_surf_dirtiness = true;
1573 }
1574
1575 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1576 {
1577 struct r600_context *rctx = (struct r600_context *)ctx;
1578
1579 if (rctx->ps_iter_samples == min_samples)
1580 return;
1581
1582 rctx->ps_iter_samples = min_samples;
1583 if (rctx->framebuffer.nr_samples > 1) {
1584 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1585 }
1586 }
1587
1588 /* 8xMSAA */
1589 static uint32_t sample_locs_8x[] = {
1590 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1591 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1592 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1593 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1594 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1595 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1596 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1597 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1598 };
1599 static unsigned max_dist_8x = 7;
1600
1601 static void evergreen_get_sample_position(struct pipe_context *ctx,
1602 unsigned sample_count,
1603 unsigned sample_index,
1604 float *out_value)
1605 {
1606 int offset, index;
1607 struct {
1608 int idx:4;
1609 } val;
1610 switch (sample_count) {
1611 case 1:
1612 default:
1613 out_value[0] = out_value[1] = 0.5;
1614 break;
1615 case 2:
1616 offset = 4 * (sample_index * 2);
1617 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1618 out_value[0] = (float)(val.idx + 8) / 16.0f;
1619 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1620 out_value[1] = (float)(val.idx + 8) / 16.0f;
1621 break;
1622 case 4:
1623 offset = 4 * (sample_index * 2);
1624 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1625 out_value[0] = (float)(val.idx + 8) / 16.0f;
1626 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1627 out_value[1] = (float)(val.idx + 8) / 16.0f;
1628 break;
1629 case 8:
1630 offset = 4 * (sample_index % 4 * 2);
1631 index = (sample_index / 4);
1632 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1633 out_value[0] = (float)(val.idx + 8) / 16.0f;
1634 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1635 out_value[1] = (float)(val.idx + 8) / 16.0f;
1636 break;
1637 }
1638 }
1639
1640 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1641 {
1642
1643 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1644 unsigned max_dist = 0;
1645
1646 switch (nr_samples) {
1647 default:
1648 nr_samples = 0;
1649 break;
1650 case 2:
1651 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x));
1652 radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x));
1653 max_dist = eg_max_dist_2x;
1654 break;
1655 case 4:
1656 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x));
1657 radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x));
1658 max_dist = eg_max_dist_4x;
1659 break;
1660 case 8:
1661 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x));
1662 radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x));
1663 max_dist = max_dist_8x;
1664 break;
1665 }
1666
1667 if (nr_samples > 1) {
1668 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1669 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1670 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1671 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1672 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1673 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1674 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1675 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1676 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1677 } else {
1678 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1679 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1680 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1681 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1682 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1683 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1684 }
1685 }
1686
1687 static void evergreen_emit_image_state(struct r600_context *rctx, struct r600_atom *atom,
1688 int immed_id_base, int res_id_base, int offset, uint32_t pkt_flags)
1689 {
1690 struct r600_image_state *state = (struct r600_image_state *)atom;
1691 struct pipe_framebuffer_state *fb_state = &rctx->framebuffer.state;
1692 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1693 struct r600_texture *rtex;
1694 struct r600_resource *resource;
1695 int i;
1696
1697 for (i = 0; i < R600_MAX_IMAGES; i++) {
1698 struct r600_image_view *image = &state->views[i];
1699 unsigned reloc, immed_reloc;
1700 int idx = i + offset;
1701
1702 if (!pkt_flags)
1703 idx += fb_state->nr_cbufs + (rctx->dual_src_blend ? 1 : 0);
1704 if (!image->base.resource)
1705 continue;
1706
1707 resource = (struct r600_resource *)image->base.resource;
1708 if (resource->b.b.target != PIPE_BUFFER)
1709 rtex = (struct r600_texture *)image->base.resource;
1710 else
1711 rtex = NULL;
1712
1713 reloc = radeon_add_to_buffer_list(&rctx->b,
1714 &rctx->b.gfx,
1715 resource,
1716 RADEON_USAGE_READWRITE,
1717 RADEON_PRIO_SHADER_RW_BUFFER);
1718
1719 immed_reloc = radeon_add_to_buffer_list(&rctx->b,
1720 &rctx->b.gfx,
1721 resource->immed_buffer,
1722 RADEON_USAGE_READWRITE,
1723 RADEON_PRIO_SHADER_RW_BUFFER);
1724
1725 if (pkt_flags)
1726 radeon_compute_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13);
1727 else
1728 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13);
1729
1730 radeon_emit(cs, image->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1731 radeon_emit(cs, image->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1732 radeon_emit(cs, image->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1733 radeon_emit(cs, image->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1734 radeon_emit(cs, image->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1735 radeon_emit(cs, image->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1736 radeon_emit(cs, image->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1737 radeon_emit(cs, rtex ? rtex->cmask.base_address_reg : image->cb_color_base); /* R_028C7C_CB_COLOR0_CMASK */
1738 radeon_emit(cs, rtex ? rtex->cmask.slice_tile_max : 0); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1739 radeon_emit(cs, image->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1740 radeon_emit(cs, image->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1741 radeon_emit(cs, rtex ? rtex->color_clear_value[0] : 0); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1742 radeon_emit(cs, rtex ? rtex->color_clear_value[1] : 0); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1743
1744 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1745 radeon_emit(cs, reloc);
1746
1747 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1748 radeon_emit(cs, reloc);
1749
1750 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1751 radeon_emit(cs, reloc);
1752
1753 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1754 radeon_emit(cs, reloc);
1755
1756 if (pkt_flags)
1757 radeon_compute_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1758 else
1759 radeon_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1760
1761 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /**/
1762 radeon_emit(cs, immed_reloc);
1763
1764 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1765 radeon_emit(cs, (immed_id_base + i + offset) * 8);
1766 radeon_emit_array(cs, image->immed_resource_words, 8);
1767
1768 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1769 radeon_emit(cs, immed_reloc);
1770
1771 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1772 radeon_emit(cs, (res_id_base + i + offset) * 8);
1773 radeon_emit_array(cs, image->resource_words, 8);
1774
1775 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1776 radeon_emit(cs, reloc);
1777
1778 if (!image->skip_mip_address_reloc) {
1779 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1780 radeon_emit(cs, reloc);
1781 }
1782 }
1783 }
1784
1785 static void evergreen_emit_fragment_image_state(struct r600_context *rctx, struct r600_atom *atom)
1786 {
1787 evergreen_emit_image_state(rctx, atom,
1788 R600_IMAGE_IMMED_RESOURCE_OFFSET,
1789 R600_IMAGE_REAL_RESOURCE_OFFSET, 0, 0);
1790 }
1791
1792 static void evergreen_emit_compute_image_state(struct r600_context *rctx, struct r600_atom *atom)
1793 {
1794 evergreen_emit_image_state(rctx, atom,
1795 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_IMMED_RESOURCE_OFFSET,
1796 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_REAL_RESOURCE_OFFSET,
1797 0, RADEON_CP_PACKET3_COMPUTE_MODE);
1798 }
1799
1800 static void evergreen_emit_fragment_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1801 {
1802 int offset = util_bitcount(rctx->fragment_images.enabled_mask);
1803 evergreen_emit_image_state(rctx, atom,
1804 R600_IMAGE_IMMED_RESOURCE_OFFSET,
1805 R600_IMAGE_REAL_RESOURCE_OFFSET, offset, 0);
1806 }
1807
1808 static void evergreen_emit_compute_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1809 {
1810 int offset = util_bitcount(rctx->compute_images.enabled_mask);
1811 evergreen_emit_image_state(rctx, atom,
1812 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_IMMED_RESOURCE_OFFSET,
1813 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_REAL_RESOURCE_OFFSET,
1814 offset, RADEON_CP_PACKET3_COMPUTE_MODE);
1815 }
1816
1817 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1818 {
1819 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1820 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1821 unsigned nr_cbufs = state->nr_cbufs;
1822 unsigned i, tl, br;
1823 struct r600_texture *tex = NULL;
1824 struct r600_surface *cb = NULL;
1825
1826 /* XXX support more colorbuffers once we need them */
1827 assert(nr_cbufs <= 8);
1828 if (nr_cbufs > 8)
1829 nr_cbufs = 8;
1830
1831 /* Colorbuffers. */
1832 for (i = 0; i < nr_cbufs; i++) {
1833 unsigned reloc, cmask_reloc;
1834
1835 cb = (struct r600_surface*)state->cbufs[i];
1836 if (!cb) {
1837 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1838 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1839 continue;
1840 }
1841
1842 tex = (struct r600_texture *)cb->base.texture;
1843 reloc = radeon_add_to_buffer_list(&rctx->b,
1844 &rctx->b.gfx,
1845 (struct r600_resource*)cb->base.texture,
1846 RADEON_USAGE_READWRITE,
1847 tex->resource.b.b.nr_samples > 1 ?
1848 RADEON_PRIO_COLOR_BUFFER_MSAA :
1849 RADEON_PRIO_COLOR_BUFFER);
1850
1851 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1852 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1853 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1854 RADEON_PRIO_CMASK);
1855 } else {
1856 cmask_reloc = reloc;
1857 }
1858
1859 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1860 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1861 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1862 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1863 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1864 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1865 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1866 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1867 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1868 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1869 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1870 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1871 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1872 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1873
1874 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1875 radeon_emit(cs, reloc);
1876
1877 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1878 radeon_emit(cs, reloc);
1879
1880 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1881 radeon_emit(cs, cmask_reloc);
1882
1883 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1884 radeon_emit(cs, reloc);
1885 }
1886 /* set CB_COLOR1_INFO for possible dual-src blending */
1887 if (rctx->framebuffer.dual_src_blend && i == 1 && state->cbufs[0]) {
1888 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1889 cb->cb_color_info | tex->cb_color_info);
1890 i++;
1891 }
1892 i += util_bitcount(rctx->fragment_images.enabled_mask);
1893 i += util_bitcount(rctx->fragment_buffers.enabled_mask);
1894 for (; i < 8 ; i++)
1895 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1896 for (; i < 12; i++)
1897 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1898
1899 /* ZS buffer. */
1900 if (state->zsbuf) {
1901 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1902 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1903 &rctx->b.gfx,
1904 (struct r600_resource*)state->zsbuf->texture,
1905 RADEON_USAGE_READWRITE,
1906 zb->base.texture->nr_samples > 1 ?
1907 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1908 RADEON_PRIO_DEPTH_BUFFER);
1909
1910 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1911
1912 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1913 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1914 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1915 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1916 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1917 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1918 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1919 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1920 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1921
1922 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1923 radeon_emit(cs, reloc);
1924
1925 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1926 radeon_emit(cs, reloc);
1927
1928 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1929 radeon_emit(cs, reloc);
1930
1931 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1932 radeon_emit(cs, reloc);
1933 } else if (rctx->screen->b.info.drm_minor >= 18) {
1934 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1935 * Older kernels are out of luck. */
1936 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1937 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1938 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1939 }
1940
1941 /* Framebuffer dimensions. */
1942 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1943
1944 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1945 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1946 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1947
1948 if (rctx->b.chip_class == EVERGREEN) {
1949 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1950 } else {
1951 unsigned sc_mode_cntl_1 =
1952 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1953 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1954
1955 if (rctx->framebuffer.nr_samples > 1)
1956 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1957 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples,
1958 rctx->ps_iter_samples, 0, sc_mode_cntl_1);
1959 }
1960 }
1961
1962 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1963 {
1964 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1965 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1966 float offset_units = state->offset_units;
1967 float offset_scale = state->offset_scale;
1968 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
1969
1970 if (!state->offset_units_unscaled) {
1971 switch (state->zs_format) {
1972 case PIPE_FORMAT_Z24X8_UNORM:
1973 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1974 case PIPE_FORMAT_X8Z24_UNORM:
1975 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1976 offset_units *= 2.0f;
1977 pa_su_poly_offset_db_fmt_cntl =
1978 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1979 break;
1980 case PIPE_FORMAT_Z16_UNORM:
1981 offset_units *= 4.0f;
1982 pa_su_poly_offset_db_fmt_cntl =
1983 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1984 break;
1985 default:
1986 pa_su_poly_offset_db_fmt_cntl =
1987 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1988 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1989 }
1990 }
1991
1992 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1993 radeon_emit(cs, fui(offset_scale));
1994 radeon_emit(cs, fui(offset_units));
1995 radeon_emit(cs, fui(offset_scale));
1996 radeon_emit(cs, fui(offset_units));
1997
1998 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1999 pa_su_poly_offset_db_fmt_cntl);
2000 }
2001
2002 uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a,
2003 unsigned nr_cbufs)
2004 {
2005 unsigned base_mask = 0;
2006 unsigned dirty_mask = a->image_rat_enabled_mask;
2007 while (dirty_mask) {
2008 unsigned idx = u_bit_scan(&dirty_mask);
2009 base_mask |= (0xf << (idx * 4));
2010 }
2011 unsigned offset = util_last_bit(a->image_rat_enabled_mask);
2012 dirty_mask = a->buffer_rat_enabled_mask;
2013 while (dirty_mask) {
2014 unsigned idx = u_bit_scan(&dirty_mask);
2015 base_mask |= (0xf << (idx + offset) * 4);
2016 }
2017 return base_mask << (nr_cbufs * 4);
2018 }
2019
2020 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2021 {
2022 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2023 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
2024 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
2025 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
2026 unsigned rat_colormask = evergreen_construct_rat_mask(rctx, a, a->nr_cbufs);
2027 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
2028 radeon_emit(cs, (a->blend_colormask & fb_colormask) | rat_colormask); /* R_028238_CB_TARGET_MASK */
2029 /* This must match the used export instructions exactly.
2030 * Other values may lead to undefined behavior and hangs.
2031 */
2032 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
2033 }
2034
2035 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
2036 {
2037 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2038 struct r600_db_state *a = (struct r600_db_state*)atom;
2039
2040 if (a->rsurf && a->rsurf->db_htile_surface) {
2041 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
2042 unsigned reloc_idx;
2043
2044 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2045 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
2046 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
2047 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
2048 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
2049 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
2050 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2051 radeon_emit(cs, reloc_idx);
2052 } else {
2053 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
2054 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
2055 }
2056 }
2057
2058 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2059 {
2060 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2061 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2062 unsigned db_render_control = 0;
2063 unsigned db_count_control = 0;
2064 unsigned db_render_override =
2065 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2066 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2067
2068 if (rctx->b.num_occlusion_queries > 0 &&
2069 !a->occlusion_queries_disabled) {
2070 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
2071 if (rctx->b.chip_class == CAYMAN) {
2072 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
2073 }
2074 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
2075 } else {
2076 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
2077 }
2078
2079 /* This is to fix a lockup when hyperz and alpha test are enabled at
2080 * the same time somehow GPU get confuse on which order to pick for
2081 * z test
2082 */
2083 if (rctx->alphatest_state.sx_alpha_test_control)
2084 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
2085
2086 if (a->flush_depthstencil_through_cb) {
2087 assert(a->copy_depth || a->copy_stencil);
2088
2089 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
2090 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
2091 S_028000_COPY_CENTROID(1) |
2092 S_028000_COPY_SAMPLE(a->copy_sample);
2093 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
2094 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
2095 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
2096 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2097 }
2098 if (a->htile_clear) {
2099 /* FIXME we might want to disable cliprect here */
2100 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
2101 }
2102
2103 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
2104 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
2105 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
2106 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2107 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2108 }
2109
2110 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
2111 struct r600_vertexbuf_state *state,
2112 unsigned resource_offset,
2113 unsigned pkt_flags)
2114 {
2115 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2116 uint32_t dirty_mask = state->dirty_mask;
2117
2118 while (dirty_mask) {
2119 struct pipe_vertex_buffer *vb;
2120 struct r600_resource *rbuffer;
2121 uint64_t va;
2122 unsigned buffer_index = u_bit_scan(&dirty_mask);
2123
2124 vb = &state->vb[buffer_index];
2125 rbuffer = (struct r600_resource*)vb->buffer.resource;
2126 assert(rbuffer);
2127
2128 va = rbuffer->gpu_address + vb->buffer_offset;
2129
2130 /* fetch resources start at index 992 */
2131 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2132 radeon_emit(cs, (resource_offset + buffer_index) * 8);
2133 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2134 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2135 radeon_emit(cs, /* RESOURCEi_WORD2 */
2136 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2137 S_030008_STRIDE(vb->stride) |
2138 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2139 radeon_emit(cs, /* RESOURCEi_WORD3 */
2140 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2141 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2142 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2143 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2144 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2145 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2146 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2147 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2148
2149 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2150 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2151 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
2152 }
2153 state->dirty_mask = 0;
2154 }
2155
2156 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2157 {
2158 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
2159 }
2160
2161 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2162 {
2163 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
2164 RADEON_CP_PACKET3_COMPUTE_MODE);
2165 }
2166
2167 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2168 struct r600_constbuf_state *state,
2169 unsigned buffer_id_base,
2170 unsigned reg_alu_constbuf_size,
2171 unsigned reg_alu_const_cache,
2172 unsigned pkt_flags)
2173 {
2174 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2175 uint32_t dirty_mask = state->dirty_mask;
2176
2177 while (dirty_mask) {
2178 struct pipe_constant_buffer *cb;
2179 struct r600_resource *rbuffer;
2180 uint64_t va;
2181 unsigned buffer_index = ffs(dirty_mask) - 1;
2182 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
2183
2184 cb = &state->cb[buffer_index];
2185 rbuffer = (struct r600_resource*)cb->buffer;
2186 assert(rbuffer);
2187
2188 va = rbuffer->gpu_address + cb->buffer_offset;
2189
2190 if (buffer_index < R600_MAX_HW_CONST_BUFFERS) {
2191 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
2192 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
2193 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
2194 pkt_flags);
2195 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2196 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2197 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2198 }
2199
2200 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2201 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
2202 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2203 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2204 radeon_emit(cs, /* RESOURCEi_WORD2 */
2205 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
2206 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
2207 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
2208 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
2209 radeon_emit(cs, /* RESOURCEi_WORD3 */
2210 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
2211 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2212 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2213 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2214 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2215 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2216 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2217 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2218 radeon_emit(cs, /* RESOURCEi_WORD7 */
2219 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
2220
2221 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2222 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2223 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2224
2225 dirty_mask &= ~(1 << buffer_index);
2226 }
2227 state->dirty_mask = 0;
2228 }
2229
2230 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
2231 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2232 {
2233 if (rctx->vs_shader->current->shader.vs_as_ls) {
2234 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2235 EG_FETCH_CONSTANTS_OFFSET_LS,
2236 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2237 R_028F40_ALU_CONST_CACHE_LS_0,
2238 0 /* PKT3 flags */);
2239 } else {
2240 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2241 EG_FETCH_CONSTANTS_OFFSET_VS,
2242 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2243 R_028980_ALU_CONST_CACHE_VS_0,
2244 0 /* PKT3 flags */);
2245 }
2246 }
2247
2248 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2249 {
2250 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
2251 EG_FETCH_CONSTANTS_OFFSET_GS,
2252 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2253 R_0289C0_ALU_CONST_CACHE_GS_0,
2254 0 /* PKT3 flags */);
2255 }
2256
2257 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2258 {
2259 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
2260 EG_FETCH_CONSTANTS_OFFSET_PS,
2261 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2262 R_028940_ALU_CONST_CACHE_PS_0,
2263 0 /* PKT3 flags */);
2264 }
2265
2266 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2267 {
2268 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
2269 EG_FETCH_CONSTANTS_OFFSET_CS,
2270 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2271 R_028F40_ALU_CONST_CACHE_LS_0,
2272 RADEON_CP_PACKET3_COMPUTE_MODE);
2273 }
2274
2275 /* tes constants can be emitted to VS or ES - which are common */
2276 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2277 {
2278 if (!rctx->tes_shader)
2279 return;
2280 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2281 EG_FETCH_CONSTANTS_OFFSET_VS,
2282 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2283 R_028980_ALU_CONST_CACHE_VS_0,
2284 0);
2285 }
2286
2287 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2288 {
2289 if (!rctx->tes_shader)
2290 return;
2291 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2292 EG_FETCH_CONSTANTS_OFFSET_HS,
2293 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
2294 R_028F00_ALU_CONST_CACHE_HS_0,
2295 0);
2296 }
2297
2298 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2299 struct r600_samplerview_state *state,
2300 unsigned resource_id_base, unsigned pkt_flags)
2301 {
2302 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2303 uint32_t dirty_mask = state->dirty_mask;
2304
2305 while (dirty_mask) {
2306 struct r600_pipe_sampler_view *rview;
2307 unsigned resource_index = u_bit_scan(&dirty_mask);
2308 unsigned reloc;
2309
2310 rview = state->views[resource_index];
2311 assert(rview);
2312
2313 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2314 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2315 radeon_emit_array(cs, rview->tex_resource_words, 8);
2316
2317 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2318 RADEON_USAGE_READ,
2319 r600_get_sampler_view_priority(rview->tex_resource));
2320 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2321 radeon_emit(cs, reloc);
2322
2323 if (!rview->skip_mip_address_reloc) {
2324 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2325 radeon_emit(cs, reloc);
2326 }
2327 }
2328 state->dirty_mask = 0;
2329 }
2330
2331 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2332 {
2333 if (rctx->vs_shader->current->shader.vs_as_ls) {
2334 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2335 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2336 } else {
2337 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2338 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2339 }
2340 }
2341
2342 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2343 {
2344 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2345 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2346 }
2347
2348 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2349 {
2350 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2351 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2352 }
2353
2354 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2355 {
2356 if (!rctx->tes_shader)
2357 return;
2358 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2359 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2360 }
2361
2362 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2363 {
2364 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2365 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2366 }
2367
2368 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2369 {
2370 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2371 EG_FETCH_CONSTANTS_OFFSET_CS + R600_MAX_CONST_BUFFERS, RADEON_CP_PACKET3_COMPUTE_MODE);
2372 }
2373
2374 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2375 struct r600_textures_info *texinfo,
2376 unsigned resource_id_base,
2377 unsigned border_index_reg,
2378 unsigned pkt_flags)
2379 {
2380 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2381 uint32_t dirty_mask = texinfo->states.dirty_mask;
2382
2383 while (dirty_mask) {
2384 struct r600_pipe_sampler_state *rstate;
2385 unsigned i = u_bit_scan(&dirty_mask);
2386
2387 rstate = texinfo->states.states[i];
2388 assert(rstate);
2389
2390 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2391 radeon_emit(cs, (resource_id_base + i) * 3);
2392 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2393
2394 if (rstate->border_color_use) {
2395 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2396 radeon_emit(cs, i);
2397 radeon_emit_array(cs, rstate->border_color.ui, 4);
2398 }
2399 }
2400 texinfo->states.dirty_mask = 0;
2401 }
2402
2403 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2404 {
2405 if (rctx->vs_shader->current->shader.vs_as_ls) {
2406 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2407 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2408 } else {
2409 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2410 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2411 }
2412 }
2413
2414 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2415 {
2416 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2417 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2418 }
2419
2420 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2421 {
2422 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2423 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2424 }
2425
2426 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2427 {
2428 if (!rctx->tes_shader)
2429 return;
2430 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2431 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2432 }
2433
2434 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2435 {
2436 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2437 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2438 }
2439
2440 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2441 {
2442 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2443 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2444 RADEON_CP_PACKET3_COMPUTE_MODE);
2445 }
2446
2447 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2448 {
2449 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2450 uint8_t mask = s->sample_mask;
2451
2452 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2453 mask | (mask << 8) | (mask << 16) | (mask << 24));
2454 }
2455
2456 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2457 {
2458 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2459 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2460 uint16_t mask = s->sample_mask;
2461
2462 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2463 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2464 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2465 }
2466
2467 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2468 {
2469 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2470 struct r600_cso_state *state = (struct r600_cso_state*)a;
2471 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2472
2473 if (!shader)
2474 return;
2475
2476 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2477 (shader->buffer->gpu_address + shader->offset) >> 8);
2478 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2479 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2480 RADEON_USAGE_READ,
2481 RADEON_PRIO_SHADER_BINARY));
2482 }
2483
2484 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2485 {
2486 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2487 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2488
2489 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2490
2491 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2492 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2493 primid = 1;
2494 }
2495
2496 if (state->geom_enable) {
2497 uint32_t cut_val;
2498
2499 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2500 cut_val = V_028A40_GS_CUT_128;
2501 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2502 cut_val = V_028A40_GS_CUT_256;
2503 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2504 cut_val = V_028A40_GS_CUT_512;
2505 else
2506 cut_val = V_028A40_GS_CUT_1024;
2507
2508 v = S_028B54_GS_EN(1) |
2509 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2510 if (!rctx->tes_shader)
2511 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2512
2513 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2514 S_028A40_CUT_MODE(cut_val);
2515
2516 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2517 primid = 1;
2518 }
2519
2520 if (rctx->tes_shader) {
2521 uint32_t type, partitioning, topology;
2522 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2523 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2524 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2525 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2526 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2527 switch (tes_prim_mode) {
2528 case PIPE_PRIM_LINES:
2529 type = V_028B6C_TESS_ISOLINE;
2530 break;
2531 case PIPE_PRIM_TRIANGLES:
2532 type = V_028B6C_TESS_TRIANGLE;
2533 break;
2534 case PIPE_PRIM_QUADS:
2535 type = V_028B6C_TESS_QUAD;
2536 break;
2537 default:
2538 assert(0);
2539 return;
2540 }
2541
2542 switch (tes_spacing) {
2543 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2544 partitioning = V_028B6C_PART_FRAC_ODD;
2545 break;
2546 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2547 partitioning = V_028B6C_PART_FRAC_EVEN;
2548 break;
2549 case PIPE_TESS_SPACING_EQUAL:
2550 partitioning = V_028B6C_PART_INTEGER;
2551 break;
2552 default:
2553 assert(0);
2554 return;
2555 }
2556
2557 if (tes_point_mode)
2558 topology = V_028B6C_OUTPUT_POINT;
2559 else if (tes_prim_mode == PIPE_PRIM_LINES)
2560 topology = V_028B6C_OUTPUT_LINE;
2561 else if (tes_vertex_order_cw)
2562 /* XXX follow radeonsi and invert */
2563 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2564 else
2565 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2566
2567 tf_param = S_028B6C_TYPE(type) |
2568 S_028B6C_PARTITIONING(partitioning) |
2569 S_028B6C_TOPOLOGY(topology);
2570 }
2571
2572 if (rctx->tes_shader) {
2573 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2574 S_028B54_HS_EN(1);
2575 if (!state->geom_enable)
2576 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2577 else
2578 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2579 }
2580
2581 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2582 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2583 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2584 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2585 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2586 }
2587
2588 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2589 {
2590 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2591 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2592 struct r600_resource *rbuffer;
2593
2594 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2595 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2596 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2597
2598 if (state->enable) {
2599 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2600 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2601 rbuffer->gpu_address >> 8);
2602 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2603 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2604 RADEON_USAGE_READWRITE,
2605 RADEON_PRIO_SHADER_RINGS));
2606 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2607 state->esgs_ring.buffer_size >> 8);
2608
2609 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2610 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2611 rbuffer->gpu_address >> 8);
2612 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2613 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2614 RADEON_USAGE_READWRITE,
2615 RADEON_PRIO_SHADER_RINGS));
2616 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2617 state->gsvs_ring.buffer_size >> 8);
2618 } else {
2619 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2620 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2621 }
2622
2623 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2624 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2625 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2626 }
2627
2628 void cayman_init_common_regs(struct r600_command_buffer *cb,
2629 enum chip_class ctx_chip_class,
2630 enum radeon_family ctx_family,
2631 int ctx_drm_minor)
2632 {
2633 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2634 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2635 /* always set the temp clauses */
2636 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2637
2638 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2639 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2640 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2641
2642 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2643
2644 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2645 r600_store_value(cb, 0);
2646 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2647
2648 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2649 }
2650
2651 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2652 {
2653 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2654 int i;
2655
2656 r600_init_command_buffer(cb, 338);
2657
2658 /* This must be first. */
2659 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2660 r600_store_value(cb, 0x80000000);
2661 r600_store_value(cb, 0x80000000);
2662
2663 /* We're setting config registers here. */
2664 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2665 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2666
2667 /* This enables pipeline stat & streamout queries.
2668 * They are only disabled by blits.
2669 */
2670 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2671 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2672
2673 cayman_init_common_regs(cb, rctx->b.chip_class,
2674 rctx->b.family, rctx->screen->b.info.drm_minor);
2675
2676 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2677 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2678
2679 /* remove LS/HS from one SIMD for hw workaround */
2680 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2681 r600_store_value(cb, 0xffffffff);
2682 r600_store_value(cb, 0xffffffff);
2683 r600_store_value(cb, 0xfffffffe);
2684
2685 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2686 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2687 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2688 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2689 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2690 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2691 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2692
2693 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2694 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2695 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2696 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2697 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2698
2699 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2700 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2701 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2702 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2703 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2704 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2705 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2706 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2707 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2708 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2709 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2710 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2711 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2712 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2713
2714 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2715
2716 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2717
2718 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2719 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2720 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2721
2722 r600_store_context_reg(cb, R_028724_GDS_ADDR_SIZE, 0x3fff);
2723 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2724 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2725 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2726
2727 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2728
2729 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2730 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2731 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2732
2733 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2734
2735 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2736
2737 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2738
2739 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2740 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2741 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2742 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2743
2744 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2745 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2746
2747 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2748 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2749
2750 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2751 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2752 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2753
2754 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2755 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2756 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2757
2758 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2759 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2760 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2761 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2762 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2763 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2764
2765 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2766
2767 /* to avoid GPU doing any preloading of constant from random address */
2768 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2769 for (i = 0; i < 16; i++)
2770 r600_store_value(cb, 0);
2771
2772 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2773 for (i = 0; i < 16; i++)
2774 r600_store_value(cb, 0);
2775
2776 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2777 for (i = 0; i < 16; i++)
2778 r600_store_value(cb, 0);
2779
2780 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2781 for (i = 0; i < 16; i++)
2782 r600_store_value(cb, 0);
2783
2784 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2785 for (i = 0; i < 16; i++)
2786 r600_store_value(cb, 0);
2787
2788 if (rctx->screen->b.has_streamout) {
2789 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2790 }
2791
2792 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2793 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2794 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2795 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2796 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2797 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2798
2799 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2800 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2801 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2802 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2803 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2804 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2805 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2806 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2807 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2808 }
2809
2810 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2811 enum chip_class ctx_chip_class,
2812 enum radeon_family ctx_family,
2813 int ctx_drm_minor)
2814 {
2815 int ps_prio;
2816 int vs_prio;
2817 int gs_prio;
2818 int es_prio;
2819
2820 int hs_prio;
2821 int cs_prio;
2822 int ls_prio;
2823
2824 unsigned tmp;
2825
2826 ps_prio = 0;
2827 vs_prio = 1;
2828 gs_prio = 2;
2829 es_prio = 3;
2830 hs_prio = 3;
2831 ls_prio = 3;
2832 cs_prio = 0;
2833
2834 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2835 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2836 rctx->r6xx_num_clause_temp_gprs = 4;
2837 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2838 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2839 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2840 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2841
2842 tmp = 0;
2843 switch (ctx_family) {
2844 case CHIP_CEDAR:
2845 case CHIP_PALM:
2846 case CHIP_SUMO:
2847 case CHIP_SUMO2:
2848 case CHIP_CAICOS:
2849 break;
2850 default:
2851 tmp |= S_008C00_VC_ENABLE(1);
2852 break;
2853 }
2854 tmp |= S_008C00_EXPORT_SRC_C(1);
2855 tmp |= S_008C00_CS_PRIO(cs_prio);
2856 tmp |= S_008C00_LS_PRIO(ls_prio);
2857 tmp |= S_008C00_HS_PRIO(hs_prio);
2858 tmp |= S_008C00_PS_PRIO(ps_prio);
2859 tmp |= S_008C00_VS_PRIO(vs_prio);
2860 tmp |= S_008C00_GS_PRIO(gs_prio);
2861 tmp |= S_008C00_ES_PRIO(es_prio);
2862
2863 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2864 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2865
2866 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2867 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2868 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2869
2870 /* The cs checker requires this register to be set. */
2871 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2872
2873 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2874 r600_store_value(cb, 0);
2875 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2876
2877 return;
2878 }
2879
2880 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2881 {
2882 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2883 int num_ps_threads;
2884 int num_vs_threads;
2885 int num_gs_threads;
2886 int num_es_threads;
2887 int num_hs_threads;
2888 int num_ls_threads;
2889
2890 int num_ps_stack_entries;
2891 int num_vs_stack_entries;
2892 int num_gs_stack_entries;
2893 int num_es_stack_entries;
2894 int num_hs_stack_entries;
2895 int num_ls_stack_entries;
2896 enum radeon_family family;
2897 unsigned tmp, i;
2898
2899 if (rctx->b.chip_class == CAYMAN) {
2900 cayman_init_atom_start_cs(rctx);
2901 return;
2902 }
2903
2904 r600_init_command_buffer(cb, 338);
2905
2906 /* This must be first. */
2907 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2908 r600_store_value(cb, 0x80000000);
2909 r600_store_value(cb, 0x80000000);
2910
2911 /* We're setting config registers here. */
2912 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2913 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2914
2915 /* This enables pipeline stat & streamout queries.
2916 * They are only disabled by blits.
2917 */
2918 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2919 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2920
2921 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2922 rctx->b.family, rctx->screen->b.info.drm_minor);
2923
2924 family = rctx->b.family;
2925 switch (family) {
2926 case CHIP_CEDAR:
2927 default:
2928 num_ps_threads = 96;
2929 num_vs_threads = 16;
2930 num_gs_threads = 16;
2931 num_es_threads = 16;
2932 num_hs_threads = 16;
2933 num_ls_threads = 16;
2934 num_ps_stack_entries = 42;
2935 num_vs_stack_entries = 42;
2936 num_gs_stack_entries = 42;
2937 num_es_stack_entries = 42;
2938 num_hs_stack_entries = 42;
2939 num_ls_stack_entries = 42;
2940 break;
2941 case CHIP_REDWOOD:
2942 num_ps_threads = 128;
2943 num_vs_threads = 20;
2944 num_gs_threads = 20;
2945 num_es_threads = 20;
2946 num_hs_threads = 20;
2947 num_ls_threads = 20;
2948 num_ps_stack_entries = 42;
2949 num_vs_stack_entries = 42;
2950 num_gs_stack_entries = 42;
2951 num_es_stack_entries = 42;
2952 num_hs_stack_entries = 42;
2953 num_ls_stack_entries = 42;
2954 break;
2955 case CHIP_JUNIPER:
2956 num_ps_threads = 128;
2957 num_vs_threads = 20;
2958 num_gs_threads = 20;
2959 num_es_threads = 20;
2960 num_hs_threads = 20;
2961 num_ls_threads = 20;
2962 num_ps_stack_entries = 85;
2963 num_vs_stack_entries = 85;
2964 num_gs_stack_entries = 85;
2965 num_es_stack_entries = 85;
2966 num_hs_stack_entries = 85;
2967 num_ls_stack_entries = 85;
2968 break;
2969 case CHIP_CYPRESS:
2970 case CHIP_HEMLOCK:
2971 num_ps_threads = 128;
2972 num_vs_threads = 20;
2973 num_gs_threads = 20;
2974 num_es_threads = 20;
2975 num_hs_threads = 20;
2976 num_ls_threads = 20;
2977 num_ps_stack_entries = 85;
2978 num_vs_stack_entries = 85;
2979 num_gs_stack_entries = 85;
2980 num_es_stack_entries = 85;
2981 num_hs_stack_entries = 85;
2982 num_ls_stack_entries = 85;
2983 break;
2984 case CHIP_PALM:
2985 num_ps_threads = 96;
2986 num_vs_threads = 16;
2987 num_gs_threads = 16;
2988 num_es_threads = 16;
2989 num_hs_threads = 16;
2990 num_ls_threads = 16;
2991 num_ps_stack_entries = 42;
2992 num_vs_stack_entries = 42;
2993 num_gs_stack_entries = 42;
2994 num_es_stack_entries = 42;
2995 num_hs_stack_entries = 42;
2996 num_ls_stack_entries = 42;
2997 break;
2998 case CHIP_SUMO:
2999 num_ps_threads = 96;
3000 num_vs_threads = 25;
3001 num_gs_threads = 25;
3002 num_es_threads = 25;
3003 num_hs_threads = 16;
3004 num_ls_threads = 16;
3005 num_ps_stack_entries = 42;
3006 num_vs_stack_entries = 42;
3007 num_gs_stack_entries = 42;
3008 num_es_stack_entries = 42;
3009 num_hs_stack_entries = 42;
3010 num_ls_stack_entries = 42;
3011 break;
3012 case CHIP_SUMO2:
3013 num_ps_threads = 96;
3014 num_vs_threads = 25;
3015 num_gs_threads = 25;
3016 num_es_threads = 25;
3017 num_hs_threads = 16;
3018 num_ls_threads = 16;
3019 num_ps_stack_entries = 85;
3020 num_vs_stack_entries = 85;
3021 num_gs_stack_entries = 85;
3022 num_es_stack_entries = 85;
3023 num_hs_stack_entries = 85;
3024 num_ls_stack_entries = 85;
3025 break;
3026 case CHIP_BARTS:
3027 num_ps_threads = 128;
3028 num_vs_threads = 20;
3029 num_gs_threads = 20;
3030 num_es_threads = 20;
3031 num_hs_threads = 20;
3032 num_ls_threads = 20;
3033 num_ps_stack_entries = 85;
3034 num_vs_stack_entries = 85;
3035 num_gs_stack_entries = 85;
3036 num_es_stack_entries = 85;
3037 num_hs_stack_entries = 85;
3038 num_ls_stack_entries = 85;
3039 break;
3040 case CHIP_TURKS:
3041 num_ps_threads = 128;
3042 num_vs_threads = 20;
3043 num_gs_threads = 20;
3044 num_es_threads = 20;
3045 num_hs_threads = 20;
3046 num_ls_threads = 20;
3047 num_ps_stack_entries = 42;
3048 num_vs_stack_entries = 42;
3049 num_gs_stack_entries = 42;
3050 num_es_stack_entries = 42;
3051 num_hs_stack_entries = 42;
3052 num_ls_stack_entries = 42;
3053 break;
3054 case CHIP_CAICOS:
3055 num_ps_threads = 96;
3056 num_vs_threads = 10;
3057 num_gs_threads = 10;
3058 num_es_threads = 10;
3059 num_hs_threads = 10;
3060 num_ls_threads = 10;
3061 num_ps_stack_entries = 42;
3062 num_vs_stack_entries = 42;
3063 num_gs_stack_entries = 42;
3064 num_es_stack_entries = 42;
3065 num_hs_stack_entries = 42;
3066 num_ls_stack_entries = 42;
3067 break;
3068 }
3069
3070 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
3071 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
3072 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
3073 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
3074
3075 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
3076 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3077
3078 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
3079 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
3080 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3081
3082 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
3083 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
3084 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3085
3086 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
3087 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
3088 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3089
3090 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
3091 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
3092 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3093
3094 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
3095 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
3096
3097 /* remove LS/HS from one SIMD for hw workaround */
3098 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
3099 r600_store_value(cb, 0xffffffff);
3100 r600_store_value(cb, 0xffffffff);
3101 r600_store_value(cb, 0xfffffffe);
3102
3103 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
3104 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
3105
3106 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
3107 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3108 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3109 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3110 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3111 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3112 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3113
3114 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3115 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3116 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3117 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3118 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3119
3120 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
3121 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3122 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
3123 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3124 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3125 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3126 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3127 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3128 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
3129 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3130 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3131 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3132 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3133 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
3134
3135 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
3136
3137 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
3138
3139 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
3140 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3141 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
3142
3143 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
3144
3145 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
3146
3147 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
3148 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3149 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3150
3151 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
3152 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
3153
3154 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
3155 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3156 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3157 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3158
3159 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
3160 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3161 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3162
3163 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
3164 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3165 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3166
3167 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3168 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3169 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3170 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3171 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
3172 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3173 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3174
3175 /* to avoid GPU doing any preloading of constant from random address */
3176 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
3177 for (i = 0; i < 16; i++)
3178 r600_store_value(cb, 0);
3179
3180 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
3181 for (i = 0; i < 16; i++)
3182 r600_store_value(cb, 0);
3183
3184 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
3185 for (i = 0; i < 16; i++)
3186 r600_store_value(cb, 0);
3187
3188 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
3189 for (i = 0; i < 16; i++)
3190 r600_store_value(cb, 0);
3191
3192 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
3193 for (i = 0; i < 16; i++)
3194 r600_store_value(cb, 0);
3195
3196 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
3197
3198 if (rctx->screen->b.has_streamout) {
3199 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3200 }
3201
3202 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
3203 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3204 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
3205 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
3206 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3207 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3208
3209 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
3210 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
3211 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
3212
3213 if (rctx->b.family == CHIP_CAICOS) {
3214 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
3215 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3216 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3217 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
3218 } else {
3219 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
3220 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3221 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3222 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
3223 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
3224 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
3225 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
3226 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
3227 }
3228
3229 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3230 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3231 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
3232 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
3233 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
3234 }
3235
3236 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3237 {
3238 struct r600_context *rctx = (struct r600_context *)ctx;
3239 struct r600_command_buffer *cb = &shader->command_buffer;
3240 struct r600_shader *rshader = &shader->shader;
3241 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
3242 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
3243 int ninterp = 0;
3244 boolean have_perspective = FALSE, have_linear = FALSE;
3245 static const unsigned spi_baryc_enable_bit[6] = {
3246 S_0286E0_PERSP_SAMPLE_ENA(1),
3247 S_0286E0_PERSP_CENTER_ENA(1),
3248 S_0286E0_PERSP_CENTROID_ENA(1),
3249 S_0286E0_LINEAR_SAMPLE_ENA(1),
3250 S_0286E0_LINEAR_CENTER_ENA(1),
3251 S_0286E0_LINEAR_CENTROID_ENA(1)
3252 };
3253 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
3254 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
3255 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3256 uint32_t spi_ps_input_cntl[32];
3257
3258 if (!cb->buf) {
3259 r600_init_command_buffer(cb, 64);
3260 } else {
3261 cb->num_dw = 0;
3262 }
3263
3264 for (i = 0; i < rshader->ninput; i++) {
3265 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3266 POSITION goes via GPRs from the SC so isn't counted */
3267 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3268 pos_index = i;
3269 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
3270 if (face_index == -1)
3271 face_index = i;
3272 }
3273 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3274 if (face_index == -1)
3275 face_index = i; /* lives in same register, same enable bit */
3276 }
3277 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
3278 fixed_pt_position_index = i;
3279 }
3280 else {
3281 ninterp++;
3282 int k = eg_get_interpolator_index(
3283 rshader->input[i].interpolate,
3284 rshader->input[i].interpolate_location);
3285 if (k >= 0) {
3286 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3287 have_perspective |= k < 3;
3288 have_linear |= !(k < 3);
3289 }
3290 }
3291
3292 sid = rshader->input[i].spi_sid;
3293
3294 if (sid) {
3295 tmp = S_028644_SEMANTIC(sid);
3296
3297 /* D3D 9 behaviour. GL is undefined */
3298 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
3299 tmp |= S_028644_DEFAULT_VAL(3);
3300
3301 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3302 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3303 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3304 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3305 tmp |= S_028644_FLAT_SHADE(1);
3306 }
3307
3308 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3309 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3310 tmp |= S_028644_PT_SPRITE_TEX(1);
3311 }
3312
3313 spi_ps_input_cntl[num++] = tmp;
3314 }
3315 }
3316
3317 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3318 r600_store_array(cb, num, spi_ps_input_cntl);
3319
3320 for (i = 0; i < rshader->noutput; i++) {
3321 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3322 z_export = 1;
3323 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3324 stencil_export = 1;
3325 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3326 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3327 mask_export = 1;
3328 }
3329 if (rshader->uses_kill)
3330 db_shader_control |= S_02880C_KILL_ENABLE(1);
3331
3332 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3333 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3334 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3335
3336 if (shader->selector->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
3337 db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
3338 S_02880C_EXEC_ON_NOOP(shader->selector->info.writes_memory);
3339 } else if (shader->selector->info.writes_memory) {
3340 db_shader_control |= S_02880C_EXEC_ON_HIER_FAIL(1);
3341 }
3342
3343 switch (rshader->ps_conservative_z) {
3344 default: /* fall through */
3345 case TGSI_FS_DEPTH_LAYOUT_ANY:
3346 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3347 break;
3348 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3349 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3350 break;
3351 case TGSI_FS_DEPTH_LAYOUT_LESS:
3352 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3353 break;
3354 }
3355
3356 exports_ps = 0;
3357 for (i = 0; i < rshader->noutput; i++) {
3358 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3359 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3360 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3361 exports_ps |= 1;
3362 }
3363
3364 num_cout = rshader->nr_ps_color_exports;
3365
3366 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3367 if (!exports_ps) {
3368 /* always at least export 1 component per pixel */
3369 exports_ps = 2;
3370 }
3371 shader->nr_ps_color_outputs = num_cout;
3372 if (ninterp == 0) {
3373 ninterp = 1;
3374 have_perspective = TRUE;
3375 }
3376 if (!spi_baryc_cntl)
3377 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3378
3379 if (!have_perspective && !have_linear)
3380 have_perspective = TRUE;
3381
3382 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3383 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3384 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3385 spi_input_z = 0;
3386 if (pos_index != -1) {
3387 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3388 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3389 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3390 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3391 }
3392
3393 spi_ps_in_control_1 = 0;
3394 if (face_index != -1) {
3395 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3396 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3397 }
3398 if (fixed_pt_position_index != -1) {
3399 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3400 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3401 }
3402
3403 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3404 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3405 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3406
3407 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3408 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3409 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3410
3411 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3412 r600_store_value(cb, shader->bo->gpu_address >> 8);
3413 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3414 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3415 S_028844_PRIME_CACHE_ON_DRAW(1) |
3416 S_028844_DX10_CLAMP(1) |
3417 S_028844_STACK_SIZE(rshader->bc.nstack));
3418 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3419
3420 shader->db_shader_control = db_shader_control;
3421 shader->ps_depth_export = z_export | stencil_export | mask_export;
3422
3423 shader->sprite_coord_enable = sprite_coord_enable;
3424 if (rctx->rasterizer)
3425 shader->flatshade = rctx->rasterizer->flatshade;
3426 }
3427
3428 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3429 {
3430 struct r600_command_buffer *cb = &shader->command_buffer;
3431 struct r600_shader *rshader = &shader->shader;
3432
3433 r600_init_command_buffer(cb, 32);
3434
3435 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3436 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3437 S_028890_DX10_CLAMP(1) |
3438 S_028890_STACK_SIZE(rshader->bc.nstack));
3439 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3440 shader->bo->gpu_address >> 8);
3441 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3442 }
3443
3444 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3445 {
3446 struct r600_context *rctx = (struct r600_context *)ctx;
3447 struct r600_command_buffer *cb = &shader->command_buffer;
3448 struct r600_shader *rshader = &shader->shader;
3449 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3450 unsigned gsvs_itemsizes[4] = {
3451 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3452 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3453 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3454 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3455 };
3456
3457 r600_init_command_buffer(cb, 64);
3458
3459 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3460
3461
3462 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3463 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3464 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3465 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3466
3467 if (rctx->screen->b.info.drm_minor >= 35) {
3468 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3469 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3470 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3471 }
3472 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3473 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3474 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3475 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3476 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3477
3478 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3479 (rshader->ring_item_sizes[0]) >> 2);
3480
3481 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3482 gsvs_itemsizes[0] +
3483 gsvs_itemsizes[1] +
3484 gsvs_itemsizes[2] +
3485 gsvs_itemsizes[3]);
3486
3487 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3488 r600_store_value(cb, gsvs_itemsizes[0]);
3489 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3490 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3491
3492 /* FIXME calculate these values somehow ??? */
3493 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3494 r600_store_value(cb, 0x80); /* GS_PER_ES */
3495 r600_store_value(cb, 0x100); /* ES_PER_GS */
3496 r600_store_value(cb, 0x2); /* GS_PER_VS */
3497
3498 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3499 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3500 S_028878_DX10_CLAMP(1) |
3501 S_028878_STACK_SIZE(rshader->bc.nstack));
3502 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3503 shader->bo->gpu_address >> 8);
3504 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3505 }
3506
3507
3508 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3509 {
3510 struct r600_command_buffer *cb = &shader->command_buffer;
3511 struct r600_shader *rshader = &shader->shader;
3512 unsigned spi_vs_out_id[10] = {};
3513 unsigned i, tmp, nparams = 0;
3514
3515 for (i = 0; i < rshader->noutput; i++) {
3516 if (rshader->output[i].spi_sid) {
3517 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3518 spi_vs_out_id[nparams / 4] |= tmp;
3519 nparams++;
3520 }
3521 }
3522
3523 r600_init_command_buffer(cb, 32);
3524
3525 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3526 for (i = 0; i < 10; i++) {
3527 r600_store_value(cb, spi_vs_out_id[i]);
3528 }
3529
3530 /* Certain attributes (position, psize, etc.) don't count as params.
3531 * VS is required to export at least one param and r600_shader_from_tgsi()
3532 * takes care of adding a dummy export.
3533 */
3534 if (nparams < 1)
3535 nparams = 1;
3536
3537 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3538 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3539 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3540 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3541 S_028860_DX10_CLAMP(1) |
3542 S_028860_STACK_SIZE(rshader->bc.nstack));
3543 if (rshader->vs_position_window_space) {
3544 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3545 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3546 } else {
3547 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3548 S_028818_VTX_W0_FMT(1) |
3549 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3550 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3551 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3552
3553 }
3554 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3555 shader->bo->gpu_address >> 8);
3556 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3557
3558 shader->pa_cl_vs_out_cntl =
3559 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->cc_dist_mask & 0x0F) != 0) |
3560 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->cc_dist_mask & 0xF0) != 0) |
3561 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3562 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3563 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3564 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3565 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3566 }
3567
3568 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3569 {
3570 struct r600_command_buffer *cb = &shader->command_buffer;
3571 struct r600_shader *rshader = &shader->shader;
3572
3573 r600_init_command_buffer(cb, 32);
3574 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3575 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3576 S_0288BC_DX10_CLAMP(1) |
3577 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3578 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3579 shader->bo->gpu_address >> 8);
3580 }
3581
3582 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3583 {
3584 struct r600_command_buffer *cb = &shader->command_buffer;
3585 struct r600_shader *rshader = &shader->shader;
3586
3587 r600_init_command_buffer(cb, 32);
3588 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3589 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3590 S_0288D4_DX10_CLAMP(1) |
3591 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3592 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3593 shader->bo->gpu_address >> 8);
3594 }
3595 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3596 {
3597 struct pipe_blend_state blend;
3598
3599 memset(&blend, 0, sizeof(blend));
3600 blend.independent_blend_enable = true;
3601 blend.rt[0].colormask = 0xf;
3602 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3603 }
3604
3605 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3606 {
3607 struct pipe_blend_state blend;
3608 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3609 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3610
3611 memset(&blend, 0, sizeof(blend));
3612 blend.independent_blend_enable = true;
3613 blend.rt[0].colormask = 0xf;
3614 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3615 }
3616
3617 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3618 {
3619 struct pipe_blend_state blend;
3620 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3621
3622 memset(&blend, 0, sizeof(blend));
3623 blend.independent_blend_enable = true;
3624 blend.rt[0].colormask = 0xf;
3625 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3626 }
3627
3628 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3629 {
3630 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3631
3632 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3633 }
3634
3635 void evergreen_update_db_shader_control(struct r600_context * rctx)
3636 {
3637 bool dual_export;
3638 unsigned db_shader_control;
3639
3640 if (!rctx->ps_shader) {
3641 return;
3642 }
3643
3644 dual_export = rctx->framebuffer.export_16bpc &&
3645 !rctx->ps_shader->current->ps_depth_export;
3646
3647 db_shader_control = rctx->ps_shader->current->db_shader_control |
3648 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3649 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3650 V_02880C_EXPORT_DB_FULL) |
3651 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3652
3653 /* When alpha test is enabled we can't trust the hw to make the proper
3654 * decision on the order in which ztest should be run related to fragment
3655 * shader execution.
3656 *
3657 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3658 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3659 * execution and thus after alpha test so if discarded by the alpha test
3660 * the z value is not written.
3661 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3662 * get a hang unless you flush the DB in between. For now just use
3663 * LATE_Z.
3664 */
3665 if (rctx->alphatest_state.sx_alpha_test_control || rctx->ps_shader->info.writes_memory) {
3666 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3667 } else {
3668 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3669 }
3670
3671 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3672 rctx->db_misc_state.db_shader_control = db_shader_control;
3673 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3674 }
3675 }
3676
3677 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3678 struct pipe_resource *dst,
3679 unsigned dst_level,
3680 unsigned dst_x,
3681 unsigned dst_y,
3682 unsigned dst_z,
3683 struct pipe_resource *src,
3684 unsigned src_level,
3685 unsigned src_x,
3686 unsigned src_y,
3687 unsigned src_z,
3688 unsigned copy_height,
3689 unsigned pitch,
3690 unsigned bpp)
3691 {
3692 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3693 struct r600_texture *rsrc = (struct r600_texture*)src;
3694 struct r600_texture *rdst = (struct r600_texture*)dst;
3695 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3696 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3697 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3698 uint64_t base, addr;
3699
3700 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3701 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3702 assert(dst_mode != src_mode);
3703
3704 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3705 if (util_format_has_depth(util_format_description(src->format)))
3706 non_disp_tiling = 1;
3707
3708 y = 0;
3709 sub_cmd = EG_DMA_COPY_TILED;
3710 lbpp = util_logbase2(bpp);
3711 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3712 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3713
3714 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
3715 /* T2L */
3716 array_mode = evergreen_array_mode(src_mode);
3717 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
3718 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3719 /* linear height must be the same as the slice tile max height, it's ok even
3720 * if the linear destination/source have smaller heigh as the size of the
3721 * dma packet will be using the copy_height which is always smaller or equal
3722 * to the linear height
3723 */
3724 height = u_minify(rsrc->resource.b.b.height0, src_level);
3725 detile = 1;
3726 x = src_x;
3727 y = src_y;
3728 z = src_z;
3729 base = rsrc->surface.u.legacy.level[src_level].offset;
3730 addr = rdst->surface.u.legacy.level[dst_level].offset;
3731 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3732 addr += dst_y * pitch + dst_x * bpp;
3733 bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh);
3734 bank_w = eg_bank_wh(rsrc->surface.u.legacy.bankw);
3735 mt_aspect = eg_macro_tile_aspect(rsrc->surface.u.legacy.mtilea);
3736 tile_split = eg_tile_split(rsrc->surface.u.legacy.tile_split);
3737 base += rsrc->resource.gpu_address;
3738 addr += rdst->resource.gpu_address;
3739 } else {
3740 /* L2T */
3741 array_mode = evergreen_array_mode(dst_mode);
3742 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
3743 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3744 /* linear height must be the same as the slice tile max height, it's ok even
3745 * if the linear destination/source have smaller heigh as the size of the
3746 * dma packet will be using the copy_height which is always smaller or equal
3747 * to the linear height
3748 */
3749 height = u_minify(rdst->resource.b.b.height0, dst_level);
3750 detile = 0;
3751 x = dst_x;
3752 y = dst_y;
3753 z = dst_z;
3754 base = rdst->surface.u.legacy.level[dst_level].offset;
3755 addr = rsrc->surface.u.legacy.level[src_level].offset;
3756 addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z;
3757 addr += src_y * pitch + src_x * bpp;
3758 bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh);
3759 bank_w = eg_bank_wh(rdst->surface.u.legacy.bankw);
3760 mt_aspect = eg_macro_tile_aspect(rdst->surface.u.legacy.mtilea);
3761 tile_split = eg_tile_split(rdst->surface.u.legacy.tile_split);
3762 base += rdst->resource.gpu_address;
3763 addr += rsrc->resource.gpu_address;
3764 }
3765
3766 size = (copy_height * pitch) / 4;
3767 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3768 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
3769
3770 for (i = 0; i < ncopy; i++) {
3771 cheight = copy_height;
3772 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3773 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3774 }
3775 size = (cheight * pitch) / 4;
3776 /* emit reloc before writing cs so that cs is always in consistent state */
3777 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3778 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3779 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3780 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3781 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size));
3782 radeon_emit(cs, base >> 8);
3783 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
3784 (lbpp << 24) | (bank_h << 21) |
3785 (bank_w << 18) | (mt_aspect << 16));
3786 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
3787 radeon_emit(cs, (slice_tile_max << 0));
3788 radeon_emit(cs, (x << 0) | (z << 18));
3789 radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28));
3790 radeon_emit(cs, addr & 0xfffffffc);
3791 radeon_emit(cs, (addr >> 32UL) & 0xff);
3792 copy_height -= cheight;
3793 addr += cheight * pitch;
3794 y += cheight;
3795 }
3796 }
3797
3798 static void evergreen_dma_copy(struct pipe_context *ctx,
3799 struct pipe_resource *dst,
3800 unsigned dst_level,
3801 unsigned dstx, unsigned dsty, unsigned dstz,
3802 struct pipe_resource *src,
3803 unsigned src_level,
3804 const struct pipe_box *src_box)
3805 {
3806 struct r600_context *rctx = (struct r600_context *)ctx;
3807 struct r600_texture *rsrc = (struct r600_texture*)src;
3808 struct r600_texture *rdst = (struct r600_texture*)dst;
3809 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3810 unsigned src_w, dst_w;
3811 unsigned src_x, src_y;
3812 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3813
3814 if (rctx->b.dma.cs == NULL) {
3815 goto fallback;
3816 }
3817
3818 if (rctx->cmd_buf_is_compute) {
3819 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
3820 rctx->cmd_buf_is_compute = false;
3821 }
3822
3823 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3824 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3825 return;
3826 }
3827
3828 if (src_box->depth > 1 ||
3829 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3830 dstz, rsrc, src_level, src_box))
3831 goto fallback;
3832
3833 src_x = util_format_get_nblocksx(src->format, src_box->x);
3834 dst_x = util_format_get_nblocksx(src->format, dst_x);
3835 src_y = util_format_get_nblocksy(src->format, src_box->y);
3836 dst_y = util_format_get_nblocksy(src->format, dst_y);
3837
3838 bpp = rdst->surface.bpe;
3839 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
3840 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
3841 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
3842 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
3843 copy_height = src_box->height / rsrc->surface.blk_h;
3844
3845 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3846 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3847
3848 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3849 /* FIXME evergreen can do partial blit */
3850 goto fallback;
3851 }
3852 /* the x test here are currently useless (because we don't support partial blit)
3853 * but keep them around so we don't forget about those
3854 */
3855 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3856 goto fallback;
3857 }
3858
3859 /* 128 bpp surfaces require non_disp_tiling for both
3860 * tiled and linear buffers on cayman. However, async
3861 * DMA only supports it on the tiled side. As such
3862 * the tile order is backwards after a L2T/T2L packet.
3863 */
3864 if ((rctx->b.chip_class == CAYMAN) &&
3865 (src_mode != dst_mode) &&
3866 (util_format_get_blocksize(src->format) >= 16)) {
3867 goto fallback;
3868 }
3869
3870 if (src_mode == dst_mode) {
3871 uint64_t dst_offset, src_offset;
3872 /* simple dma blit would do NOTE code here assume :
3873 * src_box.x/y == 0
3874 * dst_x/y == 0
3875 * dst_pitch == src_pitch
3876 */
3877 src_offset= rsrc->surface.u.legacy.level[src_level].offset;
3878 src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
3879 src_offset += src_y * src_pitch + src_x * bpp;
3880 dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
3881 dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3882 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3883 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3884 src_box->height * src_pitch);
3885 } else {
3886 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3887 src, src_level, src_x, src_y, src_box->z,
3888 copy_height, dst_pitch, bpp);
3889 }
3890 return;
3891
3892 fallback:
3893 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3894 src, src_level, src_box);
3895 }
3896
3897 static void evergreen_set_tess_state(struct pipe_context *ctx,
3898 const float default_outer_level[4],
3899 const float default_inner_level[2])
3900 {
3901 struct r600_context *rctx = (struct r600_context *)ctx;
3902
3903 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3904 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3905 rctx->driver_consts[PIPE_SHADER_TESS_CTRL].tcs_default_levels_dirty = true;
3906 }
3907
3908 static void evergreen_setup_immed_buffer(struct r600_context *rctx,
3909 struct r600_image_view *rview,
3910 enum pipe_format pformat)
3911 {
3912 struct r600_screen *rscreen = (struct r600_screen *)rctx->b.b.screen;
3913 uint32_t immed_size = rscreen->b.info.max_se * 256 * 64 * util_format_get_blocksize(pformat);
3914 struct eg_buf_res_params buf_params;
3915 bool skip_reloc = false;
3916 struct r600_resource *resource = (struct r600_resource *)rview->base.resource;
3917 if (!resource->immed_buffer) {
3918 eg_resource_alloc_immed(&rscreen->b, resource, immed_size);
3919 }
3920
3921 memset(&buf_params, 0, sizeof(buf_params));
3922 buf_params.pipe_format = pformat;
3923 buf_params.size = resource->immed_buffer->b.b.width0;
3924 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
3925 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
3926 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
3927 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
3928 buf_params.uncached = 1;
3929 evergreen_fill_buffer_resource_words(rctx, &resource->immed_buffer->b.b,
3930 &buf_params, &skip_reloc,
3931 rview->immed_resource_words);
3932 }
3933
3934 static void evergreen_set_hw_atomic_buffers(struct pipe_context *ctx,
3935 unsigned start_slot,
3936 unsigned count,
3937 const struct pipe_shader_buffer *buffers)
3938 {
3939 struct r600_context *rctx = (struct r600_context *)ctx;
3940 struct r600_atomic_buffer_state *astate;
3941 int i, idx;
3942
3943 astate = &rctx->atomic_buffer_state;
3944
3945 /* we'd probably like to expand this to 8 later so put the logic in */
3946 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
3947 const struct pipe_shader_buffer *buf;
3948 struct pipe_shader_buffer *abuf;
3949
3950 abuf = &astate->buffer[i];
3951
3952 if (!buffers || !buffers[idx].buffer) {
3953 pipe_resource_reference(&abuf->buffer, NULL);
3954 astate->enabled_mask &= ~(1 << i);
3955 continue;
3956 }
3957 buf = &buffers[idx];
3958
3959 pipe_resource_reference(&abuf->buffer, buf->buffer);
3960 abuf->buffer_offset = buf->buffer_offset;
3961 abuf->buffer_size = buf->buffer_size;
3962 astate->enabled_mask |= (1 << i);
3963 }
3964 }
3965
3966 static void evergreen_set_shader_buffers(struct pipe_context *ctx,
3967 enum pipe_shader_type shader, unsigned start_slot,
3968 unsigned count,
3969 const struct pipe_shader_buffer *buffers)
3970 {
3971 struct r600_context *rctx = (struct r600_context *)ctx;
3972 struct r600_image_state *istate = NULL;
3973 struct r600_image_view *rview;
3974 struct r600_tex_color_info color;
3975 struct eg_buf_res_params buf_params;
3976 struct r600_resource *resource;
3977 int i, idx;
3978 unsigned old_mask;
3979
3980 if (shader != PIPE_SHADER_FRAGMENT &&
3981 shader != PIPE_SHADER_COMPUTE && count == 0)
3982 return;
3983
3984 if (shader == PIPE_SHADER_FRAGMENT)
3985 istate = &rctx->fragment_buffers;
3986 else if (shader == PIPE_SHADER_COMPUTE)
3987 istate = &rctx->compute_buffers;
3988
3989 old_mask = istate->enabled_mask;
3990 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
3991 const struct pipe_shader_buffer *buf;
3992 unsigned res_type;
3993
3994 rview = &istate->views[i];
3995
3996 if (!buffers || !buffers[idx].buffer) {
3997 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
3998 istate->enabled_mask &= ~(1 << i);
3999 continue;
4000 }
4001
4002 buf = &buffers[idx];
4003 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, buf->buffer);
4004
4005 resource = (struct r600_resource *)rview->base.resource;
4006
4007 evergreen_setup_immed_buffer(rctx, rview, PIPE_FORMAT_R32_UINT);
4008
4009 color.offset = 0;
4010 color.view = 0;
4011 evergreen_set_color_surface_buffer(rctx, resource,
4012 PIPE_FORMAT_R32_UINT,
4013 buf->buffer_offset,
4014 buf->buffer_offset + buf->buffer_size,
4015 &color);
4016
4017 res_type = V_028C70_BUFFER;
4018
4019 rview->cb_color_base = color.offset;
4020 rview->cb_color_dim = color.dim;
4021 rview->cb_color_info = color.info |
4022 S_028C70_RAT(1) |
4023 S_028C70_RESOURCE_TYPE(res_type);
4024 rview->cb_color_pitch = color.pitch;
4025 rview->cb_color_slice = color.slice;
4026 rview->cb_color_view = color.view;
4027 rview->cb_color_attrib = color.attrib;
4028 rview->cb_color_fmask = color.fmask;
4029 rview->cb_color_fmask_slice = color.fmask_slice;
4030
4031 memset(&buf_params, 0, sizeof(buf_params));
4032 buf_params.pipe_format = PIPE_FORMAT_R32_UINT;
4033 buf_params.offset = buf->buffer_offset;
4034 buf_params.size = buf->buffer_size;
4035 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
4036 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
4037 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
4038 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
4039 buf_params.force_swizzle = true;
4040 buf_params.uncached = 1;
4041 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4042 &buf_params,
4043 &rview->skip_mip_address_reloc,
4044 rview->resource_words);
4045
4046 istate->enabled_mask |= (1 << i);
4047 }
4048
4049 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
4050
4051 if (old_mask != istate->enabled_mask)
4052 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4053
4054 /* construct the target mask */
4055 if (rctx->cb_misc_state.buffer_rat_enabled_mask != istate->enabled_mask) {
4056 rctx->cb_misc_state.buffer_rat_enabled_mask = istate->enabled_mask;
4057 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4058 }
4059
4060 r600_mark_atom_dirty(rctx, &istate->atom);
4061 }
4062
4063 static void evergreen_set_shader_images(struct pipe_context *ctx,
4064 enum pipe_shader_type shader, unsigned start_slot,
4065 unsigned count,
4066 const struct pipe_image_view *images)
4067 {
4068 struct r600_context *rctx = (struct r600_context *)ctx;
4069 int i;
4070 struct r600_image_view *rview;
4071 struct pipe_resource *image;
4072 struct r600_resource *resource;
4073 struct r600_tex_color_info color;
4074 struct eg_buf_res_params buf_params;
4075 struct eg_tex_res_params tex_params;
4076 unsigned old_mask;
4077 struct r600_image_state *istate = NULL;
4078 int idx;
4079 if (shader != PIPE_SHADER_FRAGMENT && shader != PIPE_SHADER_COMPUTE && count == 0)
4080 return;
4081
4082 if (shader == PIPE_SHADER_FRAGMENT)
4083 istate = &rctx->fragment_images;
4084 else if (shader == PIPE_SHADER_COMPUTE)
4085 istate = &rctx->compute_images;
4086
4087 assert (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE);
4088
4089 old_mask = istate->enabled_mask;
4090 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4091 unsigned res_type;
4092 const struct pipe_image_view *iview;
4093 rview = &istate->views[i];
4094
4095 if (!images || !images[idx].resource) {
4096 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
4097 istate->enabled_mask &= ~(1 << i);
4098 istate->compressed_colortex_mask &= ~(1 << i);
4099 istate->compressed_depthtex_mask &= ~(1 << i);
4100 continue;
4101 }
4102
4103 iview = &images[idx];
4104 image = iview->resource;
4105 resource = (struct r600_resource *)image;
4106
4107 r600_context_add_resource_size(ctx, image);
4108
4109 rview->base = *iview;
4110 rview->base.resource = NULL;
4111 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, image);
4112
4113 evergreen_setup_immed_buffer(rctx, rview, iview->format);
4114
4115 bool is_buffer = image->target == PIPE_BUFFER;
4116 struct r600_texture *rtex = (struct r600_texture *)image;
4117 if (!is_buffer & rtex->db_compatible)
4118 istate->compressed_depthtex_mask |= 1 << i;
4119 else
4120 istate->compressed_depthtex_mask &= ~(1 << i);
4121
4122 if (!is_buffer && rtex->cmask.size)
4123 istate->compressed_colortex_mask |= 1 << i;
4124 else
4125 istate->compressed_colortex_mask &= ~(1 << i);
4126 if (!is_buffer) {
4127
4128 evergreen_set_color_surface_common(rctx, rtex,
4129 iview->u.tex.level,
4130 iview->u.tex.first_layer,
4131 iview->u.tex.last_layer,
4132 iview->format,
4133 &color);
4134 color.dim = S_028C78_WIDTH_MAX(u_minify(image->width0, iview->u.tex.level) - 1) |
4135 S_028C78_HEIGHT_MAX(u_minify(image->height0, iview->u.tex.level) - 1);
4136 } else {
4137 color.offset = 0;
4138 color.view = 0;
4139 evergreen_set_color_surface_buffer(rctx, resource,
4140 iview->format,
4141 iview->u.buf.offset,
4142 iview->u.buf.size,
4143 &color);
4144 }
4145
4146 switch (image->target) {
4147 case PIPE_BUFFER:
4148 res_type = V_028C70_BUFFER;
4149 break;
4150 case PIPE_TEXTURE_1D:
4151 res_type = V_028C70_TEXTURE1D;
4152 break;
4153 case PIPE_TEXTURE_1D_ARRAY:
4154 res_type = V_028C70_TEXTURE1DARRAY;
4155 break;
4156 case PIPE_TEXTURE_2D:
4157 case PIPE_TEXTURE_RECT:
4158 res_type = V_028C70_TEXTURE2D;
4159 break;
4160 case PIPE_TEXTURE_3D:
4161 res_type = V_028C70_TEXTURE3D;
4162 break;
4163 case PIPE_TEXTURE_2D_ARRAY:
4164 case PIPE_TEXTURE_CUBE:
4165 case PIPE_TEXTURE_CUBE_ARRAY:
4166 res_type = V_028C70_TEXTURE2DARRAY;
4167 break;
4168 default:
4169 assert(0);
4170 res_type = 0;
4171 break;
4172 }
4173
4174 rview->cb_color_base = color.offset;
4175 rview->cb_color_dim = color.dim;
4176 rview->cb_color_info = color.info |
4177 S_028C70_RAT(1) |
4178 S_028C70_RESOURCE_TYPE(res_type);
4179 rview->cb_color_pitch = color.pitch;
4180 rview->cb_color_slice = color.slice;
4181 rview->cb_color_view = color.view;
4182 rview->cb_color_attrib = color.attrib;
4183 rview->cb_color_fmask = color.fmask;
4184 rview->cb_color_fmask_slice = color.fmask_slice;
4185
4186 if (image->target != PIPE_BUFFER) {
4187 memset(&tex_params, 0, sizeof(tex_params));
4188 tex_params.pipe_format = iview->format;
4189 tex_params.force_level = 0;
4190 tex_params.width0 = image->width0;
4191 tex_params.height0 = image->height0;
4192 tex_params.first_level = iview->u.tex.level;
4193 tex_params.last_level = iview->u.tex.level;
4194 tex_params.first_layer = iview->u.tex.first_layer;
4195 tex_params.last_layer = iview->u.tex.last_layer;
4196 tex_params.target = image->target;
4197 tex_params.swizzle[0] = PIPE_SWIZZLE_X;
4198 tex_params.swizzle[1] = PIPE_SWIZZLE_Y;
4199 tex_params.swizzle[2] = PIPE_SWIZZLE_Z;
4200 tex_params.swizzle[3] = PIPE_SWIZZLE_W;
4201 evergreen_fill_tex_resource_words(rctx, &resource->b.b, &tex_params,
4202 &rview->skip_mip_address_reloc,
4203 rview->resource_words);
4204
4205 } else {
4206 memset(&buf_params, 0, sizeof(buf_params));
4207 buf_params.pipe_format = iview->format;
4208 buf_params.size = iview->u.buf.size;
4209 buf_params.offset = iview->u.buf.offset;
4210 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
4211 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
4212 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
4213 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
4214 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4215 &buf_params,
4216 &rview->skip_mip_address_reloc,
4217 rview->resource_words);
4218 }
4219 istate->enabled_mask |= (1 << i);
4220 }
4221
4222 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
4223 istate->dirty_buffer_constants = TRUE;
4224 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
4225 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
4226 R600_CONTEXT_FLUSH_AND_INV_CB_META;
4227
4228 if (old_mask != istate->enabled_mask)
4229 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4230
4231 if (rctx->cb_misc_state.image_rat_enabled_mask != istate->enabled_mask) {
4232 rctx->cb_misc_state.image_rat_enabled_mask = istate->enabled_mask;
4233 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4234 }
4235
4236 r600_mark_atom_dirty(rctx, &istate->atom);
4237 }
4238
4239 static void evergreen_get_pipe_constant_buffer(struct r600_context *rctx,
4240 enum pipe_shader_type shader, uint slot,
4241 struct pipe_constant_buffer *cbuf)
4242 {
4243 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
4244 struct pipe_constant_buffer *cb;
4245 cbuf->user_buffer = NULL;
4246
4247 cb = &state->cb[slot];
4248
4249 cbuf->buffer_size = cb->buffer_size;
4250 pipe_resource_reference(&cbuf->buffer, cb->buffer);
4251 }
4252
4253 static void evergreen_get_shader_buffers(struct r600_context *rctx,
4254 enum pipe_shader_type shader,
4255 uint start_slot, uint count,
4256 struct pipe_shader_buffer *sbuf)
4257 {
4258 assert(shader == PIPE_SHADER_COMPUTE);
4259 int idx, i;
4260 struct r600_image_state *istate = &rctx->compute_buffers;
4261 struct r600_image_view *rview;
4262
4263 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4264
4265 rview = &istate->views[i];
4266
4267 pipe_resource_reference(&sbuf[idx].buffer, rview->base.resource);
4268 if (rview->base.resource) {
4269 uint64_t rview_va = ((struct r600_resource *)rview->base.resource)->gpu_address;
4270
4271 uint64_t prog_va = rview->resource_words[0];
4272
4273 prog_va += ((uint64_t)G_030008_BASE_ADDRESS_HI(rview->resource_words[2])) << 32;
4274 prog_va -= rview_va;
4275
4276 sbuf[idx].buffer_offset = prog_va & 0xffffffff;
4277 sbuf[idx].buffer_size = rview->resource_words[1] + 1;;
4278 } else {
4279 sbuf[idx].buffer_offset = 0;
4280 sbuf[idx].buffer_size = 0;
4281 }
4282 }
4283 }
4284
4285 static void evergreen_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
4286 {
4287 struct r600_context *rctx = (struct r600_context *)ctx;
4288 st->saved_compute = rctx->cs_shader_state.shader;
4289
4290 /* save constant buffer 0 */
4291 evergreen_get_pipe_constant_buffer(rctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
4292 /* save ssbo 0 */
4293 evergreen_get_shader_buffers(rctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
4294 }
4295
4296
4297 void evergreen_init_state_functions(struct r600_context *rctx)
4298 {
4299 unsigned id = 1;
4300 unsigned i;
4301 /* !!!
4302 * To avoid GPU lockup registers must be emitted in a specific order
4303 * (no kidding ...). The order below is important and have been
4304 * partially inferred from analyzing fglrx command stream.
4305 *
4306 * Don't reorder atom without carefully checking the effect (GPU lockup
4307 * or piglit regression).
4308 * !!!
4309 */
4310 if (rctx->b.chip_class == EVERGREEN) {
4311 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
4312 rctx->config_state.dyn_gpr_enabled = true;
4313 }
4314 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
4315 r600_init_atom(rctx, &rctx->fragment_images.atom, id++, evergreen_emit_fragment_image_state, 0);
4316 r600_init_atom(rctx, &rctx->compute_images.atom, id++, evergreen_emit_compute_image_state, 0);
4317 r600_init_atom(rctx, &rctx->fragment_buffers.atom, id++, evergreen_emit_fragment_buffer_state, 0);
4318 r600_init_atom(rctx, &rctx->compute_buffers.atom, id++, evergreen_emit_compute_buffer_state, 0);
4319 /* shader const */
4320 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
4321 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
4322 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
4323 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
4324 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
4325 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
4326 /* shader program */
4327 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
4328 /* sampler */
4329 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
4330 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
4331 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
4332 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
4333 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
4334 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
4335 /* resources */
4336 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
4337 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
4338 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
4339 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
4340 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
4341 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
4342 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
4343 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
4344
4345 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
4346
4347 if (rctx->b.chip_class == EVERGREEN) {
4348 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
4349 } else {
4350 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
4351 }
4352 rctx->sample_mask.sample_mask = ~0;
4353
4354 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
4355 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
4356 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
4357 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
4358 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
4359 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
4360 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
4361 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
4362 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
4363 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9);
4364 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
4365 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
4366 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
4367 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
4368 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
4369 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
4370 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
4371 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
4372 for (i = 0; i < EG_NUM_HW_STAGES; i++)
4373 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
4374 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
4375 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
4376
4377 rctx->b.b.create_blend_state = evergreen_create_blend_state;
4378 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
4379 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
4380 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
4381 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
4382 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
4383 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
4384 rctx->b.b.set_min_samples = evergreen_set_min_samples;
4385 rctx->b.b.set_tess_state = evergreen_set_tess_state;
4386 rctx->b.b.set_hw_atomic_buffers = evergreen_set_hw_atomic_buffers;
4387 rctx->b.b.set_shader_images = evergreen_set_shader_images;
4388 rctx->b.b.set_shader_buffers = evergreen_set_shader_buffers;
4389 if (rctx->b.chip_class == EVERGREEN)
4390 rctx->b.b.get_sample_position = evergreen_get_sample_position;
4391 else
4392 rctx->b.b.get_sample_position = cayman_get_sample_position;
4393 rctx->b.dma_copy = evergreen_dma_copy;
4394 rctx->b.save_qbo_state = evergreen_save_qbo_state;
4395
4396 evergreen_init_compute_state_functions(rctx);
4397 }
4398
4399 /**
4400 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
4401 *
4402 * The information about LDS and other non-compile-time parameters is then
4403 * written to the const buffer.
4404
4405 * const buffer contains -
4406 * uint32_t input_patch_size
4407 * uint32_t input_vertex_size
4408 * uint32_t num_tcs_input_cp
4409 * uint32_t num_tcs_output_cp;
4410 * uint32_t output_patch_size
4411 * uint32_t output_vertex_size
4412 * uint32_t output_patch0_offset
4413 * uint32_t perpatch_output_offset
4414 * and the same constbuf is bound to LS/HS/VS(ES).
4415 */
4416 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
4417 {
4418 struct pipe_constant_buffer constbuf = {0};
4419 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
4420 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
4421 unsigned num_tcs_input_cp = info->vertices_per_patch;
4422 unsigned num_tcs_outputs;
4423 unsigned num_tcs_output_cp;
4424 unsigned num_tcs_patch_outputs;
4425 unsigned num_tcs_inputs;
4426 unsigned input_vertex_size, output_vertex_size;
4427 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
4428 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
4429 uint32_t values[8];
4430 unsigned num_waves;
4431 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
4432 unsigned wave_divisor = (16 * num_pipes);
4433
4434 *num_patches = 1;
4435
4436 if (!rctx->tes_shader) {
4437 rctx->lds_alloc = 0;
4438 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4439 R600_LDS_INFO_CONST_BUFFER, NULL);
4440 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4441 R600_LDS_INFO_CONST_BUFFER, NULL);
4442 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4443 R600_LDS_INFO_CONST_BUFFER, NULL);
4444 return;
4445 }
4446
4447 if (rctx->lds_alloc != 0 &&
4448 rctx->last_ls == ls &&
4449 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
4450 rctx->last_tcs == tcs)
4451 return;
4452
4453 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
4454
4455 if (rctx->tcs_shader) {
4456 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
4457 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
4458 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
4459 } else {
4460 num_tcs_outputs = num_tcs_inputs;
4461 num_tcs_output_cp = num_tcs_input_cp;
4462 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
4463 }
4464
4465 /* size in bytes */
4466 input_vertex_size = num_tcs_inputs * 16;
4467 output_vertex_size = num_tcs_outputs * 16;
4468
4469 input_patch_size = num_tcs_input_cp * input_vertex_size;
4470
4471 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
4472 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
4473
4474 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
4475 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
4476
4477 lds_size = output_patch0_offset + output_patch_size * *num_patches;
4478
4479 values[0] = input_patch_size;
4480 values[1] = input_vertex_size;
4481 values[2] = num_tcs_input_cp;
4482 values[3] = num_tcs_output_cp;
4483
4484 values[4] = output_patch_size;
4485 values[5] = output_vertex_size;
4486 values[6] = output_patch0_offset;
4487 values[7] = perpatch_output_offset;
4488
4489 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
4490 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
4491 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
4492
4493 rctx->lds_alloc = (lds_size | (num_waves << 14));
4494
4495 rctx->last_ls = ls;
4496 rctx->last_tcs = tcs;
4497 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
4498
4499 constbuf.user_buffer = values;
4500 constbuf.buffer_size = 8 * 4;
4501
4502 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4503 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4504 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4505 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4506 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4507 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4508 pipe_resource_reference(&constbuf.buffer, NULL);
4509 }
4510
4511 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
4512 const struct pipe_draw_info *info,
4513 unsigned num_patches)
4514 {
4515 unsigned num_output_cp;
4516
4517 if (!rctx->tes_shader)
4518 return 0;
4519
4520 num_output_cp = rctx->tcs_shader ?
4521 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
4522 info->vertices_per_patch;
4523
4524 return S_028B58_NUM_PATCHES(num_patches) |
4525 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
4526 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
4527 }
4528
4529 void evergreen_set_ls_hs_config(struct r600_context *rctx,
4530 struct radeon_winsys_cs *cs,
4531 uint32_t ls_hs_config)
4532 {
4533 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
4534 }
4535
4536 void evergreen_set_lds_alloc(struct r600_context *rctx,
4537 struct radeon_winsys_cs *cs,
4538 uint32_t lds_alloc)
4539 {
4540 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
4541 }
4542
4543 /* on evergreen if you are running tessellation you need to disable dynamic
4544 GPRs to workaround a hardware bug.*/
4545 bool evergreen_adjust_gprs(struct r600_context *rctx)
4546 {
4547 unsigned num_gprs[EG_NUM_HW_STAGES];
4548 unsigned def_gprs[EG_NUM_HW_STAGES];
4549 unsigned cur_gprs[EG_NUM_HW_STAGES];
4550 unsigned new_gprs[EG_NUM_HW_STAGES];
4551 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
4552 unsigned max_gprs;
4553 unsigned i;
4554 unsigned total_gprs;
4555 unsigned tmp[3];
4556 bool rework = false, set_default = false, set_dirty = false;
4557 max_gprs = 0;
4558 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4559 def_gprs[i] = rctx->default_gprs[i];
4560 max_gprs += def_gprs[i];
4561 }
4562 max_gprs += def_num_clause_temp_gprs * 2;
4563
4564 /* if we have no TESS and dyn gpr is enabled then do nothing. */
4565 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
4566 if (rctx->config_state.dyn_gpr_enabled)
4567 return true;
4568
4569 /* transition back to dyn gpr enabled state */
4570 rctx->config_state.dyn_gpr_enabled = true;
4571 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4572 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4573 return true;
4574 }
4575
4576
4577 /* gather required shader gprs */
4578 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4579 if (rctx->hw_shader_stages[i].shader)
4580 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
4581 else
4582 num_gprs[i] = 0;
4583 }
4584
4585 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4586 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4587 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4588 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4589 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4590 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4591
4592 total_gprs = 0;
4593 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4594 new_gprs[i] = num_gprs[i];
4595 total_gprs += num_gprs[i];
4596 }
4597
4598 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
4599 return false;
4600
4601 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4602 if (new_gprs[i] > cur_gprs[i]) {
4603 rework = true;
4604 break;
4605 }
4606 }
4607
4608 if (rctx->config_state.dyn_gpr_enabled) {
4609 set_dirty = true;
4610 rctx->config_state.dyn_gpr_enabled = false;
4611 }
4612
4613 if (rework) {
4614 set_default = true;
4615 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4616 if (new_gprs[i] > def_gprs[i])
4617 set_default = false;
4618 }
4619
4620 if (set_default) {
4621 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4622 new_gprs[i] = def_gprs[i];
4623 }
4624 } else {
4625 unsigned ps_value = max_gprs;
4626
4627 ps_value -= (def_num_clause_temp_gprs * 2);
4628 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
4629 ps_value -= new_gprs[i];
4630
4631 new_gprs[R600_HW_STAGE_PS] = ps_value;
4632 }
4633
4634 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
4635 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
4636 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
4637
4638 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
4639 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
4640
4641 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
4642 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
4643
4644 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
4645 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
4646 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
4647 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
4648 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
4649 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
4650 set_dirty = true;
4651 }
4652 }
4653
4654
4655 if (set_dirty) {
4656 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4657 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4658 }
4659 return true;
4660 }
4661
4662 #define AC_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
4663
4664 void eg_trace_emit(struct r600_context *rctx)
4665 {
4666 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4667 unsigned reloc;
4668
4669 if (rctx->b.chip_class < EVERGREEN)
4670 return;
4671
4672 /* This must be done after r600_need_cs_space. */
4673 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4674 (struct r600_resource*)rctx->trace_buf, RADEON_USAGE_WRITE,
4675 RADEON_PRIO_CP_DMA);
4676
4677 rctx->trace_id++;
4678 radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rctx->trace_buf,
4679 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
4680 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
4681 radeon_emit(cs, rctx->trace_buf->gpu_address);
4682 radeon_emit(cs, rctx->trace_buf->gpu_address >> 32 | MEM_WRITE_32_BITS | MEM_WRITE_CONFIRM);
4683 radeon_emit(cs, rctx->trace_id);
4684 radeon_emit(cs, 0);
4685 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4686 radeon_emit(cs, reloc);
4687 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4688 radeon_emit(cs, AC_ENCODE_TRACE_POINT(rctx->trace_id));
4689 }
4690
4691 static void evergreen_emit_set_append_cnt(struct r600_context *rctx,
4692 struct r600_shader_atomic *atomic,
4693 struct r600_resource *resource,
4694 uint32_t pkt_flags)
4695 {
4696 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4697 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4698 resource,
4699 RADEON_USAGE_READ,
4700 RADEON_PRIO_SHADER_RW_BUFFER);
4701 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4702 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4703
4704 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4 - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
4705
4706 radeon_emit(cs, PKT3(PKT3_SET_APPEND_CNT, 2, 0) | pkt_flags);
4707 radeon_emit(cs, (reg_val << 16) | 0x3);
4708 radeon_emit(cs, dst_offset & 0xfffffffc);
4709 radeon_emit(cs, (dst_offset >> 32) & 0xff);
4710 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4711 radeon_emit(cs, reloc);
4712 }
4713
4714 static void evergreen_emit_event_write_eos(struct r600_context *rctx,
4715 struct r600_shader_atomic *atomic,
4716 struct r600_resource *resource,
4717 uint32_t pkt_flags)
4718 {
4719 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4720 uint32_t event = EVENT_TYPE_PS_DONE;
4721 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4722 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4723 resource,
4724 RADEON_USAGE_WRITE,
4725 RADEON_PRIO_SHADER_RW_BUFFER);
4726 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4727 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4) >> 2;
4728
4729 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4730 event = EVENT_TYPE_CS_DONE;
4731
4732 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4733 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4734 radeon_emit(cs, (dst_offset) & 0xffffffff);
4735 radeon_emit(cs, (0 << 29) | ((dst_offset >> 32) & 0xff));
4736 radeon_emit(cs, reg_val);
4737 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4738 radeon_emit(cs, reloc);
4739 }
4740
4741 static void cayman_emit_event_write_eos(struct r600_context *rctx,
4742 struct r600_shader_atomic *atomic,
4743 struct r600_resource *resource,
4744 uint32_t pkt_flags)
4745 {
4746 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4747 uint32_t event = EVENT_TYPE_PS_DONE;
4748 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4749 resource,
4750 RADEON_USAGE_WRITE,
4751 RADEON_PRIO_SHADER_RW_BUFFER);
4752 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4753
4754 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4755 event = EVENT_TYPE_CS_DONE;
4756
4757 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4758 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4759 radeon_emit(cs, (dst_offset) & 0xffffffff);
4760 radeon_emit(cs, (1 << 29) | ((dst_offset >> 32) & 0xff));
4761 radeon_emit(cs, (atomic->hw_idx) | (1 << 16));
4762 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4763 radeon_emit(cs, reloc);
4764 }
4765
4766 /* writes count from a buffer into GDS */
4767 static void cayman_write_count_to_gds(struct r600_context *rctx,
4768 struct r600_shader_atomic *atomic,
4769 struct r600_resource *resource,
4770 uint32_t pkt_flags)
4771 {
4772 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4773 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4774 resource,
4775 RADEON_USAGE_READ,
4776 RADEON_PRIO_SHADER_RW_BUFFER);
4777 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4778
4779 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0) | pkt_flags);
4780 radeon_emit(cs, dst_offset & 0xffffffff);
4781 radeon_emit(cs, PKT3_CP_DMA_CP_SYNC | PKT3_CP_DMA_DST_SEL(1) | ((dst_offset >> 32) & 0xff));// GDS
4782 radeon_emit(cs, atomic->hw_idx * 4);
4783 radeon_emit(cs, 0);
4784 radeon_emit(cs, PKT3_CP_DMA_CMD_DAS | 4);
4785 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4786 radeon_emit(cs, reloc);
4787 }
4788
4789 bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
4790 struct r600_pipe_shader *cs_shader,
4791 struct r600_shader_atomic *combined_atomics,
4792 uint8_t *atomic_used_mask_p)
4793 {
4794 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4795 unsigned pkt_flags = 0;
4796 uint8_t atomic_used_mask = 0;
4797 int i, j, k;
4798 bool is_compute = cs_shader ? true : false;
4799
4800 if (is_compute)
4801 pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
4802
4803 for (i = 0; i < (is_compute ? 1 : EG_NUM_HW_STAGES); i++) {
4804 uint8_t num_atomic_stage;
4805 struct r600_pipe_shader *pshader;
4806
4807 if (is_compute)
4808 pshader = cs_shader;
4809 else
4810 pshader = rctx->hw_shader_stages[i].shader;
4811 if (!pshader)
4812 continue;
4813
4814 num_atomic_stage = pshader->shader.nhwatomic_ranges;
4815 if (!num_atomic_stage)
4816 continue;
4817
4818 for (j = 0; j < num_atomic_stage; j++) {
4819 struct r600_shader_atomic *atomic = &pshader->shader.atomics[j];
4820 int natomics = atomic->end - atomic->start + 1;
4821
4822 for (k = 0; k < natomics; k++) {
4823 /* seen this in a previous stage */
4824 if (atomic_used_mask & (1u << (atomic->hw_idx + k)))
4825 continue;
4826
4827 combined_atomics[atomic->hw_idx + k].hw_idx = atomic->hw_idx + k;
4828 combined_atomics[atomic->hw_idx + k].buffer_id = atomic->buffer_id;
4829 combined_atomics[atomic->hw_idx + k].start = atomic->start + k;
4830 combined_atomics[atomic->hw_idx + k].end = combined_atomics[atomic->hw_idx + k].start + 1;
4831 atomic_used_mask |= (1u << (atomic->hw_idx + k));
4832 }
4833 }
4834 }
4835
4836 uint32_t mask = atomic_used_mask;
4837 while (mask) {
4838 unsigned atomic_index = u_bit_scan(&mask);
4839 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
4840 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
4841 assert(resource);
4842
4843 if (rctx->b.chip_class == CAYMAN)
4844 cayman_write_count_to_gds(rctx, atomic, resource, pkt_flags);
4845 else
4846 evergreen_emit_set_append_cnt(rctx, atomic, resource, pkt_flags);
4847 }
4848 *atomic_used_mask_p = atomic_used_mask;
4849 return true;
4850 }
4851
4852 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
4853 bool is_compute,
4854 struct r600_shader_atomic *combined_atomics,
4855 uint8_t *atomic_used_mask_p)
4856 {
4857 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4858 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4859 uint32_t pkt_flags = 0;
4860 uint32_t event = EVENT_TYPE_PS_DONE;
4861 uint32_t mask = astate->enabled_mask;
4862 uint64_t dst_offset;
4863 unsigned reloc;
4864
4865 if (is_compute)
4866 pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
4867
4868 mask = *atomic_used_mask_p;
4869 if (!mask)
4870 return;
4871
4872 while (mask) {
4873 unsigned atomic_index = u_bit_scan(&mask);
4874 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
4875 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
4876 assert(resource);
4877
4878 if (rctx->b.chip_class == CAYMAN)
4879 cayman_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
4880 else
4881 evergreen_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
4882 }
4883
4884 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4885 event = EVENT_TYPE_CS_DONE;
4886
4887 ++rctx->append_fence_id;
4888 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4889 r600_resource(rctx->append_fence),
4890 RADEON_USAGE_READWRITE,
4891 RADEON_PRIO_SHADER_RW_BUFFER);
4892 dst_offset = r600_resource(rctx->append_fence)->gpu_address;
4893 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4894 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4895 radeon_emit(cs, dst_offset & 0xffffffff);
4896 radeon_emit(cs, (2 << 29) | ((dst_offset >> 32) & 0xff));
4897 radeon_emit(cs, rctx->append_fence_id);
4898 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4899 radeon_emit(cs, reloc);
4900
4901 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0) | pkt_flags);
4902 radeon_emit(cs, WAIT_REG_MEM_GEQUAL | WAIT_REG_MEM_MEMORY | (1 << 8));
4903 radeon_emit(cs, dst_offset & 0xffffffff);
4904 radeon_emit(cs, ((dst_offset >> 32) & 0xff));
4905 radeon_emit(cs, rctx->append_fence_id);
4906 radeon_emit(cs, 0xffffffff);
4907 radeon_emit(cs, 0xa);
4908 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4909 radeon_emit(cs, reloc);
4910 }