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Merge remote-tracking branch 'origin/master' into pipe-video
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "eg_state_inlines.h"
50
51 static void evergreen_set_blend_color(struct pipe_context *ctx,
52 const struct pipe_blend_color *state)
53 {
54 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
55 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
56
57 if (rstate == NULL)
58 return;
59
60 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
61 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
62 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
63 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
65
66 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
67 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
68 r600_context_pipe_state_set(&rctx->ctx, rstate);
69 }
70
71 static void *evergreen_create_blend_state(struct pipe_context *ctx,
72 const struct pipe_blend_state *state)
73 {
74 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
75 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
76 struct r600_pipe_state *rstate;
77 u32 color_control, target_mask;
78 /* FIXME there is more then 8 framebuffer */
79 unsigned blend_cntl[8];
80 enum radeon_family family;
81
82 if (blend == NULL) {
83 return NULL;
84 }
85
86 family = r600_get_family(rctx->radeon);
87 rstate = &blend->rstate;
88
89 rstate->id = R600_PIPE_STATE_BLEND;
90
91 target_mask = 0;
92 color_control = S_028808_MODE(1);
93 if (state->logicop_enable) {
94 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
95 } else {
96 color_control |= (0xcc << 16);
97 }
98 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
99 if (state->independent_blend_enable) {
100 for (int i = 0; i < 8; i++) {
101 target_mask |= (state->rt[i].colormask << (4 * i));
102 }
103 } else {
104 for (int i = 0; i < 8; i++) {
105 target_mask |= (state->rt[0].colormask << (4 * i));
106 }
107 }
108 blend->cb_target_mask = target_mask;
109
110 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
111 color_control, 0xFFFFFFFD, NULL);
112
113 if (family != CHIP_CAYMAN)
114 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
115 else {
116 r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
117 r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
118 }
119
120 for (int i = 0; i < 8; i++) {
121 /* state->rt entries > 0 only written if independent blending */
122 const int j = state->independent_blend_enable ? i : 0;
123
124 unsigned eqRGB = state->rt[j].rgb_func;
125 unsigned srcRGB = state->rt[j].rgb_src_factor;
126 unsigned dstRGB = state->rt[j].rgb_dst_factor;
127 unsigned eqA = state->rt[j].alpha_func;
128 unsigned srcA = state->rt[j].alpha_src_factor;
129 unsigned dstA = state->rt[j].alpha_dst_factor;
130
131 blend_cntl[i] = 0;
132 if (!state->rt[j].blend_enable)
133 continue;
134
135 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
136 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
137 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
138 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
139
140 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
141 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
142 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
143 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
144 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
145 }
146 }
147 for (int i = 0; i < 8; i++) {
148 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
149 }
150
151 return rstate;
152 }
153
154 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
155 const struct pipe_depth_stencil_alpha_state *state)
156 {
157 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
158 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
159 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
160 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
161 struct r600_pipe_state *rstate;
162
163 if (dsa == NULL) {
164 return NULL;
165 }
166
167 rstate = &dsa->rstate;
168
169 rstate->id = R600_PIPE_STATE_DSA;
170 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
171 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
172 stencil_ref_mask = 0;
173 stencil_ref_mask_bf = 0;
174 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
175 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
176 S_028800_ZFUNC(state->depth.func);
177
178 /* stencil */
179 if (state->stencil[0].enabled) {
180 db_depth_control |= S_028800_STENCIL_ENABLE(1);
181 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
182 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
183 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
184 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
185
186
187 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
188 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
189 if (state->stencil[1].enabled) {
190 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
191 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
192 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
193 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
194 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
195 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
196 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
197 }
198 }
199
200 /* alpha */
201 alpha_test_control = 0;
202 alpha_ref = 0;
203 if (state->alpha.enabled) {
204 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
205 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
206 alpha_ref = fui(state->alpha.ref_value);
207 }
208 dsa->alpha_ref = alpha_ref;
209
210 /* misc */
211 db_render_control = 0;
212 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
213 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
214 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
215 /* TODO db_render_override depends on query */
216 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
217 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
218 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
219 r600_pipe_state_add_reg(rstate,
220 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
221 0xFFFFFFFF & C_028430_STENCILREF, NULL);
222 r600_pipe_state_add_reg(rstate,
223 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
224 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
225 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
226 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
227 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
228 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
229 * evergreen_pipe_shader_ps().*/
230 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL);
231 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
232 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
233 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
234 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
235 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
236 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
237
238 return rstate;
239 }
240
241 static void *evergreen_create_rs_state(struct pipe_context *ctx,
242 const struct pipe_rasterizer_state *state)
243 {
244 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
245 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
246 struct r600_pipe_state *rstate;
247 unsigned tmp;
248 unsigned prov_vtx = 1, polygon_dual_mode;
249 unsigned clip_rule;
250 enum radeon_family family;
251
252 family = r600_get_family(rctx->radeon);
253
254 if (rs == NULL) {
255 return NULL;
256 }
257
258 rstate = &rs->rstate;
259 rs->flatshade = state->flatshade;
260 rs->sprite_coord_enable = state->sprite_coord_enable;
261
262 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
263
264 /* offset */
265 rs->offset_units = state->offset_units;
266 rs->offset_scale = state->offset_scale * 12.0f;
267
268 rstate->id = R600_PIPE_STATE_RASTERIZER;
269 if (state->flatshade_first)
270 prov_vtx = 0;
271 tmp = S_0286D4_FLAT_SHADE_ENA(1);
272 if (state->sprite_coord_enable) {
273 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
274 S_0286D4_PNT_SPRITE_OVRD_X(2) |
275 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
276 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
277 S_0286D4_PNT_SPRITE_OVRD_W(1);
278 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
279 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
280 }
281 }
282 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
283
284 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
285 state->fill_back != PIPE_POLYGON_MODE_FILL);
286 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
287 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
288 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
289 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
290 S_028814_FACE(!state->front_ccw) |
291 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
292 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
293 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
294 S_028814_POLY_MODE(polygon_dual_mode) |
295 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
296 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
297 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
298 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
299 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
300 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
301 /* point size 12.4 fixed point */
302 tmp = (unsigned)(state->point_size * 8.0);
303 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
304 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
305
306 tmp = (unsigned)state->line_width * 8;
307 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
308
309 if (family == CHIP_CAYMAN) {
310 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
311 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
312 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
313 0xFFFFFFFF, NULL);
314 r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
315 r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
316 r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
317 r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
318
319
320 } else {
321 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
322
323 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
324 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
325 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
326 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
327
328 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
329 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
330 0xFFFFFFFF, NULL);
331 }
332 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
333 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
334 return rstate;
335 }
336
337 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
338 const struct pipe_sampler_state *state)
339 {
340 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
341 union util_color uc;
342 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
343
344 if (rstate == NULL) {
345 return NULL;
346 }
347
348 rstate->id = R600_PIPE_STATE_SAMPLER;
349 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
350 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
351 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
352 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
353 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
354 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
355 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
356 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
357 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
358 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
359 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
360 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
361 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
362 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
363 0xFFFFFFFF, NULL);
364 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
365 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
366 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
367 S_03C008_TYPE(1),
368 0xFFFFFFFF, NULL);
369
370 if (uc.ui) {
371 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
372 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
373 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
374 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
375 }
376 return rstate;
377 }
378
379 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
380 struct pipe_resource *texture,
381 const struct pipe_sampler_view *state)
382 {
383 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
384 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
385 struct r600_pipe_state *rstate;
386 const struct util_format_description *desc;
387 struct r600_resource_texture *tmp;
388 struct r600_resource *rbuffer;
389 unsigned format, endian;
390 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
391 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
392 struct r600_bo *bo[2];
393
394 if (resource == NULL)
395 return NULL;
396 rstate = &resource->state;
397
398 /* initialize base object */
399 resource->base = *state;
400 resource->base.texture = NULL;
401 pipe_reference(NULL, &texture->reference);
402 resource->base.texture = texture;
403 resource->base.reference.count = 1;
404 resource->base.context = ctx;
405
406 swizzle[0] = state->swizzle_r;
407 swizzle[1] = state->swizzle_g;
408 swizzle[2] = state->swizzle_b;
409 swizzle[3] = state->swizzle_a;
410 format = r600_translate_texformat(ctx->screen, state->format,
411 swizzle,
412 &word4, &yuv_format);
413 if (format == ~0) {
414 format = 0;
415 }
416 desc = util_format_description(state->format);
417 if (desc == NULL) {
418 R600_ERR("unknow format %d\n", state->format);
419 }
420 tmp = (struct r600_resource_texture *)texture;
421 if (tmp->depth && !tmp->is_flushing_texture) {
422 r600_texture_depth_flush(ctx, texture, TRUE);
423 tmp = tmp->flushed_depth_texture;
424 }
425
426 endian = r600_colorformat_endian_swap(format);
427
428 if (tmp->force_int_type) {
429 word4 &= C_030010_NUM_FORMAT_ALL;
430 word4 |= S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_INT);
431 }
432
433 rbuffer = &tmp->resource;
434 bo[0] = rbuffer->bo;
435 bo[1] = rbuffer->bo;
436
437 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
438 array_mode = tmp->array_mode[0];
439 tile_type = tmp->tile_type;
440
441 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
442 S_030000_DIM(r600_tex_dim(texture->target)) |
443 S_030000_PITCH((pitch / 8) - 1) |
444 S_030000_NON_DISP_TILING_ORDER(tile_type) |
445 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
446 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
447 S_030004_TEX_HEIGHT(texture->height0 - 1) |
448 S_030004_TEX_DEPTH(texture->depth0 - 1) |
449 S_030004_ARRAY_MODE(array_mode),
450 0xFFFFFFFF, NULL);
451 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
452 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
453 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
454 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
455 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
456 word4 |
457 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
458 S_030010_ENDIAN_SWAP(endian) |
459 S_030010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
460 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
461 S_030014_LAST_LEVEL(state->u.tex.last_level) |
462 S_030014_BASE_ARRAY(0) |
463 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
464 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
465 S_030018_MAX_ANISO(4 /* max 16 samples */),
466 0xFFFFFFFF, NULL);
467 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
468 S_03001C_DATA_FORMAT(format) |
469 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
470
471 return &resource->base;
472 }
473
474 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
475 struct pipe_sampler_view **views)
476 {
477 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
478 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
479
480 for (int i = 0; i < count; i++) {
481 if (resource[i]) {
482 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
483 i + R600_MAX_CONST_BUFFERS);
484 }
485 }
486 }
487
488 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
489 struct pipe_sampler_view **views)
490 {
491 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
492 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
493 int i;
494
495 for (i = 0; i < count; i++) {
496 if (&rctx->ps_samplers.views[i]->base != views[i]) {
497 if (resource[i])
498 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
499 i + R600_MAX_CONST_BUFFERS);
500 else
501 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
502 i + R600_MAX_CONST_BUFFERS);
503
504 pipe_sampler_view_reference(
505 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
506 views[i]);
507 }
508 }
509 for (i = count; i < NUM_TEX_UNITS; i++) {
510 if (rctx->ps_samplers.views[i]) {
511 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
512 i + R600_MAX_CONST_BUFFERS);
513 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
514 }
515 }
516 rctx->ps_samplers.n_views = count;
517 }
518
519 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
520 {
521 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
522 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
523
524
525 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
526 rctx->ps_samplers.n_samplers = count;
527
528 for (int i = 0; i < count; i++) {
529 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
530 }
531 }
532
533 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
534 {
535 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
536 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
537
538 for (int i = 0; i < count; i++) {
539 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
540 }
541 }
542
543 static void evergreen_set_clip_state(struct pipe_context *ctx,
544 const struct pipe_clip_state *state)
545 {
546 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
547 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
548
549 if (rstate == NULL)
550 return;
551
552 rctx->clip = *state;
553 rstate->id = R600_PIPE_STATE_CLIP;
554 for (int i = 0; i < state->nr; i++) {
555 r600_pipe_state_add_reg(rstate,
556 R_0285BC_PA_CL_UCP0_X + i * 16,
557 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
558 r600_pipe_state_add_reg(rstate,
559 R_0285C0_PA_CL_UCP0_Y + i * 16,
560 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
561 r600_pipe_state_add_reg(rstate,
562 R_0285C4_PA_CL_UCP0_Z + i * 16,
563 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
564 r600_pipe_state_add_reg(rstate,
565 R_0285C8_PA_CL_UCP0_W + i * 16,
566 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
567 }
568 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
569 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
570 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
571 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
572
573 free(rctx->states[R600_PIPE_STATE_CLIP]);
574 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
575 r600_context_pipe_state_set(&rctx->ctx, rstate);
576 }
577
578 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
579 const struct pipe_poly_stipple *state)
580 {
581 }
582
583 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
584 {
585 }
586
587 static void evergreen_set_scissor_state(struct pipe_context *ctx,
588 const struct pipe_scissor_state *state)
589 {
590 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
591 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
592 u32 tl, br;
593
594 if (rstate == NULL)
595 return;
596
597 rstate->id = R600_PIPE_STATE_SCISSOR;
598 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
599 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
600 r600_pipe_state_add_reg(rstate,
601 R_028210_PA_SC_CLIPRECT_0_TL, tl,
602 0xFFFFFFFF, NULL);
603 r600_pipe_state_add_reg(rstate,
604 R_028214_PA_SC_CLIPRECT_0_BR, br,
605 0xFFFFFFFF, NULL);
606 r600_pipe_state_add_reg(rstate,
607 R_028218_PA_SC_CLIPRECT_1_TL, tl,
608 0xFFFFFFFF, NULL);
609 r600_pipe_state_add_reg(rstate,
610 R_02821C_PA_SC_CLIPRECT_1_BR, br,
611 0xFFFFFFFF, NULL);
612 r600_pipe_state_add_reg(rstate,
613 R_028220_PA_SC_CLIPRECT_2_TL, tl,
614 0xFFFFFFFF, NULL);
615 r600_pipe_state_add_reg(rstate,
616 R_028224_PA_SC_CLIPRECT_2_BR, br,
617 0xFFFFFFFF, NULL);
618 r600_pipe_state_add_reg(rstate,
619 R_028228_PA_SC_CLIPRECT_3_TL, tl,
620 0xFFFFFFFF, NULL);
621 r600_pipe_state_add_reg(rstate,
622 R_02822C_PA_SC_CLIPRECT_3_BR, br,
623 0xFFFFFFFF, NULL);
624
625 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
626 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
627 r600_context_pipe_state_set(&rctx->ctx, rstate);
628 }
629
630 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
631 const struct pipe_stencil_ref *state)
632 {
633 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
634 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
635 u32 tmp;
636
637 if (rstate == NULL)
638 return;
639
640 rctx->stencil_ref = *state;
641 rstate->id = R600_PIPE_STATE_STENCIL_REF;
642 tmp = S_028430_STENCILREF(state->ref_value[0]);
643 r600_pipe_state_add_reg(rstate,
644 R_028430_DB_STENCILREFMASK, tmp,
645 ~C_028430_STENCILREF, NULL);
646 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
647 r600_pipe_state_add_reg(rstate,
648 R_028434_DB_STENCILREFMASK_BF, tmp,
649 ~C_028434_STENCILREF_BF, NULL);
650
651 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
652 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
653 r600_context_pipe_state_set(&rctx->ctx, rstate);
654 }
655
656 static void evergreen_set_viewport_state(struct pipe_context *ctx,
657 const struct pipe_viewport_state *state)
658 {
659 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
660 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
661
662 if (rstate == NULL)
663 return;
664
665 rctx->viewport = *state;
666 rstate->id = R600_PIPE_STATE_VIEWPORT;
667 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
668 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
669 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
670 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
671 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
672 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
673 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
674 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
675 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
676
677 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
678 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
679 r600_context_pipe_state_set(&rctx->ctx, rstate);
680 }
681
682 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
683 const struct pipe_framebuffer_state *state, int cb)
684 {
685 struct r600_resource_texture *rtex;
686 struct r600_resource *rbuffer;
687 struct r600_surface *surf;
688 unsigned level = state->cbufs[cb]->u.tex.level;
689 unsigned pitch, slice;
690 unsigned color_info;
691 unsigned format, swap, ntype, endian;
692 unsigned offset;
693 unsigned tile_type;
694 const struct util_format_description *desc;
695 struct r600_bo *bo[3];
696 int i;
697
698 surf = (struct r600_surface *)state->cbufs[cb];
699 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
700
701 if (rtex->depth && !rtex->is_flushing_texture) {
702 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
703 rtex = rtex->flushed_depth_texture;
704 }
705
706 rbuffer = &rtex->resource;
707 bo[0] = rbuffer->bo;
708 bo[1] = rbuffer->bo;
709 bo[2] = rbuffer->bo;
710
711 /* XXX quite sure for dx10+ hw don't need any offset hacks */
712 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
713 level, state->cbufs[cb]->u.tex.first_layer);
714 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
715 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
716 desc = util_format_description(surf->base.format);
717 for (i = 0; i < 4; i++) {
718 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
719 break;
720 }
721 }
722 ntype = V_028C70_NUMBER_UNORM;
723 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
724 ntype = V_028C70_NUMBER_SRGB;
725 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
726 ntype = V_028C70_NUMBER_SNORM;
727
728 format = r600_translate_colorformat(surf->base.format);
729 swap = r600_translate_colorswap(surf->base.format);
730 if (rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
731 endian = ENDIAN_NONE;
732 } else {
733 endian = r600_colorformat_endian_swap(format);
734 }
735
736 /* disable when gallium grows int textures */
737 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
738 ntype = V_028C70_NUMBER_UINT;
739
740 color_info = S_028C70_FORMAT(format) |
741 S_028C70_COMP_SWAP(swap) |
742 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
743 S_028C70_BLEND_CLAMP(1) |
744 S_028C70_NUMBER_TYPE(ntype) |
745 S_028C70_ENDIAN(endian);
746
747
748 /* EXPORT_NORM is an optimzation that can be enabled for better
749 * performance in certain cases.
750 * EXPORT_NORM can be enabled if:
751 * - 11-bit or smaller UNORM/SNORM/SRGB
752 * - 16-bit or smaller FLOAT
753 */
754 /* FIXME: This should probably be the same for all CBs if we want
755 * useful alpha tests. */
756 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
757 ((desc->channel[i].size < 12 &&
758 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
759 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
760 (desc->channel[i].size < 17 &&
761 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
762 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
763 rctx->export_16bpc = true;
764 } else {
765 rctx->export_16bpc = false;
766 }
767 rctx->alpha_ref_dirty = true;
768
769 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
770 tile_type = rtex->tile_type;
771 } else /* workaround for linear buffers */
772 tile_type = 1;
773
774 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
775 r600_pipe_state_add_reg(rstate,
776 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
777 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
778 r600_pipe_state_add_reg(rstate,
779 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
780 0x0, 0xFFFFFFFF, NULL);
781 r600_pipe_state_add_reg(rstate,
782 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
783 color_info, 0xFFFFFFFF, bo[0]);
784 r600_pipe_state_add_reg(rstate,
785 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
786 S_028C64_PITCH_TILE_MAX(pitch),
787 0xFFFFFFFF, NULL);
788 r600_pipe_state_add_reg(rstate,
789 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
790 S_028C68_SLICE_TILE_MAX(slice),
791 0xFFFFFFFF, NULL);
792 r600_pipe_state_add_reg(rstate,
793 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
794 0x00000000, 0xFFFFFFFF, NULL);
795 r600_pipe_state_add_reg(rstate,
796 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
797 S_028C74_NON_DISP_TILING_ORDER(tile_type),
798 0xFFFFFFFF, bo[0]);
799 }
800
801 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
802 const struct pipe_framebuffer_state *state)
803 {
804 struct r600_resource_texture *rtex;
805 struct r600_resource *rbuffer;
806 struct r600_surface *surf;
807 unsigned level;
808 unsigned pitch, slice, format, stencil_format;
809 unsigned offset;
810
811 if (state->zsbuf == NULL)
812 return;
813
814 level = state->zsbuf->u.tex.level;
815
816 surf = (struct r600_surface *)state->zsbuf;
817 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
818
819 rbuffer = &rtex->resource;
820
821 /* XXX quite sure for dx10+ hw don't need any offset hacks */
822 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
823 level, state->zsbuf->u.tex.first_layer);
824 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
825 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
826 format = r600_translate_dbformat(state->zsbuf->texture->format);
827 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
828
829 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
830 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
831 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
832 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
833
834 if (stencil_format) {
835 uint32_t stencil_offset;
836
837 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
838 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
839 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
840 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
841 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
842 }
843
844 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
845 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
846 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
847
848 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
849 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
850 0xFFFFFFFF, rbuffer->bo);
851 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
852 S_028058_PITCH_TILE_MAX(pitch),
853 0xFFFFFFFF, NULL);
854 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
855 S_02805C_SLICE_TILE_MAX(slice),
856 0xFFFFFFFF, NULL);
857 }
858
859 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
860 const struct pipe_framebuffer_state *state)
861 {
862 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
863 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
864 u32 shader_mask, tl, br, target_mask;
865 enum radeon_family family;
866 int tl_x, tl_y, br_x, br_y;
867
868 if (rstate == NULL)
869 return;
870
871 family = r600_get_family(rctx->radeon);
872
873 evergreen_context_flush_dest_caches(&rctx->ctx);
874 rctx->ctx.num_dest_buffers = state->nr_cbufs;
875
876 /* unreference old buffer and reference new one */
877 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
878
879 util_copy_framebuffer_state(&rctx->framebuffer, state);
880
881 /* build states */
882 for (int i = 0; i < state->nr_cbufs; i++) {
883 evergreen_cb(rctx, rstate, state, i);
884 }
885 if (state->zsbuf) {
886 evergreen_db(rctx, rstate, state);
887 rctx->ctx.num_dest_buffers++;
888 }
889
890 target_mask = 0x00000000;
891 target_mask = 0xFFFFFFFF;
892 shader_mask = 0;
893 for (int i = 0; i < state->nr_cbufs; i++) {
894 target_mask ^= 0xf << (i * 4);
895 shader_mask |= 0xf << (i * 4);
896 }
897 tl_x = 0;
898 tl_y = 0;
899 br_x = state->width;
900 br_y = state->height;
901 /* EG hw workaround */
902 if (br_x == 0)
903 tl_x = 1;
904 if (br_y == 0)
905 tl_y = 1;
906 /* cayman hw workaround */
907 if (family == CHIP_CAYMAN) {
908 if (br_x == 1 && br_y == 1)
909 br_x = 2;
910 }
911 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
912 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
913
914 r600_pipe_state_add_reg(rstate,
915 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
916 0xFFFFFFFF, NULL);
917 r600_pipe_state_add_reg(rstate,
918 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
919 0xFFFFFFFF, NULL);
920 r600_pipe_state_add_reg(rstate,
921 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
922 0xFFFFFFFF, NULL);
923 r600_pipe_state_add_reg(rstate,
924 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
925 0xFFFFFFFF, NULL);
926 r600_pipe_state_add_reg(rstate,
927 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
928 0xFFFFFFFF, NULL);
929 r600_pipe_state_add_reg(rstate,
930 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
931 0xFFFFFFFF, NULL);
932 r600_pipe_state_add_reg(rstate,
933 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
934 0xFFFFFFFF, NULL);
935 r600_pipe_state_add_reg(rstate,
936 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
937 0xFFFFFFFF, NULL);
938 r600_pipe_state_add_reg(rstate,
939 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
940 0xFFFFFFFF, NULL);
941 r600_pipe_state_add_reg(rstate,
942 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
943 0xFFFFFFFF, NULL);
944
945 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
946 0x00000000, target_mask, NULL);
947 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
948 shader_mask, 0xFFFFFFFF, NULL);
949
950
951 if (family == CHIP_CAYMAN) {
952 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
953 0x00000000, 0xFFFFFFFF, NULL);
954 } else {
955 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
956 0x00000000, 0xFFFFFFFF, NULL);
957 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
958 0x00000000, 0xFFFFFFFF, NULL);
959 }
960
961 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
962 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
963 r600_context_pipe_state_set(&rctx->ctx, rstate);
964
965 if (state->zsbuf) {
966 evergreen_polygon_offset_update(rctx);
967 }
968 }
969
970 static void evergreen_texture_barrier(struct pipe_context *ctx)
971 {
972 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
973
974 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
975 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
976 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
977 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
978 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
979 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
980 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
981 }
982
983 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
984 {
985 rctx->context.create_blend_state = evergreen_create_blend_state;
986 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
987 rctx->context.create_fs_state = r600_create_shader_state;
988 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
989 rctx->context.create_sampler_state = evergreen_create_sampler_state;
990 rctx->context.create_sampler_view = evergreen_create_sampler_view;
991 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
992 rctx->context.create_vs_state = r600_create_shader_state;
993 rctx->context.bind_blend_state = r600_bind_blend_state;
994 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
995 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
996 rctx->context.bind_fs_state = r600_bind_ps_shader;
997 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
998 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
999 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1000 rctx->context.bind_vs_state = r600_bind_vs_shader;
1001 rctx->context.delete_blend_state = r600_delete_state;
1002 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1003 rctx->context.delete_fs_state = r600_delete_ps_shader;
1004 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1005 rctx->context.delete_sampler_state = r600_delete_state;
1006 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1007 rctx->context.delete_vs_state = r600_delete_vs_shader;
1008 rctx->context.set_blend_color = evergreen_set_blend_color;
1009 rctx->context.set_clip_state = evergreen_set_clip_state;
1010 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1011 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1012 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1013 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1014 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1015 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1016 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1017 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1018 rctx->context.set_index_buffer = r600_set_index_buffer;
1019 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1020 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1021 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1022 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1023 rctx->context.texture_barrier = evergreen_texture_barrier;
1024 }
1025
1026 static void cayman_init_config(struct r600_pipe_context *rctx)
1027 {
1028 struct r600_pipe_state *rstate = &rctx->config;
1029 unsigned tmp;
1030
1031 tmp = 0x00000000;
1032 tmp |= S_008C00_EXPORT_SRC_C(1);
1033 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1034
1035 r600_pipe_state_add_reg(rstate, CM_R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, (4 << 28), 0xFFFFFFFF, NULL);
1036 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL);
1037
1038 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1039 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1040
1041 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1042 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1043 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1044 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1045 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1046 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1047 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1048 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1049 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1050 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1051 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1052 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1053 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1054 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1055 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1056 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1057 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1058 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1059
1060 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1061 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1062 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1063 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1064 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1065 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1066 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1067 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1068 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1069 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1070 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1071 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1072 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1073 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1074 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1075 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1076 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1077 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1078 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1079 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1080 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1081 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1082 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1083 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1084 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1085 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1086 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1087 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1088 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1089 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1090 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1091 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1092
1093 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
1094
1095 r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, 0xffffffff, 0);
1096 r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, 0xffffffff, 0);
1097
1098 r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, 0xffffffff, NULL);
1099 r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0xffffffff, NULL);
1100
1101 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, 0xffffffff, NULL);
1102 r600_context_pipe_state_set(&rctx->ctx, rstate);
1103 }
1104
1105 void evergreen_init_config(struct r600_pipe_context *rctx)
1106 {
1107 struct r600_pipe_state *rstate = &rctx->config;
1108 int ps_prio;
1109 int vs_prio;
1110 int gs_prio;
1111 int es_prio;
1112 int hs_prio, cs_prio, ls_prio;
1113 int num_ps_gprs;
1114 int num_vs_gprs;
1115 int num_gs_gprs;
1116 int num_es_gprs;
1117 int num_hs_gprs;
1118 int num_ls_gprs;
1119 int num_temp_gprs;
1120 int num_ps_threads;
1121 int num_vs_threads;
1122 int num_gs_threads;
1123 int num_es_threads;
1124 int num_hs_threads;
1125 int num_ls_threads;
1126 int num_ps_stack_entries;
1127 int num_vs_stack_entries;
1128 int num_gs_stack_entries;
1129 int num_es_stack_entries;
1130 int num_hs_stack_entries;
1131 int num_ls_stack_entries;
1132 enum radeon_family family;
1133 unsigned tmp;
1134
1135 family = r600_get_family(rctx->radeon);
1136
1137 if (family == CHIP_CAYMAN) {
1138 cayman_init_config(rctx);
1139 return;
1140 }
1141
1142 ps_prio = 0;
1143 vs_prio = 1;
1144 gs_prio = 2;
1145 es_prio = 3;
1146 hs_prio = 0;
1147 ls_prio = 0;
1148 cs_prio = 0;
1149
1150 switch (family) {
1151 case CHIP_CEDAR:
1152 default:
1153 num_ps_gprs = 93;
1154 num_vs_gprs = 46;
1155 num_temp_gprs = 4;
1156 num_gs_gprs = 31;
1157 num_es_gprs = 31;
1158 num_hs_gprs = 23;
1159 num_ls_gprs = 23;
1160 num_ps_threads = 96;
1161 num_vs_threads = 16;
1162 num_gs_threads = 16;
1163 num_es_threads = 16;
1164 num_hs_threads = 16;
1165 num_ls_threads = 16;
1166 num_ps_stack_entries = 42;
1167 num_vs_stack_entries = 42;
1168 num_gs_stack_entries = 42;
1169 num_es_stack_entries = 42;
1170 num_hs_stack_entries = 42;
1171 num_ls_stack_entries = 42;
1172 break;
1173 case CHIP_REDWOOD:
1174 num_ps_gprs = 93;
1175 num_vs_gprs = 46;
1176 num_temp_gprs = 4;
1177 num_gs_gprs = 31;
1178 num_es_gprs = 31;
1179 num_hs_gprs = 23;
1180 num_ls_gprs = 23;
1181 num_ps_threads = 128;
1182 num_vs_threads = 20;
1183 num_gs_threads = 20;
1184 num_es_threads = 20;
1185 num_hs_threads = 20;
1186 num_ls_threads = 20;
1187 num_ps_stack_entries = 42;
1188 num_vs_stack_entries = 42;
1189 num_gs_stack_entries = 42;
1190 num_es_stack_entries = 42;
1191 num_hs_stack_entries = 42;
1192 num_ls_stack_entries = 42;
1193 break;
1194 case CHIP_JUNIPER:
1195 num_ps_gprs = 93;
1196 num_vs_gprs = 46;
1197 num_temp_gprs = 4;
1198 num_gs_gprs = 31;
1199 num_es_gprs = 31;
1200 num_hs_gprs = 23;
1201 num_ls_gprs = 23;
1202 num_ps_threads = 128;
1203 num_vs_threads = 20;
1204 num_gs_threads = 20;
1205 num_es_threads = 20;
1206 num_hs_threads = 20;
1207 num_ls_threads = 20;
1208 num_ps_stack_entries = 85;
1209 num_vs_stack_entries = 85;
1210 num_gs_stack_entries = 85;
1211 num_es_stack_entries = 85;
1212 num_hs_stack_entries = 85;
1213 num_ls_stack_entries = 85;
1214 break;
1215 case CHIP_CYPRESS:
1216 case CHIP_HEMLOCK:
1217 num_ps_gprs = 93;
1218 num_vs_gprs = 46;
1219 num_temp_gprs = 4;
1220 num_gs_gprs = 31;
1221 num_es_gprs = 31;
1222 num_hs_gprs = 23;
1223 num_ls_gprs = 23;
1224 num_ps_threads = 128;
1225 num_vs_threads = 20;
1226 num_gs_threads = 20;
1227 num_es_threads = 20;
1228 num_hs_threads = 20;
1229 num_ls_threads = 20;
1230 num_ps_stack_entries = 85;
1231 num_vs_stack_entries = 85;
1232 num_gs_stack_entries = 85;
1233 num_es_stack_entries = 85;
1234 num_hs_stack_entries = 85;
1235 num_ls_stack_entries = 85;
1236 break;
1237 case CHIP_PALM:
1238 num_ps_gprs = 93;
1239 num_vs_gprs = 46;
1240 num_temp_gprs = 4;
1241 num_gs_gprs = 31;
1242 num_es_gprs = 31;
1243 num_hs_gprs = 23;
1244 num_ls_gprs = 23;
1245 num_ps_threads = 96;
1246 num_vs_threads = 16;
1247 num_gs_threads = 16;
1248 num_es_threads = 16;
1249 num_hs_threads = 16;
1250 num_ls_threads = 16;
1251 num_ps_stack_entries = 42;
1252 num_vs_stack_entries = 42;
1253 num_gs_stack_entries = 42;
1254 num_es_stack_entries = 42;
1255 num_hs_stack_entries = 42;
1256 num_ls_stack_entries = 42;
1257 break;
1258 case CHIP_SUMO:
1259 num_ps_gprs = 93;
1260 num_vs_gprs = 46;
1261 num_temp_gprs = 4;
1262 num_gs_gprs = 31;
1263 num_es_gprs = 31;
1264 num_hs_gprs = 23;
1265 num_ls_gprs = 23;
1266 num_ps_threads = 96;
1267 num_vs_threads = 25;
1268 num_gs_threads = 25;
1269 num_es_threads = 25;
1270 num_hs_threads = 25;
1271 num_ls_threads = 25;
1272 num_ps_stack_entries = 42;
1273 num_vs_stack_entries = 42;
1274 num_gs_stack_entries = 42;
1275 num_es_stack_entries = 42;
1276 num_hs_stack_entries = 42;
1277 num_ls_stack_entries = 42;
1278 break;
1279 case CHIP_SUMO2:
1280 num_ps_gprs = 93;
1281 num_vs_gprs = 46;
1282 num_temp_gprs = 4;
1283 num_gs_gprs = 31;
1284 num_es_gprs = 31;
1285 num_hs_gprs = 23;
1286 num_ls_gprs = 23;
1287 num_ps_threads = 96;
1288 num_vs_threads = 25;
1289 num_gs_threads = 25;
1290 num_es_threads = 25;
1291 num_hs_threads = 25;
1292 num_ls_threads = 25;
1293 num_ps_stack_entries = 85;
1294 num_vs_stack_entries = 85;
1295 num_gs_stack_entries = 85;
1296 num_es_stack_entries = 85;
1297 num_hs_stack_entries = 85;
1298 num_ls_stack_entries = 85;
1299 break;
1300 case CHIP_BARTS:
1301 num_ps_gprs = 93;
1302 num_vs_gprs = 46;
1303 num_temp_gprs = 4;
1304 num_gs_gprs = 31;
1305 num_es_gprs = 31;
1306 num_hs_gprs = 23;
1307 num_ls_gprs = 23;
1308 num_ps_threads = 128;
1309 num_vs_threads = 20;
1310 num_gs_threads = 20;
1311 num_es_threads = 20;
1312 num_hs_threads = 20;
1313 num_ls_threads = 20;
1314 num_ps_stack_entries = 85;
1315 num_vs_stack_entries = 85;
1316 num_gs_stack_entries = 85;
1317 num_es_stack_entries = 85;
1318 num_hs_stack_entries = 85;
1319 num_ls_stack_entries = 85;
1320 break;
1321 case CHIP_TURKS:
1322 num_ps_gprs = 93;
1323 num_vs_gprs = 46;
1324 num_temp_gprs = 4;
1325 num_gs_gprs = 31;
1326 num_es_gprs = 31;
1327 num_hs_gprs = 23;
1328 num_ls_gprs = 23;
1329 num_ps_threads = 128;
1330 num_vs_threads = 20;
1331 num_gs_threads = 20;
1332 num_es_threads = 20;
1333 num_hs_threads = 20;
1334 num_ls_threads = 20;
1335 num_ps_stack_entries = 42;
1336 num_vs_stack_entries = 42;
1337 num_gs_stack_entries = 42;
1338 num_es_stack_entries = 42;
1339 num_hs_stack_entries = 42;
1340 num_ls_stack_entries = 42;
1341 break;
1342 case CHIP_CAICOS:
1343 num_ps_gprs = 93;
1344 num_vs_gprs = 46;
1345 num_temp_gprs = 4;
1346 num_gs_gprs = 31;
1347 num_es_gprs = 31;
1348 num_hs_gprs = 23;
1349 num_ls_gprs = 23;
1350 num_ps_threads = 128;
1351 num_vs_threads = 10;
1352 num_gs_threads = 10;
1353 num_es_threads = 10;
1354 num_hs_threads = 10;
1355 num_ls_threads = 10;
1356 num_ps_stack_entries = 42;
1357 num_vs_stack_entries = 42;
1358 num_gs_stack_entries = 42;
1359 num_es_stack_entries = 42;
1360 num_hs_stack_entries = 42;
1361 num_ls_stack_entries = 42;
1362 break;
1363 }
1364
1365 tmp = 0x00000000;
1366 switch (family) {
1367 case CHIP_CEDAR:
1368 case CHIP_PALM:
1369 case CHIP_SUMO:
1370 case CHIP_SUMO2:
1371 case CHIP_CAICOS:
1372 break;
1373 default:
1374 tmp |= S_008C00_VC_ENABLE(1);
1375 break;
1376 }
1377 tmp |= S_008C00_EXPORT_SRC_C(1);
1378 tmp |= S_008C00_CS_PRIO(cs_prio);
1379 tmp |= S_008C00_LS_PRIO(ls_prio);
1380 tmp |= S_008C00_HS_PRIO(hs_prio);
1381 tmp |= S_008C00_PS_PRIO(ps_prio);
1382 tmp |= S_008C00_VS_PRIO(vs_prio);
1383 tmp |= S_008C00_GS_PRIO(gs_prio);
1384 tmp |= S_008C00_ES_PRIO(es_prio);
1385 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1386
1387 tmp = 0;
1388 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1389 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1390 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1391 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1392
1393 tmp = 0;
1394 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1395 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1396 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1397
1398 tmp = 0;
1399 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1400 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1401 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1402
1403 tmp = 0;
1404 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1405 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1406 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1407 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1408 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1409
1410 tmp = 0;
1411 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1412 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1413 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1414
1415 tmp = 0;
1416 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1417 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1418 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1419
1420 tmp = 0;
1421 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1422 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1423 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1424
1425 tmp = 0;
1426 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1427 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1428 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1429
1430 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1431 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1432
1433 #if 0
1434 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1435
1436 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1437 #endif
1438 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1439 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1440
1441 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1442 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1443 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1444 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1445 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1446 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1447
1448 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1449 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1450 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1451 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1452
1453 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1454 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1455 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1456 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1457 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1458 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1459 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1460 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1461 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1462 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1463 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1464 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1465 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1466 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1467 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1468 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1469 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1470 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1471
1472 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1473 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1474 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1475 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1476 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1477 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1478 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1479 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1480 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1481 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1482 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1483 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1484 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1485 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1486 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1487 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1488 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1489 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1490 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1491 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1492 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1493 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1494 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1495 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1496 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1497 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1498 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1499 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1500 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1501 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1502 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1503 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1504
1505 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
1506
1507 r600_context_pipe_state_set(&rctx->ctx, rstate);
1508 }
1509
1510 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
1511 {
1512 struct r600_pipe_state state;
1513
1514 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
1515 state.nregs = 0;
1516 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1517 float offset_units = rctx->rasterizer->offset_units;
1518 unsigned offset_db_fmt_cntl = 0, depth;
1519
1520 switch (rctx->framebuffer.zsbuf->texture->format) {
1521 case PIPE_FORMAT_Z24X8_UNORM:
1522 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1523 depth = -24;
1524 offset_units *= 2.0f;
1525 break;
1526 case PIPE_FORMAT_Z32_FLOAT:
1527 depth = -23;
1528 offset_units *= 1.0f;
1529 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1530 break;
1531 case PIPE_FORMAT_Z16_UNORM:
1532 depth = -16;
1533 offset_units *= 4.0f;
1534 break;
1535 default:
1536 return;
1537 }
1538 /* FIXME some of those reg can be computed with cso */
1539 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1540 r600_pipe_state_add_reg(&state,
1541 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1542 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1543 r600_pipe_state_add_reg(&state,
1544 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1545 fui(offset_units), 0xFFFFFFFF, NULL);
1546 r600_pipe_state_add_reg(&state,
1547 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1548 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1549 r600_pipe_state_add_reg(&state,
1550 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1551 fui(offset_units), 0xFFFFFFFF, NULL);
1552 r600_pipe_state_add_reg(&state,
1553 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1554 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1555 r600_context_pipe_state_set(&rctx->ctx, &state);
1556 }
1557 }
1558
1559 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1560 {
1561 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1562 struct r600_pipe_state *rstate = &shader->rstate;
1563 struct r600_shader *rshader = &shader->shader;
1564 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
1565 int pos_index = -1, face_index = -1;
1566 int ninterp = 0;
1567 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1568 unsigned spi_baryc_cntl;
1569
1570 rstate->nregs = 0;
1571
1572 db_shader_control = 0;
1573 for (i = 0; i < rshader->ninput; i++) {
1574 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1575 POSITION goes via GPRs from the SC so isn't counted */
1576 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1577 pos_index = i;
1578 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1579 face_index = i;
1580 else {
1581 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
1582 rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1583 ninterp++;
1584 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1585 have_linear = TRUE;
1586 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1587 have_perspective = TRUE;
1588 if (rshader->input[i].centroid)
1589 have_centroid = TRUE;
1590 }
1591 }
1592 for (i = 0; i < rshader->noutput; i++) {
1593 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1594 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1595 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1596 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
1597 }
1598 if (rshader->uses_kill)
1599 db_shader_control |= S_02880C_KILL_ENABLE(1);
1600
1601 exports_ps = 0;
1602 num_cout = 0;
1603 for (i = 0; i < rshader->noutput; i++) {
1604 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1605 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1606 exports_ps |= 1;
1607 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1608 num_cout++;
1609 }
1610 }
1611 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1612 if (!exports_ps) {
1613 /* always at least export 1 component per pixel */
1614 exports_ps = 2;
1615 }
1616
1617 if (ninterp == 0) {
1618 ninterp = 1;
1619 have_perspective = TRUE;
1620 }
1621
1622 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
1623 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
1624 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
1625 spi_input_z = 0;
1626 if (pos_index != -1) {
1627 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
1628 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1629 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
1630 spi_input_z |= 1;
1631 }
1632
1633 spi_ps_in_control_1 = 0;
1634 if (face_index != -1) {
1635 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1636 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1637 }
1638
1639 spi_baryc_cntl = 0;
1640 if (have_perspective)
1641 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
1642 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
1643 if (have_linear)
1644 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
1645 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
1646
1647 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1648 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1649 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1650 spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1651 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
1652 0, 0xFFFFFFFF, NULL);
1653 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1654 r600_pipe_state_add_reg(rstate,
1655 R_0286E0_SPI_BARYC_CNTL,
1656 spi_baryc_cntl,
1657 0xFFFFFFFF, NULL);
1658
1659 r600_pipe_state_add_reg(rstate,
1660 R_028840_SQ_PGM_START_PS,
1661 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1662 r600_pipe_state_add_reg(rstate,
1663 R_028844_SQ_PGM_RESOURCES_PS,
1664 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1665 S_028844_PRIME_CACHE_ON_DRAW(1) |
1666 S_028844_STACK_SIZE(rshader->bc.nstack),
1667 0xFFFFFFFF, NULL);
1668 r600_pipe_state_add_reg(rstate,
1669 R_028848_SQ_PGM_RESOURCES_2_PS,
1670 0x0, 0xFFFFFFFF, NULL);
1671 r600_pipe_state_add_reg(rstate,
1672 R_02884C_SQ_PGM_EXPORTS_PS,
1673 exports_ps, 0xFFFFFFFF, NULL);
1674 /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */
1675 /* only set some bits here, the other bits are set in the dsa state */
1676 r600_pipe_state_add_reg(rstate,
1677 R_02880C_DB_SHADER_CONTROL,
1678 db_shader_control,
1679 S_02880C_Z_EXPORT_ENABLE(1) |
1680 S_02880C_STENCIL_EXPORT_ENABLE(1) |
1681 S_02880C_KILL_ENABLE(1),
1682 NULL);
1683 r600_pipe_state_add_reg(rstate,
1684 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
1685 0xFFFFFFFF, NULL);
1686 }
1687
1688 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1689 {
1690 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1691 struct r600_pipe_state *rstate = &shader->rstate;
1692 struct r600_shader *rshader = &shader->shader;
1693 unsigned spi_vs_out_id[10];
1694 unsigned i, tmp;
1695
1696 /* clear previous register */
1697 rstate->nregs = 0;
1698
1699 /* so far never got proper semantic id from tgsi */
1700 for (i = 0; i < 10; i++) {
1701 spi_vs_out_id[i] = 0;
1702 }
1703 for (i = 0; i < 32; i++) {
1704 tmp = i << ((i & 3) * 8);
1705 spi_vs_out_id[i / 4] |= tmp;
1706 }
1707 for (i = 0; i < 10; i++) {
1708 r600_pipe_state_add_reg(rstate,
1709 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1710 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1711 }
1712
1713 r600_pipe_state_add_reg(rstate,
1714 R_0286C4_SPI_VS_OUT_CONFIG,
1715 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1716 0xFFFFFFFF, NULL);
1717 r600_pipe_state_add_reg(rstate,
1718 R_028860_SQ_PGM_RESOURCES_VS,
1719 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1720 S_028860_STACK_SIZE(rshader->bc.nstack),
1721 0xFFFFFFFF, NULL);
1722 r600_pipe_state_add_reg(rstate,
1723 R_028864_SQ_PGM_RESOURCES_2_VS,
1724 0x0, 0xFFFFFFFF, NULL);
1725 r600_pipe_state_add_reg(rstate,
1726 R_02885C_SQ_PGM_START_VS,
1727 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1728
1729 r600_pipe_state_add_reg(rstate,
1730 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1731 0xFFFFFFFF, NULL);
1732 }
1733
1734 void evergreen_fetch_shader(struct pipe_context *ctx,
1735 struct r600_vertex_element *ve)
1736 {
1737 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1738 struct r600_pipe_state *rstate = &ve->rstate;
1739 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1740 rstate->nregs = 0;
1741 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
1742 0x00000000, 0xFFFFFFFF, NULL);
1743 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
1744 (r600_bo_offset(ve->fetch_shader)) >> 8,
1745 0xFFFFFFFF, ve->fetch_shader);
1746 }
1747
1748 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1749 {
1750 struct pipe_depth_stencil_alpha_state dsa;
1751 struct r600_pipe_state *rstate;
1752
1753 memset(&dsa, 0, sizeof(dsa));
1754
1755 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1756 r600_pipe_state_add_reg(rstate,
1757 R_02880C_DB_SHADER_CONTROL,
1758 0x0,
1759 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1760 r600_pipe_state_add_reg(rstate,
1761 R_028000_DB_RENDER_CONTROL,
1762 S_028000_DEPTH_COPY_ENABLE(1) |
1763 S_028000_STENCIL_COPY_ENABLE(1) |
1764 S_028000_COPY_CENTROID(1),
1765 S_028000_DEPTH_COPY_ENABLE(1) |
1766 S_028000_STENCIL_COPY_ENABLE(1) |
1767 S_028000_COPY_CENTROID(1), NULL);
1768 return rstate;
1769 }
1770
1771 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
1772 struct r600_pipe_state *rstate,
1773 struct r600_resource *rbuffer,
1774 unsigned offset, unsigned stride)
1775 {
1776 rstate->id = R600_PIPE_STATE_RESOURCE;
1777 rstate->nregs = 0;
1778 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
1779 offset, 0xFFFFFFFF, rbuffer->bo);
1780 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
1781 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
1782 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
1783 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1784 S_030008_STRIDE(stride), 0xFFFFFFFF, NULL);
1785 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
1786 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1787 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1788 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1789 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W),
1790 0xFFFFFFFF, NULL);
1791 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
1792 0x00000000, 0xFFFFFFFF, NULL);
1793 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
1794 0x00000000, 0xFFFFFFFF, NULL);
1795 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
1796 0x00000000, 0xFFFFFFFF, NULL);
1797 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
1798 0xC0000000, 0xFFFFFFFF, NULL);
1799 }
1800
1801
1802 void evergreen_pipe_mod_buffer_resource(struct r600_pipe_state *rstate,
1803 struct r600_resource *rbuffer,
1804 unsigned offset, unsigned stride)
1805 {
1806 rstate->nregs = 0;
1807 r600_pipe_state_mod_reg_bo(rstate, offset, rbuffer->bo);
1808 r600_pipe_state_mod_reg(rstate, rbuffer->bo_size - offset - 1);
1809 r600_pipe_state_mod_reg(rstate, S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1810 S_030008_STRIDE(stride));
1811 rstate->nregs = 8;
1812
1813 }