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r600g: get s3tc working on cards with crappy 64/128 bit types.
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "eg_state_inlines.h"
50
51 static void evergreen_set_blend_color(struct pipe_context *ctx,
52 const struct pipe_blend_color *state)
53 {
54 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
55 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
56
57 if (rstate == NULL)
58 return;
59
60 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
61 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
62 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
63 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
65
66 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
67 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
68 r600_context_pipe_state_set(&rctx->ctx, rstate);
69 }
70
71 static void *evergreen_create_blend_state(struct pipe_context *ctx,
72 const struct pipe_blend_state *state)
73 {
74 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
75 struct r600_pipe_state *rstate;
76 u32 color_control, target_mask;
77 /* FIXME there is more then 8 framebuffer */
78 unsigned blend_cntl[8];
79
80 if (blend == NULL) {
81 return NULL;
82 }
83 rstate = &blend->rstate;
84
85 rstate->id = R600_PIPE_STATE_BLEND;
86
87 target_mask = 0;
88 color_control = S_028808_MODE(1);
89 if (state->logicop_enable) {
90 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
91 } else {
92 color_control |= (0xcc << 16);
93 }
94 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
95 if (state->independent_blend_enable) {
96 for (int i = 0; i < 8; i++) {
97 target_mask |= (state->rt[i].colormask << (4 * i));
98 }
99 } else {
100 for (int i = 0; i < 8; i++) {
101 target_mask |= (state->rt[0].colormask << (4 * i));
102 }
103 }
104 blend->cb_target_mask = target_mask;
105 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
106 color_control, 0xFFFFFFFD, NULL);
107 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
108
109 for (int i = 0; i < 8; i++) {
110 unsigned eqRGB = state->rt[i].rgb_func;
111 unsigned srcRGB = state->rt[i].rgb_src_factor;
112 unsigned dstRGB = state->rt[i].rgb_dst_factor;
113 unsigned eqA = state->rt[i].alpha_func;
114 unsigned srcA = state->rt[i].alpha_src_factor;
115 unsigned dstA = state->rt[i].alpha_dst_factor;
116
117 blend_cntl[i] = 0;
118 if (!state->rt[i].blend_enable)
119 continue;
120
121 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
122 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
123 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
124 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
125
126 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
127 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
128 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
129 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
130 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
131 }
132 }
133 for (int i = 0; i < 8; i++) {
134 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
135 }
136
137 return rstate;
138 }
139
140 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
141 const struct pipe_depth_stencil_alpha_state *state)
142 {
143 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
144 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
145 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
146
147 if (rstate == NULL) {
148 return NULL;
149 }
150
151 rstate->id = R600_PIPE_STATE_DSA;
152 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
153 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
154 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
155 * be set if shader use texkill instruction
156 */
157 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
158 stencil_ref_mask = 0;
159 stencil_ref_mask_bf = 0;
160 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
161 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
162 S_028800_ZFUNC(state->depth.func);
163
164 /* stencil */
165 if (state->stencil[0].enabled) {
166 db_depth_control |= S_028800_STENCIL_ENABLE(1);
167 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
168 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
169 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
170 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
171
172
173 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
174 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
175 if (state->stencil[1].enabled) {
176 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
177 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
178 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
179 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
180 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
181 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
182 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
183 }
184 }
185
186 /* alpha */
187 alpha_test_control = 0;
188 alpha_ref = 0;
189 if (state->alpha.enabled) {
190 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
191 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
192 alpha_ref = fui(state->alpha.ref_value);
193 }
194
195 /* misc */
196 db_render_control = 0;
197 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
198 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
199 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
200 /* TODO db_render_override depends on query */
201 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
202 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
203 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
204 r600_pipe_state_add_reg(rstate,
205 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
206 0xFFFFFFFF & C_028430_STENCILREF, NULL);
207 r600_pipe_state_add_reg(rstate,
208 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
209 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
210 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
211 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
212 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
213 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
214 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
215 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
216 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
217 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
218 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
219 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
220
221 return rstate;
222 }
223
224 static void *evergreen_create_rs_state(struct pipe_context *ctx,
225 const struct pipe_rasterizer_state *state)
226 {
227 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
228 struct r600_pipe_state *rstate;
229 unsigned tmp;
230 unsigned prov_vtx = 1, polygon_dual_mode;
231 unsigned clip_rule;
232
233 if (rs == NULL) {
234 return NULL;
235 }
236
237 rstate = &rs->rstate;
238 rs->flatshade = state->flatshade;
239 rs->sprite_coord_enable = state->sprite_coord_enable;
240
241 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
242
243 /* offset */
244 rs->offset_units = state->offset_units;
245 rs->offset_scale = state->offset_scale * 12.0f;
246
247 rstate->id = R600_PIPE_STATE_RASTERIZER;
248 if (state->flatshade_first)
249 prov_vtx = 0;
250 tmp = S_0286D4_FLAT_SHADE_ENA(1);
251 if (state->sprite_coord_enable) {
252 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
253 S_0286D4_PNT_SPRITE_OVRD_X(2) |
254 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
255 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
256 S_0286D4_PNT_SPRITE_OVRD_W(1);
257 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
258 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
259 }
260 }
261 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
262
263 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
264 state->fill_back != PIPE_POLYGON_MODE_FILL);
265 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
266 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
267 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
268 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
269 S_028814_FACE(!state->front_ccw) |
270 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
271 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
272 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
273 S_028814_POLY_MODE(polygon_dual_mode) |
274 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
275 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
276 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
277 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
278 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
279 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
280 /* point size 12.4 fixed point */
281 tmp = (unsigned)(state->point_size * 8.0);
282 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
283 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
284
285 tmp = (unsigned)state->line_width * 8;
286 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
287
288 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
289 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
290 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
291 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
292 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
293 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
294
295 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
296 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
297 0xFFFFFFFF, NULL);
298
299 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
300 return rstate;
301 }
302
303 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
304 const struct pipe_sampler_state *state)
305 {
306 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
307 union util_color uc;
308
309 if (rstate == NULL) {
310 return NULL;
311 }
312
313 rstate->id = R600_PIPE_STATE_SAMPLER;
314 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
315 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
316 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
317 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
318 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
319 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
320 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
321 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
322 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
323 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
324 /* FIXME LOD it depends on texture base level ... */
325 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
326 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
327 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
328 0xFFFFFFFF, NULL);
329 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
330 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
331 S_03C008_TYPE(1),
332 0xFFFFFFFF, NULL);
333
334 if (uc.ui) {
335 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
336 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
337 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
338 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
339 }
340 return rstate;
341 }
342
343 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
344 struct pipe_resource *texture,
345 const struct pipe_sampler_view *state)
346 {
347 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
348 struct r600_pipe_state *rstate;
349 const struct util_format_description *desc;
350 struct r600_resource_texture *tmp;
351 struct r600_resource *rbuffer;
352 unsigned format;
353 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
354 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
355 struct r600_bo *bo[2];
356
357 if (resource == NULL)
358 return NULL;
359 rstate = &resource->state;
360
361 /* initialize base object */
362 resource->base = *state;
363 resource->base.texture = NULL;
364 pipe_reference(NULL, &texture->reference);
365 resource->base.texture = texture;
366 resource->base.reference.count = 1;
367 resource->base.context = ctx;
368
369 swizzle[0] = state->swizzle_r;
370 swizzle[1] = state->swizzle_g;
371 swizzle[2] = state->swizzle_b;
372 swizzle[3] = state->swizzle_a;
373 format = r600_translate_texformat(state->format,
374 swizzle,
375 &word4, &yuv_format);
376 if (format == ~0) {
377 format = 0;
378 }
379 desc = util_format_description(state->format);
380 if (desc == NULL) {
381 R600_ERR("unknow format %d\n", state->format);
382 }
383 tmp = (struct r600_resource_texture *)texture;
384 if (tmp->depth && !tmp->is_flushing_texture) {
385 r600_texture_depth_flush(ctx, texture, TRUE);
386 tmp = tmp->flushed_depth_texture;
387 }
388
389 if (tmp->force_int_type) {
390 word4 &= C_030010_NUM_FORMAT_ALL;
391 word4 |= S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_INT);
392 }
393
394 rbuffer = &tmp->resource;
395 bo[0] = rbuffer->bo;
396 bo[1] = rbuffer->bo;
397
398 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
399 array_mode = tmp->array_mode[0];
400 tile_type = tmp->tile_type;
401
402 /* FIXME properly handle first level != 0 */
403 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
404 S_030000_DIM(r600_tex_dim(texture->target)) |
405 S_030000_PITCH((pitch / 8) - 1) |
406 S_030000_NON_DISP_TILING_ORDER(tile_type) |
407 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
408 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
409 S_030004_TEX_HEIGHT(texture->height0 - 1) |
410 S_030004_TEX_DEPTH(texture->depth0 - 1) |
411 S_030004_ARRAY_MODE(array_mode),
412 0xFFFFFFFF, NULL);
413 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
414 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
415 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
416 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
417 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
418 word4 |
419 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_NO_ZERO) |
420 S_030010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
421 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
422 S_030014_LAST_LEVEL(state->u.tex.last_level) |
423 S_030014_BASE_ARRAY(0) |
424 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
425 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
426 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
427 S_03001C_DATA_FORMAT(format) |
428 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
429
430 return &resource->base;
431 }
432
433 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
434 struct pipe_sampler_view **views)
435 {
436 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
437 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
438
439 for (int i = 0; i < count; i++) {
440 if (resource[i]) {
441 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
442 i + R600_MAX_CONST_BUFFERS);
443 }
444 }
445 }
446
447 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
448 struct pipe_sampler_view **views)
449 {
450 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
451 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
452 int i;
453
454 for (i = 0; i < count; i++) {
455 if (&rctx->ps_samplers.views[i]->base != views[i]) {
456 if (resource[i])
457 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
458 i + R600_MAX_CONST_BUFFERS);
459 else
460 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
461 i + R600_MAX_CONST_BUFFERS);
462
463 pipe_sampler_view_reference(
464 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
465 views[i]);
466 }
467 }
468 for (i = count; i < NUM_TEX_UNITS; i++) {
469 if (rctx->ps_samplers.views[i]) {
470 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
471 i + R600_MAX_CONST_BUFFERS);
472 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
473 }
474 }
475 rctx->ps_samplers.n_views = count;
476 }
477
478 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
479 {
480 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
481 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
482
483
484 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
485 rctx->ps_samplers.n_samplers = count;
486
487 for (int i = 0; i < count; i++) {
488 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
489 }
490 }
491
492 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
493 {
494 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
495 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
496
497 for (int i = 0; i < count; i++) {
498 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
499 }
500 }
501
502 static void evergreen_set_clip_state(struct pipe_context *ctx,
503 const struct pipe_clip_state *state)
504 {
505 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
506 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
507
508 if (rstate == NULL)
509 return;
510
511 rctx->clip = *state;
512 rstate->id = R600_PIPE_STATE_CLIP;
513 for (int i = 0; i < state->nr; i++) {
514 r600_pipe_state_add_reg(rstate,
515 R_0285BC_PA_CL_UCP0_X + i * 16,
516 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
517 r600_pipe_state_add_reg(rstate,
518 R_0285C0_PA_CL_UCP0_Y + i * 16,
519 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
520 r600_pipe_state_add_reg(rstate,
521 R_0285C4_PA_CL_UCP0_Z + i * 16,
522 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
523 r600_pipe_state_add_reg(rstate,
524 R_0285C8_PA_CL_UCP0_W + i * 16,
525 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
526 }
527 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
528 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
529 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
530 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
531
532 free(rctx->states[R600_PIPE_STATE_CLIP]);
533 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
534 r600_context_pipe_state_set(&rctx->ctx, rstate);
535 }
536
537 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
538 const struct pipe_poly_stipple *state)
539 {
540 }
541
542 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
543 {
544 }
545
546 static void evergreen_set_scissor_state(struct pipe_context *ctx,
547 const struct pipe_scissor_state *state)
548 {
549 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
550 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
551 u32 tl, br;
552
553 if (rstate == NULL)
554 return;
555
556 rstate->id = R600_PIPE_STATE_SCISSOR;
557 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
558 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
559 r600_pipe_state_add_reg(rstate,
560 R_028210_PA_SC_CLIPRECT_0_TL, tl,
561 0xFFFFFFFF, NULL);
562 r600_pipe_state_add_reg(rstate,
563 R_028214_PA_SC_CLIPRECT_0_BR, br,
564 0xFFFFFFFF, NULL);
565 r600_pipe_state_add_reg(rstate,
566 R_028218_PA_SC_CLIPRECT_1_TL, tl,
567 0xFFFFFFFF, NULL);
568 r600_pipe_state_add_reg(rstate,
569 R_02821C_PA_SC_CLIPRECT_1_BR, br,
570 0xFFFFFFFF, NULL);
571 r600_pipe_state_add_reg(rstate,
572 R_028220_PA_SC_CLIPRECT_2_TL, tl,
573 0xFFFFFFFF, NULL);
574 r600_pipe_state_add_reg(rstate,
575 R_028224_PA_SC_CLIPRECT_2_BR, br,
576 0xFFFFFFFF, NULL);
577 r600_pipe_state_add_reg(rstate,
578 R_028228_PA_SC_CLIPRECT_3_TL, tl,
579 0xFFFFFFFF, NULL);
580 r600_pipe_state_add_reg(rstate,
581 R_02822C_PA_SC_CLIPRECT_3_BR, br,
582 0xFFFFFFFF, NULL);
583
584 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
585 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
586 r600_context_pipe_state_set(&rctx->ctx, rstate);
587 }
588
589 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
590 const struct pipe_stencil_ref *state)
591 {
592 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
593 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
594 u32 tmp;
595
596 if (rstate == NULL)
597 return;
598
599 rctx->stencil_ref = *state;
600 rstate->id = R600_PIPE_STATE_STENCIL_REF;
601 tmp = S_028430_STENCILREF(state->ref_value[0]);
602 r600_pipe_state_add_reg(rstate,
603 R_028430_DB_STENCILREFMASK, tmp,
604 ~C_028430_STENCILREF, NULL);
605 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
606 r600_pipe_state_add_reg(rstate,
607 R_028434_DB_STENCILREFMASK_BF, tmp,
608 ~C_028434_STENCILREF_BF, NULL);
609
610 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
611 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
612 r600_context_pipe_state_set(&rctx->ctx, rstate);
613 }
614
615 static void evergreen_set_viewport_state(struct pipe_context *ctx,
616 const struct pipe_viewport_state *state)
617 {
618 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
619 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
620
621 if (rstate == NULL)
622 return;
623
624 rctx->viewport = *state;
625 rstate->id = R600_PIPE_STATE_VIEWPORT;
626 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
627 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
628 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
629 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
630 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
631 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
632 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
633 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
634 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
635
636 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
637 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
638 r600_context_pipe_state_set(&rctx->ctx, rstate);
639 }
640
641 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
642 const struct pipe_framebuffer_state *state, int cb)
643 {
644 struct r600_resource_texture *rtex;
645 struct r600_resource *rbuffer;
646 struct r600_surface *surf;
647 unsigned level = state->cbufs[cb]->u.tex.level;
648 unsigned pitch, slice;
649 unsigned color_info;
650 unsigned format, swap, ntype;
651 unsigned offset;
652 unsigned tile_type;
653 const struct util_format_description *desc;
654 struct r600_bo *bo[3];
655 int i;
656
657 surf = (struct r600_surface *)state->cbufs[cb];
658 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
659
660 if (rtex->depth && !rtex->is_flushing_texture) {
661 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
662 rtex = rtex->flushed_depth_texture;
663 }
664
665 rbuffer = &rtex->resource;
666 bo[0] = rbuffer->bo;
667 bo[1] = rbuffer->bo;
668 bo[2] = rbuffer->bo;
669
670 /* XXX quite sure for dx10+ hw don't need any offset hacks */
671 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
672 level, state->cbufs[cb]->u.tex.first_layer);
673 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
674 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
675 ntype = 0;
676 desc = util_format_description(surf->base.format);
677 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
678 ntype = V_028C70_NUMBER_SRGB;
679
680 format = r600_translate_colorformat(surf->base.format);
681 swap = r600_translate_colorswap(surf->base.format);
682
683 /* disable when gallium grows int textures */
684 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
685 ntype = 4;
686
687 color_info = S_028C70_FORMAT(format) |
688 S_028C70_COMP_SWAP(swap) |
689 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
690 S_028C70_BLEND_CLAMP(1) |
691 S_028C70_NUMBER_TYPE(ntype);
692
693 for (i = 0; i < 4; i++) {
694 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
695 break;
696 }
697 }
698
699 /* we can only set the export size if any thing is snorm/unorm component is > 11 bits,
700 if we aren't a float, sint or uint */
701 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
702 desc->channel[i].size < 12 && desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
703 ntype != 4 && ntype != 5)
704 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
705
706 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
707 tile_type = rtex->tile_type;
708 } else /* workaround for linear buffers */
709 tile_type = 1;
710
711 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
712 r600_pipe_state_add_reg(rstate,
713 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
714 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
715 r600_pipe_state_add_reg(rstate,
716 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
717 0x0, 0xFFFFFFFF, NULL);
718 r600_pipe_state_add_reg(rstate,
719 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
720 color_info, 0xFFFFFFFF, bo[0]);
721 r600_pipe_state_add_reg(rstate,
722 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
723 S_028C64_PITCH_TILE_MAX(pitch),
724 0xFFFFFFFF, NULL);
725 r600_pipe_state_add_reg(rstate,
726 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
727 S_028C68_SLICE_TILE_MAX(slice),
728 0xFFFFFFFF, NULL);
729 r600_pipe_state_add_reg(rstate,
730 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
731 0x00000000, 0xFFFFFFFF, NULL);
732 r600_pipe_state_add_reg(rstate,
733 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
734 S_028C74_NON_DISP_TILING_ORDER(tile_type),
735 0xFFFFFFFF, bo[0]);
736 }
737
738 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
739 const struct pipe_framebuffer_state *state)
740 {
741 struct r600_resource_texture *rtex;
742 struct r600_resource *rbuffer;
743 struct r600_surface *surf;
744 unsigned level;
745 unsigned pitch, slice, format, stencil_format;
746 unsigned offset;
747
748 if (state->zsbuf == NULL)
749 return;
750
751 level = state->zsbuf->u.tex.level;
752
753 surf = (struct r600_surface *)state->zsbuf;
754 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
755
756 rbuffer = &rtex->resource;
757
758 /* XXX quite sure for dx10+ hw don't need any offset hacks */
759 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
760 level, state->zsbuf->u.tex.first_layer);
761 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
762 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
763 format = r600_translate_dbformat(state->zsbuf->texture->format);
764 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
765
766 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
767 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
768 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
769 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
770
771 if (stencil_format) {
772 uint32_t stencil_offset;
773
774 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
775 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
776 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
777 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
778 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
779 }
780
781 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
782 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
783 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
784
785 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
786 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
787 0xFFFFFFFF, rbuffer->bo);
788 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
789 S_028058_PITCH_TILE_MAX(pitch),
790 0xFFFFFFFF, NULL);
791 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
792 S_02805C_SLICE_TILE_MAX(slice),
793 0xFFFFFFFF, NULL);
794 }
795
796 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
797 const struct pipe_framebuffer_state *state)
798 {
799 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
800 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
801 u32 shader_mask, tl, br, target_mask;
802
803 if (rstate == NULL)
804 return;
805
806 /* unreference old buffer and reference new one */
807 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
808
809 util_copy_framebuffer_state(&rctx->framebuffer, state);
810
811 /* build states */
812 for (int i = 0; i < state->nr_cbufs; i++) {
813 evergreen_cb(rctx, rstate, state, i);
814 }
815 if (state->zsbuf) {
816 evergreen_db(rctx, rstate, state);
817 }
818
819 target_mask = 0x00000000;
820 target_mask = 0xFFFFFFFF;
821 shader_mask = 0;
822 for (int i = 0; i < state->nr_cbufs; i++) {
823 target_mask ^= 0xf << (i * 4);
824 shader_mask |= 0xf << (i * 4);
825 }
826 tl = S_028240_TL_X(0) | S_028240_TL_Y(0);
827 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
828
829 r600_pipe_state_add_reg(rstate,
830 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
831 0xFFFFFFFF, NULL);
832 r600_pipe_state_add_reg(rstate,
833 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
834 0xFFFFFFFF, NULL);
835 r600_pipe_state_add_reg(rstate,
836 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
837 0xFFFFFFFF, NULL);
838 r600_pipe_state_add_reg(rstate,
839 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
840 0xFFFFFFFF, NULL);
841 r600_pipe_state_add_reg(rstate,
842 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
843 0xFFFFFFFF, NULL);
844 r600_pipe_state_add_reg(rstate,
845 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
846 0xFFFFFFFF, NULL);
847 r600_pipe_state_add_reg(rstate,
848 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
849 0xFFFFFFFF, NULL);
850 r600_pipe_state_add_reg(rstate,
851 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
852 0xFFFFFFFF, NULL);
853 r600_pipe_state_add_reg(rstate,
854 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
855 0xFFFFFFFF, NULL);
856 r600_pipe_state_add_reg(rstate,
857 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
858 0xFFFFFFFF, NULL);
859
860 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
861 0x00000000, target_mask, NULL);
862 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
863 shader_mask, 0xFFFFFFFF, NULL);
864 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
865 0x00000000, 0xFFFFFFFF, NULL);
866 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
867 0x00000000, 0xFFFFFFFF, NULL);
868
869 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
870 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
871 r600_context_pipe_state_set(&rctx->ctx, rstate);
872
873 if (state->zsbuf) {
874 evergreen_polygon_offset_update(rctx);
875 }
876 }
877
878 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
879 {
880 rctx->context.create_blend_state = evergreen_create_blend_state;
881 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
882 rctx->context.create_fs_state = r600_create_shader_state;
883 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
884 rctx->context.create_sampler_state = evergreen_create_sampler_state;
885 rctx->context.create_sampler_view = evergreen_create_sampler_view;
886 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
887 rctx->context.create_vs_state = r600_create_shader_state;
888 rctx->context.bind_blend_state = r600_bind_blend_state;
889 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
890 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
891 rctx->context.bind_fs_state = r600_bind_ps_shader;
892 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
893 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
894 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
895 rctx->context.bind_vs_state = r600_bind_vs_shader;
896 rctx->context.delete_blend_state = r600_delete_state;
897 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
898 rctx->context.delete_fs_state = r600_delete_ps_shader;
899 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
900 rctx->context.delete_sampler_state = r600_delete_state;
901 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
902 rctx->context.delete_vs_state = r600_delete_vs_shader;
903 rctx->context.set_blend_color = evergreen_set_blend_color;
904 rctx->context.set_clip_state = evergreen_set_clip_state;
905 rctx->context.set_constant_buffer = r600_set_constant_buffer;
906 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
907 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
908 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
909 rctx->context.set_sample_mask = evergreen_set_sample_mask;
910 rctx->context.set_scissor_state = evergreen_set_scissor_state;
911 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
912 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
913 rctx->context.set_index_buffer = r600_set_index_buffer;
914 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
915 rctx->context.set_viewport_state = evergreen_set_viewport_state;
916 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
917 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
918 }
919
920 void evergreen_init_config(struct r600_pipe_context *rctx)
921 {
922 struct r600_pipe_state *rstate = &rctx->config;
923 int ps_prio;
924 int vs_prio;
925 int gs_prio;
926 int es_prio;
927 int hs_prio, cs_prio, ls_prio;
928 int num_ps_gprs;
929 int num_vs_gprs;
930 int num_gs_gprs;
931 int num_es_gprs;
932 int num_hs_gprs;
933 int num_ls_gprs;
934 int num_temp_gprs;
935 int num_ps_threads;
936 int num_vs_threads;
937 int num_gs_threads;
938 int num_es_threads;
939 int num_hs_threads;
940 int num_ls_threads;
941 int num_ps_stack_entries;
942 int num_vs_stack_entries;
943 int num_gs_stack_entries;
944 int num_es_stack_entries;
945 int num_hs_stack_entries;
946 int num_ls_stack_entries;
947 enum radeon_family family;
948 unsigned tmp;
949
950 family = r600_get_family(rctx->radeon);
951 ps_prio = 0;
952 vs_prio = 1;
953 gs_prio = 2;
954 es_prio = 3;
955 hs_prio = 0;
956 ls_prio = 0;
957 cs_prio = 0;
958
959 switch (family) {
960 case CHIP_CEDAR:
961 default:
962 num_ps_gprs = 93;
963 num_vs_gprs = 46;
964 num_temp_gprs = 4;
965 num_gs_gprs = 31;
966 num_es_gprs = 31;
967 num_hs_gprs = 23;
968 num_ls_gprs = 23;
969 num_ps_threads = 96;
970 num_vs_threads = 16;
971 num_gs_threads = 16;
972 num_es_threads = 16;
973 num_hs_threads = 16;
974 num_ls_threads = 16;
975 num_ps_stack_entries = 42;
976 num_vs_stack_entries = 42;
977 num_gs_stack_entries = 42;
978 num_es_stack_entries = 42;
979 num_hs_stack_entries = 42;
980 num_ls_stack_entries = 42;
981 break;
982 case CHIP_REDWOOD:
983 num_ps_gprs = 93;
984 num_vs_gprs = 46;
985 num_temp_gprs = 4;
986 num_gs_gprs = 31;
987 num_es_gprs = 31;
988 num_hs_gprs = 23;
989 num_ls_gprs = 23;
990 num_ps_threads = 128;
991 num_vs_threads = 20;
992 num_gs_threads = 20;
993 num_es_threads = 20;
994 num_hs_threads = 20;
995 num_ls_threads = 20;
996 num_ps_stack_entries = 42;
997 num_vs_stack_entries = 42;
998 num_gs_stack_entries = 42;
999 num_es_stack_entries = 42;
1000 num_hs_stack_entries = 42;
1001 num_ls_stack_entries = 42;
1002 break;
1003 case CHIP_JUNIPER:
1004 num_ps_gprs = 93;
1005 num_vs_gprs = 46;
1006 num_temp_gprs = 4;
1007 num_gs_gprs = 31;
1008 num_es_gprs = 31;
1009 num_hs_gprs = 23;
1010 num_ls_gprs = 23;
1011 num_ps_threads = 128;
1012 num_vs_threads = 20;
1013 num_gs_threads = 20;
1014 num_es_threads = 20;
1015 num_hs_threads = 20;
1016 num_ls_threads = 20;
1017 num_ps_stack_entries = 85;
1018 num_vs_stack_entries = 85;
1019 num_gs_stack_entries = 85;
1020 num_es_stack_entries = 85;
1021 num_hs_stack_entries = 85;
1022 num_ls_stack_entries = 85;
1023 break;
1024 case CHIP_CYPRESS:
1025 case CHIP_HEMLOCK:
1026 num_ps_gprs = 93;
1027 num_vs_gprs = 46;
1028 num_temp_gprs = 4;
1029 num_gs_gprs = 31;
1030 num_es_gprs = 31;
1031 num_hs_gprs = 23;
1032 num_ls_gprs = 23;
1033 num_ps_threads = 128;
1034 num_vs_threads = 20;
1035 num_gs_threads = 20;
1036 num_es_threads = 20;
1037 num_hs_threads = 20;
1038 num_ls_threads = 20;
1039 num_ps_stack_entries = 85;
1040 num_vs_stack_entries = 85;
1041 num_gs_stack_entries = 85;
1042 num_es_stack_entries = 85;
1043 num_hs_stack_entries = 85;
1044 num_ls_stack_entries = 85;
1045 break;
1046 case CHIP_PALM:
1047 num_ps_gprs = 93;
1048 num_vs_gprs = 46;
1049 num_temp_gprs = 4;
1050 num_gs_gprs = 31;
1051 num_es_gprs = 31;
1052 num_hs_gprs = 23;
1053 num_ls_gprs = 23;
1054 num_ps_threads = 96;
1055 num_vs_threads = 16;
1056 num_gs_threads = 16;
1057 num_es_threads = 16;
1058 num_hs_threads = 16;
1059 num_ls_threads = 16;
1060 num_ps_stack_entries = 42;
1061 num_vs_stack_entries = 42;
1062 num_gs_stack_entries = 42;
1063 num_es_stack_entries = 42;
1064 num_hs_stack_entries = 42;
1065 num_ls_stack_entries = 42;
1066 break;
1067 case CHIP_BARTS:
1068 num_ps_gprs = 93;
1069 num_vs_gprs = 46;
1070 num_temp_gprs = 4;
1071 num_gs_gprs = 31;
1072 num_es_gprs = 31;
1073 num_hs_gprs = 23;
1074 num_ls_gprs = 23;
1075 num_ps_threads = 128;
1076 num_vs_threads = 20;
1077 num_gs_threads = 20;
1078 num_es_threads = 20;
1079 num_hs_threads = 20;
1080 num_ls_threads = 20;
1081 num_ps_stack_entries = 85;
1082 num_vs_stack_entries = 85;
1083 num_gs_stack_entries = 85;
1084 num_es_stack_entries = 85;
1085 num_hs_stack_entries = 85;
1086 num_ls_stack_entries = 85;
1087 break;
1088 case CHIP_TURKS:
1089 num_ps_gprs = 93;
1090 num_vs_gprs = 46;
1091 num_temp_gprs = 4;
1092 num_gs_gprs = 31;
1093 num_es_gprs = 31;
1094 num_hs_gprs = 23;
1095 num_ls_gprs = 23;
1096 num_ps_threads = 128;
1097 num_vs_threads = 20;
1098 num_gs_threads = 20;
1099 num_es_threads = 20;
1100 num_hs_threads = 20;
1101 num_ls_threads = 20;
1102 num_ps_stack_entries = 42;
1103 num_vs_stack_entries = 42;
1104 num_gs_stack_entries = 42;
1105 num_es_stack_entries = 42;
1106 num_hs_stack_entries = 42;
1107 num_ls_stack_entries = 42;
1108 break;
1109 case CHIP_CAICOS:
1110 num_ps_gprs = 93;
1111 num_vs_gprs = 46;
1112 num_temp_gprs = 4;
1113 num_gs_gprs = 31;
1114 num_es_gprs = 31;
1115 num_hs_gprs = 23;
1116 num_ls_gprs = 23;
1117 num_ps_threads = 128;
1118 num_vs_threads = 10;
1119 num_gs_threads = 10;
1120 num_es_threads = 10;
1121 num_hs_threads = 10;
1122 num_ls_threads = 10;
1123 num_ps_stack_entries = 42;
1124 num_vs_stack_entries = 42;
1125 num_gs_stack_entries = 42;
1126 num_es_stack_entries = 42;
1127 num_hs_stack_entries = 42;
1128 num_ls_stack_entries = 42;
1129 break;
1130 }
1131
1132 tmp = 0x00000000;
1133 switch (family) {
1134 case CHIP_CEDAR:
1135 case CHIP_PALM:
1136 case CHIP_CAICOS:
1137 break;
1138 default:
1139 tmp |= S_008C00_VC_ENABLE(1);
1140 break;
1141 }
1142 tmp |= S_008C00_EXPORT_SRC_C(1);
1143 tmp |= S_008C00_CS_PRIO(cs_prio);
1144 tmp |= S_008C00_LS_PRIO(ls_prio);
1145 tmp |= S_008C00_HS_PRIO(hs_prio);
1146 tmp |= S_008C00_PS_PRIO(ps_prio);
1147 tmp |= S_008C00_VS_PRIO(vs_prio);
1148 tmp |= S_008C00_GS_PRIO(gs_prio);
1149 tmp |= S_008C00_ES_PRIO(es_prio);
1150 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1151
1152 tmp = 0;
1153 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1154 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1155 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1156 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1157
1158 tmp = 0;
1159 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1160 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1161 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1162
1163 tmp = 0;
1164 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1165 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1166 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1167
1168 tmp = 0;
1169 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1170 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1171 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1172 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1173 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1174
1175 tmp = 0;
1176 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1177 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1178 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1179
1180 tmp = 0;
1181 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1182 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1183 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1184
1185 tmp = 0;
1186 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1187 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1188 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1189
1190 tmp = 0;
1191 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1192 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1193 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1194
1195 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1196 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1197
1198 // r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1199
1200 // r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1201 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1202 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1203
1204 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1205 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1206 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1207 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1208 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1209 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1210
1211 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1212 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1213 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1214 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1215
1216 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1217 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1218 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1219 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1220 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1221 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1222 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1223 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1224 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1225 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1226 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1227 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1228 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1229 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1230 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1231 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1232 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1233 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1234
1235 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1236 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1237 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1238 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1239 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1240 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1241 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1242 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1243 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1244 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1245 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1246 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1247 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1248 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1249 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1250 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1251 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1252 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1253 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1254 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1255 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1256 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1257 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1258 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1259 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1260 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1261 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1262 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1263 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1264 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1265 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1266 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1267
1268 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
1269
1270 r600_context_pipe_state_set(&rctx->ctx, rstate);
1271 }
1272
1273 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
1274 {
1275 struct r600_pipe_state state;
1276
1277 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
1278 state.nregs = 0;
1279 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1280 float offset_units = rctx->rasterizer->offset_units;
1281 unsigned offset_db_fmt_cntl = 0, depth;
1282
1283 switch (rctx->framebuffer.zsbuf->texture->format) {
1284 case PIPE_FORMAT_Z24X8_UNORM:
1285 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1286 depth = -24;
1287 offset_units *= 2.0f;
1288 break;
1289 case PIPE_FORMAT_Z32_FLOAT:
1290 depth = -23;
1291 offset_units *= 1.0f;
1292 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1293 break;
1294 case PIPE_FORMAT_Z16_UNORM:
1295 depth = -16;
1296 offset_units *= 4.0f;
1297 break;
1298 default:
1299 return;
1300 }
1301 /* FIXME some of those reg can be computed with cso */
1302 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1303 r600_pipe_state_add_reg(&state,
1304 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1305 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1306 r600_pipe_state_add_reg(&state,
1307 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1308 fui(offset_units), 0xFFFFFFFF, NULL);
1309 r600_pipe_state_add_reg(&state,
1310 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1311 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1312 r600_pipe_state_add_reg(&state,
1313 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1314 fui(offset_units), 0xFFFFFFFF, NULL);
1315 r600_pipe_state_add_reg(&state,
1316 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1317 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1318 r600_context_pipe_state_set(&rctx->ctx, &state);
1319 }
1320 }
1321
1322 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1323 {
1324 struct r600_pipe_state *rstate = &shader->rstate;
1325 struct r600_shader *rshader = &shader->shader;
1326 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
1327 int pos_index = -1, face_index = -1;
1328 int ninterp = 0;
1329 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1330 unsigned spi_baryc_cntl;
1331
1332 rstate->nregs = 0;
1333
1334 for (i = 0; i < rshader->ninput; i++) {
1335 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1336 POSITION goes via GPRs from the SC so isn't counted */
1337 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1338 pos_index = i;
1339 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1340 face_index = i;
1341 else {
1342 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
1343 rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1344 ninterp++;
1345 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1346 have_linear = TRUE;
1347 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1348 have_perspective = TRUE;
1349 if (rshader->input[i].centroid)
1350 have_centroid = TRUE;
1351 }
1352 }
1353 for (i = 0; i < rshader->noutput; i++) {
1354 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1355 r600_pipe_state_add_reg(rstate,
1356 R_02880C_DB_SHADER_CONTROL,
1357 S_02880C_Z_EXPORT_ENABLE(1),
1358 S_02880C_Z_EXPORT_ENABLE(1), NULL);
1359 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1360 r600_pipe_state_add_reg(rstate,
1361 R_02880C_DB_SHADER_CONTROL,
1362 S_02880C_STENCIL_EXPORT_ENABLE(1),
1363 S_02880C_STENCIL_EXPORT_ENABLE(1), NULL);
1364 }
1365
1366 exports_ps = 0;
1367 num_cout = 0;
1368 for (i = 0; i < rshader->noutput; i++) {
1369 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1370 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1371 exports_ps |= 1;
1372 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1373 num_cout++;
1374 }
1375 }
1376 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1377 if (!exports_ps) {
1378 /* always at least export 1 component per pixel */
1379 exports_ps = 2;
1380 }
1381
1382 if (ninterp == 0) {
1383 ninterp = 1;
1384 have_perspective = TRUE;
1385 }
1386
1387 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
1388 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
1389 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
1390 spi_input_z = 0;
1391 if (pos_index != -1) {
1392 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
1393 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1394 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
1395 spi_input_z |= 1;
1396 }
1397
1398 spi_ps_in_control_1 = 0;
1399 if (face_index != -1) {
1400 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1401 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1402 }
1403
1404 spi_baryc_cntl = 0;
1405 if (have_perspective)
1406 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
1407 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
1408 if (have_linear)
1409 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
1410 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
1411
1412 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1413 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1414 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1415 spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1416 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
1417 0, 0xFFFFFFFF, NULL);
1418 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1419 r600_pipe_state_add_reg(rstate,
1420 R_0286E0_SPI_BARYC_CNTL,
1421 spi_baryc_cntl,
1422 0xFFFFFFFF, NULL);
1423
1424 r600_pipe_state_add_reg(rstate,
1425 R_028840_SQ_PGM_START_PS,
1426 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1427 r600_pipe_state_add_reg(rstate,
1428 R_028844_SQ_PGM_RESOURCES_PS,
1429 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1430 S_028844_PRIME_CACHE_ON_DRAW(1) |
1431 S_028844_STACK_SIZE(rshader->bc.nstack),
1432 0xFFFFFFFF, NULL);
1433 r600_pipe_state_add_reg(rstate,
1434 R_028848_SQ_PGM_RESOURCES_2_PS,
1435 0x0, 0xFFFFFFFF, NULL);
1436 r600_pipe_state_add_reg(rstate,
1437 R_02884C_SQ_PGM_EXPORTS_PS,
1438 exports_ps, 0xFFFFFFFF, NULL);
1439
1440 if (rshader->uses_kill) {
1441 /* only set some bits here, the other bits are set in the dsa state */
1442 r600_pipe_state_add_reg(rstate,
1443 R_02880C_DB_SHADER_CONTROL,
1444 S_02880C_KILL_ENABLE(1),
1445 S_02880C_KILL_ENABLE(1), NULL);
1446 }
1447
1448 r600_pipe_state_add_reg(rstate,
1449 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
1450 0xFFFFFFFF, NULL);
1451 }
1452
1453 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1454 {
1455 struct r600_pipe_state *rstate = &shader->rstate;
1456 struct r600_shader *rshader = &shader->shader;
1457 unsigned spi_vs_out_id[10];
1458 unsigned i, tmp;
1459
1460 /* clear previous register */
1461 rstate->nregs = 0;
1462
1463 /* so far never got proper semantic id from tgsi */
1464 for (i = 0; i < 10; i++) {
1465 spi_vs_out_id[i] = 0;
1466 }
1467 for (i = 0; i < 32; i++) {
1468 tmp = i << ((i & 3) * 8);
1469 spi_vs_out_id[i / 4] |= tmp;
1470 }
1471 for (i = 0; i < 10; i++) {
1472 r600_pipe_state_add_reg(rstate,
1473 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1474 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1475 }
1476
1477 r600_pipe_state_add_reg(rstate,
1478 R_0286C4_SPI_VS_OUT_CONFIG,
1479 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1480 0xFFFFFFFF, NULL);
1481 r600_pipe_state_add_reg(rstate,
1482 R_028860_SQ_PGM_RESOURCES_VS,
1483 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1484 S_028860_STACK_SIZE(rshader->bc.nstack),
1485 0xFFFFFFFF, NULL);
1486 r600_pipe_state_add_reg(rstate,
1487 R_028864_SQ_PGM_RESOURCES_2_VS,
1488 0x0, 0xFFFFFFFF, NULL);
1489 r600_pipe_state_add_reg(rstate,
1490 R_02885C_SQ_PGM_START_VS,
1491 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1492
1493 r600_pipe_state_add_reg(rstate,
1494 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1495 0xFFFFFFFF, NULL);
1496 }
1497
1498 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1499 {
1500 struct pipe_depth_stencil_alpha_state dsa;
1501 struct r600_pipe_state *rstate;
1502
1503 memset(&dsa, 0, sizeof(dsa));
1504
1505 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1506 r600_pipe_state_add_reg(rstate,
1507 R_02880C_DB_SHADER_CONTROL,
1508 0x0,
1509 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1510 r600_pipe_state_add_reg(rstate,
1511 R_028000_DB_RENDER_CONTROL,
1512 S_028000_DEPTH_COPY_ENABLE(1) |
1513 S_028000_STENCIL_COPY_ENABLE(1) |
1514 S_028000_COPY_CENTROID(1),
1515 S_028000_DEPTH_COPY_ENABLE(1) |
1516 S_028000_STENCIL_COPY_ENABLE(1) |
1517 S_028000_COPY_CENTROID(1), NULL);
1518 return rstate;
1519 }
1520
1521 void evergreen_pipe_set_buffer_resource(struct r600_pipe_context *rctx,
1522 struct r600_pipe_state *rstate,
1523 struct r600_resource *rbuffer,
1524 unsigned offset, unsigned stride)
1525 {
1526 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
1527 offset, 0xFFFFFFFF, rbuffer->bo);
1528 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
1529 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
1530 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
1531 S_030008_STRIDE(stride),
1532 0xFFFFFFFF, NULL);
1533 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
1534 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1535 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1536 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1537 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W),
1538 0xFFFFFFFF, NULL);
1539 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
1540 0x00000000, 0xFFFFFFFF, NULL);
1541 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
1542 0x00000000, 0xFFFFFFFF, NULL);
1543 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
1544 0x00000000, 0xFFFFFFFF, NULL);
1545 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
1546 0xC0000000, 0xFFFFFFFF, NULL);
1547 }