2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
34 static uint32_t eg_num_banks(uint32_t nbanks
)
50 static unsigned eg_tile_split(unsigned tile_split
)
53 case 64: tile_split
= 0; break;
54 case 128: tile_split
= 1; break;
55 case 256: tile_split
= 2; break;
56 case 512: tile_split
= 3; break;
58 case 1024: tile_split
= 4; break;
59 case 2048: tile_split
= 5; break;
60 case 4096: tile_split
= 6; break;
65 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect
)
67 switch (macro_tile_aspect
) {
69 case 1: macro_tile_aspect
= 0; break;
70 case 2: macro_tile_aspect
= 1; break;
71 case 4: macro_tile_aspect
= 2; break;
72 case 8: macro_tile_aspect
= 3; break;
74 return macro_tile_aspect
;
77 static unsigned eg_bank_wh(unsigned bankwh
)
81 case 1: bankwh
= 0; break;
82 case 2: bankwh
= 1; break;
83 case 4: bankwh
= 2; break;
84 case 8: bankwh
= 3; break;
89 static uint32_t r600_translate_blend_function(int blend_func
)
93 return V_028780_COMB_DST_PLUS_SRC
;
94 case PIPE_BLEND_SUBTRACT
:
95 return V_028780_COMB_SRC_MINUS_DST
;
96 case PIPE_BLEND_REVERSE_SUBTRACT
:
97 return V_028780_COMB_DST_MINUS_SRC
;
99 return V_028780_COMB_MIN_DST_SRC
;
101 return V_028780_COMB_MAX_DST_SRC
;
103 R600_ERR("Unknown blend function %d\n", blend_func
);
110 static uint32_t r600_translate_blend_factor(int blend_fact
)
112 switch (blend_fact
) {
113 case PIPE_BLENDFACTOR_ONE
:
114 return V_028780_BLEND_ONE
;
115 case PIPE_BLENDFACTOR_SRC_COLOR
:
116 return V_028780_BLEND_SRC_COLOR
;
117 case PIPE_BLENDFACTOR_SRC_ALPHA
:
118 return V_028780_BLEND_SRC_ALPHA
;
119 case PIPE_BLENDFACTOR_DST_ALPHA
:
120 return V_028780_BLEND_DST_ALPHA
;
121 case PIPE_BLENDFACTOR_DST_COLOR
:
122 return V_028780_BLEND_DST_COLOR
;
123 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
124 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
125 case PIPE_BLENDFACTOR_CONST_COLOR
:
126 return V_028780_BLEND_CONST_COLOR
;
127 case PIPE_BLENDFACTOR_CONST_ALPHA
:
128 return V_028780_BLEND_CONST_ALPHA
;
129 case PIPE_BLENDFACTOR_ZERO
:
130 return V_028780_BLEND_ZERO
;
131 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
132 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
133 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
134 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
135 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
136 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
137 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
138 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
139 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
140 return V_028780_BLEND_ONE_MINUS_CONST_COLOR
;
141 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
142 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA
;
143 case PIPE_BLENDFACTOR_SRC1_COLOR
:
144 return V_028780_BLEND_SRC1_COLOR
;
145 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
146 return V_028780_BLEND_SRC1_ALPHA
;
147 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
148 return V_028780_BLEND_INV_SRC1_COLOR
;
149 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
150 return V_028780_BLEND_INV_SRC1_ALPHA
;
152 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
159 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
163 case PIPE_TEXTURE_1D
:
164 return V_030000_SQ_TEX_DIM_1D
;
165 case PIPE_TEXTURE_1D_ARRAY
:
166 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
167 case PIPE_TEXTURE_2D
:
168 case PIPE_TEXTURE_RECT
:
169 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_MSAA
:
170 V_030000_SQ_TEX_DIM_2D
;
171 case PIPE_TEXTURE_2D_ARRAY
:
172 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
173 V_030000_SQ_TEX_DIM_2D_ARRAY
;
174 case PIPE_TEXTURE_3D
:
175 return V_030000_SQ_TEX_DIM_3D
;
176 case PIPE_TEXTURE_CUBE
:
177 case PIPE_TEXTURE_CUBE_ARRAY
:
178 return V_030000_SQ_TEX_DIM_CUBEMAP
;
182 static uint32_t r600_translate_dbformat(enum pipe_format format
)
185 case PIPE_FORMAT_Z16_UNORM
:
186 return V_028040_Z_16
;
187 case PIPE_FORMAT_Z24X8_UNORM
:
188 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
189 return V_028040_Z_24
;
190 case PIPE_FORMAT_Z32_FLOAT
:
191 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
192 return V_028040_Z_32_FLOAT
;
198 static uint32_t r600_translate_colorswap(enum pipe_format format
)
202 case PIPE_FORMAT_L4A4_UNORM
:
203 case PIPE_FORMAT_A4R4_UNORM
:
204 return V_028C70_SWAP_ALT
;
206 case PIPE_FORMAT_A8_UNORM
:
207 case PIPE_FORMAT_A8_SNORM
:
208 case PIPE_FORMAT_A8_UINT
:
209 case PIPE_FORMAT_A8_SINT
:
210 case PIPE_FORMAT_A16_UNORM
:
211 case PIPE_FORMAT_A16_SNORM
:
212 case PIPE_FORMAT_A16_UINT
:
213 case PIPE_FORMAT_A16_SINT
:
214 case PIPE_FORMAT_A16_FLOAT
:
215 case PIPE_FORMAT_A32_UINT
:
216 case PIPE_FORMAT_A32_SINT
:
217 case PIPE_FORMAT_A32_FLOAT
:
218 case PIPE_FORMAT_R4A4_UNORM
:
219 return V_028C70_SWAP_ALT_REV
;
220 case PIPE_FORMAT_I8_UNORM
:
221 case PIPE_FORMAT_I8_SNORM
:
222 case PIPE_FORMAT_I8_UINT
:
223 case PIPE_FORMAT_I8_SINT
:
224 case PIPE_FORMAT_I16_UNORM
:
225 case PIPE_FORMAT_I16_SNORM
:
226 case PIPE_FORMAT_I16_UINT
:
227 case PIPE_FORMAT_I16_SINT
:
228 case PIPE_FORMAT_I16_FLOAT
:
229 case PIPE_FORMAT_I32_UINT
:
230 case PIPE_FORMAT_I32_SINT
:
231 case PIPE_FORMAT_I32_FLOAT
:
232 case PIPE_FORMAT_L8_UNORM
:
233 case PIPE_FORMAT_L8_SNORM
:
234 case PIPE_FORMAT_L8_UINT
:
235 case PIPE_FORMAT_L8_SINT
:
236 case PIPE_FORMAT_L8_SRGB
:
237 case PIPE_FORMAT_L16_UNORM
:
238 case PIPE_FORMAT_L16_SNORM
:
239 case PIPE_FORMAT_L16_UINT
:
240 case PIPE_FORMAT_L16_SINT
:
241 case PIPE_FORMAT_L16_FLOAT
:
242 case PIPE_FORMAT_L32_UINT
:
243 case PIPE_FORMAT_L32_SINT
:
244 case PIPE_FORMAT_L32_FLOAT
:
245 case PIPE_FORMAT_R8_UNORM
:
246 case PIPE_FORMAT_R8_SNORM
:
247 case PIPE_FORMAT_R8_UINT
:
248 case PIPE_FORMAT_R8_SINT
:
249 return V_028C70_SWAP_STD
;
251 /* 16-bit buffers. */
252 case PIPE_FORMAT_B5G6R5_UNORM
:
253 return V_028C70_SWAP_STD_REV
;
255 case PIPE_FORMAT_B5G5R5A1_UNORM
:
256 case PIPE_FORMAT_B5G5R5X1_UNORM
:
257 return V_028C70_SWAP_ALT
;
259 case PIPE_FORMAT_B4G4R4A4_UNORM
:
260 case PIPE_FORMAT_B4G4R4X4_UNORM
:
261 return V_028C70_SWAP_ALT
;
263 case PIPE_FORMAT_Z16_UNORM
:
264 return V_028C70_SWAP_STD
;
266 case PIPE_FORMAT_L8A8_UNORM
:
267 case PIPE_FORMAT_L8A8_SNORM
:
268 case PIPE_FORMAT_L8A8_UINT
:
269 case PIPE_FORMAT_L8A8_SINT
:
270 case PIPE_FORMAT_L8A8_SRGB
:
271 case PIPE_FORMAT_L16A16_UNORM
:
272 case PIPE_FORMAT_L16A16_SNORM
:
273 case PIPE_FORMAT_L16A16_UINT
:
274 case PIPE_FORMAT_L16A16_SINT
:
275 case PIPE_FORMAT_L16A16_FLOAT
:
276 case PIPE_FORMAT_L32A32_UINT
:
277 case PIPE_FORMAT_L32A32_SINT
:
278 case PIPE_FORMAT_L32A32_FLOAT
:
279 return V_028C70_SWAP_ALT
;
280 case PIPE_FORMAT_R8G8_UNORM
:
281 case PIPE_FORMAT_R8G8_SNORM
:
282 case PIPE_FORMAT_R8G8_UINT
:
283 case PIPE_FORMAT_R8G8_SINT
:
284 return V_028C70_SWAP_STD
;
286 case PIPE_FORMAT_R16_UNORM
:
287 case PIPE_FORMAT_R16_SNORM
:
288 case PIPE_FORMAT_R16_UINT
:
289 case PIPE_FORMAT_R16_SINT
:
290 case PIPE_FORMAT_R16_FLOAT
:
291 return V_028C70_SWAP_STD
;
293 /* 32-bit buffers. */
294 case PIPE_FORMAT_A8B8G8R8_SRGB
:
295 return V_028C70_SWAP_STD_REV
;
296 case PIPE_FORMAT_B8G8R8A8_SRGB
:
297 return V_028C70_SWAP_ALT
;
299 case PIPE_FORMAT_B8G8R8A8_UNORM
:
300 case PIPE_FORMAT_B8G8R8X8_UNORM
:
301 return V_028C70_SWAP_ALT
;
303 case PIPE_FORMAT_A8R8G8B8_UNORM
:
304 case PIPE_FORMAT_X8R8G8B8_UNORM
:
305 return V_028C70_SWAP_ALT_REV
;
306 case PIPE_FORMAT_R8G8B8A8_SNORM
:
307 case PIPE_FORMAT_R8G8B8A8_UNORM
:
308 case PIPE_FORMAT_R8G8B8A8_SINT
:
309 case PIPE_FORMAT_R8G8B8A8_UINT
:
310 case PIPE_FORMAT_R8G8B8X8_UNORM
:
311 return V_028C70_SWAP_STD
;
313 case PIPE_FORMAT_A8B8G8R8_UNORM
:
314 case PIPE_FORMAT_X8B8G8R8_UNORM
:
315 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
316 return V_028C70_SWAP_STD_REV
;
318 case PIPE_FORMAT_Z24X8_UNORM
:
319 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
320 return V_028C70_SWAP_STD
;
322 case PIPE_FORMAT_X8Z24_UNORM
:
323 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
324 return V_028C70_SWAP_STD
;
326 case PIPE_FORMAT_R10G10B10A2_UNORM
:
327 case PIPE_FORMAT_R10G10B10X2_SNORM
:
328 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
329 return V_028C70_SWAP_STD
;
331 case PIPE_FORMAT_B10G10R10A2_UNORM
:
332 case PIPE_FORMAT_B10G10R10A2_UINT
:
333 return V_028C70_SWAP_ALT
;
335 case PIPE_FORMAT_R11G11B10_FLOAT
:
336 case PIPE_FORMAT_R32_FLOAT
:
337 case PIPE_FORMAT_R32_UINT
:
338 case PIPE_FORMAT_R32_SINT
:
339 case PIPE_FORMAT_Z32_FLOAT
:
340 case PIPE_FORMAT_R16G16_FLOAT
:
341 case PIPE_FORMAT_R16G16_UNORM
:
342 case PIPE_FORMAT_R16G16_SNORM
:
343 case PIPE_FORMAT_R16G16_UINT
:
344 case PIPE_FORMAT_R16G16_SINT
:
345 return V_028C70_SWAP_STD
;
347 /* 64-bit buffers. */
348 case PIPE_FORMAT_R32G32_FLOAT
:
349 case PIPE_FORMAT_R32G32_UINT
:
350 case PIPE_FORMAT_R32G32_SINT
:
351 case PIPE_FORMAT_R16G16B16A16_UNORM
:
352 case PIPE_FORMAT_R16G16B16A16_SNORM
:
353 case PIPE_FORMAT_R16G16B16A16_UINT
:
354 case PIPE_FORMAT_R16G16B16A16_SINT
:
355 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
356 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
358 /* 128-bit buffers. */
359 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
360 case PIPE_FORMAT_R32G32B32A32_SNORM
:
361 case PIPE_FORMAT_R32G32B32A32_UNORM
:
362 case PIPE_FORMAT_R32G32B32A32_SINT
:
363 case PIPE_FORMAT_R32G32B32A32_UINT
:
364 return V_028C70_SWAP_STD
;
366 R600_ERR("unsupported colorswap format %d\n", format
);
372 static uint32_t r600_translate_colorformat(enum pipe_format format
)
376 case PIPE_FORMAT_A8_UNORM
:
377 case PIPE_FORMAT_A8_SNORM
:
378 case PIPE_FORMAT_A8_UINT
:
379 case PIPE_FORMAT_A8_SINT
:
380 case PIPE_FORMAT_I8_UNORM
:
381 case PIPE_FORMAT_I8_SNORM
:
382 case PIPE_FORMAT_I8_UINT
:
383 case PIPE_FORMAT_I8_SINT
:
384 case PIPE_FORMAT_L8_UNORM
:
385 case PIPE_FORMAT_L8_SNORM
:
386 case PIPE_FORMAT_L8_UINT
:
387 case PIPE_FORMAT_L8_SINT
:
388 case PIPE_FORMAT_L8_SRGB
:
389 case PIPE_FORMAT_R8_UNORM
:
390 case PIPE_FORMAT_R8_SNORM
:
391 case PIPE_FORMAT_R8_UINT
:
392 case PIPE_FORMAT_R8_SINT
:
393 return V_028C70_COLOR_8
;
395 /* 16-bit buffers. */
396 case PIPE_FORMAT_B5G6R5_UNORM
:
397 return V_028C70_COLOR_5_6_5
;
399 case PIPE_FORMAT_B5G5R5A1_UNORM
:
400 case PIPE_FORMAT_B5G5R5X1_UNORM
:
401 return V_028C70_COLOR_1_5_5_5
;
403 case PIPE_FORMAT_B4G4R4A4_UNORM
:
404 case PIPE_FORMAT_B4G4R4X4_UNORM
:
405 return V_028C70_COLOR_4_4_4_4
;
407 case PIPE_FORMAT_Z16_UNORM
:
408 return V_028C70_COLOR_16
;
410 case PIPE_FORMAT_L8A8_UNORM
:
411 case PIPE_FORMAT_L8A8_SNORM
:
412 case PIPE_FORMAT_L8A8_UINT
:
413 case PIPE_FORMAT_L8A8_SINT
:
414 case PIPE_FORMAT_L8A8_SRGB
:
415 case PIPE_FORMAT_R8G8_UNORM
:
416 case PIPE_FORMAT_R8G8_SNORM
:
417 case PIPE_FORMAT_R8G8_UINT
:
418 case PIPE_FORMAT_R8G8_SINT
:
419 return V_028C70_COLOR_8_8
;
421 case PIPE_FORMAT_R16_UNORM
:
422 case PIPE_FORMAT_R16_SNORM
:
423 case PIPE_FORMAT_R16_UINT
:
424 case PIPE_FORMAT_R16_SINT
:
425 case PIPE_FORMAT_A16_UNORM
:
426 case PIPE_FORMAT_A16_SNORM
:
427 case PIPE_FORMAT_A16_UINT
:
428 case PIPE_FORMAT_A16_SINT
:
429 case PIPE_FORMAT_L16_UNORM
:
430 case PIPE_FORMAT_L16_SNORM
:
431 case PIPE_FORMAT_L16_UINT
:
432 case PIPE_FORMAT_L16_SINT
:
433 case PIPE_FORMAT_I16_UNORM
:
434 case PIPE_FORMAT_I16_SNORM
:
435 case PIPE_FORMAT_I16_UINT
:
436 case PIPE_FORMAT_I16_SINT
:
437 return V_028C70_COLOR_16
;
439 case PIPE_FORMAT_R16_FLOAT
:
440 case PIPE_FORMAT_A16_FLOAT
:
441 case PIPE_FORMAT_L16_FLOAT
:
442 case PIPE_FORMAT_I16_FLOAT
:
443 return V_028C70_COLOR_16_FLOAT
;
445 /* 32-bit buffers. */
446 case PIPE_FORMAT_A8B8G8R8_SRGB
:
447 case PIPE_FORMAT_A8B8G8R8_UNORM
:
448 case PIPE_FORMAT_A8R8G8B8_UNORM
:
449 case PIPE_FORMAT_B8G8R8A8_SRGB
:
450 case PIPE_FORMAT_B8G8R8A8_UNORM
:
451 case PIPE_FORMAT_B8G8R8X8_UNORM
:
452 case PIPE_FORMAT_R8G8B8A8_SNORM
:
453 case PIPE_FORMAT_R8G8B8A8_UNORM
:
454 case PIPE_FORMAT_R8G8B8X8_UNORM
:
455 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
456 case PIPE_FORMAT_X8B8G8R8_UNORM
:
457 case PIPE_FORMAT_X8R8G8B8_UNORM
:
458 case PIPE_FORMAT_R8G8B8_UNORM
:
459 case PIPE_FORMAT_R8G8B8A8_SINT
:
460 case PIPE_FORMAT_R8G8B8A8_UINT
:
461 return V_028C70_COLOR_8_8_8_8
;
463 case PIPE_FORMAT_R10G10B10A2_UNORM
:
464 case PIPE_FORMAT_R10G10B10X2_SNORM
:
465 case PIPE_FORMAT_B10G10R10A2_UNORM
:
466 case PIPE_FORMAT_B10G10R10A2_UINT
:
467 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
468 return V_028C70_COLOR_2_10_10_10
;
470 case PIPE_FORMAT_Z24X8_UNORM
:
471 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
472 return V_028C70_COLOR_8_24
;
474 case PIPE_FORMAT_X8Z24_UNORM
:
475 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
476 return V_028C70_COLOR_24_8
;
478 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
479 return V_028C70_COLOR_X24_8_32_FLOAT
;
481 case PIPE_FORMAT_R32_UINT
:
482 case PIPE_FORMAT_R32_SINT
:
483 case PIPE_FORMAT_A32_UINT
:
484 case PIPE_FORMAT_A32_SINT
:
485 case PIPE_FORMAT_L32_UINT
:
486 case PIPE_FORMAT_L32_SINT
:
487 case PIPE_FORMAT_I32_UINT
:
488 case PIPE_FORMAT_I32_SINT
:
489 return V_028C70_COLOR_32
;
491 case PIPE_FORMAT_R32_FLOAT
:
492 case PIPE_FORMAT_A32_FLOAT
:
493 case PIPE_FORMAT_L32_FLOAT
:
494 case PIPE_FORMAT_I32_FLOAT
:
495 case PIPE_FORMAT_Z32_FLOAT
:
496 return V_028C70_COLOR_32_FLOAT
;
498 case PIPE_FORMAT_R16G16_FLOAT
:
499 case PIPE_FORMAT_L16A16_FLOAT
:
500 return V_028C70_COLOR_16_16_FLOAT
;
502 case PIPE_FORMAT_R16G16_UNORM
:
503 case PIPE_FORMAT_R16G16_SNORM
:
504 case PIPE_FORMAT_R16G16_UINT
:
505 case PIPE_FORMAT_R16G16_SINT
:
506 case PIPE_FORMAT_L16A16_UNORM
:
507 case PIPE_FORMAT_L16A16_SNORM
:
508 case PIPE_FORMAT_L16A16_UINT
:
509 case PIPE_FORMAT_L16A16_SINT
:
510 return V_028C70_COLOR_16_16
;
512 case PIPE_FORMAT_R11G11B10_FLOAT
:
513 return V_028C70_COLOR_10_11_11_FLOAT
;
515 /* 64-bit buffers. */
516 case PIPE_FORMAT_R16G16B16A16_UINT
:
517 case PIPE_FORMAT_R16G16B16A16_SINT
:
518 case PIPE_FORMAT_R16G16B16A16_UNORM
:
519 case PIPE_FORMAT_R16G16B16A16_SNORM
:
520 return V_028C70_COLOR_16_16_16_16
;
522 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
523 return V_028C70_COLOR_16_16_16_16_FLOAT
;
525 case PIPE_FORMAT_R32G32_FLOAT
:
526 case PIPE_FORMAT_L32A32_FLOAT
:
527 return V_028C70_COLOR_32_32_FLOAT
;
529 case PIPE_FORMAT_R32G32_SINT
:
530 case PIPE_FORMAT_R32G32_UINT
:
531 case PIPE_FORMAT_L32A32_UINT
:
532 case PIPE_FORMAT_L32A32_SINT
:
533 return V_028C70_COLOR_32_32
;
535 /* 128-bit buffers. */
536 case PIPE_FORMAT_R32G32B32A32_SNORM
:
537 case PIPE_FORMAT_R32G32B32A32_UNORM
:
538 case PIPE_FORMAT_R32G32B32A32_SINT
:
539 case PIPE_FORMAT_R32G32B32A32_UINT
:
540 return V_028C70_COLOR_32_32_32_32
;
541 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
542 return V_028C70_COLOR_32_32_32_32_FLOAT
;
545 case PIPE_FORMAT_UYVY
:
546 case PIPE_FORMAT_YUYV
:
548 return ~0U; /* Unsupported. */
552 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
554 if (R600_BIG_ENDIAN
) {
555 switch(colorformat
) {
558 case V_028C70_COLOR_8
:
561 /* 16-bit buffers. */
562 case V_028C70_COLOR_5_6_5
:
563 case V_028C70_COLOR_1_5_5_5
:
564 case V_028C70_COLOR_4_4_4_4
:
565 case V_028C70_COLOR_16
:
566 case V_028C70_COLOR_8_8
:
569 /* 32-bit buffers. */
570 case V_028C70_COLOR_8_8_8_8
:
571 case V_028C70_COLOR_2_10_10_10
:
572 case V_028C70_COLOR_8_24
:
573 case V_028C70_COLOR_24_8
:
574 case V_028C70_COLOR_32_FLOAT
:
575 case V_028C70_COLOR_16_16_FLOAT
:
576 case V_028C70_COLOR_16_16
:
579 /* 64-bit buffers. */
580 case V_028C70_COLOR_16_16_16_16
:
581 case V_028C70_COLOR_16_16_16_16_FLOAT
:
584 case V_028C70_COLOR_32_32_FLOAT
:
585 case V_028C70_COLOR_32_32
:
586 case V_028C70_COLOR_X24_8_32_FLOAT
:
589 /* 96-bit buffers. */
590 case V_028C70_COLOR_32_32_32_FLOAT
:
591 /* 128-bit buffers. */
592 case V_028C70_COLOR_32_32_32_32_FLOAT
:
593 case V_028C70_COLOR_32_32_32_32
:
596 return ENDIAN_NONE
; /* Unsupported. */
603 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
605 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
608 static bool r600_is_colorbuffer_format_supported(enum pipe_format format
)
610 return r600_translate_colorformat(format
) != ~0U &&
611 r600_translate_colorswap(format
) != ~0U;
614 static bool r600_is_zs_format_supported(enum pipe_format format
)
616 return r600_translate_dbformat(format
) != ~0U;
619 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
620 enum pipe_format format
,
621 enum pipe_texture_target target
,
622 unsigned sample_count
,
625 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
628 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
629 R600_ERR("r600: unsupported texture type %d\n", target
);
633 if (!util_format_is_supported(format
, usage
))
636 if (sample_count
> 1) {
637 if (!rscreen
->has_msaa
)
640 switch (sample_count
) {
650 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
651 r600_is_sampler_format_supported(screen
, format
)) {
652 retval
|= PIPE_BIND_SAMPLER_VIEW
;
655 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
656 PIPE_BIND_DISPLAY_TARGET
|
658 PIPE_BIND_SHARED
)) &&
659 r600_is_colorbuffer_format_supported(format
)) {
661 (PIPE_BIND_RENDER_TARGET
|
662 PIPE_BIND_DISPLAY_TARGET
|
667 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
668 r600_is_zs_format_supported(format
)) {
669 retval
|= PIPE_BIND_DEPTH_STENCIL
;
672 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
673 r600_is_vertex_format_supported(format
)) {
674 retval
|= PIPE_BIND_VERTEX_BUFFER
;
677 if (usage
& PIPE_BIND_TRANSFER_READ
)
678 retval
|= PIPE_BIND_TRANSFER_READ
;
679 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
680 retval
|= PIPE_BIND_TRANSFER_WRITE
;
682 return retval
== usage
;
685 static void *evergreen_create_blend_state_mode(struct pipe_context
*ctx
,
686 const struct pipe_blend_state
*state
, int mode
)
688 uint32_t color_control
= 0, target_mask
= 0;
689 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
695 r600_init_command_buffer(&blend
->buffer
, 20);
696 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
698 if (state
->logicop_enable
) {
699 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
701 color_control
|= (0xcc << 16);
703 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
704 if (state
->independent_blend_enable
) {
705 for (int i
= 0; i
< 8; i
++) {
706 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
709 for (int i
= 0; i
< 8; i
++) {
710 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
714 /* only have dual source on MRT0 */
715 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
716 blend
->cb_target_mask
= target_mask
;
717 blend
->alpha_to_one
= state
->alpha_to_one
;
720 color_control
|= S_028808_MODE(mode
);
722 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
725 r600_store_context_reg(&blend
->buffer
, R_028808_CB_COLOR_CONTROL
, color_control
);
726 r600_store_context_reg(&blend
->buffer
, R_028B70_DB_ALPHA_TO_MASK
,
727 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
728 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
729 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
730 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
731 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
732 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
734 /* Copy over the dwords set so far into buffer_no_blend.
735 * Only the CB_BLENDi_CONTROL registers must be set after this. */
736 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
737 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
739 for (int i
= 0; i
< 8; i
++) {
740 /* state->rt entries > 0 only written if independent blending */
741 const int j
= state
->independent_blend_enable
? i
: 0;
743 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
744 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
745 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
746 unsigned eqA
= state
->rt
[j
].alpha_func
;
747 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
748 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
751 r600_store_value(&blend
->buffer_no_blend
, 0);
753 if (!state
->rt
[j
].blend_enable
) {
754 r600_store_value(&blend
->buffer
, 0);
758 bc
|= S_028780_BLEND_CONTROL_ENABLE(1);
759 bc
|= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
760 bc
|= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
761 bc
|= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
763 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
764 bc
|= S_028780_SEPARATE_ALPHA_BLEND(1);
765 bc
|= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
766 bc
|= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
767 bc
|= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
769 r600_store_value(&blend
->buffer
, bc
);
774 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
775 const struct pipe_blend_state
*state
)
778 return evergreen_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
781 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
782 const struct pipe_depth_stencil_alpha_state
*state
)
784 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
785 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
791 r600_init_command_buffer(&dsa
->buffer
, 3);
793 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
794 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
795 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
796 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
798 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
799 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
800 S_028800_ZFUNC(state
->depth
.func
);
803 if (state
->stencil
[0].enabled
) {
804 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
805 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
806 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
807 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
808 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
810 if (state
->stencil
[1].enabled
) {
811 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
812 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
813 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
814 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
815 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
820 alpha_test_control
= 0;
822 if (state
->alpha
.enabled
) {
823 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
824 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
825 alpha_ref
= fui(state
->alpha
.ref_value
);
827 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
828 dsa
->alpha_ref
= alpha_ref
;
831 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
835 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
836 const struct pipe_rasterizer_state
*state
)
838 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
839 unsigned tmp
, spi_interp
;
840 float psize_min
, psize_max
;
841 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
847 r600_init_command_buffer(&rs
->buffer
, 30);
849 rs
->flatshade
= state
->flatshade
;
850 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
851 rs
->two_side
= state
->light_twoside
;
852 rs
->clip_plane_enable
= state
->clip_plane_enable
;
853 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
854 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
855 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
856 rs
->pa_cl_clip_cntl
=
857 S_028810_PS_UCP_MODE(3) |
858 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
859 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
860 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
861 rs
->multisample_enable
= state
->multisample
;
864 rs
->offset_units
= state
->offset_units
;
865 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
866 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
868 if (state
->point_size_per_vertex
) {
869 psize_min
= util_get_min_point_size(state
);
872 /* Force the point size to be as if the vertex output was disabled. */
873 psize_min
= state
->point_size
;
874 psize_max
= state
->point_size
;
877 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
878 if (state
->sprite_coord_enable
) {
879 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
880 S_0286D4_PNT_SPRITE_OVRD_X(2) |
881 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
882 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
883 S_0286D4_PNT_SPRITE_OVRD_W(1);
884 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
885 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
889 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
890 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
891 tmp
= r600_pack_float_12p4(state
->point_size
/2);
892 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
893 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
894 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
895 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
896 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
897 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
898 S_028A08_WIDTH((unsigned)(state
->line_width
* 8)));
900 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
901 r600_store_context_reg(&rs
->buffer
, R_028A48_PA_SC_MODE_CNTL_0
,
902 S_028A48_MSAA_ENABLE(state
->multisample
) |
903 S_028A48_VPORT_SCISSOR_ENABLE(state
->scissor
) |
904 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
));
906 if (rctx
->chip_class
== CAYMAN
) {
907 r600_store_context_reg(&rs
->buffer
, CM_R_028BE4_PA_SU_VTX_CNTL
,
908 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
) |
909 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
911 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
912 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
) |
913 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
916 r600_store_context_reg(&rs
->buffer
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
917 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
,
918 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
919 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
920 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
921 S_028814_FACE(!state
->front_ccw
) |
922 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
923 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
924 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
925 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
926 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
927 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
928 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
929 r600_store_context_reg(&rs
->buffer
, R_028350_SX_MISC
, S_028350_MULTIPASS(state
->rasterizer_discard
));
933 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
934 const struct pipe_sampler_state
*state
)
936 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
937 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
943 ss
->border_color_use
= sampler_state_needs_border_color(state
);
945 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
946 ss
->tex_sampler_words
[0] =
947 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
948 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
949 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
950 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
951 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
952 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
953 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
954 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
955 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
956 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
957 ss
->tex_sampler_words
[1] =
958 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
959 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8));
960 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
961 ss
->tex_sampler_words
[2] =
962 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
963 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
966 if (ss
->border_color_use
) {
967 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
972 static struct pipe_sampler_view
*
973 texture_buffer_sampler_view(struct r600_pipe_sampler_view
*view
,
974 unsigned width0
, unsigned height0
)
977 struct pipe_context
*ctx
= view
->base
.context
;
978 struct r600_texture
*tmp
= (struct r600_texture
*)view
->base
.texture
;
980 int stride
= util_format_get_blocksize(view
->base
.format
);
981 unsigned format
, num_format
, format_comp
, endian
;
982 unsigned swizzle_res
;
983 unsigned char swizzle
[4];
984 const struct util_format_description
*desc
;
986 swizzle
[0] = view
->base
.swizzle_r
;
987 swizzle
[1] = view
->base
.swizzle_g
;
988 swizzle
[2] = view
->base
.swizzle_b
;
989 swizzle
[3] = view
->base
.swizzle_a
;
991 r600_vertex_data_type(view
->base
.format
,
992 &format
, &num_format
, &format_comp
,
995 desc
= util_format_description(view
->base
.format
);
997 swizzle_res
= r600_get_swizzle_combined(desc
->swizzle
, swizzle
, TRUE
);
999 va
= r600_resource_va(ctx
->screen
, view
->base
.texture
);
1000 view
->tex_resource
= &tmp
->resource
;
1002 view
->skip_mip_address_reloc
= true;
1003 view
->tex_resource_words
[0] = va
;
1004 view
->tex_resource_words
[1] = width0
- 1;
1005 view
->tex_resource_words
[2] = S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
1006 S_030008_STRIDE(stride
) |
1007 S_030008_DATA_FORMAT(format
) |
1008 S_030008_NUM_FORMAT_ALL(num_format
) |
1009 S_030008_FORMAT_COMP_ALL(format_comp
) |
1010 S_030008_SRF_MODE_ALL(1) |
1011 S_030008_ENDIAN_SWAP(endian
);
1012 view
->tex_resource_words
[3] = swizzle_res
;
1014 * in theory dword 4 is for number of elements, for use with resinfo,
1015 * but it seems to utterly fail to work, the amd gpu shader analyser
1016 * uses a const buffer to store the element sizes for buffer txq
1018 view
->tex_resource_words
[4] = 0;
1019 view
->tex_resource_words
[5] = view
->tex_resource_words
[6] = 0;
1020 view
->tex_resource_words
[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
);
1024 struct pipe_sampler_view
*
1025 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
1026 struct pipe_resource
*texture
,
1027 const struct pipe_sampler_view
*state
,
1028 unsigned width0
, unsigned height0
)
1030 struct r600_screen
*rscreen
= (struct r600_screen
*)ctx
->screen
;
1031 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
1032 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
1033 unsigned format
, endian
;
1034 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
1035 unsigned char swizzle
[4], array_mode
= 0, non_disp_tiling
= 0;
1036 unsigned height
, depth
, width
;
1037 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1038 enum pipe_format pipe_format
= state
->format
;
1039 struct radeon_surface_level
*surflevel
;
1044 /* initialize base object */
1045 view
->base
= *state
;
1046 view
->base
.texture
= NULL
;
1047 pipe_reference(NULL
, &texture
->reference
);
1048 view
->base
.texture
= texture
;
1049 view
->base
.reference
.count
= 1;
1050 view
->base
.context
= ctx
;
1052 if (texture
->target
== PIPE_BUFFER
)
1053 return texture_buffer_sampler_view(view
, width0
, height0
);
1055 swizzle
[0] = state
->swizzle_r
;
1056 swizzle
[1] = state
->swizzle_g
;
1057 swizzle
[2] = state
->swizzle_b
;
1058 swizzle
[3] = state
->swizzle_a
;
1060 tile_split
= tmp
->surface
.tile_split
;
1061 surflevel
= tmp
->surface
.level
;
1063 /* Texturing with separate depth and stencil. */
1064 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
1065 switch (pipe_format
) {
1066 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1067 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1069 case PIPE_FORMAT_X24S8_UINT
:
1070 case PIPE_FORMAT_S8X24_UINT
:
1071 case PIPE_FORMAT_X32_S8X24_UINT
:
1072 pipe_format
= PIPE_FORMAT_S8_UINT
;
1073 tile_split
= tmp
->surface
.stencil_tile_split
;
1074 surflevel
= tmp
->surface
.stencil_level
;
1080 format
= r600_translate_texformat(ctx
->screen
, pipe_format
,
1082 &word4
, &yuv_format
);
1083 assert(format
!= ~0);
1089 endian
= r600_colorformat_endian_swap(format
);
1093 depth
= texture
->depth0
;
1094 pitch
= surflevel
[0].nblk_x
* util_format_get_blockwidth(pipe_format
);
1095 non_disp_tiling
= tmp
->non_disp_tiling
;
1097 switch (surflevel
[0].mode
) {
1098 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1099 array_mode
= V_028C70_ARRAY_LINEAR_ALIGNED
;
1101 case RADEON_SURF_MODE_2D
:
1102 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1104 case RADEON_SURF_MODE_1D
:
1105 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1107 case RADEON_SURF_MODE_LINEAR
:
1109 array_mode
= V_028C70_ARRAY_LINEAR_GENERAL
;
1112 macro_aspect
= tmp
->surface
.mtilea
;
1113 bankw
= tmp
->surface
.bankw
;
1114 bankh
= tmp
->surface
.bankh
;
1115 tile_split
= eg_tile_split(tile_split
);
1116 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1117 bankw
= eg_bank_wh(bankw
);
1118 bankh
= eg_bank_wh(bankh
);
1120 /* 128 bit formats require tile type = 1 */
1121 if (rscreen
->chip_class
== CAYMAN
) {
1122 if (util_format_get_blocksize(pipe_format
) >= 16)
1123 non_disp_tiling
= 1;
1125 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1127 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
1129 depth
= texture
->array_size
;
1130 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
1131 depth
= texture
->array_size
;
1132 } else if (texture
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
1133 depth
= texture
->array_size
/ 6;
1135 view
->tex_resource
= &tmp
->resource
;
1136 view
->tex_resource_words
[0] = (S_030000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
1137 S_030000_PITCH((pitch
/ 8) - 1) |
1138 S_030000_TEX_WIDTH(width
- 1));
1139 if (rscreen
->chip_class
== CAYMAN
)
1140 view
->tex_resource_words
[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
1142 view
->tex_resource_words
[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
1143 view
->tex_resource_words
[1] = (S_030004_TEX_HEIGHT(height
- 1) |
1144 S_030004_TEX_DEPTH(depth
- 1) |
1145 S_030004_ARRAY_MODE(array_mode
));
1146 view
->tex_resource_words
[2] = (surflevel
[0].offset
+ r600_resource_va(ctx
->screen
, texture
)) >> 8;
1148 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
1149 if (texture
->nr_samples
> 1 && rscreen
->msaa_texture_support
== MSAA_TEXTURE_COMPRESSED
) {
1150 /* XXX the 2x and 4x cases are broken. */
1151 if (tmp
->is_depth
|| tmp
->resource
.b
.b
.nr_samples
!= 8) {
1152 /* disable FMASK (0 = disabled) */
1153 view
->tex_resource_words
[3] = 0;
1154 view
->skip_mip_address_reloc
= true;
1156 /* FMASK should be in MIP_ADDRESS for multisample textures */
1157 view
->tex_resource_words
[3] = (tmp
->fmask_offset
+ r600_resource_va(ctx
->screen
, texture
)) >> 8;
1159 } else if (state
->u
.tex
.last_level
&& texture
->nr_samples
<= 1) {
1160 view
->tex_resource_words
[3] = (surflevel
[1].offset
+ r600_resource_va(ctx
->screen
, texture
)) >> 8;
1162 view
->tex_resource_words
[3] = (surflevel
[0].offset
+ r600_resource_va(ctx
->screen
, texture
)) >> 8;
1165 view
->tex_resource_words
[4] = (word4
|
1166 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
1167 S_030010_ENDIAN_SWAP(endian
));
1168 view
->tex_resource_words
[5] = S_030014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
1169 S_030014_LAST_ARRAY(state
->u
.tex
.last_layer
);
1170 if (texture
->nr_samples
> 1) {
1171 unsigned log_samples
= util_logbase2(texture
->nr_samples
);
1172 if (rscreen
->chip_class
== CAYMAN
) {
1173 view
->tex_resource_words
[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples
);
1175 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1176 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(log_samples
);
1178 view
->tex_resource_words
[4] |= S_030010_BASE_LEVEL(state
->u
.tex
.first_level
);
1179 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(state
->u
.tex
.last_level
);
1181 /* aniso max 16 samples */
1182 view
->tex_resource_words
[6] = (S_030018_MAX_ANISO(4)) |
1183 (S_030018_TILE_SPLIT(tile_split
));
1184 view
->tex_resource_words
[7] = S_03001C_DATA_FORMAT(format
) |
1185 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
) |
1186 S_03001C_BANK_WIDTH(bankw
) |
1187 S_03001C_BANK_HEIGHT(bankh
) |
1188 S_03001C_MACRO_TILE_ASPECT(macro_aspect
) |
1189 S_03001C_NUM_BANKS(nbanks
) |
1190 S_03001C_DEPTH_SAMPLE_ORDER(tmp
->is_depth
&& !tmp
->is_flushing_texture
);
1194 static struct pipe_sampler_view
*
1195 evergreen_create_sampler_view(struct pipe_context
*ctx
,
1196 struct pipe_resource
*tex
,
1197 const struct pipe_sampler_view
*state
)
1199 return evergreen_create_sampler_view_custom(ctx
, tex
, state
,
1200 tex
->width0
, tex
->height0
);
1203 static void evergreen_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1205 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1206 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
1208 r600_write_context_reg_seq(cs
, R_0285BC_PA_CL_UCP0_X
, 6*4);
1209 r600_write_array(cs
, 6*4, (unsigned*)state
);
1212 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
1213 const struct pipe_poly_stipple
*state
)
1217 static void evergreen_get_scissor_rect(struct r600_context
*rctx
,
1218 unsigned tl_x
, unsigned tl_y
, unsigned br_x
, unsigned br_y
,
1219 uint32_t *tl
, uint32_t *br
)
1221 /* EG hw workaround */
1227 /* cayman hw workaround */
1228 if (rctx
->chip_class
== CAYMAN
) {
1229 if (br_x
== 1 && br_y
== 1)
1233 *tl
= S_028240_TL_X(tl_x
) | S_028240_TL_Y(tl_y
);
1234 *br
= S_028244_BR_X(br_x
) | S_028244_BR_Y(br_y
);
1237 static void evergreen_set_scissor_state(struct pipe_context
*ctx
,
1238 const struct pipe_scissor_state
*state
)
1240 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1242 rctx
->scissor
.scissor
= *state
;
1243 rctx
->scissor
.atom
.dirty
= true;
1246 static void evergreen_emit_scissor_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1248 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1249 struct pipe_scissor_state
*state
= &rctx
->scissor
.scissor
;
1252 evergreen_get_scissor_rect(rctx
, state
->minx
, state
->miny
, state
->maxx
, state
->maxy
, &tl
, &br
);
1254 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
1255 r600_write_value(cs
, tl
);
1256 r600_write_value(cs
, br
);
1260 * This function intializes the CB* register values for RATs. It is meant
1261 * to be used for 1D aligned buffers that do not have an associated
1264 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
1265 struct r600_surface
*surf
)
1267 struct pipe_resource
*pipe_buffer
= surf
->base
.texture
;
1268 unsigned format
= r600_translate_colorformat(surf
->base
.format
);
1269 unsigned endian
= r600_colorformat_endian_swap(format
);
1270 unsigned swap
= r600_translate_colorswap(surf
->base
.format
);
1271 unsigned block_size
=
1272 align(util_format_get_blocksize(pipe_buffer
->format
), 4);
1273 unsigned pitch_alignment
=
1274 MAX2(64, rctx
->screen
->tiling_info
.group_bytes
/ block_size
);
1275 unsigned pitch
= align(pipe_buffer
->width0
, pitch_alignment
);
1277 /* XXX: This is copied from evergreen_init_color_surface(). I don't
1278 * know why this is necessary.
1280 if (pipe_buffer
->usage
== PIPE_USAGE_STAGING
) {
1281 endian
= ENDIAN_NONE
;
1284 surf
->cb_color_base
=
1285 r600_resource_va(rctx
->context
.screen
, pipe_buffer
) >> 8;
1287 surf
->cb_color_pitch
= (pitch
/ 8) - 1;
1289 surf
->cb_color_slice
= 0;
1291 surf
->cb_color_view
= 0;
1293 surf
->cb_color_info
=
1294 S_028C70_ENDIAN(endian
)
1295 | S_028C70_FORMAT(format
)
1296 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
)
1297 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT
)
1298 | S_028C70_COMP_SWAP(swap
)
1299 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
1300 * are using NUMBER_UINT */
1304 surf
->cb_color_attrib
= S_028C74_NON_DISP_TILING_ORDER(1);
1306 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
1308 surf
->cb_color_dim
= pipe_buffer
->width0
;
1310 surf
->cb_color_cmask
= surf
->cb_color_base
;
1311 surf
->cb_color_cmask_slice
= 0;
1312 surf
->cb_color_fmask
= surf
->cb_color_base
;
1313 surf
->cb_color_fmask_slice
= 0;
1316 void evergreen_init_color_surface(struct r600_context
*rctx
,
1317 struct r600_surface
*surf
)
1319 struct r600_screen
*rscreen
= rctx
->screen
;
1320 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1321 struct pipe_resource
*pipe_tex
= surf
->base
.texture
;
1322 unsigned level
= surf
->base
.u
.tex
.level
;
1323 unsigned pitch
, slice
;
1324 unsigned color_info
, color_attrib
, color_dim
= 0;
1325 unsigned format
, swap
, ntype
, endian
;
1326 uint64_t offset
, base_offset
;
1327 unsigned non_disp_tiling
, macro_aspect
, tile_split
, bankh
, bankw
, fmask_bankh
, nbanks
;
1328 const struct util_format_description
*desc
;
1330 bool blend_clamp
= 0, blend_bypass
= 0;
1332 offset
= rtex
->surface
.level
[level
].offset
;
1333 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1334 offset
+= rtex
->surface
.level
[level
].slice_size
*
1335 surf
->base
.u
.tex
.first_layer
;
1337 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1338 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1343 switch (rtex
->surface
.level
[level
].mode
) {
1344 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1345 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1346 non_disp_tiling
= 1;
1348 case RADEON_SURF_MODE_1D
:
1349 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1
);
1350 non_disp_tiling
= rtex
->non_disp_tiling
;
1352 case RADEON_SURF_MODE_2D
:
1353 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1
);
1354 non_disp_tiling
= rtex
->non_disp_tiling
;
1356 case RADEON_SURF_MODE_LINEAR
:
1358 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL
);
1359 non_disp_tiling
= 1;
1362 tile_split
= rtex
->surface
.tile_split
;
1363 macro_aspect
= rtex
->surface
.mtilea
;
1364 bankw
= rtex
->surface
.bankw
;
1365 bankh
= rtex
->surface
.bankh
;
1366 fmask_bankh
= rtex
->fmask_bank_height
;
1367 tile_split
= eg_tile_split(tile_split
);
1368 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1369 bankw
= eg_bank_wh(bankw
);
1370 bankh
= eg_bank_wh(bankh
);
1371 fmask_bankh
= eg_bank_wh(fmask_bankh
);
1373 /* 128 bit formats require tile type = 1 */
1374 if (rscreen
->chip_class
== CAYMAN
) {
1375 if (util_format_get_blocksize(surf
->base
.format
) >= 16)
1376 non_disp_tiling
= 1;
1378 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1379 desc
= util_format_description(surf
->base
.format
);
1380 for (i
= 0; i
< 4; i
++) {
1381 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1386 color_attrib
= S_028C74_TILE_SPLIT(tile_split
)|
1387 S_028C74_NUM_BANKS(nbanks
) |
1388 S_028C74_BANK_WIDTH(bankw
) |
1389 S_028C74_BANK_HEIGHT(bankh
) |
1390 S_028C74_MACRO_TILE_ASPECT(macro_aspect
) |
1391 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling
) |
1392 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
1394 if (rctx
->chip_class
== CAYMAN
&& rtex
->resource
.b
.b
.nr_samples
> 1) {
1395 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
1396 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1397 S_028C74_NUM_FRAGMENTS(log_samples
);
1400 ntype
= V_028C70_NUMBER_UNORM
;
1401 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1402 ntype
= V_028C70_NUMBER_SRGB
;
1403 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1404 if (desc
->channel
[i
].normalized
)
1405 ntype
= V_028C70_NUMBER_SNORM
;
1406 else if (desc
->channel
[i
].pure_integer
)
1407 ntype
= V_028C70_NUMBER_SINT
;
1408 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1409 if (desc
->channel
[i
].normalized
)
1410 ntype
= V_028C70_NUMBER_UNORM
;
1411 else if (desc
->channel
[i
].pure_integer
)
1412 ntype
= V_028C70_NUMBER_UINT
;
1415 format
= r600_translate_colorformat(surf
->base
.format
);
1416 assert(format
!= ~0);
1418 swap
= r600_translate_colorswap(surf
->base
.format
);
1421 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1422 endian
= ENDIAN_NONE
;
1424 endian
= r600_colorformat_endian_swap(format
);
1427 /* blend clamp should be set for all NORM/SRGB types */
1428 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
1429 ntype
== V_028C70_NUMBER_SRGB
)
1432 /* set blend bypass according to docs if SINT/UINT or
1433 8/24 COLOR variants */
1434 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1435 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1436 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1441 surf
->alphatest_bypass
= ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
;
1443 color_info
|= S_028C70_FORMAT(format
) |
1444 S_028C70_COMP_SWAP(swap
) |
1445 S_028C70_BLEND_CLAMP(blend_clamp
) |
1446 S_028C70_BLEND_BYPASS(blend_bypass
) |
1447 S_028C70_NUMBER_TYPE(ntype
) |
1448 S_028C70_ENDIAN(endian
);
1451 color_info
|= S_028C70_RAT(1);
1452 color_dim
= S_028C78_WIDTH_MAX(pipe_tex
->width0
& 0xffff)
1453 | S_028C78_HEIGHT_MAX((pipe_tex
->width0
>> 16) & 0xffff);
1456 /* EXPORT_NORM is an optimzation that can be enabled for better
1457 * performance in certain cases.
1458 * EXPORT_NORM can be enabled if:
1459 * - 11-bit or smaller UNORM/SNORM/SRGB
1460 * - 16-bit or smaller FLOAT
1462 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1463 ((desc
->channel
[i
].size
< 12 &&
1464 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1465 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
1466 (desc
->channel
[i
].size
< 17 &&
1467 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1468 color_info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
1469 surf
->export_16bpc
= true;
1472 if (rtex
->fmask_size
&& rtex
->cmask_size
) {
1473 color_info
|= S_028C70_COMPRESSION(1) | S_028C70_FAST_CLEAR(1);
1476 base_offset
= r600_resource_va(rctx
->context
.screen
, pipe_tex
);
1478 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1479 surf
->cb_color_base
= (base_offset
+ offset
) >> 8;
1480 surf
->cb_color_dim
= color_dim
;
1481 surf
->cb_color_info
= color_info
;
1482 surf
->cb_color_pitch
= S_028C64_PITCH_TILE_MAX(pitch
);
1483 surf
->cb_color_slice
= S_028C68_SLICE_TILE_MAX(slice
);
1484 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1485 surf
->cb_color_view
= 0;
1487 surf
->cb_color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1488 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1490 surf
->cb_color_attrib
= color_attrib
;
1491 if (rtex
->fmask_size
&& rtex
->cmask_size
) {
1492 surf
->cb_color_fmask
= (base_offset
+ rtex
->fmask_offset
) >> 8;
1493 surf
->cb_color_cmask
= (base_offset
+ rtex
->cmask_offset
) >> 8;
1495 surf
->cb_color_fmask
= surf
->cb_color_base
;
1496 surf
->cb_color_cmask
= surf
->cb_color_base
;
1498 surf
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice
);
1499 surf
->cb_color_cmask_slice
= S_028C80_TILE_MAX(rtex
->cmask_slice_tile_max
);
1501 surf
->color_initialized
= true;
1504 static void evergreen_init_depth_surface(struct r600_context
*rctx
,
1505 struct r600_surface
*surf
)
1507 struct r600_screen
*rscreen
= rctx
->screen
;
1508 struct pipe_screen
*screen
= &rscreen
->screen
;
1509 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1511 unsigned level
, pitch
, slice
, format
, array_mode
;
1512 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1514 level
= surf
->base
.u
.tex
.level
;
1515 format
= r600_translate_dbformat(surf
->base
.format
);
1516 assert(format
!= ~0);
1518 offset
= r600_resource_va(screen
, surf
->base
.texture
);
1519 offset
+= rtex
->surface
.level
[level
].offset
;
1520 pitch
= (rtex
->surface
.level
[level
].nblk_x
/ 8) - 1;
1521 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1525 switch (rtex
->surface
.level
[level
].mode
) {
1526 case RADEON_SURF_MODE_2D
:
1527 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1529 case RADEON_SURF_MODE_1D
:
1530 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1531 case RADEON_SURF_MODE_LINEAR
:
1533 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1536 tile_split
= rtex
->surface
.tile_split
;
1537 macro_aspect
= rtex
->surface
.mtilea
;
1538 bankw
= rtex
->surface
.bankw
;
1539 bankh
= rtex
->surface
.bankh
;
1540 tile_split
= eg_tile_split(tile_split
);
1541 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1542 bankw
= eg_bank_wh(bankw
);
1543 bankh
= eg_bank_wh(bankh
);
1544 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1547 surf
->db_depth_info
= S_028040_ARRAY_MODE(array_mode
) |
1548 S_028040_FORMAT(format
) |
1549 S_028040_TILE_SPLIT(tile_split
)|
1550 S_028040_NUM_BANKS(nbanks
) |
1551 S_028040_BANK_WIDTH(bankw
) |
1552 S_028040_BANK_HEIGHT(bankh
) |
1553 S_028040_MACRO_TILE_ASPECT(macro_aspect
);
1554 if (rscreen
->chip_class
== CAYMAN
&& rtex
->resource
.b
.b
.nr_samples
> 1) {
1555 surf
->db_depth_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
1557 surf
->db_depth_base
= offset
;
1558 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1559 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1560 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX(pitch
);
1561 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX(slice
);
1563 switch (surf
->base
.format
) {
1564 case PIPE_FORMAT_Z24X8_UNORM
:
1565 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1566 surf
->pa_su_poly_offset_db_fmt_cntl
=
1567 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1569 case PIPE_FORMAT_Z32_FLOAT
:
1570 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1571 surf
->pa_su_poly_offset_db_fmt_cntl
=
1572 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1573 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1575 case PIPE_FORMAT_Z16_UNORM
:
1576 surf
->pa_su_poly_offset_db_fmt_cntl
=
1577 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1582 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1583 uint64_t stencil_offset
;
1584 unsigned stile_split
= rtex
->surface
.stencil_tile_split
;
1586 stile_split
= eg_tile_split(stile_split
);
1588 stencil_offset
= rtex
->surface
.stencil_level
[level
].offset
;
1589 stencil_offset
+= r600_resource_va(screen
, surf
->base
.texture
);
1591 surf
->db_stencil_base
= stencil_offset
>> 8;
1592 surf
->db_stencil_info
= S_028044_FORMAT(V_028044_STENCIL_8
) |
1593 S_028044_TILE_SPLIT(stile_split
);
1595 surf
->db_stencil_base
= offset
;
1596 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1597 * Older kernels are out of luck. */
1598 surf
->db_stencil_info
= rctx
->screen
->info
.drm_minor
>= 18 ?
1599 S_028044_FORMAT(V_028044_STENCIL_INVALID
) :
1600 S_028044_FORMAT(V_028044_STENCIL_8
);
1603 surf
->htile_enabled
= 0;
1604 /* use htile only for first level */
1605 if (rtex
->htile
&& !level
) {
1606 uint64_t va
= r600_resource_va(&rctx
->screen
->screen
, &rtex
->htile
->b
.b
);
1607 surf
->htile_enabled
= 1;
1608 surf
->db_htile_data_base
= va
>> 8;
1609 surf
->db_htile_surface
= S_028ABC_HTILE_WIDTH(1) |
1610 S_028ABC_HTILE_HEIGHT(1) |
1612 surf
->db_depth_info
|= S_028040_TILE_SURFACE_ENABLE(1);
1613 surf
->db_preload_control
= 0;
1616 surf
->depth_initialized
= true;
1619 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
1620 const struct pipe_framebuffer_state
*state
)
1622 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1623 struct r600_surface
*surf
;
1624 struct r600_texture
*rtex
;
1625 uint32_t i
, log_samples
;
1627 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1628 rctx
->flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1630 if (rctx
->framebuffer
.state
.cbufs
[0]->texture
->nr_samples
> 1) {
1631 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV_CB_META
;
1634 if (rctx
->framebuffer
.state
.zsbuf
) {
1635 rctx
->flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1638 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1641 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1642 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&&
1643 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1644 rctx
->framebuffer
.compressed_cb_mask
= 0;
1646 if (state
->nr_cbufs
)
1647 rctx
->framebuffer
.nr_samples
= state
->cbufs
[0]->texture
->nr_samples
;
1648 else if (state
->zsbuf
)
1649 rctx
->framebuffer
.nr_samples
= state
->zsbuf
->texture
->nr_samples
;
1651 rctx
->framebuffer
.nr_samples
= 0;
1653 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1654 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1655 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1657 if (!surf
->color_initialized
) {
1658 evergreen_init_color_surface(rctx
, surf
);
1661 if (!surf
->export_16bpc
) {
1662 rctx
->framebuffer
.export_16bpc
= false;
1665 if (rtex
->fmask_size
&& rtex
->cmask_size
) {
1666 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1670 /* Update alpha-test state dependencies.
1671 * Alpha-test is done on the first colorbuffer only. */
1672 if (state
->nr_cbufs
) {
1673 surf
= (struct r600_surface
*)state
->cbufs
[0];
1674 if (rctx
->alphatest_state
.bypass
!= surf
->alphatest_bypass
) {
1675 rctx
->alphatest_state
.bypass
= surf
->alphatest_bypass
;
1676 rctx
->alphatest_state
.atom
.dirty
= true;
1678 if (rctx
->alphatest_state
.cb0_export_16bpc
!= surf
->export_16bpc
) {
1679 rctx
->alphatest_state
.cb0_export_16bpc
= surf
->export_16bpc
;
1680 rctx
->alphatest_state
.atom
.dirty
= true;
1686 surf
= (struct r600_surface
*)state
->zsbuf
;
1688 if (!surf
->depth_initialized
) {
1689 evergreen_init_depth_surface(rctx
, surf
);
1692 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1693 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1694 rctx
->poly_offset_state
.atom
.dirty
= true;
1697 if (rctx
->db_state
.rsurf
!= surf
) {
1698 rctx
->db_state
.rsurf
= surf
;
1699 rctx
->db_state
.atom
.dirty
= true;
1700 rctx
->db_misc_state
.atom
.dirty
= true;
1702 } else if (rctx
->db_state
.rsurf
) {
1703 rctx
->db_state
.rsurf
= NULL
;
1704 rctx
->db_state
.atom
.dirty
= true;
1705 rctx
->db_misc_state
.atom
.dirty
= true;
1708 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1709 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1710 rctx
->cb_misc_state
.atom
.dirty
= true;
1713 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1714 rctx
->alphatest_state
.bypass
= false;
1715 rctx
->alphatest_state
.atom
.dirty
= true;
1718 log_samples
= util_logbase2(rctx
->framebuffer
.nr_samples
);
1719 if (rctx
->chip_class
== CAYMAN
&& rctx
->db_misc_state
.log_samples
!= log_samples
) {
1720 rctx
->db_misc_state
.log_samples
= log_samples
;
1721 rctx
->db_misc_state
.atom
.dirty
= true;
1724 evergreen_update_db_shader_control(rctx
);
1726 /* Calculate the CS size. */
1727 rctx
->framebuffer
.atom
.num_dw
= 4; /* SCISSOR */
1730 if (rctx
->chip_class
== EVERGREEN
) {
1731 switch (rctx
->framebuffer
.nr_samples
) {
1734 rctx
->framebuffer
.atom
.num_dw
+= 6;
1737 rctx
->framebuffer
.atom
.num_dw
+= 10;
1740 rctx
->framebuffer
.atom
.num_dw
+= 4;
1742 switch (rctx
->framebuffer
.nr_samples
) {
1745 rctx
->framebuffer
.atom
.num_dw
+= 12;
1748 rctx
->framebuffer
.atom
.num_dw
+= 16;
1751 rctx
->framebuffer
.atom
.num_dw
+= 18;
1754 rctx
->framebuffer
.atom
.num_dw
+= 7;
1758 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 21;
1759 if (rctx
->keep_tiling_flags
)
1760 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 2;
1761 rctx
->framebuffer
.atom
.num_dw
+= (12 - state
->nr_cbufs
) * 3;
1765 rctx
->framebuffer
.atom
.num_dw
+= 24;
1766 if (rctx
->keep_tiling_flags
)
1767 rctx
->framebuffer
.atom
.num_dw
+= 2;
1768 } else if (rctx
->screen
->info
.drm_minor
>= 18) {
1769 rctx
->framebuffer
.atom
.num_dw
+= 4;
1772 rctx
->framebuffer
.atom
.dirty
= true;
1775 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1776 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1777 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1778 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1779 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1781 static void evergreen_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
1784 * There are two locations (-4, 4), (4, -4). */
1785 static uint32_t sample_locs_2x
[] = {
1786 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1787 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1788 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1789 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1791 static unsigned max_dist_2x
= 4;
1793 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1794 static uint32_t sample_locs_4x
[] = {
1795 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1796 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1797 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1798 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1800 static unsigned max_dist_4x
= 6;
1802 static uint32_t sample_locs_8x
[] = {
1803 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1804 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1805 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1806 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1807 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1808 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1809 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1810 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1812 static unsigned max_dist_8x
= 7;
1814 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1815 unsigned max_dist
= 0;
1817 switch (nr_samples
) {
1822 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(sample_locs_2x
));
1823 r600_write_array(cs
, Elements(sample_locs_2x
), sample_locs_2x
);
1824 max_dist
= max_dist_2x
;
1827 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(sample_locs_4x
));
1828 r600_write_array(cs
, Elements(sample_locs_4x
), sample_locs_4x
);
1829 max_dist
= max_dist_4x
;
1832 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(sample_locs_8x
));
1833 r600_write_array(cs
, Elements(sample_locs_8x
), sample_locs_8x
);
1834 max_dist
= max_dist_8x
;
1838 if (nr_samples
> 1) {
1839 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1840 r600_write_value(cs
, S_028C00_LAST_PIXEL(1) |
1841 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1842 r600_write_value(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1843 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1845 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1846 r600_write_value(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1847 r600_write_value(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1851 static void cayman_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
1854 * There are two locations (-4, 4), (4, -4). */
1855 static uint32_t sample_locs_2x
[] = {
1856 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1857 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1858 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1859 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1861 static unsigned max_dist_2x
= 4;
1863 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1864 static uint32_t sample_locs_4x
[] = {
1865 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1866 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1867 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1868 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1870 static unsigned max_dist_4x
= 6;
1872 static uint32_t sample_locs_8x
[] = {
1873 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1874 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1875 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1876 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1877 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1878 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1879 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1880 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1882 static unsigned max_dist_8x
= 8;
1884 static uint32_t sample_locs_16x
[] = {
1885 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1886 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1887 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1888 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1889 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1890 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1891 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1892 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1893 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1894 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1895 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1896 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1897 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1898 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1899 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1900 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1902 static unsigned max_dist_16x
= 8;
1904 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1905 unsigned max_dist
= 0;
1907 switch (nr_samples
) {
1912 r600_write_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_2x
[0]);
1913 r600_write_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_2x
[1]);
1914 r600_write_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_2x
[2]);
1915 r600_write_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_2x
[3]);
1916 max_dist
= max_dist_2x
;
1919 r600_write_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_4x
[0]);
1920 r600_write_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_4x
[1]);
1921 r600_write_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_4x
[2]);
1922 r600_write_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_4x
[3]);
1923 max_dist
= max_dist_4x
;
1926 r600_write_context_reg_seq(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 14);
1927 r600_write_value(cs
, sample_locs_8x
[0]);
1928 r600_write_value(cs
, sample_locs_8x
[4]);
1929 r600_write_value(cs
, 0);
1930 r600_write_value(cs
, 0);
1931 r600_write_value(cs
, sample_locs_8x
[1]);
1932 r600_write_value(cs
, sample_locs_8x
[5]);
1933 r600_write_value(cs
, 0);
1934 r600_write_value(cs
, 0);
1935 r600_write_value(cs
, sample_locs_8x
[2]);
1936 r600_write_value(cs
, sample_locs_8x
[6]);
1937 r600_write_value(cs
, 0);
1938 r600_write_value(cs
, 0);
1939 r600_write_value(cs
, sample_locs_8x
[3]);
1940 r600_write_value(cs
, sample_locs_8x
[7]);
1941 max_dist
= max_dist_8x
;
1944 r600_write_context_reg_seq(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 16);
1945 r600_write_value(cs
, sample_locs_16x
[0]);
1946 r600_write_value(cs
, sample_locs_16x
[4]);
1947 r600_write_value(cs
, sample_locs_16x
[8]);
1948 r600_write_value(cs
, sample_locs_16x
[12]);
1949 r600_write_value(cs
, sample_locs_16x
[1]);
1950 r600_write_value(cs
, sample_locs_16x
[5]);
1951 r600_write_value(cs
, sample_locs_16x
[9]);
1952 r600_write_value(cs
, sample_locs_16x
[13]);
1953 r600_write_value(cs
, sample_locs_16x
[2]);
1954 r600_write_value(cs
, sample_locs_16x
[6]);
1955 r600_write_value(cs
, sample_locs_16x
[10]);
1956 r600_write_value(cs
, sample_locs_16x
[14]);
1957 r600_write_value(cs
, sample_locs_16x
[3]);
1958 r600_write_value(cs
, sample_locs_16x
[7]);
1959 r600_write_value(cs
, sample_locs_16x
[11]);
1960 r600_write_value(cs
, sample_locs_16x
[15]);
1961 max_dist
= max_dist_16x
;
1965 if (nr_samples
> 1) {
1966 unsigned log_samples
= util_logbase2(nr_samples
);
1968 r600_write_context_reg_seq(cs
, CM_R_028BDC_PA_SC_LINE_CNTL
, 2);
1969 r600_write_value(cs
, S_028C00_LAST_PIXEL(1) |
1970 S_028C00_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1971 r600_write_value(cs
, S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1972 S_028BE0_MAX_SAMPLE_DIST(max_dist
) |
1973 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1975 r600_write_context_reg(cs
, CM_R_028804_DB_EQAA
,
1976 S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1977 S_028804_PS_ITER_SAMPLES(log_samples
) |
1978 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1979 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
) |
1980 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1981 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1983 r600_write_context_reg_seq(cs
, CM_R_028BDC_PA_SC_LINE_CNTL
, 2);
1984 r600_write_value(cs
, S_028C00_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1985 r600_write_value(cs
, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1987 r600_write_context_reg(cs
, CM_R_028804_DB_EQAA
,
1988 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1989 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1993 static void evergreen_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1995 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1996 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1997 unsigned nr_cbufs
= state
->nr_cbufs
;
2000 /* XXX support more colorbuffers once we need them */
2001 assert(nr_cbufs
<= 8);
2006 for (i
= 0; i
< nr_cbufs
; i
++) {
2007 struct r600_surface
*cb
= (struct r600_surface
*)state
->cbufs
[i
];
2008 unsigned reloc
= r600_context_bo_reloc(rctx
, (struct r600_resource
*)cb
->base
.texture
,
2009 RADEON_USAGE_READWRITE
);
2011 r600_write_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 11);
2012 r600_write_value(cs
, cb
->cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
2013 r600_write_value(cs
, cb
->cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
2014 r600_write_value(cs
, cb
->cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
2015 r600_write_value(cs
, cb
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
2016 r600_write_value(cs
, cb
->cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
2017 r600_write_value(cs
, cb
->cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
2018 r600_write_value(cs
, cb
->cb_color_dim
); /* R_028C78_CB_COLOR0_DIM */
2019 r600_write_value(cs
, cb
->cb_color_cmask
); /* R_028C7C_CB_COLOR0_CMASK */
2020 r600_write_value(cs
, cb
->cb_color_cmask_slice
); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2021 r600_write_value(cs
, cb
->cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
2022 r600_write_value(cs
, cb
->cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2024 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
2025 r600_write_value(cs
, reloc
);
2027 if (!rctx
->keep_tiling_flags
) {
2028 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
2029 r600_write_value(cs
, reloc
);
2032 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
2033 r600_write_value(cs
, reloc
);
2035 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
2036 r600_write_value(cs
, reloc
);
2038 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
2039 r600_write_value(cs
, reloc
);
2041 /* set CB_COLOR1_INFO for possible dual-src blending */
2042 if (i
== 1 && !((struct r600_texture
*)state
->cbufs
[0]->texture
)->is_rat
) {
2043 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C,
2044 ((struct r600_surface
*)state
->cbufs
[0])->cb_color_info
);
2046 if (!rctx
->keep_tiling_flags
) {
2047 unsigned reloc
= r600_context_bo_reloc(rctx
, (struct r600_resource
*)state
->cbufs
[0]->texture
,
2048 RADEON_USAGE_READWRITE
);
2050 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
2051 r600_write_value(cs
, reloc
);
2055 if (rctx
->keep_tiling_flags
) {
2056 for (; i
< 8 ; i
++) {
2057 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
2059 for (; i
< 12; i
++) {
2060 r600_write_context_reg(cs
, R_028E50_CB_COLOR8_INFO
+ (i
- 8) * 0x1C, 0);
2066 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
2067 unsigned reloc
= r600_context_bo_reloc(rctx
, (struct r600_resource
*)state
->zsbuf
->texture
,
2068 RADEON_USAGE_READWRITE
);
2070 r600_write_context_reg(cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
2071 zb
->pa_su_poly_offset_db_fmt_cntl
);
2072 r600_write_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
2074 r600_write_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 8);
2075 r600_write_value(cs
, zb
->db_depth_info
); /* R_028040_DB_Z_INFO */
2076 r600_write_value(cs
, zb
->db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
2077 r600_write_value(cs
, zb
->db_depth_base
); /* R_028048_DB_Z_READ_BASE */
2078 r600_write_value(cs
, zb
->db_stencil_base
); /* R_02804C_DB_STENCIL_READ_BASE */
2079 r600_write_value(cs
, zb
->db_depth_base
); /* R_028050_DB_Z_WRITE_BASE */
2080 r600_write_value(cs
, zb
->db_stencil_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
2081 r600_write_value(cs
, zb
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
2082 r600_write_value(cs
, zb
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
2084 if (!rctx
->keep_tiling_flags
) {
2085 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028040_DB_Z_INFO */
2086 r600_write_value(cs
, reloc
);
2089 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028048_DB_Z_READ_BASE */
2090 r600_write_value(cs
, reloc
);
2092 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
2093 r600_write_value(cs
, reloc
);
2095 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
2096 r600_write_value(cs
, reloc
);
2098 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
2099 r600_write_value(cs
, reloc
);
2100 } else if (rctx
->screen
->info
.drm_minor
>= 18) {
2101 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
2102 * Older kernels are out of luck. */
2103 r600_write_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
2104 r600_write_value(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
2105 r600_write_value(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
2108 /* Framebuffer dimensions. */
2109 evergreen_get_scissor_rect(rctx
, 0, 0, state
->width
, state
->height
, &tl
, &br
);
2111 r600_write_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
2112 r600_write_value(cs
, tl
); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
2113 r600_write_value(cs
, br
); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
2115 if (rctx
->chip_class
== EVERGREEN
) {
2116 evergreen_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
2118 cayman_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
2122 static void evergreen_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
2124 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2125 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
2126 float offset_units
= state
->offset_units
;
2127 float offset_scale
= state
->offset_scale
;
2129 switch (state
->zs_format
) {
2130 case PIPE_FORMAT_Z24X8_UNORM
:
2131 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2132 offset_units
*= 2.0f
;
2134 case PIPE_FORMAT_Z16_UNORM
:
2135 offset_units
*= 4.0f
;
2140 r600_write_context_reg_seq(cs
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
2141 r600_write_value(cs
, fui(offset_scale
));
2142 r600_write_value(cs
, fui(offset_units
));
2143 r600_write_value(cs
, fui(offset_scale
));
2144 r600_write_value(cs
, fui(offset_units
));
2147 static void evergreen_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2149 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2150 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
2151 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
2152 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
2154 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
2155 r600_write_value(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
2156 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
2157 * will assure that the alpha-test will work even if there is
2158 * no colorbuffer bound. */
2159 r600_write_value(cs
, 0xf | (a
->dual_src_blend
? ps_colormask
: 0) | fb_colormask
); /* R_02823C_CB_SHADER_MASK */
2162 static void evergreen_emit_db_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2164 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2165 struct r600_db_state
*a
= (struct r600_db_state
*)atom
;
2167 if (a
->rsurf
&& a
->rsurf
->htile_enabled
) {
2168 struct r600_texture
*rtex
= (struct r600_texture
*)a
->rsurf
->base
.texture
;
2171 r600_write_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear
));
2172 r600_write_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, a
->rsurf
->db_htile_surface
);
2173 r600_write_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, a
->rsurf
->db_preload_control
);
2174 r600_write_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, a
->rsurf
->db_htile_data_base
);
2175 reloc_idx
= r600_context_bo_reloc(rctx
, rtex
->htile
, RADEON_USAGE_READWRITE
);
2176 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
2177 cs
->buf
[cs
->cdw
++] = reloc_idx
;
2179 r600_write_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, 0);
2180 r600_write_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0);
2184 static void evergreen_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2186 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2187 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
2188 unsigned db_render_control
= 0;
2189 unsigned db_count_control
= 0;
2190 unsigned db_render_override
=
2191 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
2192 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
2194 if (a
->occlusion_query_enabled
) {
2195 db_count_control
|= S_028004_PERFECT_ZPASS_COUNTS(1);
2196 if (rctx
->chip_class
== CAYMAN
) {
2197 db_count_control
|= S_028004_SAMPLE_RATE(a
->log_samples
);
2199 db_render_override
|= S_02800C_NOOP_CULL_DISABLE(1);
2201 if (rctx
->db_state
.rsurf
&& rctx
->db_state
.rsurf
->htile_enabled
) {
2202 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
2203 db_render_override
|= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF
);
2205 db_render_override
|= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
);
2207 if (a
->flush_depthstencil_through_cb
) {
2208 assert(a
->copy_depth
|| a
->copy_stencil
);
2210 db_render_control
|= S_028000_DEPTH_COPY_ENABLE(a
->copy_depth
) |
2211 S_028000_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
2212 S_028000_COPY_CENTROID(1) |
2213 S_028000_COPY_SAMPLE(a
->copy_sample
);
2214 } else if (a
->flush_depthstencil_in_place
) {
2215 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(1) |
2216 S_028000_STENCIL_COMPRESS_DISABLE(1);
2217 db_render_override
|= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2219 if (a
->htile_clear
) {
2220 /* FIXME we might want to disable cliprect here */
2221 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(1);
2224 r600_write_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
2225 r600_write_value(cs
, db_render_control
); /* R_028000_DB_RENDER_CONTROL */
2226 r600_write_value(cs
, db_count_control
); /* R_028004_DB_COUNT_CONTROL */
2227 r600_write_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
2228 r600_write_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
2231 static void evergreen_emit_vertex_buffers(struct r600_context
*rctx
,
2232 struct r600_vertexbuf_state
*state
,
2233 unsigned resource_offset
,
2236 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2237 uint32_t dirty_mask
= state
->dirty_mask
;
2239 while (dirty_mask
) {
2240 struct pipe_vertex_buffer
*vb
;
2241 struct r600_resource
*rbuffer
;
2243 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
2245 vb
= &state
->vb
[buffer_index
];
2246 rbuffer
= (struct r600_resource
*)vb
->buffer
;
2249 va
= r600_resource_va(&rctx
->screen
->screen
, &rbuffer
->b
.b
);
2250 va
+= vb
->buffer_offset
;
2252 /* fetch resources start at index 992 */
2253 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
2254 r600_write_value(cs
, (resource_offset
+ buffer_index
) * 8);
2255 r600_write_value(cs
, va
); /* RESOURCEi_WORD0 */
2256 r600_write_value(cs
, rbuffer
->buf
->size
- vb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
2257 r600_write_value(cs
, /* RESOURCEi_WORD2 */
2258 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2259 S_030008_STRIDE(vb
->stride
) |
2260 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
2261 r600_write_value(cs
, /* RESOURCEi_WORD3 */
2262 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
2263 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
2264 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
2265 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
2266 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
2267 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
2268 r600_write_value(cs
, 0); /* RESOURCEi_WORD6 */
2269 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
2271 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2272 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
2274 state
->dirty_mask
= 0;
2277 static void evergreen_fs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
2279 evergreen_emit_vertex_buffers(rctx
, &rctx
->vertex_buffer_state
, 992, 0);
2282 static void evergreen_cs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
2284 evergreen_emit_vertex_buffers(rctx
, &rctx
->cs_vertex_buffer_state
, 816,
2285 RADEON_CP_PACKET3_COMPUTE_MODE
);
2288 static void evergreen_emit_constant_buffers(struct r600_context
*rctx
,
2289 struct r600_constbuf_state
*state
,
2290 unsigned buffer_id_base
,
2291 unsigned reg_alu_constbuf_size
,
2292 unsigned reg_alu_const_cache
)
2294 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2295 uint32_t dirty_mask
= state
->dirty_mask
;
2297 while (dirty_mask
) {
2298 struct pipe_constant_buffer
*cb
;
2299 struct r600_resource
*rbuffer
;
2301 unsigned buffer_index
= ffs(dirty_mask
) - 1;
2303 cb
= &state
->cb
[buffer_index
];
2304 rbuffer
= (struct r600_resource
*)cb
->buffer
;
2307 va
= r600_resource_va(&rctx
->screen
->screen
, &rbuffer
->b
.b
);
2308 va
+= cb
->buffer_offset
;
2310 r600_write_context_reg(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
2311 ALIGN_DIVUP(cb
->buffer_size
>> 4, 16));
2312 r600_write_context_reg(cs
, reg_alu_const_cache
+ buffer_index
* 4, va
>> 8);
2314 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2315 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
2317 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0));
2318 r600_write_value(cs
, (buffer_id_base
+ buffer_index
) * 8);
2319 r600_write_value(cs
, va
); /* RESOURCEi_WORD0 */
2320 r600_write_value(cs
, rbuffer
->buf
->size
- cb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
2321 r600_write_value(cs
, /* RESOURCEi_WORD2 */
2322 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2323 S_030008_STRIDE(16) |
2324 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
2325 r600_write_value(cs
, /* RESOURCEi_WORD3 */
2326 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
2327 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
2328 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
2329 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
2330 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
2331 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
2332 r600_write_value(cs
, 0); /* RESOURCEi_WORD6 */
2333 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
2335 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2336 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
2338 dirty_mask
&= ~(1 << buffer_index
);
2340 state
->dirty_mask
= 0;
2343 static void evergreen_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2345 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
], 176,
2346 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
2347 R_028980_ALU_CONST_CACHE_VS_0
);
2350 static void evergreen_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2352 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
], 336,
2353 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
2354 R_0289C0_ALU_CONST_CACHE_GS_0
);
2357 static void evergreen_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2359 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
], 0,
2360 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
2361 R_028940_ALU_CONST_CACHE_PS_0
);
2364 static void evergreen_emit_sampler_views(struct r600_context
*rctx
,
2365 struct r600_samplerview_state
*state
,
2366 unsigned resource_id_base
)
2368 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2369 uint32_t dirty_mask
= state
->dirty_mask
;
2371 while (dirty_mask
) {
2372 struct r600_pipe_sampler_view
*rview
;
2373 unsigned resource_index
= u_bit_scan(&dirty_mask
);
2376 rview
= state
->views
[resource_index
];
2379 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0));
2380 r600_write_value(cs
, (resource_id_base
+ resource_index
) * 8);
2381 r600_write_array(cs
, 8, rview
->tex_resource_words
);
2383 reloc
= r600_context_bo_reloc(rctx
, rview
->tex_resource
,
2385 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2386 r600_write_value(cs
, reloc
);
2388 if (!rview
->skip_mip_address_reloc
) {
2389 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2390 r600_write_value(cs
, reloc
);
2393 state
->dirty_mask
= 0;
2396 static void evergreen_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2398 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
, 176 + R600_MAX_CONST_BUFFERS
);
2401 static void evergreen_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2403 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
, 336 + R600_MAX_CONST_BUFFERS
);
2406 static void evergreen_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2408 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
, R600_MAX_CONST_BUFFERS
);
2411 static void evergreen_emit_sampler_states(struct r600_context
*rctx
,
2412 struct r600_textures_info
*texinfo
,
2413 unsigned resource_id_base
,
2414 unsigned border_index_reg
)
2416 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2417 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
2419 while (dirty_mask
) {
2420 struct r600_pipe_sampler_state
*rstate
;
2421 unsigned i
= u_bit_scan(&dirty_mask
);
2423 rstate
= texinfo
->states
.states
[i
];
2426 r600_write_value(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0));
2427 r600_write_value(cs
, (resource_id_base
+ i
) * 3);
2428 r600_write_array(cs
, 3, rstate
->tex_sampler_words
);
2430 if (rstate
->border_color_use
) {
2431 r600_write_config_reg_seq(cs
, border_index_reg
, 5);
2432 r600_write_value(cs
, i
);
2433 r600_write_array(cs
, 4, rstate
->border_color
.ui
);
2436 texinfo
->states
.dirty_mask
= 0;
2439 static void evergreen_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2441 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
);
2444 static void evergreen_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2446 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX
);
2449 static void evergreen_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2451 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
);
2454 static void evergreen_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2456 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2457 uint8_t mask
= s
->sample_mask
;
2459 r600_write_context_reg(rctx
->cs
, R_028C3C_PA_SC_AA_MASK
,
2460 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2463 static void cayman_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2465 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2466 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2467 uint16_t mask
= s
->sample_mask
;
2469 r600_write_context_reg_seq(cs
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2470 r600_write_value(cs
, mask
| (mask
<< 16)); /* X0Y0_X1Y0 */
2471 r600_write_value(cs
, mask
| (mask
<< 16)); /* X0Y1_X1Y1 */
2474 static void evergreen_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2476 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2477 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
2478 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
->cso
;
2480 r600_write_context_reg(cs
, R_0288A4_SQ_PGM_START_FS
,
2481 (r600_resource_va(rctx
->context
.screen
, &shader
->buffer
->b
.b
) + shader
->offset
) >> 8);
2482 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2483 r600_write_value(cs
, r600_context_bo_reloc(rctx
, shader
->buffer
, RADEON_USAGE_READ
));
2486 void evergreen_init_state_functions(struct r600_context
*rctx
)
2491 * To avoid GPU lockup registers must be emited in a specific order
2492 * (no kidding ...). The order below is important and have been
2493 * partialy infered from analyzing fglrx command stream.
2495 * Don't reorder atom without carefully checking the effect (GPU lockup
2496 * or piglit regression).
2500 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, evergreen_emit_framebuffer_state
, 0);
2502 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, evergreen_emit_vs_constant_buffers
, 0);
2503 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, evergreen_emit_gs_constant_buffers
, 0);
2504 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, evergreen_emit_ps_constant_buffers
, 0);
2505 /* shader program */
2506 r600_init_atom(rctx
, &rctx
->cs_shader_state
.atom
, id
++, evergreen_emit_cs_shader
, 0);
2508 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, evergreen_emit_vs_sampler_states
, 0);
2509 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, evergreen_emit_gs_sampler_states
, 0);
2510 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, evergreen_emit_ps_sampler_states
, 0);
2512 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, evergreen_fs_emit_vertex_buffers
, 0);
2513 r600_init_atom(rctx
, &rctx
->cs_vertex_buffer_state
.atom
, id
++, evergreen_cs_emit_vertex_buffers
, 0);
2514 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, evergreen_emit_vs_sampler_views
, 0);
2515 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, evergreen_emit_gs_sampler_views
, 0);
2516 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, evergreen_emit_ps_sampler_views
, 0);
2518 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 6);
2519 r600_init_atom(rctx
, &rctx
->vgt2_state
.atom
, id
++, r600_emit_vgt2_state
, 3);
2521 if (rctx
->chip_class
== EVERGREEN
) {
2522 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, evergreen_emit_sample_mask
, 3);
2524 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, cayman_emit_sample_mask
, 4);
2526 rctx
->sample_mask
.sample_mask
= ~0;
2528 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
2529 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
2530 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
2531 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, evergreen_emit_cb_misc_state
, 4);
2532 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 6);
2533 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, evergreen_emit_clip_state
, 26);
2534 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, evergreen_emit_db_misc_state
, 10);
2535 r600_init_atom(rctx
, &rctx
->db_state
.atom
, id
++, evergreen_emit_db_state
, 14);
2536 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
2537 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, evergreen_emit_polygon_offset
, 6);
2538 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
2539 r600_init_atom(rctx
, &rctx
->scissor
.atom
, id
++, evergreen_emit_scissor_state
, 4);
2540 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
2541 r600_init_atom(rctx
, &rctx
->viewport
.atom
, id
++, r600_emit_viewport_state
, 8);
2542 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, evergreen_emit_vertex_fetch_shader
, 5);
2544 rctx
->context
.create_blend_state
= evergreen_create_blend_state
;
2545 rctx
->context
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
2546 rctx
->context
.create_rasterizer_state
= evergreen_create_rs_state
;
2547 rctx
->context
.create_sampler_state
= evergreen_create_sampler_state
;
2548 rctx
->context
.create_sampler_view
= evergreen_create_sampler_view
;
2549 rctx
->context
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
2550 rctx
->context
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
2551 rctx
->context
.set_scissor_state
= evergreen_set_scissor_state
;
2552 evergreen_init_compute_state_functions(rctx
);
2555 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
2556 enum chip_class ctx_chip_class
,
2557 enum radeon_family ctx_family
,
2560 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2561 r600_store_value(cb
, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2562 /* always set the temp clauses */
2563 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2565 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2566 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2567 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2569 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2571 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
2573 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2575 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2578 static void cayman_init_atom_start_cs(struct r600_context
*rctx
)
2580 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2582 r600_init_command_buffer(cb
, 256);
2584 /* This must be first. */
2585 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2586 r600_store_value(cb
, 0x80000000);
2587 r600_store_value(cb
, 0x80000000);
2589 /* We're setting config registers here. */
2590 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2591 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2593 cayman_init_common_regs(cb
, rctx
->chip_class
,
2594 rctx
->family
, rctx
->screen
->info
.drm_minor
);
2596 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2597 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2599 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2600 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2601 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2602 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2603 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2604 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2605 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2607 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2608 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2609 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2610 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2611 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2613 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2614 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2615 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2616 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2617 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2618 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2619 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2620 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2621 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2622 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2623 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2624 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2625 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2626 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2628 r600_store_context_reg_seq(cb
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
2629 r600_store_value(cb
, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2630 r600_store_value(cb
, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2632 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2633 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
2634 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2636 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2638 r600_store_context_reg(cb
, CM_R_028AA8_IA_MULTI_VGT_PARAM
, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2640 r600_store_context_reg_seq(cb
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
2641 r600_store_value(cb
, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2642 r600_store_value(cb
, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2644 r600_store_context_reg_seq(cb
, CM_R_0288E8_SQ_LDS_ALLOC
, 2);
2645 r600_store_value(cb
, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2646 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2648 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2650 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2651 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2652 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2654 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2656 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2658 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2660 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2661 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2662 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2663 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2665 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2666 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2668 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
2669 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2670 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2672 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2673 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
2674 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2676 r600_store_context_reg_seq(cb
, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2677 r600_store_value(cb
, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2678 r600_store_value(cb
, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2679 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2680 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2682 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2683 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2684 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2686 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2687 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2688 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2690 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2691 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2692 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2694 /* to avoid GPU doing any preloading of constant from random address */
2695 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2696 r600_store_value(cb
, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2697 r600_store_value(cb
, 0);
2698 r600_store_value(cb
, 0);
2699 r600_store_value(cb
, 0);
2700 r600_store_value(cb
, 0);
2701 r600_store_value(cb
, 0);
2702 r600_store_value(cb
, 0);
2703 r600_store_value(cb
, 0);
2704 r600_store_value(cb
, 0);
2705 r600_store_value(cb
, 0);
2706 r600_store_value(cb
, 0);
2707 r600_store_value(cb
, 0);
2708 r600_store_value(cb
, 0);
2709 r600_store_value(cb
, 0);
2710 r600_store_value(cb
, 0);
2711 r600_store_value(cb
, 0);
2713 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2714 r600_store_value(cb
, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2715 r600_store_value(cb
, 0);
2716 r600_store_value(cb
, 0);
2717 r600_store_value(cb
, 0);
2718 r600_store_value(cb
, 0);
2719 r600_store_value(cb
, 0);
2720 r600_store_value(cb
, 0);
2721 r600_store_value(cb
, 0);
2722 r600_store_value(cb
, 0);
2723 r600_store_value(cb
, 0);
2724 r600_store_value(cb
, 0);
2725 r600_store_value(cb
, 0);
2726 r600_store_value(cb
, 0);
2727 r600_store_value(cb
, 0);
2728 r600_store_value(cb
, 0);
2729 r600_store_value(cb
, 0);
2731 if (rctx
->screen
->has_streamout
) {
2732 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2735 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2736 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2739 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
2740 enum chip_class ctx_chip_class
,
2741 enum radeon_family ctx_family
,
2780 switch (ctx_family
) {
2788 tmp
|= S_008C00_VC_ENABLE(1);
2791 tmp
|= S_008C00_EXPORT_SRC_C(1);
2792 tmp
|= S_008C00_CS_PRIO(cs_prio
);
2793 tmp
|= S_008C00_LS_PRIO(ls_prio
);
2794 tmp
|= S_008C00_HS_PRIO(hs_prio
);
2795 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2796 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2797 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2798 tmp
|= S_008C00_ES_PRIO(es_prio
);
2800 /* enable dynamic GPR resource management */
2801 if (ctx_drm_minor
>= 7) {
2802 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2803 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2804 /* always set temp clauses */
2805 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2806 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2807 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2808 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2809 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2810 r600_store_context_reg(cb
, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
,
2811 S_028838_PS_GPRS(0x1e) |
2812 S_028838_VS_GPRS(0x1e) |
2813 S_028838_GS_GPRS(0x1e) |
2814 S_028838_ES_GPRS(0x1e) |
2815 S_028838_HS_GPRS(0x1e) |
2816 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2818 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 4);
2819 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2821 tmp
= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
2822 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
2823 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
2824 r600_store_value(cb
, tmp
); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2826 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2827 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2828 r600_store_value(cb
, tmp
); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2830 tmp
= S_008C0C_NUM_HS_GPRS(num_hs_gprs
);
2831 tmp
|= S_008C0C_NUM_HS_GPRS(num_ls_gprs
);
2832 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2835 r600_store_config_reg(cb
, R_008E2C_SQ_LDS_RESOURCE_MGMT
,
2836 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2838 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
2840 /* The cs checker requires this register to be set. */
2841 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2843 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2848 void evergreen_init_atom_start_cs(struct r600_context
*rctx
)
2850 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2858 int num_ps_stack_entries
;
2859 int num_vs_stack_entries
;
2860 int num_gs_stack_entries
;
2861 int num_es_stack_entries
;
2862 int num_hs_stack_entries
;
2863 int num_ls_stack_entries
;
2864 enum radeon_family family
;
2867 if (rctx
->chip_class
== CAYMAN
) {
2868 cayman_init_atom_start_cs(rctx
);
2872 r600_init_command_buffer(cb
, 256);
2874 /* This must be first. */
2875 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2876 r600_store_value(cb
, 0x80000000);
2877 r600_store_value(cb
, 0x80000000);
2879 /* We're setting config registers here. */
2880 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2881 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2883 evergreen_init_common_regs(cb
, rctx
->chip_class
,
2884 rctx
->family
, rctx
->screen
->info
.drm_minor
);
2886 family
= rctx
->family
;
2890 num_ps_threads
= 96;
2891 num_vs_threads
= 16;
2892 num_gs_threads
= 16;
2893 num_es_threads
= 16;
2894 num_hs_threads
= 16;
2895 num_ls_threads
= 16;
2896 num_ps_stack_entries
= 42;
2897 num_vs_stack_entries
= 42;
2898 num_gs_stack_entries
= 42;
2899 num_es_stack_entries
= 42;
2900 num_hs_stack_entries
= 42;
2901 num_ls_stack_entries
= 42;
2904 num_ps_threads
= 128;
2905 num_vs_threads
= 20;
2906 num_gs_threads
= 20;
2907 num_es_threads
= 20;
2908 num_hs_threads
= 20;
2909 num_ls_threads
= 20;
2910 num_ps_stack_entries
= 42;
2911 num_vs_stack_entries
= 42;
2912 num_gs_stack_entries
= 42;
2913 num_es_stack_entries
= 42;
2914 num_hs_stack_entries
= 42;
2915 num_ls_stack_entries
= 42;
2918 num_ps_threads
= 128;
2919 num_vs_threads
= 20;
2920 num_gs_threads
= 20;
2921 num_es_threads
= 20;
2922 num_hs_threads
= 20;
2923 num_ls_threads
= 20;
2924 num_ps_stack_entries
= 85;
2925 num_vs_stack_entries
= 85;
2926 num_gs_stack_entries
= 85;
2927 num_es_stack_entries
= 85;
2928 num_hs_stack_entries
= 85;
2929 num_ls_stack_entries
= 85;
2933 num_ps_threads
= 128;
2934 num_vs_threads
= 20;
2935 num_gs_threads
= 20;
2936 num_es_threads
= 20;
2937 num_hs_threads
= 20;
2938 num_ls_threads
= 20;
2939 num_ps_stack_entries
= 85;
2940 num_vs_stack_entries
= 85;
2941 num_gs_stack_entries
= 85;
2942 num_es_stack_entries
= 85;
2943 num_hs_stack_entries
= 85;
2944 num_ls_stack_entries
= 85;
2947 num_ps_threads
= 96;
2948 num_vs_threads
= 16;
2949 num_gs_threads
= 16;
2950 num_es_threads
= 16;
2951 num_hs_threads
= 16;
2952 num_ls_threads
= 16;
2953 num_ps_stack_entries
= 42;
2954 num_vs_stack_entries
= 42;
2955 num_gs_stack_entries
= 42;
2956 num_es_stack_entries
= 42;
2957 num_hs_stack_entries
= 42;
2958 num_ls_stack_entries
= 42;
2961 num_ps_threads
= 96;
2962 num_vs_threads
= 25;
2963 num_gs_threads
= 25;
2964 num_es_threads
= 25;
2965 num_hs_threads
= 25;
2966 num_ls_threads
= 25;
2967 num_ps_stack_entries
= 42;
2968 num_vs_stack_entries
= 42;
2969 num_gs_stack_entries
= 42;
2970 num_es_stack_entries
= 42;
2971 num_hs_stack_entries
= 42;
2972 num_ls_stack_entries
= 42;
2975 num_ps_threads
= 96;
2976 num_vs_threads
= 25;
2977 num_gs_threads
= 25;
2978 num_es_threads
= 25;
2979 num_hs_threads
= 25;
2980 num_ls_threads
= 25;
2981 num_ps_stack_entries
= 85;
2982 num_vs_stack_entries
= 85;
2983 num_gs_stack_entries
= 85;
2984 num_es_stack_entries
= 85;
2985 num_hs_stack_entries
= 85;
2986 num_ls_stack_entries
= 85;
2989 num_ps_threads
= 128;
2990 num_vs_threads
= 20;
2991 num_gs_threads
= 20;
2992 num_es_threads
= 20;
2993 num_hs_threads
= 20;
2994 num_ls_threads
= 20;
2995 num_ps_stack_entries
= 85;
2996 num_vs_stack_entries
= 85;
2997 num_gs_stack_entries
= 85;
2998 num_es_stack_entries
= 85;
2999 num_hs_stack_entries
= 85;
3000 num_ls_stack_entries
= 85;
3003 num_ps_threads
= 128;
3004 num_vs_threads
= 20;
3005 num_gs_threads
= 20;
3006 num_es_threads
= 20;
3007 num_hs_threads
= 20;
3008 num_ls_threads
= 20;
3009 num_ps_stack_entries
= 42;
3010 num_vs_stack_entries
= 42;
3011 num_gs_stack_entries
= 42;
3012 num_es_stack_entries
= 42;
3013 num_hs_stack_entries
= 42;
3014 num_ls_stack_entries
= 42;
3017 num_ps_threads
= 128;
3018 num_vs_threads
= 10;
3019 num_gs_threads
= 10;
3020 num_es_threads
= 10;
3021 num_hs_threads
= 10;
3022 num_ls_threads
= 10;
3023 num_ps_stack_entries
= 42;
3024 num_vs_stack_entries
= 42;
3025 num_gs_stack_entries
= 42;
3026 num_es_stack_entries
= 42;
3027 num_hs_stack_entries
= 42;
3028 num_ls_stack_entries
= 42;
3032 tmp
= S_008C18_NUM_PS_THREADS(num_ps_threads
);
3033 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
3034 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
3035 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
3037 r600_store_config_reg_seq(cb
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, 5);
3038 r600_store_value(cb
, tmp
); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3040 tmp
= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
3041 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
3042 r600_store_value(cb
, tmp
); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3044 tmp
= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
3045 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
3046 r600_store_value(cb
, tmp
); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3048 tmp
= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
3049 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
3050 r600_store_value(cb
, tmp
); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3052 tmp
= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
3053 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
3054 r600_store_value(cb
, tmp
); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3056 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
3057 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
3059 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
3060 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3061 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3062 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3063 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3064 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3065 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3067 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
3068 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3069 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3070 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3071 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3073 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
3074 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3075 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
3076 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3077 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3078 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3079 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3080 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3081 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
3082 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3083 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3084 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3085 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3086 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
3088 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
3089 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
3090 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
3092 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
3094 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
3096 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
3097 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3098 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
3100 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
3102 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
3104 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
3105 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
3106 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
3108 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
3109 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
3110 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
3112 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
3113 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
3114 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
3116 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
3117 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3118 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3119 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3121 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
3122 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
3123 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
3124 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
3125 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
3127 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
3128 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3129 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3131 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
3132 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3133 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3135 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3136 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3137 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
3139 /* to avoid GPU doing any preloading of constant from random address */
3140 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
3141 r600_store_value(cb
, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
3142 r600_store_value(cb
, 0);
3143 r600_store_value(cb
, 0);
3144 r600_store_value(cb
, 0);
3145 r600_store_value(cb
, 0);
3146 r600_store_value(cb
, 0);
3147 r600_store_value(cb
, 0);
3148 r600_store_value(cb
, 0);
3149 r600_store_value(cb
, 0);
3150 r600_store_value(cb
, 0);
3151 r600_store_value(cb
, 0);
3152 r600_store_value(cb
, 0);
3153 r600_store_value(cb
, 0);
3154 r600_store_value(cb
, 0);
3155 r600_store_value(cb
, 0);
3156 r600_store_value(cb
, 0);
3158 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
3159 r600_store_value(cb
, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
3160 r600_store_value(cb
, 0);
3161 r600_store_value(cb
, 0);
3162 r600_store_value(cb
, 0);
3163 r600_store_value(cb
, 0);
3164 r600_store_value(cb
, 0);
3165 r600_store_value(cb
, 0);
3166 r600_store_value(cb
, 0);
3167 r600_store_value(cb
, 0);
3168 r600_store_value(cb
, 0);
3169 r600_store_value(cb
, 0);
3170 r600_store_value(cb
, 0);
3171 r600_store_value(cb
, 0);
3172 r600_store_value(cb
, 0);
3173 r600_store_value(cb
, 0);
3174 r600_store_value(cb
, 0);
3176 r600_store_context_reg_seq(cb
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
3177 r600_store_value(cb
, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
3178 r600_store_value(cb
, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
3180 if (rctx
->screen
->has_streamout
) {
3181 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
3184 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
3185 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
3188 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3190 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3191 struct r600_pipe_state
*rstate
= &shader
->rstate
;
3192 struct r600_shader
*rshader
= &shader
->shader
;
3193 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
3194 int pos_index
= -1, face_index
= -1;
3196 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
3197 unsigned spi_baryc_cntl
, sid
, tmp
, idx
= 0;
3198 unsigned z_export
= 0, stencil_export
= 0;
3199 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
3203 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
3204 for (i
= 0; i
< rshader
->ninput
; i
++) {
3205 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3206 POSITION goes via GPRs from the SC so isn't counted */
3207 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
3209 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
3213 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
3215 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
3216 have_perspective
= TRUE
;
3217 if (rshader
->input
[i
].centroid
)
3218 have_centroid
= TRUE
;
3221 sid
= rshader
->input
[i
].spi_sid
;
3225 tmp
= S_028644_SEMANTIC(sid
);
3227 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
3228 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3229 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
3230 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
)) {
3231 tmp
|= S_028644_FLAT_SHADE(1);
3234 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
3235 (sprite_coord_enable
& (1 << rshader
->input
[i
].sid
))) {
3236 tmp
|= S_028644_PT_SPRITE_TEX(1);
3239 r600_pipe_state_add_reg(rstate
, R_028644_SPI_PS_INPUT_CNTL_0
+ idx
* 4,
3246 for (i
= 0; i
< rshader
->noutput
; i
++) {
3247 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
3249 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
3252 if (rshader
->uses_kill
)
3253 db_shader_control
|= S_02880C_KILL_ENABLE(1);
3255 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
3256 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export
);
3259 for (i
= 0; i
< rshader
->noutput
; i
++) {
3260 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
3261 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
3265 num_cout
= rshader
->nr_ps_color_exports
;
3267 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
3269 /* always at least export 1 component per pixel */
3272 shader
->nr_ps_color_outputs
= num_cout
;
3275 have_perspective
= TRUE
;
3278 if (!have_perspective
&& !have_linear
)
3279 have_perspective
= TRUE
;
3281 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
3282 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
3283 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
3285 if (pos_index
!= -1) {
3286 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
3287 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
3288 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
3292 spi_ps_in_control_1
= 0;
3293 if (face_index
!= -1) {
3294 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
3295 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
3299 if (have_perspective
)
3300 spi_baryc_cntl
|= S_0286E0_PERSP_CENTER_ENA(1) |
3301 S_0286E0_PERSP_CENTROID_ENA(have_centroid
);
3303 spi_baryc_cntl
|= S_0286E0_LINEAR_CENTER_ENA(1) |
3304 S_0286E0_LINEAR_CENTROID_ENA(have_centroid
);
3306 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
,
3307 spi_ps_in_control_0
);
3308 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
,
3309 spi_ps_in_control_1
);
3310 r600_pipe_state_add_reg(rstate
, R_0286E4_SPI_PS_IN_CONTROL_2
,
3312 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
3313 r600_pipe_state_add_reg(rstate
,
3314 R_0286E0_SPI_BARYC_CNTL
,
3317 r600_pipe_state_add_reg_bo(rstate
,
3318 R_028840_SQ_PGM_START_PS
,
3319 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8,
3320 shader
->bo
, RADEON_USAGE_READ
);
3321 r600_pipe_state_add_reg(rstate
,
3322 R_028844_SQ_PGM_RESOURCES_PS
,
3323 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
3324 S_028844_PRIME_CACHE_ON_DRAW(1) |
3325 S_028844_STACK_SIZE(rshader
->bc
.nstack
));
3326 r600_pipe_state_add_reg(rstate
,
3327 R_02884C_SQ_PGM_EXPORTS_PS
,
3330 shader
->db_shader_control
= db_shader_control
;
3331 shader
->ps_depth_export
= z_export
| stencil_export
;
3333 shader
->sprite_coord_enable
= sprite_coord_enable
;
3334 if (rctx
->rasterizer
)
3335 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
3338 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3340 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3341 struct r600_pipe_state
*rstate
= &shader
->rstate
;
3342 struct r600_shader
*rshader
= &shader
->shader
;
3343 unsigned spi_vs_out_id
[10] = {};
3344 unsigned i
, tmp
, nparams
= 0;
3346 /* clear previous register */
3349 for (i
= 0; i
< rshader
->noutput
; i
++) {
3350 if (rshader
->output
[i
].spi_sid
) {
3351 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
3352 spi_vs_out_id
[nparams
/ 4] |= tmp
;
3357 for (i
= 0; i
< 10; i
++) {
3358 r600_pipe_state_add_reg(rstate
,
3359 R_02861C_SPI_VS_OUT_ID_0
+ i
* 4,
3363 /* Certain attributes (position, psize, etc.) don't count as params.
3364 * VS is required to export at least one param and r600_shader_from_tgsi()
3365 * takes care of adding a dummy export.
3370 r600_pipe_state_add_reg(rstate
,
3371 R_0286C4_SPI_VS_OUT_CONFIG
,
3372 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
3373 r600_pipe_state_add_reg(rstate
,
3374 R_028860_SQ_PGM_RESOURCES_VS
,
3375 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
3376 S_028860_STACK_SIZE(rshader
->bc
.nstack
));
3377 r600_pipe_state_add_reg_bo(rstate
,
3378 R_02885C_SQ_PGM_START_VS
,
3379 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8,
3380 shader
->bo
, RADEON_USAGE_READ
);
3382 shader
->pa_cl_vs_out_cntl
=
3383 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
3384 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
3385 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
3386 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
);
3389 void *evergreen_create_resolve_blend(struct r600_context
*rctx
)
3391 struct pipe_blend_state blend
;
3393 memset(&blend
, 0, sizeof(blend
));
3394 blend
.independent_blend_enable
= true;
3395 blend
.rt
[0].colormask
= 0xf;
3396 return evergreen_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_CB_RESOLVE
);
3399 void *evergreen_create_decompress_blend(struct r600_context
*rctx
)
3401 struct pipe_blend_state blend
;
3403 memset(&blend
, 0, sizeof(blend
));
3404 blend
.independent_blend_enable
= true;
3405 blend
.rt
[0].colormask
= 0xf;
3406 return evergreen_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_CB_DECOMPRESS
);
3409 void *evergreen_create_fmask_decompress_blend(struct r600_context
*rctx
)
3411 struct pipe_blend_state blend
;
3413 memset(&blend
, 0, sizeof(blend
));
3414 blend
.independent_blend_enable
= true;
3415 blend
.rt
[0].colormask
= 0xf;
3416 return evergreen_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_CB_FMASK_DECOMPRESS
);
3419 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
)
3421 struct pipe_depth_stencil_alpha_state dsa
= {{0}};
3423 return rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
3426 void evergreen_update_db_shader_control(struct r600_context
* rctx
)
3428 bool dual_export
= rctx
->framebuffer
.export_16bpc
&&
3429 !rctx
->ps_shader
->current
->ps_depth_export
;
3431 unsigned db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
3432 S_02880C_DUAL_EXPORT_ENABLE(dual_export
) |
3433 S_02880C_DB_SOURCE_FORMAT(dual_export
? V_02880C_EXPORT_DB_TWO
:
3434 V_02880C_EXPORT_DB_FULL
) |
3435 S_02880C_ALPHA_TO_MASK_DISABLE(rctx
->framebuffer
.cb0_is_integer
);
3437 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
) {
3438 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
3439 rctx
->db_misc_state
.atom
.dirty
= true;