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r600g: take constantly interpolated values into a/c
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_blitter.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
38 #include "util/u_surface.h"
39 #include "util/u_pack_color.h"
40 #include "util/u_memory.h"
41 #include "util/u_inlines.h"
42 #include "util/u_framebuffer.h"
43 #include "pipebuffer/pb_buffer.h"
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "r600_formats.h"
50
51 static uint32_t r600_translate_blend_function(int blend_func)
52 {
53 switch (blend_func) {
54 case PIPE_BLEND_ADD:
55 return V_028780_COMB_DST_PLUS_SRC;
56 case PIPE_BLEND_SUBTRACT:
57 return V_028780_COMB_SRC_MINUS_DST;
58 case PIPE_BLEND_REVERSE_SUBTRACT:
59 return V_028780_COMB_DST_MINUS_SRC;
60 case PIPE_BLEND_MIN:
61 return V_028780_COMB_MIN_DST_SRC;
62 case PIPE_BLEND_MAX:
63 return V_028780_COMB_MAX_DST_SRC;
64 default:
65 R600_ERR("Unknown blend function %d\n", blend_func);
66 assert(0);
67 break;
68 }
69 return 0;
70 }
71
72 static uint32_t r600_translate_blend_factor(int blend_fact)
73 {
74 switch (blend_fact) {
75 case PIPE_BLENDFACTOR_ONE:
76 return V_028780_BLEND_ONE;
77 case PIPE_BLENDFACTOR_SRC_COLOR:
78 return V_028780_BLEND_SRC_COLOR;
79 case PIPE_BLENDFACTOR_SRC_ALPHA:
80 return V_028780_BLEND_SRC_ALPHA;
81 case PIPE_BLENDFACTOR_DST_ALPHA:
82 return V_028780_BLEND_DST_ALPHA;
83 case PIPE_BLENDFACTOR_DST_COLOR:
84 return V_028780_BLEND_DST_COLOR;
85 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
86 return V_028780_BLEND_SRC_ALPHA_SATURATE;
87 case PIPE_BLENDFACTOR_CONST_COLOR:
88 return V_028780_BLEND_CONST_COLOR;
89 case PIPE_BLENDFACTOR_CONST_ALPHA:
90 return V_028780_BLEND_CONST_ALPHA;
91 case PIPE_BLENDFACTOR_ZERO:
92 return V_028780_BLEND_ZERO;
93 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
94 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
95 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
96 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
97 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
98 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
99 case PIPE_BLENDFACTOR_INV_DST_COLOR:
100 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
101 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
102 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
103 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
104 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
105 case PIPE_BLENDFACTOR_SRC1_COLOR:
106 return V_028780_BLEND_SRC1_COLOR;
107 case PIPE_BLENDFACTOR_SRC1_ALPHA:
108 return V_028780_BLEND_SRC1_ALPHA;
109 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
110 return V_028780_BLEND_INV_SRC1_COLOR;
111 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
112 return V_028780_BLEND_INV_SRC1_ALPHA;
113 default:
114 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
115 assert(0);
116 break;
117 }
118 return 0;
119 }
120
121 static uint32_t r600_translate_stencil_op(int s_op)
122 {
123 switch (s_op) {
124 case PIPE_STENCIL_OP_KEEP:
125 return V_028800_STENCIL_KEEP;
126 case PIPE_STENCIL_OP_ZERO:
127 return V_028800_STENCIL_ZERO;
128 case PIPE_STENCIL_OP_REPLACE:
129 return V_028800_STENCIL_REPLACE;
130 case PIPE_STENCIL_OP_INCR:
131 return V_028800_STENCIL_INCR;
132 case PIPE_STENCIL_OP_DECR:
133 return V_028800_STENCIL_DECR;
134 case PIPE_STENCIL_OP_INCR_WRAP:
135 return V_028800_STENCIL_INCR_WRAP;
136 case PIPE_STENCIL_OP_DECR_WRAP:
137 return V_028800_STENCIL_DECR_WRAP;
138 case PIPE_STENCIL_OP_INVERT:
139 return V_028800_STENCIL_INVERT;
140 default:
141 R600_ERR("Unknown stencil op %d", s_op);
142 assert(0);
143 break;
144 }
145 return 0;
146 }
147
148 static uint32_t r600_translate_fill(uint32_t func)
149 {
150 switch(func) {
151 case PIPE_POLYGON_MODE_FILL:
152 return 2;
153 case PIPE_POLYGON_MODE_LINE:
154 return 1;
155 case PIPE_POLYGON_MODE_POINT:
156 return 0;
157 default:
158 assert(0);
159 return 0;
160 }
161 }
162
163 /* translates straight */
164 static uint32_t r600_translate_ds_func(int func)
165 {
166 return func;
167 }
168
169 static unsigned r600_tex_wrap(unsigned wrap)
170 {
171 switch (wrap) {
172 default:
173 case PIPE_TEX_WRAP_REPEAT:
174 return V_03C000_SQ_TEX_WRAP;
175 case PIPE_TEX_WRAP_CLAMP:
176 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
177 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
178 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
179 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
180 return V_03C000_SQ_TEX_CLAMP_BORDER;
181 case PIPE_TEX_WRAP_MIRROR_REPEAT:
182 return V_03C000_SQ_TEX_MIRROR;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP:
184 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
186 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
187 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
188 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
189 }
190 }
191
192 static unsigned r600_tex_filter(unsigned filter)
193 {
194 switch (filter) {
195 default:
196 case PIPE_TEX_FILTER_NEAREST:
197 return V_03C000_SQ_TEX_XY_FILTER_POINT;
198 case PIPE_TEX_FILTER_LINEAR:
199 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
200 }
201 }
202
203 static unsigned r600_tex_mipfilter(unsigned filter)
204 {
205 switch (filter) {
206 case PIPE_TEX_MIPFILTER_NEAREST:
207 return V_03C000_SQ_TEX_Z_FILTER_POINT;
208 case PIPE_TEX_MIPFILTER_LINEAR:
209 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
210 default:
211 case PIPE_TEX_MIPFILTER_NONE:
212 return V_03C000_SQ_TEX_Z_FILTER_NONE;
213 }
214 }
215
216 static unsigned r600_tex_compare(unsigned compare)
217 {
218 switch (compare) {
219 default:
220 case PIPE_FUNC_NEVER:
221 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
222 case PIPE_FUNC_LESS:
223 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
224 case PIPE_FUNC_EQUAL:
225 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
226 case PIPE_FUNC_LEQUAL:
227 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
228 case PIPE_FUNC_GREATER:
229 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
230 case PIPE_FUNC_NOTEQUAL:
231 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
232 case PIPE_FUNC_GEQUAL:
233 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
234 case PIPE_FUNC_ALWAYS:
235 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
236 }
237 }
238
239 static unsigned r600_tex_dim(unsigned dim)
240 {
241 switch (dim) {
242 default:
243 case PIPE_TEXTURE_1D:
244 return V_030000_SQ_TEX_DIM_1D;
245 case PIPE_TEXTURE_1D_ARRAY:
246 return V_030000_SQ_TEX_DIM_1D_ARRAY;
247 case PIPE_TEXTURE_2D:
248 case PIPE_TEXTURE_RECT:
249 return V_030000_SQ_TEX_DIM_2D;
250 case PIPE_TEXTURE_2D_ARRAY:
251 return V_030000_SQ_TEX_DIM_2D_ARRAY;
252 case PIPE_TEXTURE_3D:
253 return V_030000_SQ_TEX_DIM_3D;
254 case PIPE_TEXTURE_CUBE:
255 return V_030000_SQ_TEX_DIM_CUBEMAP;
256 }
257 }
258
259 static uint32_t r600_translate_dbformat(enum pipe_format format)
260 {
261 switch (format) {
262 case PIPE_FORMAT_Z16_UNORM:
263 return V_028040_Z_16;
264 case PIPE_FORMAT_Z24X8_UNORM:
265 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
266 return V_028040_Z_24;
267 case PIPE_FORMAT_Z32_FLOAT:
268 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
269 return V_028040_Z_32_FLOAT;
270 default:
271 return ~0U;
272 }
273 }
274
275 static uint32_t r600_translate_colorswap(enum pipe_format format)
276 {
277 switch (format) {
278 /* 8-bit buffers. */
279 case PIPE_FORMAT_L4A4_UNORM:
280 case PIPE_FORMAT_A4R4_UNORM:
281 return V_028C70_SWAP_ALT;
282
283 case PIPE_FORMAT_A8_UNORM:
284 case PIPE_FORMAT_R4A4_UNORM:
285 return V_028C70_SWAP_ALT_REV;
286 case PIPE_FORMAT_I8_UNORM:
287 case PIPE_FORMAT_L8_UNORM:
288 case PIPE_FORMAT_L8_SRGB:
289 case PIPE_FORMAT_R8_UNORM:
290 case PIPE_FORMAT_R8_SNORM:
291 return V_028C70_SWAP_STD;
292
293 /* 16-bit buffers. */
294 case PIPE_FORMAT_B5G6R5_UNORM:
295 return V_028C70_SWAP_STD_REV;
296
297 case PIPE_FORMAT_B5G5R5A1_UNORM:
298 case PIPE_FORMAT_B5G5R5X1_UNORM:
299 return V_028C70_SWAP_ALT;
300
301 case PIPE_FORMAT_B4G4R4A4_UNORM:
302 case PIPE_FORMAT_B4G4R4X4_UNORM:
303 return V_028C70_SWAP_ALT;
304
305 case PIPE_FORMAT_Z16_UNORM:
306 return V_028C70_SWAP_STD;
307
308 case PIPE_FORMAT_L8A8_UNORM:
309 case PIPE_FORMAT_L8A8_SRGB:
310 return V_028C70_SWAP_ALT;
311 case PIPE_FORMAT_R8G8_UNORM:
312 return V_028C70_SWAP_STD;
313
314 case PIPE_FORMAT_R16_UNORM:
315 case PIPE_FORMAT_R16_FLOAT:
316 return V_028C70_SWAP_STD;
317
318 /* 32-bit buffers. */
319 case PIPE_FORMAT_A8B8G8R8_SRGB:
320 return V_028C70_SWAP_STD_REV;
321 case PIPE_FORMAT_B8G8R8A8_SRGB:
322 return V_028C70_SWAP_ALT;
323
324 case PIPE_FORMAT_B8G8R8A8_UNORM:
325 case PIPE_FORMAT_B8G8R8X8_UNORM:
326 return V_028C70_SWAP_ALT;
327
328 case PIPE_FORMAT_A8R8G8B8_UNORM:
329 case PIPE_FORMAT_X8R8G8B8_UNORM:
330 return V_028C70_SWAP_ALT_REV;
331 case PIPE_FORMAT_R8G8B8A8_SNORM:
332 case PIPE_FORMAT_R8G8B8A8_UNORM:
333 case PIPE_FORMAT_R8G8B8A8_SSCALED:
334 case PIPE_FORMAT_R8G8B8A8_USCALED:
335 case PIPE_FORMAT_R8G8B8X8_UNORM:
336 return V_028C70_SWAP_STD;
337
338 case PIPE_FORMAT_A8B8G8R8_UNORM:
339 case PIPE_FORMAT_X8B8G8R8_UNORM:
340 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
341 return V_028C70_SWAP_STD_REV;
342
343 case PIPE_FORMAT_Z24X8_UNORM:
344 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
345 return V_028C70_SWAP_STD;
346
347 case PIPE_FORMAT_X8Z24_UNORM:
348 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
349 return V_028C70_SWAP_STD;
350
351 case PIPE_FORMAT_R10G10B10A2_UNORM:
352 case PIPE_FORMAT_R10G10B10X2_SNORM:
353 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
354 return V_028C70_SWAP_STD;
355
356 case PIPE_FORMAT_B10G10R10A2_UNORM:
357 return V_028C70_SWAP_ALT;
358
359 case PIPE_FORMAT_R11G11B10_FLOAT:
360 case PIPE_FORMAT_R32_FLOAT:
361 case PIPE_FORMAT_Z32_FLOAT:
362 case PIPE_FORMAT_R16G16_FLOAT:
363 case PIPE_FORMAT_R16G16_UNORM:
364 return V_028C70_SWAP_STD;
365
366 /* 64-bit buffers. */
367 case PIPE_FORMAT_R32G32_FLOAT:
368 case PIPE_FORMAT_R16G16B16A16_UNORM:
369 case PIPE_FORMAT_R16G16B16A16_SNORM:
370 case PIPE_FORMAT_R16G16B16A16_USCALED:
371 case PIPE_FORMAT_R16G16B16A16_SSCALED:
372 case PIPE_FORMAT_R16G16B16A16_FLOAT:
373 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
374
375 /* 128-bit buffers. */
376 case PIPE_FORMAT_R32G32B32A32_FLOAT:
377 case PIPE_FORMAT_R32G32B32A32_SNORM:
378 case PIPE_FORMAT_R32G32B32A32_UNORM:
379 case PIPE_FORMAT_R32G32B32A32_SSCALED:
380 case PIPE_FORMAT_R32G32B32A32_USCALED:
381 return V_028C70_SWAP_STD;
382 default:
383 R600_ERR("unsupported colorswap format %d\n", format);
384 return ~0U;
385 }
386 return ~0U;
387 }
388
389 static uint32_t r600_translate_colorformat(enum pipe_format format)
390 {
391 switch (format) {
392 /* 8-bit buffers. */
393 case PIPE_FORMAT_L4A4_UNORM:
394 case PIPE_FORMAT_R4A4_UNORM:
395 case PIPE_FORMAT_A4R4_UNORM:
396 return V_028C70_COLOR_4_4;
397
398 case PIPE_FORMAT_A8_UNORM:
399 case PIPE_FORMAT_I8_UNORM:
400 case PIPE_FORMAT_L8_UNORM:
401 case PIPE_FORMAT_L8_SRGB:
402 case PIPE_FORMAT_R8_UNORM:
403 case PIPE_FORMAT_R8_SNORM:
404 return V_028C70_COLOR_8;
405
406 /* 16-bit buffers. */
407 case PIPE_FORMAT_B5G6R5_UNORM:
408 return V_028C70_COLOR_5_6_5;
409
410 case PIPE_FORMAT_B5G5R5A1_UNORM:
411 case PIPE_FORMAT_B5G5R5X1_UNORM:
412 return V_028C70_COLOR_1_5_5_5;
413
414 case PIPE_FORMAT_B4G4R4A4_UNORM:
415 case PIPE_FORMAT_B4G4R4X4_UNORM:
416 return V_028C70_COLOR_4_4_4_4;
417
418 case PIPE_FORMAT_Z16_UNORM:
419 return V_028C70_COLOR_16;
420
421 case PIPE_FORMAT_L8A8_UNORM:
422 case PIPE_FORMAT_L8A8_SRGB:
423 case PIPE_FORMAT_R8G8_UNORM:
424 return V_028C70_COLOR_8_8;
425
426 case PIPE_FORMAT_R16_UNORM:
427 return V_028C70_COLOR_16;
428
429 case PIPE_FORMAT_R16_FLOAT:
430 return V_028C70_COLOR_16_FLOAT;
431
432 /* 32-bit buffers. */
433 case PIPE_FORMAT_A8B8G8R8_SRGB:
434 case PIPE_FORMAT_A8B8G8R8_UNORM:
435 case PIPE_FORMAT_A8R8G8B8_UNORM:
436 case PIPE_FORMAT_B8G8R8A8_SRGB:
437 case PIPE_FORMAT_B8G8R8A8_UNORM:
438 case PIPE_FORMAT_B8G8R8X8_UNORM:
439 case PIPE_FORMAT_R8G8B8A8_SNORM:
440 case PIPE_FORMAT_R8G8B8A8_UNORM:
441 case PIPE_FORMAT_R8G8B8X8_UNORM:
442 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
443 case PIPE_FORMAT_X8B8G8R8_UNORM:
444 case PIPE_FORMAT_X8R8G8B8_UNORM:
445 case PIPE_FORMAT_R8G8B8_UNORM:
446 case PIPE_FORMAT_R8G8B8A8_SSCALED:
447 case PIPE_FORMAT_R8G8B8A8_USCALED:
448 return V_028C70_COLOR_8_8_8_8;
449
450 case PIPE_FORMAT_R10G10B10A2_UNORM:
451 case PIPE_FORMAT_R10G10B10X2_SNORM:
452 case PIPE_FORMAT_B10G10R10A2_UNORM:
453 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
454 return V_028C70_COLOR_2_10_10_10;
455
456 case PIPE_FORMAT_Z24X8_UNORM:
457 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
458 return V_028C70_COLOR_8_24;
459
460 case PIPE_FORMAT_X8Z24_UNORM:
461 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
462 return V_028C70_COLOR_24_8;
463
464 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
465 return V_028C70_COLOR_X24_8_32_FLOAT;
466
467 case PIPE_FORMAT_R32_FLOAT:
468 case PIPE_FORMAT_Z32_FLOAT:
469 return V_028C70_COLOR_32_FLOAT;
470
471 case PIPE_FORMAT_R16G16_FLOAT:
472 return V_028C70_COLOR_16_16_FLOAT;
473
474 case PIPE_FORMAT_R16G16_SSCALED:
475 case PIPE_FORMAT_R16G16_UNORM:
476 return V_028C70_COLOR_16_16;
477
478 case PIPE_FORMAT_R11G11B10_FLOAT:
479 return V_028C70_COLOR_10_11_11_FLOAT;
480
481 /* 64-bit buffers. */
482 case PIPE_FORMAT_R16G16B16_USCALED:
483 case PIPE_FORMAT_R16G16B16_SSCALED:
484 case PIPE_FORMAT_R16G16B16A16_USCALED:
485 case PIPE_FORMAT_R16G16B16A16_SSCALED:
486 case PIPE_FORMAT_R16G16B16A16_UNORM:
487 case PIPE_FORMAT_R16G16B16A16_SNORM:
488 return V_028C70_COLOR_16_16_16_16;
489
490 case PIPE_FORMAT_R16G16B16_FLOAT:
491 case PIPE_FORMAT_R16G16B16A16_FLOAT:
492 return V_028C70_COLOR_16_16_16_16_FLOAT;
493
494 case PIPE_FORMAT_R32G32_FLOAT:
495 return V_028C70_COLOR_32_32_FLOAT;
496
497 case PIPE_FORMAT_R32G32_USCALED:
498 case PIPE_FORMAT_R32G32_SSCALED:
499 return V_028C70_COLOR_32_32;
500
501 /* 96-bit buffers. */
502 case PIPE_FORMAT_R32G32B32_FLOAT:
503 return V_028C70_COLOR_32_32_32_FLOAT;
504
505 /* 128-bit buffers. */
506 case PIPE_FORMAT_R32G32B32A32_SNORM:
507 case PIPE_FORMAT_R32G32B32A32_UNORM:
508 case PIPE_FORMAT_R32G32B32A32_SSCALED:
509 case PIPE_FORMAT_R32G32B32A32_USCALED:
510 return V_028C70_COLOR_32_32_32_32;
511 case PIPE_FORMAT_R32G32B32A32_FLOAT:
512 return V_028C70_COLOR_32_32_32_32_FLOAT;
513
514 /* YUV buffers. */
515 case PIPE_FORMAT_UYVY:
516 case PIPE_FORMAT_YUYV:
517 default:
518 return ~0U; /* Unsupported. */
519 }
520 }
521
522 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
523 {
524 if (R600_BIG_ENDIAN) {
525 switch(colorformat) {
526 case V_028C70_COLOR_4_4:
527 return ENDIAN_NONE;
528
529 /* 8-bit buffers. */
530 case V_028C70_COLOR_8:
531 return ENDIAN_NONE;
532
533 /* 16-bit buffers. */
534 case V_028C70_COLOR_5_6_5:
535 case V_028C70_COLOR_1_5_5_5:
536 case V_028C70_COLOR_4_4_4_4:
537 case V_028C70_COLOR_16:
538 case V_028C70_COLOR_8_8:
539 return ENDIAN_8IN16;
540
541 /* 32-bit buffers. */
542 case V_028C70_COLOR_8_8_8_8:
543 case V_028C70_COLOR_2_10_10_10:
544 case V_028C70_COLOR_8_24:
545 case V_028C70_COLOR_24_8:
546 case V_028C70_COLOR_32_FLOAT:
547 case V_028C70_COLOR_16_16_FLOAT:
548 case V_028C70_COLOR_16_16:
549 return ENDIAN_8IN32;
550
551 /* 64-bit buffers. */
552 case V_028C70_COLOR_16_16_16_16:
553 case V_028C70_COLOR_16_16_16_16_FLOAT:
554 return ENDIAN_8IN16;
555
556 case V_028C70_COLOR_32_32_FLOAT:
557 case V_028C70_COLOR_32_32:
558 case V_028C70_COLOR_X24_8_32_FLOAT:
559 return ENDIAN_8IN32;
560
561 /* 96-bit buffers. */
562 case V_028C70_COLOR_32_32_32_FLOAT:
563 /* 128-bit buffers. */
564 case V_028C70_COLOR_32_32_32_32_FLOAT:
565 case V_028C70_COLOR_32_32_32_32:
566 return ENDIAN_8IN32;
567 default:
568 return ENDIAN_NONE; /* Unsupported. */
569 }
570 } else {
571 return ENDIAN_NONE;
572 }
573 }
574
575 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
576 {
577 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
578 }
579
580 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
581 {
582 return r600_translate_colorformat(format) != ~0U &&
583 r600_translate_colorswap(format) != ~0U;
584 }
585
586 static bool r600_is_zs_format_supported(enum pipe_format format)
587 {
588 return r600_translate_dbformat(format) != ~0U;
589 }
590
591 boolean evergreen_is_format_supported(struct pipe_screen *screen,
592 enum pipe_format format,
593 enum pipe_texture_target target,
594 unsigned sample_count,
595 unsigned usage)
596 {
597 unsigned retval = 0;
598
599 if (target >= PIPE_MAX_TEXTURE_TYPES) {
600 R600_ERR("r600: unsupported texture type %d\n", target);
601 return FALSE;
602 }
603
604 if (!util_format_is_supported(format, usage))
605 return FALSE;
606
607 /* Multisample */
608 if (sample_count > 1)
609 return FALSE;
610
611 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
612 r600_is_sampler_format_supported(screen, format)) {
613 retval |= PIPE_BIND_SAMPLER_VIEW;
614 }
615
616 if ((usage & (PIPE_BIND_RENDER_TARGET |
617 PIPE_BIND_DISPLAY_TARGET |
618 PIPE_BIND_SCANOUT |
619 PIPE_BIND_SHARED)) &&
620 r600_is_colorbuffer_format_supported(format)) {
621 retval |= usage &
622 (PIPE_BIND_RENDER_TARGET |
623 PIPE_BIND_DISPLAY_TARGET |
624 PIPE_BIND_SCANOUT |
625 PIPE_BIND_SHARED);
626 }
627
628 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
629 r600_is_zs_format_supported(format)) {
630 retval |= PIPE_BIND_DEPTH_STENCIL;
631 }
632
633 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
634 r600_is_vertex_format_supported(format)) {
635 retval |= PIPE_BIND_VERTEX_BUFFER;
636 }
637
638 if (usage & PIPE_BIND_TRANSFER_READ)
639 retval |= PIPE_BIND_TRANSFER_READ;
640 if (usage & PIPE_BIND_TRANSFER_WRITE)
641 retval |= PIPE_BIND_TRANSFER_WRITE;
642
643 return retval == usage;
644 }
645
646 static void evergreen_set_blend_color(struct pipe_context *ctx,
647 const struct pipe_blend_color *state)
648 {
649 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
650 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
651
652 if (rstate == NULL)
653 return;
654
655 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
656 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL, 0);
657 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL, 0);
658 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL, 0);
659 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL, 0);
660
661 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
662 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
663 r600_context_pipe_state_set(&rctx->ctx, rstate);
664 }
665
666 static void *evergreen_create_blend_state(struct pipe_context *ctx,
667 const struct pipe_blend_state *state)
668 {
669 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
670 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
671 struct r600_pipe_state *rstate;
672 u32 color_control, target_mask;
673 /* FIXME there is more then 8 framebuffer */
674 unsigned blend_cntl[8];
675
676 if (blend == NULL) {
677 return NULL;
678 }
679
680 rstate = &blend->rstate;
681
682 rstate->id = R600_PIPE_STATE_BLEND;
683
684 target_mask = 0;
685 color_control = S_028808_MODE(1);
686 if (state->logicop_enable) {
687 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
688 } else {
689 color_control |= (0xcc << 16);
690 }
691 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
692 if (state->independent_blend_enable) {
693 for (int i = 0; i < 8; i++) {
694 target_mask |= (state->rt[i].colormask << (4 * i));
695 }
696 } else {
697 for (int i = 0; i < 8; i++) {
698 target_mask |= (state->rt[0].colormask << (4 * i));
699 }
700 }
701 blend->cb_target_mask = target_mask;
702
703 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
704 color_control, 0xFFFFFFFD, NULL, 0);
705
706 if (rctx->chip_class != CAYMAN)
707 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
708 else {
709 r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
710 r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
711 }
712
713 for (int i = 0; i < 8; i++) {
714 /* state->rt entries > 0 only written if independent blending */
715 const int j = state->independent_blend_enable ? i : 0;
716
717 unsigned eqRGB = state->rt[j].rgb_func;
718 unsigned srcRGB = state->rt[j].rgb_src_factor;
719 unsigned dstRGB = state->rt[j].rgb_dst_factor;
720 unsigned eqA = state->rt[j].alpha_func;
721 unsigned srcA = state->rt[j].alpha_src_factor;
722 unsigned dstA = state->rt[j].alpha_dst_factor;
723
724 blend_cntl[i] = 0;
725 if (!state->rt[j].blend_enable)
726 continue;
727
728 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
729 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
730 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
731 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
732
733 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
734 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
735 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
736 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
737 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
738 }
739 }
740 for (int i = 0; i < 8; i++) {
741 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL, 0);
742 }
743
744 return rstate;
745 }
746
747 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
748 const struct pipe_depth_stencil_alpha_state *state)
749 {
750 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
751 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
752 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
753 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
754 struct r600_pipe_state *rstate;
755
756 if (dsa == NULL) {
757 return NULL;
758 }
759
760 rstate = &dsa->rstate;
761
762 rstate->id = R600_PIPE_STATE_DSA;
763 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
764 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
765 stencil_ref_mask = 0;
766 stencil_ref_mask_bf = 0;
767 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
768 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
769 S_028800_ZFUNC(state->depth.func);
770
771 /* stencil */
772 if (state->stencil[0].enabled) {
773 db_depth_control |= S_028800_STENCIL_ENABLE(1);
774 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
775 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
776 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
777 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
778
779
780 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
781 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
782 if (state->stencil[1].enabled) {
783 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
784 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
785 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
786 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
787 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
788 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
789 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
790 }
791 }
792
793 /* alpha */
794 alpha_test_control = 0;
795 alpha_ref = 0;
796 if (state->alpha.enabled) {
797 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
798 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
799 alpha_ref = fui(state->alpha.ref_value);
800 }
801 dsa->alpha_ref = alpha_ref;
802
803 /* misc */
804 db_render_control = 0;
805 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
806 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
807 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
808 /* TODO db_render_override depends on query */
809 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
810 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
811 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
812 r600_pipe_state_add_reg(rstate,
813 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
814 0xFFFFFFFF & C_028430_STENCILREF, NULL, 0);
815 r600_pipe_state_add_reg(rstate,
816 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
817 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL, 0);
818 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
819 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL, 0);
820 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
821 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
822 * evergreen_pipe_shader_ps().*/
823 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL, 0);
824 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL, 0);
825 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL, 0);
826 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL, 0);
827 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL, 0);
828 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL, 0);
829 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL, 0);
830
831 return rstate;
832 }
833
834 static void *evergreen_create_rs_state(struct pipe_context *ctx,
835 const struct pipe_rasterizer_state *state)
836 {
837 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
838 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
839 struct r600_pipe_state *rstate;
840 unsigned tmp;
841 unsigned prov_vtx = 1, polygon_dual_mode;
842 unsigned clip_rule;
843
844 if (rs == NULL) {
845 return NULL;
846 }
847
848 rstate = &rs->rstate;
849 rs->clamp_vertex_color = state->clamp_vertex_color;
850 rs->clamp_fragment_color = state->clamp_fragment_color;
851 rs->flatshade = state->flatshade;
852 rs->sprite_coord_enable = state->sprite_coord_enable;
853
854 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
855
856 /* offset */
857 rs->offset_units = state->offset_units;
858 rs->offset_scale = state->offset_scale * 12.0f;
859
860 rstate->id = R600_PIPE_STATE_RASTERIZER;
861 if (state->flatshade_first)
862 prov_vtx = 0;
863 tmp = S_0286D4_FLAT_SHADE_ENA(1);
864 if (state->sprite_coord_enable) {
865 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
866 S_0286D4_PNT_SPRITE_OVRD_X(2) |
867 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
868 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
869 S_0286D4_PNT_SPRITE_OVRD_W(1);
870 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
871 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
872 }
873 }
874 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL, 0);
875
876 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
877 state->fill_back != PIPE_POLYGON_MODE_FILL);
878 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
879 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
880 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
881 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
882 S_028814_FACE(!state->front_ccw) |
883 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
884 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
885 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
886 S_028814_POLY_MODE(polygon_dual_mode) |
887 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
888 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL, 0);
889 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
890 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
891 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL, 0);
892 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
893 /* point size 12.4 fixed point */
894 tmp = (unsigned)(state->point_size * 8.0);
895 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
896 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL, 0);
897
898 tmp = (unsigned)state->line_width * 8;
899 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
900
901 if (rctx->chip_class == CAYMAN) {
902 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
903 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
904 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
905 0xFFFFFFFF, NULL, 0);
906 r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
907 r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
908 r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
909 r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
910
911
912 } else {
913 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
914
915 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
916 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
917 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
918 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
919
920 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
921 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
922 0xFFFFFFFF, NULL, 0);
923 }
924 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL, 0);
925 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0);
926 return rstate;
927 }
928
929 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
930 const struct pipe_sampler_state *state)
931 {
932 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
933 union util_color uc;
934 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
935
936 if (rstate == NULL) {
937 return NULL;
938 }
939
940 rstate->id = R600_PIPE_STATE_SAMPLER;
941 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
942 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
943 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
944 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
945 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
946 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
947 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
948 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
949 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
950 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
951 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL, 0);
952 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
953 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
954 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
955 0xFFFFFFFF, NULL, 0);
956 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
957 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
958 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
959 S_03C008_TYPE(1),
960 0xFFFFFFFF, NULL, 0);
961
962 if (uc.ui) {
963 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL, 0);
964 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL, 0);
965 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL, 0);
966 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL, 0);
967 }
968 return rstate;
969 }
970
971 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
972 struct pipe_resource *texture,
973 const struct pipe_sampler_view *state)
974 {
975 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
976 struct r600_pipe_resource_state *rstate;
977 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
978 struct r600_resource *rbuffer;
979 unsigned format, endian;
980 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
981 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
982 struct r600_bo *bo[2];
983 unsigned height, depth;
984
985 if (view == NULL)
986 return NULL;
987 rstate = &view->state;
988
989 /* initialize base object */
990 view->base = *state;
991 view->base.texture = NULL;
992 pipe_reference(NULL, &texture->reference);
993 view->base.texture = texture;
994 view->base.reference.count = 1;
995 view->base.context = ctx;
996
997 swizzle[0] = state->swizzle_r;
998 swizzle[1] = state->swizzle_g;
999 swizzle[2] = state->swizzle_b;
1000 swizzle[3] = state->swizzle_a;
1001
1002 format = r600_translate_texformat(ctx->screen, state->format,
1003 swizzle,
1004 &word4, &yuv_format);
1005 if (format == ~0) {
1006 format = 0;
1007 }
1008
1009 if (tmp->depth && !tmp->is_flushing_texture) {
1010 r600_texture_depth_flush(ctx, texture, TRUE);
1011 tmp = tmp->flushed_depth_texture;
1012 }
1013
1014 endian = r600_colorformat_endian_swap(format);
1015
1016 if (tmp->force_int_type) {
1017 word4 &= C_030010_NUM_FORMAT_ALL;
1018 word4 |= S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_INT);
1019 }
1020
1021 rbuffer = &tmp->resource;
1022 bo[0] = rbuffer->bo;
1023 bo[1] = rbuffer->bo;
1024
1025 height = texture->height0;
1026 depth = texture->depth0;
1027
1028 pitch = align(tmp->pitch_in_blocks[0] *
1029 util_format_get_blockwidth(state->format), 8);
1030 array_mode = tmp->array_mode[0];
1031 tile_type = tmp->tile_type;
1032
1033 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1034 height = 1;
1035 depth = texture->array_size;
1036 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1037 depth = texture->array_size;
1038 }
1039
1040 rstate->bo[0] = bo[0];
1041 rstate->bo[1] = bo[1];
1042 rstate->bo_usage[0] = RADEON_USAGE_READ;
1043 rstate->bo_usage[1] = RADEON_USAGE_READ;
1044
1045 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1046 S_030000_PITCH((pitch / 8) - 1) |
1047 S_030000_NON_DISP_TILING_ORDER(tile_type) |
1048 S_030000_TEX_WIDTH(texture->width0 - 1));
1049 rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1050 S_030004_TEX_DEPTH(depth - 1) |
1051 S_030004_ARRAY_MODE(array_mode));
1052 rstate->val[2] = tmp->offset[0] >> 8;
1053 rstate->val[3] = tmp->offset[1] >> 8;
1054 rstate->val[4] = (word4 |
1055 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1056 S_030010_ENDIAN_SWAP(endian) |
1057 S_030010_BASE_LEVEL(state->u.tex.first_level));
1058 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1059 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1060 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1061 rstate->val[6] = (S_030018_MAX_ANISO(4 /* max 16 samples */));
1062 rstate->val[7] = (S_03001C_DATA_FORMAT(format) |
1063 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE));
1064
1065 return &view->base;
1066 }
1067
1068 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1069 struct pipe_sampler_view **views)
1070 {
1071 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1072 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1073
1074 for (int i = 0; i < count; i++) {
1075 if (resource[i]) {
1076 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
1077 i + R600_MAX_CONST_BUFFERS);
1078 }
1079 }
1080 }
1081
1082 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1083 struct pipe_sampler_view **views)
1084 {
1085 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1086 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1087 int i;
1088 int has_depth = 0;
1089
1090 for (i = 0; i < count; i++) {
1091 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1092 if (resource[i]) {
1093 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1094 has_depth = 1;
1095 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
1096 i + R600_MAX_CONST_BUFFERS);
1097 } else
1098 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1099 i + R600_MAX_CONST_BUFFERS);
1100
1101 pipe_sampler_view_reference(
1102 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1103 views[i]);
1104 } else {
1105 if (resource[i]) {
1106 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1107 has_depth = 1;
1108 }
1109 }
1110 }
1111 for (i = count; i < NUM_TEX_UNITS; i++) {
1112 if (rctx->ps_samplers.views[i]) {
1113 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1114 i + R600_MAX_CONST_BUFFERS);
1115 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1116 }
1117 }
1118 rctx->have_depth_texture = has_depth;
1119 rctx->ps_samplers.n_views = count;
1120 }
1121
1122 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1123 {
1124 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1125 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1126
1127
1128 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1129 rctx->ps_samplers.n_samplers = count;
1130
1131 for (int i = 0; i < count; i++) {
1132 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
1133 }
1134 }
1135
1136 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1137 {
1138 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1139 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1140
1141 for (int i = 0; i < count; i++) {
1142 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
1143 }
1144 }
1145
1146 static void evergreen_set_clip_state(struct pipe_context *ctx,
1147 const struct pipe_clip_state *state)
1148 {
1149 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1150 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1151
1152 if (rstate == NULL)
1153 return;
1154
1155 rctx->clip = *state;
1156 rstate->id = R600_PIPE_STATE_CLIP;
1157 for (int i = 0; i < state->nr; i++) {
1158 r600_pipe_state_add_reg(rstate,
1159 R_0285BC_PA_CL_UCP0_X + i * 16,
1160 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL, 0);
1161 r600_pipe_state_add_reg(rstate,
1162 R_0285C0_PA_CL_UCP0_Y + i * 16,
1163 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL, 0);
1164 r600_pipe_state_add_reg(rstate,
1165 R_0285C4_PA_CL_UCP0_Z + i * 16,
1166 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL, 0);
1167 r600_pipe_state_add_reg(rstate,
1168 R_0285C8_PA_CL_UCP0_W + i * 16,
1169 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL, 0);
1170 }
1171 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1172 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
1173 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
1174 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL, 0);
1175
1176 free(rctx->states[R600_PIPE_STATE_CLIP]);
1177 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1178 r600_context_pipe_state_set(&rctx->ctx, rstate);
1179 }
1180
1181 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1182 const struct pipe_poly_stipple *state)
1183 {
1184 }
1185
1186 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1187 {
1188 }
1189
1190 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1191 const struct pipe_scissor_state *state)
1192 {
1193 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1194 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1195 u32 tl, br;
1196
1197 if (rstate == NULL)
1198 return;
1199
1200 rstate->id = R600_PIPE_STATE_SCISSOR;
1201 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1202 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1203 r600_pipe_state_add_reg(rstate,
1204 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1205 0xFFFFFFFF, NULL, 0);
1206 r600_pipe_state_add_reg(rstate,
1207 R_028214_PA_SC_CLIPRECT_0_BR, br,
1208 0xFFFFFFFF, NULL, 0);
1209 r600_pipe_state_add_reg(rstate,
1210 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1211 0xFFFFFFFF, NULL, 0);
1212 r600_pipe_state_add_reg(rstate,
1213 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1214 0xFFFFFFFF, NULL, 0);
1215 r600_pipe_state_add_reg(rstate,
1216 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1217 0xFFFFFFFF, NULL, 0);
1218 r600_pipe_state_add_reg(rstate,
1219 R_028224_PA_SC_CLIPRECT_2_BR, br,
1220 0xFFFFFFFF, NULL, 0);
1221 r600_pipe_state_add_reg(rstate,
1222 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1223 0xFFFFFFFF, NULL, 0);
1224 r600_pipe_state_add_reg(rstate,
1225 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1226 0xFFFFFFFF, NULL, 0);
1227
1228 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1229 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1230 r600_context_pipe_state_set(&rctx->ctx, rstate);
1231 }
1232
1233 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
1234 const struct pipe_stencil_ref *state)
1235 {
1236 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1237 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1238 u32 tmp;
1239
1240 if (rstate == NULL)
1241 return;
1242
1243 rctx->stencil_ref = *state;
1244 rstate->id = R600_PIPE_STATE_STENCIL_REF;
1245 tmp = S_028430_STENCILREF(state->ref_value[0]);
1246 r600_pipe_state_add_reg(rstate,
1247 R_028430_DB_STENCILREFMASK, tmp,
1248 ~C_028430_STENCILREF, NULL, 0);
1249 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1250 r600_pipe_state_add_reg(rstate,
1251 R_028434_DB_STENCILREFMASK_BF, tmp,
1252 ~C_028434_STENCILREF_BF, NULL, 0);
1253
1254 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1255 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1256 r600_context_pipe_state_set(&rctx->ctx, rstate);
1257 }
1258
1259 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1260 const struct pipe_viewport_state *state)
1261 {
1262 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1263 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1264
1265 if (rstate == NULL)
1266 return;
1267
1268 rctx->viewport = *state;
1269 rstate->id = R600_PIPE_STATE_VIEWPORT;
1270 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
1271 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1272 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL, 0);
1273 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL, 0);
1274 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL, 0);
1275 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL, 0);
1276 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL, 0);
1277 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL, 0);
1278 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL, 0);
1279
1280 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1281 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1282 r600_context_pipe_state_set(&rctx->ctx, rstate);
1283 }
1284
1285 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1286 const struct pipe_framebuffer_state *state, int cb)
1287 {
1288 struct r600_resource_texture *rtex;
1289 struct r600_resource *rbuffer;
1290 struct r600_surface *surf;
1291 unsigned level = state->cbufs[cb]->u.tex.level;
1292 unsigned pitch, slice;
1293 unsigned color_info;
1294 unsigned format, swap, ntype, endian;
1295 unsigned offset;
1296 unsigned tile_type;
1297 const struct util_format_description *desc;
1298 struct r600_bo *bo[3];
1299 int i;
1300 unsigned blend_clamp = 0, blend_bypass = 0;
1301
1302 surf = (struct r600_surface *)state->cbufs[cb];
1303 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1304
1305 if (rtex->depth)
1306 rctx->have_depth_fb = TRUE;
1307
1308 if (rtex->depth && !rtex->is_flushing_texture) {
1309 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1310 rtex = rtex->flushed_depth_texture;
1311 }
1312
1313 rbuffer = &rtex->resource;
1314 bo[0] = rbuffer->bo;
1315 bo[1] = rbuffer->bo;
1316 bo[2] = rbuffer->bo;
1317
1318 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1319 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
1320 level, state->cbufs[cb]->u.tex.first_layer);
1321 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1322 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1323 desc = util_format_description(surf->base.format);
1324 for (i = 0; i < 4; i++) {
1325 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1326 break;
1327 }
1328 }
1329 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1330 ntype = V_028C70_NUMBER_SRGB;
1331 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1332 if (desc->channel[i].normalized)
1333 ntype = V_028C70_NUMBER_SNORM;
1334 else
1335 ntype = V_028C70_NUMBER_SINT;
1336 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1337 if (desc->channel[i].normalized)
1338 ntype = V_028C70_NUMBER_UNORM;
1339 else
1340 ntype = V_028C70_NUMBER_UINT;
1341 } else
1342 ntype = V_028C70_NUMBER_UNORM;
1343
1344 format = r600_translate_colorformat(surf->base.format);
1345 swap = r600_translate_colorswap(surf->base.format);
1346 if (rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
1347 endian = ENDIAN_NONE;
1348 } else {
1349 endian = r600_colorformat_endian_swap(format);
1350 }
1351
1352 /* disable when gallium grows int textures */
1353 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
1354 ntype = V_028C70_NUMBER_UINT;
1355
1356 /* blend clamp should be set for all NORM/SRGB types */
1357 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1358 ntype == V_028C70_NUMBER_SRGB)
1359 blend_clamp = 1;
1360
1361 /* set blend bypass according to docs if SINT/UINT or
1362 8/24 COLOR variants */
1363 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1364 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1365 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1366 blend_clamp = 0;
1367 blend_bypass = 1;
1368 }
1369
1370 color_info = S_028C70_FORMAT(format) |
1371 S_028C70_COMP_SWAP(swap) |
1372 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
1373 S_028C70_BLEND_CLAMP(blend_clamp) |
1374 S_028C70_BLEND_BYPASS(blend_bypass) |
1375 S_028C70_NUMBER_TYPE(ntype) |
1376 S_028C70_ENDIAN(endian);
1377
1378 /* EXPORT_NORM is an optimzation that can be enabled for better
1379 * performance in certain cases.
1380 * EXPORT_NORM can be enabled if:
1381 * - 11-bit or smaller UNORM/SNORM/SRGB
1382 * - 16-bit or smaller FLOAT
1383 */
1384 /* FIXME: This should probably be the same for all CBs if we want
1385 * useful alpha tests. */
1386 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1387 ((desc->channel[i].size < 12 &&
1388 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1389 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1390 (desc->channel[i].size < 17 &&
1391 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1392 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1393 rctx->export_16bpc = true;
1394 } else {
1395 rctx->export_16bpc = false;
1396 }
1397 rctx->alpha_ref_dirty = true;
1398
1399 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1400 tile_type = rtex->tile_type;
1401 } else /* workaround for linear buffers */
1402 tile_type = 1;
1403
1404 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1405 r600_pipe_state_add_reg(rstate,
1406 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1407 offset >> 8, 0xFFFFFFFF, bo[0], RADEON_USAGE_READWRITE);
1408 r600_pipe_state_add_reg(rstate,
1409 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1410 0x0, 0xFFFFFFFF, NULL, 0);
1411 r600_pipe_state_add_reg(rstate,
1412 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1413 color_info, 0xFFFFFFFF, bo[0], RADEON_USAGE_READWRITE);
1414 r600_pipe_state_add_reg(rstate,
1415 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1416 S_028C64_PITCH_TILE_MAX(pitch),
1417 0xFFFFFFFF, NULL, 0);
1418 r600_pipe_state_add_reg(rstate,
1419 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1420 S_028C68_SLICE_TILE_MAX(slice),
1421 0xFFFFFFFF, NULL, 0);
1422 r600_pipe_state_add_reg(rstate,
1423 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1424 0x00000000, 0xFFFFFFFF, NULL, 0);
1425 r600_pipe_state_add_reg(rstate,
1426 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1427 S_028C74_NON_DISP_TILING_ORDER(tile_type),
1428 0xFFFFFFFF, bo[0], RADEON_USAGE_READWRITE);
1429 }
1430
1431 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1432 const struct pipe_framebuffer_state *state)
1433 {
1434 struct r600_resource_texture *rtex;
1435 struct r600_surface *surf;
1436 unsigned level, first_layer;
1437 unsigned pitch, slice, format;
1438 unsigned offset;
1439
1440 if (state->zsbuf == NULL)
1441 return;
1442
1443 surf = (struct r600_surface *)state->zsbuf;
1444 rtex = (struct r600_resource_texture*)surf->base.texture;
1445
1446 level = surf->base.u.tex.level;
1447 first_layer = surf->base.u.tex.first_layer;
1448 offset = r600_texture_get_offset(rtex, level, first_layer);
1449 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1450 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1451 format = r600_translate_dbformat(rtex->real_format);
1452
1453 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1454 offset >> 8, 0xFFFFFFFF, rtex->resource.bo, RADEON_USAGE_READWRITE);
1455 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1456 offset >> 8, 0xFFFFFFFF, rtex->resource.bo, RADEON_USAGE_READWRITE);
1457 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0);
1458
1459 if (rtex->stencil) {
1460 uint32_t stencil_offset =
1461 r600_texture_get_offset(rtex->stencil, level, first_layer);
1462
1463 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1464 stencil_offset >> 8, 0xFFFFFFFF, rtex->stencil->resource.bo, RADEON_USAGE_READWRITE);
1465 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1466 stencil_offset >> 8, 0xFFFFFFFF, rtex->stencil->resource.bo, RADEON_USAGE_READWRITE);
1467 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1468 1, 0xFFFFFFFF, rtex->stencil->resource.bo, RADEON_USAGE_READWRITE);
1469 } else {
1470 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1471 0, 0xFFFFFFFF, NULL, RADEON_USAGE_READWRITE);
1472 }
1473
1474 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
1475 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
1476 0xFFFFFFFF, rtex->resource.bo, RADEON_USAGE_READWRITE);
1477 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1478 S_028058_PITCH_TILE_MAX(pitch),
1479 0xFFFFFFFF, NULL, 0);
1480 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1481 S_02805C_SLICE_TILE_MAX(slice),
1482 0xFFFFFFFF, NULL, 0);
1483 }
1484
1485 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1486 const struct pipe_framebuffer_state *state)
1487 {
1488 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1489 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1490 u32 shader_mask, tl, br, target_mask;
1491 int tl_x, tl_y, br_x, br_y;
1492
1493 if (rstate == NULL)
1494 return;
1495
1496 evergreen_context_flush_dest_caches(&rctx->ctx);
1497 rctx->ctx.num_dest_buffers = state->nr_cbufs;
1498
1499 /* unreference old buffer and reference new one */
1500 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1501
1502 util_copy_framebuffer_state(&rctx->framebuffer, state);
1503
1504 /* build states */
1505 rctx->have_depth_fb = 0;
1506 rctx->nr_cbufs = state->nr_cbufs;
1507 for (int i = 0; i < state->nr_cbufs; i++) {
1508 evergreen_cb(rctx, rstate, state, i);
1509 }
1510 if (state->zsbuf) {
1511 evergreen_db(rctx, rstate, state);
1512 rctx->ctx.num_dest_buffers++;
1513 }
1514
1515 target_mask = 0x00000000;
1516 target_mask = 0xFFFFFFFF;
1517 shader_mask = 0;
1518 for (int i = 0; i < state->nr_cbufs; i++) {
1519 target_mask ^= 0xf << (i * 4);
1520 shader_mask |= 0xf << (i * 4);
1521 }
1522 tl_x = 0;
1523 tl_y = 0;
1524 br_x = state->width;
1525 br_y = state->height;
1526 /* EG hw workaround */
1527 if (br_x == 0)
1528 tl_x = 1;
1529 if (br_y == 0)
1530 tl_y = 1;
1531 /* cayman hw workaround */
1532 if (rctx->chip_class == CAYMAN) {
1533 if (br_x == 1 && br_y == 1)
1534 br_x = 2;
1535 }
1536 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1537 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1538
1539 r600_pipe_state_add_reg(rstate,
1540 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1541 0xFFFFFFFF, NULL, 0);
1542 r600_pipe_state_add_reg(rstate,
1543 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1544 0xFFFFFFFF, NULL, 0);
1545 r600_pipe_state_add_reg(rstate,
1546 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1547 0xFFFFFFFF, NULL, 0);
1548 r600_pipe_state_add_reg(rstate,
1549 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1550 0xFFFFFFFF, NULL, 0);
1551 r600_pipe_state_add_reg(rstate,
1552 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1553 0xFFFFFFFF, NULL, 0);
1554 r600_pipe_state_add_reg(rstate,
1555 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1556 0xFFFFFFFF, NULL, 0);
1557 r600_pipe_state_add_reg(rstate,
1558 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1559 0xFFFFFFFF, NULL, 0);
1560 r600_pipe_state_add_reg(rstate,
1561 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1562 0xFFFFFFFF, NULL, 0);
1563 r600_pipe_state_add_reg(rstate,
1564 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1565 0xFFFFFFFF, NULL, 0);
1566 r600_pipe_state_add_reg(rstate,
1567 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1568 0xFFFFFFFF, NULL, 0);
1569
1570 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1571 0x00000000, target_mask, NULL, 0);
1572 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1573 shader_mask, 0xFFFFFFFF, NULL, 0);
1574
1575
1576 if (rctx->chip_class == CAYMAN) {
1577 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1578 0x00000000, 0xFFFFFFFF, NULL, 0);
1579 } else {
1580 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1581 0x00000000, 0xFFFFFFFF, NULL, 0);
1582 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1583 0x00000000, 0xFFFFFFFF, NULL, 0);
1584 }
1585
1586 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1587 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1588 r600_context_pipe_state_set(&rctx->ctx, rstate);
1589
1590 if (state->zsbuf) {
1591 evergreen_polygon_offset_update(rctx);
1592 }
1593 }
1594
1595 static void evergreen_texture_barrier(struct pipe_context *ctx)
1596 {
1597 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1598
1599 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1600 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1601 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1602 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1603 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
1604 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
1605 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
1606 }
1607
1608 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
1609 {
1610 rctx->context.create_blend_state = evergreen_create_blend_state;
1611 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1612 rctx->context.create_fs_state = r600_create_shader_state;
1613 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1614 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1615 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1616 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1617 rctx->context.create_vs_state = r600_create_shader_state;
1618 rctx->context.bind_blend_state = r600_bind_blend_state;
1619 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1620 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1621 rctx->context.bind_fs_state = r600_bind_ps_shader;
1622 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1623 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1624 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1625 rctx->context.bind_vs_state = r600_bind_vs_shader;
1626 rctx->context.delete_blend_state = r600_delete_state;
1627 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1628 rctx->context.delete_fs_state = r600_delete_ps_shader;
1629 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1630 rctx->context.delete_sampler_state = r600_delete_state;
1631 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1632 rctx->context.delete_vs_state = r600_delete_vs_shader;
1633 rctx->context.set_blend_color = evergreen_set_blend_color;
1634 rctx->context.set_clip_state = evergreen_set_clip_state;
1635 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1636 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1637 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1638 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1639 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1640 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1641 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1642 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1643 rctx->context.set_index_buffer = r600_set_index_buffer;
1644 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1645 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1646 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1647 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1648 rctx->context.texture_barrier = evergreen_texture_barrier;
1649 }
1650
1651 static void cayman_init_config(struct r600_pipe_context *rctx)
1652 {
1653 struct r600_pipe_state *rstate = &rctx->config;
1654 unsigned tmp;
1655
1656 tmp = 0x00000000;
1657 tmp |= S_008C00_EXPORT_SRC_C(1);
1658 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
1659
1660 /* always set the temp clauses */
1661 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), 0xFFFFFFFF, NULL, 0);
1662 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL, 0);
1663 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL, 0);
1664 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL, 0);
1665
1666 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL, 0);
1667 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL, 0);
1668
1669 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1670 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1671 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
1672 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
1673 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL, 0);
1674 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL, 0);
1675 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
1676 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
1677 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1678 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1679 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1680 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1681 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL, 0);
1682 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
1683 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
1684 r600_pipe_state_add_reg(rstate, R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), 0xFFFFFFFF, NULL, 0);
1685 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL, 0);
1686 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL, 0);
1687 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL, 0);
1688
1689 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL, 0);
1690 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL, 0);
1691 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL, 0);
1692 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL, 0);
1693 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL, 0);
1694 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL, 0);
1695 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL, 0);
1696 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL, 0);
1697 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL, 0);
1698 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL, 0);
1699 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL, 0);
1700 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL, 0);
1701 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL, 0);
1702 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL, 0);
1703 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL, 0);
1704 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL, 0);
1705 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL, 0);
1706 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL, 0);
1707 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL, 0);
1708 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL, 0);
1709 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL, 0);
1710 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL, 0);
1711 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL, 0);
1712 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL, 0);
1713 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL, 0);
1714 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL, 0);
1715 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL, 0);
1716 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL, 0);
1717 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL, 0);
1718 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL, 0);
1719 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL, 0);
1720 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL, 0);
1721
1722 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1723
1724 r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, 0xffffffff, NULL, 0);
1725 r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, 0xffffffff, NULL, 0);
1726
1727 r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, 0xFFFFFFFF, NULL, 0);
1728 r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0xFFFFFFFF, NULL, 0);
1729
1730 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, 0xFFFFFFFF, NULL, 0);
1731 r600_context_pipe_state_set(&rctx->ctx, rstate);
1732 }
1733
1734 void evergreen_init_config(struct r600_pipe_context *rctx)
1735 {
1736 struct r600_pipe_state *rstate = &rctx->config;
1737 int ps_prio;
1738 int vs_prio;
1739 int gs_prio;
1740 int es_prio;
1741 int hs_prio, cs_prio, ls_prio;
1742 int num_ps_gprs;
1743 int num_vs_gprs;
1744 int num_gs_gprs;
1745 int num_es_gprs;
1746 int num_hs_gprs;
1747 int num_ls_gprs;
1748 int num_temp_gprs;
1749 int num_ps_threads;
1750 int num_vs_threads;
1751 int num_gs_threads;
1752 int num_es_threads;
1753 int num_hs_threads;
1754 int num_ls_threads;
1755 int num_ps_stack_entries;
1756 int num_vs_stack_entries;
1757 int num_gs_stack_entries;
1758 int num_es_stack_entries;
1759 int num_hs_stack_entries;
1760 int num_ls_stack_entries;
1761 enum radeon_family family;
1762 unsigned tmp;
1763
1764 family = rctx->family;
1765
1766 if (rctx->chip_class == CAYMAN) {
1767 cayman_init_config(rctx);
1768 return;
1769 }
1770
1771 ps_prio = 0;
1772 vs_prio = 1;
1773 gs_prio = 2;
1774 es_prio = 3;
1775 hs_prio = 0;
1776 ls_prio = 0;
1777 cs_prio = 0;
1778
1779 switch (family) {
1780 case CHIP_CEDAR:
1781 default:
1782 num_ps_gprs = 93;
1783 num_vs_gprs = 46;
1784 num_temp_gprs = 4;
1785 num_gs_gprs = 31;
1786 num_es_gprs = 31;
1787 num_hs_gprs = 23;
1788 num_ls_gprs = 23;
1789 num_ps_threads = 96;
1790 num_vs_threads = 16;
1791 num_gs_threads = 16;
1792 num_es_threads = 16;
1793 num_hs_threads = 16;
1794 num_ls_threads = 16;
1795 num_ps_stack_entries = 42;
1796 num_vs_stack_entries = 42;
1797 num_gs_stack_entries = 42;
1798 num_es_stack_entries = 42;
1799 num_hs_stack_entries = 42;
1800 num_ls_stack_entries = 42;
1801 break;
1802 case CHIP_REDWOOD:
1803 num_ps_gprs = 93;
1804 num_vs_gprs = 46;
1805 num_temp_gprs = 4;
1806 num_gs_gprs = 31;
1807 num_es_gprs = 31;
1808 num_hs_gprs = 23;
1809 num_ls_gprs = 23;
1810 num_ps_threads = 128;
1811 num_vs_threads = 20;
1812 num_gs_threads = 20;
1813 num_es_threads = 20;
1814 num_hs_threads = 20;
1815 num_ls_threads = 20;
1816 num_ps_stack_entries = 42;
1817 num_vs_stack_entries = 42;
1818 num_gs_stack_entries = 42;
1819 num_es_stack_entries = 42;
1820 num_hs_stack_entries = 42;
1821 num_ls_stack_entries = 42;
1822 break;
1823 case CHIP_JUNIPER:
1824 num_ps_gprs = 93;
1825 num_vs_gprs = 46;
1826 num_temp_gprs = 4;
1827 num_gs_gprs = 31;
1828 num_es_gprs = 31;
1829 num_hs_gprs = 23;
1830 num_ls_gprs = 23;
1831 num_ps_threads = 128;
1832 num_vs_threads = 20;
1833 num_gs_threads = 20;
1834 num_es_threads = 20;
1835 num_hs_threads = 20;
1836 num_ls_threads = 20;
1837 num_ps_stack_entries = 85;
1838 num_vs_stack_entries = 85;
1839 num_gs_stack_entries = 85;
1840 num_es_stack_entries = 85;
1841 num_hs_stack_entries = 85;
1842 num_ls_stack_entries = 85;
1843 break;
1844 case CHIP_CYPRESS:
1845 case CHIP_HEMLOCK:
1846 num_ps_gprs = 93;
1847 num_vs_gprs = 46;
1848 num_temp_gprs = 4;
1849 num_gs_gprs = 31;
1850 num_es_gprs = 31;
1851 num_hs_gprs = 23;
1852 num_ls_gprs = 23;
1853 num_ps_threads = 128;
1854 num_vs_threads = 20;
1855 num_gs_threads = 20;
1856 num_es_threads = 20;
1857 num_hs_threads = 20;
1858 num_ls_threads = 20;
1859 num_ps_stack_entries = 85;
1860 num_vs_stack_entries = 85;
1861 num_gs_stack_entries = 85;
1862 num_es_stack_entries = 85;
1863 num_hs_stack_entries = 85;
1864 num_ls_stack_entries = 85;
1865 break;
1866 case CHIP_PALM:
1867 num_ps_gprs = 93;
1868 num_vs_gprs = 46;
1869 num_temp_gprs = 4;
1870 num_gs_gprs = 31;
1871 num_es_gprs = 31;
1872 num_hs_gprs = 23;
1873 num_ls_gprs = 23;
1874 num_ps_threads = 96;
1875 num_vs_threads = 16;
1876 num_gs_threads = 16;
1877 num_es_threads = 16;
1878 num_hs_threads = 16;
1879 num_ls_threads = 16;
1880 num_ps_stack_entries = 42;
1881 num_vs_stack_entries = 42;
1882 num_gs_stack_entries = 42;
1883 num_es_stack_entries = 42;
1884 num_hs_stack_entries = 42;
1885 num_ls_stack_entries = 42;
1886 break;
1887 case CHIP_SUMO:
1888 num_ps_gprs = 93;
1889 num_vs_gprs = 46;
1890 num_temp_gprs = 4;
1891 num_gs_gprs = 31;
1892 num_es_gprs = 31;
1893 num_hs_gprs = 23;
1894 num_ls_gprs = 23;
1895 num_ps_threads = 96;
1896 num_vs_threads = 25;
1897 num_gs_threads = 25;
1898 num_es_threads = 25;
1899 num_hs_threads = 25;
1900 num_ls_threads = 25;
1901 num_ps_stack_entries = 42;
1902 num_vs_stack_entries = 42;
1903 num_gs_stack_entries = 42;
1904 num_es_stack_entries = 42;
1905 num_hs_stack_entries = 42;
1906 num_ls_stack_entries = 42;
1907 break;
1908 case CHIP_SUMO2:
1909 num_ps_gprs = 93;
1910 num_vs_gprs = 46;
1911 num_temp_gprs = 4;
1912 num_gs_gprs = 31;
1913 num_es_gprs = 31;
1914 num_hs_gprs = 23;
1915 num_ls_gprs = 23;
1916 num_ps_threads = 96;
1917 num_vs_threads = 25;
1918 num_gs_threads = 25;
1919 num_es_threads = 25;
1920 num_hs_threads = 25;
1921 num_ls_threads = 25;
1922 num_ps_stack_entries = 85;
1923 num_vs_stack_entries = 85;
1924 num_gs_stack_entries = 85;
1925 num_es_stack_entries = 85;
1926 num_hs_stack_entries = 85;
1927 num_ls_stack_entries = 85;
1928 break;
1929 case CHIP_BARTS:
1930 num_ps_gprs = 93;
1931 num_vs_gprs = 46;
1932 num_temp_gprs = 4;
1933 num_gs_gprs = 31;
1934 num_es_gprs = 31;
1935 num_hs_gprs = 23;
1936 num_ls_gprs = 23;
1937 num_ps_threads = 128;
1938 num_vs_threads = 20;
1939 num_gs_threads = 20;
1940 num_es_threads = 20;
1941 num_hs_threads = 20;
1942 num_ls_threads = 20;
1943 num_ps_stack_entries = 85;
1944 num_vs_stack_entries = 85;
1945 num_gs_stack_entries = 85;
1946 num_es_stack_entries = 85;
1947 num_hs_stack_entries = 85;
1948 num_ls_stack_entries = 85;
1949 break;
1950 case CHIP_TURKS:
1951 num_ps_gprs = 93;
1952 num_vs_gprs = 46;
1953 num_temp_gprs = 4;
1954 num_gs_gprs = 31;
1955 num_es_gprs = 31;
1956 num_hs_gprs = 23;
1957 num_ls_gprs = 23;
1958 num_ps_threads = 128;
1959 num_vs_threads = 20;
1960 num_gs_threads = 20;
1961 num_es_threads = 20;
1962 num_hs_threads = 20;
1963 num_ls_threads = 20;
1964 num_ps_stack_entries = 42;
1965 num_vs_stack_entries = 42;
1966 num_gs_stack_entries = 42;
1967 num_es_stack_entries = 42;
1968 num_hs_stack_entries = 42;
1969 num_ls_stack_entries = 42;
1970 break;
1971 case CHIP_CAICOS:
1972 num_ps_gprs = 93;
1973 num_vs_gprs = 46;
1974 num_temp_gprs = 4;
1975 num_gs_gprs = 31;
1976 num_es_gprs = 31;
1977 num_hs_gprs = 23;
1978 num_ls_gprs = 23;
1979 num_ps_threads = 128;
1980 num_vs_threads = 10;
1981 num_gs_threads = 10;
1982 num_es_threads = 10;
1983 num_hs_threads = 10;
1984 num_ls_threads = 10;
1985 num_ps_stack_entries = 42;
1986 num_vs_stack_entries = 42;
1987 num_gs_stack_entries = 42;
1988 num_es_stack_entries = 42;
1989 num_hs_stack_entries = 42;
1990 num_ls_stack_entries = 42;
1991 break;
1992 }
1993
1994 tmp = 0x00000000;
1995 switch (family) {
1996 case CHIP_CEDAR:
1997 case CHIP_PALM:
1998 case CHIP_SUMO:
1999 case CHIP_SUMO2:
2000 case CHIP_CAICOS:
2001 break;
2002 default:
2003 tmp |= S_008C00_VC_ENABLE(1);
2004 break;
2005 }
2006 tmp |= S_008C00_EXPORT_SRC_C(1);
2007 tmp |= S_008C00_CS_PRIO(cs_prio);
2008 tmp |= S_008C00_LS_PRIO(ls_prio);
2009 tmp |= S_008C00_HS_PRIO(hs_prio);
2010 tmp |= S_008C00_PS_PRIO(ps_prio);
2011 tmp |= S_008C00_VS_PRIO(vs_prio);
2012 tmp |= S_008C00_GS_PRIO(gs_prio);
2013 tmp |= S_008C00_ES_PRIO(es_prio);
2014 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
2015
2016 /* enable dynamic GPR resource management */
2017 if (rctx->screen->info.drm_minor >= 7) {
2018 /* always set temp clauses */
2019 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
2020 S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), 0xFFFFFFFF, NULL, 0);
2021 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL, 0);
2022 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL, 0);
2023 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL, 0);
2024 r600_pipe_state_add_reg(rstate, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2025 S_028838_PS_GPRS(0x1e) |
2026 S_028838_VS_GPRS(0x1e) |
2027 S_028838_GS_GPRS(0x1e) |
2028 S_028838_ES_GPRS(0x1e) |
2029 S_028838_HS_GPRS(0x1e) |
2030 S_028838_LS_GPRS(0x1e), 0xFFFFFFFF, NULL, 0); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2031 } else {
2032 tmp = 0;
2033 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2034 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2035 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2036 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2037
2038 tmp = 0;
2039 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
2040 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2041 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2042
2043 tmp = 0;
2044 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2045 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2046 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL, 0);
2047 }
2048
2049 tmp = 0;
2050 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
2051 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2052 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2053 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2054 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2055
2056 tmp = 0;
2057 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
2058 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2059 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2060
2061 tmp = 0;
2062 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2063 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2064 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2065
2066 tmp = 0;
2067 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2068 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2069 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2070
2071 tmp = 0;
2072 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2073 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2074 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL, 0);
2075
2076 tmp = 0;
2077 tmp |= S_008E2C_NUM_PS_LDS(0x1000);
2078 tmp |= S_008E2C_NUM_LS_LDS(0x1000);
2079 r600_pipe_state_add_reg(rstate, R_008E2C_SQ_LDS_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL, 0);
2080
2081 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2082 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL, 0);
2083
2084 #if 0
2085 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL, 0);
2086
2087 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL, 0);
2088 #endif
2089 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL, 0);
2090 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL, 0);
2091
2092 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2093 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2094 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2095 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2096 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2097 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2098
2099 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2100 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL, 0);
2101 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL, 0);
2102 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL, 0);
2103
2104 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2105 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2106 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
2107 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
2108 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL, 0);
2109 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL, 0);
2110 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
2111 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
2112 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2113 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2114 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2115 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2116 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL, 0);
2117 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
2118 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
2119 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL, 0);
2120 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL, 0);
2121 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL, 0);
2122
2123 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL, 0);
2124 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL, 0);
2125 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL, 0);
2126 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL, 0);
2127 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL, 0);
2128 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL, 0);
2129 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL, 0);
2130 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL, 0);
2131 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL, 0);
2132 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL, 0);
2133 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL, 0);
2134 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL, 0);
2135 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL, 0);
2136 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL, 0);
2137 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL, 0);
2138 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL, 0);
2139 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL, 0);
2140 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL, 0);
2141 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL, 0);
2142 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL, 0);
2143 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL, 0);
2144 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL, 0);
2145 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL, 0);
2146 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL, 0);
2147 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL, 0);
2148 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL, 0);
2149 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL, 0);
2150 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL, 0);
2151 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL, 0);
2152 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL, 0);
2153 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL, 0);
2154 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL, 0);
2155
2156 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2157
2158 r600_context_pipe_state_set(&rctx->ctx, rstate);
2159 }
2160
2161 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
2162 {
2163 struct r600_pipe_state state;
2164
2165 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2166 state.nregs = 0;
2167 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2168 float offset_units = rctx->rasterizer->offset_units;
2169 unsigned offset_db_fmt_cntl = 0, depth;
2170
2171 switch (rctx->framebuffer.zsbuf->texture->format) {
2172 case PIPE_FORMAT_Z24X8_UNORM:
2173 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
2174 depth = -24;
2175 offset_units *= 2.0f;
2176 break;
2177 case PIPE_FORMAT_Z32_FLOAT:
2178 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
2179 depth = -23;
2180 offset_units *= 1.0f;
2181 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2182 break;
2183 case PIPE_FORMAT_Z16_UNORM:
2184 depth = -16;
2185 offset_units *= 4.0f;
2186 break;
2187 default:
2188 return;
2189 }
2190 /* FIXME some of those reg can be computed with cso */
2191 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2192 r600_pipe_state_add_reg(&state,
2193 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2194 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
2195 r600_pipe_state_add_reg(&state,
2196 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2197 fui(offset_units), 0xFFFFFFFF, NULL, 0);
2198 r600_pipe_state_add_reg(&state,
2199 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2200 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
2201 r600_pipe_state_add_reg(&state,
2202 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2203 fui(offset_units), 0xFFFFFFFF, NULL, 0);
2204 r600_pipe_state_add_reg(&state,
2205 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2206 offset_db_fmt_cntl, 0xFFFFFFFF, NULL, 0);
2207 r600_context_pipe_state_set(&rctx->ctx, &state);
2208 }
2209 }
2210
2211 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2212 {
2213 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2214 struct r600_pipe_state *rstate = &shader->rstate;
2215 struct r600_shader *rshader = &shader->shader;
2216 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2217 int pos_index = -1, face_index = -1;
2218 int ninterp = 0;
2219 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2220 unsigned spi_baryc_cntl;
2221
2222 rstate->nregs = 0;
2223
2224 db_shader_control = 0;
2225 for (i = 0; i < rshader->ninput; i++) {
2226 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2227 POSITION goes via GPRs from the SC so isn't counted */
2228 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2229 pos_index = i;
2230 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2231 face_index = i;
2232 else {
2233 ninterp++;
2234 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2235 have_linear = TRUE;
2236 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2237 have_perspective = TRUE;
2238 if (rshader->input[i].centroid)
2239 have_centroid = TRUE;
2240 }
2241 }
2242 for (i = 0; i < rshader->noutput; i++) {
2243 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2244 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2245 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2246 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2247 }
2248 if (rshader->uses_kill)
2249 db_shader_control |= S_02880C_KILL_ENABLE(1);
2250
2251 exports_ps = 0;
2252 num_cout = 0;
2253 for (i = 0; i < rshader->noutput; i++) {
2254 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2255 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2256 exports_ps |= 1;
2257 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2258 if (rshader->fs_write_all)
2259 num_cout = rshader->nr_cbufs;
2260 else
2261 num_cout++;
2262 }
2263 }
2264 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2265 if (!exports_ps) {
2266 /* always at least export 1 component per pixel */
2267 exports_ps = 2;
2268 }
2269
2270 if (ninterp == 0) {
2271 ninterp = 1;
2272 have_perspective = TRUE;
2273 }
2274
2275 if (!have_perspective && !have_linear)
2276 have_perspective = TRUE;
2277
2278 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2279 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2280 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2281 spi_input_z = 0;
2282 if (pos_index != -1) {
2283 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2284 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2285 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2286 spi_input_z |= 1;
2287 }
2288
2289 spi_ps_in_control_1 = 0;
2290 if (face_index != -1) {
2291 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2292 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2293 }
2294
2295 spi_baryc_cntl = 0;
2296 if (have_perspective)
2297 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2298 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2299 if (have_linear)
2300 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2301 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2302
2303 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2304 spi_ps_in_control_0, 0xFFFFFFFF, NULL, 0);
2305 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2306 spi_ps_in_control_1, 0xFFFFFFFF, NULL, 0);
2307 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2308 0, 0xFFFFFFFF, NULL, 0);
2309 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL, 0);
2310 r600_pipe_state_add_reg(rstate,
2311 R_0286E0_SPI_BARYC_CNTL,
2312 spi_baryc_cntl,
2313 0xFFFFFFFF, NULL, 0);
2314
2315 r600_pipe_state_add_reg(rstate,
2316 R_028840_SQ_PGM_START_PS,
2317 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2318 r600_pipe_state_add_reg(rstate,
2319 R_028844_SQ_PGM_RESOURCES_PS,
2320 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2321 S_028844_PRIME_CACHE_ON_DRAW(1) |
2322 S_028844_STACK_SIZE(rshader->bc.nstack),
2323 0xFFFFFFFF, NULL, 0);
2324 r600_pipe_state_add_reg(rstate,
2325 R_028848_SQ_PGM_RESOURCES_2_PS,
2326 0x0, 0xFFFFFFFF, NULL, 0);
2327 r600_pipe_state_add_reg(rstate,
2328 R_02884C_SQ_PGM_EXPORTS_PS,
2329 exports_ps, 0xFFFFFFFF, NULL, 0);
2330 /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */
2331 /* only set some bits here, the other bits are set in the dsa state */
2332 r600_pipe_state_add_reg(rstate,
2333 R_02880C_DB_SHADER_CONTROL,
2334 db_shader_control,
2335 S_02880C_Z_EXPORT_ENABLE(1) |
2336 S_02880C_STENCIL_EXPORT_ENABLE(1) |
2337 S_02880C_KILL_ENABLE(1),
2338 NULL, 0);
2339 r600_pipe_state_add_reg(rstate,
2340 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
2341 0xFFFFFFFF, NULL, 0);
2342 }
2343
2344 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2345 {
2346 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2347 struct r600_pipe_state *rstate = &shader->rstate;
2348 struct r600_shader *rshader = &shader->shader;
2349 unsigned spi_vs_out_id[10];
2350 unsigned i, tmp, nparams;
2351
2352 /* clear previous register */
2353 rstate->nregs = 0;
2354
2355 /* so far never got proper semantic id from tgsi */
2356 for (i = 0; i < 10; i++) {
2357 spi_vs_out_id[i] = 0;
2358 }
2359 for (i = 0; i < 32; i++) {
2360 tmp = i << ((i & 3) * 8);
2361 spi_vs_out_id[i / 4] |= tmp;
2362 }
2363 for (i = 0; i < 10; i++) {
2364 r600_pipe_state_add_reg(rstate,
2365 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2366 spi_vs_out_id[i], 0xFFFFFFFF, NULL, 0);
2367 }
2368
2369 /* Certain attributes (position, psize, etc.) don't count as params.
2370 * VS is required to export at least one param and r600_shader_from_tgsi()
2371 * takes care of adding a dummy export.
2372 */
2373 nparams = rshader->noutput - rshader->npos;
2374 if (nparams < 1)
2375 nparams = 1;
2376
2377 r600_pipe_state_add_reg(rstate,
2378 R_0286C4_SPI_VS_OUT_CONFIG,
2379 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2380 0xFFFFFFFF, NULL, 0);
2381 r600_pipe_state_add_reg(rstate,
2382 R_028860_SQ_PGM_RESOURCES_VS,
2383 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2384 S_028860_STACK_SIZE(rshader->bc.nstack),
2385 0xFFFFFFFF, NULL, 0);
2386 r600_pipe_state_add_reg(rstate,
2387 R_028864_SQ_PGM_RESOURCES_2_VS,
2388 0x0, 0xFFFFFFFF, NULL, 0);
2389 r600_pipe_state_add_reg(rstate,
2390 R_02885C_SQ_PGM_START_VS,
2391 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2392
2393 r600_pipe_state_add_reg(rstate,
2394 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2395 0xFFFFFFFF, NULL, 0);
2396 }
2397
2398 void evergreen_fetch_shader(struct pipe_context *ctx,
2399 struct r600_vertex_element *ve)
2400 {
2401 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2402 struct r600_pipe_state *rstate = &ve->rstate;
2403 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2404 rstate->nregs = 0;
2405 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
2406 0x00000000, 0xFFFFFFFF, NULL, 0);
2407 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2408 0,
2409 0xFFFFFFFF, ve->fetch_shader, RADEON_USAGE_READ);
2410 }
2411
2412 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
2413 {
2414 struct pipe_depth_stencil_alpha_state dsa;
2415 struct r600_pipe_state *rstate;
2416
2417 memset(&dsa, 0, sizeof(dsa));
2418
2419 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2420 r600_pipe_state_add_reg(rstate,
2421 R_02880C_DB_SHADER_CONTROL,
2422 0x0,
2423 S_02880C_DUAL_EXPORT_ENABLE(1), NULL, 0);
2424 r600_pipe_state_add_reg(rstate,
2425 R_028000_DB_RENDER_CONTROL,
2426 S_028000_DEPTH_COPY_ENABLE(1) |
2427 S_028000_STENCIL_COPY_ENABLE(1) |
2428 S_028000_COPY_CENTROID(1),
2429 S_028000_DEPTH_COPY_ENABLE(1) |
2430 S_028000_STENCIL_COPY_ENABLE(1) |
2431 S_028000_COPY_CENTROID(1), NULL, 0);
2432 return rstate;
2433 }
2434
2435 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
2436 struct r600_pipe_resource_state *rstate)
2437 {
2438 rstate->id = R600_PIPE_STATE_RESOURCE;
2439
2440 rstate->val[0] = 0;
2441 rstate->bo[0] = NULL;
2442 rstate->val[1] = 0;
2443 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2444 rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2445 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2446 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2447 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2448 rstate->val[4] = 0;
2449 rstate->val[5] = 0;
2450 rstate->val[6] = 0;
2451 rstate->val[7] = 0xc0000000;
2452 }
2453
2454
2455 void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
2456 struct r600_resource *rbuffer,
2457 unsigned offset, unsigned stride,
2458 enum radeon_bo_usage usage)
2459 {
2460 rstate->bo[0] = rbuffer->bo;
2461 rstate->bo_usage[0] = usage;
2462 rstate->val[0] = offset;
2463 rstate->val[1] = rbuffer->bo_size - offset - 1;
2464 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2465 S_030008_STRIDE(stride);
2466 }