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r600g: setup COLOR1 for possible dual-src in the framebuffer bind
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "evergreend.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31
32 static uint32_t eg_num_banks(uint32_t nbanks)
33 {
34 switch (nbanks) {
35 case 2:
36 return 0;
37 case 4:
38 return 1;
39 case 8:
40 default:
41 return 2;
42 case 16:
43 return 3;
44 }
45 }
46
47
48 static unsigned eg_tile_split(unsigned tile_split)
49 {
50 switch (tile_split) {
51 case 64: tile_split = 0; break;
52 case 128: tile_split = 1; break;
53 case 256: tile_split = 2; break;
54 case 512: tile_split = 3; break;
55 default:
56 case 1024: tile_split = 4; break;
57 case 2048: tile_split = 5; break;
58 case 4096: tile_split = 6; break;
59 }
60 return tile_split;
61 }
62
63 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
64 {
65 switch (macro_tile_aspect) {
66 default:
67 case 1: macro_tile_aspect = 0; break;
68 case 2: macro_tile_aspect = 1; break;
69 case 4: macro_tile_aspect = 2; break;
70 case 8: macro_tile_aspect = 3; break;
71 }
72 return macro_tile_aspect;
73 }
74
75 static unsigned eg_bank_wh(unsigned bankwh)
76 {
77 switch (bankwh) {
78 default:
79 case 1: bankwh = 0; break;
80 case 2: bankwh = 1; break;
81 case 4: bankwh = 2; break;
82 case 8: bankwh = 3; break;
83 }
84 return bankwh;
85 }
86
87 static uint32_t r600_translate_blend_function(int blend_func)
88 {
89 switch (blend_func) {
90 case PIPE_BLEND_ADD:
91 return V_028780_COMB_DST_PLUS_SRC;
92 case PIPE_BLEND_SUBTRACT:
93 return V_028780_COMB_SRC_MINUS_DST;
94 case PIPE_BLEND_REVERSE_SUBTRACT:
95 return V_028780_COMB_DST_MINUS_SRC;
96 case PIPE_BLEND_MIN:
97 return V_028780_COMB_MIN_DST_SRC;
98 case PIPE_BLEND_MAX:
99 return V_028780_COMB_MAX_DST_SRC;
100 default:
101 R600_ERR("Unknown blend function %d\n", blend_func);
102 assert(0);
103 break;
104 }
105 return 0;
106 }
107
108 static uint32_t r600_translate_blend_factor(int blend_fact)
109 {
110 switch (blend_fact) {
111 case PIPE_BLENDFACTOR_ONE:
112 return V_028780_BLEND_ONE;
113 case PIPE_BLENDFACTOR_SRC_COLOR:
114 return V_028780_BLEND_SRC_COLOR;
115 case PIPE_BLENDFACTOR_SRC_ALPHA:
116 return V_028780_BLEND_SRC_ALPHA;
117 case PIPE_BLENDFACTOR_DST_ALPHA:
118 return V_028780_BLEND_DST_ALPHA;
119 case PIPE_BLENDFACTOR_DST_COLOR:
120 return V_028780_BLEND_DST_COLOR;
121 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
122 return V_028780_BLEND_SRC_ALPHA_SATURATE;
123 case PIPE_BLENDFACTOR_CONST_COLOR:
124 return V_028780_BLEND_CONST_COLOR;
125 case PIPE_BLENDFACTOR_CONST_ALPHA:
126 return V_028780_BLEND_CONST_ALPHA;
127 case PIPE_BLENDFACTOR_ZERO:
128 return V_028780_BLEND_ZERO;
129 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
130 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
131 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
132 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
134 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
135 case PIPE_BLENDFACTOR_INV_DST_COLOR:
136 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
137 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
138 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
139 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
140 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
141 case PIPE_BLENDFACTOR_SRC1_COLOR:
142 return V_028780_BLEND_SRC1_COLOR;
143 case PIPE_BLENDFACTOR_SRC1_ALPHA:
144 return V_028780_BLEND_SRC1_ALPHA;
145 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
146 return V_028780_BLEND_INV_SRC1_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
148 return V_028780_BLEND_INV_SRC1_ALPHA;
149 default:
150 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
151 assert(0);
152 break;
153 }
154 return 0;
155 }
156
157 static unsigned r600_tex_dim(unsigned dim)
158 {
159 switch (dim) {
160 default:
161 case PIPE_TEXTURE_1D:
162 return V_030000_SQ_TEX_DIM_1D;
163 case PIPE_TEXTURE_1D_ARRAY:
164 return V_030000_SQ_TEX_DIM_1D_ARRAY;
165 case PIPE_TEXTURE_2D:
166 case PIPE_TEXTURE_RECT:
167 return V_030000_SQ_TEX_DIM_2D;
168 case PIPE_TEXTURE_2D_ARRAY:
169 return V_030000_SQ_TEX_DIM_2D_ARRAY;
170 case PIPE_TEXTURE_3D:
171 return V_030000_SQ_TEX_DIM_3D;
172 case PIPE_TEXTURE_CUBE:
173 return V_030000_SQ_TEX_DIM_CUBEMAP;
174 }
175 }
176
177 static uint32_t r600_translate_dbformat(enum pipe_format format)
178 {
179 switch (format) {
180 case PIPE_FORMAT_Z16_UNORM:
181 return V_028040_Z_16;
182 case PIPE_FORMAT_Z24X8_UNORM:
183 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
184 return V_028040_Z_24;
185 case PIPE_FORMAT_Z32_FLOAT:
186 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
187 return V_028040_Z_32_FLOAT;
188 default:
189 return ~0U;
190 }
191 }
192
193 static uint32_t r600_translate_colorswap(enum pipe_format format)
194 {
195 switch (format) {
196 /* 8-bit buffers. */
197 case PIPE_FORMAT_L4A4_UNORM:
198 case PIPE_FORMAT_A4R4_UNORM:
199 return V_028C70_SWAP_ALT;
200
201 case PIPE_FORMAT_A8_UNORM:
202 case PIPE_FORMAT_A8_SNORM:
203 case PIPE_FORMAT_A8_UINT:
204 case PIPE_FORMAT_A8_SINT:
205 case PIPE_FORMAT_A16_UNORM:
206 case PIPE_FORMAT_A16_SNORM:
207 case PIPE_FORMAT_A16_UINT:
208 case PIPE_FORMAT_A16_SINT:
209 case PIPE_FORMAT_A16_FLOAT:
210 case PIPE_FORMAT_A32_UINT:
211 case PIPE_FORMAT_A32_SINT:
212 case PIPE_FORMAT_A32_FLOAT:
213 case PIPE_FORMAT_R4A4_UNORM:
214 return V_028C70_SWAP_ALT_REV;
215 case PIPE_FORMAT_I8_UNORM:
216 case PIPE_FORMAT_I8_SNORM:
217 case PIPE_FORMAT_I8_UINT:
218 case PIPE_FORMAT_I8_SINT:
219 case PIPE_FORMAT_I16_UNORM:
220 case PIPE_FORMAT_I16_SNORM:
221 case PIPE_FORMAT_I16_UINT:
222 case PIPE_FORMAT_I16_SINT:
223 case PIPE_FORMAT_I16_FLOAT:
224 case PIPE_FORMAT_I32_UINT:
225 case PIPE_FORMAT_I32_SINT:
226 case PIPE_FORMAT_I32_FLOAT:
227 case PIPE_FORMAT_L8_UNORM:
228 case PIPE_FORMAT_L8_SNORM:
229 case PIPE_FORMAT_L8_UINT:
230 case PIPE_FORMAT_L8_SINT:
231 case PIPE_FORMAT_L8_SRGB:
232 case PIPE_FORMAT_L16_UNORM:
233 case PIPE_FORMAT_L16_SNORM:
234 case PIPE_FORMAT_L16_UINT:
235 case PIPE_FORMAT_L16_SINT:
236 case PIPE_FORMAT_L16_FLOAT:
237 case PIPE_FORMAT_L32_UINT:
238 case PIPE_FORMAT_L32_SINT:
239 case PIPE_FORMAT_L32_FLOAT:
240 case PIPE_FORMAT_R8_UNORM:
241 case PIPE_FORMAT_R8_SNORM:
242 case PIPE_FORMAT_R8_UINT:
243 case PIPE_FORMAT_R8_SINT:
244 return V_028C70_SWAP_STD;
245
246 /* 16-bit buffers. */
247 case PIPE_FORMAT_B5G6R5_UNORM:
248 return V_028C70_SWAP_STD_REV;
249
250 case PIPE_FORMAT_B5G5R5A1_UNORM:
251 case PIPE_FORMAT_B5G5R5X1_UNORM:
252 return V_028C70_SWAP_ALT;
253
254 case PIPE_FORMAT_B4G4R4A4_UNORM:
255 case PIPE_FORMAT_B4G4R4X4_UNORM:
256 return V_028C70_SWAP_ALT;
257
258 case PIPE_FORMAT_Z16_UNORM:
259 return V_028C70_SWAP_STD;
260
261 case PIPE_FORMAT_L8A8_UNORM:
262 case PIPE_FORMAT_L8A8_SNORM:
263 case PIPE_FORMAT_L8A8_UINT:
264 case PIPE_FORMAT_L8A8_SINT:
265 case PIPE_FORMAT_L8A8_SRGB:
266 case PIPE_FORMAT_L16A16_UNORM:
267 case PIPE_FORMAT_L16A16_SNORM:
268 case PIPE_FORMAT_L16A16_UINT:
269 case PIPE_FORMAT_L16A16_SINT:
270 case PIPE_FORMAT_L16A16_FLOAT:
271 case PIPE_FORMAT_L32A32_UINT:
272 case PIPE_FORMAT_L32A32_SINT:
273 case PIPE_FORMAT_L32A32_FLOAT:
274 return V_028C70_SWAP_ALT;
275 case PIPE_FORMAT_R8G8_UNORM:
276 case PIPE_FORMAT_R8G8_SNORM:
277 case PIPE_FORMAT_R8G8_UINT:
278 case PIPE_FORMAT_R8G8_SINT:
279 return V_028C70_SWAP_STD;
280
281 case PIPE_FORMAT_R16_UNORM:
282 case PIPE_FORMAT_R16_SNORM:
283 case PIPE_FORMAT_R16_UINT:
284 case PIPE_FORMAT_R16_SINT:
285 case PIPE_FORMAT_R16_FLOAT:
286 return V_028C70_SWAP_STD;
287
288 /* 32-bit buffers. */
289 case PIPE_FORMAT_A8B8G8R8_SRGB:
290 return V_028C70_SWAP_STD_REV;
291 case PIPE_FORMAT_B8G8R8A8_SRGB:
292 return V_028C70_SWAP_ALT;
293
294 case PIPE_FORMAT_B8G8R8A8_UNORM:
295 case PIPE_FORMAT_B8G8R8X8_UNORM:
296 return V_028C70_SWAP_ALT;
297
298 case PIPE_FORMAT_A8R8G8B8_UNORM:
299 case PIPE_FORMAT_X8R8G8B8_UNORM:
300 return V_028C70_SWAP_ALT_REV;
301 case PIPE_FORMAT_R8G8B8A8_SNORM:
302 case PIPE_FORMAT_R8G8B8A8_UNORM:
303 case PIPE_FORMAT_R8G8B8A8_SINT:
304 case PIPE_FORMAT_R8G8B8A8_UINT:
305 case PIPE_FORMAT_R8G8B8X8_UNORM:
306 return V_028C70_SWAP_STD;
307
308 case PIPE_FORMAT_A8B8G8R8_UNORM:
309 case PIPE_FORMAT_X8B8G8R8_UNORM:
310 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
311 return V_028C70_SWAP_STD_REV;
312
313 case PIPE_FORMAT_Z24X8_UNORM:
314 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
315 return V_028C70_SWAP_STD;
316
317 case PIPE_FORMAT_X8Z24_UNORM:
318 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
319 return V_028C70_SWAP_STD;
320
321 case PIPE_FORMAT_R10G10B10A2_UNORM:
322 case PIPE_FORMAT_R10G10B10X2_SNORM:
323 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
324 return V_028C70_SWAP_STD;
325
326 case PIPE_FORMAT_B10G10R10A2_UNORM:
327 case PIPE_FORMAT_B10G10R10A2_UINT:
328 return V_028C70_SWAP_ALT;
329
330 case PIPE_FORMAT_R11G11B10_FLOAT:
331 case PIPE_FORMAT_R32_FLOAT:
332 case PIPE_FORMAT_R32_UINT:
333 case PIPE_FORMAT_R32_SINT:
334 case PIPE_FORMAT_Z32_FLOAT:
335 case PIPE_FORMAT_R16G16_FLOAT:
336 case PIPE_FORMAT_R16G16_UNORM:
337 case PIPE_FORMAT_R16G16_SNORM:
338 case PIPE_FORMAT_R16G16_UINT:
339 case PIPE_FORMAT_R16G16_SINT:
340 return V_028C70_SWAP_STD;
341
342 /* 64-bit buffers. */
343 case PIPE_FORMAT_R32G32_FLOAT:
344 case PIPE_FORMAT_R32G32_UINT:
345 case PIPE_FORMAT_R32G32_SINT:
346 case PIPE_FORMAT_R16G16B16A16_UNORM:
347 case PIPE_FORMAT_R16G16B16A16_SNORM:
348 case PIPE_FORMAT_R16G16B16A16_UINT:
349 case PIPE_FORMAT_R16G16B16A16_SINT:
350 case PIPE_FORMAT_R16G16B16A16_FLOAT:
351 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
352
353 /* 128-bit buffers. */
354 case PIPE_FORMAT_R32G32B32A32_FLOAT:
355 case PIPE_FORMAT_R32G32B32A32_SNORM:
356 case PIPE_FORMAT_R32G32B32A32_UNORM:
357 case PIPE_FORMAT_R32G32B32A32_SINT:
358 case PIPE_FORMAT_R32G32B32A32_UINT:
359 return V_028C70_SWAP_STD;
360 default:
361 R600_ERR("unsupported colorswap format %d\n", format);
362 return ~0U;
363 }
364 return ~0U;
365 }
366
367 static uint32_t r600_translate_colorformat(enum pipe_format format)
368 {
369 switch (format) {
370 /* 8-bit buffers. */
371 case PIPE_FORMAT_A8_UNORM:
372 case PIPE_FORMAT_A8_SNORM:
373 case PIPE_FORMAT_A8_UINT:
374 case PIPE_FORMAT_A8_SINT:
375 case PIPE_FORMAT_I8_UNORM:
376 case PIPE_FORMAT_I8_SNORM:
377 case PIPE_FORMAT_I8_UINT:
378 case PIPE_FORMAT_I8_SINT:
379 case PIPE_FORMAT_L8_UNORM:
380 case PIPE_FORMAT_L8_SNORM:
381 case PIPE_FORMAT_L8_UINT:
382 case PIPE_FORMAT_L8_SINT:
383 case PIPE_FORMAT_L8_SRGB:
384 case PIPE_FORMAT_R8_UNORM:
385 case PIPE_FORMAT_R8_SNORM:
386 case PIPE_FORMAT_R8_UINT:
387 case PIPE_FORMAT_R8_SINT:
388 return V_028C70_COLOR_8;
389
390 /* 16-bit buffers. */
391 case PIPE_FORMAT_B5G6R5_UNORM:
392 return V_028C70_COLOR_5_6_5;
393
394 case PIPE_FORMAT_B5G5R5A1_UNORM:
395 case PIPE_FORMAT_B5G5R5X1_UNORM:
396 return V_028C70_COLOR_1_5_5_5;
397
398 case PIPE_FORMAT_B4G4R4A4_UNORM:
399 case PIPE_FORMAT_B4G4R4X4_UNORM:
400 return V_028C70_COLOR_4_4_4_4;
401
402 case PIPE_FORMAT_Z16_UNORM:
403 return V_028C70_COLOR_16;
404
405 case PIPE_FORMAT_L8A8_UNORM:
406 case PIPE_FORMAT_L8A8_SNORM:
407 case PIPE_FORMAT_L8A8_UINT:
408 case PIPE_FORMAT_L8A8_SINT:
409 case PIPE_FORMAT_L8A8_SRGB:
410 case PIPE_FORMAT_R8G8_UNORM:
411 case PIPE_FORMAT_R8G8_SNORM:
412 case PIPE_FORMAT_R8G8_UINT:
413 case PIPE_FORMAT_R8G8_SINT:
414 return V_028C70_COLOR_8_8;
415
416 case PIPE_FORMAT_R16_UNORM:
417 case PIPE_FORMAT_R16_SNORM:
418 case PIPE_FORMAT_R16_UINT:
419 case PIPE_FORMAT_R16_SINT:
420 case PIPE_FORMAT_A16_UNORM:
421 case PIPE_FORMAT_A16_SNORM:
422 case PIPE_FORMAT_A16_UINT:
423 case PIPE_FORMAT_A16_SINT:
424 case PIPE_FORMAT_L16_UNORM:
425 case PIPE_FORMAT_L16_SNORM:
426 case PIPE_FORMAT_L16_UINT:
427 case PIPE_FORMAT_L16_SINT:
428 case PIPE_FORMAT_I16_UNORM:
429 case PIPE_FORMAT_I16_SNORM:
430 case PIPE_FORMAT_I16_UINT:
431 case PIPE_FORMAT_I16_SINT:
432 return V_028C70_COLOR_16;
433
434 case PIPE_FORMAT_R16_FLOAT:
435 case PIPE_FORMAT_A16_FLOAT:
436 case PIPE_FORMAT_L16_FLOAT:
437 case PIPE_FORMAT_I16_FLOAT:
438 return V_028C70_COLOR_16_FLOAT;
439
440 /* 32-bit buffers. */
441 case PIPE_FORMAT_A8B8G8R8_SRGB:
442 case PIPE_FORMAT_A8B8G8R8_UNORM:
443 case PIPE_FORMAT_A8R8G8B8_UNORM:
444 case PIPE_FORMAT_B8G8R8A8_SRGB:
445 case PIPE_FORMAT_B8G8R8A8_UNORM:
446 case PIPE_FORMAT_B8G8R8X8_UNORM:
447 case PIPE_FORMAT_R8G8B8A8_SNORM:
448 case PIPE_FORMAT_R8G8B8A8_UNORM:
449 case PIPE_FORMAT_R8G8B8X8_UNORM:
450 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
451 case PIPE_FORMAT_X8B8G8R8_UNORM:
452 case PIPE_FORMAT_X8R8G8B8_UNORM:
453 case PIPE_FORMAT_R8G8B8_UNORM:
454 case PIPE_FORMAT_R8G8B8A8_SINT:
455 case PIPE_FORMAT_R8G8B8A8_UINT:
456 return V_028C70_COLOR_8_8_8_8;
457
458 case PIPE_FORMAT_R10G10B10A2_UNORM:
459 case PIPE_FORMAT_R10G10B10X2_SNORM:
460 case PIPE_FORMAT_B10G10R10A2_UNORM:
461 case PIPE_FORMAT_B10G10R10A2_UINT:
462 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
463 return V_028C70_COLOR_2_10_10_10;
464
465 case PIPE_FORMAT_Z24X8_UNORM:
466 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
467 return V_028C70_COLOR_8_24;
468
469 case PIPE_FORMAT_X8Z24_UNORM:
470 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
471 return V_028C70_COLOR_24_8;
472
473 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
474 return V_028C70_COLOR_X24_8_32_FLOAT;
475
476 case PIPE_FORMAT_R32_UINT:
477 case PIPE_FORMAT_R32_SINT:
478 case PIPE_FORMAT_A32_UINT:
479 case PIPE_FORMAT_A32_SINT:
480 case PIPE_FORMAT_L32_UINT:
481 case PIPE_FORMAT_L32_SINT:
482 case PIPE_FORMAT_I32_UINT:
483 case PIPE_FORMAT_I32_SINT:
484 return V_028C70_COLOR_32;
485
486 case PIPE_FORMAT_R32_FLOAT:
487 case PIPE_FORMAT_A32_FLOAT:
488 case PIPE_FORMAT_L32_FLOAT:
489 case PIPE_FORMAT_I32_FLOAT:
490 case PIPE_FORMAT_Z32_FLOAT:
491 return V_028C70_COLOR_32_FLOAT;
492
493 case PIPE_FORMAT_R16G16_FLOAT:
494 case PIPE_FORMAT_L16A16_FLOAT:
495 return V_028C70_COLOR_16_16_FLOAT;
496
497 case PIPE_FORMAT_R16G16_UNORM:
498 case PIPE_FORMAT_R16G16_SNORM:
499 case PIPE_FORMAT_R16G16_UINT:
500 case PIPE_FORMAT_R16G16_SINT:
501 case PIPE_FORMAT_L16A16_UNORM:
502 case PIPE_FORMAT_L16A16_SNORM:
503 case PIPE_FORMAT_L16A16_UINT:
504 case PIPE_FORMAT_L16A16_SINT:
505 return V_028C70_COLOR_16_16;
506
507 case PIPE_FORMAT_R11G11B10_FLOAT:
508 return V_028C70_COLOR_10_11_11_FLOAT;
509
510 /* 64-bit buffers. */
511 case PIPE_FORMAT_R16G16B16A16_UINT:
512 case PIPE_FORMAT_R16G16B16A16_SINT:
513 case PIPE_FORMAT_R16G16B16A16_UNORM:
514 case PIPE_FORMAT_R16G16B16A16_SNORM:
515 return V_028C70_COLOR_16_16_16_16;
516
517 case PIPE_FORMAT_R16G16B16_FLOAT:
518 case PIPE_FORMAT_R16G16B16A16_FLOAT:
519 return V_028C70_COLOR_16_16_16_16_FLOAT;
520
521 case PIPE_FORMAT_R32G32_FLOAT:
522 case PIPE_FORMAT_L32A32_FLOAT:
523 return V_028C70_COLOR_32_32_FLOAT;
524
525 case PIPE_FORMAT_R32G32_SINT:
526 case PIPE_FORMAT_R32G32_UINT:
527 case PIPE_FORMAT_L32A32_UINT:
528 case PIPE_FORMAT_L32A32_SINT:
529 return V_028C70_COLOR_32_32;
530
531 /* 96-bit buffers. */
532 case PIPE_FORMAT_R32G32B32_FLOAT:
533 return V_028C70_COLOR_32_32_32_FLOAT;
534
535 /* 128-bit buffers. */
536 case PIPE_FORMAT_R32G32B32A32_SNORM:
537 case PIPE_FORMAT_R32G32B32A32_UNORM:
538 case PIPE_FORMAT_R32G32B32A32_SINT:
539 case PIPE_FORMAT_R32G32B32A32_UINT:
540 return V_028C70_COLOR_32_32_32_32;
541 case PIPE_FORMAT_R32G32B32A32_FLOAT:
542 return V_028C70_COLOR_32_32_32_32_FLOAT;
543
544 /* YUV buffers. */
545 case PIPE_FORMAT_UYVY:
546 case PIPE_FORMAT_YUYV:
547 default:
548 return ~0U; /* Unsupported. */
549 }
550 }
551
552 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
553 {
554 if (R600_BIG_ENDIAN) {
555 switch(colorformat) {
556
557 /* 8-bit buffers. */
558 case V_028C70_COLOR_8:
559 return ENDIAN_NONE;
560
561 /* 16-bit buffers. */
562 case V_028C70_COLOR_5_6_5:
563 case V_028C70_COLOR_1_5_5_5:
564 case V_028C70_COLOR_4_4_4_4:
565 case V_028C70_COLOR_16:
566 case V_028C70_COLOR_8_8:
567 return ENDIAN_8IN16;
568
569 /* 32-bit buffers. */
570 case V_028C70_COLOR_8_8_8_8:
571 case V_028C70_COLOR_2_10_10_10:
572 case V_028C70_COLOR_8_24:
573 case V_028C70_COLOR_24_8:
574 case V_028C70_COLOR_32_FLOAT:
575 case V_028C70_COLOR_16_16_FLOAT:
576 case V_028C70_COLOR_16_16:
577 return ENDIAN_8IN32;
578
579 /* 64-bit buffers. */
580 case V_028C70_COLOR_16_16_16_16:
581 case V_028C70_COLOR_16_16_16_16_FLOAT:
582 return ENDIAN_8IN16;
583
584 case V_028C70_COLOR_32_32_FLOAT:
585 case V_028C70_COLOR_32_32:
586 case V_028C70_COLOR_X24_8_32_FLOAT:
587 return ENDIAN_8IN32;
588
589 /* 96-bit buffers. */
590 case V_028C70_COLOR_32_32_32_FLOAT:
591 /* 128-bit buffers. */
592 case V_028C70_COLOR_32_32_32_32_FLOAT:
593 case V_028C70_COLOR_32_32_32_32:
594 return ENDIAN_8IN32;
595 default:
596 return ENDIAN_NONE; /* Unsupported. */
597 }
598 } else {
599 return ENDIAN_NONE;
600 }
601 }
602
603 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
604 {
605 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
606 }
607
608 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
609 {
610 return r600_translate_colorformat(format) != ~0U &&
611 r600_translate_colorswap(format) != ~0U;
612 }
613
614 static bool r600_is_zs_format_supported(enum pipe_format format)
615 {
616 return r600_translate_dbformat(format) != ~0U;
617 }
618
619 boolean evergreen_is_format_supported(struct pipe_screen *screen,
620 enum pipe_format format,
621 enum pipe_texture_target target,
622 unsigned sample_count,
623 unsigned usage)
624 {
625 unsigned retval = 0;
626
627 if (target >= PIPE_MAX_TEXTURE_TYPES) {
628 R600_ERR("r600: unsupported texture type %d\n", target);
629 return FALSE;
630 }
631
632 if (!util_format_is_supported(format, usage))
633 return FALSE;
634
635 /* Multisample */
636 if (sample_count > 1)
637 return FALSE;
638
639 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
640 r600_is_sampler_format_supported(screen, format)) {
641 retval |= PIPE_BIND_SAMPLER_VIEW;
642 }
643
644 if ((usage & (PIPE_BIND_RENDER_TARGET |
645 PIPE_BIND_DISPLAY_TARGET |
646 PIPE_BIND_SCANOUT |
647 PIPE_BIND_SHARED)) &&
648 r600_is_colorbuffer_format_supported(format)) {
649 retval |= usage &
650 (PIPE_BIND_RENDER_TARGET |
651 PIPE_BIND_DISPLAY_TARGET |
652 PIPE_BIND_SCANOUT |
653 PIPE_BIND_SHARED);
654 }
655
656 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
657 r600_is_zs_format_supported(format)) {
658 retval |= PIPE_BIND_DEPTH_STENCIL;
659 }
660
661 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
662 r600_is_vertex_format_supported(format)) {
663 retval |= PIPE_BIND_VERTEX_BUFFER;
664 }
665
666 if (usage & PIPE_BIND_TRANSFER_READ)
667 retval |= PIPE_BIND_TRANSFER_READ;
668 if (usage & PIPE_BIND_TRANSFER_WRITE)
669 retval |= PIPE_BIND_TRANSFER_WRITE;
670
671 return retval == usage;
672 }
673
674 static void *evergreen_create_blend_state(struct pipe_context *ctx,
675 const struct pipe_blend_state *state)
676 {
677 struct r600_context *rctx = (struct r600_context *)ctx;
678 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
679 struct r600_pipe_state *rstate;
680 uint32_t color_control, target_mask;
681 /* XXX there is more then 8 framebuffer */
682 unsigned blend_cntl[8];
683
684 if (blend == NULL) {
685 return NULL;
686 }
687
688 rstate = &blend->rstate;
689
690 rstate->id = R600_PIPE_STATE_BLEND;
691
692 target_mask = 0;
693 color_control = S_028808_MODE(1);
694 if (state->logicop_enable) {
695 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
696 } else {
697 color_control |= (0xcc << 16);
698 }
699 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
700 if (state->independent_blend_enable) {
701 for (int i = 0; i < 8; i++) {
702 target_mask |= (state->rt[i].colormask << (4 * i));
703 }
704 } else {
705 for (int i = 0; i < 8; i++) {
706 target_mask |= (state->rt[0].colormask << (4 * i));
707 }
708 }
709 blend->cb_target_mask = target_mask;
710
711 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
712 color_control);
713 /* only have dual source on MRT0 */
714 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
715 for (int i = 0; i < 8; i++) {
716 /* state->rt entries > 0 only written if independent blending */
717 const int j = state->independent_blend_enable ? i : 0;
718
719 unsigned eqRGB = state->rt[j].rgb_func;
720 unsigned srcRGB = state->rt[j].rgb_src_factor;
721 unsigned dstRGB = state->rt[j].rgb_dst_factor;
722 unsigned eqA = state->rt[j].alpha_func;
723 unsigned srcA = state->rt[j].alpha_src_factor;
724 unsigned dstA = state->rt[j].alpha_dst_factor;
725
726 blend_cntl[i] = 0;
727 if (!state->rt[j].blend_enable)
728 continue;
729
730 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
731 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
732 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
733 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
734
735 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
736 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
737 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
738 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
739 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
740 }
741 }
742 for (int i = 0; i < 8; i++) {
743 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
744 }
745
746 return rstate;
747 }
748
749 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
750 const struct pipe_depth_stencil_alpha_state *state)
751 {
752 struct r600_context *rctx = (struct r600_context *)ctx;
753 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
754 unsigned db_depth_control, alpha_test_control, alpha_ref;
755 unsigned db_render_control;
756 struct r600_pipe_state *rstate;
757
758 if (dsa == NULL) {
759 return NULL;
760 }
761
762 dsa->valuemask[0] = state->stencil[0].valuemask;
763 dsa->valuemask[1] = state->stencil[1].valuemask;
764 dsa->writemask[0] = state->stencil[0].writemask;
765 dsa->writemask[1] = state->stencil[1].writemask;
766
767 rstate = &dsa->rstate;
768
769 rstate->id = R600_PIPE_STATE_DSA;
770 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
771 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
772 S_028800_ZFUNC(state->depth.func);
773
774 /* stencil */
775 if (state->stencil[0].enabled) {
776 db_depth_control |= S_028800_STENCIL_ENABLE(1);
777 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
778 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
779 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
780 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
781
782 if (state->stencil[1].enabled) {
783 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
784 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
785 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
786 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
787 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
788 }
789 }
790
791 /* alpha */
792 alpha_test_control = 0;
793 alpha_ref = 0;
794 if (state->alpha.enabled) {
795 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
796 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
797 alpha_ref = fui(state->alpha.ref_value);
798 }
799 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
800 dsa->alpha_ref = alpha_ref;
801
802 /* misc */
803 db_render_control = 0;
804 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
805 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control);
806 return rstate;
807 }
808
809 static void *evergreen_create_rs_state(struct pipe_context *ctx,
810 const struct pipe_rasterizer_state *state)
811 {
812 struct r600_context *rctx = (struct r600_context *)ctx;
813 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
814 struct r600_pipe_state *rstate;
815 unsigned tmp;
816 unsigned prov_vtx = 1, polygon_dual_mode;
817 float psize_min, psize_max;
818
819 if (rs == NULL) {
820 return NULL;
821 }
822
823 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
824 state->fill_back != PIPE_POLYGON_MODE_FILL);
825
826 if (state->flatshade_first)
827 prov_vtx = 0;
828
829 rstate = &rs->rstate;
830 rs->flatshade = state->flatshade;
831 rs->sprite_coord_enable = state->sprite_coord_enable;
832 rs->two_side = state->light_twoside;
833 rs->clip_plane_enable = state->clip_plane_enable;
834 rs->pa_sc_line_stipple = state->line_stipple_enable ?
835 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
836 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
837 rs->pa_cl_clip_cntl =
838 S_028810_PS_UCP_MODE(3) |
839 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
840 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
841 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
842
843 /* offset */
844 rs->offset_units = state->offset_units;
845 rs->offset_scale = state->offset_scale * 12.0f;
846
847 rstate->id = R600_PIPE_STATE_RASTERIZER;
848 tmp = S_0286D4_FLAT_SHADE_ENA(1);
849 if (state->sprite_coord_enable) {
850 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
851 S_0286D4_PNT_SPRITE_OVRD_X(2) |
852 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
853 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
854 S_0286D4_PNT_SPRITE_OVRD_W(1);
855 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
856 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
857 }
858 }
859 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
860
861 /* point size 12.4 fixed point */
862 tmp = (unsigned)(state->point_size * 8.0);
863 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
864
865 if (state->point_size_per_vertex) {
866 psize_min = util_get_min_point_size(state);
867 psize_max = 8192;
868 } else {
869 /* Force the point size to be as if the vertex output was disabled. */
870 psize_min = state->point_size;
871 psize_max = state->point_size;
872 }
873 /* Divide by two, because 0.5 = 1 pixel. */
874 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
875 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
876 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
877
878 tmp = (unsigned)state->line_width * 8;
879 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
880 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
881 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
882 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
883
884 if (rctx->chip_class == CAYMAN) {
885 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
886 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
887 } else {
888 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
889 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
890 }
891 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
892 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
893 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
894 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
895 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
896 S_028814_FACE(!state->front_ccw) |
897 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
898 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
899 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
900 S_028814_POLY_MODE(polygon_dual_mode) |
901 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
902 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
903 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
904 return rstate;
905 }
906
907 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
908 const struct pipe_sampler_state *state)
909 {
910 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
911 union util_color uc;
912 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
913
914 if (rstate == NULL) {
915 return NULL;
916 }
917
918 rstate->id = R600_PIPE_STATE_SAMPLER;
919 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
920 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
921 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
922 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
923 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
924 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
925 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
926 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
927 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
928 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
929 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
930 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
931 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
932 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
933 NULL, 0);
934 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
935 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
936 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
937 S_03C008_TYPE(1),
938 NULL, 0);
939
940 if (uc.ui) {
941 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
942 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
943 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
944 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
945 }
946 return rstate;
947 }
948
949 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
950 struct pipe_resource *texture,
951 const struct pipe_sampler_view *state)
952 {
953 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
954 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
955 struct r600_pipe_resource_state *rstate;
956 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
957 unsigned format, endian;
958 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
959 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
960 unsigned height, depth, width;
961 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
962
963 if (view == NULL)
964 return NULL;
965 rstate = &view->state;
966
967 /* initialize base object */
968 view->base = *state;
969 view->base.texture = NULL;
970 pipe_reference(NULL, &texture->reference);
971 view->base.texture = texture;
972 view->base.reference.count = 1;
973 view->base.context = ctx;
974
975 swizzle[0] = state->swizzle_r;
976 swizzle[1] = state->swizzle_g;
977 swizzle[2] = state->swizzle_b;
978 swizzle[3] = state->swizzle_a;
979
980 format = r600_translate_texformat(ctx->screen, state->format,
981 swizzle,
982 &word4, &yuv_format);
983 if (format == ~0) {
984 format = 0;
985 }
986
987 if (tmp->is_depth && !tmp->is_flushing_texture) {
988 r600_texture_depth_flush(ctx, texture, TRUE);
989 tmp = tmp->flushed_depth_texture;
990 }
991
992 endian = r600_colorformat_endian_swap(format);
993
994 if (!rscreen->use_surface_alloc) {
995 height = texture->height0;
996 depth = texture->depth0;
997 width = texture->width0;
998 pitch = align(tmp->pitch_in_blocks[0] *
999 util_format_get_blockwidth(state->format), 8);
1000 array_mode = tmp->array_mode[0];
1001 tile_type = tmp->tile_type;
1002 tile_split = 0;
1003 macro_aspect = 0;
1004 bankw = 0;
1005 bankh = 0;
1006 } else {
1007 width = tmp->surface.level[0].npix_x;
1008 height = tmp->surface.level[0].npix_y;
1009 depth = tmp->surface.level[0].npix_z;
1010 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1011 tile_type = tmp->tile_type;
1012
1013 switch (tmp->surface.level[0].mode) {
1014 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1015 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1016 break;
1017 case RADEON_SURF_MODE_2D:
1018 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1019 break;
1020 case RADEON_SURF_MODE_1D:
1021 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1022 break;
1023 case RADEON_SURF_MODE_LINEAR:
1024 default:
1025 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1026 break;
1027 }
1028 tile_split = tmp->surface.tile_split;
1029 macro_aspect = tmp->surface.mtilea;
1030 bankw = tmp->surface.bankw;
1031 bankh = tmp->surface.bankh;
1032 tile_split = eg_tile_split(tile_split);
1033 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1034 bankw = eg_bank_wh(bankw);
1035 bankh = eg_bank_wh(bankh);
1036 }
1037 /* 128 bit formats require tile type = 1 */
1038 if (rscreen->chip_class == CAYMAN) {
1039 if (util_format_get_blocksize(state->format) >= 16)
1040 tile_type = 1;
1041 }
1042 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1043
1044 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1045 height = 1;
1046 depth = texture->array_size;
1047 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1048 depth = texture->array_size;
1049 }
1050
1051 rstate->bo[0] = &tmp->resource;
1052 rstate->bo[1] = &tmp->resource;
1053 rstate->bo_usage[0] = RADEON_USAGE_READ;
1054 rstate->bo_usage[1] = RADEON_USAGE_READ;
1055
1056 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1057 S_030000_PITCH((pitch / 8) - 1) |
1058 S_030000_TEX_WIDTH(width - 1));
1059 if (rscreen->chip_class == CAYMAN)
1060 rstate->val[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1061 else
1062 rstate->val[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1063 rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1064 S_030004_TEX_DEPTH(depth - 1) |
1065 S_030004_ARRAY_MODE(array_mode));
1066 rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1067 if (state->u.tex.last_level) {
1068 rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1069 } else {
1070 rstate->val[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1071 }
1072 rstate->val[4] = (word4 |
1073 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1074 S_030010_ENDIAN_SWAP(endian) |
1075 S_030010_BASE_LEVEL(state->u.tex.first_level));
1076 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1077 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1078 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1079 /* aniso max 16 samples */
1080 rstate->val[6] = (S_030018_MAX_ANISO(4)) |
1081 (S_030018_TILE_SPLIT(tile_split));
1082 rstate->val[7] = S_03001C_DATA_FORMAT(format) |
1083 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1084 S_03001C_BANK_WIDTH(bankw) |
1085 S_03001C_BANK_HEIGHT(bankh) |
1086 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1087 S_03001C_NUM_BANKS(nbanks);
1088
1089 return &view->base;
1090 }
1091
1092 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1093 struct pipe_sampler_view **views)
1094 {
1095 struct r600_context *rctx = (struct r600_context *)ctx;
1096 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1097
1098 for (int i = 0; i < count; i++) {
1099 if (resource[i]) {
1100 r600_context_pipe_state_set_vs_resource(rctx, &resource[i]->state,
1101 i + R600_MAX_CONST_BUFFERS);
1102 }
1103 }
1104 }
1105
1106 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1107 struct pipe_sampler_view **views)
1108 {
1109 struct r600_context *rctx = (struct r600_context *)ctx;
1110 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1111 int i;
1112 int has_depth = 0;
1113
1114 for (i = 0; i < count; i++) {
1115 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1116 if (resource[i]) {
1117 if (((struct r600_resource_texture *)resource[i]->base.texture)->is_depth)
1118 has_depth = 1;
1119 r600_context_pipe_state_set_ps_resource(rctx, &resource[i]->state,
1120 i + R600_MAX_CONST_BUFFERS);
1121 } else
1122 r600_context_pipe_state_set_ps_resource(rctx, NULL,
1123 i + R600_MAX_CONST_BUFFERS);
1124
1125 pipe_sampler_view_reference(
1126 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1127 views[i]);
1128 } else {
1129 if (resource[i]) {
1130 if (((struct r600_resource_texture *)resource[i]->base.texture)->is_depth)
1131 has_depth = 1;
1132 }
1133 }
1134 }
1135 for (i = count; i < NUM_TEX_UNITS; i++) {
1136 if (rctx->ps_samplers.views[i]) {
1137 r600_context_pipe_state_set_ps_resource(rctx, NULL,
1138 i + R600_MAX_CONST_BUFFERS);
1139 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1140 }
1141 }
1142 rctx->have_depth_texture = has_depth;
1143 rctx->ps_samplers.n_views = count;
1144 }
1145
1146 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1147 {
1148 struct r600_context *rctx = (struct r600_context *)ctx;
1149 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1150
1151 if (count)
1152 r600_inval_texture_cache(rctx);
1153
1154 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1155 rctx->ps_samplers.n_samplers = count;
1156
1157 for (int i = 0; i < count; i++) {
1158 evergreen_context_pipe_state_set_ps_sampler(rctx, rstates[i], i);
1159 }
1160 }
1161
1162 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1163 {
1164 struct r600_context *rctx = (struct r600_context *)ctx;
1165 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1166
1167 if (count)
1168 r600_inval_texture_cache(rctx);
1169
1170 for (int i = 0; i < count; i++) {
1171 evergreen_context_pipe_state_set_vs_sampler(rctx, rstates[i], i);
1172 }
1173 }
1174
1175 static void evergreen_set_clip_state(struct pipe_context *ctx,
1176 const struct pipe_clip_state *state)
1177 {
1178 struct r600_context *rctx = (struct r600_context *)ctx;
1179 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1180 struct pipe_constant_buffer cb;
1181
1182 if (rstate == NULL)
1183 return;
1184
1185 rctx->clip = *state;
1186 rstate->id = R600_PIPE_STATE_CLIP;
1187 for (int i = 0; i < 6; i++) {
1188 r600_pipe_state_add_reg(rstate,
1189 R_0285BC_PA_CL_UCP0_X + i * 16,
1190 fui(state->ucp[i][0]));
1191 r600_pipe_state_add_reg(rstate,
1192 R_0285C0_PA_CL_UCP0_Y + i * 16,
1193 fui(state->ucp[i][1]) );
1194 r600_pipe_state_add_reg(rstate,
1195 R_0285C4_PA_CL_UCP0_Z + i * 16,
1196 fui(state->ucp[i][2]));
1197 r600_pipe_state_add_reg(rstate,
1198 R_0285C8_PA_CL_UCP0_W + i * 16,
1199 fui(state->ucp[i][3]));
1200 }
1201
1202 free(rctx->states[R600_PIPE_STATE_CLIP]);
1203 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1204 r600_context_pipe_state_set(rctx, rstate);
1205
1206 cb.buffer = NULL;
1207 cb.user_buffer = state->ucp;
1208 cb.buffer_offset = 0;
1209 cb.buffer_size = 4*4*8;
1210 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1211 pipe_resource_reference(&cb.buffer, NULL);
1212 }
1213
1214 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1215 const struct pipe_poly_stipple *state)
1216 {
1217 }
1218
1219 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1220 {
1221 }
1222
1223 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1224 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1225 uint32_t *tl, uint32_t *br)
1226 {
1227 /* EG hw workaround */
1228 if (br_x == 0)
1229 tl_x = 1;
1230 if (br_y == 0)
1231 tl_y = 1;
1232
1233 /* cayman hw workaround */
1234 if (rctx->chip_class == CAYMAN) {
1235 if (br_x == 1 && br_y == 1)
1236 br_x = 2;
1237 }
1238
1239 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1240 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1241 }
1242
1243 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1244 const struct pipe_scissor_state *state)
1245 {
1246 struct r600_context *rctx = (struct r600_context *)ctx;
1247 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1248 uint32_t tl, br;
1249
1250 if (rstate == NULL)
1251 return;
1252
1253 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1254
1255 rstate->id = R600_PIPE_STATE_SCISSOR;
1256 r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1257 r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1258
1259 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1260 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1261 r600_context_pipe_state_set(rctx, rstate);
1262 }
1263
1264 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1265 const struct pipe_viewport_state *state)
1266 {
1267 struct r600_context *rctx = (struct r600_context *)ctx;
1268 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1269
1270 if (rstate == NULL)
1271 return;
1272
1273 rctx->viewport = *state;
1274 rstate->id = R600_PIPE_STATE_VIEWPORT;
1275 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1276 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1277 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1278 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1279 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1280 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1281
1282 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1283 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1284 r600_context_pipe_state_set(rctx, rstate);
1285 }
1286
1287 static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1288 const struct pipe_framebuffer_state *state, int cb)
1289 {
1290 struct r600_screen *rscreen = rctx->screen;
1291 struct r600_resource_texture *rtex;
1292 struct r600_surface *surf;
1293 unsigned level = state->cbufs[cb]->u.tex.level;
1294 unsigned pitch, slice;
1295 unsigned color_info, color_attrib;
1296 unsigned format, swap, ntype, endian;
1297 uint64_t offset;
1298 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1299 const struct util_format_description *desc;
1300 int i;
1301 unsigned blend_clamp = 0, blend_bypass = 0;
1302
1303 surf = (struct r600_surface *)state->cbufs[cb];
1304 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1305
1306 if (rtex->is_depth)
1307 rctx->have_depth_fb = TRUE;
1308
1309 if (rtex->is_depth && !rtex->is_flushing_texture) {
1310 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1311 rtex = rtex->flushed_depth_texture;
1312 }
1313
1314 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1315 if (!rscreen->use_surface_alloc) {
1316 offset = r600_texture_get_offset(rtex,
1317 level, state->cbufs[cb]->u.tex.first_layer);
1318 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1319 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1320 if (slice) {
1321 slice = slice - 1;
1322 }
1323 color_info = S_028C70_ARRAY_MODE(rtex->array_mode[level]);
1324 tile_split = 0;
1325 macro_aspect = 0;
1326 bankw = 0;
1327 bankh = 0;
1328 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1329 tile_type = rtex->tile_type;
1330 } else {
1331 /* workaround for linear buffers */
1332 tile_type = 1;
1333 }
1334 } else {
1335 offset = rtex->surface.level[level].offset;
1336 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1337 offset += rtex->surface.level[level].slice_size *
1338 state->cbufs[cb]->u.tex.first_layer;
1339 }
1340 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1341 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1342 if (slice) {
1343 slice = slice - 1;
1344 }
1345 color_info = 0;
1346 switch (rtex->surface.level[level].mode) {
1347 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1348 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1349 tile_type = 1;
1350 break;
1351 case RADEON_SURF_MODE_1D:
1352 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1353 tile_type = rtex->tile_type;
1354 break;
1355 case RADEON_SURF_MODE_2D:
1356 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1357 tile_type = rtex->tile_type;
1358 break;
1359 case RADEON_SURF_MODE_LINEAR:
1360 default:
1361 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1362 tile_type = 1;
1363 break;
1364 }
1365 tile_split = rtex->surface.tile_split;
1366 macro_aspect = rtex->surface.mtilea;
1367 bankw = rtex->surface.bankw;
1368 bankh = rtex->surface.bankh;
1369 tile_split = eg_tile_split(tile_split);
1370 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1371 bankw = eg_bank_wh(bankw);
1372 bankh = eg_bank_wh(bankh);
1373 }
1374 /* 128 bit formats require tile type = 1 */
1375 if (rscreen->chip_class == CAYMAN) {
1376 if (util_format_get_blocksize(surf->base.format) >= 16)
1377 tile_type = 1;
1378 }
1379 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1380 desc = util_format_description(surf->base.format);
1381 for (i = 0; i < 4; i++) {
1382 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1383 break;
1384 }
1385 }
1386
1387 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1388 S_028C74_NUM_BANKS(nbanks) |
1389 S_028C74_BANK_WIDTH(bankw) |
1390 S_028C74_BANK_HEIGHT(bankh) |
1391 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1392 S_028C74_NON_DISP_TILING_ORDER(tile_type);
1393
1394 ntype = V_028C70_NUMBER_UNORM;
1395 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1396 ntype = V_028C70_NUMBER_SRGB;
1397 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1398 if (desc->channel[i].normalized)
1399 ntype = V_028C70_NUMBER_SNORM;
1400 else if (desc->channel[i].pure_integer)
1401 ntype = V_028C70_NUMBER_SINT;
1402 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1403 if (desc->channel[i].normalized)
1404 ntype = V_028C70_NUMBER_UNORM;
1405 else if (desc->channel[i].pure_integer)
1406 ntype = V_028C70_NUMBER_UINT;
1407 }
1408
1409 format = r600_translate_colorformat(surf->base.format);
1410 swap = r600_translate_colorswap(surf->base.format);
1411 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1412 endian = ENDIAN_NONE;
1413 } else {
1414 endian = r600_colorformat_endian_swap(format);
1415 }
1416
1417 /* blend clamp should be set for all NORM/SRGB types */
1418 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1419 ntype == V_028C70_NUMBER_SRGB)
1420 blend_clamp = 1;
1421
1422 /* set blend bypass according to docs if SINT/UINT or
1423 8/24 COLOR variants */
1424 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1425 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1426 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1427 blend_clamp = 0;
1428 blend_bypass = 1;
1429 }
1430
1431 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT)
1432 rctx->sx_alpha_test_control |= S_028410_ALPHA_TEST_BYPASS(1);
1433 else
1434 rctx->sx_alpha_test_control &= C_028410_ALPHA_TEST_BYPASS;
1435
1436 color_info |= S_028C70_FORMAT(format) |
1437 S_028C70_COMP_SWAP(swap) |
1438 S_028C70_BLEND_CLAMP(blend_clamp) |
1439 S_028C70_BLEND_BYPASS(blend_bypass) |
1440 S_028C70_NUMBER_TYPE(ntype) |
1441 S_028C70_ENDIAN(endian);
1442
1443 /* EXPORT_NORM is an optimzation that can be enabled for better
1444 * performance in certain cases.
1445 * EXPORT_NORM can be enabled if:
1446 * - 11-bit or smaller UNORM/SNORM/SRGB
1447 * - 16-bit or smaller FLOAT
1448 */
1449 /* XXX: This should probably be the same for all CBs if we want
1450 * useful alpha tests. */
1451 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1452 ((desc->channel[i].size < 12 &&
1453 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1454 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1455 (desc->channel[i].size < 17 &&
1456 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1457 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1458 rctx->export_16bpc = true;
1459 } else {
1460 rctx->export_16bpc = false;
1461 }
1462 rctx->alpha_ref_dirty = true;
1463
1464 /* for possible dual-src MRT */
1465 if (cb == 0 && rctx->framebuffer.nr_cbufs == 1) {
1466 r600_pipe_state_add_reg_bo(rstate,
1467 R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1468 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1469 }
1470
1471 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1472 offset >>= 8;
1473
1474 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1475 r600_pipe_state_add_reg_bo(rstate,
1476 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1477 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1478 r600_pipe_state_add_reg(rstate,
1479 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1480 0x0);
1481 r600_pipe_state_add_reg_bo(rstate,
1482 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1483 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1484 r600_pipe_state_add_reg(rstate,
1485 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1486 S_028C64_PITCH_TILE_MAX(pitch));
1487 r600_pipe_state_add_reg(rstate,
1488 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1489 S_028C68_SLICE_TILE_MAX(slice));
1490 if (!rscreen->use_surface_alloc) {
1491 r600_pipe_state_add_reg(rstate,
1492 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1493 0x00000000);
1494 } else {
1495 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1496 r600_pipe_state_add_reg(rstate,
1497 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1498 0x00000000);
1499 } else {
1500 r600_pipe_state_add_reg(rstate,
1501 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1502 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1503 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1504 }
1505 }
1506 r600_pipe_state_add_reg_bo(rstate,
1507 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1508 color_attrib,
1509 &rtex->resource, RADEON_USAGE_READWRITE);
1510 }
1511
1512 static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1513 const struct pipe_framebuffer_state *state)
1514 {
1515 struct r600_screen *rscreen = rctx->screen;
1516 struct r600_resource_texture *rtex;
1517 struct r600_surface *surf;
1518 uint64_t offset;
1519 unsigned level, first_layer, pitch, slice, format, array_mode;
1520 unsigned macro_aspect, tile_split, bankh, bankw, z_info, nbanks;
1521
1522 if (state->zsbuf == NULL)
1523 return;
1524
1525 surf = (struct r600_surface *)state->zsbuf;
1526 level = surf->base.u.tex.level;
1527 rtex = (struct r600_resource_texture*)surf->base.texture;
1528 first_layer = surf->base.u.tex.first_layer;
1529 format = r600_translate_dbformat(rtex->real_format);
1530
1531 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1532 /* XXX remove this once tiling is properly supported */
1533 if (!rscreen->use_surface_alloc) {
1534 /* XXX remove this once tiling is properly supported */
1535 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1536 V_028C70_ARRAY_1D_TILED_THIN1;
1537
1538 offset += r600_texture_get_offset(rtex, level, first_layer);
1539 pitch = (rtex->pitch_in_blocks[level] / 8) - 1;
1540 slice = ((rtex->pitch_in_blocks[level] * surf->aligned_height) / 64);
1541 if (slice) {
1542 slice = slice - 1;
1543 }
1544 tile_split = 0;
1545 macro_aspect = 0;
1546 bankw = 0;
1547 bankh = 0;
1548 } else {
1549 offset += rtex->surface.level[level].offset;
1550 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1551 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1552 if (slice) {
1553 slice = slice - 1;
1554 }
1555 switch (rtex->surface.level[level].mode) {
1556 case RADEON_SURF_MODE_2D:
1557 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1558 break;
1559 case RADEON_SURF_MODE_1D:
1560 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1561 case RADEON_SURF_MODE_LINEAR:
1562 default:
1563 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1564 break;
1565 }
1566 tile_split = rtex->surface.tile_split;
1567 macro_aspect = rtex->surface.mtilea;
1568 bankw = rtex->surface.bankw;
1569 bankh = rtex->surface.bankh;
1570 tile_split = eg_tile_split(tile_split);
1571 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1572 bankw = eg_bank_wh(bankw);
1573 bankh = eg_bank_wh(bankh);
1574 }
1575 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1576 offset >>= 8;
1577
1578 z_info = S_028040_ARRAY_MODE(array_mode) |
1579 S_028040_FORMAT(format) |
1580 S_028040_TILE_SPLIT(tile_split)|
1581 S_028040_NUM_BANKS(nbanks) |
1582 S_028040_BANK_WIDTH(bankw) |
1583 S_028040_BANK_HEIGHT(bankh) |
1584 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1585
1586 r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE,
1587 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1588 r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE,
1589 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1590 if (!rscreen->use_surface_alloc) {
1591 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1592 0x00000000);
1593 } else {
1594 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1595 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1596 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1597 }
1598
1599 if (rtex->stencil) {
1600 uint64_t stencil_offset =
1601 r600_texture_get_offset(rtex->stencil, level, first_layer);
1602 unsigned stile_split;
1603
1604 stile_split = eg_tile_split(rtex->stencil->surface.tile_split);
1605 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1606 stencil_offset >>= 8;
1607
1608 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
1609 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1610 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1611 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1612 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1613 1 | S_028044_TILE_SPLIT(stile_split),
1614 &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1615 } else {
1616 if (rscreen->use_surface_alloc && rtex->surface.flags & RADEON_SURF_SBUFFER) {
1617 uint64_t stencil_offset = rtex->surface.stencil_offset;
1618 unsigned stile_split = rtex->surface.stencil_tile_split;
1619
1620 stile_split = eg_tile_split(stile_split);
1621 stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1622 stencil_offset += rtex->surface.level[level].offset / 4;
1623 stencil_offset >>= 8;
1624
1625 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
1626 stencil_offset, &rtex->resource,
1627 RADEON_USAGE_READWRITE);
1628 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1629 stencil_offset, &rtex->resource,
1630 RADEON_USAGE_READWRITE);
1631 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1632 1 | S_028044_TILE_SPLIT(stile_split),
1633 &rtex->resource,
1634 RADEON_USAGE_READWRITE);
1635 } else {
1636 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
1637 offset, &rtex->resource,
1638 RADEON_USAGE_READWRITE);
1639 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1640 offset, &rtex->resource,
1641 RADEON_USAGE_READWRITE);
1642 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1643 0, NULL, RADEON_USAGE_READWRITE);
1644 }
1645 }
1646
1647 r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, z_info,
1648 &rtex->resource, RADEON_USAGE_READWRITE);
1649 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1650 S_028058_PITCH_TILE_MAX(pitch));
1651 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1652 S_02805C_SLICE_TILE_MAX(slice));
1653 }
1654
1655 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1656 const struct pipe_framebuffer_state *state)
1657 {
1658 struct r600_context *rctx = (struct r600_context *)ctx;
1659 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1660 uint32_t tl, br;
1661
1662 if (rstate == NULL)
1663 return;
1664
1665 r600_flush_framebuffer(rctx, false);
1666
1667 /* unreference old buffer and reference new one */
1668 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1669
1670 util_copy_framebuffer_state(&rctx->framebuffer, state);
1671
1672 /* build states */
1673 rctx->have_depth_fb = 0;
1674 rctx->nr_cbufs = state->nr_cbufs;
1675 for (int i = 0; i < state->nr_cbufs; i++) {
1676 evergreen_cb(rctx, rstate, state, i);
1677 }
1678 if (state->zsbuf) {
1679 evergreen_db(rctx, rstate, state);
1680 }
1681
1682 rctx->fb_cb_shader_mask = 0;
1683 for (int i = 0; i < state->nr_cbufs; i++) {
1684 rctx->fb_cb_shader_mask |= 0xf << (i * 4);
1685 }
1686
1687 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1688
1689 r600_pipe_state_add_reg(rstate,
1690 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1691 r600_pipe_state_add_reg(rstate,
1692 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1693
1694 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1695 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1696 r600_context_pipe_state_set(rctx, rstate);
1697
1698 if (state->zsbuf) {
1699 evergreen_polygon_offset_update(rctx);
1700 }
1701 }
1702
1703 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1704 {
1705 struct radeon_winsys_cs *cs = rctx->cs;
1706 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1707 unsigned db_count_control = 0;
1708 unsigned db_render_override =
1709 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1710 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1711 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1712
1713 if (a->occlusion_query_enabled) {
1714 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1715 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1716 }
1717
1718 r600_write_context_reg(cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1719 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1720 }
1721
1722 static void evergreen_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1723 {
1724 struct radeon_winsys_cs *cs = rctx->cs;
1725 struct pipe_vertex_buffer *vb = rctx->vertex_buffer;
1726 unsigned count = rctx->nr_vertex_buffers;
1727 unsigned i;
1728 uint64_t va;
1729
1730 for (i = 0; i < count; i++) {
1731 struct r600_resource *rbuffer = (struct r600_resource*)vb[i].buffer;
1732
1733 if (!rbuffer) {
1734 continue;
1735 }
1736
1737 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1738 va += vb[i].buffer_offset;
1739
1740 /* fetch resources start at index 992 */
1741 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1742 r600_write_value(cs, (992 + i) * 8);
1743 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1744 r600_write_value(cs, rbuffer->buf->size - vb[i].buffer_offset - 1); /* RESOURCEi_WORD1 */
1745 r600_write_value(cs, /* RESOURCEi_WORD2 */
1746 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1747 S_030008_STRIDE(vb[i].stride) |
1748 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1749 r600_write_value(cs, /* RESOURCEi_WORD3 */
1750 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1751 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1752 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1753 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1754 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1755 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1756 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1757 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1758
1759 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1760 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1761 }
1762 }
1763
1764 static void evergreen_emit_constant_buffer(struct r600_context *rctx,
1765 struct r600_constbuf_state *state,
1766 unsigned buffer_id_base,
1767 unsigned reg_alu_constbuf_size,
1768 unsigned reg_alu_const_cache)
1769 {
1770 struct radeon_winsys_cs *cs = rctx->cs;
1771 uint32_t dirty_mask = state->dirty_mask;
1772
1773 while (dirty_mask) {
1774 struct pipe_constant_buffer *cb;
1775 struct r600_resource *rbuffer;
1776 uint64_t va;
1777 unsigned buffer_index = ffs(dirty_mask) - 1;
1778
1779 cb = &state->cb[buffer_index];
1780 rbuffer = (struct r600_resource*)cb->buffer;
1781 assert(rbuffer);
1782
1783 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1784 va += cb->buffer_offset;
1785
1786 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1787 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1788 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
1789
1790 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1791 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1792
1793 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1794 r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
1795 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1796 r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1797 r600_write_value(cs, /* RESOURCEi_WORD2 */
1798 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1799 S_030008_STRIDE(16) |
1800 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1801 r600_write_value(cs, /* RESOURCEi_WORD3 */
1802 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1803 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1804 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1805 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1806 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1807 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1808 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1809 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1810
1811 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1812 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1813
1814 dirty_mask &= ~(1 << buffer_index);
1815 }
1816 state->dirty_mask = 0;
1817 }
1818
1819 static void evergreen_emit_vs_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
1820 {
1821 evergreen_emit_constant_buffer(rctx, &rctx->vs_constbuf_state, 176,
1822 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1823 R_028980_ALU_CONST_CACHE_VS_0);
1824 }
1825
1826 static void evergreen_emit_ps_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
1827 {
1828 evergreen_emit_constant_buffer(rctx, &rctx->ps_constbuf_state, 0,
1829 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1830 R_028940_ALU_CONST_CACHE_PS_0);
1831 }
1832
1833 void evergreen_init_state_functions(struct r600_context *rctx)
1834 {
1835 r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 6, 0);
1836 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1837 r600_init_atom(&rctx->vertex_buffer_state, evergreen_emit_vertex_buffers, 0, 0);
1838 r600_init_atom(&rctx->vs_constbuf_state.atom, evergreen_emit_vs_constant_buffer, 0, 0);
1839 r600_init_atom(&rctx->ps_constbuf_state.atom, evergreen_emit_ps_constant_buffer, 0, 0);
1840
1841 rctx->context.create_blend_state = evergreen_create_blend_state;
1842 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1843 rctx->context.create_fs_state = r600_create_shader_state;
1844 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1845 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1846 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1847 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1848 rctx->context.create_vs_state = r600_create_shader_state;
1849 rctx->context.bind_blend_state = r600_bind_blend_state;
1850 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1851 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1852 rctx->context.bind_fs_state = r600_bind_ps_shader;
1853 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1854 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1855 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1856 rctx->context.bind_vs_state = r600_bind_vs_shader;
1857 rctx->context.delete_blend_state = r600_delete_state;
1858 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1859 rctx->context.delete_fs_state = r600_delete_ps_shader;
1860 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1861 rctx->context.delete_sampler_state = r600_delete_state;
1862 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1863 rctx->context.delete_vs_state = r600_delete_vs_shader;
1864 rctx->context.set_blend_color = r600_set_blend_color;
1865 rctx->context.set_clip_state = evergreen_set_clip_state;
1866 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1867 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1868 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1869 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1870 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1871 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1872 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1873 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1874 rctx->context.set_index_buffer = r600_set_index_buffer;
1875 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1876 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1877 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1878 rctx->context.texture_barrier = r600_texture_barrier;
1879 rctx->context.create_stream_output_target = r600_create_so_target;
1880 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1881 rctx->context.set_stream_output_targets = r600_set_so_targets;
1882 }
1883
1884 static void cayman_init_atom_start_cs(struct r600_context *rctx)
1885 {
1886 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1887
1888 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1889
1890 /* This must be first. */
1891 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1892 r600_store_value(cb, 0x80000000);
1893 r600_store_value(cb, 0x80000000);
1894
1895 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
1896 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
1897 /* always set the temp clauses */
1898 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
1899
1900 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
1901 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
1902 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
1903
1904 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
1905
1906 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
1907
1908 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
1909 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
1910 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
1911 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
1912 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
1913 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
1914 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
1915 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
1916 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
1917 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
1918 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
1919 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
1920 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
1921 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
1922
1923 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
1924 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
1925 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
1926
1927 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
1928 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
1929 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
1930
1931 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
1932
1933 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
1934
1935 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1936 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
1937 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
1938
1939 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
1940 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
1941 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
1942
1943 r600_store_context_reg(cb, CM_R_028804_DB_EQAA, 0x110000);
1944
1945 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
1946 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
1947 r600_store_value(cb, 0);
1948 r600_store_value(cb, 0);
1949 r600_store_value(cb, 0);
1950 r600_store_value(cb, 0);
1951 r600_store_value(cb, 0);
1952 r600_store_value(cb, 0);
1953 r600_store_value(cb, 0);
1954 r600_store_value(cb, 0);
1955 r600_store_value(cb, 0);
1956 r600_store_value(cb, 0);
1957 r600_store_value(cb, 0);
1958 r600_store_value(cb, 0);
1959 r600_store_value(cb, 0);
1960 r600_store_value(cb, 0);
1961 r600_store_value(cb, 0);
1962 r600_store_value(cb, 0);
1963 r600_store_value(cb, 0);
1964 r600_store_value(cb, 0);
1965 r600_store_value(cb, 0);
1966 r600_store_value(cb, 0);
1967 r600_store_value(cb, 0);
1968 r600_store_value(cb, 0);
1969 r600_store_value(cb, 0);
1970 r600_store_value(cb, 0);
1971 r600_store_value(cb, 0);
1972 r600_store_value(cb, 0);
1973 r600_store_value(cb, 0);
1974 r600_store_value(cb, 0);
1975 r600_store_value(cb, 0);
1976 r600_store_value(cb, 0);
1977 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
1978 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
1979 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
1980
1981 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
1982
1983 r600_store_context_reg_seq(cb, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
1984 r600_store_value(cb, ~0); /* CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 */
1985 r600_store_value(cb, ~0); /* CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 */
1986
1987 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
1988 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
1989 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
1990
1991 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
1992
1993 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
1994 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
1995 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
1996 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
1997
1998 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
1999 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2000
2001 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2002 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2003 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2004
2005 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2006 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2007 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2008 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2009
2010 r600_store_context_reg_seq(cb, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
2011 r600_store_value(cb, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2012 r600_store_value(cb, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2013
2014 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2015 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2016 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2017 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2018 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2019
2020 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2021 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2022 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2023
2024 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2025 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2026 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2027
2028 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
2029 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
2030 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2031
2032 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2033 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2034
2035 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2036 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2037 }
2038
2039 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2040 {
2041 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2042 int ps_prio;
2043 int vs_prio;
2044 int gs_prio;
2045 int es_prio;
2046 int hs_prio, cs_prio, ls_prio;
2047 int num_ps_gprs;
2048 int num_vs_gprs;
2049 int num_gs_gprs;
2050 int num_es_gprs;
2051 int num_hs_gprs;
2052 int num_ls_gprs;
2053 int num_temp_gprs;
2054 int num_ps_threads;
2055 int num_vs_threads;
2056 int num_gs_threads;
2057 int num_es_threads;
2058 int num_hs_threads;
2059 int num_ls_threads;
2060 int num_ps_stack_entries;
2061 int num_vs_stack_entries;
2062 int num_gs_stack_entries;
2063 int num_es_stack_entries;
2064 int num_hs_stack_entries;
2065 int num_ls_stack_entries;
2066 enum radeon_family family;
2067 unsigned tmp;
2068
2069 if (rctx->chip_class == CAYMAN) {
2070 cayman_init_atom_start_cs(rctx);
2071 return;
2072 }
2073
2074 r600_init_command_buffer(cb, 256, EMIT_EARLY);
2075
2076 /* This must be first. */
2077 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2078 r600_store_value(cb, 0x80000000);
2079 r600_store_value(cb, 0x80000000);
2080
2081 family = rctx->family;
2082 ps_prio = 0;
2083 vs_prio = 1;
2084 gs_prio = 2;
2085 es_prio = 3;
2086 hs_prio = 0;
2087 ls_prio = 0;
2088 cs_prio = 0;
2089
2090 switch (family) {
2091 case CHIP_CEDAR:
2092 default:
2093 num_ps_gprs = 93;
2094 num_vs_gprs = 46;
2095 num_temp_gprs = 4;
2096 num_gs_gprs = 31;
2097 num_es_gprs = 31;
2098 num_hs_gprs = 23;
2099 num_ls_gprs = 23;
2100 num_ps_threads = 96;
2101 num_vs_threads = 16;
2102 num_gs_threads = 16;
2103 num_es_threads = 16;
2104 num_hs_threads = 16;
2105 num_ls_threads = 16;
2106 num_ps_stack_entries = 42;
2107 num_vs_stack_entries = 42;
2108 num_gs_stack_entries = 42;
2109 num_es_stack_entries = 42;
2110 num_hs_stack_entries = 42;
2111 num_ls_stack_entries = 42;
2112 break;
2113 case CHIP_REDWOOD:
2114 num_ps_gprs = 93;
2115 num_vs_gprs = 46;
2116 num_temp_gprs = 4;
2117 num_gs_gprs = 31;
2118 num_es_gprs = 31;
2119 num_hs_gprs = 23;
2120 num_ls_gprs = 23;
2121 num_ps_threads = 128;
2122 num_vs_threads = 20;
2123 num_gs_threads = 20;
2124 num_es_threads = 20;
2125 num_hs_threads = 20;
2126 num_ls_threads = 20;
2127 num_ps_stack_entries = 42;
2128 num_vs_stack_entries = 42;
2129 num_gs_stack_entries = 42;
2130 num_es_stack_entries = 42;
2131 num_hs_stack_entries = 42;
2132 num_ls_stack_entries = 42;
2133 break;
2134 case CHIP_JUNIPER:
2135 num_ps_gprs = 93;
2136 num_vs_gprs = 46;
2137 num_temp_gprs = 4;
2138 num_gs_gprs = 31;
2139 num_es_gprs = 31;
2140 num_hs_gprs = 23;
2141 num_ls_gprs = 23;
2142 num_ps_threads = 128;
2143 num_vs_threads = 20;
2144 num_gs_threads = 20;
2145 num_es_threads = 20;
2146 num_hs_threads = 20;
2147 num_ls_threads = 20;
2148 num_ps_stack_entries = 85;
2149 num_vs_stack_entries = 85;
2150 num_gs_stack_entries = 85;
2151 num_es_stack_entries = 85;
2152 num_hs_stack_entries = 85;
2153 num_ls_stack_entries = 85;
2154 break;
2155 case CHIP_CYPRESS:
2156 case CHIP_HEMLOCK:
2157 num_ps_gprs = 93;
2158 num_vs_gprs = 46;
2159 num_temp_gprs = 4;
2160 num_gs_gprs = 31;
2161 num_es_gprs = 31;
2162 num_hs_gprs = 23;
2163 num_ls_gprs = 23;
2164 num_ps_threads = 128;
2165 num_vs_threads = 20;
2166 num_gs_threads = 20;
2167 num_es_threads = 20;
2168 num_hs_threads = 20;
2169 num_ls_threads = 20;
2170 num_ps_stack_entries = 85;
2171 num_vs_stack_entries = 85;
2172 num_gs_stack_entries = 85;
2173 num_es_stack_entries = 85;
2174 num_hs_stack_entries = 85;
2175 num_ls_stack_entries = 85;
2176 break;
2177 case CHIP_PALM:
2178 num_ps_gprs = 93;
2179 num_vs_gprs = 46;
2180 num_temp_gprs = 4;
2181 num_gs_gprs = 31;
2182 num_es_gprs = 31;
2183 num_hs_gprs = 23;
2184 num_ls_gprs = 23;
2185 num_ps_threads = 96;
2186 num_vs_threads = 16;
2187 num_gs_threads = 16;
2188 num_es_threads = 16;
2189 num_hs_threads = 16;
2190 num_ls_threads = 16;
2191 num_ps_stack_entries = 42;
2192 num_vs_stack_entries = 42;
2193 num_gs_stack_entries = 42;
2194 num_es_stack_entries = 42;
2195 num_hs_stack_entries = 42;
2196 num_ls_stack_entries = 42;
2197 break;
2198 case CHIP_SUMO:
2199 num_ps_gprs = 93;
2200 num_vs_gprs = 46;
2201 num_temp_gprs = 4;
2202 num_gs_gprs = 31;
2203 num_es_gprs = 31;
2204 num_hs_gprs = 23;
2205 num_ls_gprs = 23;
2206 num_ps_threads = 96;
2207 num_vs_threads = 25;
2208 num_gs_threads = 25;
2209 num_es_threads = 25;
2210 num_hs_threads = 25;
2211 num_ls_threads = 25;
2212 num_ps_stack_entries = 42;
2213 num_vs_stack_entries = 42;
2214 num_gs_stack_entries = 42;
2215 num_es_stack_entries = 42;
2216 num_hs_stack_entries = 42;
2217 num_ls_stack_entries = 42;
2218 break;
2219 case CHIP_SUMO2:
2220 num_ps_gprs = 93;
2221 num_vs_gprs = 46;
2222 num_temp_gprs = 4;
2223 num_gs_gprs = 31;
2224 num_es_gprs = 31;
2225 num_hs_gprs = 23;
2226 num_ls_gprs = 23;
2227 num_ps_threads = 96;
2228 num_vs_threads = 25;
2229 num_gs_threads = 25;
2230 num_es_threads = 25;
2231 num_hs_threads = 25;
2232 num_ls_threads = 25;
2233 num_ps_stack_entries = 85;
2234 num_vs_stack_entries = 85;
2235 num_gs_stack_entries = 85;
2236 num_es_stack_entries = 85;
2237 num_hs_stack_entries = 85;
2238 num_ls_stack_entries = 85;
2239 break;
2240 case CHIP_BARTS:
2241 num_ps_gprs = 93;
2242 num_vs_gprs = 46;
2243 num_temp_gprs = 4;
2244 num_gs_gprs = 31;
2245 num_es_gprs = 31;
2246 num_hs_gprs = 23;
2247 num_ls_gprs = 23;
2248 num_ps_threads = 128;
2249 num_vs_threads = 20;
2250 num_gs_threads = 20;
2251 num_es_threads = 20;
2252 num_hs_threads = 20;
2253 num_ls_threads = 20;
2254 num_ps_stack_entries = 85;
2255 num_vs_stack_entries = 85;
2256 num_gs_stack_entries = 85;
2257 num_es_stack_entries = 85;
2258 num_hs_stack_entries = 85;
2259 num_ls_stack_entries = 85;
2260 break;
2261 case CHIP_TURKS:
2262 num_ps_gprs = 93;
2263 num_vs_gprs = 46;
2264 num_temp_gprs = 4;
2265 num_gs_gprs = 31;
2266 num_es_gprs = 31;
2267 num_hs_gprs = 23;
2268 num_ls_gprs = 23;
2269 num_ps_threads = 128;
2270 num_vs_threads = 20;
2271 num_gs_threads = 20;
2272 num_es_threads = 20;
2273 num_hs_threads = 20;
2274 num_ls_threads = 20;
2275 num_ps_stack_entries = 42;
2276 num_vs_stack_entries = 42;
2277 num_gs_stack_entries = 42;
2278 num_es_stack_entries = 42;
2279 num_hs_stack_entries = 42;
2280 num_ls_stack_entries = 42;
2281 break;
2282 case CHIP_CAICOS:
2283 num_ps_gprs = 93;
2284 num_vs_gprs = 46;
2285 num_temp_gprs = 4;
2286 num_gs_gprs = 31;
2287 num_es_gprs = 31;
2288 num_hs_gprs = 23;
2289 num_ls_gprs = 23;
2290 num_ps_threads = 128;
2291 num_vs_threads = 10;
2292 num_gs_threads = 10;
2293 num_es_threads = 10;
2294 num_hs_threads = 10;
2295 num_ls_threads = 10;
2296 num_ps_stack_entries = 42;
2297 num_vs_stack_entries = 42;
2298 num_gs_stack_entries = 42;
2299 num_es_stack_entries = 42;
2300 num_hs_stack_entries = 42;
2301 num_ls_stack_entries = 42;
2302 break;
2303 }
2304
2305 tmp = 0;
2306 switch (family) {
2307 case CHIP_CEDAR:
2308 case CHIP_PALM:
2309 case CHIP_SUMO:
2310 case CHIP_SUMO2:
2311 case CHIP_CAICOS:
2312 break;
2313 default:
2314 tmp |= S_008C00_VC_ENABLE(1);
2315 break;
2316 }
2317 tmp |= S_008C00_EXPORT_SRC_C(1);
2318 tmp |= S_008C00_CS_PRIO(cs_prio);
2319 tmp |= S_008C00_LS_PRIO(ls_prio);
2320 tmp |= S_008C00_HS_PRIO(hs_prio);
2321 tmp |= S_008C00_PS_PRIO(ps_prio);
2322 tmp |= S_008C00_VS_PRIO(vs_prio);
2323 tmp |= S_008C00_GS_PRIO(gs_prio);
2324 tmp |= S_008C00_ES_PRIO(es_prio);
2325
2326 /* enable dynamic GPR resource management */
2327 if (rctx->screen->info.drm_minor >= 7) {
2328 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2329 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2330 /* always set temp clauses */
2331 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2332 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2333 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2334 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2335 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2336 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2337 S_028838_PS_GPRS(0x1e) |
2338 S_028838_VS_GPRS(0x1e) |
2339 S_028838_GS_GPRS(0x1e) |
2340 S_028838_ES_GPRS(0x1e) |
2341 S_028838_HS_GPRS(0x1e) |
2342 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2343 } else {
2344 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2345 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2346
2347 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2348 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2349 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2350 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2351
2352 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2353 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2354 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2355
2356 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2357 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2358 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2359 }
2360
2361 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2362 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2363 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2364 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2365 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2366 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2367
2368 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2369 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2370 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2371
2372 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2373 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2374 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2375
2376 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2377 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2378 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2379
2380 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2381 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2382 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2383
2384 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2385 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2386
2387 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2388 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2389
2390 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2391
2392 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2393 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2394 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2395 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2396 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2397 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2398 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2399
2400 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2401 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2402 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2403 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2404 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2405
2406 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2407 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2408 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2409 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2410 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2411 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2412 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2413 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2414 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2415 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2416 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2417 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2418 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2419 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2420
2421 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2422 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2423 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2424
2425 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2426 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2427 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2428
2429 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2430
2431 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2432 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2433 r600_store_value(cb, 0);
2434 r600_store_value(cb, 0);
2435 r600_store_value(cb, 0);
2436 r600_store_value(cb, 0);
2437 r600_store_value(cb, 0);
2438 r600_store_value(cb, 0);
2439 r600_store_value(cb, 0);
2440 r600_store_value(cb, 0);
2441 r600_store_value(cb, 0);
2442 r600_store_value(cb, 0);
2443 r600_store_value(cb, 0);
2444 r600_store_value(cb, 0);
2445 r600_store_value(cb, 0);
2446 r600_store_value(cb, 0);
2447 r600_store_value(cb, 0);
2448 r600_store_value(cb, 0);
2449 r600_store_value(cb, 0);
2450 r600_store_value(cb, 0);
2451 r600_store_value(cb, 0);
2452 r600_store_value(cb, 0);
2453 r600_store_value(cb, 0);
2454 r600_store_value(cb, 0);
2455 r600_store_value(cb, 0);
2456 r600_store_value(cb, 0);
2457 r600_store_value(cb, 0);
2458 r600_store_value(cb, 0);
2459 r600_store_value(cb, 0);
2460 r600_store_value(cb, 0);
2461 r600_store_value(cb, 0);
2462 r600_store_value(cb, 0);
2463 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2464 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2465 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2466
2467 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2468
2469 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2470 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2471 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2472
2473 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2474 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2475 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2476
2477 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2478 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2479 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2480
2481 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2482 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2483 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2484
2485 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2486 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2487 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2488 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2489
2490 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2491
2492 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2493 r600_store_value(cb, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
2494 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2495
2496 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 5);
2497 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2498 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2499 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2500 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2501 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
2502
2503 r600_store_context_reg(cb, R_028C3C_PA_SC_AA_MASK, ~0);
2504
2505 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2506 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2507 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2508
2509 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2510 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2511 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2512
2513 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
2514 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
2515 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2516
2517 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2518 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2519
2520 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2521 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2522 }
2523
2524 void evergreen_polygon_offset_update(struct r600_context *rctx)
2525 {
2526 struct r600_pipe_state state;
2527
2528 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2529 state.nregs = 0;
2530 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2531 float offset_units = rctx->rasterizer->offset_units;
2532 unsigned offset_db_fmt_cntl = 0, depth;
2533
2534 switch (rctx->framebuffer.zsbuf->texture->format) {
2535 case PIPE_FORMAT_Z24X8_UNORM:
2536 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2537 depth = -24;
2538 offset_units *= 2.0f;
2539 break;
2540 case PIPE_FORMAT_Z32_FLOAT:
2541 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2542 depth = -23;
2543 offset_units *= 1.0f;
2544 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2545 break;
2546 case PIPE_FORMAT_Z16_UNORM:
2547 depth = -16;
2548 offset_units *= 4.0f;
2549 break;
2550 default:
2551 return;
2552 }
2553 /* XXX some of those reg can be computed with cso */
2554 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2555 r600_pipe_state_add_reg(&state,
2556 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2557 fui(rctx->rasterizer->offset_scale));
2558 r600_pipe_state_add_reg(&state,
2559 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2560 fui(offset_units));
2561 r600_pipe_state_add_reg(&state,
2562 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2563 fui(rctx->rasterizer->offset_scale));
2564 r600_pipe_state_add_reg(&state,
2565 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2566 fui(offset_units));
2567 r600_pipe_state_add_reg(&state,
2568 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2569 offset_db_fmt_cntl);
2570 r600_context_pipe_state_set(rctx, &state);
2571 }
2572 }
2573
2574 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2575 {
2576 struct r600_context *rctx = (struct r600_context *)ctx;
2577 struct r600_pipe_state *rstate = &shader->rstate;
2578 struct r600_shader *rshader = &shader->shader;
2579 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2580 int pos_index = -1, face_index = -1;
2581 int ninterp = 0;
2582 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2583 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2584
2585 rstate->nregs = 0;
2586
2587 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2588 for (i = 0; i < rshader->ninput; i++) {
2589 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2590 POSITION goes via GPRs from the SC so isn't counted */
2591 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2592 pos_index = i;
2593 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2594 face_index = i;
2595 else {
2596 ninterp++;
2597 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2598 have_linear = TRUE;
2599 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2600 have_perspective = TRUE;
2601 if (rshader->input[i].centroid)
2602 have_centroid = TRUE;
2603 }
2604
2605 sid = rshader->input[i].spi_sid;
2606
2607 if (sid) {
2608
2609 tmp = S_028644_SEMANTIC(sid);
2610
2611 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2612 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2613 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2614 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2615 tmp |= S_028644_FLAT_SHADE(1);
2616 }
2617
2618 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2619 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2620 tmp |= S_028644_PT_SPRITE_TEX(1);
2621 }
2622
2623 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2624 tmp);
2625
2626 idx++;
2627 }
2628 }
2629
2630 for (i = 0; i < rshader->noutput; i++) {
2631 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2632 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2633 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2634 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2635 }
2636 if (rshader->uses_kill)
2637 db_shader_control |= S_02880C_KILL_ENABLE(1);
2638
2639 exports_ps = 0;
2640 num_cout = 0;
2641 for (i = 0; i < rshader->noutput; i++) {
2642 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2643 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2644 exports_ps |= 1;
2645 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2646 if (rshader->fs_write_all)
2647 num_cout = rshader->nr_cbufs;
2648 else
2649 num_cout++;
2650 }
2651 }
2652 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2653 if (!exports_ps) {
2654 /* always at least export 1 component per pixel */
2655 exports_ps = 2;
2656 }
2657 shader->ps_cb_shader_mask = (1ULL << ((unsigned)num_cout * 4)) - 1;
2658 if (ninterp == 0) {
2659 ninterp = 1;
2660 have_perspective = TRUE;
2661 }
2662
2663 if (!have_perspective && !have_linear)
2664 have_perspective = TRUE;
2665
2666 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2667 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2668 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2669 spi_input_z = 0;
2670 if (pos_index != -1) {
2671 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2672 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2673 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2674 spi_input_z |= 1;
2675 }
2676
2677 spi_ps_in_control_1 = 0;
2678 if (face_index != -1) {
2679 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2680 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2681 }
2682
2683 spi_baryc_cntl = 0;
2684 if (have_perspective)
2685 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2686 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2687 if (have_linear)
2688 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2689 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2690
2691 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2692 spi_ps_in_control_0);
2693 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2694 spi_ps_in_control_1);
2695 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2696 0);
2697 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2698 r600_pipe_state_add_reg(rstate,
2699 R_0286E0_SPI_BARYC_CNTL,
2700 spi_baryc_cntl);
2701
2702 r600_pipe_state_add_reg_bo(rstate,
2703 R_028840_SQ_PGM_START_PS,
2704 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2705 shader->bo, RADEON_USAGE_READ);
2706 r600_pipe_state_add_reg(rstate,
2707 R_028844_SQ_PGM_RESOURCES_PS,
2708 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2709 S_028844_PRIME_CACHE_ON_DRAW(1) |
2710 S_028844_STACK_SIZE(rshader->bc.nstack));
2711 r600_pipe_state_add_reg(rstate,
2712 R_02884C_SQ_PGM_EXPORTS_PS,
2713 exports_ps);
2714 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2715 db_shader_control);
2716
2717 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2718 if (rctx->rasterizer)
2719 shader->flatshade = rctx->rasterizer->flatshade;
2720 }
2721
2722 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2723 {
2724 struct r600_context *rctx = (struct r600_context *)ctx;
2725 struct r600_pipe_state *rstate = &shader->rstate;
2726 struct r600_shader *rshader = &shader->shader;
2727 unsigned spi_vs_out_id[10] = {};
2728 unsigned i, tmp, nparams = 0;
2729
2730 /* clear previous register */
2731 rstate->nregs = 0;
2732
2733 for (i = 0; i < rshader->noutput; i++) {
2734 if (rshader->output[i].spi_sid) {
2735 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2736 spi_vs_out_id[nparams / 4] |= tmp;
2737 nparams++;
2738 }
2739 }
2740
2741 for (i = 0; i < 10; i++) {
2742 r600_pipe_state_add_reg(rstate,
2743 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2744 spi_vs_out_id[i]);
2745 }
2746
2747 /* Certain attributes (position, psize, etc.) don't count as params.
2748 * VS is required to export at least one param and r600_shader_from_tgsi()
2749 * takes care of adding a dummy export.
2750 */
2751 if (nparams < 1)
2752 nparams = 1;
2753
2754 r600_pipe_state_add_reg(rstate,
2755 R_0286C4_SPI_VS_OUT_CONFIG,
2756 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2757 r600_pipe_state_add_reg(rstate,
2758 R_028860_SQ_PGM_RESOURCES_VS,
2759 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2760 S_028860_STACK_SIZE(rshader->bc.nstack));
2761 r600_pipe_state_add_reg_bo(rstate,
2762 R_02885C_SQ_PGM_START_VS,
2763 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2764 shader->bo, RADEON_USAGE_READ);
2765
2766 shader->pa_cl_vs_out_cntl =
2767 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2768 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2769 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2770 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2771 }
2772
2773 void evergreen_fetch_shader(struct pipe_context *ctx,
2774 struct r600_vertex_element *ve)
2775 {
2776 struct r600_context *rctx = (struct r600_context *)ctx;
2777 struct r600_pipe_state *rstate = &ve->rstate;
2778 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2779 rstate->nregs = 0;
2780 r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
2781 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2782 ve->fetch_shader, RADEON_USAGE_READ);
2783 }
2784
2785 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2786 {
2787 struct pipe_depth_stencil_alpha_state dsa;
2788 struct r600_pipe_state *rstate;
2789
2790 memset(&dsa, 0, sizeof(dsa));
2791
2792 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2793 r600_pipe_state_add_reg(rstate,
2794 R_028000_DB_RENDER_CONTROL,
2795 S_028000_DEPTH_COPY_ENABLE(1) |
2796 S_028000_STENCIL_COPY_ENABLE(1) |
2797 S_028000_COPY_CENTROID(1));
2798 /* Don't set the 'is_flush' flag in r600_pipe_dsa, evergreen doesn't need it. */
2799 return rstate;
2800 }