2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "evergreend.h"
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
31 static uint32_t eg_num_banks(uint32_t nbanks
)
47 static unsigned eg_tile_split(unsigned tile_split
)
50 case 64: tile_split
= 0; break;
51 case 128: tile_split
= 1; break;
52 case 256: tile_split
= 2; break;
53 case 512: tile_split
= 3; break;
55 case 1024: tile_split
= 4; break;
56 case 2048: tile_split
= 5; break;
57 case 4096: tile_split
= 6; break;
62 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect
)
64 switch (macro_tile_aspect
) {
66 case 1: macro_tile_aspect
= 0; break;
67 case 2: macro_tile_aspect
= 1; break;
68 case 4: macro_tile_aspect
= 2; break;
69 case 8: macro_tile_aspect
= 3; break;
71 return macro_tile_aspect
;
74 static unsigned eg_bank_wh(unsigned bankwh
)
78 case 1: bankwh
= 0; break;
79 case 2: bankwh
= 1; break;
80 case 4: bankwh
= 2; break;
81 case 8: bankwh
= 3; break;
86 static uint32_t r600_translate_blend_function(int blend_func
)
90 return V_028780_COMB_DST_PLUS_SRC
;
91 case PIPE_BLEND_SUBTRACT
:
92 return V_028780_COMB_SRC_MINUS_DST
;
93 case PIPE_BLEND_REVERSE_SUBTRACT
:
94 return V_028780_COMB_DST_MINUS_SRC
;
96 return V_028780_COMB_MIN_DST_SRC
;
98 return V_028780_COMB_MAX_DST_SRC
;
100 R600_ERR("Unknown blend function %d\n", blend_func
);
107 static uint32_t r600_translate_blend_factor(int blend_fact
)
109 switch (blend_fact
) {
110 case PIPE_BLENDFACTOR_ONE
:
111 return V_028780_BLEND_ONE
;
112 case PIPE_BLENDFACTOR_SRC_COLOR
:
113 return V_028780_BLEND_SRC_COLOR
;
114 case PIPE_BLENDFACTOR_SRC_ALPHA
:
115 return V_028780_BLEND_SRC_ALPHA
;
116 case PIPE_BLENDFACTOR_DST_ALPHA
:
117 return V_028780_BLEND_DST_ALPHA
;
118 case PIPE_BLENDFACTOR_DST_COLOR
:
119 return V_028780_BLEND_DST_COLOR
;
120 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
121 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
122 case PIPE_BLENDFACTOR_CONST_COLOR
:
123 return V_028780_BLEND_CONST_COLOR
;
124 case PIPE_BLENDFACTOR_CONST_ALPHA
:
125 return V_028780_BLEND_CONST_ALPHA
;
126 case PIPE_BLENDFACTOR_ZERO
:
127 return V_028780_BLEND_ZERO
;
128 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
129 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
130 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
131 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
132 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
133 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
134 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
135 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
136 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
137 return V_028780_BLEND_ONE_MINUS_CONST_COLOR
;
138 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
139 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA
;
140 case PIPE_BLENDFACTOR_SRC1_COLOR
:
141 return V_028780_BLEND_SRC1_COLOR
;
142 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
143 return V_028780_BLEND_SRC1_ALPHA
;
144 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
145 return V_028780_BLEND_INV_SRC1_COLOR
;
146 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
147 return V_028780_BLEND_INV_SRC1_ALPHA
;
149 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
156 static unsigned r600_tex_dim(unsigned dim
)
160 case PIPE_TEXTURE_1D
:
161 return V_030000_SQ_TEX_DIM_1D
;
162 case PIPE_TEXTURE_1D_ARRAY
:
163 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
164 case PIPE_TEXTURE_2D
:
165 case PIPE_TEXTURE_RECT
:
166 return V_030000_SQ_TEX_DIM_2D
;
167 case PIPE_TEXTURE_2D_ARRAY
:
168 return V_030000_SQ_TEX_DIM_2D_ARRAY
;
169 case PIPE_TEXTURE_3D
:
170 return V_030000_SQ_TEX_DIM_3D
;
171 case PIPE_TEXTURE_CUBE
:
172 return V_030000_SQ_TEX_DIM_CUBEMAP
;
176 static uint32_t r600_translate_dbformat(enum pipe_format format
)
179 case PIPE_FORMAT_Z16_UNORM
:
180 return V_028040_Z_16
;
181 case PIPE_FORMAT_Z24X8_UNORM
:
182 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
183 return V_028040_Z_24
;
184 case PIPE_FORMAT_Z32_FLOAT
:
185 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
186 return V_028040_Z_32_FLOAT
;
192 static uint32_t r600_translate_colorswap(enum pipe_format format
)
196 case PIPE_FORMAT_L4A4_UNORM
:
197 case PIPE_FORMAT_A4R4_UNORM
:
198 return V_028C70_SWAP_ALT
;
200 case PIPE_FORMAT_A8_UNORM
:
201 case PIPE_FORMAT_A8_SNORM
:
202 case PIPE_FORMAT_A8_UINT
:
203 case PIPE_FORMAT_A8_SINT
:
204 case PIPE_FORMAT_A16_UNORM
:
205 case PIPE_FORMAT_A16_SNORM
:
206 case PIPE_FORMAT_A16_UINT
:
207 case PIPE_FORMAT_A16_SINT
:
208 case PIPE_FORMAT_A16_FLOAT
:
209 case PIPE_FORMAT_A32_UINT
:
210 case PIPE_FORMAT_A32_SINT
:
211 case PIPE_FORMAT_A32_FLOAT
:
212 case PIPE_FORMAT_R4A4_UNORM
:
213 return V_028C70_SWAP_ALT_REV
;
214 case PIPE_FORMAT_I8_UNORM
:
215 case PIPE_FORMAT_I8_SNORM
:
216 case PIPE_FORMAT_I8_UINT
:
217 case PIPE_FORMAT_I8_SINT
:
218 case PIPE_FORMAT_I16_UNORM
:
219 case PIPE_FORMAT_I16_SNORM
:
220 case PIPE_FORMAT_I16_UINT
:
221 case PIPE_FORMAT_I16_SINT
:
222 case PIPE_FORMAT_I16_FLOAT
:
223 case PIPE_FORMAT_I32_UINT
:
224 case PIPE_FORMAT_I32_SINT
:
225 case PIPE_FORMAT_I32_FLOAT
:
226 case PIPE_FORMAT_L8_UNORM
:
227 case PIPE_FORMAT_L8_SNORM
:
228 case PIPE_FORMAT_L8_UINT
:
229 case PIPE_FORMAT_L8_SINT
:
230 case PIPE_FORMAT_L8_SRGB
:
231 case PIPE_FORMAT_L16_UNORM
:
232 case PIPE_FORMAT_L16_SNORM
:
233 case PIPE_FORMAT_L16_UINT
:
234 case PIPE_FORMAT_L16_SINT
:
235 case PIPE_FORMAT_L16_FLOAT
:
236 case PIPE_FORMAT_L32_UINT
:
237 case PIPE_FORMAT_L32_SINT
:
238 case PIPE_FORMAT_L32_FLOAT
:
239 case PIPE_FORMAT_R8_UNORM
:
240 case PIPE_FORMAT_R8_SNORM
:
241 case PIPE_FORMAT_R8_UINT
:
242 case PIPE_FORMAT_R8_SINT
:
243 return V_028C70_SWAP_STD
;
245 /* 16-bit buffers. */
246 case PIPE_FORMAT_B5G6R5_UNORM
:
247 return V_028C70_SWAP_STD_REV
;
249 case PIPE_FORMAT_B5G5R5A1_UNORM
:
250 case PIPE_FORMAT_B5G5R5X1_UNORM
:
251 return V_028C70_SWAP_ALT
;
253 case PIPE_FORMAT_B4G4R4A4_UNORM
:
254 case PIPE_FORMAT_B4G4R4X4_UNORM
:
255 return V_028C70_SWAP_ALT
;
257 case PIPE_FORMAT_Z16_UNORM
:
258 return V_028C70_SWAP_STD
;
260 case PIPE_FORMAT_L8A8_UNORM
:
261 case PIPE_FORMAT_L8A8_SNORM
:
262 case PIPE_FORMAT_L8A8_UINT
:
263 case PIPE_FORMAT_L8A8_SINT
:
264 case PIPE_FORMAT_L8A8_SRGB
:
265 case PIPE_FORMAT_L16A16_UNORM
:
266 case PIPE_FORMAT_L16A16_SNORM
:
267 case PIPE_FORMAT_L16A16_UINT
:
268 case PIPE_FORMAT_L16A16_SINT
:
269 case PIPE_FORMAT_L16A16_FLOAT
:
270 case PIPE_FORMAT_L32A32_UINT
:
271 case PIPE_FORMAT_L32A32_SINT
:
272 case PIPE_FORMAT_L32A32_FLOAT
:
273 return V_028C70_SWAP_ALT
;
274 case PIPE_FORMAT_R8G8_UNORM
:
275 case PIPE_FORMAT_R8G8_SNORM
:
276 case PIPE_FORMAT_R8G8_UINT
:
277 case PIPE_FORMAT_R8G8_SINT
:
278 return V_028C70_SWAP_STD
;
280 case PIPE_FORMAT_R16_UNORM
:
281 case PIPE_FORMAT_R16_SNORM
:
282 case PIPE_FORMAT_R16_UINT
:
283 case PIPE_FORMAT_R16_SINT
:
284 case PIPE_FORMAT_R16_FLOAT
:
285 return V_028C70_SWAP_STD
;
287 /* 32-bit buffers. */
288 case PIPE_FORMAT_A8B8G8R8_SRGB
:
289 return V_028C70_SWAP_STD_REV
;
290 case PIPE_FORMAT_B8G8R8A8_SRGB
:
291 return V_028C70_SWAP_ALT
;
293 case PIPE_FORMAT_B8G8R8A8_UNORM
:
294 case PIPE_FORMAT_B8G8R8X8_UNORM
:
295 return V_028C70_SWAP_ALT
;
297 case PIPE_FORMAT_A8R8G8B8_UNORM
:
298 case PIPE_FORMAT_X8R8G8B8_UNORM
:
299 return V_028C70_SWAP_ALT_REV
;
300 case PIPE_FORMAT_R8G8B8A8_SNORM
:
301 case PIPE_FORMAT_R8G8B8A8_UNORM
:
302 case PIPE_FORMAT_R8G8B8A8_SINT
:
303 case PIPE_FORMAT_R8G8B8A8_UINT
:
304 case PIPE_FORMAT_R8G8B8X8_UNORM
:
305 return V_028C70_SWAP_STD
;
307 case PIPE_FORMAT_A8B8G8R8_UNORM
:
308 case PIPE_FORMAT_X8B8G8R8_UNORM
:
309 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
310 return V_028C70_SWAP_STD_REV
;
312 case PIPE_FORMAT_Z24X8_UNORM
:
313 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
314 return V_028C70_SWAP_STD
;
316 case PIPE_FORMAT_X8Z24_UNORM
:
317 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
318 return V_028C70_SWAP_STD
;
320 case PIPE_FORMAT_R10G10B10A2_UNORM
:
321 case PIPE_FORMAT_R10G10B10X2_SNORM
:
322 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
323 return V_028C70_SWAP_STD
;
325 case PIPE_FORMAT_B10G10R10A2_UNORM
:
326 case PIPE_FORMAT_B10G10R10A2_UINT
:
327 return V_028C70_SWAP_ALT
;
329 case PIPE_FORMAT_R11G11B10_FLOAT
:
330 case PIPE_FORMAT_R32_FLOAT
:
331 case PIPE_FORMAT_R32_UINT
:
332 case PIPE_FORMAT_R32_SINT
:
333 case PIPE_FORMAT_Z32_FLOAT
:
334 case PIPE_FORMAT_R16G16_FLOAT
:
335 case PIPE_FORMAT_R16G16_UNORM
:
336 case PIPE_FORMAT_R16G16_SNORM
:
337 case PIPE_FORMAT_R16G16_UINT
:
338 case PIPE_FORMAT_R16G16_SINT
:
339 return V_028C70_SWAP_STD
;
341 /* 64-bit buffers. */
342 case PIPE_FORMAT_R32G32_FLOAT
:
343 case PIPE_FORMAT_R32G32_UINT
:
344 case PIPE_FORMAT_R32G32_SINT
:
345 case PIPE_FORMAT_R16G16B16A16_UNORM
:
346 case PIPE_FORMAT_R16G16B16A16_SNORM
:
347 case PIPE_FORMAT_R16G16B16A16_UINT
:
348 case PIPE_FORMAT_R16G16B16A16_SINT
:
349 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
350 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
352 /* 128-bit buffers. */
353 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
354 case PIPE_FORMAT_R32G32B32A32_SNORM
:
355 case PIPE_FORMAT_R32G32B32A32_UNORM
:
356 case PIPE_FORMAT_R32G32B32A32_SINT
:
357 case PIPE_FORMAT_R32G32B32A32_UINT
:
358 return V_028C70_SWAP_STD
;
360 R600_ERR("unsupported colorswap format %d\n", format
);
366 static uint32_t r600_translate_colorformat(enum pipe_format format
)
370 case PIPE_FORMAT_A8_UNORM
:
371 case PIPE_FORMAT_A8_SNORM
:
372 case PIPE_FORMAT_A8_UINT
:
373 case PIPE_FORMAT_A8_SINT
:
374 case PIPE_FORMAT_I8_UNORM
:
375 case PIPE_FORMAT_I8_SNORM
:
376 case PIPE_FORMAT_I8_UINT
:
377 case PIPE_FORMAT_I8_SINT
:
378 case PIPE_FORMAT_L8_UNORM
:
379 case PIPE_FORMAT_L8_SNORM
:
380 case PIPE_FORMAT_L8_UINT
:
381 case PIPE_FORMAT_L8_SINT
:
382 case PIPE_FORMAT_L8_SRGB
:
383 case PIPE_FORMAT_R8_UNORM
:
384 case PIPE_FORMAT_R8_SNORM
:
385 case PIPE_FORMAT_R8_UINT
:
386 case PIPE_FORMAT_R8_SINT
:
387 return V_028C70_COLOR_8
;
389 /* 16-bit buffers. */
390 case PIPE_FORMAT_B5G6R5_UNORM
:
391 return V_028C70_COLOR_5_6_5
;
393 case PIPE_FORMAT_B5G5R5A1_UNORM
:
394 case PIPE_FORMAT_B5G5R5X1_UNORM
:
395 return V_028C70_COLOR_1_5_5_5
;
397 case PIPE_FORMAT_B4G4R4A4_UNORM
:
398 case PIPE_FORMAT_B4G4R4X4_UNORM
:
399 return V_028C70_COLOR_4_4_4_4
;
401 case PIPE_FORMAT_Z16_UNORM
:
402 return V_028C70_COLOR_16
;
404 case PIPE_FORMAT_L8A8_UNORM
:
405 case PIPE_FORMAT_L8A8_SNORM
:
406 case PIPE_FORMAT_L8A8_UINT
:
407 case PIPE_FORMAT_L8A8_SINT
:
408 case PIPE_FORMAT_L8A8_SRGB
:
409 case PIPE_FORMAT_R8G8_UNORM
:
410 case PIPE_FORMAT_R8G8_SNORM
:
411 case PIPE_FORMAT_R8G8_UINT
:
412 case PIPE_FORMAT_R8G8_SINT
:
413 return V_028C70_COLOR_8_8
;
415 case PIPE_FORMAT_R16_UNORM
:
416 case PIPE_FORMAT_R16_SNORM
:
417 case PIPE_FORMAT_R16_UINT
:
418 case PIPE_FORMAT_R16_SINT
:
419 case PIPE_FORMAT_A16_UNORM
:
420 case PIPE_FORMAT_A16_SNORM
:
421 case PIPE_FORMAT_A16_UINT
:
422 case PIPE_FORMAT_A16_SINT
:
423 case PIPE_FORMAT_L16_UNORM
:
424 case PIPE_FORMAT_L16_SNORM
:
425 case PIPE_FORMAT_L16_UINT
:
426 case PIPE_FORMAT_L16_SINT
:
427 case PIPE_FORMAT_I16_UNORM
:
428 case PIPE_FORMAT_I16_SNORM
:
429 case PIPE_FORMAT_I16_UINT
:
430 case PIPE_FORMAT_I16_SINT
:
431 return V_028C70_COLOR_16
;
433 case PIPE_FORMAT_R16_FLOAT
:
434 case PIPE_FORMAT_A16_FLOAT
:
435 case PIPE_FORMAT_L16_FLOAT
:
436 case PIPE_FORMAT_I16_FLOAT
:
437 return V_028C70_COLOR_16_FLOAT
;
439 /* 32-bit buffers. */
440 case PIPE_FORMAT_A8B8G8R8_SRGB
:
441 case PIPE_FORMAT_A8B8G8R8_UNORM
:
442 case PIPE_FORMAT_A8R8G8B8_UNORM
:
443 case PIPE_FORMAT_B8G8R8A8_SRGB
:
444 case PIPE_FORMAT_B8G8R8A8_UNORM
:
445 case PIPE_FORMAT_B8G8R8X8_UNORM
:
446 case PIPE_FORMAT_R8G8B8A8_SNORM
:
447 case PIPE_FORMAT_R8G8B8A8_UNORM
:
448 case PIPE_FORMAT_R8G8B8X8_UNORM
:
449 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
450 case PIPE_FORMAT_X8B8G8R8_UNORM
:
451 case PIPE_FORMAT_X8R8G8B8_UNORM
:
452 case PIPE_FORMAT_R8G8B8_UNORM
:
453 case PIPE_FORMAT_R8G8B8A8_SINT
:
454 case PIPE_FORMAT_R8G8B8A8_UINT
:
455 return V_028C70_COLOR_8_8_8_8
;
457 case PIPE_FORMAT_R10G10B10A2_UNORM
:
458 case PIPE_FORMAT_R10G10B10X2_SNORM
:
459 case PIPE_FORMAT_B10G10R10A2_UNORM
:
460 case PIPE_FORMAT_B10G10R10A2_UINT
:
461 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
462 return V_028C70_COLOR_2_10_10_10
;
464 case PIPE_FORMAT_Z24X8_UNORM
:
465 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
466 return V_028C70_COLOR_8_24
;
468 case PIPE_FORMAT_X8Z24_UNORM
:
469 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
470 return V_028C70_COLOR_24_8
;
472 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
473 return V_028C70_COLOR_X24_8_32_FLOAT
;
475 case PIPE_FORMAT_R32_UINT
:
476 case PIPE_FORMAT_R32_SINT
:
477 case PIPE_FORMAT_A32_UINT
:
478 case PIPE_FORMAT_A32_SINT
:
479 case PIPE_FORMAT_L32_UINT
:
480 case PIPE_FORMAT_L32_SINT
:
481 case PIPE_FORMAT_I32_UINT
:
482 case PIPE_FORMAT_I32_SINT
:
483 return V_028C70_COLOR_32
;
485 case PIPE_FORMAT_R32_FLOAT
:
486 case PIPE_FORMAT_A32_FLOAT
:
487 case PIPE_FORMAT_L32_FLOAT
:
488 case PIPE_FORMAT_I32_FLOAT
:
489 case PIPE_FORMAT_Z32_FLOAT
:
490 return V_028C70_COLOR_32_FLOAT
;
492 case PIPE_FORMAT_R16G16_FLOAT
:
493 case PIPE_FORMAT_L16A16_FLOAT
:
494 return V_028C70_COLOR_16_16_FLOAT
;
496 case PIPE_FORMAT_R16G16_UNORM
:
497 case PIPE_FORMAT_R16G16_SNORM
:
498 case PIPE_FORMAT_R16G16_UINT
:
499 case PIPE_FORMAT_R16G16_SINT
:
500 case PIPE_FORMAT_L16A16_UNORM
:
501 case PIPE_FORMAT_L16A16_SNORM
:
502 case PIPE_FORMAT_L16A16_UINT
:
503 case PIPE_FORMAT_L16A16_SINT
:
504 return V_028C70_COLOR_16_16
;
506 case PIPE_FORMAT_R11G11B10_FLOAT
:
507 return V_028C70_COLOR_10_11_11_FLOAT
;
509 /* 64-bit buffers. */
510 case PIPE_FORMAT_R16G16B16A16_UINT
:
511 case PIPE_FORMAT_R16G16B16A16_SINT
:
512 case PIPE_FORMAT_R16G16B16A16_UNORM
:
513 case PIPE_FORMAT_R16G16B16A16_SNORM
:
514 return V_028C70_COLOR_16_16_16_16
;
516 case PIPE_FORMAT_R16G16B16_FLOAT
:
517 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
518 return V_028C70_COLOR_16_16_16_16_FLOAT
;
520 case PIPE_FORMAT_R32G32_FLOAT
:
521 case PIPE_FORMAT_L32A32_FLOAT
:
522 return V_028C70_COLOR_32_32_FLOAT
;
524 case PIPE_FORMAT_R32G32_SINT
:
525 case PIPE_FORMAT_R32G32_UINT
:
526 case PIPE_FORMAT_L32A32_UINT
:
527 case PIPE_FORMAT_L32A32_SINT
:
528 return V_028C70_COLOR_32_32
;
530 /* 96-bit buffers. */
531 case PIPE_FORMAT_R32G32B32_FLOAT
:
532 return V_028C70_COLOR_32_32_32_FLOAT
;
534 /* 128-bit buffers. */
535 case PIPE_FORMAT_R32G32B32A32_SNORM
:
536 case PIPE_FORMAT_R32G32B32A32_UNORM
:
537 case PIPE_FORMAT_R32G32B32A32_SINT
:
538 case PIPE_FORMAT_R32G32B32A32_UINT
:
539 return V_028C70_COLOR_32_32_32_32
;
540 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
541 return V_028C70_COLOR_32_32_32_32_FLOAT
;
544 case PIPE_FORMAT_UYVY
:
545 case PIPE_FORMAT_YUYV
:
547 return ~0U; /* Unsupported. */
551 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
553 if (R600_BIG_ENDIAN
) {
554 switch(colorformat
) {
557 case V_028C70_COLOR_8
:
560 /* 16-bit buffers. */
561 case V_028C70_COLOR_5_6_5
:
562 case V_028C70_COLOR_1_5_5_5
:
563 case V_028C70_COLOR_4_4_4_4
:
564 case V_028C70_COLOR_16
:
565 case V_028C70_COLOR_8_8
:
568 /* 32-bit buffers. */
569 case V_028C70_COLOR_8_8_8_8
:
570 case V_028C70_COLOR_2_10_10_10
:
571 case V_028C70_COLOR_8_24
:
572 case V_028C70_COLOR_24_8
:
573 case V_028C70_COLOR_32_FLOAT
:
574 case V_028C70_COLOR_16_16_FLOAT
:
575 case V_028C70_COLOR_16_16
:
578 /* 64-bit buffers. */
579 case V_028C70_COLOR_16_16_16_16
:
580 case V_028C70_COLOR_16_16_16_16_FLOAT
:
583 case V_028C70_COLOR_32_32_FLOAT
:
584 case V_028C70_COLOR_32_32
:
585 case V_028C70_COLOR_X24_8_32_FLOAT
:
588 /* 96-bit buffers. */
589 case V_028C70_COLOR_32_32_32_FLOAT
:
590 /* 128-bit buffers. */
591 case V_028C70_COLOR_32_32_32_32_FLOAT
:
592 case V_028C70_COLOR_32_32_32_32
:
595 return ENDIAN_NONE
; /* Unsupported. */
602 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
604 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
607 static bool r600_is_colorbuffer_format_supported(enum pipe_format format
)
609 return r600_translate_colorformat(format
) != ~0U &&
610 r600_translate_colorswap(format
) != ~0U;
613 static bool r600_is_zs_format_supported(enum pipe_format format
)
615 return r600_translate_dbformat(format
) != ~0U;
618 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
619 enum pipe_format format
,
620 enum pipe_texture_target target
,
621 unsigned sample_count
,
626 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
627 R600_ERR("r600: unsupported texture type %d\n", target
);
631 if (!util_format_is_supported(format
, usage
))
635 if (sample_count
> 1)
638 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
639 r600_is_sampler_format_supported(screen
, format
)) {
640 retval
|= PIPE_BIND_SAMPLER_VIEW
;
643 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
644 PIPE_BIND_DISPLAY_TARGET
|
646 PIPE_BIND_SHARED
)) &&
647 r600_is_colorbuffer_format_supported(format
)) {
649 (PIPE_BIND_RENDER_TARGET
|
650 PIPE_BIND_DISPLAY_TARGET
|
655 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
656 r600_is_zs_format_supported(format
)) {
657 retval
|= PIPE_BIND_DEPTH_STENCIL
;
660 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
661 r600_is_vertex_format_supported(format
)) {
662 retval
|= PIPE_BIND_VERTEX_BUFFER
;
665 if (usage
& PIPE_BIND_TRANSFER_READ
)
666 retval
|= PIPE_BIND_TRANSFER_READ
;
667 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
668 retval
|= PIPE_BIND_TRANSFER_WRITE
;
670 return retval
== usage
;
673 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
674 const struct pipe_blend_state
*state
)
676 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
677 struct r600_pipe_blend
*blend
= CALLOC_STRUCT(r600_pipe_blend
);
678 struct r600_pipe_state
*rstate
;
679 uint32_t color_control
, target_mask
;
680 /* XXX there is more then 8 framebuffer */
681 unsigned blend_cntl
[8];
687 rstate
= &blend
->rstate
;
689 rstate
->id
= R600_PIPE_STATE_BLEND
;
692 color_control
= S_028808_MODE(1);
693 if (state
->logicop_enable
) {
694 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
696 color_control
|= (0xcc << 16);
698 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
699 if (state
->independent_blend_enable
) {
700 for (int i
= 0; i
< 8; i
++) {
701 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
704 for (int i
= 0; i
< 8; i
++) {
705 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
708 blend
->cb_target_mask
= target_mask
;
710 r600_pipe_state_add_reg(rstate
, R_028808_CB_COLOR_CONTROL
,
711 color_control
, NULL
, 0);
713 for (int i
= 0; i
< 8; i
++) {
714 /* state->rt entries > 0 only written if independent blending */
715 const int j
= state
->independent_blend_enable
? i
: 0;
717 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
718 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
719 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
720 unsigned eqA
= state
->rt
[j
].alpha_func
;
721 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
722 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
725 if (!state
->rt
[j
].blend_enable
)
728 blend_cntl
[i
] |= S_028780_BLEND_CONTROL_ENABLE(1);
729 blend_cntl
[i
] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
730 blend_cntl
[i
] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
731 blend_cntl
[i
] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
733 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
734 blend_cntl
[i
] |= S_028780_SEPARATE_ALPHA_BLEND(1);
735 blend_cntl
[i
] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
736 blend_cntl
[i
] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
737 blend_cntl
[i
] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
740 for (int i
= 0; i
< 8; i
++) {
741 r600_pipe_state_add_reg(rstate
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
[i
], NULL
, 0);
747 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
748 const struct pipe_depth_stencil_alpha_state
*state
)
750 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
751 struct r600_pipe_dsa
*dsa
= CALLOC_STRUCT(r600_pipe_dsa
);
752 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
753 unsigned db_render_control
;
754 struct r600_pipe_state
*rstate
;
760 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
761 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
762 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
763 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
765 rstate
= &dsa
->rstate
;
767 rstate
->id
= R600_PIPE_STATE_DSA
;
768 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
769 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
770 S_028800_ZFUNC(state
->depth
.func
);
773 if (state
->stencil
[0].enabled
) {
774 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
775 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
776 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
777 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
778 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
780 if (state
->stencil
[1].enabled
) {
781 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
782 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
783 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
784 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
785 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
790 alpha_test_control
= 0;
792 if (state
->alpha
.enabled
) {
793 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
794 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
795 alpha_ref
= fui(state
->alpha
.ref_value
);
797 dsa
->alpha_ref
= alpha_ref
;
800 db_render_control
= 0;
801 r600_pipe_state_add_reg(rstate
, R_028410_SX_ALPHA_TEST_CONTROL
, alpha_test_control
, NULL
, 0);
802 r600_pipe_state_add_reg(rstate
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
, NULL
, 0);
803 r600_pipe_state_add_reg(rstate
, R_028000_DB_RENDER_CONTROL
, db_render_control
, NULL
, 0);
807 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
808 const struct pipe_rasterizer_state
*state
)
810 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
811 struct r600_pipe_rasterizer
*rs
= CALLOC_STRUCT(r600_pipe_rasterizer
);
812 struct r600_pipe_state
*rstate
;
814 unsigned prov_vtx
= 1, polygon_dual_mode
;
815 float psize_min
, psize_max
;
821 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
822 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
824 if (state
->flatshade_first
)
827 rstate
= &rs
->rstate
;
828 rs
->rasterizer_discard
= state
->rasterizer_discard
;
829 rs
->flatshade
= state
->flatshade
;
830 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
831 rs
->two_side
= state
->light_twoside
;
832 rs
->clip_plane_enable
= state
->clip_plane_enable
;
833 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
834 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
835 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
836 rs
->pa_cl_clip_cntl
=
837 S_028810_PS_UCP_MODE(3) |
838 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
839 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
840 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
843 rs
->offset_units
= state
->offset_units
;
844 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
846 rstate
->id
= R600_PIPE_STATE_RASTERIZER
;
847 tmp
= S_0286D4_FLAT_SHADE_ENA(1);
848 if (state
->sprite_coord_enable
) {
849 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
850 S_0286D4_PNT_SPRITE_OVRD_X(2) |
851 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
852 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
853 S_0286D4_PNT_SPRITE_OVRD_W(1);
854 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
855 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
858 r600_pipe_state_add_reg(rstate
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
, NULL
, 0);
860 /* point size 12.4 fixed point */
861 tmp
= (unsigned)(state
->point_size
* 8.0);
862 r600_pipe_state_add_reg(rstate
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
), NULL
, 0);
864 if (state
->point_size_per_vertex
) {
865 psize_min
= util_get_min_point_size(state
);
868 /* Force the point size to be as if the vertex output was disabled. */
869 psize_min
= state
->point_size
;
870 psize_max
= state
->point_size
;
872 /* Divide by two, because 0.5 = 1 pixel. */
873 r600_pipe_state_add_reg(rstate
, R_028A04_PA_SU_POINT_MINMAX
,
874 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
875 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)),
878 tmp
= (unsigned)state
->line_width
* 8;
879 r600_pipe_state_add_reg(rstate
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
), NULL
, 0);
880 r600_pipe_state_add_reg(rstate
, R_028A48_PA_SC_MODE_CNTL_0
,
881 S_028A48_VPORT_SCISSOR_ENABLE(state
->scissor
) |
882 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
),
885 if (rctx
->chip_class
== CAYMAN
) {
886 r600_pipe_state_add_reg(rstate
, CM_R_028BE4_PA_SU_VTX_CNTL
,
887 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
),
890 r600_pipe_state_add_reg(rstate
, R_028C08_PA_SU_VTX_CNTL
,
891 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
),
894 r600_pipe_state_add_reg(rstate
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
), NULL
, 0);
895 r600_pipe_state_add_reg(rstate
, R_028814_PA_SU_SC_MODE_CNTL
,
896 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
897 S_028814_CULL_FRONT(state
->cull_face
& PIPE_FACE_FRONT
? 1 : 0) |
898 S_028814_CULL_BACK(state
->cull_face
& PIPE_FACE_BACK
? 1 : 0) |
899 S_028814_FACE(!state
->front_ccw
) |
900 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
901 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
902 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
903 S_028814_POLY_MODE(polygon_dual_mode
) |
904 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
905 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)),
910 void evergreen_set_rasterizer_discard(struct pipe_context
*ctx
, boolean discard
)
912 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
914 if (discard
!= rctx
->atom_eg_strmout_config
.rasterizer_discard
) {
915 rctx
->atom_eg_strmout_config
.rasterizer_discard
= discard
;
916 r600_atom_dirty(rctx
, &rctx
->atom_eg_strmout_config
.atom
);
920 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
921 const struct pipe_sampler_state
*state
)
923 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
925 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
927 if (rstate
== NULL
) {
931 rstate
->id
= R600_PIPE_STATE_SAMPLER
;
932 util_pack_color(state
->border_color
.f
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
933 r600_pipe_state_add_reg_noblock(rstate
, R_03C000_SQ_TEX_SAMPLER_WORD0_0
,
934 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
935 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
936 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
937 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
938 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
939 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
940 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
941 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
942 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0), NULL
, 0);
943 r600_pipe_state_add_reg_noblock(rstate
, R_03C004_SQ_TEX_SAMPLER_WORD1_0
,
944 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
945 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)),
947 r600_pipe_state_add_reg_noblock(rstate
, R_03C008_SQ_TEX_SAMPLER_WORD2_0
,
948 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
949 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
954 r600_pipe_state_add_reg_noblock(rstate
, R_00A404_TD_PS_SAMPLER0_BORDER_RED
, fui(state
->border_color
.f
[0]), NULL
, 0);
955 r600_pipe_state_add_reg_noblock(rstate
, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN
, fui(state
->border_color
.f
[1]), NULL
, 0);
956 r600_pipe_state_add_reg_noblock(rstate
, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE
, fui(state
->border_color
.f
[2]), NULL
, 0);
957 r600_pipe_state_add_reg_noblock(rstate
, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA
, fui(state
->border_color
.f
[3]), NULL
, 0);
962 static struct pipe_sampler_view
*evergreen_create_sampler_view(struct pipe_context
*ctx
,
963 struct pipe_resource
*texture
,
964 const struct pipe_sampler_view
*state
)
966 struct r600_screen
*rscreen
= (struct r600_screen
*)ctx
->screen
;
967 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
968 struct r600_pipe_resource_state
*rstate
;
969 struct r600_resource_texture
*tmp
= (struct r600_resource_texture
*)texture
;
970 unsigned format
, endian
;
971 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
972 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
973 unsigned height
, depth
, width
;
974 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
978 rstate
= &view
->state
;
980 /* initialize base object */
982 view
->base
.texture
= NULL
;
983 pipe_reference(NULL
, &texture
->reference
);
984 view
->base
.texture
= texture
;
985 view
->base
.reference
.count
= 1;
986 view
->base
.context
= ctx
;
988 swizzle
[0] = state
->swizzle_r
;
989 swizzle
[1] = state
->swizzle_g
;
990 swizzle
[2] = state
->swizzle_b
;
991 swizzle
[3] = state
->swizzle_a
;
993 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
995 &word4
, &yuv_format
);
1000 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
1001 r600_texture_depth_flush(ctx
, texture
, TRUE
);
1002 tmp
= tmp
->flushed_depth_texture
;
1005 endian
= r600_colorformat_endian_swap(format
);
1007 if (!rscreen
->use_surface_alloc
) {
1008 height
= texture
->height0
;
1009 depth
= texture
->depth0
;
1010 width
= texture
->width0
;
1011 pitch
= align(tmp
->pitch_in_blocks
[0] *
1012 util_format_get_blockwidth(state
->format
), 8);
1013 array_mode
= tmp
->array_mode
[0];
1014 tile_type
= tmp
->tile_type
;
1020 width
= tmp
->surface
.level
[0].npix_x
;
1021 height
= tmp
->surface
.level
[0].npix_y
;
1022 depth
= tmp
->surface
.level
[0].npix_z
;
1023 pitch
= tmp
->surface
.level
[0].nblk_x
* util_format_get_blockwidth(state
->format
);
1024 tile_type
= tmp
->tile_type
;
1026 switch (tmp
->surface
.level
[0].mode
) {
1027 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1028 array_mode
= V_028C70_ARRAY_LINEAR_ALIGNED
;
1030 case RADEON_SURF_MODE_2D
:
1031 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1033 case RADEON_SURF_MODE_1D
:
1034 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1036 case RADEON_SURF_MODE_LINEAR
:
1038 array_mode
= V_028C70_ARRAY_LINEAR_GENERAL
;
1041 tile_split
= tmp
->surface
.tile_split
;
1042 macro_aspect
= tmp
->surface
.mtilea
;
1043 bankw
= tmp
->surface
.bankw
;
1044 bankh
= tmp
->surface
.bankh
;
1045 tile_split
= eg_tile_split(tile_split
);
1046 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1047 bankw
= eg_bank_wh(bankw
);
1048 bankh
= eg_bank_wh(bankh
);
1050 /* 128 bit formats require tile type = 1 */
1051 if (rscreen
->chip_class
== CAYMAN
) {
1052 if (util_format_get_blocksize(state
->format
) >= 16)
1055 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1057 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
1059 depth
= texture
->array_size
;
1060 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
1061 depth
= texture
->array_size
;
1064 rstate
->bo
[0] = &tmp
->resource
;
1065 rstate
->bo
[1] = &tmp
->resource
;
1066 rstate
->bo_usage
[0] = RADEON_USAGE_READ
;
1067 rstate
->bo_usage
[1] = RADEON_USAGE_READ
;
1069 rstate
->val
[0] = (S_030000_DIM(r600_tex_dim(texture
->target
)) |
1070 S_030000_PITCH((pitch
/ 8) - 1) |
1071 S_030000_TEX_WIDTH(width
- 1));
1072 if (rscreen
->chip_class
== CAYMAN
)
1073 rstate
->val
[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type
);
1075 rstate
->val
[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type
);
1076 rstate
->val
[1] = (S_030004_TEX_HEIGHT(height
- 1) |
1077 S_030004_TEX_DEPTH(depth
- 1) |
1078 S_030004_ARRAY_MODE(array_mode
));
1079 rstate
->val
[2] = (tmp
->offset
[0] + r600_resource_va(ctx
->screen
, texture
)) >> 8;
1080 if (state
->u
.tex
.last_level
) {
1081 rstate
->val
[3] = (tmp
->offset
[1] + r600_resource_va(ctx
->screen
, texture
)) >> 8;
1083 rstate
->val
[3] = (tmp
->offset
[0] + r600_resource_va(ctx
->screen
, texture
)) >> 8;
1085 rstate
->val
[4] = (word4
|
1086 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
1087 S_030010_ENDIAN_SWAP(endian
) |
1088 S_030010_BASE_LEVEL(state
->u
.tex
.first_level
));
1089 rstate
->val
[5] = (S_030014_LAST_LEVEL(state
->u
.tex
.last_level
) |
1090 S_030014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
1091 S_030014_LAST_ARRAY(state
->u
.tex
.last_layer
));
1092 /* aniso max 16 samples */
1093 rstate
->val
[6] = (S_030018_MAX_ANISO(4)) |
1094 (S_030018_TILE_SPLIT(tile_split
));
1095 rstate
->val
[7] = S_03001C_DATA_FORMAT(format
) |
1096 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
) |
1097 S_03001C_BANK_WIDTH(bankw
) |
1098 S_03001C_BANK_HEIGHT(bankh
) |
1099 S_03001C_MACRO_TILE_ASPECT(macro_aspect
) |
1100 S_03001C_NUM_BANKS(nbanks
);
1105 static void evergreen_set_vs_sampler_view(struct pipe_context
*ctx
, unsigned count
,
1106 struct pipe_sampler_view
**views
)
1108 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1109 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
1111 for (int i
= 0; i
< count
; i
++) {
1113 r600_context_pipe_state_set_vs_resource(rctx
, &resource
[i
]->state
,
1114 i
+ R600_MAX_CONST_BUFFERS
);
1119 static void evergreen_set_ps_sampler_view(struct pipe_context
*ctx
, unsigned count
,
1120 struct pipe_sampler_view
**views
)
1122 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1123 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
1127 for (i
= 0; i
< count
; i
++) {
1128 if (&rctx
->ps_samplers
.views
[i
]->base
!= views
[i
]) {
1130 if (((struct r600_resource_texture
*)resource
[i
]->base
.texture
)->is_depth
)
1132 r600_context_pipe_state_set_ps_resource(rctx
, &resource
[i
]->state
,
1133 i
+ R600_MAX_CONST_BUFFERS
);
1135 r600_context_pipe_state_set_ps_resource(rctx
, NULL
,
1136 i
+ R600_MAX_CONST_BUFFERS
);
1138 pipe_sampler_view_reference(
1139 (struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
],
1143 if (((struct r600_resource_texture
*)resource
[i
]->base
.texture
)->is_depth
)
1148 for (i
= count
; i
< NUM_TEX_UNITS
; i
++) {
1149 if (rctx
->ps_samplers
.views
[i
]) {
1150 r600_context_pipe_state_set_ps_resource(rctx
, NULL
,
1151 i
+ R600_MAX_CONST_BUFFERS
);
1152 pipe_sampler_view_reference((struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
], NULL
);
1155 rctx
->have_depth_texture
= has_depth
;
1156 rctx
->ps_samplers
.n_views
= count
;
1159 static void evergreen_bind_ps_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
1161 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1162 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
1165 r600_inval_texture_cache(rctx
);
1167 memcpy(rctx
->ps_samplers
.samplers
, states
, sizeof(void*) * count
);
1168 rctx
->ps_samplers
.n_samplers
= count
;
1170 for (int i
= 0; i
< count
; i
++) {
1171 evergreen_context_pipe_state_set_ps_sampler(rctx
, rstates
[i
], i
);
1175 static void evergreen_bind_vs_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
1177 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1178 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
1181 r600_inval_texture_cache(rctx
);
1183 for (int i
= 0; i
< count
; i
++) {
1184 evergreen_context_pipe_state_set_vs_sampler(rctx
, rstates
[i
], i
);
1188 static void evergreen_set_clip_state(struct pipe_context
*ctx
,
1189 const struct pipe_clip_state
*state
)
1191 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1192 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1193 struct pipe_resource
*cbuf
;
1198 rctx
->clip
= *state
;
1199 rstate
->id
= R600_PIPE_STATE_CLIP
;
1200 for (int i
= 0; i
< 6; i
++) {
1201 r600_pipe_state_add_reg(rstate
,
1202 R_0285BC_PA_CL_UCP0_X
+ i
* 16,
1203 fui(state
->ucp
[i
][0]), NULL
, 0);
1204 r600_pipe_state_add_reg(rstate
,
1205 R_0285C0_PA_CL_UCP0_Y
+ i
* 16,
1206 fui(state
->ucp
[i
][1]) , NULL
, 0);
1207 r600_pipe_state_add_reg(rstate
,
1208 R_0285C4_PA_CL_UCP0_Z
+ i
* 16,
1209 fui(state
->ucp
[i
][2]), NULL
, 0);
1210 r600_pipe_state_add_reg(rstate
,
1211 R_0285C8_PA_CL_UCP0_W
+ i
* 16,
1212 fui(state
->ucp
[i
][3]), NULL
, 0);
1215 free(rctx
->states
[R600_PIPE_STATE_CLIP
]);
1216 rctx
->states
[R600_PIPE_STATE_CLIP
] = rstate
;
1217 r600_context_pipe_state_set(rctx
, rstate
);
1219 cbuf
= pipe_user_buffer_create(ctx
->screen
,
1221 4*4*8, /* 8*4 floats */
1222 PIPE_BIND_CONSTANT_BUFFER
);
1223 r600_set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, 1, cbuf
);
1224 pipe_resource_reference(&cbuf
, NULL
);
1227 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
1228 const struct pipe_poly_stipple
*state
)
1232 static void evergreen_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1236 static void evergreen_get_scissor_rect(struct r600_context
*rctx
,
1237 unsigned tl_x
, unsigned tl_y
, unsigned br_x
, unsigned br_y
,
1238 uint32_t *tl
, uint32_t *br
)
1240 /* EG hw workaround */
1246 /* cayman hw workaround */
1247 if (rctx
->chip_class
== CAYMAN
) {
1248 if (br_x
== 1 && br_y
== 1)
1252 *tl
= S_028240_TL_X(tl_x
) | S_028240_TL_Y(tl_y
);
1253 *br
= S_028244_BR_X(br_x
) | S_028244_BR_Y(br_y
);
1256 static void evergreen_set_scissor_state(struct pipe_context
*ctx
,
1257 const struct pipe_scissor_state
*state
)
1259 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1260 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1266 evergreen_get_scissor_rect(rctx
, state
->minx
, state
->miny
, state
->maxx
, state
->maxy
, &tl
, &br
);
1268 rstate
->id
= R600_PIPE_STATE_SCISSOR
;
1269 r600_pipe_state_add_reg(rstate
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
, NULL
, 0);
1270 r600_pipe_state_add_reg(rstate
, R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
, NULL
, 0);
1272 free(rctx
->states
[R600_PIPE_STATE_SCISSOR
]);
1273 rctx
->states
[R600_PIPE_STATE_SCISSOR
] = rstate
;
1274 r600_context_pipe_state_set(rctx
, rstate
);
1277 static void evergreen_set_viewport_state(struct pipe_context
*ctx
,
1278 const struct pipe_viewport_state
*state
)
1280 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1281 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1286 rctx
->viewport
= *state
;
1287 rstate
->id
= R600_PIPE_STATE_VIEWPORT
;
1288 r600_pipe_state_add_reg(rstate
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]), NULL
, 0);
1289 r600_pipe_state_add_reg(rstate
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]), NULL
, 0);
1290 r600_pipe_state_add_reg(rstate
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]), NULL
, 0);
1291 r600_pipe_state_add_reg(rstate
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]), NULL
, 0);
1292 r600_pipe_state_add_reg(rstate
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]), NULL
, 0);
1293 r600_pipe_state_add_reg(rstate
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]), NULL
, 0);
1295 free(rctx
->states
[R600_PIPE_STATE_VIEWPORT
]);
1296 rctx
->states
[R600_PIPE_STATE_VIEWPORT
] = rstate
;
1297 r600_context_pipe_state_set(rctx
, rstate
);
1300 static void evergreen_cb(struct r600_context
*rctx
, struct r600_pipe_state
*rstate
,
1301 const struct pipe_framebuffer_state
*state
, int cb
)
1303 struct r600_screen
*rscreen
= rctx
->screen
;
1304 struct r600_resource_texture
*rtex
;
1305 struct r600_surface
*surf
;
1306 unsigned level
= state
->cbufs
[cb
]->u
.tex
.level
;
1307 unsigned pitch
, slice
;
1308 unsigned color_info
, color_attrib
;
1309 unsigned format
, swap
, ntype
, endian
;
1311 unsigned tile_type
, macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1312 const struct util_format_description
*desc
;
1314 unsigned blend_clamp
= 0, blend_bypass
= 0;
1316 surf
= (struct r600_surface
*)state
->cbufs
[cb
];
1317 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
1320 rctx
->have_depth_fb
= TRUE
;
1322 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
1323 r600_texture_depth_flush(&rctx
->context
, state
->cbufs
[cb
]->texture
, TRUE
);
1324 rtex
= rtex
->flushed_depth_texture
;
1327 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1328 if (!rscreen
->use_surface_alloc
) {
1329 offset
= r600_texture_get_offset(rtex
,
1330 level
, state
->cbufs
[cb
]->u
.tex
.first_layer
);
1331 pitch
= rtex
->pitch_in_blocks
[level
] / 8 - 1;
1332 slice
= rtex
->pitch_in_blocks
[level
] * surf
->aligned_height
/ 64;
1336 color_info
= S_028C70_ARRAY_MODE(rtex
->array_mode
[level
]);
1341 if (rtex
->array_mode
[level
] > V_028C70_ARRAY_LINEAR_ALIGNED
) {
1342 tile_type
= rtex
->tile_type
;
1344 /* workaround for linear buffers */
1348 offset
= rtex
->surface
.level
[level
].offset
;
1349 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1350 offset
+= rtex
->surface
.level
[level
].slice_size
*
1351 state
->cbufs
[cb
]->u
.tex
.first_layer
;
1353 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1354 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1359 switch (rtex
->surface
.level
[level
].mode
) {
1360 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1361 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1364 case RADEON_SURF_MODE_1D
:
1365 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1
);
1366 tile_type
= rtex
->tile_type
;
1368 case RADEON_SURF_MODE_2D
:
1369 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1
);
1370 tile_type
= rtex
->tile_type
;
1372 case RADEON_SURF_MODE_LINEAR
:
1374 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL
);
1378 tile_split
= rtex
->surface
.tile_split
;
1379 macro_aspect
= rtex
->surface
.mtilea
;
1380 bankw
= rtex
->surface
.bankw
;
1381 bankh
= rtex
->surface
.bankh
;
1382 tile_split
= eg_tile_split(tile_split
);
1383 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1384 bankw
= eg_bank_wh(bankw
);
1385 bankh
= eg_bank_wh(bankh
);
1387 /* 128 bit formats require tile type = 1 */
1388 if (rscreen
->chip_class
== CAYMAN
) {
1389 if (util_format_get_blocksize(surf
->base
.format
) >= 16)
1392 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1393 desc
= util_format_description(surf
->base
.format
);
1394 for (i
= 0; i
< 4; i
++) {
1395 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1400 color_attrib
= S_028C74_TILE_SPLIT(tile_split
)|
1401 S_028C74_NUM_BANKS(nbanks
) |
1402 S_028C74_BANK_WIDTH(bankw
) |
1403 S_028C74_BANK_HEIGHT(bankh
) |
1404 S_028C74_MACRO_TILE_ASPECT(macro_aspect
) |
1405 S_028C74_NON_DISP_TILING_ORDER(tile_type
);
1407 ntype
= V_028C70_NUMBER_UNORM
;
1408 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1409 ntype
= V_028C70_NUMBER_SRGB
;
1410 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1411 if (desc
->channel
[i
].normalized
)
1412 ntype
= V_028C70_NUMBER_SNORM
;
1413 else if (desc
->channel
[i
].pure_integer
)
1414 ntype
= V_028C70_NUMBER_SINT
;
1415 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1416 if (desc
->channel
[i
].normalized
)
1417 ntype
= V_028C70_NUMBER_UNORM
;
1418 else if (desc
->channel
[i
].pure_integer
)
1419 ntype
= V_028C70_NUMBER_UINT
;
1422 format
= r600_translate_colorformat(surf
->base
.format
);
1423 swap
= r600_translate_colorswap(surf
->base
.format
);
1424 if (rtex
->resource
.b
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1425 endian
= ENDIAN_NONE
;
1427 endian
= r600_colorformat_endian_swap(format
);
1430 /* blend clamp should be set for all NORM/SRGB types */
1431 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
1432 ntype
== V_028C70_NUMBER_SRGB
)
1435 /* set blend bypass according to docs if SINT/UINT or
1436 8/24 COLOR variants */
1437 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1438 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1439 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1444 color_info
|= S_028C70_FORMAT(format
) |
1445 S_028C70_COMP_SWAP(swap
) |
1446 S_028C70_BLEND_CLAMP(blend_clamp
) |
1447 S_028C70_BLEND_BYPASS(blend_bypass
) |
1448 S_028C70_NUMBER_TYPE(ntype
) |
1449 S_028C70_ENDIAN(endian
);
1451 /* EXPORT_NORM is an optimzation that can be enabled for better
1452 * performance in certain cases.
1453 * EXPORT_NORM can be enabled if:
1454 * - 11-bit or smaller UNORM/SNORM/SRGB
1455 * - 16-bit or smaller FLOAT
1457 /* XXX: This should probably be the same for all CBs if we want
1458 * useful alpha tests. */
1459 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1460 ((desc
->channel
[i
].size
< 12 &&
1461 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1462 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
1463 (desc
->channel
[i
].size
< 17 &&
1464 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1465 color_info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
1466 rctx
->export_16bpc
= true;
1468 rctx
->export_16bpc
= false;
1470 rctx
->alpha_ref_dirty
= true;
1473 offset
+= r600_resource_va(rctx
->context
.screen
, state
->cbufs
[cb
]->texture
);
1476 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1477 r600_pipe_state_add_reg(rstate
,
1478 R_028C60_CB_COLOR0_BASE
+ cb
* 0x3C,
1479 offset
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1480 r600_pipe_state_add_reg(rstate
,
1481 R_028C78_CB_COLOR0_DIM
+ cb
* 0x3C,
1483 r600_pipe_state_add_reg(rstate
,
1484 R_028C70_CB_COLOR0_INFO
+ cb
* 0x3C,
1485 color_info
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1486 r600_pipe_state_add_reg(rstate
,
1487 R_028C64_CB_COLOR0_PITCH
+ cb
* 0x3C,
1488 S_028C64_PITCH_TILE_MAX(pitch
),
1490 r600_pipe_state_add_reg(rstate
,
1491 R_028C68_CB_COLOR0_SLICE
+ cb
* 0x3C,
1492 S_028C68_SLICE_TILE_MAX(slice
),
1494 if (!rscreen
->use_surface_alloc
) {
1495 r600_pipe_state_add_reg(rstate
,
1496 R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C,
1497 0x00000000, NULL
, 0);
1499 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1500 r600_pipe_state_add_reg(rstate
,
1501 R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C,
1502 0x00000000, NULL
, 0);
1504 r600_pipe_state_add_reg(rstate
,
1505 R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C,
1506 S_028C6C_SLICE_START(state
->cbufs
[cb
]->u
.tex
.first_layer
) |
1507 S_028C6C_SLICE_MAX(state
->cbufs
[cb
]->u
.tex
.last_layer
),
1511 r600_pipe_state_add_reg(rstate
,
1512 R_028C74_CB_COLOR0_ATTRIB
+ cb
* 0x3C,
1514 &rtex
->resource
, RADEON_USAGE_READWRITE
);
1517 static void evergreen_db(struct r600_context
*rctx
, struct r600_pipe_state
*rstate
,
1518 const struct pipe_framebuffer_state
*state
)
1520 struct r600_screen
*rscreen
= rctx
->screen
;
1521 struct r600_resource_texture
*rtex
;
1522 struct r600_surface
*surf
;
1524 unsigned level
, first_layer
, pitch
, slice
, format
, array_mode
;
1525 unsigned macro_aspect
, tile_split
, bankh
, bankw
, z_info
, nbanks
;
1527 if (state
->zsbuf
== NULL
)
1530 surf
= (struct r600_surface
*)state
->zsbuf
;
1531 level
= surf
->base
.u
.tex
.level
;
1532 rtex
= (struct r600_resource_texture
*)surf
->base
.texture
;
1533 first_layer
= surf
->base
.u
.tex
.first_layer
;
1534 format
= r600_translate_dbformat(rtex
->real_format
);
1536 offset
= r600_resource_va(rctx
->context
.screen
, surf
->base
.texture
);
1537 /* XXX remove this once tiling is properly supported */
1538 if (!rscreen
->use_surface_alloc
) {
1539 /* XXX remove this once tiling is properly supported */
1540 array_mode
= rtex
->array_mode
[level
] ? rtex
->array_mode
[level
] :
1541 V_028C70_ARRAY_1D_TILED_THIN1
;
1543 offset
+= r600_texture_get_offset(rtex
, level
, first_layer
);
1544 pitch
= (rtex
->pitch_in_blocks
[level
] / 8) - 1;
1545 slice
= ((rtex
->pitch_in_blocks
[level
] * surf
->aligned_height
) / 64);
1554 offset
+= rtex
->surface
.level
[level
].offset
;
1555 pitch
= (rtex
->surface
.level
[level
].nblk_x
/ 8) - 1;
1556 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1560 switch (rtex
->surface
.level
[level
].mode
) {
1561 case RADEON_SURF_MODE_2D
:
1562 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1564 case RADEON_SURF_MODE_1D
:
1565 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1566 case RADEON_SURF_MODE_LINEAR
:
1568 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1571 tile_split
= rtex
->surface
.tile_split
;
1572 macro_aspect
= rtex
->surface
.mtilea
;
1573 bankw
= rtex
->surface
.bankw
;
1574 bankh
= rtex
->surface
.bankh
;
1575 tile_split
= eg_tile_split(tile_split
);
1576 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1577 bankw
= eg_bank_wh(bankw
);
1578 bankh
= eg_bank_wh(bankh
);
1580 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1583 z_info
= S_028040_ARRAY_MODE(array_mode
) |
1584 S_028040_FORMAT(format
) |
1585 S_028040_TILE_SPLIT(tile_split
)|
1586 S_028040_NUM_BANKS(nbanks
) |
1587 S_028040_BANK_WIDTH(bankw
) |
1588 S_028040_BANK_HEIGHT(bankh
) |
1589 S_028040_MACRO_TILE_ASPECT(macro_aspect
);
1591 r600_pipe_state_add_reg(rstate
, R_028048_DB_Z_READ_BASE
,
1592 offset
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1593 r600_pipe_state_add_reg(rstate
, R_028050_DB_Z_WRITE_BASE
,
1594 offset
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1595 if (!rscreen
->use_surface_alloc
) {
1596 r600_pipe_state_add_reg(rstate
, R_028008_DB_DEPTH_VIEW
,
1597 0x00000000, NULL
, 0);
1599 r600_pipe_state_add_reg(rstate
, R_028008_DB_DEPTH_VIEW
,
1600 S_028008_SLICE_START(state
->zsbuf
->u
.tex
.first_layer
) |
1601 S_028008_SLICE_MAX(state
->zsbuf
->u
.tex
.last_layer
),
1605 if (rtex
->stencil
) {
1606 uint64_t stencil_offset
=
1607 r600_texture_get_offset(rtex
->stencil
, level
, first_layer
);
1608 unsigned stile_split
;
1610 stile_split
= eg_tile_split(rtex
->stencil
->surface
.tile_split
);
1611 stencil_offset
+= r600_resource_va(rctx
->context
.screen
, (void*)rtex
->stencil
);
1612 stencil_offset
>>= 8;
1614 r600_pipe_state_add_reg(rstate
, R_02804C_DB_STENCIL_READ_BASE
,
1615 stencil_offset
, &rtex
->stencil
->resource
, RADEON_USAGE_READWRITE
);
1616 r600_pipe_state_add_reg(rstate
, R_028054_DB_STENCIL_WRITE_BASE
,
1617 stencil_offset
, &rtex
->stencil
->resource
, RADEON_USAGE_READWRITE
);
1618 r600_pipe_state_add_reg(rstate
, R_028044_DB_STENCIL_INFO
,
1619 1 | S_028044_TILE_SPLIT(stile_split
),
1620 &rtex
->stencil
->resource
, RADEON_USAGE_READWRITE
);
1622 if (rscreen
->use_surface_alloc
&& rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1623 uint64_t stencil_offset
= rtex
->surface
.stencil_offset
;
1624 unsigned stile_split
= rtex
->surface
.stencil_tile_split
;
1626 stile_split
= eg_tile_split(stile_split
);
1627 stencil_offset
+= r600_resource_va(rctx
->context
.screen
, surf
->base
.texture
);
1628 stencil_offset
+= rtex
->surface
.level
[level
].offset
/ 4;
1629 stencil_offset
>>= 8;
1631 r600_pipe_state_add_reg(rstate
, R_02804C_DB_STENCIL_READ_BASE
,
1632 stencil_offset
, &rtex
->resource
,
1633 RADEON_USAGE_READWRITE
);
1634 r600_pipe_state_add_reg(rstate
, R_028054_DB_STENCIL_WRITE_BASE
,
1635 stencil_offset
, &rtex
->resource
,
1636 RADEON_USAGE_READWRITE
);
1637 r600_pipe_state_add_reg(rstate
, R_028044_DB_STENCIL_INFO
,
1638 1 | S_028044_TILE_SPLIT(stile_split
),
1640 RADEON_USAGE_READWRITE
);
1642 r600_pipe_state_add_reg(rstate
, R_02804C_DB_STENCIL_READ_BASE
,
1643 offset
, &rtex
->resource
,
1644 RADEON_USAGE_READWRITE
);
1645 r600_pipe_state_add_reg(rstate
, R_028054_DB_STENCIL_WRITE_BASE
,
1646 offset
, &rtex
->resource
,
1647 RADEON_USAGE_READWRITE
);
1648 r600_pipe_state_add_reg(rstate
, R_028044_DB_STENCIL_INFO
,
1649 0, NULL
, RADEON_USAGE_READWRITE
);
1653 r600_pipe_state_add_reg(rstate
, R_028040_DB_Z_INFO
, z_info
,
1654 &rtex
->resource
, RADEON_USAGE_READWRITE
);
1655 r600_pipe_state_add_reg(rstate
, R_028058_DB_DEPTH_SIZE
,
1656 S_028058_PITCH_TILE_MAX(pitch
),
1658 r600_pipe_state_add_reg(rstate
, R_02805C_DB_DEPTH_SLICE
,
1659 S_02805C_SLICE_TILE_MAX(slice
),
1663 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
1664 const struct pipe_framebuffer_state
*state
)
1666 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1667 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1668 uint32_t shader_mask
, tl
, br
;
1673 r600_flush_framebuffer(rctx
, false);
1675 /* unreference old buffer and reference new one */
1676 rstate
->id
= R600_PIPE_STATE_FRAMEBUFFER
;
1678 util_copy_framebuffer_state(&rctx
->framebuffer
, state
);
1681 rctx
->have_depth_fb
= 0;
1682 rctx
->nr_cbufs
= state
->nr_cbufs
;
1683 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1684 evergreen_cb(rctx
, rstate
, state
, i
);
1687 evergreen_db(rctx
, rstate
, state
);
1691 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1692 shader_mask
|= 0xf << (i
* 4);
1695 evergreen_get_scissor_rect(rctx
, 0, 0, state
->width
, state
->height
, &tl
, &br
);
1697 r600_pipe_state_add_reg(rstate
,
1698 R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
,
1700 r600_pipe_state_add_reg(rstate
,
1701 R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
,
1703 r600_pipe_state_add_reg(rstate
, R_02823C_CB_SHADER_MASK
,
1704 shader_mask
, NULL
, 0);
1706 free(rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
]);
1707 rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
] = rstate
;
1708 r600_context_pipe_state_set(rctx
, rstate
);
1711 evergreen_polygon_offset_update(rctx
);
1715 static void evergreen_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1717 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1718 struct r600_atom_db_misc_state
*a
= (struct r600_atom_db_misc_state
*)atom
;
1719 unsigned db_count_control
= 0;
1720 unsigned db_render_override
=
1721 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
) |
1722 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
1723 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
1725 if (a
->occlusion_query_enabled
) {
1726 db_count_control
|= S_028004_PERFECT_ZPASS_COUNTS(1);
1727 db_render_override
|= S_02800C_NOOP_CULL_DISABLE(1);
1730 r600_write_context_reg(cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1731 r600_write_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
1734 static void evergreen_emit_streamout_config(struct r600_context
*rctx
, struct r600_atom
*atom
)
1736 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1737 struct r600_atom_eg_strmout_config
*a
= (struct r600_atom_eg_strmout_config
*)atom
;
1739 r600_write_context_reg(cs
, R_028B94_VGT_STRMOUT_CONFIG
,
1740 S_028B94_STREAMOUT_0_EN(a
->stream0_enable
) |
1741 S_028B94_RAST_STREAM(a
->rasterizer_discard
? 4 : 0));
1744 void evergreen_init_state_functions(struct r600_context
*rctx
)
1746 r600_init_atom(&rctx
->atom_db_misc_state
.atom
, evergreen_emit_db_misc_state
, 6, 0);
1747 r600_atom_dirty(rctx
, &rctx
->atom_db_misc_state
.atom
);
1748 r600_init_atom(&rctx
->atom_eg_strmout_config
.atom
, evergreen_emit_streamout_config
, 6, 0);
1749 r600_atom_dirty(rctx
, &rctx
->atom_eg_strmout_config
.atom
);
1751 rctx
->context
.create_blend_state
= evergreen_create_blend_state
;
1752 rctx
->context
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
1753 rctx
->context
.create_fs_state
= r600_create_shader_state
;
1754 rctx
->context
.create_rasterizer_state
= evergreen_create_rs_state
;
1755 rctx
->context
.create_sampler_state
= evergreen_create_sampler_state
;
1756 rctx
->context
.create_sampler_view
= evergreen_create_sampler_view
;
1757 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
1758 rctx
->context
.create_vs_state
= r600_create_shader_state
;
1759 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1760 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
1761 rctx
->context
.bind_fragment_sampler_states
= evergreen_bind_ps_sampler
;
1762 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
1763 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1764 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1765 rctx
->context
.bind_vertex_sampler_states
= evergreen_bind_vs_sampler
;
1766 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
1767 rctx
->context
.delete_blend_state
= r600_delete_state
;
1768 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
1769 rctx
->context
.delete_fs_state
= r600_delete_ps_shader
;
1770 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1771 rctx
->context
.delete_sampler_state
= r600_delete_state
;
1772 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
1773 rctx
->context
.delete_vs_state
= r600_delete_vs_shader
;
1774 rctx
->context
.set_blend_color
= r600_set_blend_color
;
1775 rctx
->context
.set_clip_state
= evergreen_set_clip_state
;
1776 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1777 rctx
->context
.set_fragment_sampler_views
= evergreen_set_ps_sampler_view
;
1778 rctx
->context
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
1779 rctx
->context
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
1780 rctx
->context
.set_sample_mask
= evergreen_set_sample_mask
;
1781 rctx
->context
.set_scissor_state
= evergreen_set_scissor_state
;
1782 rctx
->context
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
1783 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1784 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1785 rctx
->context
.set_vertex_sampler_views
= evergreen_set_vs_sampler_view
;
1786 rctx
->context
.set_viewport_state
= evergreen_set_viewport_state
;
1787 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1788 rctx
->context
.redefine_user_buffer
= u_default_redefine_user_buffer
;
1789 rctx
->context
.texture_barrier
= r600_texture_barrier
;
1790 rctx
->context
.create_stream_output_target
= r600_create_so_target
;
1791 rctx
->context
.stream_output_target_destroy
= r600_so_target_destroy
;
1792 rctx
->context
.set_stream_output_targets
= r600_set_so_targets
;
1795 static void cayman_init_atom_start_cs(struct r600_context
*rctx
)
1797 struct r600_command_buffer
*cb
= &rctx
->atom_start_cs
;
1799 r600_init_command_buffer(cb
, 256, EMIT_EARLY
);
1801 /* This must be first. */
1802 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1803 r600_store_value(cb
, 0x80000000);
1804 r600_store_value(cb
, 0x80000000);
1806 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
1807 r600_store_value(cb
, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
1808 /* always set the temp clauses */
1809 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
1811 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
1812 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
1813 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
1815 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
1817 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
1819 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
1820 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
1821 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
1822 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
1823 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
1824 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
1825 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
1826 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
1827 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
1828 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
1829 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
1830 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
1831 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
1832 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
1834 r600_store_context_reg(cb
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0);
1836 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
1837 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
1838 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
1840 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
1842 r600_store_context_reg(cb
, CM_R_028AA8_IA_MULTI_VGT_PARAM
, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
1844 r600_store_context_reg_seq(cb
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1845 r600_store_value(cb
, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
1846 r600_store_value(cb
, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
1848 r600_store_context_reg_seq(cb
, CM_R_0288E8_SQ_LDS_ALLOC
, 2);
1849 r600_store_value(cb
, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
1850 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
1852 r600_store_context_reg(cb
, CM_R_028804_DB_EQAA
, 0x110000);
1854 r600_store_context_reg_seq(cb
, R_028380_SQ_VTX_SEMANTIC_0
, 34);
1855 r600_store_value(cb
, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
1856 r600_store_value(cb
, 0);
1857 r600_store_value(cb
, 0);
1858 r600_store_value(cb
, 0);
1859 r600_store_value(cb
, 0);
1860 r600_store_value(cb
, 0);
1861 r600_store_value(cb
, 0);
1862 r600_store_value(cb
, 0);
1863 r600_store_value(cb
, 0);
1864 r600_store_value(cb
, 0);
1865 r600_store_value(cb
, 0);
1866 r600_store_value(cb
, 0);
1867 r600_store_value(cb
, 0);
1868 r600_store_value(cb
, 0);
1869 r600_store_value(cb
, 0);
1870 r600_store_value(cb
, 0);
1871 r600_store_value(cb
, 0);
1872 r600_store_value(cb
, 0);
1873 r600_store_value(cb
, 0);
1874 r600_store_value(cb
, 0);
1875 r600_store_value(cb
, 0);
1876 r600_store_value(cb
, 0);
1877 r600_store_value(cb
, 0);
1878 r600_store_value(cb
, 0);
1879 r600_store_value(cb
, 0);
1880 r600_store_value(cb
, 0);
1881 r600_store_value(cb
, 0);
1882 r600_store_value(cb
, 0);
1883 r600_store_value(cb
, 0);
1884 r600_store_value(cb
, 0);
1885 r600_store_value(cb
, 0);
1886 r600_store_value(cb
, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
1887 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
1888 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
1890 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
1892 r600_store_context_reg_seq(cb
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
1893 r600_store_value(cb
, ~0); /* CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 */
1894 r600_store_value(cb
, ~0); /* CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 */
1896 r600_store_context_reg_seq(cb
, R_028028_DB_STENCIL_CLEAR
, 2);
1897 r600_store_value(cb
, 0); /* R_028028_DB_STENCIL_CLEAR */
1898 r600_store_value(cb
, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
1900 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
1902 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
1903 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
1904 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
1905 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
1907 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
1908 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
1910 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
1911 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
1912 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
1914 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
1915 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
1916 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
1917 r600_store_context_reg(cb
, R_028B70_DB_ALPHA_TO_MASK
, 0x0000AA00);
1919 r600_store_context_reg_seq(cb
, CM_R_028BDC_PA_SC_LINE_CNTL
, 2);
1920 r600_store_value(cb
, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1921 r600_store_value(cb
, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1923 r600_store_context_reg_seq(cb
, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
1924 r600_store_value(cb
, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
1925 r600_store_value(cb
, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
1926 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
1927 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
1929 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
1930 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
1931 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
1933 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
1934 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
1935 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
1937 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO
));
1938 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO
));
1939 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
1941 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
1942 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
1944 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
1945 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
1948 void evergreen_init_atom_start_cs(struct r600_context
*rctx
)
1950 struct r600_command_buffer
*cb
= &rctx
->atom_start_cs
;
1955 int hs_prio
, cs_prio
, ls_prio
;
1969 int num_ps_stack_entries
;
1970 int num_vs_stack_entries
;
1971 int num_gs_stack_entries
;
1972 int num_es_stack_entries
;
1973 int num_hs_stack_entries
;
1974 int num_ls_stack_entries
;
1975 enum radeon_family family
;
1978 if (rctx
->chip_class
== CAYMAN
) {
1979 cayman_init_atom_start_cs(rctx
);
1983 r600_init_command_buffer(cb
, 256, EMIT_EARLY
);
1985 /* This must be first. */
1986 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1987 r600_store_value(cb
, 0x80000000);
1988 r600_store_value(cb
, 0x80000000);
1990 family
= rctx
->family
;
2009 num_ps_threads
= 96;
2010 num_vs_threads
= 16;
2011 num_gs_threads
= 16;
2012 num_es_threads
= 16;
2013 num_hs_threads
= 16;
2014 num_ls_threads
= 16;
2015 num_ps_stack_entries
= 42;
2016 num_vs_stack_entries
= 42;
2017 num_gs_stack_entries
= 42;
2018 num_es_stack_entries
= 42;
2019 num_hs_stack_entries
= 42;
2020 num_ls_stack_entries
= 42;
2030 num_ps_threads
= 128;
2031 num_vs_threads
= 20;
2032 num_gs_threads
= 20;
2033 num_es_threads
= 20;
2034 num_hs_threads
= 20;
2035 num_ls_threads
= 20;
2036 num_ps_stack_entries
= 42;
2037 num_vs_stack_entries
= 42;
2038 num_gs_stack_entries
= 42;
2039 num_es_stack_entries
= 42;
2040 num_hs_stack_entries
= 42;
2041 num_ls_stack_entries
= 42;
2051 num_ps_threads
= 128;
2052 num_vs_threads
= 20;
2053 num_gs_threads
= 20;
2054 num_es_threads
= 20;
2055 num_hs_threads
= 20;
2056 num_ls_threads
= 20;
2057 num_ps_stack_entries
= 85;
2058 num_vs_stack_entries
= 85;
2059 num_gs_stack_entries
= 85;
2060 num_es_stack_entries
= 85;
2061 num_hs_stack_entries
= 85;
2062 num_ls_stack_entries
= 85;
2073 num_ps_threads
= 128;
2074 num_vs_threads
= 20;
2075 num_gs_threads
= 20;
2076 num_es_threads
= 20;
2077 num_hs_threads
= 20;
2078 num_ls_threads
= 20;
2079 num_ps_stack_entries
= 85;
2080 num_vs_stack_entries
= 85;
2081 num_gs_stack_entries
= 85;
2082 num_es_stack_entries
= 85;
2083 num_hs_stack_entries
= 85;
2084 num_ls_stack_entries
= 85;
2094 num_ps_threads
= 96;
2095 num_vs_threads
= 16;
2096 num_gs_threads
= 16;
2097 num_es_threads
= 16;
2098 num_hs_threads
= 16;
2099 num_ls_threads
= 16;
2100 num_ps_stack_entries
= 42;
2101 num_vs_stack_entries
= 42;
2102 num_gs_stack_entries
= 42;
2103 num_es_stack_entries
= 42;
2104 num_hs_stack_entries
= 42;
2105 num_ls_stack_entries
= 42;
2115 num_ps_threads
= 96;
2116 num_vs_threads
= 25;
2117 num_gs_threads
= 25;
2118 num_es_threads
= 25;
2119 num_hs_threads
= 25;
2120 num_ls_threads
= 25;
2121 num_ps_stack_entries
= 42;
2122 num_vs_stack_entries
= 42;
2123 num_gs_stack_entries
= 42;
2124 num_es_stack_entries
= 42;
2125 num_hs_stack_entries
= 42;
2126 num_ls_stack_entries
= 42;
2136 num_ps_threads
= 96;
2137 num_vs_threads
= 25;
2138 num_gs_threads
= 25;
2139 num_es_threads
= 25;
2140 num_hs_threads
= 25;
2141 num_ls_threads
= 25;
2142 num_ps_stack_entries
= 85;
2143 num_vs_stack_entries
= 85;
2144 num_gs_stack_entries
= 85;
2145 num_es_stack_entries
= 85;
2146 num_hs_stack_entries
= 85;
2147 num_ls_stack_entries
= 85;
2157 num_ps_threads
= 128;
2158 num_vs_threads
= 20;
2159 num_gs_threads
= 20;
2160 num_es_threads
= 20;
2161 num_hs_threads
= 20;
2162 num_ls_threads
= 20;
2163 num_ps_stack_entries
= 85;
2164 num_vs_stack_entries
= 85;
2165 num_gs_stack_entries
= 85;
2166 num_es_stack_entries
= 85;
2167 num_hs_stack_entries
= 85;
2168 num_ls_stack_entries
= 85;
2178 num_ps_threads
= 128;
2179 num_vs_threads
= 20;
2180 num_gs_threads
= 20;
2181 num_es_threads
= 20;
2182 num_hs_threads
= 20;
2183 num_ls_threads
= 20;
2184 num_ps_stack_entries
= 42;
2185 num_vs_stack_entries
= 42;
2186 num_gs_stack_entries
= 42;
2187 num_es_stack_entries
= 42;
2188 num_hs_stack_entries
= 42;
2189 num_ls_stack_entries
= 42;
2199 num_ps_threads
= 128;
2200 num_vs_threads
= 10;
2201 num_gs_threads
= 10;
2202 num_es_threads
= 10;
2203 num_hs_threads
= 10;
2204 num_ls_threads
= 10;
2205 num_ps_stack_entries
= 42;
2206 num_vs_stack_entries
= 42;
2207 num_gs_stack_entries
= 42;
2208 num_es_stack_entries
= 42;
2209 num_hs_stack_entries
= 42;
2210 num_ls_stack_entries
= 42;
2223 tmp
|= S_008C00_VC_ENABLE(1);
2226 tmp
|= S_008C00_EXPORT_SRC_C(1);
2227 tmp
|= S_008C00_CS_PRIO(cs_prio
);
2228 tmp
|= S_008C00_LS_PRIO(ls_prio
);
2229 tmp
|= S_008C00_HS_PRIO(hs_prio
);
2230 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2231 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2232 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2233 tmp
|= S_008C00_ES_PRIO(es_prio
);
2235 /* enable dynamic GPR resource management */
2236 if (rctx
->screen
->info
.drm_minor
>= 7) {
2237 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2238 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2239 /* always set temp clauses */
2240 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2241 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2242 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2243 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2244 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2245 r600_store_context_reg(cb
, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
,
2246 S_028838_PS_GPRS(0x1e) |
2247 S_028838_VS_GPRS(0x1e) |
2248 S_028838_GS_GPRS(0x1e) |
2249 S_028838_ES_GPRS(0x1e) |
2250 S_028838_HS_GPRS(0x1e) |
2251 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2253 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 4);
2254 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2256 tmp
= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
2257 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
2258 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
2259 r600_store_value(cb
, tmp
); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2261 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2262 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2263 r600_store_value(cb
, tmp
); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2265 tmp
= S_008C0C_NUM_HS_GPRS(num_hs_gprs
);
2266 tmp
|= S_008C0C_NUM_HS_GPRS(num_ls_gprs
);
2267 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2270 tmp
= S_008C18_NUM_PS_THREADS(num_ps_threads
);
2271 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
2272 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
2273 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
2274 r600_store_config_reg_seq(cb
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, 5);
2275 r600_store_value(cb
, tmp
); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2277 tmp
= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
2278 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
2279 r600_store_value(cb
, tmp
); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2281 tmp
= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2282 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2283 r600_store_value(cb
, tmp
); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2285 tmp
= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2286 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2287 r600_store_value(cb
, tmp
); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2289 tmp
= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
2290 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
2291 r600_store_value(cb
, tmp
); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2293 r600_store_config_reg(cb
, R_008E2C_SQ_LDS_RESOURCE_MGMT
,
2294 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2296 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2297 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2299 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
2301 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2302 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2303 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2304 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2305 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2306 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2307 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2309 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2310 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2311 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2312 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2313 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2315 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2316 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2317 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2318 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2319 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2320 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2321 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2322 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2323 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2324 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2325 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2326 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2327 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2328 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2330 r600_store_context_reg(cb
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0);
2332 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2333 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
2334 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2336 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2338 r600_store_context_reg_seq(cb
, R_028380_SQ_VTX_SEMANTIC_0
, 34);
2339 r600_store_value(cb
, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2340 r600_store_value(cb
, 0);
2341 r600_store_value(cb
, 0);
2342 r600_store_value(cb
, 0);
2343 r600_store_value(cb
, 0);
2344 r600_store_value(cb
, 0);
2345 r600_store_value(cb
, 0);
2346 r600_store_value(cb
, 0);
2347 r600_store_value(cb
, 0);
2348 r600_store_value(cb
, 0);
2349 r600_store_value(cb
, 0);
2350 r600_store_value(cb
, 0);
2351 r600_store_value(cb
, 0);
2352 r600_store_value(cb
, 0);
2353 r600_store_value(cb
, 0);
2354 r600_store_value(cb
, 0);
2355 r600_store_value(cb
, 0);
2356 r600_store_value(cb
, 0);
2357 r600_store_value(cb
, 0);
2358 r600_store_value(cb
, 0);
2359 r600_store_value(cb
, 0);
2360 r600_store_value(cb
, 0);
2361 r600_store_value(cb
, 0);
2362 r600_store_value(cb
, 0);
2363 r600_store_value(cb
, 0);
2364 r600_store_value(cb
, 0);
2365 r600_store_value(cb
, 0);
2366 r600_store_value(cb
, 0);
2367 r600_store_value(cb
, 0);
2368 r600_store_value(cb
, 0);
2369 r600_store_value(cb
, 0);
2370 r600_store_value(cb
, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2371 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2372 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2374 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2376 r600_store_context_reg_seq(cb
, R_028028_DB_STENCIL_CLEAR
, 2);
2377 r600_store_value(cb
, 0); /* R_028028_DB_STENCIL_CLEAR */
2378 r600_store_value(cb
, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2380 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2381 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2382 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2384 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
2385 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2386 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2388 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2389 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
2390 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2392 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2393 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2394 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2395 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2397 r600_store_context_reg(cb
, R_028B70_DB_ALPHA_TO_MASK
, 0x0000AA00);
2399 r600_store_context_reg_seq(cb
, R_028C00_PA_SC_LINE_CNTL
, 2);
2400 r600_store_value(cb
, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
2401 r600_store_value(cb
, 0); /* R_028C04_PA_SC_AA_CONFIG */
2403 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 5);
2404 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2405 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2406 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2407 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2408 r600_store_value(cb
, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
2410 r600_store_context_reg(cb
, R_028C3C_PA_SC_AA_MASK
, ~0);
2412 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2413 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2414 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2416 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2417 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2418 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2420 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO
));
2421 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO
));
2422 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2424 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2425 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2427 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2428 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2431 void evergreen_polygon_offset_update(struct r600_context
*rctx
)
2433 struct r600_pipe_state state
;
2435 state
.id
= R600_PIPE_STATE_POLYGON_OFFSET
;
2437 if (rctx
->rasterizer
&& rctx
->framebuffer
.zsbuf
) {
2438 float offset_units
= rctx
->rasterizer
->offset_units
;
2439 unsigned offset_db_fmt_cntl
= 0, depth
;
2441 switch (rctx
->framebuffer
.zsbuf
->texture
->format
) {
2442 case PIPE_FORMAT_Z24X8_UNORM
:
2443 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2445 offset_units
*= 2.0f
;
2447 case PIPE_FORMAT_Z32_FLOAT
:
2448 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2450 offset_units
*= 1.0f
;
2451 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2453 case PIPE_FORMAT_Z16_UNORM
:
2455 offset_units
*= 4.0f
;
2460 /* XXX some of those reg can be computed with cso */
2461 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
2462 r600_pipe_state_add_reg(&state
,
2463 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
2464 fui(rctx
->rasterizer
->offset_scale
), NULL
, 0);
2465 r600_pipe_state_add_reg(&state
,
2466 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
2467 fui(offset_units
), NULL
, 0);
2468 r600_pipe_state_add_reg(&state
,
2469 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
2470 fui(rctx
->rasterizer
->offset_scale
), NULL
, 0);
2471 r600_pipe_state_add_reg(&state
,
2472 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
2473 fui(offset_units
), NULL
, 0);
2474 r600_pipe_state_add_reg(&state
,
2475 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
2476 offset_db_fmt_cntl
, NULL
, 0);
2477 r600_context_pipe_state_set(rctx
, &state
);
2481 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2483 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2484 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2485 struct r600_shader
*rshader
= &shader
->shader
;
2486 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
2487 int pos_index
= -1, face_index
= -1;
2489 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
2490 unsigned spi_baryc_cntl
, sid
, tmp
, idx
= 0;
2494 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2495 for (i
= 0; i
< rshader
->ninput
; i
++) {
2496 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2497 POSITION goes via GPRs from the SC so isn't counted */
2498 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2500 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
2504 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
2506 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
2507 have_perspective
= TRUE
;
2508 if (rshader
->input
[i
].centroid
)
2509 have_centroid
= TRUE
;
2512 sid
= rshader
->input
[i
].spi_sid
;
2516 tmp
= S_028644_SEMANTIC(sid
);
2518 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2519 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2520 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2521 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
)) {
2522 tmp
|= S_028644_FLAT_SHADE(1);
2525 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2526 (rctx
->sprite_coord_enable
& (1 << rshader
->input
[i
].sid
))) {
2527 tmp
|= S_028644_PT_SPRITE_TEX(1);
2530 r600_pipe_state_add_reg(rstate
, R_028644_SPI_PS_INPUT_CNTL_0
+ idx
* 4,
2537 for (i
= 0; i
< rshader
->noutput
; i
++) {
2538 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2539 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(1);
2540 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2541 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(1);
2543 if (rshader
->uses_kill
)
2544 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2548 for (i
= 0; i
< rshader
->noutput
; i
++) {
2549 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2550 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2552 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
2553 if (rshader
->fs_write_all
)
2554 num_cout
= rshader
->nr_cbufs
;
2559 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
2561 /* always at least export 1 component per pixel */
2567 have_perspective
= TRUE
;
2570 if (!have_perspective
&& !have_linear
)
2571 have_perspective
= TRUE
;
2573 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
2574 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
2575 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
2577 if (pos_index
!= -1) {
2578 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
2579 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
2580 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
2584 spi_ps_in_control_1
= 0;
2585 if (face_index
!= -1) {
2586 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2587 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2591 if (have_perspective
)
2592 spi_baryc_cntl
|= S_0286E0_PERSP_CENTER_ENA(1) |
2593 S_0286E0_PERSP_CENTROID_ENA(have_centroid
);
2595 spi_baryc_cntl
|= S_0286E0_LINEAR_CENTER_ENA(1) |
2596 S_0286E0_LINEAR_CENTROID_ENA(have_centroid
);
2598 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
,
2599 spi_ps_in_control_0
, NULL
, 0);
2600 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
,
2601 spi_ps_in_control_1
, NULL
, 0);
2602 r600_pipe_state_add_reg(rstate
, R_0286E4_SPI_PS_IN_CONTROL_2
,
2604 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
, NULL
, 0);
2605 r600_pipe_state_add_reg(rstate
,
2606 R_0286E0_SPI_BARYC_CNTL
,
2610 r600_pipe_state_add_reg(rstate
,
2611 R_028840_SQ_PGM_START_PS
,
2612 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8,
2613 shader
->bo
, RADEON_USAGE_READ
);
2614 r600_pipe_state_add_reg(rstate
,
2615 R_028844_SQ_PGM_RESOURCES_PS
,
2616 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
2617 S_028844_PRIME_CACHE_ON_DRAW(1) |
2618 S_028844_STACK_SIZE(rshader
->bc
.nstack
),
2620 r600_pipe_state_add_reg(rstate
,
2621 R_02884C_SQ_PGM_EXPORTS_PS
,
2622 exports_ps
, NULL
, 0);
2623 r600_pipe_state_add_reg(rstate
, R_02880C_DB_SHADER_CONTROL
,
2627 shader
->sprite_coord_enable
= rctx
->sprite_coord_enable
;
2628 if (rctx
->rasterizer
)
2629 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
2632 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2634 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2635 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2636 struct r600_shader
*rshader
= &shader
->shader
;
2637 unsigned spi_vs_out_id
[10] = {};
2638 unsigned i
, tmp
, nparams
= 0;
2640 /* clear previous register */
2643 for (i
= 0; i
< rshader
->noutput
; i
++) {
2644 if (rshader
->output
[i
].spi_sid
) {
2645 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
2646 spi_vs_out_id
[nparams
/ 4] |= tmp
;
2651 for (i
= 0; i
< 10; i
++) {
2652 r600_pipe_state_add_reg(rstate
,
2653 R_02861C_SPI_VS_OUT_ID_0
+ i
* 4,
2654 spi_vs_out_id
[i
], NULL
, 0);
2657 /* Certain attributes (position, psize, etc.) don't count as params.
2658 * VS is required to export at least one param and r600_shader_from_tgsi()
2659 * takes care of adding a dummy export.
2664 r600_pipe_state_add_reg(rstate
,
2665 R_0286C4_SPI_VS_OUT_CONFIG
,
2666 S_0286C4_VS_EXPORT_COUNT(nparams
- 1),
2668 r600_pipe_state_add_reg(rstate
,
2669 R_028860_SQ_PGM_RESOURCES_VS
,
2670 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
2671 S_028860_STACK_SIZE(rshader
->bc
.nstack
),
2673 r600_pipe_state_add_reg(rstate
,
2674 R_02885C_SQ_PGM_START_VS
,
2675 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8,
2676 shader
->bo
, RADEON_USAGE_READ
);
2678 shader
->pa_cl_vs_out_cntl
=
2679 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
2680 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
2681 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
2682 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
);
2685 void evergreen_fetch_shader(struct pipe_context
*ctx
,
2686 struct r600_vertex_element
*ve
)
2688 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2689 struct r600_pipe_state
*rstate
= &ve
->rstate
;
2690 rstate
->id
= R600_PIPE_STATE_FETCH_SHADER
;
2692 r600_pipe_state_add_reg(rstate
, R_0288A4_SQ_PGM_START_FS
,
2693 r600_resource_va(ctx
->screen
, (void *)ve
->fetch_shader
) >> 8,
2694 ve
->fetch_shader
, RADEON_USAGE_READ
);
2697 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
)
2699 struct pipe_depth_stencil_alpha_state dsa
;
2700 struct r600_pipe_state
*rstate
;
2702 memset(&dsa
, 0, sizeof(dsa
));
2704 rstate
= rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
2705 r600_pipe_state_add_reg(rstate
,
2706 R_028000_DB_RENDER_CONTROL
,
2707 S_028000_DEPTH_COPY_ENABLE(1) |
2708 S_028000_STENCIL_COPY_ENABLE(1) |
2709 S_028000_COPY_CENTROID(1),
2711 /* Don't set the 'is_flush' flag in r600_pipe_dsa, evergreen doesn't need it. */
2715 void evergreen_pipe_init_buffer_resource(struct r600_context
*rctx
,
2716 struct r600_pipe_resource_state
*rstate
)
2718 rstate
->id
= R600_PIPE_STATE_RESOURCE
;
2721 rstate
->bo
[0] = NULL
;
2723 rstate
->val
[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2724 rstate
->val
[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
2725 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
2726 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
2727 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
);
2731 rstate
->val
[7] = 0xc0000000;
2735 void evergreen_pipe_mod_buffer_resource(struct pipe_context
*ctx
,
2736 struct r600_pipe_resource_state
*rstate
,
2737 struct r600_resource
*rbuffer
,
2738 unsigned offset
, unsigned stride
,
2739 enum radeon_bo_usage usage
)
2743 va
= r600_resource_va(ctx
->screen
, (void *)rbuffer
);
2744 rstate
->bo
[0] = rbuffer
;
2745 rstate
->bo_usage
[0] = usage
;
2746 rstate
->val
[0] = (offset
+ va
) & 0xFFFFFFFFUL
;
2747 rstate
->val
[1] = rbuffer
->buf
->size
- offset
- 1;
2748 rstate
->val
[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2749 S_030008_STRIDE(stride
) |
2750 (((va
+ offset
) >> 32UL) & 0xFF);