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r600/eg: update shader stage emission/tf param for tess.
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static inline unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
39 break;
40 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
41 break;
42 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
43 default:
44 case RADEON_SURF_MODE_LINEAR: return V_028C70_ARRAY_LINEAR_GENERAL;
45 }
46 }
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
174 {
175 switch (dim) {
176 default:
177 case PIPE_TEXTURE_1D:
178 return V_030000_SQ_TEX_DIM_1D;
179 case PIPE_TEXTURE_1D_ARRAY:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY;
181 case PIPE_TEXTURE_2D:
182 case PIPE_TEXTURE_RECT:
183 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
184 V_030000_SQ_TEX_DIM_2D;
185 case PIPE_TEXTURE_2D_ARRAY:
186 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
187 V_030000_SQ_TEX_DIM_2D_ARRAY;
188 case PIPE_TEXTURE_3D:
189 return V_030000_SQ_TEX_DIM_3D;
190 case PIPE_TEXTURE_CUBE:
191 case PIPE_TEXTURE_CUBE_ARRAY:
192 return V_030000_SQ_TEX_DIM_CUBEMAP;
193 }
194 }
195
196 static uint32_t r600_translate_dbformat(enum pipe_format format)
197 {
198 switch (format) {
199 case PIPE_FORMAT_Z16_UNORM:
200 return V_028040_Z_16;
201 case PIPE_FORMAT_Z24X8_UNORM:
202 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
203 case PIPE_FORMAT_X8Z24_UNORM:
204 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
205 return V_028040_Z_24;
206 case PIPE_FORMAT_Z32_FLOAT:
207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
208 return V_028040_Z_32_FLOAT;
209 default:
210 return ~0U;
211 }
212 }
213
214 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
215 {
216 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
217 }
218
219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
220 {
221 return r600_translate_colorformat(chip, format) != ~0U &&
222 r600_translate_colorswap(format) != ~0U;
223 }
224
225 static bool r600_is_zs_format_supported(enum pipe_format format)
226 {
227 return r600_translate_dbformat(format) != ~0U;
228 }
229
230 boolean evergreen_is_format_supported(struct pipe_screen *screen,
231 enum pipe_format format,
232 enum pipe_texture_target target,
233 unsigned sample_count,
234 unsigned usage)
235 {
236 struct r600_screen *rscreen = (struct r600_screen*)screen;
237 unsigned retval = 0;
238
239 if (target >= PIPE_MAX_TEXTURE_TYPES) {
240 R600_ERR("r600: unsupported texture type %d\n", target);
241 return FALSE;
242 }
243
244 if (!util_format_is_supported(format, usage))
245 return FALSE;
246
247 if (sample_count > 1) {
248 if (!rscreen->has_msaa)
249 return FALSE;
250
251 switch (sample_count) {
252 case 2:
253 case 4:
254 case 8:
255 break;
256 default:
257 return FALSE;
258 }
259 }
260
261 if (usage & PIPE_BIND_SAMPLER_VIEW) {
262 if (target == PIPE_BUFFER) {
263 if (r600_is_vertex_format_supported(format))
264 retval |= PIPE_BIND_SAMPLER_VIEW;
265 } else {
266 if (r600_is_sampler_format_supported(screen, format))
267 retval |= PIPE_BIND_SAMPLER_VIEW;
268 }
269 }
270
271 if ((usage & (PIPE_BIND_RENDER_TARGET |
272 PIPE_BIND_DISPLAY_TARGET |
273 PIPE_BIND_SCANOUT |
274 PIPE_BIND_SHARED |
275 PIPE_BIND_BLENDABLE)) &&
276 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
277 retval |= usage &
278 (PIPE_BIND_RENDER_TARGET |
279 PIPE_BIND_DISPLAY_TARGET |
280 PIPE_BIND_SCANOUT |
281 PIPE_BIND_SHARED);
282 if (!util_format_is_pure_integer(format) &&
283 !util_format_is_depth_or_stencil(format))
284 retval |= usage & PIPE_BIND_BLENDABLE;
285 }
286
287 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
288 r600_is_zs_format_supported(format)) {
289 retval |= PIPE_BIND_DEPTH_STENCIL;
290 }
291
292 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
293 r600_is_vertex_format_supported(format)) {
294 retval |= PIPE_BIND_VERTEX_BUFFER;
295 }
296
297 if (usage & PIPE_BIND_TRANSFER_READ)
298 retval |= PIPE_BIND_TRANSFER_READ;
299 if (usage & PIPE_BIND_TRANSFER_WRITE)
300 retval |= PIPE_BIND_TRANSFER_WRITE;
301
302 return retval == usage;
303 }
304
305 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
306 const struct pipe_blend_state *state, int mode)
307 {
308 uint32_t color_control = 0, target_mask = 0;
309 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
310
311 if (!blend) {
312 return NULL;
313 }
314
315 r600_init_command_buffer(&blend->buffer, 20);
316 r600_init_command_buffer(&blend->buffer_no_blend, 20);
317
318 if (state->logicop_enable) {
319 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
320 } else {
321 color_control |= (0xcc << 16);
322 }
323 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
324 if (state->independent_blend_enable) {
325 for (int i = 0; i < 8; i++) {
326 target_mask |= (state->rt[i].colormask << (4 * i));
327 }
328 } else {
329 for (int i = 0; i < 8; i++) {
330 target_mask |= (state->rt[0].colormask << (4 * i));
331 }
332 }
333
334 /* only have dual source on MRT0 */
335 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
336 blend->cb_target_mask = target_mask;
337 blend->alpha_to_one = state->alpha_to_one;
338
339 if (target_mask)
340 color_control |= S_028808_MODE(mode);
341 else
342 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
343
344
345 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
346 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
347 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
348 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
349 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
350 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
351 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
352 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
353
354 /* Copy over the dwords set so far into buffer_no_blend.
355 * Only the CB_BLENDi_CONTROL registers must be set after this. */
356 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
357 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
358
359 for (int i = 0; i < 8; i++) {
360 /* state->rt entries > 0 only written if independent blending */
361 const int j = state->independent_blend_enable ? i : 0;
362
363 unsigned eqRGB = state->rt[j].rgb_func;
364 unsigned srcRGB = state->rt[j].rgb_src_factor;
365 unsigned dstRGB = state->rt[j].rgb_dst_factor;
366 unsigned eqA = state->rt[j].alpha_func;
367 unsigned srcA = state->rt[j].alpha_src_factor;
368 unsigned dstA = state->rt[j].alpha_dst_factor;
369 uint32_t bc = 0;
370
371 r600_store_value(&blend->buffer_no_blend, 0);
372
373 if (!state->rt[j].blend_enable) {
374 r600_store_value(&blend->buffer, 0);
375 continue;
376 }
377
378 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
379 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
380 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
381 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
382
383 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
384 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
385 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
386 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
387 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
388 }
389 r600_store_value(&blend->buffer, bc);
390 }
391 return blend;
392 }
393
394 static void *evergreen_create_blend_state(struct pipe_context *ctx,
395 const struct pipe_blend_state *state)
396 {
397
398 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
399 }
400
401 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
402 const struct pipe_depth_stencil_alpha_state *state)
403 {
404 unsigned db_depth_control, alpha_test_control, alpha_ref;
405 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
406
407 if (!dsa) {
408 return NULL;
409 }
410
411 r600_init_command_buffer(&dsa->buffer, 3);
412
413 dsa->valuemask[0] = state->stencil[0].valuemask;
414 dsa->valuemask[1] = state->stencil[1].valuemask;
415 dsa->writemask[0] = state->stencil[0].writemask;
416 dsa->writemask[1] = state->stencil[1].writemask;
417 dsa->zwritemask = state->depth.writemask;
418
419 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
420 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
421 S_028800_ZFUNC(state->depth.func);
422
423 /* stencil */
424 if (state->stencil[0].enabled) {
425 db_depth_control |= S_028800_STENCIL_ENABLE(1);
426 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
427 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
428 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
429 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
430
431 if (state->stencil[1].enabled) {
432 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
433 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
434 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
435 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
436 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
437 }
438 }
439
440 /* alpha */
441 alpha_test_control = 0;
442 alpha_ref = 0;
443 if (state->alpha.enabled) {
444 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
445 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
446 alpha_ref = fui(state->alpha.ref_value);
447 }
448 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
449 dsa->alpha_ref = alpha_ref;
450
451 /* misc */
452 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
453 return dsa;
454 }
455
456 static void *evergreen_create_rs_state(struct pipe_context *ctx,
457 const struct pipe_rasterizer_state *state)
458 {
459 struct r600_context *rctx = (struct r600_context *)ctx;
460 unsigned tmp, spi_interp;
461 float psize_min, psize_max;
462 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
463
464 if (!rs) {
465 return NULL;
466 }
467
468 r600_init_command_buffer(&rs->buffer, 30);
469
470 rs->flatshade = state->flatshade;
471 rs->sprite_coord_enable = state->sprite_coord_enable;
472 rs->two_side = state->light_twoside;
473 rs->clip_plane_enable = state->clip_plane_enable;
474 rs->pa_sc_line_stipple = state->line_stipple_enable ?
475 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
476 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
477 rs->pa_cl_clip_cntl =
478 S_028810_PS_UCP_MODE(3) |
479 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
480 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
481 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
482 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
483 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
484 rs->multisample_enable = state->multisample;
485
486 /* offset */
487 rs->offset_units = state->offset_units;
488 rs->offset_scale = state->offset_scale * 16.0f;
489 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
490
491 if (state->point_size_per_vertex) {
492 psize_min = util_get_min_point_size(state);
493 psize_max = 8192;
494 } else {
495 /* Force the point size to be as if the vertex output was disabled. */
496 psize_min = state->point_size;
497 psize_max = state->point_size;
498 }
499
500 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
501 if (state->sprite_coord_enable) {
502 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
503 S_0286D4_PNT_SPRITE_OVRD_X(2) |
504 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
505 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
506 S_0286D4_PNT_SPRITE_OVRD_W(1);
507 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
508 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
509 }
510 }
511
512 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
513 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
514 tmp = r600_pack_float_12p4(state->point_size/2);
515 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
516 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
517 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
518 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
519 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
520 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
521 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
522
523 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
524 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
525 S_028A48_MSAA_ENABLE(state->multisample) |
526 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
527 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
528
529 if (rctx->b.chip_class == CAYMAN) {
530 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
531 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
532 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
533 } else {
534 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
535 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
536 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
537 }
538
539 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
540 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
541 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
542 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
543 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
544 S_028814_FACE(!state->front_ccw) |
545 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
546 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
547 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
548 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
549 state->fill_back != PIPE_POLYGON_MODE_FILL) |
550 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
551 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
552 return rs;
553 }
554
555 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
556 const struct pipe_sampler_state *state)
557 {
558 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
559 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
560
561 if (!ss) {
562 return NULL;
563 }
564
565 ss->border_color_use = sampler_state_needs_border_color(state);
566
567 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
568 ss->tex_sampler_words[0] =
569 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
570 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
571 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
572 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
573 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
574 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
575 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
576 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
577 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
578 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
579 ss->tex_sampler_words[1] =
580 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
581 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
582 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
583 ss->tex_sampler_words[2] =
584 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
585 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
586 S_03C008_TYPE(1);
587
588 if (ss->border_color_use) {
589 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
590 }
591 return ss;
592 }
593
594 static struct pipe_sampler_view *
595 texture_buffer_sampler_view(struct r600_context *rctx,
596 struct r600_pipe_sampler_view *view,
597 unsigned width0, unsigned height0)
598
599 {
600 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
601 uint64_t va;
602 int stride = util_format_get_blocksize(view->base.format);
603 unsigned format, num_format, format_comp, endian;
604 unsigned swizzle_res;
605 unsigned char swizzle[4];
606 const struct util_format_description *desc;
607 unsigned offset = view->base.u.buf.first_element * stride;
608 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
609
610 swizzle[0] = view->base.swizzle_r;
611 swizzle[1] = view->base.swizzle_g;
612 swizzle[2] = view->base.swizzle_b;
613 swizzle[3] = view->base.swizzle_a;
614
615 r600_vertex_data_type(view->base.format,
616 &format, &num_format, &format_comp,
617 &endian);
618
619 desc = util_format_description(view->base.format);
620
621 swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
622
623 va = tmp->resource.gpu_address + offset;
624 view->tex_resource = &tmp->resource;
625
626 view->skip_mip_address_reloc = true;
627 view->tex_resource_words[0] = va;
628 view->tex_resource_words[1] = size - 1;
629 view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
630 S_030008_STRIDE(stride) |
631 S_030008_DATA_FORMAT(format) |
632 S_030008_NUM_FORMAT_ALL(num_format) |
633 S_030008_FORMAT_COMP_ALL(format_comp) |
634 S_030008_ENDIAN_SWAP(endian);
635 view->tex_resource_words[3] = swizzle_res;
636 /*
637 * in theory dword 4 is for number of elements, for use with resinfo,
638 * but it seems to utterly fail to work, the amd gpu shader analyser
639 * uses a const buffer to store the element sizes for buffer txq
640 */
641 view->tex_resource_words[4] = 0;
642 view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
643 view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
644
645 if (tmp->resource.gpu_address)
646 LIST_ADDTAIL(&view->list, &rctx->b.texture_buffers);
647 return &view->base;
648 }
649
650 struct pipe_sampler_view *
651 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
652 struct pipe_resource *texture,
653 const struct pipe_sampler_view *state,
654 unsigned width0, unsigned height0,
655 unsigned force_level)
656 {
657 struct r600_context *rctx = (struct r600_context*)ctx;
658 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
659 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
660 struct r600_texture *tmp = (struct r600_texture*)texture;
661 unsigned format, endian;
662 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
663 unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
664 unsigned height, depth, width;
665 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
666 enum pipe_format pipe_format = state->format;
667 struct radeon_surf_level *surflevel;
668 unsigned base_level, first_level, last_level;
669 unsigned dim, last_layer;
670 uint64_t va;
671
672 if (!view)
673 return NULL;
674
675 /* initialize base object */
676 view->base = *state;
677 view->base.texture = NULL;
678 pipe_reference(NULL, &texture->reference);
679 view->base.texture = texture;
680 view->base.reference.count = 1;
681 view->base.context = ctx;
682
683 if (state->target == PIPE_BUFFER)
684 return texture_buffer_sampler_view(rctx, view, width0, height0);
685
686 swizzle[0] = state->swizzle_r;
687 swizzle[1] = state->swizzle_g;
688 swizzle[2] = state->swizzle_b;
689 swizzle[3] = state->swizzle_a;
690
691 tile_split = tmp->surface.tile_split;
692 surflevel = tmp->surface.level;
693
694 /* Texturing with separate depth and stencil. */
695 if (tmp->is_depth && !tmp->is_flushing_texture) {
696 switch (pipe_format) {
697 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
698 pipe_format = PIPE_FORMAT_Z32_FLOAT;
699 break;
700 case PIPE_FORMAT_X8Z24_UNORM:
701 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
702 /* Z24 is always stored like this. */
703 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
704 break;
705 case PIPE_FORMAT_X24S8_UINT:
706 case PIPE_FORMAT_S8X24_UINT:
707 case PIPE_FORMAT_X32_S8X24_UINT:
708 pipe_format = PIPE_FORMAT_S8_UINT;
709 tile_split = tmp->surface.stencil_tile_split;
710 surflevel = tmp->surface.stencil_level;
711 break;
712 default:;
713 }
714 }
715
716 format = r600_translate_texformat(ctx->screen, pipe_format,
717 swizzle,
718 &word4, &yuv_format);
719 assert(format != ~0);
720 if (format == ~0) {
721 FREE(view);
722 return NULL;
723 }
724
725 endian = r600_colorformat_endian_swap(format);
726
727 base_level = 0;
728 first_level = state->u.tex.first_level;
729 last_level = state->u.tex.last_level;
730 width = width0;
731 height = height0;
732 depth = texture->depth0;
733
734 if (force_level) {
735 base_level = force_level;
736 first_level = 0;
737 last_level = 0;
738 width = u_minify(width, force_level);
739 height = u_minify(height, force_level);
740 depth = u_minify(depth, force_level);
741 }
742
743 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
744 non_disp_tiling = tmp->non_disp_tiling;
745
746 switch (surflevel[base_level].mode) {
747 case RADEON_SURF_MODE_LINEAR_ALIGNED:
748 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
749 break;
750 case RADEON_SURF_MODE_2D:
751 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
752 break;
753 case RADEON_SURF_MODE_1D:
754 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
755 break;
756 case RADEON_SURF_MODE_LINEAR:
757 default:
758 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
759 break;
760 }
761 macro_aspect = tmp->surface.mtilea;
762 bankw = tmp->surface.bankw;
763 bankh = tmp->surface.bankh;
764 tile_split = eg_tile_split(tile_split);
765 macro_aspect = eg_macro_tile_aspect(macro_aspect);
766 bankw = eg_bank_wh(bankw);
767 bankh = eg_bank_wh(bankh);
768 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
769
770 /* 128 bit formats require tile type = 1 */
771 if (rscreen->b.chip_class == CAYMAN) {
772 if (util_format_get_blocksize(pipe_format) >= 16)
773 non_disp_tiling = 1;
774 }
775 nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
776
777 if (state->target == PIPE_TEXTURE_1D_ARRAY) {
778 height = 1;
779 depth = texture->array_size;
780 } else if (state->target == PIPE_TEXTURE_2D_ARRAY) {
781 depth = texture->array_size;
782 } else if (state->target == PIPE_TEXTURE_CUBE_ARRAY)
783 depth = texture->array_size / 6;
784
785 va = tmp->resource.gpu_address;
786
787 if (state->format == PIPE_FORMAT_X24S8_UINT ||
788 state->format == PIPE_FORMAT_S8X24_UINT ||
789 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
790 state->format == PIPE_FORMAT_S8_UINT)
791 view->is_stencil_sampler = true;
792
793 view->tex_resource = &tmp->resource;
794
795 /* array type views and views into array types need to use layer offset */
796 dim = state->target;
797 if (state->target != PIPE_TEXTURE_CUBE)
798 dim = MAX2(state->target, texture->target);
799
800 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(dim, texture->nr_samples)) |
801 S_030000_PITCH((pitch / 8) - 1) |
802 S_030000_TEX_WIDTH(width - 1));
803 if (rscreen->b.chip_class == CAYMAN)
804 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
805 else
806 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
807 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
808 S_030004_TEX_DEPTH(depth - 1) |
809 S_030004_ARRAY_MODE(array_mode));
810 view->tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
811
812 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
813 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
814 if (tmp->is_depth) {
815 /* disable FMASK (0 = disabled) */
816 view->tex_resource_words[3] = 0;
817 view->skip_mip_address_reloc = true;
818 } else {
819 /* FMASK should be in MIP_ADDRESS for multisample textures */
820 view->tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
821 }
822 } else if (last_level && texture->nr_samples <= 1) {
823 view->tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
824 } else {
825 view->tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
826 }
827
828 last_layer = state->u.tex.last_layer;
829 if (state->target != texture->target && depth == 1) {
830 last_layer = state->u.tex.first_layer;
831 }
832 view->tex_resource_words[4] = (word4 |
833 S_030010_ENDIAN_SWAP(endian));
834 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
835 S_030014_LAST_ARRAY(last_layer);
836 view->tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
837
838 if (texture->nr_samples > 1) {
839 unsigned log_samples = util_logbase2(texture->nr_samples);
840 if (rscreen->b.chip_class == CAYMAN) {
841 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
842 }
843 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
844 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
845 view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
846 } else {
847 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
848 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
849 /* aniso max 16 samples */
850 view->tex_resource_words[6] |= S_030018_MAX_ANISO(4);
851 }
852
853 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
854 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
855 S_03001C_BANK_WIDTH(bankw) |
856 S_03001C_BANK_HEIGHT(bankh) |
857 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
858 S_03001C_NUM_BANKS(nbanks) |
859 S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
860 return &view->base;
861 }
862
863 static struct pipe_sampler_view *
864 evergreen_create_sampler_view(struct pipe_context *ctx,
865 struct pipe_resource *tex,
866 const struct pipe_sampler_view *state)
867 {
868 return evergreen_create_sampler_view_custom(ctx, tex, state,
869 tex->width0, tex->height0, 0);
870 }
871
872 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
873 {
874 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
875 struct pipe_clip_state *state = &rctx->clip_state.state;
876
877 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
878 radeon_emit_array(cs, (unsigned*)state, 6*4);
879 }
880
881 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
882 const struct pipe_poly_stipple *state)
883 {
884 }
885
886 static void evergreen_get_scissor_rect(struct r600_context *rctx,
887 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
888 uint32_t *tl, uint32_t *br)
889 {
890 /* EG hw workaround */
891 if (br_x == 0)
892 tl_x = 1;
893 if (br_y == 0)
894 tl_y = 1;
895
896 /* cayman hw workaround */
897 if (rctx->b.chip_class == CAYMAN) {
898 if (br_x == 1 && br_y == 1)
899 br_x = 2;
900 }
901
902 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
903 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
904 }
905
906 static void evergreen_set_scissor_states(struct pipe_context *ctx,
907 unsigned start_slot,
908 unsigned num_scissors,
909 const struct pipe_scissor_state *state)
910 {
911 struct r600_context *rctx = (struct r600_context *)ctx;
912 struct r600_scissor_state *rstate = &rctx->scissor;
913 int i;
914
915 for (i = start_slot; i < start_slot + num_scissors; i++)
916 rstate->scissor[i] = state[i - start_slot];
917 rstate->dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
918 rstate->atom.num_dw = util_bitcount(rstate->dirty_mask) * 4;
919 r600_mark_atom_dirty(rctx, &rstate->atom);
920 }
921
922 static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
923 {
924 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
925 struct r600_scissor_state *rstate = &rctx->scissor;
926 struct pipe_scissor_state *state;
927 uint32_t dirty_mask;
928 unsigned i, offset;
929 uint32_t tl, br;
930
931 dirty_mask = rstate->dirty_mask;
932 while (dirty_mask != 0) {
933 i = u_bit_scan(&dirty_mask);
934 state = &rstate->scissor[i];
935 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
936
937 offset = i * 4 * 2;
938 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
939 radeon_emit(cs, tl);
940 radeon_emit(cs, br);
941 }
942 rstate->dirty_mask = 0;
943 rstate->atom.num_dw = 0;
944 }
945
946 /**
947 * This function intializes the CB* register values for RATs. It is meant
948 * to be used for 1D aligned buffers that do not have an associated
949 * radeon_surf.
950 */
951 void evergreen_init_color_surface_rat(struct r600_context *rctx,
952 struct r600_surface *surf)
953 {
954 struct pipe_resource *pipe_buffer = surf->base.texture;
955 unsigned format = r600_translate_colorformat(rctx->b.chip_class,
956 surf->base.format);
957 unsigned endian = r600_colorformat_endian_swap(format);
958 unsigned swap = r600_translate_colorswap(surf->base.format);
959 unsigned block_size =
960 align(util_format_get_blocksize(pipe_buffer->format), 4);
961 unsigned pitch_alignment =
962 MAX2(64, rctx->screen->b.tiling_info.group_bytes / block_size);
963 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
964
965 /* XXX: This is copied from evergreen_init_color_surface(). I don't
966 * know why this is necessary.
967 */
968 if (pipe_buffer->usage == PIPE_USAGE_STAGING) {
969 endian = ENDIAN_NONE;
970 }
971
972 surf->cb_color_base = r600_resource(pipe_buffer)->gpu_address >> 8;
973
974 surf->cb_color_pitch = (pitch / 8) - 1;
975
976 surf->cb_color_slice = 0;
977
978 surf->cb_color_view = 0;
979
980 surf->cb_color_info =
981 S_028C70_ENDIAN(endian)
982 | S_028C70_FORMAT(format)
983 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
984 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
985 | S_028C70_COMP_SWAP(swap)
986 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
987 * are using NUMBER_UINT */
988 | S_028C70_RAT(1)
989 ;
990
991 surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
992
993 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
994 * elements. */
995 surf->cb_color_dim = pipe_buffer->width0;
996
997 /* Set the buffer range the GPU will have access to: */
998 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
999 0, pipe_buffer->width0);
1000
1001 surf->cb_color_fmask = surf->cb_color_base;
1002 surf->cb_color_fmask_slice = 0;
1003 }
1004
1005 void evergreen_init_color_surface(struct r600_context *rctx,
1006 struct r600_surface *surf)
1007 {
1008 struct r600_screen *rscreen = rctx->screen;
1009 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1010 unsigned level = surf->base.u.tex.level;
1011 unsigned pitch, slice;
1012 unsigned color_info, color_attrib, color_dim = 0, color_view;
1013 unsigned format, swap, ntype, endian;
1014 uint64_t offset, base_offset;
1015 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1016 const struct util_format_description *desc;
1017 int i;
1018 bool blend_clamp = 0, blend_bypass = 0;
1019
1020 offset = rtex->surface.level[level].offset;
1021 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1022 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1023 offset += rtex->surface.level[level].slice_size *
1024 surf->base.u.tex.first_layer;
1025 color_view = 0;
1026 } else
1027 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1028 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1029
1030 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1031 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1032 if (slice) {
1033 slice = slice - 1;
1034 }
1035 color_info = 0;
1036 switch (rtex->surface.level[level].mode) {
1037 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1038 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1039 non_disp_tiling = 1;
1040 break;
1041 case RADEON_SURF_MODE_1D:
1042 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1043 non_disp_tiling = rtex->non_disp_tiling;
1044 break;
1045 case RADEON_SURF_MODE_2D:
1046 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1047 non_disp_tiling = rtex->non_disp_tiling;
1048 break;
1049 case RADEON_SURF_MODE_LINEAR:
1050 default:
1051 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1052 non_disp_tiling = 1;
1053 break;
1054 }
1055 tile_split = rtex->surface.tile_split;
1056 macro_aspect = rtex->surface.mtilea;
1057 bankw = rtex->surface.bankw;
1058 bankh = rtex->surface.bankh;
1059 if (rtex->fmask.size)
1060 fmask_bankh = rtex->fmask.bank_height;
1061 else
1062 fmask_bankh = rtex->surface.bankh;
1063 tile_split = eg_tile_split(tile_split);
1064 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1065 bankw = eg_bank_wh(bankw);
1066 bankh = eg_bank_wh(bankh);
1067 fmask_bankh = eg_bank_wh(fmask_bankh);
1068
1069 /* 128 bit formats require tile type = 1 */
1070 if (rscreen->b.chip_class == CAYMAN) {
1071 if (util_format_get_blocksize(surf->base.format) >= 16)
1072 non_disp_tiling = 1;
1073 }
1074 nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
1075 desc = util_format_description(surf->base.format);
1076 for (i = 0; i < 4; i++) {
1077 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1078 break;
1079 }
1080 }
1081
1082 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1083 S_028C74_NUM_BANKS(nbanks) |
1084 S_028C74_BANK_WIDTH(bankw) |
1085 S_028C74_BANK_HEIGHT(bankh) |
1086 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1087 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1088 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1089
1090 if (rctx->b.chip_class == CAYMAN) {
1091 color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1092 UTIL_FORMAT_SWIZZLE_1);
1093
1094 if (rtex->resource.b.b.nr_samples > 1) {
1095 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1096 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1097 S_028C74_NUM_FRAGMENTS(log_samples);
1098 }
1099 }
1100
1101 ntype = V_028C70_NUMBER_UNORM;
1102 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1103 ntype = V_028C70_NUMBER_SRGB;
1104 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1105 if (desc->channel[i].normalized)
1106 ntype = V_028C70_NUMBER_SNORM;
1107 else if (desc->channel[i].pure_integer)
1108 ntype = V_028C70_NUMBER_SINT;
1109 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1110 if (desc->channel[i].normalized)
1111 ntype = V_028C70_NUMBER_UNORM;
1112 else if (desc->channel[i].pure_integer)
1113 ntype = V_028C70_NUMBER_UINT;
1114 }
1115
1116 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
1117 assert(format != ~0);
1118
1119 swap = r600_translate_colorswap(surf->base.format);
1120 assert(swap != ~0);
1121
1122 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1123 endian = ENDIAN_NONE;
1124 } else {
1125 endian = r600_colorformat_endian_swap(format);
1126 }
1127
1128 /* blend clamp should be set for all NORM/SRGB types */
1129 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1130 ntype == V_028C70_NUMBER_SRGB)
1131 blend_clamp = 1;
1132
1133 /* set blend bypass according to docs if SINT/UINT or
1134 8/24 COLOR variants */
1135 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1136 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1137 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1138 blend_clamp = 0;
1139 blend_bypass = 1;
1140 }
1141
1142 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1143
1144 color_info |= S_028C70_FORMAT(format) |
1145 S_028C70_COMP_SWAP(swap) |
1146 S_028C70_BLEND_CLAMP(blend_clamp) |
1147 S_028C70_BLEND_BYPASS(blend_bypass) |
1148 S_028C70_NUMBER_TYPE(ntype) |
1149 S_028C70_ENDIAN(endian);
1150
1151 /* EXPORT_NORM is an optimzation that can be enabled for better
1152 * performance in certain cases.
1153 * EXPORT_NORM can be enabled if:
1154 * - 11-bit or smaller UNORM/SNORM/SRGB
1155 * - 16-bit or smaller FLOAT
1156 */
1157 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1158 ((desc->channel[i].size < 12 &&
1159 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1160 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1161 (desc->channel[i].size < 17 &&
1162 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1163 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1164 surf->export_16bpc = true;
1165 }
1166
1167 if (rtex->fmask.size) {
1168 color_info |= S_028C70_COMPRESSION(1);
1169 }
1170
1171 base_offset = rtex->resource.gpu_address;
1172
1173 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1174 surf->cb_color_base = (base_offset + offset) >> 8;
1175 surf->cb_color_dim = color_dim;
1176 surf->cb_color_info = color_info;
1177 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1178 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1179 surf->cb_color_view = color_view;
1180 surf->cb_color_attrib = color_attrib;
1181 if (rtex->fmask.size) {
1182 surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8;
1183 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1184 } else {
1185 surf->cb_color_fmask = surf->cb_color_base;
1186 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1187 }
1188
1189 surf->color_initialized = true;
1190 }
1191
1192 static void evergreen_init_depth_surface(struct r600_context *rctx,
1193 struct r600_surface *surf)
1194 {
1195 struct r600_screen *rscreen = rctx->screen;
1196 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1197 unsigned level = surf->base.u.tex.level;
1198 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1199 uint64_t offset;
1200 unsigned format, array_mode;
1201 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1202
1203
1204 format = r600_translate_dbformat(surf->base.format);
1205 assert(format != ~0);
1206
1207 offset = rtex->resource.gpu_address;
1208 offset += rtex->surface.level[level].offset;
1209
1210 switch (rtex->surface.level[level].mode) {
1211 case RADEON_SURF_MODE_2D:
1212 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1213 break;
1214 case RADEON_SURF_MODE_1D:
1215 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1216 case RADEON_SURF_MODE_LINEAR:
1217 default:
1218 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1219 break;
1220 }
1221 tile_split = rtex->surface.tile_split;
1222 macro_aspect = rtex->surface.mtilea;
1223 bankw = rtex->surface.bankw;
1224 bankh = rtex->surface.bankh;
1225 tile_split = eg_tile_split(tile_split);
1226 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1227 bankw = eg_bank_wh(bankw);
1228 bankh = eg_bank_wh(bankh);
1229 nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
1230 offset >>= 8;
1231
1232 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1233 S_028040_FORMAT(format) |
1234 S_028040_TILE_SPLIT(tile_split)|
1235 S_028040_NUM_BANKS(nbanks) |
1236 S_028040_BANK_WIDTH(bankw) |
1237 S_028040_BANK_HEIGHT(bankh) |
1238 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1239 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1240 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1241 }
1242
1243 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1244
1245 surf->db_depth_base = offset;
1246 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1247 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1248 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1249 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1250 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1251 levelinfo->nblk_y / 64 - 1);
1252
1253 switch (surf->base.format) {
1254 case PIPE_FORMAT_Z24X8_UNORM:
1255 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1256 case PIPE_FORMAT_X8Z24_UNORM:
1257 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1258 surf->pa_su_poly_offset_db_fmt_cntl =
1259 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1260 break;
1261 case PIPE_FORMAT_Z32_FLOAT:
1262 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1263 surf->pa_su_poly_offset_db_fmt_cntl =
1264 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1265 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1266 break;
1267 case PIPE_FORMAT_Z16_UNORM:
1268 surf->pa_su_poly_offset_db_fmt_cntl =
1269 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1270 break;
1271 default:;
1272 }
1273
1274 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1275 uint64_t stencil_offset;
1276 unsigned stile_split = rtex->surface.stencil_tile_split;
1277
1278 stile_split = eg_tile_split(stile_split);
1279
1280 stencil_offset = rtex->surface.stencil_level[level].offset;
1281 stencil_offset += rtex->resource.gpu_address;
1282
1283 surf->db_stencil_base = stencil_offset >> 8;
1284 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1285 S_028044_TILE_SPLIT(stile_split);
1286 } else {
1287 surf->db_stencil_base = offset;
1288 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1289 * Older kernels are out of luck. */
1290 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1291 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1292 S_028044_FORMAT(V_028044_STENCIL_8);
1293 }
1294
1295 /* use htile only for first level */
1296 if (rtex->htile_buffer && !level) {
1297 uint64_t va = rtex->htile_buffer->gpu_address;
1298 surf->db_htile_data_base = va >> 8;
1299 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1300 S_028ABC_HTILE_HEIGHT(1) |
1301 S_028ABC_FULL_CACHE(1);
1302 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1303 surf->db_preload_control = 0;
1304 }
1305
1306 surf->depth_initialized = true;
1307 }
1308
1309 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1310 const struct pipe_framebuffer_state *state)
1311 {
1312 struct r600_context *rctx = (struct r600_context *)ctx;
1313 struct r600_surface *surf;
1314 struct r600_texture *rtex;
1315 uint32_t i, log_samples;
1316
1317 if (rctx->framebuffer.state.nr_cbufs) {
1318 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1319 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1320 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1321 }
1322 if (rctx->framebuffer.state.zsbuf) {
1323 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1324 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1325
1326 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1327 if (rtex->htile_buffer) {
1328 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1329 }
1330 }
1331
1332 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1333
1334 /* Colorbuffers. */
1335 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1336 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1337 util_format_is_pure_integer(state->cbufs[0]->format);
1338 rctx->framebuffer.compressed_cb_mask = 0;
1339 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1340
1341 for (i = 0; i < state->nr_cbufs; i++) {
1342 surf = (struct r600_surface*)state->cbufs[i];
1343 if (!surf)
1344 continue;
1345
1346 rtex = (struct r600_texture*)surf->base.texture;
1347
1348 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1349
1350 if (!surf->color_initialized) {
1351 evergreen_init_color_surface(rctx, surf);
1352 }
1353
1354 if (!surf->export_16bpc) {
1355 rctx->framebuffer.export_16bpc = false;
1356 }
1357
1358 if (rtex->fmask.size && rtex->cmask.size) {
1359 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1360 }
1361 }
1362
1363 /* Update alpha-test state dependencies.
1364 * Alpha-test is done on the first colorbuffer only. */
1365 if (state->nr_cbufs) {
1366 bool alphatest_bypass = false;
1367 bool export_16bpc = true;
1368
1369 surf = (struct r600_surface*)state->cbufs[0];
1370 if (surf) {
1371 alphatest_bypass = surf->alphatest_bypass;
1372 export_16bpc = surf->export_16bpc;
1373 }
1374
1375 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1376 rctx->alphatest_state.bypass = alphatest_bypass;
1377 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1378 }
1379 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1380 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1381 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1382 }
1383 }
1384
1385 /* ZS buffer. */
1386 if (state->zsbuf) {
1387 surf = (struct r600_surface*)state->zsbuf;
1388
1389 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1390
1391 if (!surf->depth_initialized) {
1392 evergreen_init_depth_surface(rctx, surf);
1393 }
1394
1395 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1396 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1397 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1398 }
1399
1400 if (rctx->db_state.rsurf != surf) {
1401 rctx->db_state.rsurf = surf;
1402 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1403 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1404 }
1405 } else if (rctx->db_state.rsurf) {
1406 rctx->db_state.rsurf = NULL;
1407 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1408 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1409 }
1410
1411 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1412 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1413 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1414 }
1415
1416 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1417 rctx->alphatest_state.bypass = false;
1418 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1419 }
1420
1421 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1422 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1423 if ((rctx->b.chip_class == CAYMAN ||
1424 rctx->b.family == CHIP_RV770) &&
1425 rctx->db_misc_state.log_samples != log_samples) {
1426 rctx->db_misc_state.log_samples = log_samples;
1427 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1428 }
1429
1430
1431 /* Calculate the CS size. */
1432 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1433
1434 /* MSAA. */
1435 if (rctx->b.chip_class == EVERGREEN)
1436 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1437 else
1438 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1439
1440 /* Colorbuffers. */
1441 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1442 if (rctx->keep_tiling_flags)
1443 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1444 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1445
1446 /* ZS buffer. */
1447 if (state->zsbuf) {
1448 rctx->framebuffer.atom.num_dw += 24;
1449 if (rctx->keep_tiling_flags)
1450 rctx->framebuffer.atom.num_dw += 2;
1451 } else if (rctx->screen->b.info.drm_minor >= 18) {
1452 rctx->framebuffer.atom.num_dw += 4;
1453 }
1454
1455 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1456
1457 r600_set_sample_locations_constant_buffer(rctx);
1458 }
1459
1460 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1461 {
1462 struct r600_context *rctx = (struct r600_context *)ctx;
1463
1464 if (rctx->ps_iter_samples == min_samples)
1465 return;
1466
1467 rctx->ps_iter_samples = min_samples;
1468 if (rctx->framebuffer.nr_samples > 1) {
1469 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1470 }
1471 }
1472
1473 /* 8xMSAA */
1474 static uint32_t sample_locs_8x[] = {
1475 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1476 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1477 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1478 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1479 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1480 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1481 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1482 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1483 };
1484 static unsigned max_dist_8x = 7;
1485
1486 static void evergreen_get_sample_position(struct pipe_context *ctx,
1487 unsigned sample_count,
1488 unsigned sample_index,
1489 float *out_value)
1490 {
1491 int offset, index;
1492 struct {
1493 int idx:4;
1494 } val;
1495 switch (sample_count) {
1496 case 1:
1497 default:
1498 out_value[0] = out_value[1] = 0.5;
1499 break;
1500 case 2:
1501 offset = 4 * (sample_index * 2);
1502 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1503 out_value[0] = (float)(val.idx + 8) / 16.0f;
1504 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1505 out_value[1] = (float)(val.idx + 8) / 16.0f;
1506 break;
1507 case 4:
1508 offset = 4 * (sample_index * 2);
1509 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1510 out_value[0] = (float)(val.idx + 8) / 16.0f;
1511 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1512 out_value[1] = (float)(val.idx + 8) / 16.0f;
1513 break;
1514 case 8:
1515 offset = 4 * (sample_index % 4 * 2);
1516 index = (sample_index / 4);
1517 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1518 out_value[0] = (float)(val.idx + 8) / 16.0f;
1519 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1520 out_value[1] = (float)(val.idx + 8) / 16.0f;
1521 break;
1522 }
1523 }
1524
1525 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1526 {
1527
1528 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1529 unsigned max_dist = 0;
1530
1531 switch (nr_samples) {
1532 default:
1533 nr_samples = 0;
1534 break;
1535 case 2:
1536 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_2x));
1537 radeon_emit_array(cs, eg_sample_locs_2x, Elements(eg_sample_locs_2x));
1538 max_dist = eg_max_dist_2x;
1539 break;
1540 case 4:
1541 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_4x));
1542 radeon_emit_array(cs, eg_sample_locs_4x, Elements(eg_sample_locs_4x));
1543 max_dist = eg_max_dist_4x;
1544 break;
1545 case 8:
1546 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1547 radeon_emit_array(cs, sample_locs_8x, Elements(sample_locs_8x));
1548 max_dist = max_dist_8x;
1549 break;
1550 }
1551
1552 if (nr_samples > 1) {
1553 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1554 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1555 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1556 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1557 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1558 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1));
1559 } else {
1560 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1561 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1562 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1563 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, 0);
1564 }
1565 }
1566
1567 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1568 {
1569 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1570 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1571 unsigned nr_cbufs = state->nr_cbufs;
1572 unsigned i, tl, br;
1573 struct r600_texture *tex = NULL;
1574 struct r600_surface *cb = NULL;
1575
1576 /* XXX support more colorbuffers once we need them */
1577 assert(nr_cbufs <= 8);
1578 if (nr_cbufs > 8)
1579 nr_cbufs = 8;
1580
1581 /* Colorbuffers. */
1582 for (i = 0; i < nr_cbufs; i++) {
1583 unsigned reloc, cmask_reloc;
1584
1585 cb = (struct r600_surface*)state->cbufs[i];
1586 if (!cb) {
1587 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1588 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1589 continue;
1590 }
1591
1592 tex = (struct r600_texture *)cb->base.texture;
1593 reloc = radeon_add_to_buffer_list(&rctx->b,
1594 &rctx->b.gfx,
1595 (struct r600_resource*)cb->base.texture,
1596 RADEON_USAGE_READWRITE,
1597 tex->surface.nsamples > 1 ?
1598 RADEON_PRIO_COLOR_BUFFER_MSAA :
1599 RADEON_PRIO_COLOR_BUFFER);
1600
1601 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1602 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1603 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1604 RADEON_PRIO_CMASK);
1605 } else {
1606 cmask_reloc = reloc;
1607 }
1608
1609 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1610 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1611 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1612 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1613 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1614 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1615 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1616 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1617 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1618 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1619 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1620 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1621 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1622 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1623
1624 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1625 radeon_emit(cs, reloc);
1626
1627 if (!rctx->keep_tiling_flags) {
1628 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1629 radeon_emit(cs, reloc);
1630 }
1631
1632 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1633 radeon_emit(cs, reloc);
1634
1635 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1636 radeon_emit(cs, cmask_reloc);
1637
1638 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1639 radeon_emit(cs, reloc);
1640 }
1641 /* set CB_COLOR1_INFO for possible dual-src blending */
1642 if (i == 1 && state->cbufs[0]) {
1643 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1644 cb->cb_color_info | tex->cb_color_info);
1645
1646 if (!rctx->keep_tiling_flags) {
1647 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1648 &rctx->b.gfx,
1649 (struct r600_resource*)state->cbufs[0]->texture,
1650 RADEON_USAGE_READWRITE,
1651 RADEON_PRIO_COLOR_BUFFER);
1652
1653 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1654 radeon_emit(cs, reloc);
1655 }
1656 i++;
1657 }
1658 if (rctx->keep_tiling_flags) {
1659 for (; i < 8 ; i++) {
1660 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1661 }
1662 for (; i < 12; i++) {
1663 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1664 }
1665 }
1666
1667 /* ZS buffer. */
1668 if (state->zsbuf) {
1669 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1670 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1671 &rctx->b.gfx,
1672 (struct r600_resource*)state->zsbuf->texture,
1673 RADEON_USAGE_READWRITE,
1674 zb->base.texture->nr_samples > 1 ?
1675 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1676 RADEON_PRIO_DEPTH_BUFFER);
1677
1678 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1679 zb->pa_su_poly_offset_db_fmt_cntl);
1680 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1681
1682 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1683 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1684 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1685 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1686 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1687 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1688 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1689 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1690 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1691
1692 if (!rctx->keep_tiling_flags) {
1693 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
1694 radeon_emit(cs, reloc);
1695 }
1696
1697 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1698 radeon_emit(cs, reloc);
1699
1700 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1701 radeon_emit(cs, reloc);
1702
1703 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1704 radeon_emit(cs, reloc);
1705
1706 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1707 radeon_emit(cs, reloc);
1708 } else if (rctx->screen->b.info.drm_minor >= 18) {
1709 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1710 * Older kernels are out of luck. */
1711 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1712 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1713 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1714 }
1715
1716 /* Framebuffer dimensions. */
1717 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1718
1719 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1720 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1721 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1722
1723 if (rctx->b.chip_class == EVERGREEN) {
1724 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1725 } else {
1726 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1727 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples, rctx->ps_iter_samples, 0);
1728 }
1729 }
1730
1731 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1732 {
1733 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1734 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1735 float offset_units = state->offset_units;
1736 float offset_scale = state->offset_scale;
1737
1738 switch (state->zs_format) {
1739 case PIPE_FORMAT_Z24X8_UNORM:
1740 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1741 case PIPE_FORMAT_X8Z24_UNORM:
1742 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1743 offset_units *= 2.0f;
1744 break;
1745 case PIPE_FORMAT_Z16_UNORM:
1746 offset_units *= 4.0f;
1747 break;
1748 default:;
1749 }
1750
1751 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1752 radeon_emit(cs, fui(offset_scale));
1753 radeon_emit(cs, fui(offset_units));
1754 radeon_emit(cs, fui(offset_scale));
1755 radeon_emit(cs, fui(offset_units));
1756 }
1757
1758 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1759 {
1760 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1761 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1762 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1763 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1764
1765 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1766 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1767 /* This must match the used export instructions exactly.
1768 * Other values may lead to undefined behavior and hangs.
1769 */
1770 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
1771 }
1772
1773 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1774 {
1775 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1776 struct r600_db_state *a = (struct r600_db_state*)atom;
1777
1778 if (a->rsurf && a->rsurf->db_htile_surface) {
1779 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1780 unsigned reloc_idx;
1781
1782 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1783 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1784 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
1785 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1786 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1787 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1788 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1789 cs->buf[cs->cdw++] = reloc_idx;
1790 } else {
1791 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
1792 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
1793 }
1794 }
1795
1796 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1797 {
1798 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1799 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1800 unsigned db_render_control = 0;
1801 unsigned db_count_control = 0;
1802 unsigned db_render_override =
1803 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1804 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
1805 /* There is a hang with HTILE if stencil is used and
1806 * fast stencil is enabled. */
1807 S_02800C_FAST_STENCIL_DISABLE(1);
1808
1809 if (a->occlusion_query_enabled) {
1810 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1811 if (rctx->b.chip_class == CAYMAN) {
1812 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1813 }
1814 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1815 }
1816 /* FIXME we should be able to use hyperz even if we are not writing to
1817 * zbuffer but somehow this trigger GPU lockup. See :
1818 *
1819 * https://bugs.freedesktop.org/show_bug.cgi?id=60848
1820 *
1821 * Disable hyperz for now if not writing to zbuffer.
1822 */
1823 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface && rctx->zwritemask) {
1824 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1825 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
1826 /* This is to fix a lockup when hyperz and alpha test are enabled at
1827 * the same time somehow GPU get confuse on which order to pick for
1828 * z test
1829 */
1830 if (rctx->alphatest_state.sx_alpha_test_control) {
1831 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
1832 }
1833 } else {
1834 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
1835 }
1836 if (a->flush_depthstencil_through_cb) {
1837 assert(a->copy_depth || a->copy_stencil);
1838
1839 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1840 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1841 S_028000_COPY_CENTROID(1) |
1842 S_028000_COPY_SAMPLE(a->copy_sample);
1843 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1844 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1845 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1846 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1847 }
1848 if (a->htile_clear) {
1849 /* FIXME we might want to disable cliprect here */
1850 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
1851 }
1852
1853 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1854 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1855 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1856 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1857 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1858 }
1859
1860 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1861 struct r600_vertexbuf_state *state,
1862 unsigned resource_offset,
1863 unsigned pkt_flags)
1864 {
1865 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1866 uint32_t dirty_mask = state->dirty_mask;
1867
1868 while (dirty_mask) {
1869 struct pipe_vertex_buffer *vb;
1870 struct r600_resource *rbuffer;
1871 uint64_t va;
1872 unsigned buffer_index = u_bit_scan(&dirty_mask);
1873
1874 vb = &state->vb[buffer_index];
1875 rbuffer = (struct r600_resource*)vb->buffer;
1876 assert(rbuffer);
1877
1878 va = rbuffer->gpu_address + vb->buffer_offset;
1879
1880 /* fetch resources start at index 992 */
1881 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1882 radeon_emit(cs, (resource_offset + buffer_index) * 8);
1883 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1884 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1885 radeon_emit(cs, /* RESOURCEi_WORD2 */
1886 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1887 S_030008_STRIDE(vb->stride) |
1888 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1889 radeon_emit(cs, /* RESOURCEi_WORD3 */
1890 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1891 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1892 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1893 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1894 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1895 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1896 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1897 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1898
1899 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1900 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1901 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1902 }
1903 state->dirty_mask = 0;
1904 }
1905
1906 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1907 {
1908 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
1909 }
1910
1911 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1912 {
1913 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
1914 RADEON_CP_PACKET3_COMPUTE_MODE);
1915 }
1916
1917 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1918 struct r600_constbuf_state *state,
1919 unsigned buffer_id_base,
1920 unsigned reg_alu_constbuf_size,
1921 unsigned reg_alu_const_cache,
1922 unsigned pkt_flags)
1923 {
1924 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1925 uint32_t dirty_mask = state->dirty_mask;
1926
1927 while (dirty_mask) {
1928 struct pipe_constant_buffer *cb;
1929 struct r600_resource *rbuffer;
1930 uint64_t va;
1931 unsigned buffer_index = ffs(dirty_mask) - 1;
1932 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1933
1934 cb = &state->cb[buffer_index];
1935 rbuffer = (struct r600_resource*)cb->buffer;
1936 assert(rbuffer);
1937
1938 va = rbuffer->gpu_address + cb->buffer_offset;
1939
1940 if (!gs_ring_buffer) {
1941 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
1942 ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags);
1943 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
1944 pkt_flags);
1945 }
1946
1947 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1948 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1949 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1950
1951 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1952 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
1953 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1954 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1955 radeon_emit(cs, /* RESOURCEi_WORD2 */
1956 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1957 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
1958 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
1959 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
1960 radeon_emit(cs, /* RESOURCEi_WORD3 */
1961 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
1962 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1963 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1964 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1965 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1966 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1967 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1968 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1969 radeon_emit(cs, /* RESOURCEi_WORD7 */
1970 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
1971
1972 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1973 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1974 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1975
1976 dirty_mask &= ~(1 << buffer_index);
1977 }
1978 state->dirty_mask = 0;
1979 }
1980
1981 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
1982 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1983 {
1984 if (rctx->vs_shader->current->shader.vs_as_ls) {
1985 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1986 EG_FETCH_CONSTANTS_OFFSET_LS,
1987 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
1988 R_028F40_ALU_CONST_CACHE_LS_0,
1989 0 /* PKT3 flags */);
1990 } else {
1991 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1992 EG_FETCH_CONSTANTS_OFFSET_VS,
1993 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1994 R_028980_ALU_CONST_CACHE_VS_0,
1995 0 /* PKT3 flags */);
1996 }
1997 }
1998
1999 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2000 {
2001 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
2002 EG_FETCH_CONSTANTS_OFFSET_GS,
2003 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2004 R_0289C0_ALU_CONST_CACHE_GS_0,
2005 0 /* PKT3 flags */);
2006 }
2007
2008 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2009 {
2010 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
2011 EG_FETCH_CONSTANTS_OFFSET_PS,
2012 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2013 R_028940_ALU_CONST_CACHE_PS_0,
2014 0 /* PKT3 flags */);
2015 }
2016
2017 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2018 {
2019 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
2020 EG_FETCH_CONSTANTS_OFFSET_CS,
2021 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2022 R_028F40_ALU_CONST_CACHE_LS_0,
2023 RADEON_CP_PACKET3_COMPUTE_MODE);
2024 }
2025
2026 /* tes constants can be emitted to VS or ES - which are common */
2027 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2028 {
2029 if (!rctx->tes_shader)
2030 return;
2031 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2032 EG_FETCH_CONSTANTS_OFFSET_VS,
2033 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2034 R_028980_ALU_CONST_CACHE_VS_0,
2035 0);
2036 }
2037
2038 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2039 {
2040 if (!rctx->tes_shader)
2041 return;
2042 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2043 EG_FETCH_CONSTANTS_OFFSET_HS,
2044 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
2045 R_028F00_ALU_CONST_CACHE_HS_0,
2046 0);
2047 }
2048
2049 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2050 struct r600_samplerview_state *state,
2051 unsigned resource_id_base, unsigned pkt_flags)
2052 {
2053 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2054 uint32_t dirty_mask = state->dirty_mask;
2055
2056 while (dirty_mask) {
2057 struct r600_pipe_sampler_view *rview;
2058 unsigned resource_index = u_bit_scan(&dirty_mask);
2059 unsigned reloc;
2060
2061 rview = state->views[resource_index];
2062 assert(rview);
2063
2064 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2065 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2066 radeon_emit_array(cs, rview->tex_resource_words, 8);
2067
2068 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2069 RADEON_USAGE_READ,
2070 r600_get_sampler_view_priority(rview->tex_resource));
2071 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2072 radeon_emit(cs, reloc);
2073
2074 if (!rview->skip_mip_address_reloc) {
2075 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2076 radeon_emit(cs, reloc);
2077 }
2078 }
2079 state->dirty_mask = 0;
2080 }
2081
2082 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2083 {
2084 if (rctx->vs_shader->current->shader.vs_as_ls) {
2085 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2086 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2087 } else {
2088 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2089 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2090 }
2091 }
2092
2093 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2094 {
2095 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2096 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2097 }
2098
2099 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2100 {
2101 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2102 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2103 }
2104
2105 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2106 {
2107 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2108 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2109 }
2110
2111 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2112 {
2113 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2114 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2115 }
2116
2117 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2118 {
2119 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2120 EG_FETCH_CONSTANTS_OFFSET_CS + 2, RADEON_CP_PACKET3_COMPUTE_MODE);
2121 }
2122
2123 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2124 struct r600_textures_info *texinfo,
2125 unsigned resource_id_base,
2126 unsigned border_index_reg,
2127 unsigned pkt_flags)
2128 {
2129 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2130 uint32_t dirty_mask = texinfo->states.dirty_mask;
2131
2132 while (dirty_mask) {
2133 struct r600_pipe_sampler_state *rstate;
2134 unsigned i = u_bit_scan(&dirty_mask);
2135
2136 rstate = texinfo->states.states[i];
2137 assert(rstate);
2138
2139 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2140 radeon_emit(cs, (resource_id_base + i) * 3);
2141 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2142
2143 if (rstate->border_color_use) {
2144 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2145 radeon_emit(cs, i);
2146 radeon_emit_array(cs, rstate->border_color.ui, 4);
2147 }
2148 }
2149 texinfo->states.dirty_mask = 0;
2150 }
2151
2152 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2153 {
2154 if (rctx->vs_shader->current->shader.vs_as_ls) {
2155 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2156 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2157 } else {
2158 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2159 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2160 }
2161 }
2162
2163 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2164 {
2165 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2166 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2167 }
2168
2169 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2170 {
2171 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2172 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2173 }
2174
2175 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2176 {
2177 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2178 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2179 }
2180
2181 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2182 {
2183 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2184 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2185 }
2186
2187 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2188 {
2189 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2190 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2191 RADEON_CP_PACKET3_COMPUTE_MODE);
2192 }
2193
2194 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2195 {
2196 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2197 uint8_t mask = s->sample_mask;
2198
2199 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2200 mask | (mask << 8) | (mask << 16) | (mask << 24));
2201 }
2202
2203 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2204 {
2205 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2206 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2207 uint16_t mask = s->sample_mask;
2208
2209 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2210 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2211 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2212 }
2213
2214 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2215 {
2216 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2217 struct r600_cso_state *state = (struct r600_cso_state*)a;
2218 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2219
2220 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2221 (shader->buffer->gpu_address + shader->offset) >> 8);
2222 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2223 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2224 RADEON_USAGE_READ,
2225 RADEON_PRIO_INTERNAL_SHADER));
2226 }
2227
2228 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2229 {
2230 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2231 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2232
2233 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2234
2235 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2236 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2237 primid = 1;
2238 }
2239
2240 if (state->geom_enable) {
2241 uint32_t cut_val;
2242
2243 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2244 cut_val = V_028A40_GS_CUT_128;
2245 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2246 cut_val = V_028A40_GS_CUT_256;
2247 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2248 cut_val = V_028A40_GS_CUT_512;
2249 else
2250 cut_val = V_028A40_GS_CUT_1024;
2251
2252 v = S_028B54_GS_EN(1) |
2253 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2254 if (!rctx->tes_shader)
2255 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2256
2257 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2258 S_028A40_CUT_MODE(cut_val);
2259
2260 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2261 primid = 1;
2262 }
2263
2264 if (rctx->tes_shader) {
2265 uint32_t type, partitioning, topology;
2266 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2267 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2268 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2269 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2270 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2271 switch (tes_prim_mode) {
2272 case PIPE_PRIM_LINES:
2273 type = V_028B6C_TESS_ISOLINE;
2274 break;
2275 case PIPE_PRIM_TRIANGLES:
2276 type = V_028B6C_TESS_TRIANGLE;
2277 break;
2278 case PIPE_PRIM_QUADS:
2279 type = V_028B6C_TESS_QUAD;
2280 break;
2281 default:
2282 assert(0);
2283 return;
2284 }
2285
2286 switch (tes_spacing) {
2287 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2288 partitioning = V_028B6C_PART_FRAC_ODD;
2289 break;
2290 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2291 partitioning = V_028B6C_PART_FRAC_EVEN;
2292 break;
2293 case PIPE_TESS_SPACING_EQUAL:
2294 partitioning = V_028B6C_PART_INTEGER;
2295 break;
2296 default:
2297 assert(0);
2298 return;
2299 }
2300
2301 if (tes_point_mode)
2302 topology = V_028B6C_OUTPUT_POINT;
2303 else if (tes_prim_mode == PIPE_PRIM_LINES)
2304 topology = V_028B6C_OUTPUT_LINE;
2305 else if (tes_vertex_order_cw)
2306 /* XXX follow radeonsi and invert */
2307 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2308 else
2309 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2310
2311 tf_param = S_028B6C_TYPE(type) |
2312 S_028B6C_PARTITIONING(partitioning) |
2313 S_028B6C_TOPOLOGY(topology);
2314 }
2315
2316 if (rctx->tes_shader) {
2317 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2318 S_028B54_HS_EN(1);
2319 if (!state->geom_enable)
2320 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2321 else
2322 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2323 }
2324
2325 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2326 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2327 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2328 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2329 }
2330
2331 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2332 {
2333 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2334 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2335 struct r600_resource *rbuffer;
2336
2337 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2338 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2339 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2340
2341 if (state->enable) {
2342 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2343 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2344 rbuffer->gpu_address >> 8);
2345 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2346 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2347 RADEON_USAGE_READWRITE,
2348 RADEON_PRIO_RINGS_STREAMOUT));
2349 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2350 state->esgs_ring.buffer_size >> 8);
2351
2352 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2353 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2354 rbuffer->gpu_address >> 8);
2355 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2356 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2357 RADEON_USAGE_READWRITE,
2358 RADEON_PRIO_RINGS_STREAMOUT));
2359 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2360 state->gsvs_ring.buffer_size >> 8);
2361 } else {
2362 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2363 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2364 }
2365
2366 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2367 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2368 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2369 }
2370
2371 void cayman_init_common_regs(struct r600_command_buffer *cb,
2372 enum chip_class ctx_chip_class,
2373 enum radeon_family ctx_family,
2374 int ctx_drm_minor)
2375 {
2376 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2377 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2378 /* always set the temp clauses */
2379 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2380
2381 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2382 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2383 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2384
2385 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2386
2387 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2388 r600_store_value(cb, 0);
2389 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2390
2391 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2392 }
2393
2394 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2395 {
2396 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2397 int tmp, i;
2398
2399 r600_init_command_buffer(cb, 336);
2400
2401 /* This must be first. */
2402 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2403 r600_store_value(cb, 0x80000000);
2404 r600_store_value(cb, 0x80000000);
2405
2406 /* We're setting config registers here. */
2407 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2408 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2409
2410 cayman_init_common_regs(cb, rctx->b.chip_class,
2411 rctx->b.family, rctx->screen->b.info.drm_minor);
2412
2413 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2414 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2415
2416 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2417 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2418 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2419 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2420 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2421 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2422 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2423
2424 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2425 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2426 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2427 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2428 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2429
2430 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2431 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2432 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2433 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2434 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2435 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2436 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2437 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2438 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2439 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2440 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2441 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2442 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2443 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2444
2445 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2446
2447 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2448 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2449 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2450
2451 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2452
2453 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2454 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2455 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2456
2457 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2458 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2459 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2460
2461 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2462
2463 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2464 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2465 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2466
2467 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2468
2469 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2470
2471 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2472
2473 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2474 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2475 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2476 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2477
2478 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2479 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2480
2481 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2482 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2483 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2484 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2485 }
2486
2487 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2488 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2489
2490 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2491 r600_store_value(cb, fui(1.0)); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2492 r600_store_value(cb, fui(1.0)); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2493 r600_store_value(cb, fui(1.0)); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2494 r600_store_value(cb, fui(1.0)); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2495
2496 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2497 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2498 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2499
2500 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2501 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2502 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2503
2504 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2505 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2506 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2507 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2508 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2509 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2510
2511 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2512
2513 /* to avoid GPU doing any preloading of constant from random address */
2514 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2515 for (i = 0; i < 16; i++)
2516 r600_store_value(cb, 0);
2517
2518 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2519 for (i = 0; i < 16; i++)
2520 r600_store_value(cb, 0);
2521
2522 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2523 for (i = 0; i < 16; i++)
2524 r600_store_value(cb, 0);
2525
2526 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2527 for (i = 0; i < 16; i++)
2528 r600_store_value(cb, 0);
2529
2530 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2531 for (i = 0; i < 16; i++)
2532 r600_store_value(cb, 0);
2533
2534 if (rctx->screen->b.has_streamout) {
2535 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2536 }
2537
2538 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2539 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2540 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2541 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2542 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2543 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2544
2545 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2546 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2547 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2548 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2549 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2550 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2551 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2552 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2553 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2554 }
2555
2556 void evergreen_init_common_regs(struct r600_command_buffer *cb,
2557 enum chip_class ctx_chip_class,
2558 enum radeon_family ctx_family,
2559 int ctx_drm_minor)
2560 {
2561 int ps_prio;
2562 int vs_prio;
2563 int gs_prio;
2564 int es_prio;
2565
2566 int hs_prio;
2567 int cs_prio;
2568 int ls_prio;
2569
2570 int num_ps_gprs;
2571 int num_vs_gprs;
2572 int num_gs_gprs;
2573 int num_es_gprs;
2574 int num_hs_gprs;
2575 int num_ls_gprs;
2576 int num_temp_gprs;
2577
2578 unsigned tmp;
2579
2580 ps_prio = 0;
2581 vs_prio = 1;
2582 gs_prio = 2;
2583 es_prio = 3;
2584 hs_prio = 0;
2585 ls_prio = 0;
2586 cs_prio = 0;
2587
2588 num_ps_gprs = 93;
2589 num_vs_gprs = 46;
2590 num_temp_gprs = 4;
2591 num_gs_gprs = 31;
2592 num_es_gprs = 31;
2593 num_hs_gprs = 23;
2594 num_ls_gprs = 23;
2595
2596 tmp = 0;
2597 switch (ctx_family) {
2598 case CHIP_CEDAR:
2599 case CHIP_PALM:
2600 case CHIP_SUMO:
2601 case CHIP_SUMO2:
2602 case CHIP_CAICOS:
2603 break;
2604 default:
2605 tmp |= S_008C00_VC_ENABLE(1);
2606 break;
2607 }
2608 tmp |= S_008C00_EXPORT_SRC_C(1);
2609 tmp |= S_008C00_CS_PRIO(cs_prio);
2610 tmp |= S_008C00_LS_PRIO(ls_prio);
2611 tmp |= S_008C00_HS_PRIO(hs_prio);
2612 tmp |= S_008C00_PS_PRIO(ps_prio);
2613 tmp |= S_008C00_VS_PRIO(vs_prio);
2614 tmp |= S_008C00_GS_PRIO(gs_prio);
2615 tmp |= S_008C00_ES_PRIO(es_prio);
2616
2617 /* enable dynamic GPR resource management */
2618 if (ctx_drm_minor >= 7) {
2619 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2620 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2621 /* always set temp clauses */
2622 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2623 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2624 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2625 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2626 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2627 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2628 S_028838_PS_GPRS(0x1e) |
2629 S_028838_VS_GPRS(0x1e) |
2630 S_028838_GS_GPRS(0x1e) |
2631 S_028838_ES_GPRS(0x1e) |
2632 S_028838_HS_GPRS(0x1e) |
2633 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2634 } else {
2635 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2636 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2637
2638 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2639 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2640 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2641 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2642
2643 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2644 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2645 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2646
2647 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2648 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2649 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2650 }
2651
2652 /* The cs checker requires this register to be set. */
2653 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2654
2655 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2656 r600_store_value(cb, 0);
2657 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2658
2659 return;
2660 }
2661
2662 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2663 {
2664 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2665 int num_ps_threads;
2666 int num_vs_threads;
2667 int num_gs_threads;
2668 int num_es_threads;
2669 int num_hs_threads;
2670 int num_ls_threads;
2671
2672 int num_ps_stack_entries;
2673 int num_vs_stack_entries;
2674 int num_gs_stack_entries;
2675 int num_es_stack_entries;
2676 int num_hs_stack_entries;
2677 int num_ls_stack_entries;
2678 enum radeon_family family;
2679 unsigned tmp, i;
2680
2681 if (rctx->b.chip_class == CAYMAN) {
2682 cayman_init_atom_start_cs(rctx);
2683 return;
2684 }
2685
2686 r600_init_command_buffer(cb, 342);
2687
2688 /* This must be first. */
2689 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2690 r600_store_value(cb, 0x80000000);
2691 r600_store_value(cb, 0x80000000);
2692
2693 /* We're setting config registers here. */
2694 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2695 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2696
2697 evergreen_init_common_regs(cb, rctx->b.chip_class,
2698 rctx->b.family, rctx->screen->b.info.drm_minor);
2699
2700 family = rctx->b.family;
2701 switch (family) {
2702 case CHIP_CEDAR:
2703 default:
2704 num_ps_threads = 96;
2705 num_vs_threads = 16;
2706 num_gs_threads = 16;
2707 num_es_threads = 16;
2708 num_hs_threads = 16;
2709 num_ls_threads = 16;
2710 num_ps_stack_entries = 42;
2711 num_vs_stack_entries = 42;
2712 num_gs_stack_entries = 42;
2713 num_es_stack_entries = 42;
2714 num_hs_stack_entries = 42;
2715 num_ls_stack_entries = 42;
2716 break;
2717 case CHIP_REDWOOD:
2718 num_ps_threads = 128;
2719 num_vs_threads = 20;
2720 num_gs_threads = 20;
2721 num_es_threads = 20;
2722 num_hs_threads = 20;
2723 num_ls_threads = 20;
2724 num_ps_stack_entries = 42;
2725 num_vs_stack_entries = 42;
2726 num_gs_stack_entries = 42;
2727 num_es_stack_entries = 42;
2728 num_hs_stack_entries = 42;
2729 num_ls_stack_entries = 42;
2730 break;
2731 case CHIP_JUNIPER:
2732 num_ps_threads = 128;
2733 num_vs_threads = 20;
2734 num_gs_threads = 20;
2735 num_es_threads = 20;
2736 num_hs_threads = 20;
2737 num_ls_threads = 20;
2738 num_ps_stack_entries = 85;
2739 num_vs_stack_entries = 85;
2740 num_gs_stack_entries = 85;
2741 num_es_stack_entries = 85;
2742 num_hs_stack_entries = 85;
2743 num_ls_stack_entries = 85;
2744 break;
2745 case CHIP_CYPRESS:
2746 case CHIP_HEMLOCK:
2747 num_ps_threads = 128;
2748 num_vs_threads = 20;
2749 num_gs_threads = 20;
2750 num_es_threads = 20;
2751 num_hs_threads = 20;
2752 num_ls_threads = 20;
2753 num_ps_stack_entries = 85;
2754 num_vs_stack_entries = 85;
2755 num_gs_stack_entries = 85;
2756 num_es_stack_entries = 85;
2757 num_hs_stack_entries = 85;
2758 num_ls_stack_entries = 85;
2759 break;
2760 case CHIP_PALM:
2761 num_ps_threads = 96;
2762 num_vs_threads = 16;
2763 num_gs_threads = 16;
2764 num_es_threads = 16;
2765 num_hs_threads = 16;
2766 num_ls_threads = 16;
2767 num_ps_stack_entries = 42;
2768 num_vs_stack_entries = 42;
2769 num_gs_stack_entries = 42;
2770 num_es_stack_entries = 42;
2771 num_hs_stack_entries = 42;
2772 num_ls_stack_entries = 42;
2773 break;
2774 case CHIP_SUMO:
2775 num_ps_threads = 96;
2776 num_vs_threads = 25;
2777 num_gs_threads = 25;
2778 num_es_threads = 25;
2779 num_hs_threads = 25;
2780 num_ls_threads = 25;
2781 num_ps_stack_entries = 42;
2782 num_vs_stack_entries = 42;
2783 num_gs_stack_entries = 42;
2784 num_es_stack_entries = 42;
2785 num_hs_stack_entries = 42;
2786 num_ls_stack_entries = 42;
2787 break;
2788 case CHIP_SUMO2:
2789 num_ps_threads = 96;
2790 num_vs_threads = 25;
2791 num_gs_threads = 25;
2792 num_es_threads = 25;
2793 num_hs_threads = 25;
2794 num_ls_threads = 25;
2795 num_ps_stack_entries = 85;
2796 num_vs_stack_entries = 85;
2797 num_gs_stack_entries = 85;
2798 num_es_stack_entries = 85;
2799 num_hs_stack_entries = 85;
2800 num_ls_stack_entries = 85;
2801 break;
2802 case CHIP_BARTS:
2803 num_ps_threads = 128;
2804 num_vs_threads = 20;
2805 num_gs_threads = 20;
2806 num_es_threads = 20;
2807 num_hs_threads = 20;
2808 num_ls_threads = 20;
2809 num_ps_stack_entries = 85;
2810 num_vs_stack_entries = 85;
2811 num_gs_stack_entries = 85;
2812 num_es_stack_entries = 85;
2813 num_hs_stack_entries = 85;
2814 num_ls_stack_entries = 85;
2815 break;
2816 case CHIP_TURKS:
2817 num_ps_threads = 128;
2818 num_vs_threads = 20;
2819 num_gs_threads = 20;
2820 num_es_threads = 20;
2821 num_hs_threads = 20;
2822 num_ls_threads = 20;
2823 num_ps_stack_entries = 42;
2824 num_vs_stack_entries = 42;
2825 num_gs_stack_entries = 42;
2826 num_es_stack_entries = 42;
2827 num_hs_stack_entries = 42;
2828 num_ls_stack_entries = 42;
2829 break;
2830 case CHIP_CAICOS:
2831 num_ps_threads = 128;
2832 num_vs_threads = 10;
2833 num_gs_threads = 10;
2834 num_es_threads = 10;
2835 num_hs_threads = 10;
2836 num_ls_threads = 10;
2837 num_ps_stack_entries = 42;
2838 num_vs_stack_entries = 42;
2839 num_gs_stack_entries = 42;
2840 num_es_stack_entries = 42;
2841 num_hs_stack_entries = 42;
2842 num_ls_stack_entries = 42;
2843 break;
2844 }
2845
2846 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2847 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2848 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2849 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2850
2851 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2852 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2853
2854 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2855 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2856 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2857
2858 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2859 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2860 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2861
2862 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2863 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2864 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2865
2866 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2867 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2868 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2869
2870 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2871 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2872
2873 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2874 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2875
2876 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2877 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2878 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2879 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2880 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2881 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2882 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2883
2884 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2885 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2886 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2887 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2888 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2889
2890 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2891 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2892 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2893 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2894 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2895 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2896 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2897 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2898 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2899 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2900 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2901 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2902 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2903 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2904
2905 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2906 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2907 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2908
2909 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2910
2911 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2912
2913 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2914 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2915 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2916
2917 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2918
2919 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2920
2921 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2922 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2923 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2924
2925 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2926 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2927 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2928 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2929 }
2930
2931 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2932 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2933
2934 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2935 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2936 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2937 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2938
2939 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2940 r600_store_value(cb, fui(1.0)); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2941 r600_store_value(cb, fui(1.0)); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2942 r600_store_value(cb, fui(1.0)); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2943 r600_store_value(cb, fui(1.0)); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2944
2945 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2946 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2947 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2948
2949 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2950 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2951 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2952
2953 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2954 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2955 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2956 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2957 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2958 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2959 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2960
2961 /* to avoid GPU doing any preloading of constant from random address */
2962 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2963 for (i = 0; i < 16; i++)
2964 r600_store_value(cb, 0);
2965
2966 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2967 for (i = 0; i < 16; i++)
2968 r600_store_value(cb, 0);
2969
2970 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2971 for (i = 0; i < 16; i++)
2972 r600_store_value(cb, 0);
2973
2974 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2975 for (i = 0; i < 16; i++)
2976 r600_store_value(cb, 0);
2977
2978 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2979 for (i = 0; i < 16; i++)
2980 r600_store_value(cb, 0);
2981
2982 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2983
2984 if (rctx->screen->b.has_streamout) {
2985 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2986 }
2987
2988 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2989 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2990 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2991 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2992 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2993 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2994
2995 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2996 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2997 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2998
2999 if (rctx->b.family == CHIP_CAICOS) {
3000 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
3001 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3002 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3003 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
3004 } else {
3005 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
3006 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3007 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3008 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
3009 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
3010 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
3011 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
3012 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
3013 }
3014
3015 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3016 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3017 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
3018 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
3019 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
3020 }
3021
3022 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3023 {
3024 struct r600_context *rctx = (struct r600_context *)ctx;
3025 struct r600_command_buffer *cb = &shader->command_buffer;
3026 struct r600_shader *rshader = &shader->shader;
3027 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
3028 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
3029 int ninterp = 0;
3030 boolean have_perspective = FALSE, have_linear = FALSE;
3031 static const unsigned spi_baryc_enable_bit[6] = {
3032 S_0286E0_PERSP_SAMPLE_ENA(1),
3033 S_0286E0_PERSP_CENTER_ENA(1),
3034 S_0286E0_PERSP_CENTROID_ENA(1),
3035 S_0286E0_LINEAR_SAMPLE_ENA(1),
3036 S_0286E0_LINEAR_CENTER_ENA(1),
3037 S_0286E0_LINEAR_CENTROID_ENA(1)
3038 };
3039 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
3040 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
3041 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3042 uint32_t spi_ps_input_cntl[32];
3043
3044 if (!cb->buf) {
3045 r600_init_command_buffer(cb, 64);
3046 } else {
3047 cb->num_dw = 0;
3048 }
3049
3050 for (i = 0; i < rshader->ninput; i++) {
3051 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3052 POSITION goes via GPRs from the SC so isn't counted */
3053 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3054 pos_index = i;
3055 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
3056 if (face_index == -1)
3057 face_index = i;
3058 }
3059 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3060 if (face_index == -1)
3061 face_index = i; /* lives in same register, same enable bit */
3062 }
3063 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
3064 fixed_pt_position_index = i;
3065 }
3066 else {
3067 ninterp++;
3068 int k = eg_get_interpolator_index(
3069 rshader->input[i].interpolate,
3070 rshader->input[i].interpolate_location);
3071 if (k >= 0) {
3072 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3073 have_perspective |= k < 3;
3074 have_linear |= !(k < 3);
3075 }
3076 }
3077
3078 sid = rshader->input[i].spi_sid;
3079
3080 if (sid) {
3081 tmp = S_028644_SEMANTIC(sid);
3082
3083 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3084 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3085 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3086 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3087 tmp |= S_028644_FLAT_SHADE(1);
3088 }
3089
3090 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3091 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3092 tmp |= S_028644_PT_SPRITE_TEX(1);
3093 }
3094
3095 spi_ps_input_cntl[num++] = tmp;
3096 }
3097 }
3098
3099 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3100 r600_store_array(cb, num, spi_ps_input_cntl);
3101
3102 for (i = 0; i < rshader->noutput; i++) {
3103 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3104 z_export = 1;
3105 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3106 stencil_export = 1;
3107 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3108 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3109 mask_export = 1;
3110 }
3111 if (rshader->uses_kill)
3112 db_shader_control |= S_02880C_KILL_ENABLE(1);
3113
3114 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3115 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3116 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3117
3118 switch (rshader->ps_conservative_z) {
3119 default: /* fall through */
3120 case TGSI_FS_DEPTH_LAYOUT_ANY:
3121 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3122 break;
3123 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3124 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3125 break;
3126 case TGSI_FS_DEPTH_LAYOUT_LESS:
3127 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3128 break;
3129 }
3130
3131 exports_ps = 0;
3132 for (i = 0; i < rshader->noutput; i++) {
3133 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3134 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3135 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3136 exports_ps |= 1;
3137 }
3138
3139 num_cout = rshader->nr_ps_color_exports;
3140
3141 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3142 if (!exports_ps) {
3143 /* always at least export 1 component per pixel */
3144 exports_ps = 2;
3145 }
3146 shader->nr_ps_color_outputs = num_cout;
3147 if (ninterp == 0) {
3148 ninterp = 1;
3149 have_perspective = TRUE;
3150 }
3151 if (!spi_baryc_cntl)
3152 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3153
3154 if (!have_perspective && !have_linear)
3155 have_perspective = TRUE;
3156
3157 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3158 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3159 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3160 spi_input_z = 0;
3161 if (pos_index != -1) {
3162 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3163 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3164 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3165 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3166 }
3167
3168 spi_ps_in_control_1 = 0;
3169 if (face_index != -1) {
3170 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3171 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3172 }
3173 if (fixed_pt_position_index != -1) {
3174 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3175 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3176 }
3177
3178 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3179 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3180 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3181
3182 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3183 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3184 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3185
3186 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3187 r600_store_value(cb, shader->bo->gpu_address >> 8);
3188 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3189 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3190 S_028844_PRIME_CACHE_ON_DRAW(1) |
3191 S_028844_STACK_SIZE(rshader->bc.nstack));
3192 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3193
3194 shader->db_shader_control = db_shader_control;
3195 shader->ps_depth_export = z_export | stencil_export | mask_export;
3196
3197 shader->sprite_coord_enable = sprite_coord_enable;
3198 if (rctx->rasterizer)
3199 shader->flatshade = rctx->rasterizer->flatshade;
3200 }
3201
3202 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3203 {
3204 struct r600_command_buffer *cb = &shader->command_buffer;
3205 struct r600_shader *rshader = &shader->shader;
3206
3207 r600_init_command_buffer(cb, 32);
3208
3209 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3210 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3211 S_028890_STACK_SIZE(rshader->bc.nstack));
3212 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3213 shader->bo->gpu_address >> 8);
3214 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3215 }
3216
3217 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3218 {
3219 struct r600_context *rctx = (struct r600_context *)ctx;
3220 struct r600_command_buffer *cb = &shader->command_buffer;
3221 struct r600_shader *rshader = &shader->shader;
3222 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3223 unsigned gsvs_itemsizes[4] = {
3224 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3225 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3226 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3227 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3228 };
3229
3230 r600_init_command_buffer(cb, 64);
3231
3232 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3233
3234 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
3235
3236 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3237 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3238 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3239 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3240
3241 if (rctx->screen->b.info.drm_minor >= 35) {
3242 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3243 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3244 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3245 }
3246 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3247 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3248 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3249 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3250 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3251
3252 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3253 (rshader->ring_item_sizes[0]) >> 2);
3254
3255 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3256 gsvs_itemsizes[0] +
3257 gsvs_itemsizes[1] +
3258 gsvs_itemsizes[2] +
3259 gsvs_itemsizes[3]);
3260
3261 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3262 r600_store_value(cb, gsvs_itemsizes[0]);
3263 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3264 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3265
3266 /* FIXME calculate these values somehow ??? */
3267 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3268 r600_store_value(cb, 0x80); /* GS_PER_ES */
3269 r600_store_value(cb, 0x100); /* ES_PER_GS */
3270 r600_store_value(cb, 0x2); /* GS_PER_VS */
3271
3272 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3273 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3274 S_028878_STACK_SIZE(rshader->bc.nstack));
3275 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3276 shader->bo->gpu_address >> 8);
3277 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3278 }
3279
3280
3281 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3282 {
3283 struct r600_command_buffer *cb = &shader->command_buffer;
3284 struct r600_shader *rshader = &shader->shader;
3285 unsigned spi_vs_out_id[10] = {};
3286 unsigned i, tmp, nparams = 0;
3287
3288 for (i = 0; i < rshader->noutput; i++) {
3289 if (rshader->output[i].spi_sid) {
3290 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3291 spi_vs_out_id[nparams / 4] |= tmp;
3292 nparams++;
3293 }
3294 }
3295
3296 r600_init_command_buffer(cb, 32);
3297
3298 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3299 for (i = 0; i < 10; i++) {
3300 r600_store_value(cb, spi_vs_out_id[i]);
3301 }
3302
3303 /* Certain attributes (position, psize, etc.) don't count as params.
3304 * VS is required to export at least one param and r600_shader_from_tgsi()
3305 * takes care of adding a dummy export.
3306 */
3307 if (nparams < 1)
3308 nparams = 1;
3309
3310 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3311 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3312 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3313 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3314 S_028860_STACK_SIZE(rshader->bc.nstack));
3315 if (rshader->vs_position_window_space) {
3316 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3317 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3318 } else {
3319 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3320 S_028818_VTX_W0_FMT(1) |
3321 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3322 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3323 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3324
3325 }
3326 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3327 shader->bo->gpu_address >> 8);
3328 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3329
3330 shader->pa_cl_vs_out_cntl =
3331 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3332 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3333 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3334 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3335 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3336 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3337 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3338 }
3339
3340 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3341 {
3342 struct r600_command_buffer *cb = &shader->command_buffer;
3343 struct r600_shader *rshader = &shader->shader;
3344
3345 r600_init_command_buffer(cb, 32);
3346 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3347 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3348 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3349 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3350 shader->bo->gpu_address >> 8);
3351 }
3352
3353 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3354 {
3355 struct r600_command_buffer *cb = &shader->command_buffer;
3356 struct r600_shader *rshader = &shader->shader;
3357
3358 r600_init_command_buffer(cb, 32);
3359 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3360 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3361 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3362 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3363 shader->bo->gpu_address >> 8);
3364 }
3365 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3366 {
3367 struct pipe_blend_state blend;
3368
3369 memset(&blend, 0, sizeof(blend));
3370 blend.independent_blend_enable = true;
3371 blend.rt[0].colormask = 0xf;
3372 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3373 }
3374
3375 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3376 {
3377 struct pipe_blend_state blend;
3378 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3379 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3380
3381 memset(&blend, 0, sizeof(blend));
3382 blend.independent_blend_enable = true;
3383 blend.rt[0].colormask = 0xf;
3384 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3385 }
3386
3387 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3388 {
3389 struct pipe_blend_state blend;
3390 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3391
3392 memset(&blend, 0, sizeof(blend));
3393 blend.independent_blend_enable = true;
3394 blend.rt[0].colormask = 0xf;
3395 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3396 }
3397
3398 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3399 {
3400 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3401
3402 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3403 }
3404
3405 void evergreen_update_db_shader_control(struct r600_context * rctx)
3406 {
3407 bool dual_export;
3408 unsigned db_shader_control;
3409
3410 if (!rctx->ps_shader) {
3411 return;
3412 }
3413
3414 dual_export = rctx->framebuffer.export_16bpc &&
3415 !rctx->ps_shader->current->ps_depth_export;
3416
3417 db_shader_control = rctx->ps_shader->current->db_shader_control |
3418 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3419 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3420 V_02880C_EXPORT_DB_FULL) |
3421 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3422
3423 /* When alpha test is enabled we can't trust the hw to make the proper
3424 * decision on the order in which ztest should be run related to fragment
3425 * shader execution.
3426 *
3427 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3428 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3429 * execution and thus after alpha test so if discarded by the alpha test
3430 * the z value is not written.
3431 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3432 * get a hang unless you flush the DB in between. For now just use
3433 * LATE_Z.
3434 */
3435 if (rctx->alphatest_state.sx_alpha_test_control) {
3436 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3437 } else {
3438 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3439 }
3440
3441 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3442 rctx->db_misc_state.db_shader_control = db_shader_control;
3443 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3444 }
3445 }
3446
3447 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3448 struct pipe_resource *dst,
3449 unsigned dst_level,
3450 unsigned dst_x,
3451 unsigned dst_y,
3452 unsigned dst_z,
3453 struct pipe_resource *src,
3454 unsigned src_level,
3455 unsigned src_x,
3456 unsigned src_y,
3457 unsigned src_z,
3458 unsigned copy_height,
3459 unsigned pitch,
3460 unsigned bpp)
3461 {
3462 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3463 struct r600_texture *rsrc = (struct r600_texture*)src;
3464 struct r600_texture *rdst = (struct r600_texture*)dst;
3465 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3466 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3467 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3468 uint64_t base, addr;
3469
3470 dst_mode = rdst->surface.level[dst_level].mode;
3471 src_mode = rsrc->surface.level[src_level].mode;
3472 /* downcast linear aligned to linear to simplify test */
3473 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3474 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3475 assert(dst_mode != src_mode);
3476
3477 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3478 if (util_format_has_depth(util_format_description(src->format)))
3479 non_disp_tiling = 1;
3480
3481 y = 0;
3482 sub_cmd = EG_DMA_COPY_TILED;
3483 lbpp = util_logbase2(bpp);
3484 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3485 nbanks = eg_num_banks(rctx->screen->b.tiling_info.num_banks);
3486
3487 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
3488 /* T2L */
3489 array_mode = evergreen_array_mode(src_mode);
3490 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
3491 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3492 /* linear height must be the same as the slice tile max height, it's ok even
3493 * if the linear destination/source have smaller heigh as the size of the
3494 * dma packet will be using the copy_height which is always smaller or equal
3495 * to the linear height
3496 */
3497 height = rsrc->surface.level[src_level].npix_y;
3498 detile = 1;
3499 x = src_x;
3500 y = src_y;
3501 z = src_z;
3502 base = rsrc->surface.level[src_level].offset;
3503 addr = rdst->surface.level[dst_level].offset;
3504 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3505 addr += dst_y * pitch + dst_x * bpp;
3506 bank_h = eg_bank_wh(rsrc->surface.bankh);
3507 bank_w = eg_bank_wh(rsrc->surface.bankw);
3508 mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
3509 tile_split = eg_tile_split(rsrc->surface.tile_split);
3510 base += rsrc->resource.gpu_address;
3511 addr += rdst->resource.gpu_address;
3512 } else {
3513 /* L2T */
3514 array_mode = evergreen_array_mode(dst_mode);
3515 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
3516 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3517 /* linear height must be the same as the slice tile max height, it's ok even
3518 * if the linear destination/source have smaller heigh as the size of the
3519 * dma packet will be using the copy_height which is always smaller or equal
3520 * to the linear height
3521 */
3522 height = rdst->surface.level[dst_level].npix_y;
3523 detile = 0;
3524 x = dst_x;
3525 y = dst_y;
3526 z = dst_z;
3527 base = rdst->surface.level[dst_level].offset;
3528 addr = rsrc->surface.level[src_level].offset;
3529 addr += rsrc->surface.level[src_level].slice_size * src_z;
3530 addr += src_y * pitch + src_x * bpp;
3531 bank_h = eg_bank_wh(rdst->surface.bankh);
3532 bank_w = eg_bank_wh(rdst->surface.bankw);
3533 mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
3534 tile_split = eg_tile_split(rdst->surface.tile_split);
3535 base += rdst->resource.gpu_address;
3536 addr += rsrc->resource.gpu_address;
3537 }
3538
3539 size = (copy_height * pitch) / 4;
3540 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3541 r600_need_dma_space(&rctx->b, ncopy * 9);
3542
3543 for (i = 0; i < ncopy; i++) {
3544 cheight = copy_height;
3545 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3546 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3547 }
3548 size = (cheight * pitch) / 4;
3549 /* emit reloc before writing cs so that cs is always in consistent state */
3550 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3551 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3552 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3553 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3554 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
3555 cs->buf[cs->cdw++] = base >> 8;
3556 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3557 (lbpp << 24) | (bank_h << 21) |
3558 (bank_w << 18) | (mt_aspect << 16);
3559 cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
3560 cs->buf[cs->cdw++] = (slice_tile_max << 0);
3561 cs->buf[cs->cdw++] = (x << 0) | (z << 18);
3562 cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28);
3563 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3564 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3565 copy_height -= cheight;
3566 addr += cheight * pitch;
3567 y += cheight;
3568 }
3569 }
3570
3571 static void evergreen_dma_copy(struct pipe_context *ctx,
3572 struct pipe_resource *dst,
3573 unsigned dst_level,
3574 unsigned dstx, unsigned dsty, unsigned dstz,
3575 struct pipe_resource *src,
3576 unsigned src_level,
3577 const struct pipe_box *src_box)
3578 {
3579 struct r600_context *rctx = (struct r600_context *)ctx;
3580 struct r600_texture *rsrc = (struct r600_texture*)src;
3581 struct r600_texture *rdst = (struct r600_texture*)dst;
3582 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3583 unsigned src_w, dst_w;
3584 unsigned src_x, src_y;
3585 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3586
3587 if (rctx->b.dma.cs == NULL) {
3588 goto fallback;
3589 }
3590
3591 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3592 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3593 return;
3594 }
3595
3596 if (src->format != dst->format || src_box->depth > 1 ||
3597 (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level)) {
3598 goto fallback;
3599 }
3600
3601 if (rsrc->dirty_level_mask & (1 << src_level)) {
3602 ctx->flush_resource(ctx, src);
3603 }
3604
3605 src_x = util_format_get_nblocksx(src->format, src_box->x);
3606 dst_x = util_format_get_nblocksx(src->format, dst_x);
3607 src_y = util_format_get_nblocksy(src->format, src_box->y);
3608 dst_y = util_format_get_nblocksy(src->format, dst_y);
3609
3610 bpp = rdst->surface.bpe;
3611 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3612 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3613 src_w = rsrc->surface.level[src_level].npix_x;
3614 dst_w = rdst->surface.level[dst_level].npix_x;
3615 copy_height = src_box->height / rsrc->surface.blk_h;
3616
3617 dst_mode = rdst->surface.level[dst_level].mode;
3618 src_mode = rsrc->surface.level[src_level].mode;
3619 /* downcast linear aligned to linear to simplify test */
3620 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3621 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3622
3623 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3624 /* FIXME evergreen can do partial blit */
3625 goto fallback;
3626 }
3627 /* the x test here are currently useless (because we don't support partial blit)
3628 * but keep them around so we don't forget about those
3629 */
3630 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3631 goto fallback;
3632 }
3633
3634 /* 128 bpp surfaces require non_disp_tiling for both
3635 * tiled and linear buffers on cayman. However, async
3636 * DMA only supports it on the tiled side. As such
3637 * the tile order is backwards after a L2T/T2L packet.
3638 */
3639 if ((rctx->b.chip_class == CAYMAN) &&
3640 (src_mode != dst_mode) &&
3641 (util_format_get_blocksize(src->format) >= 16)) {
3642 goto fallback;
3643 }
3644
3645 if (src_mode == dst_mode) {
3646 uint64_t dst_offset, src_offset;
3647 /* simple dma blit would do NOTE code here assume :
3648 * src_box.x/y == 0
3649 * dst_x/y == 0
3650 * dst_pitch == src_pitch
3651 */
3652 src_offset= rsrc->surface.level[src_level].offset;
3653 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3654 src_offset += src_y * src_pitch + src_x * bpp;
3655 dst_offset = rdst->surface.level[dst_level].offset;
3656 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3657 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3658 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3659 src_box->height * src_pitch);
3660 } else {
3661 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3662 src, src_level, src_x, src_y, src_box->z,
3663 copy_height, dst_pitch, bpp);
3664 }
3665 return;
3666
3667 fallback:
3668 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3669 src, src_level, src_box);
3670 }
3671
3672 static void evergreen_set_tess_state(struct pipe_context *ctx,
3673 const float default_outer_level[4],
3674 const float default_inner_level[2])
3675 {
3676 struct r600_context *rctx = (struct r600_context *)ctx;
3677
3678 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3679 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3680 }
3681
3682 void evergreen_init_state_functions(struct r600_context *rctx)
3683 {
3684 unsigned id = 1;
3685 unsigned i;
3686 /* !!!
3687 * To avoid GPU lockup registers must be emited in a specific order
3688 * (no kidding ...). The order below is important and have been
3689 * partialy infered from analyzing fglrx command stream.
3690 *
3691 * Don't reorder atom without carefully checking the effect (GPU lockup
3692 * or piglit regression).
3693 * !!!
3694 */
3695
3696 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
3697 /* shader const */
3698 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
3699 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
3700 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
3701 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
3702 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
3703 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
3704 /* shader program */
3705 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
3706 /* sampler */
3707 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
3708 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
3709 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
3710 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
3711 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
3712 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
3713 /* resources */
3714 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
3715 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
3716 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
3717 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
3718 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
3719 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
3720 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
3721 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
3722
3723 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3724
3725 if (rctx->b.chip_class == EVERGREEN) {
3726 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
3727 } else {
3728 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
3729 }
3730 rctx->sample_mask.sample_mask = ~0;
3731
3732 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3733 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3734 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3735 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
3736 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3737 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
3738 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
3739 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
3740 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3741 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
3742 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3743 r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 0);
3744 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 0);
3745 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3746 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
3747 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3748 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3749 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3750 for (i = 0; i < EG_NUM_HW_STAGES; i++)
3751 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3752 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 12);
3753 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
3754
3755 rctx->b.b.create_blend_state = evergreen_create_blend_state;
3756 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
3757 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
3758 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
3759 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
3760 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
3761 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
3762 rctx->b.b.set_min_samples = evergreen_set_min_samples;
3763 rctx->b.b.set_scissor_states = evergreen_set_scissor_states;
3764 rctx->b.b.set_tess_state = evergreen_set_tess_state;
3765 if (rctx->b.chip_class == EVERGREEN)
3766 rctx->b.b.get_sample_position = evergreen_get_sample_position;
3767 else
3768 rctx->b.b.get_sample_position = cayman_get_sample_position;
3769 rctx->b.dma_copy = evergreen_dma_copy;
3770
3771 evergreen_init_compute_state_functions(rctx);
3772 }