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r600g: some -Wsign-compare fixes
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600_query.h"
26 #include "evergreend.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_memory.h"
31 #include "util/u_framebuffer.h"
32 #include "util/u_dual_blend.h"
33 #include "evergreen_compute.h"
34 #include "util/u_math.h"
35
36 static inline unsigned evergreen_array_mode(unsigned mode)
37 {
38 switch (mode) {
39 default:
40 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
41 break;
42 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
43 break;
44 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
45 }
46 }
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(struct r600_texture *rtex,
174 unsigned view_target, unsigned nr_samples)
175 {
176 unsigned res_target = rtex->resource.b.b.target;
177
178 if (view_target == PIPE_TEXTURE_CUBE ||
179 view_target == PIPE_TEXTURE_CUBE_ARRAY)
180 res_target = view_target;
181 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
182 else if (res_target == PIPE_TEXTURE_CUBE ||
183 res_target == PIPE_TEXTURE_CUBE_ARRAY)
184 res_target = PIPE_TEXTURE_2D_ARRAY;
185
186 switch (res_target) {
187 default:
188 case PIPE_TEXTURE_1D:
189 return V_030000_SQ_TEX_DIM_1D;
190 case PIPE_TEXTURE_1D_ARRAY:
191 return V_030000_SQ_TEX_DIM_1D_ARRAY;
192 case PIPE_TEXTURE_2D:
193 case PIPE_TEXTURE_RECT:
194 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
195 V_030000_SQ_TEX_DIM_2D;
196 case PIPE_TEXTURE_2D_ARRAY:
197 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
198 V_030000_SQ_TEX_DIM_2D_ARRAY;
199 case PIPE_TEXTURE_3D:
200 return V_030000_SQ_TEX_DIM_3D;
201 case PIPE_TEXTURE_CUBE:
202 case PIPE_TEXTURE_CUBE_ARRAY:
203 return V_030000_SQ_TEX_DIM_CUBEMAP;
204 }
205 }
206
207 static uint32_t r600_translate_dbformat(enum pipe_format format)
208 {
209 switch (format) {
210 case PIPE_FORMAT_Z16_UNORM:
211 return V_028040_Z_16;
212 case PIPE_FORMAT_Z24X8_UNORM:
213 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
214 case PIPE_FORMAT_X8Z24_UNORM:
215 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
216 return V_028040_Z_24;
217 case PIPE_FORMAT_Z32_FLOAT:
218 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
219 return V_028040_Z_32_FLOAT;
220 default:
221 return ~0U;
222 }
223 }
224
225 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
226 {
227 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
228 FALSE) != ~0U;
229 }
230
231 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
232 {
233 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
234 r600_translate_colorswap(format, FALSE) != ~0U;
235 }
236
237 static bool r600_is_zs_format_supported(enum pipe_format format)
238 {
239 return r600_translate_dbformat(format) != ~0U;
240 }
241
242 boolean evergreen_is_format_supported(struct pipe_screen *screen,
243 enum pipe_format format,
244 enum pipe_texture_target target,
245 unsigned sample_count,
246 unsigned usage)
247 {
248 struct r600_screen *rscreen = (struct r600_screen*)screen;
249 unsigned retval = 0;
250
251 if (target >= PIPE_MAX_TEXTURE_TYPES) {
252 R600_ERR("r600: unsupported texture type %d\n", target);
253 return FALSE;
254 }
255
256 if (sample_count > 1) {
257 if (!rscreen->has_msaa)
258 return FALSE;
259
260 switch (sample_count) {
261 case 2:
262 case 4:
263 case 8:
264 break;
265 default:
266 return FALSE;
267 }
268 }
269
270 if (usage & PIPE_BIND_SAMPLER_VIEW) {
271 if (target == PIPE_BUFFER) {
272 if (r600_is_vertex_format_supported(format))
273 retval |= PIPE_BIND_SAMPLER_VIEW;
274 } else {
275 if (r600_is_sampler_format_supported(screen, format))
276 retval |= PIPE_BIND_SAMPLER_VIEW;
277 }
278 }
279
280 if ((usage & (PIPE_BIND_RENDER_TARGET |
281 PIPE_BIND_DISPLAY_TARGET |
282 PIPE_BIND_SCANOUT |
283 PIPE_BIND_SHARED |
284 PIPE_BIND_BLENDABLE)) &&
285 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
286 retval |= usage &
287 (PIPE_BIND_RENDER_TARGET |
288 PIPE_BIND_DISPLAY_TARGET |
289 PIPE_BIND_SCANOUT |
290 PIPE_BIND_SHARED);
291 if (!util_format_is_pure_integer(format) &&
292 !util_format_is_depth_or_stencil(format))
293 retval |= usage & PIPE_BIND_BLENDABLE;
294 }
295
296 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
297 r600_is_zs_format_supported(format)) {
298 retval |= PIPE_BIND_DEPTH_STENCIL;
299 }
300
301 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
302 r600_is_vertex_format_supported(format)) {
303 retval |= PIPE_BIND_VERTEX_BUFFER;
304 }
305
306 if ((usage & PIPE_BIND_LINEAR) &&
307 !util_format_is_compressed(format) &&
308 !(usage & PIPE_BIND_DEPTH_STENCIL))
309 retval |= PIPE_BIND_LINEAR;
310
311 return retval == usage;
312 }
313
314 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
315 const struct pipe_blend_state *state, int mode)
316 {
317 uint32_t color_control = 0, target_mask = 0;
318 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
319
320 if (!blend) {
321 return NULL;
322 }
323
324 r600_init_command_buffer(&blend->buffer, 20);
325 r600_init_command_buffer(&blend->buffer_no_blend, 20);
326
327 if (state->logicop_enable) {
328 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
329 } else {
330 color_control |= (0xcc << 16);
331 }
332 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
333 if (state->independent_blend_enable) {
334 for (int i = 0; i < 8; i++) {
335 target_mask |= (state->rt[i].colormask << (4 * i));
336 }
337 } else {
338 for (int i = 0; i < 8; i++) {
339 target_mask |= (state->rt[0].colormask << (4 * i));
340 }
341 }
342
343 /* only have dual source on MRT0 */
344 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
345 blend->cb_target_mask = target_mask;
346 blend->alpha_to_one = state->alpha_to_one;
347
348 if (target_mask)
349 color_control |= S_028808_MODE(mode);
350 else
351 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
352
353
354 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
355 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
356 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
357 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
358 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
359 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
360 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
361 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
362
363 /* Copy over the dwords set so far into buffer_no_blend.
364 * Only the CB_BLENDi_CONTROL registers must be set after this. */
365 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
366 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
367
368 for (int i = 0; i < 8; i++) {
369 /* state->rt entries > 0 only written if independent blending */
370 const int j = state->independent_blend_enable ? i : 0;
371
372 unsigned eqRGB = state->rt[j].rgb_func;
373 unsigned srcRGB = state->rt[j].rgb_src_factor;
374 unsigned dstRGB = state->rt[j].rgb_dst_factor;
375 unsigned eqA = state->rt[j].alpha_func;
376 unsigned srcA = state->rt[j].alpha_src_factor;
377 unsigned dstA = state->rt[j].alpha_dst_factor;
378 uint32_t bc = 0;
379
380 r600_store_value(&blend->buffer_no_blend, 0);
381
382 if (!state->rt[j].blend_enable) {
383 r600_store_value(&blend->buffer, 0);
384 continue;
385 }
386
387 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
388 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
389 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
390 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
391
392 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
393 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
394 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
395 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
396 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
397 }
398 r600_store_value(&blend->buffer, bc);
399 }
400 return blend;
401 }
402
403 static void *evergreen_create_blend_state(struct pipe_context *ctx,
404 const struct pipe_blend_state *state)
405 {
406
407 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
408 }
409
410 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
411 const struct pipe_depth_stencil_alpha_state *state)
412 {
413 unsigned db_depth_control, alpha_test_control, alpha_ref;
414 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
415
416 if (!dsa) {
417 return NULL;
418 }
419
420 r600_init_command_buffer(&dsa->buffer, 3);
421
422 dsa->valuemask[0] = state->stencil[0].valuemask;
423 dsa->valuemask[1] = state->stencil[1].valuemask;
424 dsa->writemask[0] = state->stencil[0].writemask;
425 dsa->writemask[1] = state->stencil[1].writemask;
426 dsa->zwritemask = state->depth.writemask;
427
428 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
429 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
430 S_028800_ZFUNC(state->depth.func);
431
432 /* stencil */
433 if (state->stencil[0].enabled) {
434 db_depth_control |= S_028800_STENCIL_ENABLE(1);
435 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
436 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
437 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
438 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
439
440 if (state->stencil[1].enabled) {
441 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
442 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
443 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
444 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
445 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
446 }
447 }
448
449 /* alpha */
450 alpha_test_control = 0;
451 alpha_ref = 0;
452 if (state->alpha.enabled) {
453 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
454 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
455 alpha_ref = fui(state->alpha.ref_value);
456 }
457 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
458 dsa->alpha_ref = alpha_ref;
459
460 /* misc */
461 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
462 return dsa;
463 }
464
465 static void *evergreen_create_rs_state(struct pipe_context *ctx,
466 const struct pipe_rasterizer_state *state)
467 {
468 struct r600_context *rctx = (struct r600_context *)ctx;
469 unsigned tmp, spi_interp;
470 float psize_min, psize_max;
471 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
472
473 if (!rs) {
474 return NULL;
475 }
476
477 r600_init_command_buffer(&rs->buffer, 30);
478
479 rs->scissor_enable = state->scissor;
480 rs->clip_halfz = state->clip_halfz;
481 rs->flatshade = state->flatshade;
482 rs->sprite_coord_enable = state->sprite_coord_enable;
483 rs->rasterizer_discard = state->rasterizer_discard;
484 rs->two_side = state->light_twoside;
485 rs->clip_plane_enable = state->clip_plane_enable;
486 rs->pa_sc_line_stipple = state->line_stipple_enable ?
487 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
488 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
489 rs->pa_cl_clip_cntl =
490 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
491 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
492 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
493 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
494 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
495 rs->multisample_enable = state->multisample;
496
497 /* offset */
498 rs->offset_units = state->offset_units;
499 rs->offset_scale = state->offset_scale * 16.0f;
500 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
501 rs->offset_units_unscaled = state->offset_units_unscaled;
502
503 if (state->point_size_per_vertex) {
504 psize_min = util_get_min_point_size(state);
505 psize_max = 8192;
506 } else {
507 /* Force the point size to be as if the vertex output was disabled. */
508 psize_min = state->point_size;
509 psize_max = state->point_size;
510 }
511
512 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
513 if (state->sprite_coord_enable) {
514 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
515 S_0286D4_PNT_SPRITE_OVRD_X(2) |
516 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
517 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
518 S_0286D4_PNT_SPRITE_OVRD_W(1);
519 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
520 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
521 }
522 }
523
524 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
525 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
526 tmp = r600_pack_float_12p4(state->point_size/2);
527 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
528 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
529 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
530 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
531 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
532 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
533 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
534
535 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
536 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
537 S_028A48_MSAA_ENABLE(state->multisample) |
538 S_028A48_VPORT_SCISSOR_ENABLE(1) |
539 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
540
541 if (rctx->b.chip_class == CAYMAN) {
542 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
543 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
544 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
545 } else {
546 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
547 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
548 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
549 }
550
551 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
552 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
553 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
554 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
555 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
556 S_028814_FACE(!state->front_ccw) |
557 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
558 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
559 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
560 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
561 state->fill_back != PIPE_POLYGON_MODE_FILL) |
562 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
563 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
564 return rs;
565 }
566
567 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
568 const struct pipe_sampler_state *state)
569 {
570 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
571 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
572 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
573 : state->max_anisotropy;
574 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
575 float max_lod = state->max_lod;
576
577 if (!ss) {
578 return NULL;
579 }
580
581 /* If the min_mip_filter is NONE, then the texture has no mipmapping and
582 * MIP_FILTER will also be set to NONE. However, if more then one LOD is
583 * configured, then the texture lookup seems to fail for some specific texture
584 * formats. Forcing the number of LODs to one in this case fixes it. */
585 if (state->min_mip_filter == PIPE_TEX_MIPFILTER_NONE)
586 max_lod = state->min_lod;
587
588 ss->border_color_use = sampler_state_needs_border_color(state);
589
590 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
591 ss->tex_sampler_words[0] =
592 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
593 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
594 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
595 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
596 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
597 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
598 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
599 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
600 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
601 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
602 ss->tex_sampler_words[1] =
603 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
604 S_03C004_MAX_LOD(S_FIXED(CLAMP(max_lod, 0, 15), 8));
605 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
606 ss->tex_sampler_words[2] =
607 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
608 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
609 S_03C008_TYPE(1);
610
611 if (ss->border_color_use) {
612 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
613 }
614 return ss;
615 }
616
617 struct eg_buf_res_params {
618 enum pipe_format pipe_format;
619 unsigned offset;
620 unsigned size;
621 unsigned char swizzle[4];
622 bool uncached;
623 bool force_swizzle;
624 bool size_in_bytes;
625 };
626
627 static void evergreen_fill_buffer_resource_words(struct r600_context *rctx,
628 struct pipe_resource *buffer,
629 struct eg_buf_res_params *params,
630 bool *skip_mip_address_reloc,
631 unsigned tex_resource_words[8])
632 {
633 struct r600_texture *tmp = (struct r600_texture*)buffer;
634 uint64_t va;
635 int stride = util_format_get_blocksize(params->pipe_format);
636 unsigned format, num_format, format_comp, endian;
637 unsigned swizzle_res;
638 const struct util_format_description *desc;
639
640 r600_vertex_data_type(params->pipe_format,
641 &format, &num_format, &format_comp,
642 &endian);
643
644 desc = util_format_description(params->pipe_format);
645
646 if (params->force_swizzle)
647 swizzle_res = r600_get_swizzle_combined(params->swizzle, NULL, TRUE);
648 else
649 swizzle_res = r600_get_swizzle_combined(desc->swizzle, params->swizzle, TRUE);
650
651 va = tmp->resource.gpu_address + params->offset;
652 *skip_mip_address_reloc = true;
653 tex_resource_words[0] = va;
654 tex_resource_words[1] = params->size - 1;
655 tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
656 S_030008_STRIDE(stride) |
657 S_030008_DATA_FORMAT(format) |
658 S_030008_NUM_FORMAT_ALL(num_format) |
659 S_030008_FORMAT_COMP_ALL(format_comp) |
660 S_030008_ENDIAN_SWAP(endian);
661 tex_resource_words[3] = swizzle_res | S_03000C_UNCACHED(params->uncached);
662 /*
663 * dword 4 is for number of elements, for use with resinfo,
664 * albeit the amd gpu shader analyser
665 * uses a const buffer to store the element sizes for buffer txq
666 */
667 tex_resource_words[4] = params->size_in_bytes ? params->size : (params->size / stride);
668
669 tex_resource_words[5] = tex_resource_words[6] = 0;
670 tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
671 }
672
673 static struct pipe_sampler_view *
674 texture_buffer_sampler_view(struct r600_context *rctx,
675 struct r600_pipe_sampler_view *view,
676 unsigned width0, unsigned height0)
677 {
678 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
679 struct eg_buf_res_params params;
680
681 memset(&params, 0, sizeof(params));
682
683 params.pipe_format = view->base.format;
684 params.offset = view->base.u.buf.offset;
685 params.size = view->base.u.buf.size;
686 params.swizzle[0] = view->base.swizzle_r;
687 params.swizzle[1] = view->base.swizzle_g;
688 params.swizzle[2] = view->base.swizzle_b;
689 params.swizzle[3] = view->base.swizzle_a;
690
691 evergreen_fill_buffer_resource_words(rctx, view->base.texture,
692 &params, &view->skip_mip_address_reloc,
693 view->tex_resource_words);
694 view->tex_resource = &tmp->resource;
695
696 if (tmp->resource.gpu_address)
697 LIST_ADDTAIL(&view->list, &rctx->texture_buffers);
698 return &view->base;
699 }
700
701 struct eg_tex_res_params {
702 enum pipe_format pipe_format;
703 int force_level;
704 unsigned width0;
705 unsigned height0;
706 unsigned first_level;
707 unsigned last_level;
708 unsigned first_layer;
709 unsigned last_layer;
710 unsigned target;
711 unsigned char swizzle[4];
712 };
713
714 static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
715 struct pipe_resource *texture,
716 struct eg_tex_res_params *params,
717 bool *skip_mip_address_reloc,
718 unsigned tex_resource_words[8])
719 {
720 struct r600_screen *rscreen = (struct r600_screen*)rctx->b.b.screen;
721 struct r600_texture *tmp = (struct r600_texture*)texture;
722 unsigned format, endian;
723 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
724 unsigned char array_mode = 0, non_disp_tiling = 0;
725 unsigned height, depth, width;
726 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
727 struct legacy_surf_level *surflevel;
728 unsigned base_level, first_level, last_level;
729 unsigned dim, last_layer;
730 uint64_t va;
731 bool do_endian_swap = FALSE;
732
733 tile_split = tmp->surface.u.legacy.tile_split;
734 surflevel = tmp->surface.u.legacy.level;
735
736 /* Texturing with separate depth and stencil. */
737 if (tmp->db_compatible) {
738 switch (params->pipe_format) {
739 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
740 params->pipe_format = PIPE_FORMAT_Z32_FLOAT;
741 break;
742 case PIPE_FORMAT_X8Z24_UNORM:
743 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
744 /* Z24 is always stored like this for DB
745 * compatibility.
746 */
747 params->pipe_format = PIPE_FORMAT_Z24X8_UNORM;
748 break;
749 case PIPE_FORMAT_X24S8_UINT:
750 case PIPE_FORMAT_S8X24_UINT:
751 case PIPE_FORMAT_X32_S8X24_UINT:
752 params->pipe_format = PIPE_FORMAT_S8_UINT;
753 tile_split = tmp->surface.u.legacy.stencil_tile_split;
754 surflevel = tmp->surface.u.legacy.stencil_level;
755 break;
756 default:;
757 }
758 }
759
760 if (R600_BIG_ENDIAN)
761 do_endian_swap = !tmp->db_compatible;
762
763 format = r600_translate_texformat(rctx->b.b.screen, params->pipe_format,
764 params->swizzle,
765 &word4, &yuv_format, do_endian_swap);
766 assert(format != ~0);
767 if (format == ~0) {
768 return -1;
769 }
770
771 endian = r600_colorformat_endian_swap(format, do_endian_swap);
772
773 base_level = 0;
774 first_level = params->first_level;
775 last_level = params->last_level;
776 width = params->width0;
777 height = params->height0;
778 depth = texture->depth0;
779
780 if (params->force_level) {
781 base_level = params->force_level;
782 first_level = 0;
783 last_level = 0;
784 width = u_minify(width, params->force_level);
785 height = u_minify(height, params->force_level);
786 depth = u_minify(depth, params->force_level);
787 }
788
789 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(params->pipe_format);
790 non_disp_tiling = tmp->non_disp_tiling;
791
792 switch (surflevel[base_level].mode) {
793 default:
794 case RADEON_SURF_MODE_LINEAR_ALIGNED:
795 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
796 break;
797 case RADEON_SURF_MODE_2D:
798 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
799 break;
800 case RADEON_SURF_MODE_1D:
801 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
802 break;
803 }
804 macro_aspect = tmp->surface.u.legacy.mtilea;
805 bankw = tmp->surface.u.legacy.bankw;
806 bankh = tmp->surface.u.legacy.bankh;
807 tile_split = eg_tile_split(tile_split);
808 macro_aspect = eg_macro_tile_aspect(macro_aspect);
809 bankw = eg_bank_wh(bankw);
810 bankh = eg_bank_wh(bankh);
811 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
812
813 /* 128 bit formats require tile type = 1 */
814 if (rscreen->b.chip_class == CAYMAN) {
815 if (util_format_get_blocksize(params->pipe_format) >= 16)
816 non_disp_tiling = 1;
817 }
818 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
819
820
821 va = tmp->resource.gpu_address;
822
823 /* array type views and views into array types need to use layer offset */
824 dim = r600_tex_dim(tmp, params->target, texture->nr_samples);
825
826 if (dim == V_030000_SQ_TEX_DIM_1D_ARRAY) {
827 height = 1;
828 depth = texture->array_size;
829 } else if (dim == V_030000_SQ_TEX_DIM_2D_ARRAY ||
830 dim == V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA) {
831 depth = texture->array_size;
832 } else if (dim == V_030000_SQ_TEX_DIM_CUBEMAP)
833 depth = texture->array_size / 6;
834
835 tex_resource_words[0] = (S_030000_DIM(dim) |
836 S_030000_PITCH((pitch / 8) - 1) |
837 S_030000_TEX_WIDTH(width - 1));
838 if (rscreen->b.chip_class == CAYMAN)
839 tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
840 else
841 tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
842 tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
843 S_030004_TEX_DEPTH(depth - 1) |
844 S_030004_ARRAY_MODE(array_mode));
845 tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
846
847 *skip_mip_address_reloc = false;
848 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
849 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
850 if (tmp->is_depth) {
851 /* disable FMASK (0 = disabled) */
852 tex_resource_words[3] = 0;
853 *skip_mip_address_reloc = true;
854 } else {
855 /* FMASK should be in MIP_ADDRESS for multisample textures */
856 tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
857 }
858 } else if (last_level && texture->nr_samples <= 1) {
859 tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
860 } else {
861 tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
862 }
863
864 last_layer = params->last_layer;
865 if (params->target != texture->target && depth == 1) {
866 last_layer = params->first_layer;
867 }
868 tex_resource_words[4] = (word4 |
869 S_030010_ENDIAN_SWAP(endian));
870 tex_resource_words[5] = S_030014_BASE_ARRAY(params->first_layer) |
871 S_030014_LAST_ARRAY(last_layer);
872 tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
873
874 if (texture->nr_samples > 1) {
875 unsigned log_samples = util_logbase2(texture->nr_samples);
876 if (rscreen->b.chip_class == CAYMAN) {
877 tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
878 }
879 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
880 tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
881 tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
882 } else {
883 bool no_mip = first_level == last_level;
884
885 tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
886 tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
887 /* aniso max 16 samples */
888 tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
889 }
890
891 tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
892 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
893 S_03001C_BANK_WIDTH(bankw) |
894 S_03001C_BANK_HEIGHT(bankh) |
895 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
896 S_03001C_NUM_BANKS(nbanks) |
897 S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible);
898 return 0;
899 }
900
901 struct pipe_sampler_view *
902 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
903 struct pipe_resource *texture,
904 const struct pipe_sampler_view *state,
905 unsigned width0, unsigned height0,
906 unsigned force_level)
907 {
908 struct r600_context *rctx = (struct r600_context*)ctx;
909 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
910 struct r600_texture *tmp = (struct r600_texture*)texture;
911 struct eg_tex_res_params params;
912 int ret;
913
914 if (!view)
915 return NULL;
916
917 /* initialize base object */
918 view->base = *state;
919 view->base.texture = NULL;
920 pipe_reference(NULL, &texture->reference);
921 view->base.texture = texture;
922 view->base.reference.count = 1;
923 view->base.context = ctx;
924
925 if (state->target == PIPE_BUFFER)
926 return texture_buffer_sampler_view(rctx, view, width0, height0);
927
928 memset(&params, 0, sizeof(params));
929 params.pipe_format = state->format;
930 params.force_level = force_level;
931 params.width0 = width0;
932 params.height0 = height0;
933 params.first_level = state->u.tex.first_level;
934 params.last_level = state->u.tex.last_level;
935 params.first_layer = state->u.tex.first_layer;
936 params.last_layer = state->u.tex.last_layer;
937 params.target = state->target;
938 params.swizzle[0] = state->swizzle_r;
939 params.swizzle[1] = state->swizzle_g;
940 params.swizzle[2] = state->swizzle_b;
941 params.swizzle[3] = state->swizzle_a;
942
943 ret = evergreen_fill_tex_resource_words(rctx, texture, &params,
944 &view->skip_mip_address_reloc,
945 view->tex_resource_words);
946 if (ret != 0) {
947 FREE(view);
948 return NULL;
949 }
950
951 if (state->format == PIPE_FORMAT_X24S8_UINT ||
952 state->format == PIPE_FORMAT_S8X24_UINT ||
953 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
954 state->format == PIPE_FORMAT_S8_UINT)
955 view->is_stencil_sampler = true;
956
957 view->tex_resource = &tmp->resource;
958
959 return &view->base;
960 }
961
962 static struct pipe_sampler_view *
963 evergreen_create_sampler_view(struct pipe_context *ctx,
964 struct pipe_resource *tex,
965 const struct pipe_sampler_view *state)
966 {
967 return evergreen_create_sampler_view_custom(ctx, tex, state,
968 tex->width0, tex->height0, 0);
969 }
970
971 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
972 {
973 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
974 struct r600_config_state *a = (struct r600_config_state*)atom;
975
976 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
977 if (a->dyn_gpr_enabled) {
978 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
979 radeon_emit(cs, 0);
980 radeon_emit(cs, 0);
981 } else {
982 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
983 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
984 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
985 }
986 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
987 if (a->dyn_gpr_enabled) {
988 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
989 S_028838_PS_GPRS(0x1e) |
990 S_028838_VS_GPRS(0x1e) |
991 S_028838_GS_GPRS(0x1e) |
992 S_028838_ES_GPRS(0x1e) |
993 S_028838_HS_GPRS(0x1e) |
994 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
995 }
996 }
997
998 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
999 {
1000 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1001 struct pipe_clip_state *state = &rctx->clip_state.state;
1002
1003 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
1004 radeon_emit_array(cs, (unsigned*)state, 6*4);
1005 }
1006
1007 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1008 const struct pipe_poly_stipple *state)
1009 {
1010 }
1011
1012 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1013 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1014 uint32_t *tl, uint32_t *br)
1015 {
1016 struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
1017
1018 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
1019
1020 *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
1021 *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
1022 }
1023
1024 struct r600_tex_color_info {
1025 unsigned info;
1026 unsigned view;
1027 unsigned dim;
1028 unsigned pitch;
1029 unsigned slice;
1030 unsigned attrib;
1031 unsigned ntype;
1032 unsigned fmask;
1033 unsigned fmask_slice;
1034 uint64_t offset;
1035 boolean export_16bpc;
1036 };
1037
1038 static void evergreen_set_color_surface_buffer(struct r600_context *rctx,
1039 struct r600_resource *res,
1040 enum pipe_format pformat,
1041 unsigned first_element,
1042 unsigned last_element,
1043 struct r600_tex_color_info *color)
1044 {
1045 unsigned format, swap, ntype, endian;
1046 const struct util_format_description *desc;
1047 unsigned block_size = util_format_get_blocksize(res->b.b.format);
1048 unsigned pitch_alignment =
1049 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
1050 unsigned pitch = align(res->b.b.width0, pitch_alignment);
1051 int i;
1052 unsigned width_elements;
1053
1054 width_elements = last_element - first_element + 1;
1055
1056 format = r600_translate_colorformat(rctx->b.chip_class, pformat, FALSE);
1057 swap = r600_translate_colorswap(pformat, FALSE);
1058
1059 endian = r600_colorformat_endian_swap(format, FALSE);
1060
1061 desc = util_format_description(pformat);
1062 for (i = 0; i < 4; i++) {
1063 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1064 break;
1065 }
1066 }
1067 ntype = V_028C70_NUMBER_UNORM;
1068 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1069 ntype = V_028C70_NUMBER_SRGB;
1070 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1071 if (desc->channel[i].normalized)
1072 ntype = V_028C70_NUMBER_SNORM;
1073 else if (desc->channel[i].pure_integer)
1074 ntype = V_028C70_NUMBER_SINT;
1075 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1076 if (desc->channel[i].normalized)
1077 ntype = V_028C70_NUMBER_UNORM;
1078 else if (desc->channel[i].pure_integer)
1079 ntype = V_028C70_NUMBER_UINT;
1080 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1081 ntype = V_028C70_NUMBER_FLOAT;
1082 }
1083
1084 pitch = (pitch / 8) - 1;
1085 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1086
1087 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1088 color->info |= S_028C70_FORMAT(format) |
1089 S_028C70_COMP_SWAP(swap) |
1090 S_028C70_BLEND_CLAMP(0) |
1091 S_028C70_BLEND_BYPASS(1) |
1092 S_028C70_NUMBER_TYPE(ntype) |
1093 S_028C70_ENDIAN(endian);
1094 color->attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1095 color->ntype = ntype;
1096 color->export_16bpc = false;
1097 color->dim = width_elements - 1;
1098 color->slice = 0; /* (width_elements / 64) - 1;*/
1099 color->view = 0;
1100 color->offset = (res->gpu_address + first_element) >> 8;
1101
1102 color->fmask = color->offset;
1103 color->fmask_slice = 0;
1104 }
1105
1106 static void evergreen_set_color_surface_common(struct r600_context *rctx,
1107 struct r600_texture *rtex,
1108 unsigned level,
1109 unsigned first_layer,
1110 unsigned last_layer,
1111 enum pipe_format pformat,
1112 struct r600_tex_color_info *color)
1113 {
1114 struct r600_screen *rscreen = rctx->screen;
1115 unsigned pitch, slice;
1116 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1117 unsigned format, swap, ntype, endian;
1118 const struct util_format_description *desc;
1119 bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
1120 int i;
1121
1122 color->offset = rtex->surface.u.legacy.level[level].offset;
1123 color->view = S_028C6C_SLICE_START(first_layer) |
1124 S_028C6C_SLICE_MAX(last_layer);
1125
1126 color->offset += rtex->resource.gpu_address;
1127 color->offset >>= 8;
1128
1129 color->dim = 0;
1130 pitch = (rtex->surface.u.legacy.level[level].nblk_x) / 8 - 1;
1131 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1132 if (slice) {
1133 slice = slice - 1;
1134 }
1135
1136 color->info = 0;
1137 switch (rtex->surface.u.legacy.level[level].mode) {
1138 default:
1139 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1140 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1141 non_disp_tiling = 1;
1142 break;
1143 case RADEON_SURF_MODE_1D:
1144 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1145 non_disp_tiling = rtex->non_disp_tiling;
1146 break;
1147 case RADEON_SURF_MODE_2D:
1148 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1149 non_disp_tiling = rtex->non_disp_tiling;
1150 break;
1151 }
1152 tile_split = rtex->surface.u.legacy.tile_split;
1153 macro_aspect = rtex->surface.u.legacy.mtilea;
1154 bankw = rtex->surface.u.legacy.bankw;
1155 bankh = rtex->surface.u.legacy.bankh;
1156 if (rtex->fmask.size)
1157 fmask_bankh = rtex->fmask.bank_height;
1158 else
1159 fmask_bankh = rtex->surface.u.legacy.bankh;
1160 tile_split = eg_tile_split(tile_split);
1161 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1162 bankw = eg_bank_wh(bankw);
1163 bankh = eg_bank_wh(bankh);
1164 fmask_bankh = eg_bank_wh(fmask_bankh);
1165
1166 if (rscreen->b.chip_class == CAYMAN) {
1167 if (util_format_get_blocksize(pformat) >= 16)
1168 non_disp_tiling = 1;
1169 }
1170 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1171 desc = util_format_description(pformat);
1172 for (i = 0; i < 4; i++) {
1173 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1174 break;
1175 }
1176 }
1177 color->attrib = S_028C74_TILE_SPLIT(tile_split)|
1178 S_028C74_NUM_BANKS(nbanks) |
1179 S_028C74_BANK_WIDTH(bankw) |
1180 S_028C74_BANK_HEIGHT(bankh) |
1181 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1182 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1183 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1184
1185 if (rctx->b.chip_class == CAYMAN) {
1186 color->attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1187 PIPE_SWIZZLE_1);
1188
1189 if (rtex->resource.b.b.nr_samples > 1) {
1190 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1191 color->attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1192 S_028C74_NUM_FRAGMENTS(log_samples);
1193 }
1194 }
1195
1196 ntype = V_028C70_NUMBER_UNORM;
1197 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1198 ntype = V_028C70_NUMBER_SRGB;
1199 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1200 if (desc->channel[i].normalized)
1201 ntype = V_028C70_NUMBER_SNORM;
1202 else if (desc->channel[i].pure_integer)
1203 ntype = V_028C70_NUMBER_SINT;
1204 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1205 if (desc->channel[i].normalized)
1206 ntype = V_028C70_NUMBER_UNORM;
1207 else if (desc->channel[i].pure_integer)
1208 ntype = V_028C70_NUMBER_UINT;
1209 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1210 ntype = V_028C70_NUMBER_FLOAT;
1211 }
1212
1213 if (R600_BIG_ENDIAN)
1214 do_endian_swap = !rtex->db_compatible;
1215
1216 format = r600_translate_colorformat(rctx->b.chip_class, pformat, do_endian_swap);
1217 assert(format != ~0);
1218 swap = r600_translate_colorswap(pformat, do_endian_swap);
1219 assert(swap != ~0);
1220
1221 endian = r600_colorformat_endian_swap(format, do_endian_swap);
1222
1223 /* blend clamp should be set for all NORM/SRGB types */
1224 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1225 ntype == V_028C70_NUMBER_SRGB)
1226 blend_clamp = 1;
1227
1228 /* set blend bypass according to docs if SINT/UINT or
1229 8/24 COLOR variants */
1230 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1231 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1232 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1233 blend_clamp = 0;
1234 blend_bypass = 1;
1235 }
1236
1237 color->ntype = ntype;
1238 color->info |= S_028C70_FORMAT(format) |
1239 S_028C70_COMP_SWAP(swap) |
1240 S_028C70_BLEND_CLAMP(blend_clamp) |
1241 S_028C70_BLEND_BYPASS(blend_bypass) |
1242 S_028C70_SIMPLE_FLOAT(1) |
1243 S_028C70_NUMBER_TYPE(ntype) |
1244 S_028C70_ENDIAN(endian);
1245
1246 if (rtex->fmask.size) {
1247 color->info |= S_028C70_COMPRESSION(1);
1248 }
1249
1250 /* EXPORT_NORM is an optimzation that can be enabled for better
1251 * performance in certain cases.
1252 * EXPORT_NORM can be enabled if:
1253 * - 11-bit or smaller UNORM/SNORM/SRGB
1254 * - 16-bit or smaller FLOAT
1255 */
1256 color->export_16bpc = false;
1257 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1258 ((desc->channel[i].size < 12 &&
1259 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1260 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1261 (desc->channel[i].size < 17 &&
1262 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1263 color->info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1264 color->export_16bpc = true;
1265 }
1266
1267 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1268 color->slice = S_028C68_SLICE_TILE_MAX(slice);
1269
1270 if (rtex->fmask.size) {
1271 color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8;
1272 color->fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1273 } else {
1274 color->fmask = color->offset;
1275 color->fmask_slice = S_028C88_TILE_MAX(slice);
1276 }
1277 }
1278
1279 /**
1280 * This function intializes the CB* register values for RATs. It is meant
1281 * to be used for 1D aligned buffers that do not have an associated
1282 * radeon_surf.
1283 */
1284 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1285 struct r600_surface *surf)
1286 {
1287 struct pipe_resource *pipe_buffer = surf->base.texture;
1288 struct r600_tex_color_info color;
1289
1290 evergreen_set_color_surface_buffer(rctx, (struct r600_resource *)surf->base.texture,
1291 surf->base.format, 0, pipe_buffer->width0,
1292 &color);
1293
1294 surf->cb_color_base = color.offset;
1295 surf->cb_color_dim = color.dim;
1296 surf->cb_color_info = color.info | S_028C70_RAT(1);
1297 surf->cb_color_pitch = color.pitch;
1298 surf->cb_color_slice = color.slice;
1299 surf->cb_color_view = color.view;
1300 surf->cb_color_attrib = color.attrib;
1301 surf->cb_color_fmask = color.fmask;
1302 surf->cb_color_fmask_slice = color.fmask_slice;
1303
1304 surf->cb_color_view = 0;
1305
1306 /* Set the buffer range the GPU will have access to: */
1307 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
1308 0, pipe_buffer->width0);
1309 }
1310
1311
1312 void evergreen_init_color_surface(struct r600_context *rctx,
1313 struct r600_surface *surf)
1314 {
1315 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1316 unsigned level = surf->base.u.tex.level;
1317 struct r600_tex_color_info color;
1318
1319 evergreen_set_color_surface_common(rctx, rtex, level,
1320 surf->base.u.tex.first_layer,
1321 surf->base.u.tex.last_layer,
1322 surf->base.format,
1323 &color);
1324
1325 surf->alphatest_bypass = color.ntype == V_028C70_NUMBER_UINT ||
1326 color.ntype == V_028C70_NUMBER_SINT;
1327 surf->export_16bpc = color.export_16bpc;
1328
1329 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1330 surf->cb_color_base = color.offset;
1331 surf->cb_color_dim = color.dim;
1332 surf->cb_color_info = color.info;
1333 surf->cb_color_pitch = color.pitch;
1334 surf->cb_color_slice = color.slice;
1335 surf->cb_color_view = color.view;
1336 surf->cb_color_attrib = color.attrib;
1337 surf->cb_color_fmask = color.fmask;
1338 surf->cb_color_fmask_slice = color.fmask_slice;
1339
1340 surf->color_initialized = true;
1341 }
1342
1343 static void evergreen_init_depth_surface(struct r600_context *rctx,
1344 struct r600_surface *surf)
1345 {
1346 struct r600_screen *rscreen = rctx->screen;
1347 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1348 unsigned level = surf->base.u.tex.level;
1349 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
1350 uint64_t offset;
1351 unsigned format, array_mode;
1352 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1353
1354
1355 format = r600_translate_dbformat(surf->base.format);
1356 assert(format != ~0);
1357
1358 offset = rtex->resource.gpu_address;
1359 offset += rtex->surface.u.legacy.level[level].offset;
1360
1361 switch (rtex->surface.u.legacy.level[level].mode) {
1362 case RADEON_SURF_MODE_2D:
1363 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1364 break;
1365 case RADEON_SURF_MODE_1D:
1366 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1367 default:
1368 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1369 break;
1370 }
1371 tile_split = rtex->surface.u.legacy.tile_split;
1372 macro_aspect = rtex->surface.u.legacy.mtilea;
1373 bankw = rtex->surface.u.legacy.bankw;
1374 bankh = rtex->surface.u.legacy.bankh;
1375 tile_split = eg_tile_split(tile_split);
1376 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1377 bankw = eg_bank_wh(bankw);
1378 bankh = eg_bank_wh(bankh);
1379 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1380 offset >>= 8;
1381
1382 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1383 S_028040_FORMAT(format) |
1384 S_028040_TILE_SPLIT(tile_split)|
1385 S_028040_NUM_BANKS(nbanks) |
1386 S_028040_BANK_WIDTH(bankw) |
1387 S_028040_BANK_HEIGHT(bankh) |
1388 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1389 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1390 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1391 }
1392
1393 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1394
1395 surf->db_depth_base = offset;
1396 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1397 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1398 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1399 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1400 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1401 levelinfo->nblk_y / 64 - 1);
1402
1403 if (rtex->surface.has_stencil) {
1404 uint64_t stencil_offset;
1405 unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split;
1406
1407 stile_split = eg_tile_split(stile_split);
1408
1409 stencil_offset = rtex->surface.u.legacy.stencil_level[level].offset;
1410 stencil_offset += rtex->resource.gpu_address;
1411
1412 surf->db_stencil_base = stencil_offset >> 8;
1413 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1414 S_028044_TILE_SPLIT(stile_split);
1415 } else {
1416 surf->db_stencil_base = offset;
1417 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1418 * Older kernels are out of luck. */
1419 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1420 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1421 S_028044_FORMAT(V_028044_STENCIL_8);
1422 }
1423
1424 if (r600_htile_enabled(rtex, level)) {
1425 uint64_t va = rtex->resource.gpu_address + rtex->htile_offset;
1426 surf->db_htile_data_base = va >> 8;
1427 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1428 S_028ABC_HTILE_HEIGHT(1) |
1429 S_028ABC_FULL_CACHE(1);
1430 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1431 surf->db_preload_control = 0;
1432 }
1433
1434 surf->depth_initialized = true;
1435 }
1436
1437 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1438 const struct pipe_framebuffer_state *state)
1439 {
1440 struct r600_context *rctx = (struct r600_context *)ctx;
1441 struct r600_surface *surf;
1442 struct r600_texture *rtex;
1443 uint32_t i, log_samples;
1444 uint32_t target_mask = 0;
1445 /* Flush TC when changing the framebuffer state, because the only
1446 * client not using TC that can change textures is the framebuffer.
1447 * Other places don't typically have to flush TC.
1448 */
1449 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1450 R600_CONTEXT_FLUSH_AND_INV |
1451 R600_CONTEXT_FLUSH_AND_INV_CB |
1452 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1453 R600_CONTEXT_FLUSH_AND_INV_DB |
1454 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1455 R600_CONTEXT_INV_TEX_CACHE;
1456
1457 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1458
1459 /* Colorbuffers. */
1460 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1461 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1462 util_format_is_pure_integer(state->cbufs[0]->format);
1463 rctx->framebuffer.compressed_cb_mask = 0;
1464 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1465
1466 for (i = 0; i < state->nr_cbufs; i++) {
1467 surf = (struct r600_surface*)state->cbufs[i];
1468 if (!surf)
1469 continue;
1470
1471 target_mask |= (0xf << (i * 4));
1472
1473 rtex = (struct r600_texture*)surf->base.texture;
1474
1475 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1476
1477 if (!surf->color_initialized) {
1478 evergreen_init_color_surface(rctx, surf);
1479 }
1480
1481 if (!surf->export_16bpc) {
1482 rctx->framebuffer.export_16bpc = false;
1483 }
1484
1485 if (rtex->fmask.size) {
1486 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1487 }
1488 }
1489
1490 /* Update alpha-test state dependencies.
1491 * Alpha-test is done on the first colorbuffer only. */
1492 if (state->nr_cbufs) {
1493 bool alphatest_bypass = false;
1494 bool export_16bpc = true;
1495
1496 surf = (struct r600_surface*)state->cbufs[0];
1497 if (surf) {
1498 alphatest_bypass = surf->alphatest_bypass;
1499 export_16bpc = surf->export_16bpc;
1500 }
1501
1502 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1503 rctx->alphatest_state.bypass = alphatest_bypass;
1504 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1505 }
1506 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1507 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1508 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1509 }
1510 }
1511
1512 /* ZS buffer. */
1513 if (state->zsbuf) {
1514 surf = (struct r600_surface*)state->zsbuf;
1515
1516 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1517
1518 if (!surf->depth_initialized) {
1519 evergreen_init_depth_surface(rctx, surf);
1520 }
1521
1522 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1523 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1524 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1525 }
1526
1527 if (rctx->db_state.rsurf != surf) {
1528 rctx->db_state.rsurf = surf;
1529 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1530 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1531 }
1532 } else if (rctx->db_state.rsurf) {
1533 rctx->db_state.rsurf = NULL;
1534 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1535 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1536 }
1537
1538 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs ||
1539 rctx->cb_misc_state.bound_cbufs_target_mask != target_mask) {
1540 rctx->cb_misc_state.bound_cbufs_target_mask = target_mask;
1541 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1542 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1543 }
1544
1545 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1546 rctx->alphatest_state.bypass = false;
1547 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1548 }
1549
1550 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1551 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1552 if ((rctx->b.chip_class == CAYMAN ||
1553 rctx->b.family == CHIP_RV770) &&
1554 rctx->db_misc_state.log_samples != log_samples) {
1555 rctx->db_misc_state.log_samples = log_samples;
1556 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1557 }
1558
1559
1560 /* Calculate the CS size. */
1561 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1562
1563 /* MSAA. */
1564 if (rctx->b.chip_class == EVERGREEN)
1565 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1566 else
1567 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1568
1569 /* Colorbuffers. */
1570 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1571 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1572 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1573
1574 /* ZS buffer. */
1575 if (state->zsbuf) {
1576 rctx->framebuffer.atom.num_dw += 24;
1577 rctx->framebuffer.atom.num_dw += 2;
1578 } else if (rctx->screen->b.info.drm_minor >= 18) {
1579 rctx->framebuffer.atom.num_dw += 4;
1580 }
1581
1582 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1583
1584 r600_set_sample_locations_constant_buffer(rctx);
1585 rctx->framebuffer.do_update_surf_dirtiness = true;
1586 }
1587
1588 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1589 {
1590 struct r600_context *rctx = (struct r600_context *)ctx;
1591
1592 if (rctx->ps_iter_samples == min_samples)
1593 return;
1594
1595 rctx->ps_iter_samples = min_samples;
1596 if (rctx->framebuffer.nr_samples > 1) {
1597 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1598 }
1599 }
1600
1601 /* 8xMSAA */
1602 static const uint32_t sample_locs_8x[] = {
1603 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1604 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1605 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1606 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1607 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1608 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1609 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1610 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1611 };
1612 static unsigned max_dist_8x = 7;
1613
1614 static void evergreen_get_sample_position(struct pipe_context *ctx,
1615 unsigned sample_count,
1616 unsigned sample_index,
1617 float *out_value)
1618 {
1619 int offset, index;
1620 struct {
1621 int idx:4;
1622 } val;
1623 switch (sample_count) {
1624 case 1:
1625 default:
1626 out_value[0] = out_value[1] = 0.5;
1627 break;
1628 case 2:
1629 offset = 4 * (sample_index * 2);
1630 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1631 out_value[0] = (float)(val.idx + 8) / 16.0f;
1632 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1633 out_value[1] = (float)(val.idx + 8) / 16.0f;
1634 break;
1635 case 4:
1636 offset = 4 * (sample_index * 2);
1637 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1638 out_value[0] = (float)(val.idx + 8) / 16.0f;
1639 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1640 out_value[1] = (float)(val.idx + 8) / 16.0f;
1641 break;
1642 case 8:
1643 offset = 4 * (sample_index % 4 * 2);
1644 index = (sample_index / 4);
1645 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1646 out_value[0] = (float)(val.idx + 8) / 16.0f;
1647 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1648 out_value[1] = (float)(val.idx + 8) / 16.0f;
1649 break;
1650 }
1651 }
1652
1653 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1654 {
1655
1656 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1657 unsigned max_dist = 0;
1658
1659 switch (nr_samples) {
1660 default:
1661 nr_samples = 0;
1662 break;
1663 case 2:
1664 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x));
1665 radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x));
1666 max_dist = eg_max_dist_2x;
1667 break;
1668 case 4:
1669 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x));
1670 radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x));
1671 max_dist = eg_max_dist_4x;
1672 break;
1673 case 8:
1674 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x));
1675 radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x));
1676 max_dist = max_dist_8x;
1677 break;
1678 }
1679
1680 if (nr_samples > 1) {
1681 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1682 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1683 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1684 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1685 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1686 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1687 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1688 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1689 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1690 } else {
1691 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1692 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1693 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1694 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1695 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1696 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1697 }
1698 }
1699
1700 static void evergreen_emit_image_state(struct r600_context *rctx, struct r600_atom *atom,
1701 int immed_id_base, int res_id_base, int offset, uint32_t pkt_flags)
1702 {
1703 struct r600_image_state *state = (struct r600_image_state *)atom;
1704 struct pipe_framebuffer_state *fb_state = &rctx->framebuffer.state;
1705 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1706 struct r600_texture *rtex;
1707 struct r600_resource *resource;
1708 int i;
1709
1710 for (i = 0; i < R600_MAX_IMAGES; i++) {
1711 struct r600_image_view *image = &state->views[i];
1712 unsigned reloc, immed_reloc;
1713 int idx = i + offset;
1714
1715 if (!pkt_flags)
1716 idx += fb_state->nr_cbufs + (rctx->dual_src_blend ? 1 : 0);
1717 if (!image->base.resource)
1718 continue;
1719
1720 resource = (struct r600_resource *)image->base.resource;
1721 if (resource->b.b.target != PIPE_BUFFER)
1722 rtex = (struct r600_texture *)image->base.resource;
1723 else
1724 rtex = NULL;
1725
1726 reloc = radeon_add_to_buffer_list(&rctx->b,
1727 &rctx->b.gfx,
1728 resource,
1729 RADEON_USAGE_READWRITE,
1730 RADEON_PRIO_SHADER_RW_BUFFER);
1731
1732 immed_reloc = radeon_add_to_buffer_list(&rctx->b,
1733 &rctx->b.gfx,
1734 resource->immed_buffer,
1735 RADEON_USAGE_READWRITE,
1736 RADEON_PRIO_SHADER_RW_BUFFER);
1737
1738 if (pkt_flags)
1739 radeon_compute_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13);
1740 else
1741 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13);
1742
1743 radeon_emit(cs, image->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1744 radeon_emit(cs, image->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1745 radeon_emit(cs, image->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1746 radeon_emit(cs, image->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1747 radeon_emit(cs, image->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1748 radeon_emit(cs, image->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1749 radeon_emit(cs, image->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1750 radeon_emit(cs, rtex ? rtex->cmask.base_address_reg : image->cb_color_base); /* R_028C7C_CB_COLOR0_CMASK */
1751 radeon_emit(cs, rtex ? rtex->cmask.slice_tile_max : 0); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1752 radeon_emit(cs, image->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1753 radeon_emit(cs, image->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1754 radeon_emit(cs, rtex ? rtex->color_clear_value[0] : 0); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1755 radeon_emit(cs, rtex ? rtex->color_clear_value[1] : 0); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1756
1757 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1758 radeon_emit(cs, reloc);
1759
1760 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1761 radeon_emit(cs, reloc);
1762
1763 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1764 radeon_emit(cs, reloc);
1765
1766 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1767 radeon_emit(cs, reloc);
1768
1769 if (pkt_flags)
1770 radeon_compute_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1771 else
1772 radeon_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1773
1774 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /**/
1775 radeon_emit(cs, immed_reloc);
1776
1777 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1778 radeon_emit(cs, (immed_id_base + i + offset) * 8);
1779 radeon_emit_array(cs, image->immed_resource_words, 8);
1780
1781 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1782 radeon_emit(cs, immed_reloc);
1783
1784 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1785 radeon_emit(cs, (res_id_base + i + offset) * 8);
1786 radeon_emit_array(cs, image->resource_words, 8);
1787
1788 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1789 radeon_emit(cs, reloc);
1790
1791 if (!image->skip_mip_address_reloc) {
1792 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1793 radeon_emit(cs, reloc);
1794 }
1795 }
1796 }
1797
1798 static void evergreen_emit_fragment_image_state(struct r600_context *rctx, struct r600_atom *atom)
1799 {
1800 evergreen_emit_image_state(rctx, atom,
1801 R600_IMAGE_IMMED_RESOURCE_OFFSET,
1802 R600_IMAGE_REAL_RESOURCE_OFFSET, 0, 0);
1803 }
1804
1805 static void evergreen_emit_compute_image_state(struct r600_context *rctx, struct r600_atom *atom)
1806 {
1807 evergreen_emit_image_state(rctx, atom,
1808 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_IMMED_RESOURCE_OFFSET,
1809 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_REAL_RESOURCE_OFFSET,
1810 0, RADEON_CP_PACKET3_COMPUTE_MODE);
1811 }
1812
1813 static void evergreen_emit_fragment_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1814 {
1815 int offset = util_bitcount(rctx->fragment_images.enabled_mask);
1816 evergreen_emit_image_state(rctx, atom,
1817 R600_IMAGE_IMMED_RESOURCE_OFFSET,
1818 R600_IMAGE_REAL_RESOURCE_OFFSET, offset, 0);
1819 }
1820
1821 static void evergreen_emit_compute_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1822 {
1823 int offset = util_bitcount(rctx->compute_images.enabled_mask);
1824 evergreen_emit_image_state(rctx, atom,
1825 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_IMMED_RESOURCE_OFFSET,
1826 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_REAL_RESOURCE_OFFSET,
1827 offset, RADEON_CP_PACKET3_COMPUTE_MODE);
1828 }
1829
1830 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1831 {
1832 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1833 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1834 unsigned nr_cbufs = state->nr_cbufs;
1835 unsigned i, tl, br;
1836 struct r600_texture *tex = NULL;
1837 struct r600_surface *cb = NULL;
1838
1839 /* XXX support more colorbuffers once we need them */
1840 assert(nr_cbufs <= 8);
1841 if (nr_cbufs > 8)
1842 nr_cbufs = 8;
1843
1844 /* Colorbuffers. */
1845 for (i = 0; i < nr_cbufs; i++) {
1846 unsigned reloc, cmask_reloc;
1847
1848 cb = (struct r600_surface*)state->cbufs[i];
1849 if (!cb) {
1850 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1851 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1852 continue;
1853 }
1854
1855 tex = (struct r600_texture *)cb->base.texture;
1856 reloc = radeon_add_to_buffer_list(&rctx->b,
1857 &rctx->b.gfx,
1858 (struct r600_resource*)cb->base.texture,
1859 RADEON_USAGE_READWRITE,
1860 tex->resource.b.b.nr_samples > 1 ?
1861 RADEON_PRIO_COLOR_BUFFER_MSAA :
1862 RADEON_PRIO_COLOR_BUFFER);
1863
1864 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1865 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1866 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1867 RADEON_PRIO_SEPARATE_META);
1868 } else {
1869 cmask_reloc = reloc;
1870 }
1871
1872 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1873 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1874 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1875 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1876 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1877 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1878 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1879 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1880 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1881 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1882 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1883 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1884 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1885 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1886
1887 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1888 radeon_emit(cs, reloc);
1889
1890 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1891 radeon_emit(cs, reloc);
1892
1893 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1894 radeon_emit(cs, cmask_reloc);
1895
1896 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1897 radeon_emit(cs, reloc);
1898 }
1899 /* set CB_COLOR1_INFO for possible dual-src blending */
1900 if (rctx->framebuffer.dual_src_blend && i == 1 && state->cbufs[0]) {
1901 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1902 cb->cb_color_info | tex->cb_color_info);
1903 i++;
1904 }
1905 i += util_bitcount(rctx->fragment_images.enabled_mask);
1906 i += util_bitcount(rctx->fragment_buffers.enabled_mask);
1907 for (; i < 8 ; i++)
1908 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1909 for (; i < 12; i++)
1910 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1911
1912 /* ZS buffer. */
1913 if (state->zsbuf) {
1914 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1915 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1916 &rctx->b.gfx,
1917 (struct r600_resource*)state->zsbuf->texture,
1918 RADEON_USAGE_READWRITE,
1919 zb->base.texture->nr_samples > 1 ?
1920 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1921 RADEON_PRIO_DEPTH_BUFFER);
1922
1923 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1924
1925 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1926 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1927 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1928 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1929 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1930 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1931 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1932 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1933 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1934
1935 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1936 radeon_emit(cs, reloc);
1937
1938 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1939 radeon_emit(cs, reloc);
1940
1941 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1942 radeon_emit(cs, reloc);
1943
1944 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1945 radeon_emit(cs, reloc);
1946 } else if (rctx->screen->b.info.drm_minor >= 18) {
1947 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1948 * Older kernels are out of luck. */
1949 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1950 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1951 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1952 }
1953
1954 /* Framebuffer dimensions. */
1955 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1956
1957 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1958 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1959 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1960
1961 if (rctx->b.chip_class == EVERGREEN) {
1962 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1963 } else {
1964 cayman_emit_msaa_state(cs, rctx->framebuffer.nr_samples,
1965 rctx->ps_iter_samples, 0);
1966 }
1967 }
1968
1969 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1970 {
1971 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1972 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1973 float offset_units = state->offset_units;
1974 float offset_scale = state->offset_scale;
1975 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
1976
1977 if (!state->offset_units_unscaled) {
1978 switch (state->zs_format) {
1979 case PIPE_FORMAT_Z24X8_UNORM:
1980 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1981 case PIPE_FORMAT_X8Z24_UNORM:
1982 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1983 offset_units *= 2.0f;
1984 pa_su_poly_offset_db_fmt_cntl =
1985 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1986 break;
1987 case PIPE_FORMAT_Z16_UNORM:
1988 offset_units *= 4.0f;
1989 pa_su_poly_offset_db_fmt_cntl =
1990 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1991 break;
1992 default:
1993 pa_su_poly_offset_db_fmt_cntl =
1994 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1995 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1996 }
1997 }
1998
1999 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
2000 radeon_emit(cs, fui(offset_scale));
2001 radeon_emit(cs, fui(offset_units));
2002 radeon_emit(cs, fui(offset_scale));
2003 radeon_emit(cs, fui(offset_units));
2004
2005 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2006 pa_su_poly_offset_db_fmt_cntl);
2007 }
2008
2009 uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a,
2010 unsigned nr_cbufs)
2011 {
2012 unsigned base_mask = 0;
2013 unsigned dirty_mask = a->image_rat_enabled_mask;
2014 while (dirty_mask) {
2015 unsigned idx = u_bit_scan(&dirty_mask);
2016 base_mask |= (0xf << (idx * 4));
2017 }
2018 unsigned offset = util_last_bit(a->image_rat_enabled_mask);
2019 dirty_mask = a->buffer_rat_enabled_mask;
2020 while (dirty_mask) {
2021 unsigned idx = u_bit_scan(&dirty_mask);
2022 base_mask |= (0xf << (idx + offset) * 4);
2023 }
2024 return base_mask << (nr_cbufs * 4);
2025 }
2026
2027 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2028 {
2029 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
2030 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
2031 unsigned fb_colormask = a->bound_cbufs_target_mask;
2032 unsigned ps_colormask = a->ps_color_export_mask;
2033 unsigned rat_colormask = evergreen_construct_rat_mask(rctx, a, a->nr_cbufs);
2034 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
2035 radeon_emit(cs, (a->blend_colormask & fb_colormask) | rat_colormask); /* R_028238_CB_TARGET_MASK */
2036 /* This must match the used export instructions exactly.
2037 * Other values may lead to undefined behavior and hangs.
2038 */
2039 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
2040 }
2041
2042 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
2043 {
2044 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
2045 struct r600_db_state *a = (struct r600_db_state*)atom;
2046
2047 if (a->rsurf && a->rsurf->db_htile_surface) {
2048 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
2049 unsigned reloc_idx;
2050
2051 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2052 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
2053 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
2054 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
2055 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
2056 RADEON_USAGE_READWRITE, RADEON_PRIO_SEPARATE_META);
2057 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2058 radeon_emit(cs, reloc_idx);
2059 } else {
2060 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
2061 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
2062 }
2063 }
2064
2065 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2066 {
2067 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
2068 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2069 unsigned db_render_control = 0;
2070 unsigned db_count_control = 0;
2071 unsigned db_render_override =
2072 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2073 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2074
2075 if (rctx->b.num_occlusion_queries > 0 &&
2076 !a->occlusion_queries_disabled) {
2077 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
2078 if (rctx->b.chip_class == CAYMAN) {
2079 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
2080 }
2081 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
2082 } else {
2083 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
2084 }
2085
2086 /* This is to fix a lockup when hyperz and alpha test are enabled at
2087 * the same time somehow GPU get confuse on which order to pick for
2088 * z test
2089 */
2090 if (rctx->alphatest_state.sx_alpha_test_control)
2091 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
2092
2093 if (a->flush_depthstencil_through_cb) {
2094 assert(a->copy_depth || a->copy_stencil);
2095
2096 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
2097 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
2098 S_028000_COPY_CENTROID(1) |
2099 S_028000_COPY_SAMPLE(a->copy_sample);
2100 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
2101 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
2102 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
2103 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2104 }
2105 if (a->htile_clear) {
2106 /* FIXME we might want to disable cliprect here */
2107 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
2108 }
2109
2110 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
2111 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
2112 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
2113 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2114 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2115 }
2116
2117 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
2118 struct r600_vertexbuf_state *state,
2119 unsigned resource_offset,
2120 unsigned pkt_flags)
2121 {
2122 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
2123 uint32_t dirty_mask = state->dirty_mask;
2124
2125 while (dirty_mask) {
2126 struct pipe_vertex_buffer *vb;
2127 struct r600_resource *rbuffer;
2128 uint64_t va;
2129 unsigned buffer_index = u_bit_scan(&dirty_mask);
2130
2131 vb = &state->vb[buffer_index];
2132 rbuffer = (struct r600_resource*)vb->buffer.resource;
2133 assert(rbuffer);
2134
2135 va = rbuffer->gpu_address + vb->buffer_offset;
2136
2137 /* fetch resources start at index 992 */
2138 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2139 radeon_emit(cs, (resource_offset + buffer_index) * 8);
2140 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2141 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2142 radeon_emit(cs, /* RESOURCEi_WORD2 */
2143 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2144 S_030008_STRIDE(vb->stride) |
2145 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2146 radeon_emit(cs, /* RESOURCEi_WORD3 */
2147 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2148 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2149 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2150 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2151 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2152 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2153 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2154 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2155
2156 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2157 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2158 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
2159 }
2160 state->dirty_mask = 0;
2161 }
2162
2163 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2164 {
2165 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
2166 }
2167
2168 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2169 {
2170 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
2171 RADEON_CP_PACKET3_COMPUTE_MODE);
2172 }
2173
2174 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2175 struct r600_constbuf_state *state,
2176 unsigned buffer_id_base,
2177 unsigned reg_alu_constbuf_size,
2178 unsigned reg_alu_const_cache,
2179 unsigned pkt_flags)
2180 {
2181 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
2182 uint32_t dirty_mask = state->dirty_mask;
2183
2184 while (dirty_mask) {
2185 struct pipe_constant_buffer *cb;
2186 struct r600_resource *rbuffer;
2187 uint64_t va;
2188 unsigned buffer_index = ffs(dirty_mask) - 1;
2189 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
2190
2191 cb = &state->cb[buffer_index];
2192 rbuffer = (struct r600_resource*)cb->buffer;
2193 assert(rbuffer);
2194
2195 va = rbuffer->gpu_address + cb->buffer_offset;
2196
2197 if (buffer_index < R600_MAX_HW_CONST_BUFFERS) {
2198 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
2199 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
2200 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
2201 pkt_flags);
2202 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2203 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2204 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2205 }
2206
2207 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2208 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
2209 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2210 radeon_emit(cs, cb->buffer_size -1); /* RESOURCEi_WORD1 */
2211 radeon_emit(cs, /* RESOURCEi_WORD2 */
2212 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
2213 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
2214 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
2215 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
2216 radeon_emit(cs, /* RESOURCEi_WORD3 */
2217 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
2218 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2219 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2220 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2221 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2222 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2223 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2224 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2225 radeon_emit(cs, /* RESOURCEi_WORD7 */
2226 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
2227
2228 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2229 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2230 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2231
2232 dirty_mask &= ~(1 << buffer_index);
2233 }
2234 state->dirty_mask = 0;
2235 }
2236
2237 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
2238 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2239 {
2240 if (rctx->vs_shader->current->shader.vs_as_ls) {
2241 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2242 EG_FETCH_CONSTANTS_OFFSET_LS,
2243 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2244 R_028F40_ALU_CONST_CACHE_LS_0,
2245 0 /* PKT3 flags */);
2246 } else {
2247 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2248 EG_FETCH_CONSTANTS_OFFSET_VS,
2249 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2250 R_028980_ALU_CONST_CACHE_VS_0,
2251 0 /* PKT3 flags */);
2252 }
2253 }
2254
2255 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2256 {
2257 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
2258 EG_FETCH_CONSTANTS_OFFSET_GS,
2259 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2260 R_0289C0_ALU_CONST_CACHE_GS_0,
2261 0 /* PKT3 flags */);
2262 }
2263
2264 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2265 {
2266 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
2267 EG_FETCH_CONSTANTS_OFFSET_PS,
2268 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2269 R_028940_ALU_CONST_CACHE_PS_0,
2270 0 /* PKT3 flags */);
2271 }
2272
2273 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2274 {
2275 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
2276 EG_FETCH_CONSTANTS_OFFSET_CS,
2277 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2278 R_028F40_ALU_CONST_CACHE_LS_0,
2279 RADEON_CP_PACKET3_COMPUTE_MODE);
2280 }
2281
2282 /* tes constants can be emitted to VS or ES - which are common */
2283 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2284 {
2285 if (!rctx->tes_shader)
2286 return;
2287 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2288 EG_FETCH_CONSTANTS_OFFSET_VS,
2289 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2290 R_028980_ALU_CONST_CACHE_VS_0,
2291 0);
2292 }
2293
2294 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2295 {
2296 if (!rctx->tes_shader)
2297 return;
2298 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2299 EG_FETCH_CONSTANTS_OFFSET_HS,
2300 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
2301 R_028F00_ALU_CONST_CACHE_HS_0,
2302 0);
2303 }
2304
2305 void evergreen_setup_scratch_buffers(struct r600_context *rctx) {
2306 static const struct {
2307 unsigned ring_base;
2308 unsigned item_size;
2309 unsigned ring_size;
2310 } regs[EG_NUM_HW_STAGES] = {
2311 [R600_HW_STAGE_PS] = { R_008C68_SQ_PSTMP_RING_BASE, R_028914_SQ_PSTMP_RING_ITEMSIZE, R_008C6C_SQ_PSTMP_RING_SIZE },
2312 [R600_HW_STAGE_VS] = { R_008C60_SQ_VSTMP_RING_BASE, R_028910_SQ_VSTMP_RING_ITEMSIZE, R_008C64_SQ_VSTMP_RING_SIZE },
2313 [R600_HW_STAGE_GS] = { R_008C58_SQ_GSTMP_RING_BASE, R_02890C_SQ_GSTMP_RING_ITEMSIZE, R_008C5C_SQ_GSTMP_RING_SIZE },
2314 [R600_HW_STAGE_ES] = { R_008C50_SQ_ESTMP_RING_BASE, R_028908_SQ_ESTMP_RING_ITEMSIZE, R_008C54_SQ_ESTMP_RING_SIZE },
2315 [EG_HW_STAGE_LS] = { R_008E10_SQ_LSTMP_RING_BASE, R_028830_SQ_LSTMP_RING_ITEMSIZE, R_008E14_SQ_LSTMP_RING_SIZE },
2316 [EG_HW_STAGE_HS] = { R_008E18_SQ_HSTMP_RING_BASE, R_028834_SQ_HSTMP_RING_ITEMSIZE, R_008E1C_SQ_HSTMP_RING_SIZE }
2317 };
2318
2319 for (unsigned i = 0; i < EG_NUM_HW_STAGES; i++) {
2320 struct r600_pipe_shader *stage = rctx->hw_shader_stages[i].shader;
2321
2322 if (stage && unlikely(stage->scratch_space_needed)) {
2323 r600_setup_scratch_area_for_shader(rctx, stage,
2324 &rctx->scratch_buffers[i], regs[i].ring_base, regs[i].item_size, regs[i].ring_size);
2325 }
2326 }
2327 }
2328
2329 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2330 struct r600_samplerview_state *state,
2331 unsigned resource_id_base, unsigned pkt_flags)
2332 {
2333 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
2334 uint32_t dirty_mask = state->dirty_mask;
2335
2336 while (dirty_mask) {
2337 struct r600_pipe_sampler_view *rview;
2338 unsigned resource_index = u_bit_scan(&dirty_mask);
2339 unsigned reloc;
2340
2341 rview = state->views[resource_index];
2342 assert(rview);
2343
2344 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2345 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2346 radeon_emit_array(cs, rview->tex_resource_words, 8);
2347
2348 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2349 RADEON_USAGE_READ,
2350 r600_get_sampler_view_priority(rview->tex_resource));
2351 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2352 radeon_emit(cs, reloc);
2353
2354 if (!rview->skip_mip_address_reloc) {
2355 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2356 radeon_emit(cs, reloc);
2357 }
2358 }
2359 state->dirty_mask = 0;
2360 }
2361
2362 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2363 {
2364 if (rctx->vs_shader->current->shader.vs_as_ls) {
2365 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2366 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2367 } else {
2368 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2369 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2370 }
2371 }
2372
2373 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2374 {
2375 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2376 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2377 }
2378
2379 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2380 {
2381 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2382 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2383 }
2384
2385 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2386 {
2387 if (!rctx->tes_shader)
2388 return;
2389 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2390 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2391 }
2392
2393 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2394 {
2395 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2396 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2397 }
2398
2399 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2400 {
2401 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2402 EG_FETCH_CONSTANTS_OFFSET_CS + R600_MAX_CONST_BUFFERS, RADEON_CP_PACKET3_COMPUTE_MODE);
2403 }
2404
2405 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2406 struct r600_textures_info *texinfo,
2407 unsigned resource_id_base,
2408 unsigned border_index_reg,
2409 unsigned pkt_flags)
2410 {
2411 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
2412 uint32_t dirty_mask = texinfo->states.dirty_mask;
2413
2414 while (dirty_mask) {
2415 struct r600_pipe_sampler_state *rstate;
2416 unsigned i = u_bit_scan(&dirty_mask);
2417
2418 rstate = texinfo->states.states[i];
2419 assert(rstate);
2420
2421 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2422 radeon_emit(cs, (resource_id_base + i) * 3);
2423 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2424
2425 if (rstate->border_color_use) {
2426 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2427 radeon_emit(cs, i);
2428 radeon_emit_array(cs, rstate->border_color.ui, 4);
2429 }
2430 }
2431 texinfo->states.dirty_mask = 0;
2432 }
2433
2434 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2435 {
2436 if (rctx->vs_shader->current->shader.vs_as_ls) {
2437 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2438 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2439 } else {
2440 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2441 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2442 }
2443 }
2444
2445 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2446 {
2447 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2448 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2449 }
2450
2451 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2452 {
2453 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2454 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2455 }
2456
2457 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2458 {
2459 if (!rctx->tes_shader)
2460 return;
2461 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2462 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2463 }
2464
2465 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2466 {
2467 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2468 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2469 }
2470
2471 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2472 {
2473 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2474 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2475 RADEON_CP_PACKET3_COMPUTE_MODE);
2476 }
2477
2478 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2479 {
2480 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2481 uint8_t mask = s->sample_mask;
2482
2483 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2484 mask | (mask << 8) | (mask << 16) | (mask << 24));
2485 }
2486
2487 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2488 {
2489 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2490 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
2491 uint16_t mask = s->sample_mask;
2492
2493 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2494 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2495 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2496 }
2497
2498 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2499 {
2500 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
2501 struct r600_cso_state *state = (struct r600_cso_state*)a;
2502 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2503
2504 if (!shader)
2505 return;
2506
2507 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2508 (shader->buffer->gpu_address + shader->offset) >> 8);
2509 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2510 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2511 RADEON_USAGE_READ,
2512 RADEON_PRIO_SHADER_BINARY));
2513 }
2514
2515 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2516 {
2517 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
2518 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2519
2520 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2521
2522 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2523 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2524 primid = 1;
2525 }
2526
2527 if (state->geom_enable) {
2528 uint32_t cut_val;
2529
2530 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2531 cut_val = V_028A40_GS_CUT_128;
2532 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2533 cut_val = V_028A40_GS_CUT_256;
2534 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2535 cut_val = V_028A40_GS_CUT_512;
2536 else
2537 cut_val = V_028A40_GS_CUT_1024;
2538
2539 v = S_028B54_GS_EN(1) |
2540 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2541 if (!rctx->tes_shader)
2542 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2543
2544 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2545 S_028A40_CUT_MODE(cut_val);
2546
2547 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2548 primid = 1;
2549 }
2550
2551 if (rctx->tes_shader) {
2552 uint32_t type, partitioning, topology;
2553 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2554 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2555 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2556 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2557 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2558 switch (tes_prim_mode) {
2559 case PIPE_PRIM_LINES:
2560 type = V_028B6C_TESS_ISOLINE;
2561 break;
2562 case PIPE_PRIM_TRIANGLES:
2563 type = V_028B6C_TESS_TRIANGLE;
2564 break;
2565 case PIPE_PRIM_QUADS:
2566 type = V_028B6C_TESS_QUAD;
2567 break;
2568 default:
2569 assert(0);
2570 return;
2571 }
2572
2573 switch (tes_spacing) {
2574 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2575 partitioning = V_028B6C_PART_FRAC_ODD;
2576 break;
2577 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2578 partitioning = V_028B6C_PART_FRAC_EVEN;
2579 break;
2580 case PIPE_TESS_SPACING_EQUAL:
2581 partitioning = V_028B6C_PART_INTEGER;
2582 break;
2583 default:
2584 assert(0);
2585 return;
2586 }
2587
2588 if (tes_point_mode)
2589 topology = V_028B6C_OUTPUT_POINT;
2590 else if (tes_prim_mode == PIPE_PRIM_LINES)
2591 topology = V_028B6C_OUTPUT_LINE;
2592 else if (tes_vertex_order_cw)
2593 /* XXX follow radeonsi and invert */
2594 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2595 else
2596 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2597
2598 tf_param = S_028B6C_TYPE(type) |
2599 S_028B6C_PARTITIONING(partitioning) |
2600 S_028B6C_TOPOLOGY(topology);
2601 }
2602
2603 if (rctx->tes_shader) {
2604 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2605 S_028B54_HS_EN(1);
2606 if (!state->geom_enable)
2607 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2608 else
2609 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2610 }
2611
2612 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2613 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2614 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2615 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2616 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2617 }
2618
2619 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2620 {
2621 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
2622 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2623 struct r600_resource *rbuffer;
2624
2625 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2626 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2627 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2628
2629 if (state->enable) {
2630 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2631 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2632 rbuffer->gpu_address >> 8);
2633 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2634 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2635 RADEON_USAGE_READWRITE,
2636 RADEON_PRIO_SHADER_RINGS));
2637 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2638 state->esgs_ring.buffer_size >> 8);
2639
2640 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2641 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2642 rbuffer->gpu_address >> 8);
2643 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2644 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2645 RADEON_USAGE_READWRITE,
2646 RADEON_PRIO_SHADER_RINGS));
2647 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2648 state->gsvs_ring.buffer_size >> 8);
2649 } else {
2650 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2651 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2652 }
2653
2654 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2655 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2656 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2657 }
2658
2659 void cayman_init_common_regs(struct r600_command_buffer *cb,
2660 enum chip_class ctx_chip_class,
2661 enum radeon_family ctx_family,
2662 int ctx_drm_minor)
2663 {
2664 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2665 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2666 /* always set the temp clauses */
2667 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2668
2669 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2670 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2671 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2672
2673 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2674
2675 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2676 r600_store_value(cb, 0);
2677 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2678
2679 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2680 }
2681
2682 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2683 {
2684 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2685 int i;
2686
2687 r600_init_command_buffer(cb, 338);
2688
2689 /* This must be first. */
2690 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2691 r600_store_value(cb, 0x80000000);
2692 r600_store_value(cb, 0x80000000);
2693
2694 /* We're setting config registers here. */
2695 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2696 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2697
2698 /* This enables pipeline stat & streamout queries.
2699 * They are only disabled by blits.
2700 */
2701 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2702 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2703
2704 cayman_init_common_regs(cb, rctx->b.chip_class,
2705 rctx->b.family, rctx->screen->b.info.drm_minor);
2706
2707 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2708 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2709
2710 /* remove LS/HS from one SIMD for hw workaround */
2711 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2712 r600_store_value(cb, 0xffffffff);
2713 r600_store_value(cb, 0xffffffff);
2714 r600_store_value(cb, 0xfffffffe);
2715
2716 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2717 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2718 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2719 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2720 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2721 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2722 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2723
2724 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2725 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2726 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2727 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2728 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2729
2730 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2731 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2732 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2733 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2734 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2735 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2736 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2737 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2738 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2739 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2740 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2741 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2742 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2743 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2744
2745 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2746
2747 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2748
2749 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2750 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2751 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2752
2753 r600_store_context_reg(cb, R_028724_GDS_ADDR_SIZE, 0x3fff);
2754 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2755 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2756 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2757
2758 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2759
2760 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2761 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2762 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2763
2764 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2765
2766 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2767
2768 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2769
2770 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2771 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2772 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2773 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2774
2775 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2776 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2777
2778 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2779 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2780
2781 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2782 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2783 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2784
2785 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2786 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2787 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2788
2789 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2790 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2791 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2792 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2793 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2794 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2795
2796 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2797
2798 /* to avoid GPU doing any preloading of constant from random address */
2799 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2800 for (i = 0; i < 16; i++)
2801 r600_store_value(cb, 0);
2802
2803 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2804 for (i = 0; i < 16; i++)
2805 r600_store_value(cb, 0);
2806
2807 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2808 for (i = 0; i < 16; i++)
2809 r600_store_value(cb, 0);
2810
2811 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2812 for (i = 0; i < 16; i++)
2813 r600_store_value(cb, 0);
2814
2815 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2816 for (i = 0; i < 16; i++)
2817 r600_store_value(cb, 0);
2818
2819 if (rctx->screen->b.has_streamout) {
2820 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2821 }
2822
2823 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2824 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2825 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2826 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2827 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2828 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2829
2830 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2831 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2832 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2833 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2834 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2835 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2836 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2837 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2838 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2839 }
2840
2841 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2842 enum chip_class ctx_chip_class,
2843 enum radeon_family ctx_family,
2844 int ctx_drm_minor)
2845 {
2846 int ps_prio;
2847 int vs_prio;
2848 int gs_prio;
2849 int es_prio;
2850
2851 int hs_prio;
2852 int cs_prio;
2853 int ls_prio;
2854
2855 unsigned tmp;
2856
2857 ps_prio = 0;
2858 vs_prio = 1;
2859 gs_prio = 2;
2860 es_prio = 3;
2861 hs_prio = 3;
2862 ls_prio = 3;
2863 cs_prio = 0;
2864
2865 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2866 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2867 rctx->r6xx_num_clause_temp_gprs = 4;
2868 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2869 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2870 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2871 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2872
2873 tmp = 0;
2874 switch (ctx_family) {
2875 case CHIP_CEDAR:
2876 case CHIP_PALM:
2877 case CHIP_SUMO:
2878 case CHIP_SUMO2:
2879 case CHIP_CAICOS:
2880 break;
2881 default:
2882 tmp |= S_008C00_VC_ENABLE(1);
2883 break;
2884 }
2885 tmp |= S_008C00_EXPORT_SRC_C(1);
2886 tmp |= S_008C00_CS_PRIO(cs_prio);
2887 tmp |= S_008C00_LS_PRIO(ls_prio);
2888 tmp |= S_008C00_HS_PRIO(hs_prio);
2889 tmp |= S_008C00_PS_PRIO(ps_prio);
2890 tmp |= S_008C00_VS_PRIO(vs_prio);
2891 tmp |= S_008C00_GS_PRIO(gs_prio);
2892 tmp |= S_008C00_ES_PRIO(es_prio);
2893
2894 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2895 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2896
2897 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2898 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2899 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2900
2901 /* The cs checker requires this register to be set. */
2902 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2903
2904 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2905 r600_store_value(cb, 0);
2906 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2907
2908 return;
2909 }
2910
2911 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2912 {
2913 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2914 int num_ps_threads;
2915 int num_vs_threads;
2916 int num_gs_threads;
2917 int num_es_threads;
2918 int num_hs_threads;
2919 int num_ls_threads;
2920
2921 int num_ps_stack_entries;
2922 int num_vs_stack_entries;
2923 int num_gs_stack_entries;
2924 int num_es_stack_entries;
2925 int num_hs_stack_entries;
2926 int num_ls_stack_entries;
2927 enum radeon_family family;
2928 unsigned tmp, i;
2929
2930 if (rctx->b.chip_class == CAYMAN) {
2931 cayman_init_atom_start_cs(rctx);
2932 return;
2933 }
2934
2935 r600_init_command_buffer(cb, 338);
2936
2937 /* This must be first. */
2938 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2939 r600_store_value(cb, 0x80000000);
2940 r600_store_value(cb, 0x80000000);
2941
2942 /* We're setting config registers here. */
2943 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2944 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2945
2946 /* This enables pipeline stat & streamout queries.
2947 * They are only disabled by blits.
2948 */
2949 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2950 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2951
2952 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2953 rctx->b.family, rctx->screen->b.info.drm_minor);
2954
2955 family = rctx->b.family;
2956 switch (family) {
2957 case CHIP_CEDAR:
2958 default:
2959 num_ps_threads = 96;
2960 num_vs_threads = 16;
2961 num_gs_threads = 16;
2962 num_es_threads = 16;
2963 num_hs_threads = 16;
2964 num_ls_threads = 16;
2965 num_ps_stack_entries = 42;
2966 num_vs_stack_entries = 42;
2967 num_gs_stack_entries = 42;
2968 num_es_stack_entries = 42;
2969 num_hs_stack_entries = 42;
2970 num_ls_stack_entries = 42;
2971 break;
2972 case CHIP_REDWOOD:
2973 num_ps_threads = 128;
2974 num_vs_threads = 20;
2975 num_gs_threads = 20;
2976 num_es_threads = 20;
2977 num_hs_threads = 20;
2978 num_ls_threads = 20;
2979 num_ps_stack_entries = 42;
2980 num_vs_stack_entries = 42;
2981 num_gs_stack_entries = 42;
2982 num_es_stack_entries = 42;
2983 num_hs_stack_entries = 42;
2984 num_ls_stack_entries = 42;
2985 break;
2986 case CHIP_JUNIPER:
2987 num_ps_threads = 128;
2988 num_vs_threads = 20;
2989 num_gs_threads = 20;
2990 num_es_threads = 20;
2991 num_hs_threads = 20;
2992 num_ls_threads = 20;
2993 num_ps_stack_entries = 85;
2994 num_vs_stack_entries = 85;
2995 num_gs_stack_entries = 85;
2996 num_es_stack_entries = 85;
2997 num_hs_stack_entries = 85;
2998 num_ls_stack_entries = 85;
2999 break;
3000 case CHIP_CYPRESS:
3001 case CHIP_HEMLOCK:
3002 num_ps_threads = 128;
3003 num_vs_threads = 20;
3004 num_gs_threads = 20;
3005 num_es_threads = 20;
3006 num_hs_threads = 20;
3007 num_ls_threads = 20;
3008 num_ps_stack_entries = 85;
3009 num_vs_stack_entries = 85;
3010 num_gs_stack_entries = 85;
3011 num_es_stack_entries = 85;
3012 num_hs_stack_entries = 85;
3013 num_ls_stack_entries = 85;
3014 break;
3015 case CHIP_PALM:
3016 num_ps_threads = 96;
3017 num_vs_threads = 16;
3018 num_gs_threads = 16;
3019 num_es_threads = 16;
3020 num_hs_threads = 16;
3021 num_ls_threads = 16;
3022 num_ps_stack_entries = 42;
3023 num_vs_stack_entries = 42;
3024 num_gs_stack_entries = 42;
3025 num_es_stack_entries = 42;
3026 num_hs_stack_entries = 42;
3027 num_ls_stack_entries = 42;
3028 break;
3029 case CHIP_SUMO:
3030 num_ps_threads = 96;
3031 num_vs_threads = 25;
3032 num_gs_threads = 25;
3033 num_es_threads = 25;
3034 num_hs_threads = 16;
3035 num_ls_threads = 16;
3036 num_ps_stack_entries = 42;
3037 num_vs_stack_entries = 42;
3038 num_gs_stack_entries = 42;
3039 num_es_stack_entries = 42;
3040 num_hs_stack_entries = 42;
3041 num_ls_stack_entries = 42;
3042 break;
3043 case CHIP_SUMO2:
3044 num_ps_threads = 96;
3045 num_vs_threads = 25;
3046 num_gs_threads = 25;
3047 num_es_threads = 25;
3048 num_hs_threads = 16;
3049 num_ls_threads = 16;
3050 num_ps_stack_entries = 85;
3051 num_vs_stack_entries = 85;
3052 num_gs_stack_entries = 85;
3053 num_es_stack_entries = 85;
3054 num_hs_stack_entries = 85;
3055 num_ls_stack_entries = 85;
3056 break;
3057 case CHIP_BARTS:
3058 num_ps_threads = 128;
3059 num_vs_threads = 20;
3060 num_gs_threads = 20;
3061 num_es_threads = 20;
3062 num_hs_threads = 20;
3063 num_ls_threads = 20;
3064 num_ps_stack_entries = 85;
3065 num_vs_stack_entries = 85;
3066 num_gs_stack_entries = 85;
3067 num_es_stack_entries = 85;
3068 num_hs_stack_entries = 85;
3069 num_ls_stack_entries = 85;
3070 break;
3071 case CHIP_TURKS:
3072 num_ps_threads = 128;
3073 num_vs_threads = 20;
3074 num_gs_threads = 20;
3075 num_es_threads = 20;
3076 num_hs_threads = 20;
3077 num_ls_threads = 20;
3078 num_ps_stack_entries = 42;
3079 num_vs_stack_entries = 42;
3080 num_gs_stack_entries = 42;
3081 num_es_stack_entries = 42;
3082 num_hs_stack_entries = 42;
3083 num_ls_stack_entries = 42;
3084 break;
3085 case CHIP_CAICOS:
3086 num_ps_threads = 96;
3087 num_vs_threads = 10;
3088 num_gs_threads = 10;
3089 num_es_threads = 10;
3090 num_hs_threads = 10;
3091 num_ls_threads = 10;
3092 num_ps_stack_entries = 42;
3093 num_vs_stack_entries = 42;
3094 num_gs_stack_entries = 42;
3095 num_es_stack_entries = 42;
3096 num_hs_stack_entries = 42;
3097 num_ls_stack_entries = 42;
3098 break;
3099 }
3100
3101 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
3102 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
3103 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
3104 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
3105
3106 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
3107 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3108
3109 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
3110 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
3111 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3112
3113 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
3114 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
3115 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3116
3117 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
3118 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
3119 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3120
3121 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
3122 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
3123 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3124
3125 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
3126 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
3127
3128 /* remove LS/HS from one SIMD for hw workaround */
3129 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
3130 r600_store_value(cb, 0xffffffff);
3131 r600_store_value(cb, 0xffffffff);
3132 r600_store_value(cb, 0xfffffffe);
3133
3134 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
3135 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
3136
3137 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
3138 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3139 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3140 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3141 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3142 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3143 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3144
3145 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3146 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3147 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3148 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3149 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3150
3151 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
3152 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3153 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
3154 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3155 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3156 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3157 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3158 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3159 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
3160 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3161 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3162 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3163 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3164 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
3165
3166 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
3167
3168 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
3169
3170 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
3171 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3172 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
3173
3174 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
3175
3176 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
3177
3178 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
3179 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3180 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3181
3182 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
3183 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
3184
3185 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
3186 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3187 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3188 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3189
3190 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
3191 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3192 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3193
3194 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
3195 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3196 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3197
3198 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3199 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3200 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3201 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3202 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
3203 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3204 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3205
3206 /* to avoid GPU doing any preloading of constant from random address */
3207 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
3208 for (i = 0; i < 16; i++)
3209 r600_store_value(cb, 0);
3210
3211 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
3212 for (i = 0; i < 16; i++)
3213 r600_store_value(cb, 0);
3214
3215 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
3216 for (i = 0; i < 16; i++)
3217 r600_store_value(cb, 0);
3218
3219 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
3220 for (i = 0; i < 16; i++)
3221 r600_store_value(cb, 0);
3222
3223 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
3224 for (i = 0; i < 16; i++)
3225 r600_store_value(cb, 0);
3226
3227 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
3228
3229 if (rctx->screen->b.has_streamout) {
3230 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3231 }
3232
3233 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
3234 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3235 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
3236 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
3237 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3238 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3239
3240 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
3241 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
3242 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
3243
3244 if (rctx->b.family == CHIP_CAICOS) {
3245 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
3246 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3247 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3248 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
3249 } else {
3250 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
3251 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3252 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3253 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
3254 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
3255 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
3256 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
3257 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
3258 }
3259
3260 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3261 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3262 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
3263 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
3264 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
3265 }
3266
3267 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3268 {
3269 struct r600_context *rctx = (struct r600_context *)ctx;
3270 struct r600_command_buffer *cb = &shader->command_buffer;
3271 struct r600_shader *rshader = &shader->shader;
3272 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
3273 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
3274 int ninterp = 0;
3275 boolean have_perspective = FALSE, have_linear = FALSE;
3276 static const unsigned spi_baryc_enable_bit[6] = {
3277 S_0286E0_PERSP_SAMPLE_ENA(1),
3278 S_0286E0_PERSP_CENTER_ENA(1),
3279 S_0286E0_PERSP_CENTROID_ENA(1),
3280 S_0286E0_LINEAR_SAMPLE_ENA(1),
3281 S_0286E0_LINEAR_CENTER_ENA(1),
3282 S_0286E0_LINEAR_CENTROID_ENA(1)
3283 };
3284 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
3285 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
3286 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3287 uint32_t spi_ps_input_cntl[32];
3288
3289 if (!cb->buf) {
3290 r600_init_command_buffer(cb, 64);
3291 } else {
3292 cb->num_dw = 0;
3293 }
3294
3295 for (i = 0; i < rshader->ninput; i++) {
3296 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3297 POSITION goes via GPRs from the SC so isn't counted */
3298 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3299 pos_index = i;
3300 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
3301 if (face_index == -1)
3302 face_index = i;
3303 }
3304 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3305 if (face_index == -1)
3306 face_index = i; /* lives in same register, same enable bit */
3307 }
3308 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
3309 fixed_pt_position_index = i;
3310 }
3311 else {
3312 ninterp++;
3313 int k = eg_get_interpolator_index(
3314 rshader->input[i].interpolate,
3315 rshader->input[i].interpolate_location);
3316 if (k >= 0) {
3317 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3318 have_perspective |= k < 3;
3319 have_linear |= !(k < 3);
3320 }
3321 }
3322
3323 sid = rshader->input[i].spi_sid;
3324
3325 if (sid) {
3326 tmp = S_028644_SEMANTIC(sid);
3327
3328 /* D3D 9 behaviour. GL is undefined */
3329 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
3330 tmp |= S_028644_DEFAULT_VAL(3);
3331
3332 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3333 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3334 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3335 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3336 tmp |= S_028644_FLAT_SHADE(1);
3337 }
3338
3339 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3340 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3341 tmp |= S_028644_PT_SPRITE_TEX(1);
3342 }
3343
3344 spi_ps_input_cntl[num++] = tmp;
3345 }
3346 }
3347
3348 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3349 r600_store_array(cb, num, spi_ps_input_cntl);
3350
3351 for (i = 0; i < rshader->noutput; i++) {
3352 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3353 z_export = 1;
3354 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3355 stencil_export = 1;
3356 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3357 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3358 mask_export = 1;
3359 }
3360 if (rshader->uses_kill)
3361 db_shader_control |= S_02880C_KILL_ENABLE(1);
3362
3363 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3364 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3365 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3366
3367 if (shader->selector->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
3368 db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
3369 S_02880C_EXEC_ON_NOOP(shader->selector->info.writes_memory);
3370 } else if (shader->selector->info.writes_memory) {
3371 db_shader_control |= S_02880C_EXEC_ON_HIER_FAIL(1);
3372 }
3373
3374 switch (rshader->ps_conservative_z) {
3375 default: /* fall through */
3376 case TGSI_FS_DEPTH_LAYOUT_ANY:
3377 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3378 break;
3379 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3380 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3381 break;
3382 case TGSI_FS_DEPTH_LAYOUT_LESS:
3383 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3384 break;
3385 }
3386
3387 exports_ps = 0;
3388 for (i = 0; i < rshader->noutput; i++) {
3389 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3390 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3391 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3392 exports_ps |= 1;
3393 }
3394
3395 num_cout = rshader->ps_export_highest + 1;
3396
3397 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3398 if (!exports_ps) {
3399 /* always at least export 1 component per pixel */
3400 exports_ps = 2;
3401 }
3402 shader->nr_ps_color_outputs = num_cout;
3403 shader->ps_color_export_mask = rshader->ps_color_export_mask;
3404 if (ninterp == 0) {
3405 ninterp = 1;
3406 have_perspective = TRUE;
3407 }
3408 if (!spi_baryc_cntl)
3409 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3410
3411 if (!have_perspective && !have_linear)
3412 have_perspective = TRUE;
3413
3414 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3415 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3416 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3417 spi_input_z = 0;
3418 if (pos_index != -1) {
3419 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3420 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3421 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3422 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3423 }
3424
3425 spi_ps_in_control_1 = 0;
3426 if (face_index != -1) {
3427 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3428 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3429 }
3430 if (fixed_pt_position_index != -1) {
3431 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3432 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3433 }
3434
3435 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3436 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3437 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3438
3439 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3440 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3441 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3442
3443 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3444 r600_store_value(cb, shader->bo->gpu_address >> 8);
3445 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3446 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3447 S_028844_PRIME_CACHE_ON_DRAW(1) |
3448 S_028844_DX10_CLAMP(1) |
3449 S_028844_STACK_SIZE(rshader->bc.nstack));
3450 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3451
3452 shader->db_shader_control = db_shader_control;
3453 shader->ps_depth_export = z_export | stencil_export | mask_export;
3454
3455 shader->sprite_coord_enable = sprite_coord_enable;
3456 if (rctx->rasterizer)
3457 shader->flatshade = rctx->rasterizer->flatshade;
3458 }
3459
3460 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3461 {
3462 struct r600_command_buffer *cb = &shader->command_buffer;
3463 struct r600_shader *rshader = &shader->shader;
3464
3465 r600_init_command_buffer(cb, 32);
3466
3467 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3468 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3469 S_028890_DX10_CLAMP(1) |
3470 S_028890_STACK_SIZE(rshader->bc.nstack));
3471 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3472 shader->bo->gpu_address >> 8);
3473 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3474 }
3475
3476 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3477 {
3478 struct r600_context *rctx = (struct r600_context *)ctx;
3479 struct r600_command_buffer *cb = &shader->command_buffer;
3480 struct r600_shader *rshader = &shader->shader;
3481 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3482 unsigned gsvs_itemsizes[4] = {
3483 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3484 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3485 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3486 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3487 };
3488
3489 r600_init_command_buffer(cb, 64);
3490
3491 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3492
3493
3494 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3495 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3496 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3497 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3498
3499 if (rctx->screen->b.info.drm_minor >= 35) {
3500 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3501 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3502 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3503 }
3504 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3505 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3506 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3507 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3508 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3509
3510 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3511 (rshader->ring_item_sizes[0]) >> 2);
3512
3513 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3514 gsvs_itemsizes[0] +
3515 gsvs_itemsizes[1] +
3516 gsvs_itemsizes[2] +
3517 gsvs_itemsizes[3]);
3518
3519 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3520 r600_store_value(cb, gsvs_itemsizes[0]);
3521 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3522 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3523
3524 /* FIXME calculate these values somehow ??? */
3525 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3526 r600_store_value(cb, 0x80); /* GS_PER_ES */
3527 r600_store_value(cb, 0x100); /* ES_PER_GS */
3528 r600_store_value(cb, 0x2); /* GS_PER_VS */
3529
3530 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3531 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3532 S_028878_DX10_CLAMP(1) |
3533 S_028878_STACK_SIZE(rshader->bc.nstack));
3534 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3535 shader->bo->gpu_address >> 8);
3536 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3537 }
3538
3539
3540 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3541 {
3542 struct r600_command_buffer *cb = &shader->command_buffer;
3543 struct r600_shader *rshader = &shader->shader;
3544 unsigned spi_vs_out_id[10] = {};
3545 unsigned i, tmp, nparams = 0;
3546
3547 for (i = 0; i < rshader->noutput; i++) {
3548 if (rshader->output[i].spi_sid) {
3549 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3550 spi_vs_out_id[nparams / 4] |= tmp;
3551 nparams++;
3552 }
3553 }
3554
3555 r600_init_command_buffer(cb, 32);
3556
3557 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3558 for (i = 0; i < 10; i++) {
3559 r600_store_value(cb, spi_vs_out_id[i]);
3560 }
3561
3562 /* Certain attributes (position, psize, etc.) don't count as params.
3563 * VS is required to export at least one param and r600_shader_from_tgsi()
3564 * takes care of adding a dummy export.
3565 */
3566 if (nparams < 1)
3567 nparams = 1;
3568
3569 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3570 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3571 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3572 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3573 S_028860_DX10_CLAMP(1) |
3574 S_028860_STACK_SIZE(rshader->bc.nstack));
3575 if (rshader->vs_position_window_space) {
3576 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3577 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3578 } else {
3579 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3580 S_028818_VTX_W0_FMT(1) |
3581 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3582 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3583 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3584
3585 }
3586 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3587 shader->bo->gpu_address >> 8);
3588 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3589
3590 shader->pa_cl_vs_out_cntl =
3591 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->cc_dist_mask & 0x0F) != 0) |
3592 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->cc_dist_mask & 0xF0) != 0) |
3593 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3594 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3595 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3596 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3597 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3598 }
3599
3600 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3601 {
3602 struct r600_command_buffer *cb = &shader->command_buffer;
3603 struct r600_shader *rshader = &shader->shader;
3604
3605 r600_init_command_buffer(cb, 32);
3606 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3607 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3608 S_0288BC_DX10_CLAMP(1) |
3609 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3610 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3611 shader->bo->gpu_address >> 8);
3612 }
3613
3614 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3615 {
3616 struct r600_command_buffer *cb = &shader->command_buffer;
3617 struct r600_shader *rshader = &shader->shader;
3618
3619 r600_init_command_buffer(cb, 32);
3620 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3621 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3622 S_0288D4_DX10_CLAMP(1) |
3623 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3624 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3625 shader->bo->gpu_address >> 8);
3626 }
3627 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3628 {
3629 struct pipe_blend_state blend;
3630
3631 memset(&blend, 0, sizeof(blend));
3632 blend.independent_blend_enable = true;
3633 blend.rt[0].colormask = 0xf;
3634 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3635 }
3636
3637 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3638 {
3639 struct pipe_blend_state blend;
3640 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3641 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3642
3643 memset(&blend, 0, sizeof(blend));
3644 blend.independent_blend_enable = true;
3645 blend.rt[0].colormask = 0xf;
3646 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3647 }
3648
3649 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3650 {
3651 struct pipe_blend_state blend;
3652 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3653
3654 memset(&blend, 0, sizeof(blend));
3655 blend.independent_blend_enable = true;
3656 blend.rt[0].colormask = 0xf;
3657 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3658 }
3659
3660 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3661 {
3662 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3663
3664 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3665 }
3666
3667 void evergreen_update_db_shader_control(struct r600_context * rctx)
3668 {
3669 bool dual_export;
3670 unsigned db_shader_control;
3671
3672 if (!rctx->ps_shader) {
3673 return;
3674 }
3675
3676 dual_export = rctx->framebuffer.export_16bpc &&
3677 !rctx->ps_shader->current->ps_depth_export;
3678
3679 db_shader_control = rctx->ps_shader->current->db_shader_control |
3680 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3681 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3682 V_02880C_EXPORT_DB_FULL) |
3683 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3684
3685 /* When alpha test is enabled we can't trust the hw to make the proper
3686 * decision on the order in which ztest should be run related to fragment
3687 * shader execution.
3688 *
3689 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3690 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3691 * execution and thus after alpha test so if discarded by the alpha test
3692 * the z value is not written.
3693 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3694 * get a hang unless you flush the DB in between. For now just use
3695 * LATE_Z.
3696 */
3697 if (rctx->alphatest_state.sx_alpha_test_control || rctx->ps_shader->info.writes_memory) {
3698 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3699 } else {
3700 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3701 }
3702
3703 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3704 rctx->db_misc_state.db_shader_control = db_shader_control;
3705 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3706 }
3707 }
3708
3709 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3710 struct pipe_resource *dst,
3711 unsigned dst_level,
3712 unsigned dst_x,
3713 unsigned dst_y,
3714 unsigned dst_z,
3715 struct pipe_resource *src,
3716 unsigned src_level,
3717 unsigned src_x,
3718 unsigned src_y,
3719 unsigned src_z,
3720 unsigned copy_height,
3721 unsigned pitch,
3722 unsigned bpp)
3723 {
3724 struct radeon_cmdbuf *cs = rctx->b.dma.cs;
3725 struct r600_texture *rsrc = (struct r600_texture*)src;
3726 struct r600_texture *rdst = (struct r600_texture*)dst;
3727 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3728 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3729 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3730 uint64_t base, addr;
3731
3732 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3733 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3734 assert(dst_mode != src_mode);
3735
3736 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3737 if (util_format_has_depth(util_format_description(src->format)))
3738 non_disp_tiling = 1;
3739
3740 y = 0;
3741 sub_cmd = EG_DMA_COPY_TILED;
3742 lbpp = util_logbase2(bpp);
3743 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3744 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3745
3746 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
3747 /* T2L */
3748 array_mode = evergreen_array_mode(src_mode);
3749 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
3750 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3751 /* linear height must be the same as the slice tile max height, it's ok even
3752 * if the linear destination/source have smaller heigh as the size of the
3753 * dma packet will be using the copy_height which is always smaller or equal
3754 * to the linear height
3755 */
3756 height = u_minify(rsrc->resource.b.b.height0, src_level);
3757 detile = 1;
3758 x = src_x;
3759 y = src_y;
3760 z = src_z;
3761 base = rsrc->surface.u.legacy.level[src_level].offset;
3762 addr = rdst->surface.u.legacy.level[dst_level].offset;
3763 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3764 addr += dst_y * pitch + dst_x * bpp;
3765 bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh);
3766 bank_w = eg_bank_wh(rsrc->surface.u.legacy.bankw);
3767 mt_aspect = eg_macro_tile_aspect(rsrc->surface.u.legacy.mtilea);
3768 tile_split = eg_tile_split(rsrc->surface.u.legacy.tile_split);
3769 base += rsrc->resource.gpu_address;
3770 addr += rdst->resource.gpu_address;
3771 } else {
3772 /* L2T */
3773 array_mode = evergreen_array_mode(dst_mode);
3774 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
3775 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3776 /* linear height must be the same as the slice tile max height, it's ok even
3777 * if the linear destination/source have smaller heigh as the size of the
3778 * dma packet will be using the copy_height which is always smaller or equal
3779 * to the linear height
3780 */
3781 height = u_minify(rdst->resource.b.b.height0, dst_level);
3782 detile = 0;
3783 x = dst_x;
3784 y = dst_y;
3785 z = dst_z;
3786 base = rdst->surface.u.legacy.level[dst_level].offset;
3787 addr = rsrc->surface.u.legacy.level[src_level].offset;
3788 addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z;
3789 addr += src_y * pitch + src_x * bpp;
3790 bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh);
3791 bank_w = eg_bank_wh(rdst->surface.u.legacy.bankw);
3792 mt_aspect = eg_macro_tile_aspect(rdst->surface.u.legacy.mtilea);
3793 tile_split = eg_tile_split(rdst->surface.u.legacy.tile_split);
3794 base += rdst->resource.gpu_address;
3795 addr += rsrc->resource.gpu_address;
3796 }
3797
3798 size = (copy_height * pitch) / 4;
3799 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3800 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
3801
3802 for (i = 0; i < ncopy; i++) {
3803 cheight = copy_height;
3804 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3805 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3806 }
3807 size = (cheight * pitch) / 4;
3808 /* emit reloc before writing cs so that cs is always in consistent state */
3809 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3810 RADEON_USAGE_READ, 0);
3811 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3812 RADEON_USAGE_WRITE, 0);
3813 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size));
3814 radeon_emit(cs, base >> 8);
3815 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
3816 (lbpp << 24) | (bank_h << 21) |
3817 (bank_w << 18) | (mt_aspect << 16));
3818 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
3819 radeon_emit(cs, (slice_tile_max << 0));
3820 radeon_emit(cs, (x << 0) | (z << 18));
3821 radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28));
3822 radeon_emit(cs, addr & 0xfffffffc);
3823 radeon_emit(cs, (addr >> 32UL) & 0xff);
3824 copy_height -= cheight;
3825 addr += cheight * pitch;
3826 y += cheight;
3827 }
3828 }
3829
3830 static void evergreen_dma_copy(struct pipe_context *ctx,
3831 struct pipe_resource *dst,
3832 unsigned dst_level,
3833 unsigned dstx, unsigned dsty, unsigned dstz,
3834 struct pipe_resource *src,
3835 unsigned src_level,
3836 const struct pipe_box *src_box)
3837 {
3838 struct r600_context *rctx = (struct r600_context *)ctx;
3839 struct r600_texture *rsrc = (struct r600_texture*)src;
3840 struct r600_texture *rdst = (struct r600_texture*)dst;
3841 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3842 unsigned src_w, dst_w;
3843 unsigned src_x, src_y;
3844 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3845
3846 if (rctx->b.dma.cs == NULL) {
3847 goto fallback;
3848 }
3849
3850 if (rctx->cmd_buf_is_compute) {
3851 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
3852 rctx->cmd_buf_is_compute = false;
3853 }
3854
3855 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3856 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3857 return;
3858 }
3859
3860 if (src_box->depth > 1 ||
3861 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3862 dstz, rsrc, src_level, src_box))
3863 goto fallback;
3864
3865 src_x = util_format_get_nblocksx(src->format, src_box->x);
3866 dst_x = util_format_get_nblocksx(src->format, dst_x);
3867 src_y = util_format_get_nblocksy(src->format, src_box->y);
3868 dst_y = util_format_get_nblocksy(src->format, dst_y);
3869
3870 bpp = rdst->surface.bpe;
3871 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
3872 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
3873 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
3874 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
3875 copy_height = src_box->height / rsrc->surface.blk_h;
3876
3877 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3878 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3879
3880 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3881 /* FIXME evergreen can do partial blit */
3882 goto fallback;
3883 }
3884 /* the x test here are currently useless (because we don't support partial blit)
3885 * but keep them around so we don't forget about those
3886 */
3887 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3888 goto fallback;
3889 }
3890
3891 /* 128 bpp surfaces require non_disp_tiling for both
3892 * tiled and linear buffers on cayman. However, async
3893 * DMA only supports it on the tiled side. As such
3894 * the tile order is backwards after a L2T/T2L packet.
3895 */
3896 if ((rctx->b.chip_class == CAYMAN) &&
3897 (src_mode != dst_mode) &&
3898 (util_format_get_blocksize(src->format) >= 16)) {
3899 goto fallback;
3900 }
3901
3902 if (src_mode == dst_mode) {
3903 uint64_t dst_offset, src_offset;
3904 /* simple dma blit would do NOTE code here assume :
3905 * src_box.x/y == 0
3906 * dst_x/y == 0
3907 * dst_pitch == src_pitch
3908 */
3909 src_offset= rsrc->surface.u.legacy.level[src_level].offset;
3910 src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
3911 src_offset += src_y * src_pitch + src_x * bpp;
3912 dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
3913 dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3914 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3915 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3916 src_box->height * src_pitch);
3917 } else {
3918 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3919 src, src_level, src_x, src_y, src_box->z,
3920 copy_height, dst_pitch, bpp);
3921 }
3922 return;
3923
3924 fallback:
3925 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3926 src, src_level, src_box);
3927 }
3928
3929 static void evergreen_set_tess_state(struct pipe_context *ctx,
3930 const float default_outer_level[4],
3931 const float default_inner_level[2])
3932 {
3933 struct r600_context *rctx = (struct r600_context *)ctx;
3934
3935 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3936 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3937 rctx->driver_consts[PIPE_SHADER_TESS_CTRL].tcs_default_levels_dirty = true;
3938 }
3939
3940 static void evergreen_setup_immed_buffer(struct r600_context *rctx,
3941 struct r600_image_view *rview,
3942 enum pipe_format pformat)
3943 {
3944 struct r600_screen *rscreen = (struct r600_screen *)rctx->b.b.screen;
3945 uint32_t immed_size = rscreen->b.info.max_se * 256 * 64 * util_format_get_blocksize(pformat);
3946 struct eg_buf_res_params buf_params;
3947 bool skip_reloc = false;
3948 struct r600_resource *resource = (struct r600_resource *)rview->base.resource;
3949 if (!resource->immed_buffer) {
3950 eg_resource_alloc_immed(&rscreen->b, resource, immed_size);
3951 }
3952
3953 memset(&buf_params, 0, sizeof(buf_params));
3954 buf_params.pipe_format = pformat;
3955 buf_params.size = resource->immed_buffer->b.b.width0;
3956 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
3957 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
3958 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
3959 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
3960 buf_params.uncached = 1;
3961 evergreen_fill_buffer_resource_words(rctx, &resource->immed_buffer->b.b,
3962 &buf_params, &skip_reloc,
3963 rview->immed_resource_words);
3964 }
3965
3966 static void evergreen_set_hw_atomic_buffers(struct pipe_context *ctx,
3967 unsigned start_slot,
3968 unsigned count,
3969 const struct pipe_shader_buffer *buffers)
3970 {
3971 struct r600_context *rctx = (struct r600_context *)ctx;
3972 struct r600_atomic_buffer_state *astate;
3973 unsigned i, idx;
3974
3975 astate = &rctx->atomic_buffer_state;
3976
3977 /* we'd probably like to expand this to 8 later so put the logic in */
3978 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
3979 const struct pipe_shader_buffer *buf;
3980 struct pipe_shader_buffer *abuf;
3981
3982 abuf = &astate->buffer[i];
3983
3984 if (!buffers || !buffers[idx].buffer) {
3985 pipe_resource_reference(&abuf->buffer, NULL);
3986 astate->enabled_mask &= ~(1 << i);
3987 continue;
3988 }
3989 buf = &buffers[idx];
3990
3991 pipe_resource_reference(&abuf->buffer, buf->buffer);
3992 abuf->buffer_offset = buf->buffer_offset;
3993 abuf->buffer_size = buf->buffer_size;
3994 astate->enabled_mask |= (1 << i);
3995 }
3996 }
3997
3998 static void evergreen_set_shader_buffers(struct pipe_context *ctx,
3999 enum pipe_shader_type shader, unsigned start_slot,
4000 unsigned count,
4001 const struct pipe_shader_buffer *buffers)
4002 {
4003 struct r600_context *rctx = (struct r600_context *)ctx;
4004 struct r600_image_state *istate = NULL;
4005 struct r600_image_view *rview;
4006 struct r600_tex_color_info color;
4007 struct eg_buf_res_params buf_params;
4008 struct r600_resource *resource;
4009 unsigned i, idx;
4010 unsigned old_mask;
4011
4012 if (shader != PIPE_SHADER_FRAGMENT &&
4013 shader != PIPE_SHADER_COMPUTE && count == 0)
4014 return;
4015
4016 if (shader == PIPE_SHADER_FRAGMENT)
4017 istate = &rctx->fragment_buffers;
4018 else if (shader == PIPE_SHADER_COMPUTE)
4019 istate = &rctx->compute_buffers;
4020
4021 old_mask = istate->enabled_mask;
4022 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4023 const struct pipe_shader_buffer *buf;
4024 unsigned res_type;
4025
4026 rview = &istate->views[i];
4027
4028 if (!buffers || !buffers[idx].buffer) {
4029 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
4030 istate->enabled_mask &= ~(1 << i);
4031 continue;
4032 }
4033
4034 buf = &buffers[idx];
4035 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, buf->buffer);
4036
4037 resource = (struct r600_resource *)rview->base.resource;
4038
4039 evergreen_setup_immed_buffer(rctx, rview, PIPE_FORMAT_R32_UINT);
4040
4041 color.offset = 0;
4042 color.view = 0;
4043 evergreen_set_color_surface_buffer(rctx, resource,
4044 PIPE_FORMAT_R32_UINT,
4045 buf->buffer_offset,
4046 buf->buffer_offset + buf->buffer_size,
4047 &color);
4048
4049 res_type = V_028C70_BUFFER;
4050
4051 rview->cb_color_base = color.offset;
4052 rview->cb_color_dim = color.dim;
4053 rview->cb_color_info = color.info |
4054 S_028C70_RAT(1) |
4055 S_028C70_RESOURCE_TYPE(res_type);
4056 rview->cb_color_pitch = color.pitch;
4057 rview->cb_color_slice = color.slice;
4058 rview->cb_color_view = color.view;
4059 rview->cb_color_attrib = color.attrib;
4060 rview->cb_color_fmask = color.fmask;
4061 rview->cb_color_fmask_slice = color.fmask_slice;
4062
4063 memset(&buf_params, 0, sizeof(buf_params));
4064 buf_params.pipe_format = PIPE_FORMAT_R32_UINT;
4065 buf_params.offset = buf->buffer_offset;
4066 buf_params.size = buf->buffer_size;
4067 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
4068 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
4069 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
4070 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
4071 buf_params.force_swizzle = true;
4072 buf_params.uncached = 1;
4073 buf_params.size_in_bytes = true;
4074 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4075 &buf_params,
4076 &rview->skip_mip_address_reloc,
4077 rview->resource_words);
4078
4079 istate->enabled_mask |= (1 << i);
4080 }
4081
4082 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
4083
4084 if (old_mask != istate->enabled_mask)
4085 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4086
4087 /* construct the target mask */
4088 if (rctx->cb_misc_state.buffer_rat_enabled_mask != istate->enabled_mask) {
4089 rctx->cb_misc_state.buffer_rat_enabled_mask = istate->enabled_mask;
4090 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4091 }
4092
4093 if (shader == PIPE_SHADER_FRAGMENT)
4094 r600_mark_atom_dirty(rctx, &istate->atom);
4095 }
4096
4097 static void evergreen_set_shader_images(struct pipe_context *ctx,
4098 enum pipe_shader_type shader, unsigned start_slot,
4099 unsigned count,
4100 const struct pipe_image_view *images)
4101 {
4102 struct r600_context *rctx = (struct r600_context *)ctx;
4103 unsigned i;
4104 struct r600_image_view *rview;
4105 struct pipe_resource *image;
4106 struct r600_resource *resource;
4107 struct r600_tex_color_info color;
4108 struct eg_buf_res_params buf_params;
4109 struct eg_tex_res_params tex_params;
4110 unsigned old_mask;
4111 struct r600_image_state *istate = NULL;
4112 int idx;
4113 if (shader != PIPE_SHADER_FRAGMENT && shader != PIPE_SHADER_COMPUTE && count == 0)
4114 return;
4115
4116 if (shader == PIPE_SHADER_FRAGMENT)
4117 istate = &rctx->fragment_images;
4118 else if (shader == PIPE_SHADER_COMPUTE)
4119 istate = &rctx->compute_images;
4120
4121 assert (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE);
4122
4123 old_mask = istate->enabled_mask;
4124 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4125 unsigned res_type;
4126 const struct pipe_image_view *iview;
4127 rview = &istate->views[i];
4128
4129 if (!images || !images[idx].resource) {
4130 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
4131 istate->enabled_mask &= ~(1 << i);
4132 istate->compressed_colortex_mask &= ~(1 << i);
4133 istate->compressed_depthtex_mask &= ~(1 << i);
4134 continue;
4135 }
4136
4137 iview = &images[idx];
4138 image = iview->resource;
4139 resource = (struct r600_resource *)image;
4140
4141 r600_context_add_resource_size(ctx, image);
4142
4143 rview->base = *iview;
4144 rview->base.resource = NULL;
4145 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, image);
4146
4147 evergreen_setup_immed_buffer(rctx, rview, iview->format);
4148
4149 bool is_buffer = image->target == PIPE_BUFFER;
4150 struct r600_texture *rtex = (struct r600_texture *)image;
4151 if (!is_buffer & rtex->db_compatible)
4152 istate->compressed_depthtex_mask |= 1 << i;
4153 else
4154 istate->compressed_depthtex_mask &= ~(1 << i);
4155
4156 if (!is_buffer && rtex->cmask.size)
4157 istate->compressed_colortex_mask |= 1 << i;
4158 else
4159 istate->compressed_colortex_mask &= ~(1 << i);
4160 if (!is_buffer) {
4161
4162 evergreen_set_color_surface_common(rctx, rtex,
4163 iview->u.tex.level,
4164 iview->u.tex.first_layer,
4165 iview->u.tex.last_layer,
4166 iview->format,
4167 &color);
4168 color.dim = S_028C78_WIDTH_MAX(u_minify(image->width0, iview->u.tex.level) - 1) |
4169 S_028C78_HEIGHT_MAX(u_minify(image->height0, iview->u.tex.level) - 1);
4170 } else {
4171 color.offset = 0;
4172 color.view = 0;
4173 evergreen_set_color_surface_buffer(rctx, resource,
4174 iview->format,
4175 iview->u.buf.offset,
4176 iview->u.buf.size,
4177 &color);
4178 }
4179
4180 switch (image->target) {
4181 case PIPE_BUFFER:
4182 res_type = V_028C70_BUFFER;
4183 break;
4184 case PIPE_TEXTURE_1D:
4185 res_type = V_028C70_TEXTURE1D;
4186 break;
4187 case PIPE_TEXTURE_1D_ARRAY:
4188 res_type = V_028C70_TEXTURE1DARRAY;
4189 break;
4190 case PIPE_TEXTURE_2D:
4191 case PIPE_TEXTURE_RECT:
4192 res_type = V_028C70_TEXTURE2D;
4193 break;
4194 case PIPE_TEXTURE_3D:
4195 res_type = V_028C70_TEXTURE3D;
4196 break;
4197 case PIPE_TEXTURE_2D_ARRAY:
4198 case PIPE_TEXTURE_CUBE:
4199 case PIPE_TEXTURE_CUBE_ARRAY:
4200 res_type = V_028C70_TEXTURE2DARRAY;
4201 break;
4202 default:
4203 assert(0);
4204 res_type = 0;
4205 break;
4206 }
4207
4208 rview->cb_color_base = color.offset;
4209 rview->cb_color_dim = color.dim;
4210 rview->cb_color_info = color.info |
4211 S_028C70_RAT(1) |
4212 S_028C70_RESOURCE_TYPE(res_type);
4213 rview->cb_color_pitch = color.pitch;
4214 rview->cb_color_slice = color.slice;
4215 rview->cb_color_view = color.view;
4216 rview->cb_color_attrib = color.attrib;
4217 rview->cb_color_fmask = color.fmask;
4218 rview->cb_color_fmask_slice = color.fmask_slice;
4219
4220 if (image->target != PIPE_BUFFER) {
4221 memset(&tex_params, 0, sizeof(tex_params));
4222 tex_params.pipe_format = iview->format;
4223 tex_params.force_level = 0;
4224 tex_params.width0 = image->width0;
4225 tex_params.height0 = image->height0;
4226 tex_params.first_level = iview->u.tex.level;
4227 tex_params.last_level = iview->u.tex.level;
4228 tex_params.first_layer = iview->u.tex.first_layer;
4229 tex_params.last_layer = iview->u.tex.last_layer;
4230 tex_params.target = image->target;
4231 tex_params.swizzle[0] = PIPE_SWIZZLE_X;
4232 tex_params.swizzle[1] = PIPE_SWIZZLE_Y;
4233 tex_params.swizzle[2] = PIPE_SWIZZLE_Z;
4234 tex_params.swizzle[3] = PIPE_SWIZZLE_W;
4235 evergreen_fill_tex_resource_words(rctx, &resource->b.b, &tex_params,
4236 &rview->skip_mip_address_reloc,
4237 rview->resource_words);
4238
4239 } else {
4240 memset(&buf_params, 0, sizeof(buf_params));
4241 buf_params.pipe_format = iview->format;
4242 buf_params.size = iview->u.buf.size;
4243 buf_params.offset = iview->u.buf.offset;
4244 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
4245 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
4246 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
4247 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
4248 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4249 &buf_params,
4250 &rview->skip_mip_address_reloc,
4251 rview->resource_words);
4252 }
4253 istate->enabled_mask |= (1 << i);
4254 }
4255
4256 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
4257 istate->dirty_buffer_constants = TRUE;
4258 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
4259 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
4260 R600_CONTEXT_FLUSH_AND_INV_CB_META;
4261
4262 if (old_mask != istate->enabled_mask)
4263 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4264
4265 if (rctx->cb_misc_state.image_rat_enabled_mask != istate->enabled_mask) {
4266 rctx->cb_misc_state.image_rat_enabled_mask = istate->enabled_mask;
4267 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4268 }
4269
4270 if (shader == PIPE_SHADER_FRAGMENT)
4271 r600_mark_atom_dirty(rctx, &istate->atom);
4272 }
4273
4274 static void evergreen_get_pipe_constant_buffer(struct r600_context *rctx,
4275 enum pipe_shader_type shader, uint slot,
4276 struct pipe_constant_buffer *cbuf)
4277 {
4278 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
4279 struct pipe_constant_buffer *cb;
4280 cbuf->user_buffer = NULL;
4281
4282 cb = &state->cb[slot];
4283
4284 cbuf->buffer_size = cb->buffer_size;
4285 pipe_resource_reference(&cbuf->buffer, cb->buffer);
4286 }
4287
4288 static void evergreen_get_shader_buffers(struct r600_context *rctx,
4289 enum pipe_shader_type shader,
4290 uint start_slot, uint count,
4291 struct pipe_shader_buffer *sbuf)
4292 {
4293 assert(shader == PIPE_SHADER_COMPUTE);
4294 int idx, i;
4295 struct r600_image_state *istate = &rctx->compute_buffers;
4296 struct r600_image_view *rview;
4297
4298 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4299
4300 rview = &istate->views[i];
4301
4302 pipe_resource_reference(&sbuf[idx].buffer, rview->base.resource);
4303 if (rview->base.resource) {
4304 uint64_t rview_va = ((struct r600_resource *)rview->base.resource)->gpu_address;
4305
4306 uint64_t prog_va = rview->resource_words[0];
4307
4308 prog_va += ((uint64_t)G_030008_BASE_ADDRESS_HI(rview->resource_words[2])) << 32;
4309 prog_va -= rview_va;
4310
4311 sbuf[idx].buffer_offset = prog_va & 0xffffffff;
4312 sbuf[idx].buffer_size = rview->resource_words[1] + 1;;
4313 } else {
4314 sbuf[idx].buffer_offset = 0;
4315 sbuf[idx].buffer_size = 0;
4316 }
4317 }
4318 }
4319
4320 static void evergreen_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
4321 {
4322 struct r600_context *rctx = (struct r600_context *)ctx;
4323 st->saved_compute = rctx->cs_shader_state.shader;
4324
4325 /* save constant buffer 0 */
4326 evergreen_get_pipe_constant_buffer(rctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
4327 /* save ssbo 0 */
4328 evergreen_get_shader_buffers(rctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
4329 }
4330
4331
4332 void evergreen_init_state_functions(struct r600_context *rctx)
4333 {
4334 unsigned id = 1;
4335 unsigned i;
4336 /* !!!
4337 * To avoid GPU lockup registers must be emitted in a specific order
4338 * (no kidding ...). The order below is important and have been
4339 * partially inferred from analyzing fglrx command stream.
4340 *
4341 * Don't reorder atom without carefully checking the effect (GPU lockup
4342 * or piglit regression).
4343 * !!!
4344 */
4345 if (rctx->b.chip_class == EVERGREEN) {
4346 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
4347 rctx->config_state.dyn_gpr_enabled = true;
4348 }
4349 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
4350 r600_init_atom(rctx, &rctx->fragment_images.atom, id++, evergreen_emit_fragment_image_state, 0);
4351 r600_init_atom(rctx, &rctx->compute_images.atom, id++, evergreen_emit_compute_image_state, 0);
4352 r600_init_atom(rctx, &rctx->fragment_buffers.atom, id++, evergreen_emit_fragment_buffer_state, 0);
4353 r600_init_atom(rctx, &rctx->compute_buffers.atom, id++, evergreen_emit_compute_buffer_state, 0);
4354 /* shader const */
4355 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
4356 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
4357 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
4358 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
4359 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
4360 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
4361 /* shader program */
4362 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
4363 /* sampler */
4364 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
4365 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
4366 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
4367 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
4368 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
4369 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
4370 /* resources */
4371 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
4372 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
4373 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
4374 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
4375 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
4376 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
4377 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
4378 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
4379
4380 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
4381
4382 if (rctx->b.chip_class == EVERGREEN) {
4383 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
4384 } else {
4385 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
4386 }
4387 rctx->sample_mask.sample_mask = ~0;
4388
4389 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
4390 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
4391 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
4392 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
4393 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
4394 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
4395 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
4396 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
4397 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
4398 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9);
4399 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
4400 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
4401 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
4402 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
4403 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
4404 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
4405 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
4406 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
4407 for (i = 0; i < EG_NUM_HW_STAGES; i++)
4408 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
4409 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
4410 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
4411
4412 rctx->b.b.create_blend_state = evergreen_create_blend_state;
4413 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
4414 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
4415 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
4416 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
4417 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
4418 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
4419 rctx->b.b.set_min_samples = evergreen_set_min_samples;
4420 rctx->b.b.set_tess_state = evergreen_set_tess_state;
4421 rctx->b.b.set_hw_atomic_buffers = evergreen_set_hw_atomic_buffers;
4422 rctx->b.b.set_shader_images = evergreen_set_shader_images;
4423 rctx->b.b.set_shader_buffers = evergreen_set_shader_buffers;
4424 if (rctx->b.chip_class == EVERGREEN)
4425 rctx->b.b.get_sample_position = evergreen_get_sample_position;
4426 else
4427 rctx->b.b.get_sample_position = cayman_get_sample_position;
4428 rctx->b.dma_copy = evergreen_dma_copy;
4429 rctx->b.save_qbo_state = evergreen_save_qbo_state;
4430
4431 evergreen_init_compute_state_functions(rctx);
4432 }
4433
4434 /**
4435 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
4436 *
4437 * The information about LDS and other non-compile-time parameters is then
4438 * written to the const buffer.
4439
4440 * const buffer contains -
4441 * uint32_t input_patch_size
4442 * uint32_t input_vertex_size
4443 * uint32_t num_tcs_input_cp
4444 * uint32_t num_tcs_output_cp;
4445 * uint32_t output_patch_size
4446 * uint32_t output_vertex_size
4447 * uint32_t output_patch0_offset
4448 * uint32_t perpatch_output_offset
4449 * and the same constbuf is bound to LS/HS/VS(ES).
4450 */
4451 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
4452 {
4453 struct pipe_constant_buffer constbuf = {0};
4454 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
4455 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
4456 unsigned num_tcs_input_cp = info->vertices_per_patch;
4457 unsigned num_tcs_outputs;
4458 unsigned num_tcs_output_cp;
4459 unsigned num_tcs_patch_outputs;
4460 unsigned num_tcs_inputs;
4461 unsigned input_vertex_size, output_vertex_size;
4462 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
4463 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
4464 uint32_t values[8];
4465 unsigned num_waves;
4466 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
4467 unsigned wave_divisor = (16 * num_pipes);
4468
4469 *num_patches = 1;
4470
4471 if (!rctx->tes_shader) {
4472 rctx->lds_alloc = 0;
4473 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4474 R600_LDS_INFO_CONST_BUFFER, NULL);
4475 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4476 R600_LDS_INFO_CONST_BUFFER, NULL);
4477 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4478 R600_LDS_INFO_CONST_BUFFER, NULL);
4479 return;
4480 }
4481
4482 if (rctx->lds_alloc != 0 &&
4483 rctx->last_ls == ls &&
4484 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
4485 rctx->last_tcs == tcs)
4486 return;
4487
4488 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
4489
4490 if (rctx->tcs_shader) {
4491 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
4492 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
4493 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
4494 } else {
4495 num_tcs_outputs = num_tcs_inputs;
4496 num_tcs_output_cp = num_tcs_input_cp;
4497 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
4498 }
4499
4500 /* size in bytes */
4501 input_vertex_size = num_tcs_inputs * 16;
4502 output_vertex_size = num_tcs_outputs * 16;
4503
4504 input_patch_size = num_tcs_input_cp * input_vertex_size;
4505
4506 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
4507 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
4508
4509 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
4510 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
4511
4512 lds_size = output_patch0_offset + output_patch_size * *num_patches;
4513
4514 values[0] = input_patch_size;
4515 values[1] = input_vertex_size;
4516 values[2] = num_tcs_input_cp;
4517 values[3] = num_tcs_output_cp;
4518
4519 values[4] = output_patch_size;
4520 values[5] = output_vertex_size;
4521 values[6] = output_patch0_offset;
4522 values[7] = perpatch_output_offset;
4523
4524 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
4525 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
4526 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
4527
4528 rctx->lds_alloc = (lds_size | (num_waves << 14));
4529
4530 rctx->last_ls = ls;
4531 rctx->last_tcs = tcs;
4532 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
4533
4534 constbuf.user_buffer = values;
4535 constbuf.buffer_size = 8 * 4;
4536
4537 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4538 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4539 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4540 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4541 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4542 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4543 pipe_resource_reference(&constbuf.buffer, NULL);
4544 }
4545
4546 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
4547 const struct pipe_draw_info *info,
4548 unsigned num_patches)
4549 {
4550 unsigned num_output_cp;
4551
4552 if (!rctx->tes_shader)
4553 return 0;
4554
4555 num_output_cp = rctx->tcs_shader ?
4556 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
4557 info->vertices_per_patch;
4558
4559 return S_028B58_NUM_PATCHES(num_patches) |
4560 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
4561 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
4562 }
4563
4564 void evergreen_set_ls_hs_config(struct r600_context *rctx,
4565 struct radeon_cmdbuf *cs,
4566 uint32_t ls_hs_config)
4567 {
4568 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
4569 }
4570
4571 void evergreen_set_lds_alloc(struct r600_context *rctx,
4572 struct radeon_cmdbuf *cs,
4573 uint32_t lds_alloc)
4574 {
4575 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
4576 }
4577
4578 /* on evergreen if you are running tessellation you need to disable dynamic
4579 GPRs to workaround a hardware bug.*/
4580 bool evergreen_adjust_gprs(struct r600_context *rctx)
4581 {
4582 unsigned num_gprs[EG_NUM_HW_STAGES];
4583 unsigned def_gprs[EG_NUM_HW_STAGES];
4584 unsigned cur_gprs[EG_NUM_HW_STAGES];
4585 unsigned new_gprs[EG_NUM_HW_STAGES];
4586 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
4587 unsigned max_gprs;
4588 unsigned i;
4589 unsigned total_gprs;
4590 unsigned tmp[3];
4591 bool rework = false, set_default = false, set_dirty = false;
4592 max_gprs = 0;
4593 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4594 def_gprs[i] = rctx->default_gprs[i];
4595 max_gprs += def_gprs[i];
4596 }
4597 max_gprs += def_num_clause_temp_gprs * 2;
4598
4599 /* if we have no TESS and dyn gpr is enabled then do nothing. */
4600 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
4601 if (rctx->config_state.dyn_gpr_enabled)
4602 return true;
4603
4604 /* transition back to dyn gpr enabled state */
4605 rctx->config_state.dyn_gpr_enabled = true;
4606 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4607 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4608 return true;
4609 }
4610
4611
4612 /* gather required shader gprs */
4613 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4614 if (rctx->hw_shader_stages[i].shader)
4615 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
4616 else
4617 num_gprs[i] = 0;
4618 }
4619
4620 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4621 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4622 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4623 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4624 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4625 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4626
4627 total_gprs = 0;
4628 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4629 new_gprs[i] = num_gprs[i];
4630 total_gprs += num_gprs[i];
4631 }
4632
4633 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
4634 return false;
4635
4636 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4637 if (new_gprs[i] > cur_gprs[i]) {
4638 rework = true;
4639 break;
4640 }
4641 }
4642
4643 if (rctx->config_state.dyn_gpr_enabled) {
4644 set_dirty = true;
4645 rctx->config_state.dyn_gpr_enabled = false;
4646 }
4647
4648 if (rework) {
4649 set_default = true;
4650 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4651 if (new_gprs[i] > def_gprs[i])
4652 set_default = false;
4653 }
4654
4655 if (set_default) {
4656 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4657 new_gprs[i] = def_gprs[i];
4658 }
4659 } else {
4660 unsigned ps_value = max_gprs;
4661
4662 ps_value -= (def_num_clause_temp_gprs * 2);
4663 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
4664 ps_value -= new_gprs[i];
4665
4666 new_gprs[R600_HW_STAGE_PS] = ps_value;
4667 }
4668
4669 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
4670 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
4671 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
4672
4673 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
4674 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
4675
4676 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
4677 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
4678
4679 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
4680 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
4681 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
4682 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
4683 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
4684 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
4685 set_dirty = true;
4686 }
4687 }
4688
4689
4690 if (set_dirty) {
4691 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4692 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4693 }
4694 return true;
4695 }
4696
4697 #define AC_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
4698
4699 void eg_trace_emit(struct r600_context *rctx)
4700 {
4701 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
4702 unsigned reloc;
4703
4704 if (rctx->b.chip_class < EVERGREEN)
4705 return;
4706
4707 /* This must be done after r600_need_cs_space. */
4708 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4709 (struct r600_resource*)rctx->trace_buf, RADEON_USAGE_WRITE,
4710 RADEON_PRIO_CP_DMA);
4711
4712 rctx->trace_id++;
4713 radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rctx->trace_buf,
4714 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
4715 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
4716 radeon_emit(cs, rctx->trace_buf->gpu_address);
4717 radeon_emit(cs, rctx->trace_buf->gpu_address >> 32 | MEM_WRITE_32_BITS | MEM_WRITE_CONFIRM);
4718 radeon_emit(cs, rctx->trace_id);
4719 radeon_emit(cs, 0);
4720 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4721 radeon_emit(cs, reloc);
4722 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4723 radeon_emit(cs, AC_ENCODE_TRACE_POINT(rctx->trace_id));
4724 }
4725
4726 static void evergreen_emit_set_append_cnt(struct r600_context *rctx,
4727 struct r600_shader_atomic *atomic,
4728 struct r600_resource *resource,
4729 uint32_t pkt_flags)
4730 {
4731 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
4732 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4733 resource,
4734 RADEON_USAGE_READ,
4735 RADEON_PRIO_SHADER_RW_BUFFER);
4736 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4737 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4738
4739 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4 - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
4740
4741 radeon_emit(cs, PKT3(PKT3_SET_APPEND_CNT, 2, 0) | pkt_flags);
4742 radeon_emit(cs, (reg_val << 16) | 0x3);
4743 radeon_emit(cs, dst_offset & 0xfffffffc);
4744 radeon_emit(cs, (dst_offset >> 32) & 0xff);
4745 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4746 radeon_emit(cs, reloc);
4747 }
4748
4749 static void evergreen_emit_event_write_eos(struct r600_context *rctx,
4750 struct r600_shader_atomic *atomic,
4751 struct r600_resource *resource,
4752 uint32_t pkt_flags)
4753 {
4754 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
4755 uint32_t event = EVENT_TYPE_PS_DONE;
4756 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4757 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4758 resource,
4759 RADEON_USAGE_WRITE,
4760 RADEON_PRIO_SHADER_RW_BUFFER);
4761 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4762 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4) >> 2;
4763
4764 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4765 event = EVENT_TYPE_CS_DONE;
4766
4767 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4768 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4769 radeon_emit(cs, (dst_offset) & 0xffffffff);
4770 radeon_emit(cs, (0 << 29) | ((dst_offset >> 32) & 0xff));
4771 radeon_emit(cs, reg_val);
4772 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4773 radeon_emit(cs, reloc);
4774 }
4775
4776 static void cayman_emit_event_write_eos(struct r600_context *rctx,
4777 struct r600_shader_atomic *atomic,
4778 struct r600_resource *resource,
4779 uint32_t pkt_flags)
4780 {
4781 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
4782 uint32_t event = EVENT_TYPE_PS_DONE;
4783 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4784 resource,
4785 RADEON_USAGE_WRITE,
4786 RADEON_PRIO_SHADER_RW_BUFFER);
4787 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4788
4789 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4790 event = EVENT_TYPE_CS_DONE;
4791
4792 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4793 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4794 radeon_emit(cs, (dst_offset) & 0xffffffff);
4795 radeon_emit(cs, (1 << 29) | ((dst_offset >> 32) & 0xff));
4796 radeon_emit(cs, (atomic->hw_idx) | (1 << 16));
4797 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4798 radeon_emit(cs, reloc);
4799 }
4800
4801 /* writes count from a buffer into GDS */
4802 static void cayman_write_count_to_gds(struct r600_context *rctx,
4803 struct r600_shader_atomic *atomic,
4804 struct r600_resource *resource,
4805 uint32_t pkt_flags)
4806 {
4807 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
4808 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4809 resource,
4810 RADEON_USAGE_READ,
4811 RADEON_PRIO_SHADER_RW_BUFFER);
4812 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4813
4814 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0) | pkt_flags);
4815 radeon_emit(cs, dst_offset & 0xffffffff);
4816 radeon_emit(cs, PKT3_CP_DMA_CP_SYNC | PKT3_CP_DMA_DST_SEL(1) | ((dst_offset >> 32) & 0xff));// GDS
4817 radeon_emit(cs, atomic->hw_idx * 4);
4818 radeon_emit(cs, 0);
4819 radeon_emit(cs, PKT3_CP_DMA_CMD_DAS | 4);
4820 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4821 radeon_emit(cs, reloc);
4822 }
4823
4824 bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
4825 struct r600_pipe_shader *cs_shader,
4826 struct r600_shader_atomic *combined_atomics,
4827 uint8_t *atomic_used_mask_p)
4828 {
4829 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4830 unsigned pkt_flags = 0;
4831 uint8_t atomic_used_mask = 0;
4832 int i, j, k;
4833 bool is_compute = cs_shader ? true : false;
4834
4835 if (is_compute)
4836 pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
4837
4838 for (i = 0; i < (is_compute ? 1 : EG_NUM_HW_STAGES); i++) {
4839 uint8_t num_atomic_stage;
4840 struct r600_pipe_shader *pshader;
4841
4842 if (is_compute)
4843 pshader = cs_shader;
4844 else
4845 pshader = rctx->hw_shader_stages[i].shader;
4846 if (!pshader)
4847 continue;
4848
4849 num_atomic_stage = pshader->shader.nhwatomic_ranges;
4850 if (!num_atomic_stage)
4851 continue;
4852
4853 for (j = 0; j < num_atomic_stage; j++) {
4854 struct r600_shader_atomic *atomic = &pshader->shader.atomics[j];
4855 int natomics = atomic->end - atomic->start + 1;
4856
4857 for (k = 0; k < natomics; k++) {
4858 /* seen this in a previous stage */
4859 if (atomic_used_mask & (1u << (atomic->hw_idx + k)))
4860 continue;
4861
4862 combined_atomics[atomic->hw_idx + k].hw_idx = atomic->hw_idx + k;
4863 combined_atomics[atomic->hw_idx + k].buffer_id = atomic->buffer_id;
4864 combined_atomics[atomic->hw_idx + k].start = atomic->start + k;
4865 combined_atomics[atomic->hw_idx + k].end = combined_atomics[atomic->hw_idx + k].start + 1;
4866 atomic_used_mask |= (1u << (atomic->hw_idx + k));
4867 }
4868 }
4869 }
4870
4871 uint32_t mask = atomic_used_mask;
4872 while (mask) {
4873 unsigned atomic_index = u_bit_scan(&mask);
4874 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
4875 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
4876 assert(resource);
4877
4878 if (rctx->b.chip_class == CAYMAN)
4879 cayman_write_count_to_gds(rctx, atomic, resource, pkt_flags);
4880 else
4881 evergreen_emit_set_append_cnt(rctx, atomic, resource, pkt_flags);
4882 }
4883 *atomic_used_mask_p = atomic_used_mask;
4884 return true;
4885 }
4886
4887 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
4888 bool is_compute,
4889 struct r600_shader_atomic *combined_atomics,
4890 uint8_t *atomic_used_mask_p)
4891 {
4892 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
4893 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4894 uint32_t pkt_flags = 0;
4895 uint32_t event = EVENT_TYPE_PS_DONE;
4896 uint32_t mask = astate->enabled_mask;
4897 uint64_t dst_offset;
4898 unsigned reloc;
4899
4900 if (is_compute)
4901 pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
4902
4903 mask = *atomic_used_mask_p;
4904 if (!mask)
4905 return;
4906
4907 while (mask) {
4908 unsigned atomic_index = u_bit_scan(&mask);
4909 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
4910 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
4911 assert(resource);
4912
4913 if (rctx->b.chip_class == CAYMAN)
4914 cayman_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
4915 else
4916 evergreen_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
4917 }
4918
4919 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4920 event = EVENT_TYPE_CS_DONE;
4921
4922 ++rctx->append_fence_id;
4923 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4924 r600_resource(rctx->append_fence),
4925 RADEON_USAGE_READWRITE,
4926 RADEON_PRIO_SHADER_RW_BUFFER);
4927 dst_offset = r600_resource(rctx->append_fence)->gpu_address;
4928 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4929 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4930 radeon_emit(cs, dst_offset & 0xffffffff);
4931 radeon_emit(cs, (2 << 29) | ((dst_offset >> 32) & 0xff));
4932 radeon_emit(cs, rctx->append_fence_id);
4933 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4934 radeon_emit(cs, reloc);
4935
4936 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0) | pkt_flags);
4937 radeon_emit(cs, WAIT_REG_MEM_GEQUAL | WAIT_REG_MEM_MEMORY | (1 << 8));
4938 radeon_emit(cs, dst_offset & 0xffffffff);
4939 radeon_emit(cs, ((dst_offset >> 32) & 0xff));
4940 radeon_emit(cs, rctx->append_fence_id);
4941 radeon_emit(cs, 0xffffffff);
4942 radeon_emit(cs, 0xa);
4943 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4944 radeon_emit(cs, reloc);
4945 }