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Merge branch 'xa_branch'
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "eg_state_inlines.h"
50
51 static void evergreen_set_blend_color(struct pipe_context *ctx,
52 const struct pipe_blend_color *state)
53 {
54 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
55 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
56
57 if (rstate == NULL)
58 return;
59
60 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
61 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
62 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
63 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
65
66 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
67 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
68 r600_context_pipe_state_set(&rctx->ctx, rstate);
69 }
70
71 static void *evergreen_create_blend_state(struct pipe_context *ctx,
72 const struct pipe_blend_state *state)
73 {
74 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
75 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
76 struct r600_pipe_state *rstate;
77 u32 color_control, target_mask;
78 /* FIXME there is more then 8 framebuffer */
79 unsigned blend_cntl[8];
80 enum radeon_family family;
81
82 if (blend == NULL) {
83 return NULL;
84 }
85
86 family = r600_get_family(rctx->radeon);
87 rstate = &blend->rstate;
88
89 rstate->id = R600_PIPE_STATE_BLEND;
90
91 target_mask = 0;
92 color_control = S_028808_MODE(1);
93 if (state->logicop_enable) {
94 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
95 } else {
96 color_control |= (0xcc << 16);
97 }
98 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
99 if (state->independent_blend_enable) {
100 for (int i = 0; i < 8; i++) {
101 target_mask |= (state->rt[i].colormask << (4 * i));
102 }
103 } else {
104 for (int i = 0; i < 8; i++) {
105 target_mask |= (state->rt[0].colormask << (4 * i));
106 }
107 }
108 blend->cb_target_mask = target_mask;
109
110 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
111 color_control, 0xFFFFFFFD, NULL);
112
113 if (family != CHIP_CAYMAN)
114 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
115 else {
116 r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
117 r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
118 }
119
120 for (int i = 0; i < 8; i++) {
121 /* state->rt entries > 0 only written if independent blending */
122 const int j = state->independent_blend_enable ? i : 0;
123
124 unsigned eqRGB = state->rt[j].rgb_func;
125 unsigned srcRGB = state->rt[j].rgb_src_factor;
126 unsigned dstRGB = state->rt[j].rgb_dst_factor;
127 unsigned eqA = state->rt[j].alpha_func;
128 unsigned srcA = state->rt[j].alpha_src_factor;
129 unsigned dstA = state->rt[j].alpha_dst_factor;
130
131 blend_cntl[i] = 0;
132 if (!state->rt[j].blend_enable)
133 continue;
134
135 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
136 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
137 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
138 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
139
140 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
141 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
142 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
143 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
144 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
145 }
146 }
147 for (int i = 0; i < 8; i++) {
148 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
149 }
150
151 return rstate;
152 }
153
154 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
155 const struct pipe_depth_stencil_alpha_state *state)
156 {
157 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
158 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
159 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
160 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
161 struct r600_pipe_state *rstate;
162
163 if (dsa == NULL) {
164 return NULL;
165 }
166
167 rstate = &dsa->rstate;
168
169 rstate->id = R600_PIPE_STATE_DSA;
170 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
171 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
172 stencil_ref_mask = 0;
173 stencil_ref_mask_bf = 0;
174 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
175 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
176 S_028800_ZFUNC(state->depth.func);
177
178 /* stencil */
179 if (state->stencil[0].enabled) {
180 db_depth_control |= S_028800_STENCIL_ENABLE(1);
181 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
182 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
183 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
184 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
185
186
187 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
188 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
189 if (state->stencil[1].enabled) {
190 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
191 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
192 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
193 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
194 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
195 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
196 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
197 }
198 }
199
200 /* alpha */
201 alpha_test_control = 0;
202 alpha_ref = 0;
203 if (state->alpha.enabled) {
204 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
205 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
206 alpha_ref = fui(state->alpha.ref_value);
207 }
208 dsa->alpha_ref = alpha_ref;
209
210 /* misc */
211 db_render_control = 0;
212 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
213 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
214 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
215 /* TODO db_render_override depends on query */
216 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
217 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
218 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
219 r600_pipe_state_add_reg(rstate,
220 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
221 0xFFFFFFFF & C_028430_STENCILREF, NULL);
222 r600_pipe_state_add_reg(rstate,
223 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
224 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
225 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
226 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
227 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
228 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
229 * evergreen_pipe_shader_ps().*/
230 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL);
231 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
232 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
233 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
234 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
235 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
236 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
237
238 return rstate;
239 }
240
241 static void *evergreen_create_rs_state(struct pipe_context *ctx,
242 const struct pipe_rasterizer_state *state)
243 {
244 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
245 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
246 struct r600_pipe_state *rstate;
247 unsigned tmp;
248 unsigned prov_vtx = 1, polygon_dual_mode;
249 unsigned clip_rule;
250 enum radeon_family family;
251
252 family = r600_get_family(rctx->radeon);
253
254 if (rs == NULL) {
255 return NULL;
256 }
257
258 rstate = &rs->rstate;
259 rs->clamp_vertex_color = state->clamp_vertex_color;
260 rs->clamp_fragment_color = state->clamp_fragment_color;
261 rs->flatshade = state->flatshade;
262 rs->sprite_coord_enable = state->sprite_coord_enable;
263
264 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
265
266 /* offset */
267 rs->offset_units = state->offset_units;
268 rs->offset_scale = state->offset_scale * 12.0f;
269
270 rstate->id = R600_PIPE_STATE_RASTERIZER;
271 if (state->flatshade_first)
272 prov_vtx = 0;
273 tmp = S_0286D4_FLAT_SHADE_ENA(1);
274 if (state->sprite_coord_enable) {
275 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
276 S_0286D4_PNT_SPRITE_OVRD_X(2) |
277 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
278 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
279 S_0286D4_PNT_SPRITE_OVRD_W(1);
280 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
281 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
282 }
283 }
284 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
285
286 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
287 state->fill_back != PIPE_POLYGON_MODE_FILL);
288 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
289 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
290 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
291 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
292 S_028814_FACE(!state->front_ccw) |
293 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
294 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
295 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
296 S_028814_POLY_MODE(polygon_dual_mode) |
297 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
298 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
299 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
300 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
301 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
302 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
303 /* point size 12.4 fixed point */
304 tmp = (unsigned)(state->point_size * 8.0);
305 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
306 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
307
308 tmp = (unsigned)state->line_width * 8;
309 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
310
311 if (family == CHIP_CAYMAN) {
312 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
313 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
314 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
315 0xFFFFFFFF, NULL);
316 r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
317 r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
318 r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
319 r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
320
321
322 } else {
323 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
324
325 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
326 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
327 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
328 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
329
330 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
331 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
332 0xFFFFFFFF, NULL);
333 }
334 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
335 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
336 return rstate;
337 }
338
339 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
340 const struct pipe_sampler_state *state)
341 {
342 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
343 union util_color uc;
344 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
345
346 if (rstate == NULL) {
347 return NULL;
348 }
349
350 rstate->id = R600_PIPE_STATE_SAMPLER;
351 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
352 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
353 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
354 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
355 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
356 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
357 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
358 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
359 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
360 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
361 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
362 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
363 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
364 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
365 0xFFFFFFFF, NULL);
366 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
367 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
368 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
369 S_03C008_TYPE(1),
370 0xFFFFFFFF, NULL);
371
372 if (uc.ui) {
373 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
374 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
375 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
376 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
377 }
378 return rstate;
379 }
380
381 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
382 struct pipe_resource *texture,
383 const struct pipe_sampler_view *state)
384 {
385 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
386 struct r600_pipe_resource_state *rstate;
387 const struct util_format_description *desc;
388 struct r600_resource_texture *tmp;
389 struct r600_resource *rbuffer;
390 unsigned format, endian;
391 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
392 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
393 struct r600_bo *bo[2];
394
395 if (resource == NULL)
396 return NULL;
397 rstate = &resource->state;
398
399 /* initialize base object */
400 resource->base = *state;
401 resource->base.texture = NULL;
402 pipe_reference(NULL, &texture->reference);
403 resource->base.texture = texture;
404 resource->base.reference.count = 1;
405 resource->base.context = ctx;
406
407 swizzle[0] = state->swizzle_r;
408 swizzle[1] = state->swizzle_g;
409 swizzle[2] = state->swizzle_b;
410 swizzle[3] = state->swizzle_a;
411 format = r600_translate_texformat(ctx->screen, state->format,
412 swizzle,
413 &word4, &yuv_format);
414 if (format == ~0) {
415 format = 0;
416 }
417 desc = util_format_description(state->format);
418 if (desc == NULL) {
419 R600_ERR("unknow format %d\n", state->format);
420 }
421 tmp = (struct r600_resource_texture *)texture;
422 if (tmp->depth && !tmp->is_flushing_texture) {
423 r600_texture_depth_flush(ctx, texture, TRUE);
424 tmp = tmp->flushed_depth_texture;
425 }
426
427 endian = r600_colorformat_endian_swap(format);
428
429 if (tmp->force_int_type) {
430 word4 &= C_030010_NUM_FORMAT_ALL;
431 word4 |= S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_INT);
432 }
433
434 rbuffer = &tmp->resource;
435 bo[0] = rbuffer->bo;
436 bo[1] = rbuffer->bo;
437
438 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
439 array_mode = tmp->array_mode[0];
440 tile_type = tmp->tile_type;
441
442 rstate->bo[0] = bo[0];
443 rstate->bo[1] = bo[1];
444 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
445 S_030000_PITCH((pitch / 8) - 1) |
446 S_030000_NON_DISP_TILING_ORDER(tile_type) |
447 S_030000_TEX_WIDTH(texture->width0 - 1));
448 rstate->val[1] = (S_030004_TEX_HEIGHT(texture->height0 - 1) |
449 S_030004_TEX_DEPTH(texture->depth0 - 1) |
450 S_030004_ARRAY_MODE(array_mode));
451 rstate->val[2] = (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8;
452 rstate->val[3] = (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8;
453 rstate->val[4] = (word4 |
454 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
455 S_030010_ENDIAN_SWAP(endian) |
456 S_030010_BASE_LEVEL(state->u.tex.first_level));
457 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
458 S_030014_BASE_ARRAY(0) |
459 S_030014_LAST_ARRAY(0));
460 rstate->val[6] = (S_030018_MAX_ANISO(4 /* max 16 samples */));
461 rstate->val[7] = (S_03001C_DATA_FORMAT(format) |
462 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE));
463
464 return &resource->base;
465 }
466
467 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
468 struct pipe_sampler_view **views)
469 {
470 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
471 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
472
473 for (int i = 0; i < count; i++) {
474 if (resource[i]) {
475 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
476 i + R600_MAX_CONST_BUFFERS);
477 }
478 }
479 }
480
481 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
482 struct pipe_sampler_view **views)
483 {
484 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
485 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
486 int i;
487 int has_depth = 0;
488
489 for (i = 0; i < count; i++) {
490 if (&rctx->ps_samplers.views[i]->base != views[i]) {
491 if (resource[i]) {
492 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
493 has_depth = 1;
494 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
495 i + R600_MAX_CONST_BUFFERS);
496 } else
497 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
498 i + R600_MAX_CONST_BUFFERS);
499
500 pipe_sampler_view_reference(
501 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
502 views[i]);
503 } else {
504 if (resource[i]) {
505 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
506 has_depth = 1;
507 }
508 }
509 }
510 for (i = count; i < NUM_TEX_UNITS; i++) {
511 if (rctx->ps_samplers.views[i]) {
512 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
513 i + R600_MAX_CONST_BUFFERS);
514 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
515 }
516 }
517 rctx->have_depth_texture = has_depth;
518 rctx->ps_samplers.n_views = count;
519 }
520
521 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
522 {
523 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
524 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
525
526
527 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
528 rctx->ps_samplers.n_samplers = count;
529
530 for (int i = 0; i < count; i++) {
531 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
532 }
533 }
534
535 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
536 {
537 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
538 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
539
540 for (int i = 0; i < count; i++) {
541 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
542 }
543 }
544
545 static void evergreen_set_clip_state(struct pipe_context *ctx,
546 const struct pipe_clip_state *state)
547 {
548 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
549 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
550
551 if (rstate == NULL)
552 return;
553
554 rctx->clip = *state;
555 rstate->id = R600_PIPE_STATE_CLIP;
556 for (int i = 0; i < state->nr; i++) {
557 r600_pipe_state_add_reg(rstate,
558 R_0285BC_PA_CL_UCP0_X + i * 16,
559 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
560 r600_pipe_state_add_reg(rstate,
561 R_0285C0_PA_CL_UCP0_Y + i * 16,
562 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
563 r600_pipe_state_add_reg(rstate,
564 R_0285C4_PA_CL_UCP0_Z + i * 16,
565 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
566 r600_pipe_state_add_reg(rstate,
567 R_0285C8_PA_CL_UCP0_W + i * 16,
568 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
569 }
570 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
571 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
572 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
573 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
574
575 free(rctx->states[R600_PIPE_STATE_CLIP]);
576 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
577 r600_context_pipe_state_set(&rctx->ctx, rstate);
578 }
579
580 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
581 const struct pipe_poly_stipple *state)
582 {
583 }
584
585 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
586 {
587 }
588
589 static void evergreen_set_scissor_state(struct pipe_context *ctx,
590 const struct pipe_scissor_state *state)
591 {
592 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
593 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
594 u32 tl, br;
595
596 if (rstate == NULL)
597 return;
598
599 rstate->id = R600_PIPE_STATE_SCISSOR;
600 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
601 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
602 r600_pipe_state_add_reg(rstate,
603 R_028210_PA_SC_CLIPRECT_0_TL, tl,
604 0xFFFFFFFF, NULL);
605 r600_pipe_state_add_reg(rstate,
606 R_028214_PA_SC_CLIPRECT_0_BR, br,
607 0xFFFFFFFF, NULL);
608 r600_pipe_state_add_reg(rstate,
609 R_028218_PA_SC_CLIPRECT_1_TL, tl,
610 0xFFFFFFFF, NULL);
611 r600_pipe_state_add_reg(rstate,
612 R_02821C_PA_SC_CLIPRECT_1_BR, br,
613 0xFFFFFFFF, NULL);
614 r600_pipe_state_add_reg(rstate,
615 R_028220_PA_SC_CLIPRECT_2_TL, tl,
616 0xFFFFFFFF, NULL);
617 r600_pipe_state_add_reg(rstate,
618 R_028224_PA_SC_CLIPRECT_2_BR, br,
619 0xFFFFFFFF, NULL);
620 r600_pipe_state_add_reg(rstate,
621 R_028228_PA_SC_CLIPRECT_3_TL, tl,
622 0xFFFFFFFF, NULL);
623 r600_pipe_state_add_reg(rstate,
624 R_02822C_PA_SC_CLIPRECT_3_BR, br,
625 0xFFFFFFFF, NULL);
626
627 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
628 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
629 r600_context_pipe_state_set(&rctx->ctx, rstate);
630 }
631
632 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
633 const struct pipe_stencil_ref *state)
634 {
635 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
636 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
637 u32 tmp;
638
639 if (rstate == NULL)
640 return;
641
642 rctx->stencil_ref = *state;
643 rstate->id = R600_PIPE_STATE_STENCIL_REF;
644 tmp = S_028430_STENCILREF(state->ref_value[0]);
645 r600_pipe_state_add_reg(rstate,
646 R_028430_DB_STENCILREFMASK, tmp,
647 ~C_028430_STENCILREF, NULL);
648 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
649 r600_pipe_state_add_reg(rstate,
650 R_028434_DB_STENCILREFMASK_BF, tmp,
651 ~C_028434_STENCILREF_BF, NULL);
652
653 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
654 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
655 r600_context_pipe_state_set(&rctx->ctx, rstate);
656 }
657
658 static void evergreen_set_viewport_state(struct pipe_context *ctx,
659 const struct pipe_viewport_state *state)
660 {
661 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
662 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
663
664 if (rstate == NULL)
665 return;
666
667 rctx->viewport = *state;
668 rstate->id = R600_PIPE_STATE_VIEWPORT;
669 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
670 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
671 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
672 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
673 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
674 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
675 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
676 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
677 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
678
679 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
680 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
681 r600_context_pipe_state_set(&rctx->ctx, rstate);
682 }
683
684 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
685 const struct pipe_framebuffer_state *state, int cb)
686 {
687 struct r600_resource_texture *rtex;
688 struct r600_resource *rbuffer;
689 struct r600_surface *surf;
690 unsigned level = state->cbufs[cb]->u.tex.level;
691 unsigned pitch, slice;
692 unsigned color_info;
693 unsigned format, swap, ntype, endian;
694 unsigned offset;
695 unsigned tile_type;
696 const struct util_format_description *desc;
697 struct r600_bo *bo[3];
698 int i;
699
700 surf = (struct r600_surface *)state->cbufs[cb];
701 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
702
703 if (rtex->depth)
704 rctx->have_depth_fb = TRUE;
705
706 if (rtex->depth && !rtex->is_flushing_texture) {
707 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
708 rtex = rtex->flushed_depth_texture;
709 }
710
711 rbuffer = &rtex->resource;
712 bo[0] = rbuffer->bo;
713 bo[1] = rbuffer->bo;
714 bo[2] = rbuffer->bo;
715
716 /* XXX quite sure for dx10+ hw don't need any offset hacks */
717 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
718 level, state->cbufs[cb]->u.tex.first_layer);
719 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
720 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
721 desc = util_format_description(surf->base.format);
722 for (i = 0; i < 4; i++) {
723 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
724 break;
725 }
726 }
727 ntype = V_028C70_NUMBER_UNORM;
728 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
729 ntype = V_028C70_NUMBER_SRGB;
730 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
731 ntype = V_028C70_NUMBER_SNORM;
732
733 format = r600_translate_colorformat(surf->base.format);
734 swap = r600_translate_colorswap(surf->base.format);
735 if (rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
736 endian = ENDIAN_NONE;
737 } else {
738 endian = r600_colorformat_endian_swap(format);
739 }
740
741 /* disable when gallium grows int textures */
742 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
743 ntype = V_028C70_NUMBER_UINT;
744
745 color_info = S_028C70_FORMAT(format) |
746 S_028C70_COMP_SWAP(swap) |
747 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
748 S_028C70_BLEND_CLAMP(1) |
749 S_028C70_NUMBER_TYPE(ntype) |
750 S_028C70_ENDIAN(endian);
751
752
753 /* EXPORT_NORM is an optimzation that can be enabled for better
754 * performance in certain cases.
755 * EXPORT_NORM can be enabled if:
756 * - 11-bit or smaller UNORM/SNORM/SRGB
757 * - 16-bit or smaller FLOAT
758 */
759 /* FIXME: This should probably be the same for all CBs if we want
760 * useful alpha tests. */
761 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
762 ((desc->channel[i].size < 12 &&
763 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
764 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
765 (desc->channel[i].size < 17 &&
766 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
767 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
768 rctx->export_16bpc = true;
769 } else {
770 rctx->export_16bpc = false;
771 }
772 rctx->alpha_ref_dirty = true;
773
774 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
775 tile_type = rtex->tile_type;
776 } else /* workaround for linear buffers */
777 tile_type = 1;
778
779 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
780 r600_pipe_state_add_reg(rstate,
781 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
782 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
783 r600_pipe_state_add_reg(rstate,
784 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
785 0x0, 0xFFFFFFFF, NULL);
786 r600_pipe_state_add_reg(rstate,
787 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
788 color_info, 0xFFFFFFFF, bo[0]);
789 r600_pipe_state_add_reg(rstate,
790 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
791 S_028C64_PITCH_TILE_MAX(pitch),
792 0xFFFFFFFF, NULL);
793 r600_pipe_state_add_reg(rstate,
794 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
795 S_028C68_SLICE_TILE_MAX(slice),
796 0xFFFFFFFF, NULL);
797 r600_pipe_state_add_reg(rstate,
798 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
799 0x00000000, 0xFFFFFFFF, NULL);
800 r600_pipe_state_add_reg(rstate,
801 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
802 S_028C74_NON_DISP_TILING_ORDER(tile_type),
803 0xFFFFFFFF, bo[0]);
804 }
805
806 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
807 const struct pipe_framebuffer_state *state)
808 {
809 struct r600_resource_texture *rtex;
810 struct r600_resource *rbuffer;
811 struct r600_surface *surf;
812 unsigned level;
813 unsigned pitch, slice, format, stencil_format;
814 unsigned offset;
815
816 if (state->zsbuf == NULL)
817 return;
818
819 level = state->zsbuf->u.tex.level;
820
821 surf = (struct r600_surface *)state->zsbuf;
822 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
823
824 rbuffer = &rtex->resource;
825
826 /* XXX quite sure for dx10+ hw don't need any offset hacks */
827 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
828 level, state->zsbuf->u.tex.first_layer);
829 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
830 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
831 format = r600_translate_dbformat(state->zsbuf->texture->format);
832 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
833
834 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
835 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
836 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
837 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
838
839 if (stencil_format) {
840 uint32_t stencil_offset;
841
842 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
843 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
844 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
845 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
846 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
847 }
848
849 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
850 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
851 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
852
853 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
854 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
855 0xFFFFFFFF, rbuffer->bo);
856 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
857 S_028058_PITCH_TILE_MAX(pitch),
858 0xFFFFFFFF, NULL);
859 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
860 S_02805C_SLICE_TILE_MAX(slice),
861 0xFFFFFFFF, NULL);
862 }
863
864 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
865 const struct pipe_framebuffer_state *state)
866 {
867 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
868 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
869 u32 shader_mask, tl, br, target_mask;
870 enum radeon_family family;
871 int tl_x, tl_y, br_x, br_y;
872
873 if (rstate == NULL)
874 return;
875
876 family = r600_get_family(rctx->radeon);
877
878 evergreen_context_flush_dest_caches(&rctx->ctx);
879 rctx->ctx.num_dest_buffers = state->nr_cbufs;
880
881 /* unreference old buffer and reference new one */
882 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
883
884 util_copy_framebuffer_state(&rctx->framebuffer, state);
885
886 /* build states */
887 rctx->have_depth_fb = 0;
888 rctx->nr_cbufs = state->nr_cbufs;
889 for (int i = 0; i < state->nr_cbufs; i++) {
890 evergreen_cb(rctx, rstate, state, i);
891 }
892 if (state->zsbuf) {
893 evergreen_db(rctx, rstate, state);
894 rctx->ctx.num_dest_buffers++;
895 }
896
897 target_mask = 0x00000000;
898 target_mask = 0xFFFFFFFF;
899 shader_mask = 0;
900 for (int i = 0; i < state->nr_cbufs; i++) {
901 target_mask ^= 0xf << (i * 4);
902 shader_mask |= 0xf << (i * 4);
903 }
904 tl_x = 0;
905 tl_y = 0;
906 br_x = state->width;
907 br_y = state->height;
908 /* EG hw workaround */
909 if (br_x == 0)
910 tl_x = 1;
911 if (br_y == 0)
912 tl_y = 1;
913 /* cayman hw workaround */
914 if (family == CHIP_CAYMAN) {
915 if (br_x == 1 && br_y == 1)
916 br_x = 2;
917 }
918 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
919 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
920
921 r600_pipe_state_add_reg(rstate,
922 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
923 0xFFFFFFFF, NULL);
924 r600_pipe_state_add_reg(rstate,
925 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
926 0xFFFFFFFF, NULL);
927 r600_pipe_state_add_reg(rstate,
928 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
929 0xFFFFFFFF, NULL);
930 r600_pipe_state_add_reg(rstate,
931 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
932 0xFFFFFFFF, NULL);
933 r600_pipe_state_add_reg(rstate,
934 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
935 0xFFFFFFFF, NULL);
936 r600_pipe_state_add_reg(rstate,
937 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
938 0xFFFFFFFF, NULL);
939 r600_pipe_state_add_reg(rstate,
940 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
941 0xFFFFFFFF, NULL);
942 r600_pipe_state_add_reg(rstate,
943 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
944 0xFFFFFFFF, NULL);
945 r600_pipe_state_add_reg(rstate,
946 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
947 0xFFFFFFFF, NULL);
948 r600_pipe_state_add_reg(rstate,
949 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
950 0xFFFFFFFF, NULL);
951
952 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
953 0x00000000, target_mask, NULL);
954 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
955 shader_mask, 0xFFFFFFFF, NULL);
956
957
958 if (family == CHIP_CAYMAN) {
959 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
960 0x00000000, 0xFFFFFFFF, NULL);
961 } else {
962 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
963 0x00000000, 0xFFFFFFFF, NULL);
964 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
965 0x00000000, 0xFFFFFFFF, NULL);
966 }
967
968 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
969 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
970 r600_context_pipe_state_set(&rctx->ctx, rstate);
971
972 if (state->zsbuf) {
973 evergreen_polygon_offset_update(rctx);
974 }
975 }
976
977 static void evergreen_texture_barrier(struct pipe_context *ctx)
978 {
979 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
980
981 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
982 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
983 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
984 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
985 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
986 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
987 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
988 }
989
990 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
991 {
992 rctx->context.create_blend_state = evergreen_create_blend_state;
993 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
994 rctx->context.create_fs_state = r600_create_shader_state;
995 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
996 rctx->context.create_sampler_state = evergreen_create_sampler_state;
997 rctx->context.create_sampler_view = evergreen_create_sampler_view;
998 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
999 rctx->context.create_vs_state = r600_create_shader_state;
1000 rctx->context.bind_blend_state = r600_bind_blend_state;
1001 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1002 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1003 rctx->context.bind_fs_state = r600_bind_ps_shader;
1004 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1005 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1006 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1007 rctx->context.bind_vs_state = r600_bind_vs_shader;
1008 rctx->context.delete_blend_state = r600_delete_state;
1009 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1010 rctx->context.delete_fs_state = r600_delete_ps_shader;
1011 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1012 rctx->context.delete_sampler_state = r600_delete_state;
1013 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1014 rctx->context.delete_vs_state = r600_delete_vs_shader;
1015 rctx->context.set_blend_color = evergreen_set_blend_color;
1016 rctx->context.set_clip_state = evergreen_set_clip_state;
1017 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1018 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1019 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1020 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1021 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1022 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1023 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1024 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1025 rctx->context.set_index_buffer = r600_set_index_buffer;
1026 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1027 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1028 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1029 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1030 rctx->context.texture_barrier = evergreen_texture_barrier;
1031 }
1032
1033 static void cayman_init_config(struct r600_pipe_context *rctx)
1034 {
1035 struct r600_pipe_state *rstate = &rctx->config;
1036 unsigned tmp;
1037
1038 tmp = 0x00000000;
1039 tmp |= S_008C00_EXPORT_SRC_C(1);
1040 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1041
1042 /* always set the temp clauses */
1043 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), 0xFFFFFFFF, NULL);
1044 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL);
1045 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL);
1046 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL);
1047
1048 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1049 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1050
1051 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1052 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1053 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1054 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1055 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1056 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1057 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1058 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1059 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1060 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1061 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1062 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1063 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1064 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1065 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1066 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1067 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1068 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1069
1070 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1071 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1072 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1073 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1074 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1075 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1076 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1077 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1078 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1079 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1080 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1081 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1082 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1083 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1084 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1085 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1086 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1087 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1088 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1089 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1090 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1091 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1092 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1093 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1094 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1095 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1096 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1097 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1098 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1099 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1100 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1101 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1102
1103 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
1104
1105 r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, 0xffffffff, 0);
1106 r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, 0xffffffff, 0);
1107
1108 r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, 0xffffffff, NULL);
1109 r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0xffffffff, NULL);
1110
1111 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, 0xffffffff, NULL);
1112 r600_context_pipe_state_set(&rctx->ctx, rstate);
1113 }
1114
1115 void evergreen_init_config(struct r600_pipe_context *rctx)
1116 {
1117 struct r600_pipe_state *rstate = &rctx->config;
1118 int ps_prio;
1119 int vs_prio;
1120 int gs_prio;
1121 int es_prio;
1122 int hs_prio, cs_prio, ls_prio;
1123 int num_ps_gprs;
1124 int num_vs_gprs;
1125 int num_gs_gprs;
1126 int num_es_gprs;
1127 int num_hs_gprs;
1128 int num_ls_gprs;
1129 int num_temp_gprs;
1130 int num_ps_threads;
1131 int num_vs_threads;
1132 int num_gs_threads;
1133 int num_es_threads;
1134 int num_hs_threads;
1135 int num_ls_threads;
1136 int num_ps_stack_entries;
1137 int num_vs_stack_entries;
1138 int num_gs_stack_entries;
1139 int num_es_stack_entries;
1140 int num_hs_stack_entries;
1141 int num_ls_stack_entries;
1142 enum radeon_family family;
1143 unsigned tmp;
1144
1145 family = r600_get_family(rctx->radeon);
1146
1147 if (family == CHIP_CAYMAN) {
1148 cayman_init_config(rctx);
1149 return;
1150 }
1151
1152 ps_prio = 0;
1153 vs_prio = 1;
1154 gs_prio = 2;
1155 es_prio = 3;
1156 hs_prio = 0;
1157 ls_prio = 0;
1158 cs_prio = 0;
1159
1160 switch (family) {
1161 case CHIP_CEDAR:
1162 default:
1163 num_ps_gprs = 93;
1164 num_vs_gprs = 46;
1165 num_temp_gprs = 4;
1166 num_gs_gprs = 31;
1167 num_es_gprs = 31;
1168 num_hs_gprs = 23;
1169 num_ls_gprs = 23;
1170 num_ps_threads = 96;
1171 num_vs_threads = 16;
1172 num_gs_threads = 16;
1173 num_es_threads = 16;
1174 num_hs_threads = 16;
1175 num_ls_threads = 16;
1176 num_ps_stack_entries = 42;
1177 num_vs_stack_entries = 42;
1178 num_gs_stack_entries = 42;
1179 num_es_stack_entries = 42;
1180 num_hs_stack_entries = 42;
1181 num_ls_stack_entries = 42;
1182 break;
1183 case CHIP_REDWOOD:
1184 num_ps_gprs = 93;
1185 num_vs_gprs = 46;
1186 num_temp_gprs = 4;
1187 num_gs_gprs = 31;
1188 num_es_gprs = 31;
1189 num_hs_gprs = 23;
1190 num_ls_gprs = 23;
1191 num_ps_threads = 128;
1192 num_vs_threads = 20;
1193 num_gs_threads = 20;
1194 num_es_threads = 20;
1195 num_hs_threads = 20;
1196 num_ls_threads = 20;
1197 num_ps_stack_entries = 42;
1198 num_vs_stack_entries = 42;
1199 num_gs_stack_entries = 42;
1200 num_es_stack_entries = 42;
1201 num_hs_stack_entries = 42;
1202 num_ls_stack_entries = 42;
1203 break;
1204 case CHIP_JUNIPER:
1205 num_ps_gprs = 93;
1206 num_vs_gprs = 46;
1207 num_temp_gprs = 4;
1208 num_gs_gprs = 31;
1209 num_es_gprs = 31;
1210 num_hs_gprs = 23;
1211 num_ls_gprs = 23;
1212 num_ps_threads = 128;
1213 num_vs_threads = 20;
1214 num_gs_threads = 20;
1215 num_es_threads = 20;
1216 num_hs_threads = 20;
1217 num_ls_threads = 20;
1218 num_ps_stack_entries = 85;
1219 num_vs_stack_entries = 85;
1220 num_gs_stack_entries = 85;
1221 num_es_stack_entries = 85;
1222 num_hs_stack_entries = 85;
1223 num_ls_stack_entries = 85;
1224 break;
1225 case CHIP_CYPRESS:
1226 case CHIP_HEMLOCK:
1227 num_ps_gprs = 93;
1228 num_vs_gprs = 46;
1229 num_temp_gprs = 4;
1230 num_gs_gprs = 31;
1231 num_es_gprs = 31;
1232 num_hs_gprs = 23;
1233 num_ls_gprs = 23;
1234 num_ps_threads = 128;
1235 num_vs_threads = 20;
1236 num_gs_threads = 20;
1237 num_es_threads = 20;
1238 num_hs_threads = 20;
1239 num_ls_threads = 20;
1240 num_ps_stack_entries = 85;
1241 num_vs_stack_entries = 85;
1242 num_gs_stack_entries = 85;
1243 num_es_stack_entries = 85;
1244 num_hs_stack_entries = 85;
1245 num_ls_stack_entries = 85;
1246 break;
1247 case CHIP_PALM:
1248 num_ps_gprs = 93;
1249 num_vs_gprs = 46;
1250 num_temp_gprs = 4;
1251 num_gs_gprs = 31;
1252 num_es_gprs = 31;
1253 num_hs_gprs = 23;
1254 num_ls_gprs = 23;
1255 num_ps_threads = 96;
1256 num_vs_threads = 16;
1257 num_gs_threads = 16;
1258 num_es_threads = 16;
1259 num_hs_threads = 16;
1260 num_ls_threads = 16;
1261 num_ps_stack_entries = 42;
1262 num_vs_stack_entries = 42;
1263 num_gs_stack_entries = 42;
1264 num_es_stack_entries = 42;
1265 num_hs_stack_entries = 42;
1266 num_ls_stack_entries = 42;
1267 break;
1268 case CHIP_SUMO:
1269 num_ps_gprs = 93;
1270 num_vs_gprs = 46;
1271 num_temp_gprs = 4;
1272 num_gs_gprs = 31;
1273 num_es_gprs = 31;
1274 num_hs_gprs = 23;
1275 num_ls_gprs = 23;
1276 num_ps_threads = 96;
1277 num_vs_threads = 25;
1278 num_gs_threads = 25;
1279 num_es_threads = 25;
1280 num_hs_threads = 25;
1281 num_ls_threads = 25;
1282 num_ps_stack_entries = 42;
1283 num_vs_stack_entries = 42;
1284 num_gs_stack_entries = 42;
1285 num_es_stack_entries = 42;
1286 num_hs_stack_entries = 42;
1287 num_ls_stack_entries = 42;
1288 break;
1289 case CHIP_SUMO2:
1290 num_ps_gprs = 93;
1291 num_vs_gprs = 46;
1292 num_temp_gprs = 4;
1293 num_gs_gprs = 31;
1294 num_es_gprs = 31;
1295 num_hs_gprs = 23;
1296 num_ls_gprs = 23;
1297 num_ps_threads = 96;
1298 num_vs_threads = 25;
1299 num_gs_threads = 25;
1300 num_es_threads = 25;
1301 num_hs_threads = 25;
1302 num_ls_threads = 25;
1303 num_ps_stack_entries = 85;
1304 num_vs_stack_entries = 85;
1305 num_gs_stack_entries = 85;
1306 num_es_stack_entries = 85;
1307 num_hs_stack_entries = 85;
1308 num_ls_stack_entries = 85;
1309 break;
1310 case CHIP_BARTS:
1311 num_ps_gprs = 93;
1312 num_vs_gprs = 46;
1313 num_temp_gprs = 4;
1314 num_gs_gprs = 31;
1315 num_es_gprs = 31;
1316 num_hs_gprs = 23;
1317 num_ls_gprs = 23;
1318 num_ps_threads = 128;
1319 num_vs_threads = 20;
1320 num_gs_threads = 20;
1321 num_es_threads = 20;
1322 num_hs_threads = 20;
1323 num_ls_threads = 20;
1324 num_ps_stack_entries = 85;
1325 num_vs_stack_entries = 85;
1326 num_gs_stack_entries = 85;
1327 num_es_stack_entries = 85;
1328 num_hs_stack_entries = 85;
1329 num_ls_stack_entries = 85;
1330 break;
1331 case CHIP_TURKS:
1332 num_ps_gprs = 93;
1333 num_vs_gprs = 46;
1334 num_temp_gprs = 4;
1335 num_gs_gprs = 31;
1336 num_es_gprs = 31;
1337 num_hs_gprs = 23;
1338 num_ls_gprs = 23;
1339 num_ps_threads = 128;
1340 num_vs_threads = 20;
1341 num_gs_threads = 20;
1342 num_es_threads = 20;
1343 num_hs_threads = 20;
1344 num_ls_threads = 20;
1345 num_ps_stack_entries = 42;
1346 num_vs_stack_entries = 42;
1347 num_gs_stack_entries = 42;
1348 num_es_stack_entries = 42;
1349 num_hs_stack_entries = 42;
1350 num_ls_stack_entries = 42;
1351 break;
1352 case CHIP_CAICOS:
1353 num_ps_gprs = 93;
1354 num_vs_gprs = 46;
1355 num_temp_gprs = 4;
1356 num_gs_gprs = 31;
1357 num_es_gprs = 31;
1358 num_hs_gprs = 23;
1359 num_ls_gprs = 23;
1360 num_ps_threads = 128;
1361 num_vs_threads = 10;
1362 num_gs_threads = 10;
1363 num_es_threads = 10;
1364 num_hs_threads = 10;
1365 num_ls_threads = 10;
1366 num_ps_stack_entries = 42;
1367 num_vs_stack_entries = 42;
1368 num_gs_stack_entries = 42;
1369 num_es_stack_entries = 42;
1370 num_hs_stack_entries = 42;
1371 num_ls_stack_entries = 42;
1372 break;
1373 }
1374
1375 tmp = 0x00000000;
1376 switch (family) {
1377 case CHIP_CEDAR:
1378 case CHIP_PALM:
1379 case CHIP_SUMO:
1380 case CHIP_SUMO2:
1381 case CHIP_CAICOS:
1382 break;
1383 default:
1384 tmp |= S_008C00_VC_ENABLE(1);
1385 break;
1386 }
1387 tmp |= S_008C00_EXPORT_SRC_C(1);
1388 tmp |= S_008C00_CS_PRIO(cs_prio);
1389 tmp |= S_008C00_LS_PRIO(ls_prio);
1390 tmp |= S_008C00_HS_PRIO(hs_prio);
1391 tmp |= S_008C00_PS_PRIO(ps_prio);
1392 tmp |= S_008C00_VS_PRIO(vs_prio);
1393 tmp |= S_008C00_GS_PRIO(gs_prio);
1394 tmp |= S_008C00_ES_PRIO(es_prio);
1395 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1396
1397 /* enable dynamic GPR resource management */
1398 if (r600_get_minor_version(rctx->radeon) >= 7) {
1399 /* always set temp clauses */
1400 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
1401 S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), 0xFFFFFFFF, NULL);
1402 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL);
1403 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL);
1404 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL);
1405 r600_pipe_state_add_reg(rstate, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
1406 S_028838_PS_GPRS(0x1e) |
1407 S_028838_VS_GPRS(0x1e) |
1408 S_028838_GS_GPRS(0x1e) |
1409 S_028838_ES_GPRS(0x1e) |
1410 S_028838_HS_GPRS(0x1e) |
1411 S_028838_LS_GPRS(0x1e), 0xFFFFFFFF, NULL); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
1412 } else {
1413 tmp = 0;
1414 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1415 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1416 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1417 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1418
1419 tmp = 0;
1420 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1421 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1422 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1423
1424 tmp = 0;
1425 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1426 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
1427 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1428 }
1429
1430 tmp = 0;
1431 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1432 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1433 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1434 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1435 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1436
1437 tmp = 0;
1438 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1439 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1440 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1441
1442 tmp = 0;
1443 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1444 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1445 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1446
1447 tmp = 0;
1448 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1449 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1450 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1451
1452 tmp = 0;
1453 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1454 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1455 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1456
1457 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1458 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1459
1460 #if 0
1461 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1462
1463 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1464 #endif
1465 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1466 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1467
1468 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1469 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1470 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1471 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1472 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1473 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1474
1475 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1476 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1477 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1478 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1479
1480 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1481 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1482 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1483 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1484 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1485 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1486 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1487 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1488 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1489 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1490 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1491 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1492 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1493 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1494 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1495 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1496 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1497 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1498
1499 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1500 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1501 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1502 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1503 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1504 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1505 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1506 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1507 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1508 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1509 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1510 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1511 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1512 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1513 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1514 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1515 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1516 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1517 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1518 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1519 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1520 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1521 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1522 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1523 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1524 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1525 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1526 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1527 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1528 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1529 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1530 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1531
1532 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
1533
1534 r600_context_pipe_state_set(&rctx->ctx, rstate);
1535 }
1536
1537 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
1538 {
1539 struct r600_pipe_state state;
1540
1541 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
1542 state.nregs = 0;
1543 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1544 float offset_units = rctx->rasterizer->offset_units;
1545 unsigned offset_db_fmt_cntl = 0, depth;
1546
1547 switch (rctx->framebuffer.zsbuf->texture->format) {
1548 case PIPE_FORMAT_Z24X8_UNORM:
1549 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1550 depth = -24;
1551 offset_units *= 2.0f;
1552 break;
1553 case PIPE_FORMAT_Z32_FLOAT:
1554 depth = -23;
1555 offset_units *= 1.0f;
1556 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1557 break;
1558 case PIPE_FORMAT_Z16_UNORM:
1559 depth = -16;
1560 offset_units *= 4.0f;
1561 break;
1562 default:
1563 return;
1564 }
1565 /* FIXME some of those reg can be computed with cso */
1566 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1567 r600_pipe_state_add_reg(&state,
1568 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1569 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1570 r600_pipe_state_add_reg(&state,
1571 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1572 fui(offset_units), 0xFFFFFFFF, NULL);
1573 r600_pipe_state_add_reg(&state,
1574 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1575 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1576 r600_pipe_state_add_reg(&state,
1577 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1578 fui(offset_units), 0xFFFFFFFF, NULL);
1579 r600_pipe_state_add_reg(&state,
1580 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1581 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1582 r600_context_pipe_state_set(&rctx->ctx, &state);
1583 }
1584 }
1585
1586 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1587 {
1588 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1589 struct r600_pipe_state *rstate = &shader->rstate;
1590 struct r600_shader *rshader = &shader->shader;
1591 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
1592 int pos_index = -1, face_index = -1;
1593 int ninterp = 0;
1594 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1595 unsigned spi_baryc_cntl;
1596
1597 rstate->nregs = 0;
1598
1599 db_shader_control = 0;
1600 for (i = 0; i < rshader->ninput; i++) {
1601 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1602 POSITION goes via GPRs from the SC so isn't counted */
1603 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1604 pos_index = i;
1605 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1606 face_index = i;
1607 else {
1608 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
1609 rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1610 ninterp++;
1611 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1612 have_linear = TRUE;
1613 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1614 have_perspective = TRUE;
1615 if (rshader->input[i].centroid)
1616 have_centroid = TRUE;
1617 }
1618 }
1619 for (i = 0; i < rshader->noutput; i++) {
1620 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1621 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1622 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1623 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
1624 }
1625 if (rshader->uses_kill)
1626 db_shader_control |= S_02880C_KILL_ENABLE(1);
1627
1628 exports_ps = 0;
1629 num_cout = 0;
1630 for (i = 0; i < rshader->noutput; i++) {
1631 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1632 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1633 exports_ps |= 1;
1634 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1635 if (rshader->fs_write_all)
1636 num_cout = rshader->nr_cbufs;
1637 else
1638 num_cout++;
1639 }
1640 }
1641 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1642 if (!exports_ps) {
1643 /* always at least export 1 component per pixel */
1644 exports_ps = 2;
1645 }
1646
1647 if (ninterp == 0) {
1648 ninterp = 1;
1649 have_perspective = TRUE;
1650 }
1651
1652 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
1653 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
1654 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
1655 spi_input_z = 0;
1656 if (pos_index != -1) {
1657 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
1658 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1659 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
1660 spi_input_z |= 1;
1661 }
1662
1663 spi_ps_in_control_1 = 0;
1664 if (face_index != -1) {
1665 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1666 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1667 }
1668
1669 spi_baryc_cntl = 0;
1670 if (have_perspective)
1671 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
1672 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
1673 if (have_linear)
1674 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
1675 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
1676
1677 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1678 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1679 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1680 spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1681 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
1682 0, 0xFFFFFFFF, NULL);
1683 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1684 r600_pipe_state_add_reg(rstate,
1685 R_0286E0_SPI_BARYC_CNTL,
1686 spi_baryc_cntl,
1687 0xFFFFFFFF, NULL);
1688
1689 r600_pipe_state_add_reg(rstate,
1690 R_028840_SQ_PGM_START_PS,
1691 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1692 r600_pipe_state_add_reg(rstate,
1693 R_028844_SQ_PGM_RESOURCES_PS,
1694 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1695 S_028844_PRIME_CACHE_ON_DRAW(1) |
1696 S_028844_STACK_SIZE(rshader->bc.nstack),
1697 0xFFFFFFFF, NULL);
1698 r600_pipe_state_add_reg(rstate,
1699 R_028848_SQ_PGM_RESOURCES_2_PS,
1700 0x0, 0xFFFFFFFF, NULL);
1701 r600_pipe_state_add_reg(rstate,
1702 R_02884C_SQ_PGM_EXPORTS_PS,
1703 exports_ps, 0xFFFFFFFF, NULL);
1704 /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */
1705 /* only set some bits here, the other bits are set in the dsa state */
1706 r600_pipe_state_add_reg(rstate,
1707 R_02880C_DB_SHADER_CONTROL,
1708 db_shader_control,
1709 S_02880C_Z_EXPORT_ENABLE(1) |
1710 S_02880C_STENCIL_EXPORT_ENABLE(1) |
1711 S_02880C_KILL_ENABLE(1),
1712 NULL);
1713 r600_pipe_state_add_reg(rstate,
1714 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
1715 0xFFFFFFFF, NULL);
1716 }
1717
1718 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1719 {
1720 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1721 struct r600_pipe_state *rstate = &shader->rstate;
1722 struct r600_shader *rshader = &shader->shader;
1723 unsigned spi_vs_out_id[10];
1724 unsigned i, tmp;
1725
1726 /* clear previous register */
1727 rstate->nregs = 0;
1728
1729 /* so far never got proper semantic id from tgsi */
1730 for (i = 0; i < 10; i++) {
1731 spi_vs_out_id[i] = 0;
1732 }
1733 for (i = 0; i < 32; i++) {
1734 tmp = i << ((i & 3) * 8);
1735 spi_vs_out_id[i / 4] |= tmp;
1736 }
1737 for (i = 0; i < 10; i++) {
1738 r600_pipe_state_add_reg(rstate,
1739 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1740 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1741 }
1742
1743 r600_pipe_state_add_reg(rstate,
1744 R_0286C4_SPI_VS_OUT_CONFIG,
1745 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1746 0xFFFFFFFF, NULL);
1747 r600_pipe_state_add_reg(rstate,
1748 R_028860_SQ_PGM_RESOURCES_VS,
1749 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1750 S_028860_STACK_SIZE(rshader->bc.nstack),
1751 0xFFFFFFFF, NULL);
1752 r600_pipe_state_add_reg(rstate,
1753 R_028864_SQ_PGM_RESOURCES_2_VS,
1754 0x0, 0xFFFFFFFF, NULL);
1755 r600_pipe_state_add_reg(rstate,
1756 R_02885C_SQ_PGM_START_VS,
1757 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1758
1759 r600_pipe_state_add_reg(rstate,
1760 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1761 0xFFFFFFFF, NULL);
1762 }
1763
1764 void evergreen_fetch_shader(struct pipe_context *ctx,
1765 struct r600_vertex_element *ve)
1766 {
1767 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1768 struct r600_pipe_state *rstate = &ve->rstate;
1769 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1770 rstate->nregs = 0;
1771 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
1772 0x00000000, 0xFFFFFFFF, NULL);
1773 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
1774 (r600_bo_offset(ve->fetch_shader)) >> 8,
1775 0xFFFFFFFF, ve->fetch_shader);
1776 }
1777
1778 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1779 {
1780 struct pipe_depth_stencil_alpha_state dsa;
1781 struct r600_pipe_state *rstate;
1782
1783 memset(&dsa, 0, sizeof(dsa));
1784
1785 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1786 r600_pipe_state_add_reg(rstate,
1787 R_02880C_DB_SHADER_CONTROL,
1788 0x0,
1789 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1790 r600_pipe_state_add_reg(rstate,
1791 R_028000_DB_RENDER_CONTROL,
1792 S_028000_DEPTH_COPY_ENABLE(1) |
1793 S_028000_STENCIL_COPY_ENABLE(1) |
1794 S_028000_COPY_CENTROID(1),
1795 S_028000_DEPTH_COPY_ENABLE(1) |
1796 S_028000_STENCIL_COPY_ENABLE(1) |
1797 S_028000_COPY_CENTROID(1), NULL);
1798 return rstate;
1799 }
1800
1801 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
1802 struct r600_pipe_resource_state *rstate)
1803 {
1804 rstate->id = R600_PIPE_STATE_RESOURCE;
1805
1806 rstate->val[0] = 0;
1807 rstate->bo[0] = NULL;
1808 rstate->val[1] = 0;
1809 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
1810 rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1811 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1812 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1813 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
1814 rstate->val[4] = 0;
1815 rstate->val[5] = 0;
1816 rstate->val[6] = 0;
1817 rstate->val[7] = 0xc0000000;
1818 }
1819
1820
1821 void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
1822 struct r600_resource *rbuffer,
1823 unsigned offset, unsigned stride)
1824 {
1825 rstate->bo[0] = rbuffer->bo;
1826 rstate->val[0] = offset;
1827 rstate->val[1] = rbuffer->bo_size - offset - 1;
1828 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1829 S_030008_STRIDE(stride);
1830 }