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r600: increase number of UBOs to 15
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static inline unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 default:
39 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
40 break;
41 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
42 break;
43 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
44 }
45 }
46
47 static uint32_t eg_num_banks(uint32_t nbanks)
48 {
49 switch (nbanks) {
50 case 2:
51 return 0;
52 case 4:
53 return 1;
54 case 8:
55 default:
56 return 2;
57 case 16:
58 return 3;
59 }
60 }
61
62
63 static unsigned eg_tile_split(unsigned tile_split)
64 {
65 switch (tile_split) {
66 case 64: tile_split = 0; break;
67 case 128: tile_split = 1; break;
68 case 256: tile_split = 2; break;
69 case 512: tile_split = 3; break;
70 default:
71 case 1024: tile_split = 4; break;
72 case 2048: tile_split = 5; break;
73 case 4096: tile_split = 6; break;
74 }
75 return tile_split;
76 }
77
78 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
79 {
80 switch (macro_tile_aspect) {
81 default:
82 case 1: macro_tile_aspect = 0; break;
83 case 2: macro_tile_aspect = 1; break;
84 case 4: macro_tile_aspect = 2; break;
85 case 8: macro_tile_aspect = 3; break;
86 }
87 return macro_tile_aspect;
88 }
89
90 static unsigned eg_bank_wh(unsigned bankwh)
91 {
92 switch (bankwh) {
93 default:
94 case 1: bankwh = 0; break;
95 case 2: bankwh = 1; break;
96 case 4: bankwh = 2; break;
97 case 8: bankwh = 3; break;
98 }
99 return bankwh;
100 }
101
102 static uint32_t r600_translate_blend_function(int blend_func)
103 {
104 switch (blend_func) {
105 case PIPE_BLEND_ADD:
106 return V_028780_COMB_DST_PLUS_SRC;
107 case PIPE_BLEND_SUBTRACT:
108 return V_028780_COMB_SRC_MINUS_DST;
109 case PIPE_BLEND_REVERSE_SUBTRACT:
110 return V_028780_COMB_DST_MINUS_SRC;
111 case PIPE_BLEND_MIN:
112 return V_028780_COMB_MIN_DST_SRC;
113 case PIPE_BLEND_MAX:
114 return V_028780_COMB_MAX_DST_SRC;
115 default:
116 R600_ERR("Unknown blend function %d\n", blend_func);
117 assert(0);
118 break;
119 }
120 return 0;
121 }
122
123 static uint32_t r600_translate_blend_factor(int blend_fact)
124 {
125 switch (blend_fact) {
126 case PIPE_BLENDFACTOR_ONE:
127 return V_028780_BLEND_ONE;
128 case PIPE_BLENDFACTOR_SRC_COLOR:
129 return V_028780_BLEND_SRC_COLOR;
130 case PIPE_BLENDFACTOR_SRC_ALPHA:
131 return V_028780_BLEND_SRC_ALPHA;
132 case PIPE_BLENDFACTOR_DST_ALPHA:
133 return V_028780_BLEND_DST_ALPHA;
134 case PIPE_BLENDFACTOR_DST_COLOR:
135 return V_028780_BLEND_DST_COLOR;
136 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
137 return V_028780_BLEND_SRC_ALPHA_SATURATE;
138 case PIPE_BLENDFACTOR_CONST_COLOR:
139 return V_028780_BLEND_CONST_COLOR;
140 case PIPE_BLENDFACTOR_CONST_ALPHA:
141 return V_028780_BLEND_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_ZERO:
143 return V_028780_BLEND_ZERO;
144 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
145 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
146 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
147 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
148 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
149 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
150 case PIPE_BLENDFACTOR_INV_DST_COLOR:
151 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
152 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
153 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
154 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
155 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
156 case PIPE_BLENDFACTOR_SRC1_COLOR:
157 return V_028780_BLEND_SRC1_COLOR;
158 case PIPE_BLENDFACTOR_SRC1_ALPHA:
159 return V_028780_BLEND_SRC1_ALPHA;
160 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
161 return V_028780_BLEND_INV_SRC1_COLOR;
162 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
163 return V_028780_BLEND_INV_SRC1_ALPHA;
164 default:
165 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
166 assert(0);
167 break;
168 }
169 return 0;
170 }
171
172 static unsigned r600_tex_dim(struct r600_texture *rtex,
173 unsigned view_target, unsigned nr_samples)
174 {
175 unsigned res_target = rtex->resource.b.b.target;
176
177 if (view_target == PIPE_TEXTURE_CUBE ||
178 view_target == PIPE_TEXTURE_CUBE_ARRAY)
179 res_target = view_target;
180 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
181 else if (res_target == PIPE_TEXTURE_CUBE ||
182 res_target == PIPE_TEXTURE_CUBE_ARRAY)
183 res_target = PIPE_TEXTURE_2D_ARRAY;
184
185 switch (res_target) {
186 default:
187 case PIPE_TEXTURE_1D:
188 return V_030000_SQ_TEX_DIM_1D;
189 case PIPE_TEXTURE_1D_ARRAY:
190 return V_030000_SQ_TEX_DIM_1D_ARRAY;
191 case PIPE_TEXTURE_2D:
192 case PIPE_TEXTURE_RECT:
193 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
194 V_030000_SQ_TEX_DIM_2D;
195 case PIPE_TEXTURE_2D_ARRAY:
196 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
197 V_030000_SQ_TEX_DIM_2D_ARRAY;
198 case PIPE_TEXTURE_3D:
199 return V_030000_SQ_TEX_DIM_3D;
200 case PIPE_TEXTURE_CUBE:
201 case PIPE_TEXTURE_CUBE_ARRAY:
202 return V_030000_SQ_TEX_DIM_CUBEMAP;
203 }
204 }
205
206 static uint32_t r600_translate_dbformat(enum pipe_format format)
207 {
208 switch (format) {
209 case PIPE_FORMAT_Z16_UNORM:
210 return V_028040_Z_16;
211 case PIPE_FORMAT_Z24X8_UNORM:
212 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
213 case PIPE_FORMAT_X8Z24_UNORM:
214 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
215 return V_028040_Z_24;
216 case PIPE_FORMAT_Z32_FLOAT:
217 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
218 return V_028040_Z_32_FLOAT;
219 default:
220 return ~0U;
221 }
222 }
223
224 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
225 {
226 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
227 FALSE) != ~0U;
228 }
229
230 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
231 {
232 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
233 r600_translate_colorswap(format, FALSE) != ~0U;
234 }
235
236 static bool r600_is_zs_format_supported(enum pipe_format format)
237 {
238 return r600_translate_dbformat(format) != ~0U;
239 }
240
241 boolean evergreen_is_format_supported(struct pipe_screen *screen,
242 enum pipe_format format,
243 enum pipe_texture_target target,
244 unsigned sample_count,
245 unsigned usage)
246 {
247 struct r600_screen *rscreen = (struct r600_screen*)screen;
248 unsigned retval = 0;
249
250 if (target >= PIPE_MAX_TEXTURE_TYPES) {
251 R600_ERR("r600: unsupported texture type %d\n", target);
252 return FALSE;
253 }
254
255 if (!util_format_is_supported(format, usage))
256 return FALSE;
257
258 if (sample_count > 1) {
259 if (!rscreen->has_msaa)
260 return FALSE;
261
262 switch (sample_count) {
263 case 2:
264 case 4:
265 case 8:
266 break;
267 default:
268 return FALSE;
269 }
270 }
271
272 if (usage & PIPE_BIND_SAMPLER_VIEW) {
273 if (target == PIPE_BUFFER) {
274 if (r600_is_vertex_format_supported(format))
275 retval |= PIPE_BIND_SAMPLER_VIEW;
276 } else {
277 if (r600_is_sampler_format_supported(screen, format))
278 retval |= PIPE_BIND_SAMPLER_VIEW;
279 }
280 }
281
282 if ((usage & (PIPE_BIND_RENDER_TARGET |
283 PIPE_BIND_DISPLAY_TARGET |
284 PIPE_BIND_SCANOUT |
285 PIPE_BIND_SHARED |
286 PIPE_BIND_BLENDABLE)) &&
287 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
288 retval |= usage &
289 (PIPE_BIND_RENDER_TARGET |
290 PIPE_BIND_DISPLAY_TARGET |
291 PIPE_BIND_SCANOUT |
292 PIPE_BIND_SHARED);
293 if (!util_format_is_pure_integer(format) &&
294 !util_format_is_depth_or_stencil(format))
295 retval |= usage & PIPE_BIND_BLENDABLE;
296 }
297
298 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
299 r600_is_zs_format_supported(format)) {
300 retval |= PIPE_BIND_DEPTH_STENCIL;
301 }
302
303 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
304 r600_is_vertex_format_supported(format)) {
305 retval |= PIPE_BIND_VERTEX_BUFFER;
306 }
307
308 if ((usage & PIPE_BIND_LINEAR) &&
309 !util_format_is_compressed(format) &&
310 !(usage & PIPE_BIND_DEPTH_STENCIL))
311 retval |= PIPE_BIND_LINEAR;
312
313 return retval == usage;
314 }
315
316 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
317 const struct pipe_blend_state *state, int mode)
318 {
319 uint32_t color_control = 0, target_mask = 0;
320 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
321
322 if (!blend) {
323 return NULL;
324 }
325
326 r600_init_command_buffer(&blend->buffer, 20);
327 r600_init_command_buffer(&blend->buffer_no_blend, 20);
328
329 if (state->logicop_enable) {
330 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
331 } else {
332 color_control |= (0xcc << 16);
333 }
334 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
335 if (state->independent_blend_enable) {
336 for (int i = 0; i < 8; i++) {
337 target_mask |= (state->rt[i].colormask << (4 * i));
338 }
339 } else {
340 for (int i = 0; i < 8; i++) {
341 target_mask |= (state->rt[0].colormask << (4 * i));
342 }
343 }
344
345 /* only have dual source on MRT0 */
346 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
347 blend->cb_target_mask = target_mask;
348 blend->alpha_to_one = state->alpha_to_one;
349
350 if (target_mask)
351 color_control |= S_028808_MODE(mode);
352 else
353 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
354
355
356 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
357 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
358 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
359 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
360 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
361 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
362 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
363 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
364
365 /* Copy over the dwords set so far into buffer_no_blend.
366 * Only the CB_BLENDi_CONTROL registers must be set after this. */
367 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
368 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
369
370 for (int i = 0; i < 8; i++) {
371 /* state->rt entries > 0 only written if independent blending */
372 const int j = state->independent_blend_enable ? i : 0;
373
374 unsigned eqRGB = state->rt[j].rgb_func;
375 unsigned srcRGB = state->rt[j].rgb_src_factor;
376 unsigned dstRGB = state->rt[j].rgb_dst_factor;
377 unsigned eqA = state->rt[j].alpha_func;
378 unsigned srcA = state->rt[j].alpha_src_factor;
379 unsigned dstA = state->rt[j].alpha_dst_factor;
380 uint32_t bc = 0;
381
382 r600_store_value(&blend->buffer_no_blend, 0);
383
384 if (!state->rt[j].blend_enable) {
385 r600_store_value(&blend->buffer, 0);
386 continue;
387 }
388
389 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
390 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
391 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
392 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
393
394 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
395 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
396 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
397 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
398 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
399 }
400 r600_store_value(&blend->buffer, bc);
401 }
402 return blend;
403 }
404
405 static void *evergreen_create_blend_state(struct pipe_context *ctx,
406 const struct pipe_blend_state *state)
407 {
408
409 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
410 }
411
412 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
413 const struct pipe_depth_stencil_alpha_state *state)
414 {
415 unsigned db_depth_control, alpha_test_control, alpha_ref;
416 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
417
418 if (!dsa) {
419 return NULL;
420 }
421
422 r600_init_command_buffer(&dsa->buffer, 3);
423
424 dsa->valuemask[0] = state->stencil[0].valuemask;
425 dsa->valuemask[1] = state->stencil[1].valuemask;
426 dsa->writemask[0] = state->stencil[0].writemask;
427 dsa->writemask[1] = state->stencil[1].writemask;
428 dsa->zwritemask = state->depth.writemask;
429
430 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
431 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
432 S_028800_ZFUNC(state->depth.func);
433
434 /* stencil */
435 if (state->stencil[0].enabled) {
436 db_depth_control |= S_028800_STENCIL_ENABLE(1);
437 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
438 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
439 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
440 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
441
442 if (state->stencil[1].enabled) {
443 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
444 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
445 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
446 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
447 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
448 }
449 }
450
451 /* alpha */
452 alpha_test_control = 0;
453 alpha_ref = 0;
454 if (state->alpha.enabled) {
455 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
456 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
457 alpha_ref = fui(state->alpha.ref_value);
458 }
459 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
460 dsa->alpha_ref = alpha_ref;
461
462 /* misc */
463 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
464 return dsa;
465 }
466
467 static void *evergreen_create_rs_state(struct pipe_context *ctx,
468 const struct pipe_rasterizer_state *state)
469 {
470 struct r600_context *rctx = (struct r600_context *)ctx;
471 unsigned tmp, spi_interp;
472 float psize_min, psize_max;
473 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
474
475 if (!rs) {
476 return NULL;
477 }
478
479 r600_init_command_buffer(&rs->buffer, 30);
480
481 rs->scissor_enable = state->scissor;
482 rs->clip_halfz = state->clip_halfz;
483 rs->flatshade = state->flatshade;
484 rs->sprite_coord_enable = state->sprite_coord_enable;
485 rs->rasterizer_discard = state->rasterizer_discard;
486 rs->two_side = state->light_twoside;
487 rs->clip_plane_enable = state->clip_plane_enable;
488 rs->pa_sc_line_stipple = state->line_stipple_enable ?
489 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
490 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
491 rs->pa_cl_clip_cntl =
492 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
493 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
494 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
495 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
496 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
497 rs->multisample_enable = state->multisample;
498
499 /* offset */
500 rs->offset_units = state->offset_units;
501 rs->offset_scale = state->offset_scale * 16.0f;
502 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
503 rs->offset_units_unscaled = state->offset_units_unscaled;
504
505 if (state->point_size_per_vertex) {
506 psize_min = util_get_min_point_size(state);
507 psize_max = 8192;
508 } else {
509 /* Force the point size to be as if the vertex output was disabled. */
510 psize_min = state->point_size;
511 psize_max = state->point_size;
512 }
513
514 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
515 if (state->sprite_coord_enable) {
516 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
517 S_0286D4_PNT_SPRITE_OVRD_X(2) |
518 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
519 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
520 S_0286D4_PNT_SPRITE_OVRD_W(1);
521 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
522 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
523 }
524 }
525
526 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
527 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
528 tmp = r600_pack_float_12p4(state->point_size/2);
529 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
530 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
531 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
532 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
533 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
534 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
535 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
536
537 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
538 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
539 S_028A48_MSAA_ENABLE(state->multisample) |
540 S_028A48_VPORT_SCISSOR_ENABLE(1) |
541 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
542
543 if (rctx->b.chip_class == CAYMAN) {
544 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
545 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
546 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
547 } else {
548 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
549 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
550 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
551 }
552
553 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
554 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
555 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
556 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
557 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
558 S_028814_FACE(!state->front_ccw) |
559 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
560 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
561 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
562 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
563 state->fill_back != PIPE_POLYGON_MODE_FILL) |
564 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
565 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
566 return rs;
567 }
568
569 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
570 const struct pipe_sampler_state *state)
571 {
572 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
573 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
574 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
575 : state->max_anisotropy;
576 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
577
578 if (!ss) {
579 return NULL;
580 }
581
582 ss->border_color_use = sampler_state_needs_border_color(state);
583
584 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
585 ss->tex_sampler_words[0] =
586 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
587 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
588 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
589 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
590 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
591 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
592 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
593 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
594 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
595 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
596 ss->tex_sampler_words[1] =
597 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
598 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
599 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
600 ss->tex_sampler_words[2] =
601 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
602 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
603 S_03C008_TYPE(1);
604
605 if (ss->border_color_use) {
606 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
607 }
608 return ss;
609 }
610
611 struct eg_buf_res_params {
612 enum pipe_format pipe_format;
613 unsigned offset;
614 unsigned size;
615 unsigned char swizzle[4];
616 bool uncached;
617 bool force_swizzle;
618 };
619
620 static void evergreen_fill_buffer_resource_words(struct r600_context *rctx,
621 struct pipe_resource *buffer,
622 struct eg_buf_res_params *params,
623 bool *skip_mip_address_reloc,
624 unsigned tex_resource_words[8])
625 {
626 struct r600_texture *tmp = (struct r600_texture*)buffer;
627 uint64_t va;
628 int stride = util_format_get_blocksize(params->pipe_format);
629 unsigned format, num_format, format_comp, endian;
630 unsigned swizzle_res;
631 const struct util_format_description *desc;
632
633 r600_vertex_data_type(params->pipe_format,
634 &format, &num_format, &format_comp,
635 &endian);
636
637 desc = util_format_description(params->pipe_format);
638
639 if (params->force_swizzle)
640 swizzle_res = r600_get_swizzle_combined(params->swizzle, NULL, TRUE);
641 else
642 swizzle_res = r600_get_swizzle_combined(desc->swizzle, params->swizzle, TRUE);
643
644 va = tmp->resource.gpu_address + params->offset;
645 *skip_mip_address_reloc = true;
646 tex_resource_words[0] = va;
647 tex_resource_words[1] = params->size - 1;
648 tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
649 S_030008_STRIDE(stride) |
650 S_030008_DATA_FORMAT(format) |
651 S_030008_NUM_FORMAT_ALL(num_format) |
652 S_030008_FORMAT_COMP_ALL(format_comp) |
653 S_030008_ENDIAN_SWAP(endian);
654 tex_resource_words[3] = swizzle_res | S_03000C_UNCACHED(params->uncached);
655 /*
656 * dword 4 is for number of elements, for use with resinfo,
657 * albeit the amd gpu shader analyser
658 * uses a const buffer to store the element sizes for buffer txq
659 */
660 tex_resource_words[4] = params->size / stride;
661
662 tex_resource_words[5] = tex_resource_words[6] = 0;
663 tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
664 }
665
666 static struct pipe_sampler_view *
667 texture_buffer_sampler_view(struct r600_context *rctx,
668 struct r600_pipe_sampler_view *view,
669 unsigned width0, unsigned height0)
670 {
671 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
672 struct eg_buf_res_params params;
673
674 memset(&params, 0, sizeof(params));
675
676 params.pipe_format = view->base.format;
677 params.offset = view->base.u.buf.offset;
678 params.size = view->base.u.buf.size;
679 params.swizzle[0] = view->base.swizzle_r;
680 params.swizzle[1] = view->base.swizzle_g;
681 params.swizzle[2] = view->base.swizzle_b;
682 params.swizzle[3] = view->base.swizzle_a;
683
684 evergreen_fill_buffer_resource_words(rctx, view->base.texture,
685 &params, &view->skip_mip_address_reloc,
686 view->tex_resource_words);
687 view->tex_resource = &tmp->resource;
688
689 if (tmp->resource.gpu_address)
690 LIST_ADDTAIL(&view->list, &rctx->texture_buffers);
691 return &view->base;
692 }
693
694 struct eg_tex_res_params {
695 enum pipe_format pipe_format;
696 int force_level;
697 unsigned width0;
698 unsigned height0;
699 unsigned first_level;
700 unsigned last_level;
701 unsigned first_layer;
702 unsigned last_layer;
703 unsigned target;
704 unsigned char swizzle[4];
705 };
706
707 static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
708 struct pipe_resource *texture,
709 struct eg_tex_res_params *params,
710 bool *skip_mip_address_reloc,
711 unsigned tex_resource_words[8])
712 {
713 struct r600_screen *rscreen = (struct r600_screen*)rctx->b.b.screen;
714 struct r600_texture *tmp = (struct r600_texture*)texture;
715 unsigned format, endian;
716 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
717 unsigned char array_mode = 0, non_disp_tiling = 0;
718 unsigned height, depth, width;
719 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
720 struct legacy_surf_level *surflevel;
721 unsigned base_level, first_level, last_level;
722 unsigned dim, last_layer;
723 uint64_t va;
724 bool do_endian_swap = FALSE;
725
726 tile_split = tmp->surface.u.legacy.tile_split;
727 surflevel = tmp->surface.u.legacy.level;
728
729 /* Texturing with separate depth and stencil. */
730 if (tmp->db_compatible) {
731 switch (params->pipe_format) {
732 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
733 params->pipe_format = PIPE_FORMAT_Z32_FLOAT;
734 break;
735 case PIPE_FORMAT_X8Z24_UNORM:
736 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
737 /* Z24 is always stored like this for DB
738 * compatibility.
739 */
740 params->pipe_format = PIPE_FORMAT_Z24X8_UNORM;
741 break;
742 case PIPE_FORMAT_X24S8_UINT:
743 case PIPE_FORMAT_S8X24_UINT:
744 case PIPE_FORMAT_X32_S8X24_UINT:
745 params->pipe_format = PIPE_FORMAT_S8_UINT;
746 tile_split = tmp->surface.u.legacy.stencil_tile_split;
747 surflevel = tmp->surface.u.legacy.stencil_level;
748 break;
749 default:;
750 }
751 }
752
753 if (R600_BIG_ENDIAN)
754 do_endian_swap = !tmp->db_compatible;
755
756 format = r600_translate_texformat(rctx->b.b.screen, params->pipe_format,
757 params->swizzle,
758 &word4, &yuv_format, do_endian_swap);
759 assert(format != ~0);
760 if (format == ~0) {
761 return -1;
762 }
763
764 endian = r600_colorformat_endian_swap(format, do_endian_swap);
765
766 base_level = 0;
767 first_level = params->first_level;
768 last_level = params->last_level;
769 width = params->width0;
770 height = params->height0;
771 depth = texture->depth0;
772
773 if (params->force_level) {
774 base_level = params->force_level;
775 first_level = 0;
776 last_level = 0;
777 width = u_minify(width, params->force_level);
778 height = u_minify(height, params->force_level);
779 depth = u_minify(depth, params->force_level);
780 }
781
782 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(params->pipe_format);
783 non_disp_tiling = tmp->non_disp_tiling;
784
785 switch (surflevel[base_level].mode) {
786 default:
787 case RADEON_SURF_MODE_LINEAR_ALIGNED:
788 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
789 break;
790 case RADEON_SURF_MODE_2D:
791 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
792 break;
793 case RADEON_SURF_MODE_1D:
794 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
795 break;
796 }
797 macro_aspect = tmp->surface.u.legacy.mtilea;
798 bankw = tmp->surface.u.legacy.bankw;
799 bankh = tmp->surface.u.legacy.bankh;
800 tile_split = eg_tile_split(tile_split);
801 macro_aspect = eg_macro_tile_aspect(macro_aspect);
802 bankw = eg_bank_wh(bankw);
803 bankh = eg_bank_wh(bankh);
804 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
805
806 /* 128 bit formats require tile type = 1 */
807 if (rscreen->b.chip_class == CAYMAN) {
808 if (util_format_get_blocksize(params->pipe_format) >= 16)
809 non_disp_tiling = 1;
810 }
811 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
812
813 if (params->target == PIPE_TEXTURE_1D_ARRAY) {
814 height = 1;
815 depth = texture->array_size;
816 } else if (params->target == PIPE_TEXTURE_2D_ARRAY) {
817 depth = texture->array_size;
818 } else if (params->target == PIPE_TEXTURE_CUBE_ARRAY)
819 depth = texture->array_size / 6;
820
821 va = tmp->resource.gpu_address;
822
823 /* array type views and views into array types need to use layer offset */
824 dim = r600_tex_dim(tmp, params->target, texture->nr_samples);
825 tex_resource_words[0] = (S_030000_DIM(dim) |
826 S_030000_PITCH((pitch / 8) - 1) |
827 S_030000_TEX_WIDTH(width - 1));
828 if (rscreen->b.chip_class == CAYMAN)
829 tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
830 else
831 tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
832 tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
833 S_030004_TEX_DEPTH(depth - 1) |
834 S_030004_ARRAY_MODE(array_mode));
835 tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
836
837 *skip_mip_address_reloc = false;
838 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
839 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
840 if (tmp->is_depth) {
841 /* disable FMASK (0 = disabled) */
842 tex_resource_words[3] = 0;
843 *skip_mip_address_reloc = true;
844 } else {
845 /* FMASK should be in MIP_ADDRESS for multisample textures */
846 tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
847 }
848 } else if (last_level && texture->nr_samples <= 1) {
849 tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
850 } else {
851 tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
852 }
853
854 last_layer = params->last_layer;
855 if (params->target != texture->target && depth == 1) {
856 last_layer = params->first_layer;
857 }
858 tex_resource_words[4] = (word4 |
859 S_030010_ENDIAN_SWAP(endian));
860 tex_resource_words[5] = S_030014_BASE_ARRAY(params->first_layer) |
861 S_030014_LAST_ARRAY(last_layer);
862 tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
863
864 if (texture->nr_samples > 1) {
865 unsigned log_samples = util_logbase2(texture->nr_samples);
866 if (rscreen->b.chip_class == CAYMAN) {
867 tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
868 }
869 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
870 tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
871 tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
872 } else {
873 bool no_mip = first_level == last_level;
874
875 tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
876 tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
877 /* aniso max 16 samples */
878 tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
879 }
880
881 tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
882 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
883 S_03001C_BANK_WIDTH(bankw) |
884 S_03001C_BANK_HEIGHT(bankh) |
885 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
886 S_03001C_NUM_BANKS(nbanks) |
887 S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible);
888 return 0;
889 }
890
891 struct pipe_sampler_view *
892 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
893 struct pipe_resource *texture,
894 const struct pipe_sampler_view *state,
895 unsigned width0, unsigned height0,
896 unsigned force_level)
897 {
898 struct r600_context *rctx = (struct r600_context*)ctx;
899 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
900 struct r600_texture *tmp = (struct r600_texture*)texture;
901 struct eg_tex_res_params params;
902 int ret;
903
904 if (!view)
905 return NULL;
906
907 /* initialize base object */
908 view->base = *state;
909 view->base.texture = NULL;
910 pipe_reference(NULL, &texture->reference);
911 view->base.texture = texture;
912 view->base.reference.count = 1;
913 view->base.context = ctx;
914
915 if (state->target == PIPE_BUFFER)
916 return texture_buffer_sampler_view(rctx, view, width0, height0);
917
918 memset(&params, 0, sizeof(params));
919 params.pipe_format = state->format;
920 params.force_level = force_level;
921 params.width0 = width0;
922 params.height0 = height0;
923 params.first_level = state->u.tex.first_level;
924 params.last_level = state->u.tex.last_level;
925 params.first_layer = state->u.tex.first_layer;
926 params.last_layer = state->u.tex.last_layer;
927 params.target = state->target;
928 params.swizzle[0] = state->swizzle_r;
929 params.swizzle[1] = state->swizzle_g;
930 params.swizzle[2] = state->swizzle_b;
931 params.swizzle[3] = state->swizzle_a;
932
933 ret = evergreen_fill_tex_resource_words(rctx, texture, &params,
934 &view->skip_mip_address_reloc,
935 view->tex_resource_words);
936 if (ret != 0) {
937 FREE(view);
938 return NULL;
939 }
940
941 if (state->format == PIPE_FORMAT_X24S8_UINT ||
942 state->format == PIPE_FORMAT_S8X24_UINT ||
943 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
944 state->format == PIPE_FORMAT_S8_UINT)
945 view->is_stencil_sampler = true;
946
947 view->tex_resource = &tmp->resource;
948
949 return &view->base;
950 }
951
952 static struct pipe_sampler_view *
953 evergreen_create_sampler_view(struct pipe_context *ctx,
954 struct pipe_resource *tex,
955 const struct pipe_sampler_view *state)
956 {
957 return evergreen_create_sampler_view_custom(ctx, tex, state,
958 tex->width0, tex->height0, 0);
959 }
960
961 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
962 {
963 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
964 struct r600_config_state *a = (struct r600_config_state*)atom;
965
966 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
967 if (a->dyn_gpr_enabled) {
968 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
969 radeon_emit(cs, 0);
970 radeon_emit(cs, 0);
971 } else {
972 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
973 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
974 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
975 }
976 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
977 if (a->dyn_gpr_enabled) {
978 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
979 S_028838_PS_GPRS(0x1e) |
980 S_028838_VS_GPRS(0x1e) |
981 S_028838_GS_GPRS(0x1e) |
982 S_028838_ES_GPRS(0x1e) |
983 S_028838_HS_GPRS(0x1e) |
984 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
985 }
986 }
987
988 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
989 {
990 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
991 struct pipe_clip_state *state = &rctx->clip_state.state;
992
993 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
994 radeon_emit_array(cs, (unsigned*)state, 6*4);
995 }
996
997 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
998 const struct pipe_poly_stipple *state)
999 {
1000 }
1001
1002 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1003 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1004 uint32_t *tl, uint32_t *br)
1005 {
1006 struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
1007
1008 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
1009
1010 *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
1011 *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
1012 }
1013
1014 struct r600_tex_color_info {
1015 unsigned info;
1016 unsigned view;
1017 unsigned dim;
1018 unsigned pitch;
1019 unsigned slice;
1020 unsigned attrib;
1021 unsigned ntype;
1022 unsigned fmask;
1023 unsigned fmask_slice;
1024 uint64_t offset;
1025 boolean export_16bpc;
1026 };
1027
1028 static void evergreen_set_color_surface_buffer(struct r600_context *rctx,
1029 struct r600_resource *res,
1030 enum pipe_format pformat,
1031 unsigned first_element,
1032 unsigned last_element,
1033 struct r600_tex_color_info *color)
1034 {
1035 unsigned format, swap, ntype, endian;
1036 const struct util_format_description *desc;
1037 unsigned block_size = util_format_get_blocksize(res->b.b.format);
1038 unsigned pitch_alignment =
1039 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
1040 unsigned pitch = align(res->b.b.width0, pitch_alignment);
1041 int i;
1042 unsigned width_elements;
1043
1044 width_elements = last_element - first_element + 1;
1045
1046 format = r600_translate_colorformat(rctx->b.chip_class, pformat, FALSE);
1047 swap = r600_translate_colorswap(pformat, FALSE);
1048
1049 endian = r600_colorformat_endian_swap(format, FALSE);
1050
1051 desc = util_format_description(pformat);
1052 for (i = 0; i < 4; i++) {
1053 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1054 break;
1055 }
1056 }
1057 ntype = V_028C70_NUMBER_UNORM;
1058 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1059 ntype = V_028C70_NUMBER_SRGB;
1060 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1061 if (desc->channel[i].normalized)
1062 ntype = V_028C70_NUMBER_SNORM;
1063 else if (desc->channel[i].pure_integer)
1064 ntype = V_028C70_NUMBER_SINT;
1065 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1066 if (desc->channel[i].normalized)
1067 ntype = V_028C70_NUMBER_UNORM;
1068 else if (desc->channel[i].pure_integer)
1069 ntype = V_028C70_NUMBER_UINT;
1070 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1071 ntype = V_028C70_NUMBER_FLOAT;
1072 }
1073
1074 pitch = (pitch / 8) - 1;
1075 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1076
1077 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1078 color->info |= S_028C70_FORMAT(format) |
1079 S_028C70_COMP_SWAP(swap) |
1080 S_028C70_BLEND_CLAMP(0) |
1081 S_028C70_BLEND_BYPASS(1) |
1082 S_028C70_NUMBER_TYPE(ntype) |
1083 S_028C70_ENDIAN(endian);
1084 color->attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1085 color->ntype = ntype;
1086 color->export_16bpc = false;
1087 color->dim = width_elements - 1;
1088 color->slice = 0; /* (width_elements / 64) - 1;*/
1089 color->view = 0;
1090 color->offset = (res->gpu_address + first_element) >> 8;
1091
1092 color->fmask = color->offset;
1093 color->fmask_slice = 0;
1094 }
1095
1096 static void evergreen_set_color_surface_common(struct r600_context *rctx,
1097 struct r600_texture *rtex,
1098 unsigned level,
1099 unsigned first_layer,
1100 unsigned last_layer,
1101 enum pipe_format pformat,
1102 struct r600_tex_color_info *color)
1103 {
1104 struct r600_screen *rscreen = rctx->screen;
1105 unsigned pitch, slice;
1106 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1107 unsigned format, swap, ntype, endian;
1108 const struct util_format_description *desc;
1109 bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
1110 int i;
1111
1112 color->offset = rtex->surface.u.legacy.level[level].offset;
1113 color->view = S_028C6C_SLICE_START(first_layer) |
1114 S_028C6C_SLICE_MAX(last_layer);
1115
1116 color->offset += rtex->resource.gpu_address;
1117 color->offset >>= 8;
1118
1119 color->dim = 0;
1120 pitch = (rtex->surface.u.legacy.level[level].nblk_x) / 8 - 1;
1121 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1122 if (slice) {
1123 slice = slice - 1;
1124 }
1125
1126 color->info = 0;
1127 switch (rtex->surface.u.legacy.level[level].mode) {
1128 default:
1129 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1130 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1131 non_disp_tiling = 1;
1132 break;
1133 case RADEON_SURF_MODE_1D:
1134 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1135 non_disp_tiling = rtex->non_disp_tiling;
1136 break;
1137 case RADEON_SURF_MODE_2D:
1138 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1139 non_disp_tiling = rtex->non_disp_tiling;
1140 break;
1141 }
1142 tile_split = rtex->surface.u.legacy.tile_split;
1143 macro_aspect = rtex->surface.u.legacy.mtilea;
1144 bankw = rtex->surface.u.legacy.bankw;
1145 bankh = rtex->surface.u.legacy.bankh;
1146 if (rtex->fmask.size)
1147 fmask_bankh = rtex->fmask.bank_height;
1148 else
1149 fmask_bankh = rtex->surface.u.legacy.bankh;
1150 tile_split = eg_tile_split(tile_split);
1151 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1152 bankw = eg_bank_wh(bankw);
1153 bankh = eg_bank_wh(bankh);
1154 fmask_bankh = eg_bank_wh(fmask_bankh);
1155
1156 if (rscreen->b.chip_class == CAYMAN) {
1157 if (util_format_get_blocksize(pformat) >= 16)
1158 non_disp_tiling = 1;
1159 }
1160 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1161 desc = util_format_description(pformat);
1162 for (i = 0; i < 4; i++) {
1163 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1164 break;
1165 }
1166 }
1167 color->attrib = S_028C74_TILE_SPLIT(tile_split)|
1168 S_028C74_NUM_BANKS(nbanks) |
1169 S_028C74_BANK_WIDTH(bankw) |
1170 S_028C74_BANK_HEIGHT(bankh) |
1171 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1172 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1173 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1174
1175 if (rctx->b.chip_class == CAYMAN) {
1176 color->attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1177 PIPE_SWIZZLE_1);
1178
1179 if (rtex->resource.b.b.nr_samples > 1) {
1180 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1181 color->attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1182 S_028C74_NUM_FRAGMENTS(log_samples);
1183 }
1184 }
1185
1186 ntype = V_028C70_NUMBER_UNORM;
1187 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1188 ntype = V_028C70_NUMBER_SRGB;
1189 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1190 if (desc->channel[i].normalized)
1191 ntype = V_028C70_NUMBER_SNORM;
1192 else if (desc->channel[i].pure_integer)
1193 ntype = V_028C70_NUMBER_SINT;
1194 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1195 if (desc->channel[i].normalized)
1196 ntype = V_028C70_NUMBER_UNORM;
1197 else if (desc->channel[i].pure_integer)
1198 ntype = V_028C70_NUMBER_UINT;
1199 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1200 ntype = V_028C70_NUMBER_FLOAT;
1201 }
1202
1203 if (R600_BIG_ENDIAN)
1204 do_endian_swap = !rtex->db_compatible;
1205
1206 format = r600_translate_colorformat(rctx->b.chip_class, pformat, do_endian_swap);
1207 assert(format != ~0);
1208 swap = r600_translate_colorswap(pformat, do_endian_swap);
1209 assert(swap != ~0);
1210
1211 endian = r600_colorformat_endian_swap(format, do_endian_swap);
1212
1213 /* blend clamp should be set for all NORM/SRGB types */
1214 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1215 ntype == V_028C70_NUMBER_SRGB)
1216 blend_clamp = 1;
1217
1218 /* set blend bypass according to docs if SINT/UINT or
1219 8/24 COLOR variants */
1220 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1221 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1222 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1223 blend_clamp = 0;
1224 blend_bypass = 1;
1225 }
1226
1227 color->ntype = ntype;
1228 color->info |= S_028C70_FORMAT(format) |
1229 S_028C70_COMP_SWAP(swap) |
1230 S_028C70_BLEND_CLAMP(blend_clamp) |
1231 S_028C70_BLEND_BYPASS(blend_bypass) |
1232 S_028C70_SIMPLE_FLOAT(1) |
1233 S_028C70_NUMBER_TYPE(ntype) |
1234 S_028C70_ENDIAN(endian);
1235
1236 if (rtex->fmask.size) {
1237 color->info |= S_028C70_COMPRESSION(1);
1238 }
1239
1240 /* EXPORT_NORM is an optimzation that can be enabled for better
1241 * performance in certain cases.
1242 * EXPORT_NORM can be enabled if:
1243 * - 11-bit or smaller UNORM/SNORM/SRGB
1244 * - 16-bit or smaller FLOAT
1245 */
1246 color->export_16bpc = false;
1247 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1248 ((desc->channel[i].size < 12 &&
1249 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1250 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1251 (desc->channel[i].size < 17 &&
1252 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1253 color->info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1254 color->export_16bpc = true;
1255 }
1256
1257 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1258 color->slice = S_028C68_SLICE_TILE_MAX(slice);
1259
1260 if (rtex->fmask.size) {
1261 color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8;
1262 color->fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1263 } else {
1264 color->fmask = color->offset;
1265 color->fmask_slice = S_028C88_TILE_MAX(slice);
1266 }
1267 }
1268
1269 /**
1270 * This function intializes the CB* register values for RATs. It is meant
1271 * to be used for 1D aligned buffers that do not have an associated
1272 * radeon_surf.
1273 */
1274 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1275 struct r600_surface *surf)
1276 {
1277 struct pipe_resource *pipe_buffer = surf->base.texture;
1278 struct r600_tex_color_info color;
1279
1280 evergreen_set_color_surface_buffer(rctx, (struct r600_resource *)surf->base.texture,
1281 surf->base.format, 0, pipe_buffer->width0,
1282 &color);
1283
1284 surf->cb_color_base = color.offset;
1285 surf->cb_color_dim = color.dim;
1286 surf->cb_color_info = color.info | S_028C70_RAT(1);
1287 surf->cb_color_pitch = color.pitch;
1288 surf->cb_color_slice = color.slice;
1289 surf->cb_color_view = color.view;
1290 surf->cb_color_attrib = color.attrib;
1291 surf->cb_color_fmask = color.fmask;
1292 surf->cb_color_fmask_slice = color.fmask_slice;
1293
1294 surf->cb_color_view = 0;
1295
1296 /* Set the buffer range the GPU will have access to: */
1297 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
1298 0, pipe_buffer->width0);
1299 }
1300
1301
1302 void evergreen_init_color_surface(struct r600_context *rctx,
1303 struct r600_surface *surf)
1304 {
1305 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1306 unsigned level = surf->base.u.tex.level;
1307 struct r600_tex_color_info color;
1308
1309 evergreen_set_color_surface_common(rctx, rtex, level,
1310 surf->base.u.tex.first_layer,
1311 surf->base.u.tex.last_layer,
1312 surf->base.format,
1313 &color);
1314
1315 surf->alphatest_bypass = color.ntype == V_028C70_NUMBER_UINT ||
1316 color.ntype == V_028C70_NUMBER_SINT;
1317 surf->export_16bpc = color.export_16bpc;
1318
1319 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1320 surf->cb_color_base = color.offset;
1321 surf->cb_color_dim = color.dim;
1322 surf->cb_color_info = color.info;
1323 surf->cb_color_pitch = color.pitch;
1324 surf->cb_color_slice = color.slice;
1325 surf->cb_color_view = color.view;
1326 surf->cb_color_attrib = color.attrib;
1327 surf->cb_color_fmask = color.fmask;
1328 surf->cb_color_fmask_slice = color.fmask_slice;
1329
1330 surf->color_initialized = true;
1331 }
1332
1333 static void evergreen_init_depth_surface(struct r600_context *rctx,
1334 struct r600_surface *surf)
1335 {
1336 struct r600_screen *rscreen = rctx->screen;
1337 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1338 unsigned level = surf->base.u.tex.level;
1339 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
1340 uint64_t offset;
1341 unsigned format, array_mode;
1342 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1343
1344
1345 format = r600_translate_dbformat(surf->base.format);
1346 assert(format != ~0);
1347
1348 offset = rtex->resource.gpu_address;
1349 offset += rtex->surface.u.legacy.level[level].offset;
1350
1351 switch (rtex->surface.u.legacy.level[level].mode) {
1352 case RADEON_SURF_MODE_2D:
1353 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1354 break;
1355 case RADEON_SURF_MODE_1D:
1356 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1357 default:
1358 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1359 break;
1360 }
1361 tile_split = rtex->surface.u.legacy.tile_split;
1362 macro_aspect = rtex->surface.u.legacy.mtilea;
1363 bankw = rtex->surface.u.legacy.bankw;
1364 bankh = rtex->surface.u.legacy.bankh;
1365 tile_split = eg_tile_split(tile_split);
1366 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1367 bankw = eg_bank_wh(bankw);
1368 bankh = eg_bank_wh(bankh);
1369 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1370 offset >>= 8;
1371
1372 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1373 S_028040_FORMAT(format) |
1374 S_028040_TILE_SPLIT(tile_split)|
1375 S_028040_NUM_BANKS(nbanks) |
1376 S_028040_BANK_WIDTH(bankw) |
1377 S_028040_BANK_HEIGHT(bankh) |
1378 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1379 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1380 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1381 }
1382
1383 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1384
1385 surf->db_depth_base = offset;
1386 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1387 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1388 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1389 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1390 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1391 levelinfo->nblk_y / 64 - 1);
1392
1393 if (rtex->surface.has_stencil) {
1394 uint64_t stencil_offset;
1395 unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split;
1396
1397 stile_split = eg_tile_split(stile_split);
1398
1399 stencil_offset = rtex->surface.u.legacy.stencil_level[level].offset;
1400 stencil_offset += rtex->resource.gpu_address;
1401
1402 surf->db_stencil_base = stencil_offset >> 8;
1403 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1404 S_028044_TILE_SPLIT(stile_split);
1405 } else {
1406 surf->db_stencil_base = offset;
1407 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1408 * Older kernels are out of luck. */
1409 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1410 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1411 S_028044_FORMAT(V_028044_STENCIL_8);
1412 }
1413
1414 if (r600_htile_enabled(rtex, level)) {
1415 uint64_t va = rtex->resource.gpu_address + rtex->htile_offset;
1416 surf->db_htile_data_base = va >> 8;
1417 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1418 S_028ABC_HTILE_HEIGHT(1) |
1419 S_028ABC_FULL_CACHE(1);
1420 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1421 surf->db_preload_control = 0;
1422 }
1423
1424 surf->depth_initialized = true;
1425 }
1426
1427 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1428 const struct pipe_framebuffer_state *state)
1429 {
1430 struct r600_context *rctx = (struct r600_context *)ctx;
1431 struct r600_surface *surf;
1432 struct r600_texture *rtex;
1433 uint32_t i, log_samples;
1434
1435 /* Flush TC when changing the framebuffer state, because the only
1436 * client not using TC that can change textures is the framebuffer.
1437 * Other places don't typically have to flush TC.
1438 */
1439 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1440 R600_CONTEXT_FLUSH_AND_INV |
1441 R600_CONTEXT_FLUSH_AND_INV_CB |
1442 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1443 R600_CONTEXT_FLUSH_AND_INV_DB |
1444 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1445 R600_CONTEXT_INV_TEX_CACHE;
1446
1447 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1448
1449 /* Colorbuffers. */
1450 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1451 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1452 util_format_is_pure_integer(state->cbufs[0]->format);
1453 rctx->framebuffer.compressed_cb_mask = 0;
1454 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1455
1456 for (i = 0; i < state->nr_cbufs; i++) {
1457 surf = (struct r600_surface*)state->cbufs[i];
1458 if (!surf)
1459 continue;
1460
1461 rtex = (struct r600_texture*)surf->base.texture;
1462
1463 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1464
1465 if (!surf->color_initialized) {
1466 evergreen_init_color_surface(rctx, surf);
1467 }
1468
1469 if (!surf->export_16bpc) {
1470 rctx->framebuffer.export_16bpc = false;
1471 }
1472
1473 if (rtex->fmask.size) {
1474 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1475 }
1476 }
1477
1478 /* Update alpha-test state dependencies.
1479 * Alpha-test is done on the first colorbuffer only. */
1480 if (state->nr_cbufs) {
1481 bool alphatest_bypass = false;
1482 bool export_16bpc = true;
1483
1484 surf = (struct r600_surface*)state->cbufs[0];
1485 if (surf) {
1486 alphatest_bypass = surf->alphatest_bypass;
1487 export_16bpc = surf->export_16bpc;
1488 }
1489
1490 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1491 rctx->alphatest_state.bypass = alphatest_bypass;
1492 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1493 }
1494 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1495 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1496 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1497 }
1498 }
1499
1500 /* ZS buffer. */
1501 if (state->zsbuf) {
1502 surf = (struct r600_surface*)state->zsbuf;
1503
1504 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1505
1506 if (!surf->depth_initialized) {
1507 evergreen_init_depth_surface(rctx, surf);
1508 }
1509
1510 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1511 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1512 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1513 }
1514
1515 if (rctx->db_state.rsurf != surf) {
1516 rctx->db_state.rsurf = surf;
1517 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1518 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1519 }
1520 } else if (rctx->db_state.rsurf) {
1521 rctx->db_state.rsurf = NULL;
1522 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1523 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1524 }
1525
1526 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1527 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1528 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1529 }
1530
1531 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1532 rctx->alphatest_state.bypass = false;
1533 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1534 }
1535
1536 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1537 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1538 if ((rctx->b.chip_class == CAYMAN ||
1539 rctx->b.family == CHIP_RV770) &&
1540 rctx->db_misc_state.log_samples != log_samples) {
1541 rctx->db_misc_state.log_samples = log_samples;
1542 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1543 }
1544
1545
1546 /* Calculate the CS size. */
1547 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1548
1549 /* MSAA. */
1550 if (rctx->b.chip_class == EVERGREEN)
1551 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1552 else
1553 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1554
1555 /* Colorbuffers. */
1556 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1557 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1558 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1559
1560 /* ZS buffer. */
1561 if (state->zsbuf) {
1562 rctx->framebuffer.atom.num_dw += 24;
1563 rctx->framebuffer.atom.num_dw += 2;
1564 } else if (rctx->screen->b.info.drm_minor >= 18) {
1565 rctx->framebuffer.atom.num_dw += 4;
1566 }
1567
1568 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1569
1570 r600_set_sample_locations_constant_buffer(rctx);
1571 rctx->framebuffer.do_update_surf_dirtiness = true;
1572 }
1573
1574 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1575 {
1576 struct r600_context *rctx = (struct r600_context *)ctx;
1577
1578 if (rctx->ps_iter_samples == min_samples)
1579 return;
1580
1581 rctx->ps_iter_samples = min_samples;
1582 if (rctx->framebuffer.nr_samples > 1) {
1583 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1584 }
1585 }
1586
1587 /* 8xMSAA */
1588 static uint32_t sample_locs_8x[] = {
1589 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1590 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1591 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1592 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1593 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1594 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1595 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1596 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1597 };
1598 static unsigned max_dist_8x = 7;
1599
1600 static void evergreen_get_sample_position(struct pipe_context *ctx,
1601 unsigned sample_count,
1602 unsigned sample_index,
1603 float *out_value)
1604 {
1605 int offset, index;
1606 struct {
1607 int idx:4;
1608 } val;
1609 switch (sample_count) {
1610 case 1:
1611 default:
1612 out_value[0] = out_value[1] = 0.5;
1613 break;
1614 case 2:
1615 offset = 4 * (sample_index * 2);
1616 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1617 out_value[0] = (float)(val.idx + 8) / 16.0f;
1618 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1619 out_value[1] = (float)(val.idx + 8) / 16.0f;
1620 break;
1621 case 4:
1622 offset = 4 * (sample_index * 2);
1623 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1624 out_value[0] = (float)(val.idx + 8) / 16.0f;
1625 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1626 out_value[1] = (float)(val.idx + 8) / 16.0f;
1627 break;
1628 case 8:
1629 offset = 4 * (sample_index % 4 * 2);
1630 index = (sample_index / 4);
1631 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1632 out_value[0] = (float)(val.idx + 8) / 16.0f;
1633 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1634 out_value[1] = (float)(val.idx + 8) / 16.0f;
1635 break;
1636 }
1637 }
1638
1639 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1640 {
1641
1642 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1643 unsigned max_dist = 0;
1644
1645 switch (nr_samples) {
1646 default:
1647 nr_samples = 0;
1648 break;
1649 case 2:
1650 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x));
1651 radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x));
1652 max_dist = eg_max_dist_2x;
1653 break;
1654 case 4:
1655 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x));
1656 radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x));
1657 max_dist = eg_max_dist_4x;
1658 break;
1659 case 8:
1660 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x));
1661 radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x));
1662 max_dist = max_dist_8x;
1663 break;
1664 }
1665
1666 if (nr_samples > 1) {
1667 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1668 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1669 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1670 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1671 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1672 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1673 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1674 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1675 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1676 } else {
1677 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1678 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1679 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1680 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1681 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1682 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1683 }
1684 }
1685
1686 static void evergreen_emit_image_state(struct r600_context *rctx, struct r600_atom *atom,
1687 int immed_id_base, int res_id_base, int offset, uint32_t pkt_flags)
1688 {
1689 struct r600_image_state *state = (struct r600_image_state *)atom;
1690 struct pipe_framebuffer_state *fb_state = &rctx->framebuffer.state;
1691 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1692 struct r600_texture *rtex;
1693 struct r600_resource *resource;
1694 int i;
1695
1696 for (i = 0; i < R600_MAX_IMAGES; i++) {
1697 struct r600_image_view *image = &state->views[i];
1698 unsigned reloc, immed_reloc;
1699 int idx = i + offset;
1700
1701 if (!pkt_flags)
1702 idx += fb_state->nr_cbufs + (rctx->dual_src_blend ? 1 : 0);
1703 if (!image->base.resource)
1704 continue;
1705
1706 resource = (struct r600_resource *)image->base.resource;
1707 if (resource->b.b.target != PIPE_BUFFER)
1708 rtex = (struct r600_texture *)image->base.resource;
1709 else
1710 rtex = NULL;
1711
1712 reloc = radeon_add_to_buffer_list(&rctx->b,
1713 &rctx->b.gfx,
1714 resource,
1715 RADEON_USAGE_READWRITE,
1716 RADEON_PRIO_SHADER_RW_BUFFER);
1717
1718 immed_reloc = radeon_add_to_buffer_list(&rctx->b,
1719 &rctx->b.gfx,
1720 resource->immed_buffer,
1721 RADEON_USAGE_READWRITE,
1722 RADEON_PRIO_SHADER_RW_BUFFER);
1723
1724 if (pkt_flags)
1725 radeon_compute_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13);
1726 else
1727 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13);
1728
1729 radeon_emit(cs, image->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1730 radeon_emit(cs, image->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1731 radeon_emit(cs, image->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1732 radeon_emit(cs, image->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1733 radeon_emit(cs, image->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1734 radeon_emit(cs, image->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1735 radeon_emit(cs, image->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1736 radeon_emit(cs, rtex ? rtex->cmask.base_address_reg : image->cb_color_base); /* R_028C7C_CB_COLOR0_CMASK */
1737 radeon_emit(cs, rtex ? rtex->cmask.slice_tile_max : 0); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1738 radeon_emit(cs, image->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1739 radeon_emit(cs, image->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1740 radeon_emit(cs, rtex ? rtex->color_clear_value[0] : 0); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1741 radeon_emit(cs, rtex ? rtex->color_clear_value[1] : 0); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1742
1743 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1744 radeon_emit(cs, reloc);
1745
1746 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1747 radeon_emit(cs, reloc);
1748
1749 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1750 radeon_emit(cs, reloc);
1751
1752 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1753 radeon_emit(cs, reloc);
1754
1755 if (pkt_flags)
1756 radeon_compute_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1757 else
1758 radeon_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1759
1760 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /**/
1761 radeon_emit(cs, immed_reloc);
1762
1763 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1764 radeon_emit(cs, (immed_id_base + i + offset) * 8);
1765 radeon_emit_array(cs, image->immed_resource_words, 8);
1766
1767 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1768 radeon_emit(cs, immed_reloc);
1769
1770 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1771 radeon_emit(cs, (res_id_base + i + offset) * 8);
1772 radeon_emit_array(cs, image->resource_words, 8);
1773
1774 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1775 radeon_emit(cs, reloc);
1776
1777 if (!image->skip_mip_address_reloc) {
1778 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1779 radeon_emit(cs, reloc);
1780 }
1781 }
1782 }
1783
1784 static void evergreen_emit_fragment_image_state(struct r600_context *rctx, struct r600_atom *atom)
1785 {
1786 evergreen_emit_image_state(rctx, atom,
1787 R600_IMAGE_IMMED_RESOURCE_OFFSET,
1788 R600_IMAGE_REAL_RESOURCE_OFFSET, 0, 0);
1789 }
1790
1791 static void evergreen_emit_compute_image_state(struct r600_context *rctx, struct r600_atom *atom)
1792 {
1793 evergreen_emit_image_state(rctx, atom,
1794 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_IMMED_RESOURCE_OFFSET,
1795 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_REAL_RESOURCE_OFFSET,
1796 0, RADEON_CP_PACKET3_COMPUTE_MODE);
1797 }
1798
1799 static void evergreen_emit_fragment_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1800 {
1801 int offset = util_bitcount(rctx->fragment_images.enabled_mask);
1802 evergreen_emit_image_state(rctx, atom,
1803 R600_IMAGE_IMMED_RESOURCE_OFFSET,
1804 R600_IMAGE_REAL_RESOURCE_OFFSET, offset, 0);
1805 }
1806
1807 static void evergreen_emit_compute_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1808 {
1809 int offset = util_bitcount(rctx->compute_images.enabled_mask);
1810 evergreen_emit_image_state(rctx, atom,
1811 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_IMMED_RESOURCE_OFFSET,
1812 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_REAL_RESOURCE_OFFSET,
1813 offset, RADEON_CP_PACKET3_COMPUTE_MODE);
1814 }
1815
1816 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1817 {
1818 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1819 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1820 unsigned nr_cbufs = state->nr_cbufs;
1821 unsigned i, tl, br;
1822 struct r600_texture *tex = NULL;
1823 struct r600_surface *cb = NULL;
1824
1825 /* XXX support more colorbuffers once we need them */
1826 assert(nr_cbufs <= 8);
1827 if (nr_cbufs > 8)
1828 nr_cbufs = 8;
1829
1830 /* Colorbuffers. */
1831 for (i = 0; i < nr_cbufs; i++) {
1832 unsigned reloc, cmask_reloc;
1833
1834 cb = (struct r600_surface*)state->cbufs[i];
1835 if (!cb) {
1836 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1837 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1838 continue;
1839 }
1840
1841 tex = (struct r600_texture *)cb->base.texture;
1842 reloc = radeon_add_to_buffer_list(&rctx->b,
1843 &rctx->b.gfx,
1844 (struct r600_resource*)cb->base.texture,
1845 RADEON_USAGE_READWRITE,
1846 tex->resource.b.b.nr_samples > 1 ?
1847 RADEON_PRIO_COLOR_BUFFER_MSAA :
1848 RADEON_PRIO_COLOR_BUFFER);
1849
1850 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1851 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1852 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1853 RADEON_PRIO_CMASK);
1854 } else {
1855 cmask_reloc = reloc;
1856 }
1857
1858 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1859 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1860 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1861 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1862 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1863 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1864 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1865 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1866 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1867 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1868 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1869 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1870 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1871 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1872
1873 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1874 radeon_emit(cs, reloc);
1875
1876 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1877 radeon_emit(cs, reloc);
1878
1879 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1880 radeon_emit(cs, cmask_reloc);
1881
1882 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1883 radeon_emit(cs, reloc);
1884 }
1885 /* set CB_COLOR1_INFO for possible dual-src blending */
1886 if (rctx->framebuffer.dual_src_blend && i == 1 && state->cbufs[0]) {
1887 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1888 cb->cb_color_info | tex->cb_color_info);
1889 i++;
1890 }
1891 i += util_bitcount(rctx->fragment_images.enabled_mask);
1892 i += util_bitcount(rctx->fragment_buffers.enabled_mask);
1893 for (; i < 8 ; i++)
1894 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1895 for (; i < 12; i++)
1896 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1897
1898 /* ZS buffer. */
1899 if (state->zsbuf) {
1900 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1901 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1902 &rctx->b.gfx,
1903 (struct r600_resource*)state->zsbuf->texture,
1904 RADEON_USAGE_READWRITE,
1905 zb->base.texture->nr_samples > 1 ?
1906 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1907 RADEON_PRIO_DEPTH_BUFFER);
1908
1909 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1910
1911 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1912 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1913 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1914 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1915 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1916 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1917 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1918 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1919 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1920
1921 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1922 radeon_emit(cs, reloc);
1923
1924 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1925 radeon_emit(cs, reloc);
1926
1927 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1928 radeon_emit(cs, reloc);
1929
1930 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1931 radeon_emit(cs, reloc);
1932 } else if (rctx->screen->b.info.drm_minor >= 18) {
1933 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1934 * Older kernels are out of luck. */
1935 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1936 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1937 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1938 }
1939
1940 /* Framebuffer dimensions. */
1941 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1942
1943 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1944 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1945 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1946
1947 if (rctx->b.chip_class == EVERGREEN) {
1948 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1949 } else {
1950 unsigned sc_mode_cntl_1 =
1951 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1952 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1953
1954 if (rctx->framebuffer.nr_samples > 1)
1955 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1956 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples,
1957 rctx->ps_iter_samples, 0, sc_mode_cntl_1);
1958 }
1959 }
1960
1961 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1962 {
1963 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1964 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1965 float offset_units = state->offset_units;
1966 float offset_scale = state->offset_scale;
1967 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
1968
1969 if (!state->offset_units_unscaled) {
1970 switch (state->zs_format) {
1971 case PIPE_FORMAT_Z24X8_UNORM:
1972 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1973 case PIPE_FORMAT_X8Z24_UNORM:
1974 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1975 offset_units *= 2.0f;
1976 pa_su_poly_offset_db_fmt_cntl =
1977 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1978 break;
1979 case PIPE_FORMAT_Z16_UNORM:
1980 offset_units *= 4.0f;
1981 pa_su_poly_offset_db_fmt_cntl =
1982 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1983 break;
1984 default:
1985 pa_su_poly_offset_db_fmt_cntl =
1986 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1987 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1988 }
1989 }
1990
1991 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1992 radeon_emit(cs, fui(offset_scale));
1993 radeon_emit(cs, fui(offset_units));
1994 radeon_emit(cs, fui(offset_scale));
1995 radeon_emit(cs, fui(offset_units));
1996
1997 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1998 pa_su_poly_offset_db_fmt_cntl);
1999 }
2000
2001 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2002 {
2003 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2004 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
2005 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
2006 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
2007 unsigned rat_colormask = ((1ULL << ((unsigned)(a->nr_image_rats + a->nr_buffer_rats) * 4)) - 1) << (a->nr_cbufs * 4);
2008 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
2009 radeon_emit(cs, (a->blend_colormask & fb_colormask) | rat_colormask); /* R_028238_CB_TARGET_MASK */
2010 /* This must match the used export instructions exactly.
2011 * Other values may lead to undefined behavior and hangs.
2012 */
2013 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
2014 }
2015
2016 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
2017 {
2018 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2019 struct r600_db_state *a = (struct r600_db_state*)atom;
2020
2021 if (a->rsurf && a->rsurf->db_htile_surface) {
2022 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
2023 unsigned reloc_idx;
2024
2025 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2026 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
2027 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
2028 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
2029 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
2030 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
2031 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2032 radeon_emit(cs, reloc_idx);
2033 } else {
2034 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
2035 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
2036 }
2037 }
2038
2039 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2040 {
2041 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2042 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2043 unsigned db_render_control = 0;
2044 unsigned db_count_control = 0;
2045 unsigned db_render_override =
2046 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2047 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2048
2049 if (rctx->b.num_occlusion_queries > 0 &&
2050 !a->occlusion_queries_disabled) {
2051 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
2052 if (rctx->b.chip_class == CAYMAN) {
2053 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
2054 }
2055 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
2056 } else {
2057 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
2058 }
2059
2060 /* This is to fix a lockup when hyperz and alpha test are enabled at
2061 * the same time somehow GPU get confuse on which order to pick for
2062 * z test
2063 */
2064 if (rctx->alphatest_state.sx_alpha_test_control)
2065 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
2066
2067 if (a->flush_depthstencil_through_cb) {
2068 assert(a->copy_depth || a->copy_stencil);
2069
2070 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
2071 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
2072 S_028000_COPY_CENTROID(1) |
2073 S_028000_COPY_SAMPLE(a->copy_sample);
2074 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
2075 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
2076 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
2077 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2078 }
2079 if (a->htile_clear) {
2080 /* FIXME we might want to disable cliprect here */
2081 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
2082 }
2083
2084 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
2085 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
2086 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
2087 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2088 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2089 }
2090
2091 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
2092 struct r600_vertexbuf_state *state,
2093 unsigned resource_offset,
2094 unsigned pkt_flags)
2095 {
2096 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2097 uint32_t dirty_mask = state->dirty_mask;
2098
2099 while (dirty_mask) {
2100 struct pipe_vertex_buffer *vb;
2101 struct r600_resource *rbuffer;
2102 uint64_t va;
2103 unsigned buffer_index = u_bit_scan(&dirty_mask);
2104
2105 vb = &state->vb[buffer_index];
2106 rbuffer = (struct r600_resource*)vb->buffer.resource;
2107 assert(rbuffer);
2108
2109 va = rbuffer->gpu_address + vb->buffer_offset;
2110
2111 /* fetch resources start at index 992 */
2112 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2113 radeon_emit(cs, (resource_offset + buffer_index) * 8);
2114 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2115 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2116 radeon_emit(cs, /* RESOURCEi_WORD2 */
2117 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2118 S_030008_STRIDE(vb->stride) |
2119 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2120 radeon_emit(cs, /* RESOURCEi_WORD3 */
2121 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2122 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2123 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2124 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2125 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2126 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2127 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2128 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2129
2130 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2131 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2132 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
2133 }
2134 state->dirty_mask = 0;
2135 }
2136
2137 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2138 {
2139 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
2140 }
2141
2142 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2143 {
2144 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
2145 RADEON_CP_PACKET3_COMPUTE_MODE);
2146 }
2147
2148 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2149 struct r600_constbuf_state *state,
2150 unsigned buffer_id_base,
2151 unsigned reg_alu_constbuf_size,
2152 unsigned reg_alu_const_cache,
2153 unsigned pkt_flags)
2154 {
2155 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2156 uint32_t dirty_mask = state->dirty_mask;
2157
2158 while (dirty_mask) {
2159 struct pipe_constant_buffer *cb;
2160 struct r600_resource *rbuffer;
2161 uint64_t va;
2162 unsigned buffer_index = ffs(dirty_mask) - 1;
2163 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
2164
2165 cb = &state->cb[buffer_index];
2166 rbuffer = (struct r600_resource*)cb->buffer;
2167 assert(rbuffer);
2168
2169 va = rbuffer->gpu_address + cb->buffer_offset;
2170
2171 if (buffer_index < R600_MAX_HW_CONST_BUFFERS) {
2172 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
2173 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
2174 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
2175 pkt_flags);
2176 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2177 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2178 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2179 }
2180
2181 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2182 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
2183 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2184 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2185 radeon_emit(cs, /* RESOURCEi_WORD2 */
2186 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
2187 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
2188 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
2189 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
2190 radeon_emit(cs, /* RESOURCEi_WORD3 */
2191 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
2192 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2193 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2194 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2195 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2196 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2197 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2198 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2199 radeon_emit(cs, /* RESOURCEi_WORD7 */
2200 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
2201
2202 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2203 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2204 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2205
2206 dirty_mask &= ~(1 << buffer_index);
2207 }
2208 state->dirty_mask = 0;
2209 }
2210
2211 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
2212 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2213 {
2214 if (rctx->vs_shader->current->shader.vs_as_ls) {
2215 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2216 EG_FETCH_CONSTANTS_OFFSET_LS,
2217 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2218 R_028F40_ALU_CONST_CACHE_LS_0,
2219 0 /* PKT3 flags */);
2220 } else {
2221 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2222 EG_FETCH_CONSTANTS_OFFSET_VS,
2223 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2224 R_028980_ALU_CONST_CACHE_VS_0,
2225 0 /* PKT3 flags */);
2226 }
2227 }
2228
2229 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2230 {
2231 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
2232 EG_FETCH_CONSTANTS_OFFSET_GS,
2233 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2234 R_0289C0_ALU_CONST_CACHE_GS_0,
2235 0 /* PKT3 flags */);
2236 }
2237
2238 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2239 {
2240 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
2241 EG_FETCH_CONSTANTS_OFFSET_PS,
2242 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2243 R_028940_ALU_CONST_CACHE_PS_0,
2244 0 /* PKT3 flags */);
2245 }
2246
2247 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2248 {
2249 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
2250 EG_FETCH_CONSTANTS_OFFSET_CS,
2251 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2252 R_028F40_ALU_CONST_CACHE_LS_0,
2253 RADEON_CP_PACKET3_COMPUTE_MODE);
2254 }
2255
2256 /* tes constants can be emitted to VS or ES - which are common */
2257 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2258 {
2259 if (!rctx->tes_shader)
2260 return;
2261 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2262 EG_FETCH_CONSTANTS_OFFSET_VS,
2263 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2264 R_028980_ALU_CONST_CACHE_VS_0,
2265 0);
2266 }
2267
2268 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2269 {
2270 if (!rctx->tes_shader)
2271 return;
2272 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2273 EG_FETCH_CONSTANTS_OFFSET_HS,
2274 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
2275 R_028F00_ALU_CONST_CACHE_HS_0,
2276 0);
2277 }
2278
2279 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2280 struct r600_samplerview_state *state,
2281 unsigned resource_id_base, unsigned pkt_flags)
2282 {
2283 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2284 uint32_t dirty_mask = state->dirty_mask;
2285
2286 while (dirty_mask) {
2287 struct r600_pipe_sampler_view *rview;
2288 unsigned resource_index = u_bit_scan(&dirty_mask);
2289 unsigned reloc;
2290
2291 rview = state->views[resource_index];
2292 assert(rview);
2293
2294 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2295 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2296 radeon_emit_array(cs, rview->tex_resource_words, 8);
2297
2298 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2299 RADEON_USAGE_READ,
2300 r600_get_sampler_view_priority(rview->tex_resource));
2301 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2302 radeon_emit(cs, reloc);
2303
2304 if (!rview->skip_mip_address_reloc) {
2305 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2306 radeon_emit(cs, reloc);
2307 }
2308 }
2309 state->dirty_mask = 0;
2310 }
2311
2312 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2313 {
2314 if (rctx->vs_shader->current->shader.vs_as_ls) {
2315 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2316 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2317 } else {
2318 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2319 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2320 }
2321 }
2322
2323 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2324 {
2325 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2326 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2327 }
2328
2329 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2330 {
2331 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2332 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2333 }
2334
2335 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2336 {
2337 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2338 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2339 }
2340
2341 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2342 {
2343 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2344 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2345 }
2346
2347 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2348 {
2349 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2350 EG_FETCH_CONSTANTS_OFFSET_CS + R600_MAX_CONST_BUFFERS, RADEON_CP_PACKET3_COMPUTE_MODE);
2351 }
2352
2353 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2354 struct r600_textures_info *texinfo,
2355 unsigned resource_id_base,
2356 unsigned border_index_reg,
2357 unsigned pkt_flags)
2358 {
2359 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2360 uint32_t dirty_mask = texinfo->states.dirty_mask;
2361
2362 while (dirty_mask) {
2363 struct r600_pipe_sampler_state *rstate;
2364 unsigned i = u_bit_scan(&dirty_mask);
2365
2366 rstate = texinfo->states.states[i];
2367 assert(rstate);
2368
2369 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2370 radeon_emit(cs, (resource_id_base + i) * 3);
2371 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2372
2373 if (rstate->border_color_use) {
2374 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2375 radeon_emit(cs, i);
2376 radeon_emit_array(cs, rstate->border_color.ui, 4);
2377 }
2378 }
2379 texinfo->states.dirty_mask = 0;
2380 }
2381
2382 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2383 {
2384 if (rctx->vs_shader->current->shader.vs_as_ls) {
2385 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2386 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2387 } else {
2388 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2389 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2390 }
2391 }
2392
2393 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2394 {
2395 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2396 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2397 }
2398
2399 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2400 {
2401 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2402 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2403 }
2404
2405 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2406 {
2407 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2408 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2409 }
2410
2411 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2412 {
2413 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2414 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2415 }
2416
2417 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2418 {
2419 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2420 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2421 RADEON_CP_PACKET3_COMPUTE_MODE);
2422 }
2423
2424 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2425 {
2426 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2427 uint8_t mask = s->sample_mask;
2428
2429 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2430 mask | (mask << 8) | (mask << 16) | (mask << 24));
2431 }
2432
2433 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2434 {
2435 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2436 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2437 uint16_t mask = s->sample_mask;
2438
2439 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2440 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2441 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2442 }
2443
2444 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2445 {
2446 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2447 struct r600_cso_state *state = (struct r600_cso_state*)a;
2448 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2449
2450 if (!shader)
2451 return;
2452
2453 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2454 (shader->buffer->gpu_address + shader->offset) >> 8);
2455 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2456 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2457 RADEON_USAGE_READ,
2458 RADEON_PRIO_SHADER_BINARY));
2459 }
2460
2461 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2462 {
2463 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2464 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2465
2466 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2467
2468 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2469 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2470 primid = 1;
2471 }
2472
2473 if (state->geom_enable) {
2474 uint32_t cut_val;
2475
2476 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2477 cut_val = V_028A40_GS_CUT_128;
2478 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2479 cut_val = V_028A40_GS_CUT_256;
2480 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2481 cut_val = V_028A40_GS_CUT_512;
2482 else
2483 cut_val = V_028A40_GS_CUT_1024;
2484
2485 v = S_028B54_GS_EN(1) |
2486 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2487 if (!rctx->tes_shader)
2488 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2489
2490 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2491 S_028A40_CUT_MODE(cut_val);
2492
2493 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2494 primid = 1;
2495 }
2496
2497 if (rctx->tes_shader) {
2498 uint32_t type, partitioning, topology;
2499 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2500 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2501 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2502 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2503 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2504 switch (tes_prim_mode) {
2505 case PIPE_PRIM_LINES:
2506 type = V_028B6C_TESS_ISOLINE;
2507 break;
2508 case PIPE_PRIM_TRIANGLES:
2509 type = V_028B6C_TESS_TRIANGLE;
2510 break;
2511 case PIPE_PRIM_QUADS:
2512 type = V_028B6C_TESS_QUAD;
2513 break;
2514 default:
2515 assert(0);
2516 return;
2517 }
2518
2519 switch (tes_spacing) {
2520 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2521 partitioning = V_028B6C_PART_FRAC_ODD;
2522 break;
2523 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2524 partitioning = V_028B6C_PART_FRAC_EVEN;
2525 break;
2526 case PIPE_TESS_SPACING_EQUAL:
2527 partitioning = V_028B6C_PART_INTEGER;
2528 break;
2529 default:
2530 assert(0);
2531 return;
2532 }
2533
2534 if (tes_point_mode)
2535 topology = V_028B6C_OUTPUT_POINT;
2536 else if (tes_prim_mode == PIPE_PRIM_LINES)
2537 topology = V_028B6C_OUTPUT_LINE;
2538 else if (tes_vertex_order_cw)
2539 /* XXX follow radeonsi and invert */
2540 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2541 else
2542 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2543
2544 tf_param = S_028B6C_TYPE(type) |
2545 S_028B6C_PARTITIONING(partitioning) |
2546 S_028B6C_TOPOLOGY(topology);
2547 }
2548
2549 if (rctx->tes_shader) {
2550 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2551 S_028B54_HS_EN(1);
2552 if (!state->geom_enable)
2553 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2554 else
2555 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2556 }
2557
2558 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2559 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2560 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2561 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2562 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2563 }
2564
2565 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2566 {
2567 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2568 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2569 struct r600_resource *rbuffer;
2570
2571 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2572 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2573 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2574
2575 if (state->enable) {
2576 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2577 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2578 rbuffer->gpu_address >> 8);
2579 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2580 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2581 RADEON_USAGE_READWRITE,
2582 RADEON_PRIO_SHADER_RINGS));
2583 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2584 state->esgs_ring.buffer_size >> 8);
2585
2586 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2587 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2588 rbuffer->gpu_address >> 8);
2589 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2590 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2591 RADEON_USAGE_READWRITE,
2592 RADEON_PRIO_SHADER_RINGS));
2593 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2594 state->gsvs_ring.buffer_size >> 8);
2595 } else {
2596 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2597 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2598 }
2599
2600 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2601 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2602 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2603 }
2604
2605 void cayman_init_common_regs(struct r600_command_buffer *cb,
2606 enum chip_class ctx_chip_class,
2607 enum radeon_family ctx_family,
2608 int ctx_drm_minor)
2609 {
2610 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2611 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2612 /* always set the temp clauses */
2613 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2614
2615 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2616 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2617 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2618
2619 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2620
2621 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2622 r600_store_value(cb, 0);
2623 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2624
2625 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2626 }
2627
2628 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2629 {
2630 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2631 int i;
2632
2633 r600_init_command_buffer(cb, 338);
2634
2635 /* This must be first. */
2636 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2637 r600_store_value(cb, 0x80000000);
2638 r600_store_value(cb, 0x80000000);
2639
2640 /* We're setting config registers here. */
2641 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2642 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2643
2644 /* This enables pipeline stat & streamout queries.
2645 * They are only disabled by blits.
2646 */
2647 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2648 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2649
2650 cayman_init_common_regs(cb, rctx->b.chip_class,
2651 rctx->b.family, rctx->screen->b.info.drm_minor);
2652
2653 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2654 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2655
2656 /* remove LS/HS from one SIMD for hw workaround */
2657 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2658 r600_store_value(cb, 0xffffffff);
2659 r600_store_value(cb, 0xffffffff);
2660 r600_store_value(cb, 0xfffffffe);
2661
2662 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2663 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2664 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2665 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2666 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2667 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2668 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2669
2670 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2671 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2672 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2673 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2674 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2675
2676 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2677 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2678 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2679 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2680 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2681 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2682 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2683 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2684 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2685 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2686 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2687 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2688 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2689 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2690
2691 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2692
2693 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2694
2695 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2696 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2697 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2698
2699 r600_store_context_reg(cb, R_028724_GDS_ADDR_SIZE, 0x3fff);
2700 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2701 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2702 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2703
2704 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2705
2706 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2707 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2708 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2709
2710 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2711
2712 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2713
2714 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2715
2716 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2717 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2718 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2719 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2720
2721 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2722 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2723
2724 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2725 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2726
2727 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2728 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2729 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2730
2731 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2732 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2733 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2734
2735 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2736 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2737 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2738 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2739 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2740 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2741
2742 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2743
2744 /* to avoid GPU doing any preloading of constant from random address */
2745 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2746 for (i = 0; i < 16; i++)
2747 r600_store_value(cb, 0);
2748
2749 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2750 for (i = 0; i < 16; i++)
2751 r600_store_value(cb, 0);
2752
2753 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2754 for (i = 0; i < 16; i++)
2755 r600_store_value(cb, 0);
2756
2757 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2758 for (i = 0; i < 16; i++)
2759 r600_store_value(cb, 0);
2760
2761 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2762 for (i = 0; i < 16; i++)
2763 r600_store_value(cb, 0);
2764
2765 if (rctx->screen->b.has_streamout) {
2766 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2767 }
2768
2769 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2770 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2771 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2772 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2773 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2774 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2775
2776 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2777 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2778 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2779 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2780 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2781 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2782 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2783 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2784 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2785 }
2786
2787 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2788 enum chip_class ctx_chip_class,
2789 enum radeon_family ctx_family,
2790 int ctx_drm_minor)
2791 {
2792 int ps_prio;
2793 int vs_prio;
2794 int gs_prio;
2795 int es_prio;
2796
2797 int hs_prio;
2798 int cs_prio;
2799 int ls_prio;
2800
2801 unsigned tmp;
2802
2803 ps_prio = 0;
2804 vs_prio = 1;
2805 gs_prio = 2;
2806 es_prio = 3;
2807 hs_prio = 3;
2808 ls_prio = 3;
2809 cs_prio = 0;
2810
2811 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2812 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2813 rctx->r6xx_num_clause_temp_gprs = 4;
2814 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2815 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2816 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2817 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2818
2819 tmp = 0;
2820 switch (ctx_family) {
2821 case CHIP_CEDAR:
2822 case CHIP_PALM:
2823 case CHIP_SUMO:
2824 case CHIP_SUMO2:
2825 case CHIP_CAICOS:
2826 break;
2827 default:
2828 tmp |= S_008C00_VC_ENABLE(1);
2829 break;
2830 }
2831 tmp |= S_008C00_EXPORT_SRC_C(1);
2832 tmp |= S_008C00_CS_PRIO(cs_prio);
2833 tmp |= S_008C00_LS_PRIO(ls_prio);
2834 tmp |= S_008C00_HS_PRIO(hs_prio);
2835 tmp |= S_008C00_PS_PRIO(ps_prio);
2836 tmp |= S_008C00_VS_PRIO(vs_prio);
2837 tmp |= S_008C00_GS_PRIO(gs_prio);
2838 tmp |= S_008C00_ES_PRIO(es_prio);
2839
2840 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2841 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2842
2843 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2844 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2845 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2846
2847 /* The cs checker requires this register to be set. */
2848 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2849
2850 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2851 r600_store_value(cb, 0);
2852 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2853
2854 return;
2855 }
2856
2857 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2858 {
2859 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2860 int num_ps_threads;
2861 int num_vs_threads;
2862 int num_gs_threads;
2863 int num_es_threads;
2864 int num_hs_threads;
2865 int num_ls_threads;
2866
2867 int num_ps_stack_entries;
2868 int num_vs_stack_entries;
2869 int num_gs_stack_entries;
2870 int num_es_stack_entries;
2871 int num_hs_stack_entries;
2872 int num_ls_stack_entries;
2873 enum radeon_family family;
2874 unsigned tmp, i;
2875
2876 if (rctx->b.chip_class == CAYMAN) {
2877 cayman_init_atom_start_cs(rctx);
2878 return;
2879 }
2880
2881 r600_init_command_buffer(cb, 338);
2882
2883 /* This must be first. */
2884 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2885 r600_store_value(cb, 0x80000000);
2886 r600_store_value(cb, 0x80000000);
2887
2888 /* We're setting config registers here. */
2889 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2890 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2891
2892 /* This enables pipeline stat & streamout queries.
2893 * They are only disabled by blits.
2894 */
2895 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2896 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2897
2898 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2899 rctx->b.family, rctx->screen->b.info.drm_minor);
2900
2901 family = rctx->b.family;
2902 switch (family) {
2903 case CHIP_CEDAR:
2904 default:
2905 num_ps_threads = 96;
2906 num_vs_threads = 16;
2907 num_gs_threads = 16;
2908 num_es_threads = 16;
2909 num_hs_threads = 16;
2910 num_ls_threads = 16;
2911 num_ps_stack_entries = 42;
2912 num_vs_stack_entries = 42;
2913 num_gs_stack_entries = 42;
2914 num_es_stack_entries = 42;
2915 num_hs_stack_entries = 42;
2916 num_ls_stack_entries = 42;
2917 break;
2918 case CHIP_REDWOOD:
2919 num_ps_threads = 128;
2920 num_vs_threads = 20;
2921 num_gs_threads = 20;
2922 num_es_threads = 20;
2923 num_hs_threads = 20;
2924 num_ls_threads = 20;
2925 num_ps_stack_entries = 42;
2926 num_vs_stack_entries = 42;
2927 num_gs_stack_entries = 42;
2928 num_es_stack_entries = 42;
2929 num_hs_stack_entries = 42;
2930 num_ls_stack_entries = 42;
2931 break;
2932 case CHIP_JUNIPER:
2933 num_ps_threads = 128;
2934 num_vs_threads = 20;
2935 num_gs_threads = 20;
2936 num_es_threads = 20;
2937 num_hs_threads = 20;
2938 num_ls_threads = 20;
2939 num_ps_stack_entries = 85;
2940 num_vs_stack_entries = 85;
2941 num_gs_stack_entries = 85;
2942 num_es_stack_entries = 85;
2943 num_hs_stack_entries = 85;
2944 num_ls_stack_entries = 85;
2945 break;
2946 case CHIP_CYPRESS:
2947 case CHIP_HEMLOCK:
2948 num_ps_threads = 128;
2949 num_vs_threads = 20;
2950 num_gs_threads = 20;
2951 num_es_threads = 20;
2952 num_hs_threads = 20;
2953 num_ls_threads = 20;
2954 num_ps_stack_entries = 85;
2955 num_vs_stack_entries = 85;
2956 num_gs_stack_entries = 85;
2957 num_es_stack_entries = 85;
2958 num_hs_stack_entries = 85;
2959 num_ls_stack_entries = 85;
2960 break;
2961 case CHIP_PALM:
2962 num_ps_threads = 96;
2963 num_vs_threads = 16;
2964 num_gs_threads = 16;
2965 num_es_threads = 16;
2966 num_hs_threads = 16;
2967 num_ls_threads = 16;
2968 num_ps_stack_entries = 42;
2969 num_vs_stack_entries = 42;
2970 num_gs_stack_entries = 42;
2971 num_es_stack_entries = 42;
2972 num_hs_stack_entries = 42;
2973 num_ls_stack_entries = 42;
2974 break;
2975 case CHIP_SUMO:
2976 num_ps_threads = 96;
2977 num_vs_threads = 25;
2978 num_gs_threads = 25;
2979 num_es_threads = 25;
2980 num_hs_threads = 16;
2981 num_ls_threads = 16;
2982 num_ps_stack_entries = 42;
2983 num_vs_stack_entries = 42;
2984 num_gs_stack_entries = 42;
2985 num_es_stack_entries = 42;
2986 num_hs_stack_entries = 42;
2987 num_ls_stack_entries = 42;
2988 break;
2989 case CHIP_SUMO2:
2990 num_ps_threads = 96;
2991 num_vs_threads = 25;
2992 num_gs_threads = 25;
2993 num_es_threads = 25;
2994 num_hs_threads = 16;
2995 num_ls_threads = 16;
2996 num_ps_stack_entries = 85;
2997 num_vs_stack_entries = 85;
2998 num_gs_stack_entries = 85;
2999 num_es_stack_entries = 85;
3000 num_hs_stack_entries = 85;
3001 num_ls_stack_entries = 85;
3002 break;
3003 case CHIP_BARTS:
3004 num_ps_threads = 128;
3005 num_vs_threads = 20;
3006 num_gs_threads = 20;
3007 num_es_threads = 20;
3008 num_hs_threads = 20;
3009 num_ls_threads = 20;
3010 num_ps_stack_entries = 85;
3011 num_vs_stack_entries = 85;
3012 num_gs_stack_entries = 85;
3013 num_es_stack_entries = 85;
3014 num_hs_stack_entries = 85;
3015 num_ls_stack_entries = 85;
3016 break;
3017 case CHIP_TURKS:
3018 num_ps_threads = 128;
3019 num_vs_threads = 20;
3020 num_gs_threads = 20;
3021 num_es_threads = 20;
3022 num_hs_threads = 20;
3023 num_ls_threads = 20;
3024 num_ps_stack_entries = 42;
3025 num_vs_stack_entries = 42;
3026 num_gs_stack_entries = 42;
3027 num_es_stack_entries = 42;
3028 num_hs_stack_entries = 42;
3029 num_ls_stack_entries = 42;
3030 break;
3031 case CHIP_CAICOS:
3032 num_ps_threads = 96;
3033 num_vs_threads = 10;
3034 num_gs_threads = 10;
3035 num_es_threads = 10;
3036 num_hs_threads = 10;
3037 num_ls_threads = 10;
3038 num_ps_stack_entries = 42;
3039 num_vs_stack_entries = 42;
3040 num_gs_stack_entries = 42;
3041 num_es_stack_entries = 42;
3042 num_hs_stack_entries = 42;
3043 num_ls_stack_entries = 42;
3044 break;
3045 }
3046
3047 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
3048 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
3049 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
3050 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
3051
3052 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
3053 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3054
3055 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
3056 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
3057 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3058
3059 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
3060 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
3061 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3062
3063 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
3064 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
3065 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3066
3067 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
3068 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
3069 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3070
3071 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
3072 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
3073
3074 /* remove LS/HS from one SIMD for hw workaround */
3075 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
3076 r600_store_value(cb, 0xffffffff);
3077 r600_store_value(cb, 0xffffffff);
3078 r600_store_value(cb, 0xfffffffe);
3079
3080 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
3081 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
3082
3083 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
3084 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3085 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3086 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3087 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3088 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3089 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3090
3091 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3092 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3093 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3094 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3095 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3096
3097 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
3098 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3099 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
3100 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3101 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3102 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3103 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3104 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3105 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
3106 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3107 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3108 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3109 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3110 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
3111
3112 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
3113
3114 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
3115
3116 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
3117 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3118 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
3119
3120 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
3121
3122 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
3123
3124 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
3125 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3126 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3127
3128 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
3129 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
3130
3131 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
3132 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3133 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3134 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3135
3136 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
3137 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3138 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3139
3140 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
3141 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3142 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3143
3144 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3145 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3146 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3147 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3148 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
3149 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3150 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3151
3152 /* to avoid GPU doing any preloading of constant from random address */
3153 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
3154 for (i = 0; i < 16; i++)
3155 r600_store_value(cb, 0);
3156
3157 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
3158 for (i = 0; i < 16; i++)
3159 r600_store_value(cb, 0);
3160
3161 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
3162 for (i = 0; i < 16; i++)
3163 r600_store_value(cb, 0);
3164
3165 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
3166 for (i = 0; i < 16; i++)
3167 r600_store_value(cb, 0);
3168
3169 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
3170 for (i = 0; i < 16; i++)
3171 r600_store_value(cb, 0);
3172
3173 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
3174
3175 if (rctx->screen->b.has_streamout) {
3176 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3177 }
3178
3179 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
3180 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3181 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
3182 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
3183 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3184 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3185
3186 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
3187 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
3188 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
3189
3190 if (rctx->b.family == CHIP_CAICOS) {
3191 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
3192 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3193 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3194 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
3195 } else {
3196 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
3197 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3198 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3199 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
3200 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
3201 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
3202 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
3203 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
3204 }
3205
3206 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3207 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3208 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
3209 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
3210 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
3211 }
3212
3213 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3214 {
3215 struct r600_context *rctx = (struct r600_context *)ctx;
3216 struct r600_command_buffer *cb = &shader->command_buffer;
3217 struct r600_shader *rshader = &shader->shader;
3218 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
3219 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
3220 int ninterp = 0;
3221 boolean have_perspective = FALSE, have_linear = FALSE;
3222 static const unsigned spi_baryc_enable_bit[6] = {
3223 S_0286E0_PERSP_SAMPLE_ENA(1),
3224 S_0286E0_PERSP_CENTER_ENA(1),
3225 S_0286E0_PERSP_CENTROID_ENA(1),
3226 S_0286E0_LINEAR_SAMPLE_ENA(1),
3227 S_0286E0_LINEAR_CENTER_ENA(1),
3228 S_0286E0_LINEAR_CENTROID_ENA(1)
3229 };
3230 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
3231 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
3232 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3233 uint32_t spi_ps_input_cntl[32];
3234
3235 if (!cb->buf) {
3236 r600_init_command_buffer(cb, 64);
3237 } else {
3238 cb->num_dw = 0;
3239 }
3240
3241 for (i = 0; i < rshader->ninput; i++) {
3242 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3243 POSITION goes via GPRs from the SC so isn't counted */
3244 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3245 pos_index = i;
3246 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
3247 if (face_index == -1)
3248 face_index = i;
3249 }
3250 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3251 if (face_index == -1)
3252 face_index = i; /* lives in same register, same enable bit */
3253 }
3254 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
3255 fixed_pt_position_index = i;
3256 }
3257 else {
3258 ninterp++;
3259 int k = eg_get_interpolator_index(
3260 rshader->input[i].interpolate,
3261 rshader->input[i].interpolate_location);
3262 if (k >= 0) {
3263 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3264 have_perspective |= k < 3;
3265 have_linear |= !(k < 3);
3266 }
3267 }
3268
3269 sid = rshader->input[i].spi_sid;
3270
3271 if (sid) {
3272 tmp = S_028644_SEMANTIC(sid);
3273
3274 /* D3D 9 behaviour. GL is undefined */
3275 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
3276 tmp |= S_028644_DEFAULT_VAL(3);
3277
3278 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3279 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3280 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3281 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3282 tmp |= S_028644_FLAT_SHADE(1);
3283 }
3284
3285 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3286 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3287 tmp |= S_028644_PT_SPRITE_TEX(1);
3288 }
3289
3290 spi_ps_input_cntl[num++] = tmp;
3291 }
3292 }
3293
3294 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3295 r600_store_array(cb, num, spi_ps_input_cntl);
3296
3297 for (i = 0; i < rshader->noutput; i++) {
3298 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3299 z_export = 1;
3300 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3301 stencil_export = 1;
3302 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3303 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3304 mask_export = 1;
3305 }
3306 if (rshader->uses_kill)
3307 db_shader_control |= S_02880C_KILL_ENABLE(1);
3308
3309 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3310 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3311 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3312
3313 if (shader->selector->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
3314 db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
3315 S_02880C_EXEC_ON_NOOP(shader->selector->info.writes_memory);
3316 } else if (shader->selector->info.writes_memory) {
3317 db_shader_control |= S_02880C_EXEC_ON_HIER_FAIL(1);
3318 }
3319
3320 switch (rshader->ps_conservative_z) {
3321 default: /* fall through */
3322 case TGSI_FS_DEPTH_LAYOUT_ANY:
3323 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3324 break;
3325 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3326 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3327 break;
3328 case TGSI_FS_DEPTH_LAYOUT_LESS:
3329 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3330 break;
3331 }
3332
3333 exports_ps = 0;
3334 for (i = 0; i < rshader->noutput; i++) {
3335 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3336 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3337 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3338 exports_ps |= 1;
3339 }
3340
3341 num_cout = rshader->nr_ps_color_exports;
3342
3343 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3344 if (!exports_ps) {
3345 /* always at least export 1 component per pixel */
3346 exports_ps = 2;
3347 }
3348 shader->nr_ps_color_outputs = num_cout;
3349 if (ninterp == 0) {
3350 ninterp = 1;
3351 have_perspective = TRUE;
3352 }
3353 if (!spi_baryc_cntl)
3354 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3355
3356 if (!have_perspective && !have_linear)
3357 have_perspective = TRUE;
3358
3359 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3360 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3361 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3362 spi_input_z = 0;
3363 if (pos_index != -1) {
3364 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3365 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3366 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3367 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3368 }
3369
3370 spi_ps_in_control_1 = 0;
3371 if (face_index != -1) {
3372 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3373 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3374 }
3375 if (fixed_pt_position_index != -1) {
3376 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3377 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3378 }
3379
3380 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3381 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3382 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3383
3384 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3385 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3386 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3387
3388 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3389 r600_store_value(cb, shader->bo->gpu_address >> 8);
3390 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3391 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3392 S_028844_PRIME_CACHE_ON_DRAW(1) |
3393 S_028844_DX10_CLAMP(1) |
3394 S_028844_STACK_SIZE(rshader->bc.nstack));
3395 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3396
3397 shader->db_shader_control = db_shader_control;
3398 shader->ps_depth_export = z_export | stencil_export | mask_export;
3399
3400 shader->sprite_coord_enable = sprite_coord_enable;
3401 if (rctx->rasterizer)
3402 shader->flatshade = rctx->rasterizer->flatshade;
3403 }
3404
3405 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3406 {
3407 struct r600_command_buffer *cb = &shader->command_buffer;
3408 struct r600_shader *rshader = &shader->shader;
3409
3410 r600_init_command_buffer(cb, 32);
3411
3412 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3413 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3414 S_028890_DX10_CLAMP(1) |
3415 S_028890_STACK_SIZE(rshader->bc.nstack));
3416 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3417 shader->bo->gpu_address >> 8);
3418 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3419 }
3420
3421 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3422 {
3423 struct r600_context *rctx = (struct r600_context *)ctx;
3424 struct r600_command_buffer *cb = &shader->command_buffer;
3425 struct r600_shader *rshader = &shader->shader;
3426 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3427 unsigned gsvs_itemsizes[4] = {
3428 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3429 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3430 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3431 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3432 };
3433
3434 r600_init_command_buffer(cb, 64);
3435
3436 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3437
3438
3439 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3440 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3441 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3442 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3443
3444 if (rctx->screen->b.info.drm_minor >= 35) {
3445 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3446 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3447 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3448 }
3449 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3450 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3451 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3452 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3453 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3454
3455 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3456 (rshader->ring_item_sizes[0]) >> 2);
3457
3458 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3459 gsvs_itemsizes[0] +
3460 gsvs_itemsizes[1] +
3461 gsvs_itemsizes[2] +
3462 gsvs_itemsizes[3]);
3463
3464 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3465 r600_store_value(cb, gsvs_itemsizes[0]);
3466 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3467 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3468
3469 /* FIXME calculate these values somehow ??? */
3470 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3471 r600_store_value(cb, 0x80); /* GS_PER_ES */
3472 r600_store_value(cb, 0x100); /* ES_PER_GS */
3473 r600_store_value(cb, 0x2); /* GS_PER_VS */
3474
3475 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3476 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3477 S_028878_DX10_CLAMP(1) |
3478 S_028878_STACK_SIZE(rshader->bc.nstack));
3479 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3480 shader->bo->gpu_address >> 8);
3481 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3482 }
3483
3484
3485 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3486 {
3487 struct r600_command_buffer *cb = &shader->command_buffer;
3488 struct r600_shader *rshader = &shader->shader;
3489 unsigned spi_vs_out_id[10] = {};
3490 unsigned i, tmp, nparams = 0;
3491
3492 for (i = 0; i < rshader->noutput; i++) {
3493 if (rshader->output[i].spi_sid) {
3494 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3495 spi_vs_out_id[nparams / 4] |= tmp;
3496 nparams++;
3497 }
3498 }
3499
3500 r600_init_command_buffer(cb, 32);
3501
3502 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3503 for (i = 0; i < 10; i++) {
3504 r600_store_value(cb, spi_vs_out_id[i]);
3505 }
3506
3507 /* Certain attributes (position, psize, etc.) don't count as params.
3508 * VS is required to export at least one param and r600_shader_from_tgsi()
3509 * takes care of adding a dummy export.
3510 */
3511 if (nparams < 1)
3512 nparams = 1;
3513
3514 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3515 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3516 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3517 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3518 S_028860_DX10_CLAMP(1) |
3519 S_028860_STACK_SIZE(rshader->bc.nstack));
3520 if (rshader->vs_position_window_space) {
3521 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3522 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3523 } else {
3524 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3525 S_028818_VTX_W0_FMT(1) |
3526 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3527 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3528 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3529
3530 }
3531 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3532 shader->bo->gpu_address >> 8);
3533 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3534
3535 shader->pa_cl_vs_out_cntl =
3536 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->cc_dist_mask & 0x0F) != 0) |
3537 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->cc_dist_mask & 0xF0) != 0) |
3538 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3539 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3540 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3541 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3542 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3543 }
3544
3545 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3546 {
3547 struct r600_command_buffer *cb = &shader->command_buffer;
3548 struct r600_shader *rshader = &shader->shader;
3549
3550 r600_init_command_buffer(cb, 32);
3551 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3552 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3553 S_0288BC_DX10_CLAMP(1) |
3554 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3555 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3556 shader->bo->gpu_address >> 8);
3557 }
3558
3559 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3560 {
3561 struct r600_command_buffer *cb = &shader->command_buffer;
3562 struct r600_shader *rshader = &shader->shader;
3563
3564 r600_init_command_buffer(cb, 32);
3565 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3566 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3567 S_0288D4_DX10_CLAMP(1) |
3568 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3569 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3570 shader->bo->gpu_address >> 8);
3571 }
3572 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3573 {
3574 struct pipe_blend_state blend;
3575
3576 memset(&blend, 0, sizeof(blend));
3577 blend.independent_blend_enable = true;
3578 blend.rt[0].colormask = 0xf;
3579 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3580 }
3581
3582 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3583 {
3584 struct pipe_blend_state blend;
3585 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3586 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3587
3588 memset(&blend, 0, sizeof(blend));
3589 blend.independent_blend_enable = true;
3590 blend.rt[0].colormask = 0xf;
3591 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3592 }
3593
3594 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3595 {
3596 struct pipe_blend_state blend;
3597 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3598
3599 memset(&blend, 0, sizeof(blend));
3600 blend.independent_blend_enable = true;
3601 blend.rt[0].colormask = 0xf;
3602 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3603 }
3604
3605 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3606 {
3607 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3608
3609 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3610 }
3611
3612 void evergreen_update_db_shader_control(struct r600_context * rctx)
3613 {
3614 bool dual_export;
3615 unsigned db_shader_control;
3616
3617 if (!rctx->ps_shader) {
3618 return;
3619 }
3620
3621 dual_export = rctx->framebuffer.export_16bpc &&
3622 !rctx->ps_shader->current->ps_depth_export;
3623
3624 db_shader_control = rctx->ps_shader->current->db_shader_control |
3625 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3626 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3627 V_02880C_EXPORT_DB_FULL) |
3628 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3629
3630 /* When alpha test is enabled we can't trust the hw to make the proper
3631 * decision on the order in which ztest should be run related to fragment
3632 * shader execution.
3633 *
3634 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3635 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3636 * execution and thus after alpha test so if discarded by the alpha test
3637 * the z value is not written.
3638 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3639 * get a hang unless you flush the DB in between. For now just use
3640 * LATE_Z.
3641 */
3642 if (rctx->alphatest_state.sx_alpha_test_control || rctx->ps_shader->info.writes_memory) {
3643 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3644 } else {
3645 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3646 }
3647
3648 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3649 rctx->db_misc_state.db_shader_control = db_shader_control;
3650 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3651 }
3652 }
3653
3654 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3655 struct pipe_resource *dst,
3656 unsigned dst_level,
3657 unsigned dst_x,
3658 unsigned dst_y,
3659 unsigned dst_z,
3660 struct pipe_resource *src,
3661 unsigned src_level,
3662 unsigned src_x,
3663 unsigned src_y,
3664 unsigned src_z,
3665 unsigned copy_height,
3666 unsigned pitch,
3667 unsigned bpp)
3668 {
3669 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3670 struct r600_texture *rsrc = (struct r600_texture*)src;
3671 struct r600_texture *rdst = (struct r600_texture*)dst;
3672 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3673 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3674 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3675 uint64_t base, addr;
3676
3677 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3678 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3679 assert(dst_mode != src_mode);
3680
3681 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3682 if (util_format_has_depth(util_format_description(src->format)))
3683 non_disp_tiling = 1;
3684
3685 y = 0;
3686 sub_cmd = EG_DMA_COPY_TILED;
3687 lbpp = util_logbase2(bpp);
3688 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3689 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3690
3691 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
3692 /* T2L */
3693 array_mode = evergreen_array_mode(src_mode);
3694 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
3695 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3696 /* linear height must be the same as the slice tile max height, it's ok even
3697 * if the linear destination/source have smaller heigh as the size of the
3698 * dma packet will be using the copy_height which is always smaller or equal
3699 * to the linear height
3700 */
3701 height = u_minify(rsrc->resource.b.b.height0, src_level);
3702 detile = 1;
3703 x = src_x;
3704 y = src_y;
3705 z = src_z;
3706 base = rsrc->surface.u.legacy.level[src_level].offset;
3707 addr = rdst->surface.u.legacy.level[dst_level].offset;
3708 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3709 addr += dst_y * pitch + dst_x * bpp;
3710 bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh);
3711 bank_w = eg_bank_wh(rsrc->surface.u.legacy.bankw);
3712 mt_aspect = eg_macro_tile_aspect(rsrc->surface.u.legacy.mtilea);
3713 tile_split = eg_tile_split(rsrc->surface.u.legacy.tile_split);
3714 base += rsrc->resource.gpu_address;
3715 addr += rdst->resource.gpu_address;
3716 } else {
3717 /* L2T */
3718 array_mode = evergreen_array_mode(dst_mode);
3719 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
3720 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3721 /* linear height must be the same as the slice tile max height, it's ok even
3722 * if the linear destination/source have smaller heigh as the size of the
3723 * dma packet will be using the copy_height which is always smaller or equal
3724 * to the linear height
3725 */
3726 height = u_minify(rdst->resource.b.b.height0, dst_level);
3727 detile = 0;
3728 x = dst_x;
3729 y = dst_y;
3730 z = dst_z;
3731 base = rdst->surface.u.legacy.level[dst_level].offset;
3732 addr = rsrc->surface.u.legacy.level[src_level].offset;
3733 addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z;
3734 addr += src_y * pitch + src_x * bpp;
3735 bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh);
3736 bank_w = eg_bank_wh(rdst->surface.u.legacy.bankw);
3737 mt_aspect = eg_macro_tile_aspect(rdst->surface.u.legacy.mtilea);
3738 tile_split = eg_tile_split(rdst->surface.u.legacy.tile_split);
3739 base += rdst->resource.gpu_address;
3740 addr += rsrc->resource.gpu_address;
3741 }
3742
3743 size = (copy_height * pitch) / 4;
3744 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3745 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
3746
3747 for (i = 0; i < ncopy; i++) {
3748 cheight = copy_height;
3749 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3750 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3751 }
3752 size = (cheight * pitch) / 4;
3753 /* emit reloc before writing cs so that cs is always in consistent state */
3754 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3755 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3756 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3757 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3758 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size));
3759 radeon_emit(cs, base >> 8);
3760 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
3761 (lbpp << 24) | (bank_h << 21) |
3762 (bank_w << 18) | (mt_aspect << 16));
3763 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
3764 radeon_emit(cs, (slice_tile_max << 0));
3765 radeon_emit(cs, (x << 0) | (z << 18));
3766 radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28));
3767 radeon_emit(cs, addr & 0xfffffffc);
3768 radeon_emit(cs, (addr >> 32UL) & 0xff);
3769 copy_height -= cheight;
3770 addr += cheight * pitch;
3771 y += cheight;
3772 }
3773 }
3774
3775 static void evergreen_dma_copy(struct pipe_context *ctx,
3776 struct pipe_resource *dst,
3777 unsigned dst_level,
3778 unsigned dstx, unsigned dsty, unsigned dstz,
3779 struct pipe_resource *src,
3780 unsigned src_level,
3781 const struct pipe_box *src_box)
3782 {
3783 struct r600_context *rctx = (struct r600_context *)ctx;
3784 struct r600_texture *rsrc = (struct r600_texture*)src;
3785 struct r600_texture *rdst = (struct r600_texture*)dst;
3786 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3787 unsigned src_w, dst_w;
3788 unsigned src_x, src_y;
3789 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3790
3791 if (rctx->b.dma.cs == NULL) {
3792 goto fallback;
3793 }
3794
3795 if (rctx->cmd_buf_is_compute) {
3796 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
3797 rctx->cmd_buf_is_compute = false;
3798 }
3799
3800 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3801 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3802 return;
3803 }
3804
3805 if (src_box->depth > 1 ||
3806 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3807 dstz, rsrc, src_level, src_box))
3808 goto fallback;
3809
3810 src_x = util_format_get_nblocksx(src->format, src_box->x);
3811 dst_x = util_format_get_nblocksx(src->format, dst_x);
3812 src_y = util_format_get_nblocksy(src->format, src_box->y);
3813 dst_y = util_format_get_nblocksy(src->format, dst_y);
3814
3815 bpp = rdst->surface.bpe;
3816 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
3817 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
3818 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
3819 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
3820 copy_height = src_box->height / rsrc->surface.blk_h;
3821
3822 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3823 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3824
3825 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3826 /* FIXME evergreen can do partial blit */
3827 goto fallback;
3828 }
3829 /* the x test here are currently useless (because we don't support partial blit)
3830 * but keep them around so we don't forget about those
3831 */
3832 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3833 goto fallback;
3834 }
3835
3836 /* 128 bpp surfaces require non_disp_tiling for both
3837 * tiled and linear buffers on cayman. However, async
3838 * DMA only supports it on the tiled side. As such
3839 * the tile order is backwards after a L2T/T2L packet.
3840 */
3841 if ((rctx->b.chip_class == CAYMAN) &&
3842 (src_mode != dst_mode) &&
3843 (util_format_get_blocksize(src->format) >= 16)) {
3844 goto fallback;
3845 }
3846
3847 if (src_mode == dst_mode) {
3848 uint64_t dst_offset, src_offset;
3849 /* simple dma blit would do NOTE code here assume :
3850 * src_box.x/y == 0
3851 * dst_x/y == 0
3852 * dst_pitch == src_pitch
3853 */
3854 src_offset= rsrc->surface.u.legacy.level[src_level].offset;
3855 src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
3856 src_offset += src_y * src_pitch + src_x * bpp;
3857 dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
3858 dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3859 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3860 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3861 src_box->height * src_pitch);
3862 } else {
3863 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3864 src, src_level, src_x, src_y, src_box->z,
3865 copy_height, dst_pitch, bpp);
3866 }
3867 return;
3868
3869 fallback:
3870 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3871 src, src_level, src_box);
3872 }
3873
3874 static void evergreen_set_tess_state(struct pipe_context *ctx,
3875 const float default_outer_level[4],
3876 const float default_inner_level[2])
3877 {
3878 struct r600_context *rctx = (struct r600_context *)ctx;
3879
3880 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3881 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3882 rctx->driver_consts[PIPE_SHADER_TESS_CTRL].tcs_default_levels_dirty = true;
3883 }
3884
3885 static void evergreen_setup_immed_buffer(struct r600_context *rctx,
3886 struct r600_image_view *rview,
3887 enum pipe_format pformat)
3888 {
3889 struct r600_screen *rscreen = (struct r600_screen *)rctx->b.b.screen;
3890 uint32_t immed_size = rscreen->b.info.max_se * 256 * 64 * util_format_get_blocksize(pformat);
3891 struct eg_buf_res_params buf_params;
3892 bool skip_reloc = false;
3893 struct r600_resource *resource = (struct r600_resource *)rview->base.resource;
3894 if (!resource->immed_buffer) {
3895 eg_resource_alloc_immed(&rscreen->b, resource, immed_size);
3896 }
3897
3898 memset(&buf_params, 0, sizeof(buf_params));
3899 buf_params.pipe_format = pformat;
3900 buf_params.size = resource->immed_buffer->b.b.width0;
3901 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
3902 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
3903 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
3904 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
3905 buf_params.uncached = 1;
3906 evergreen_fill_buffer_resource_words(rctx, &resource->immed_buffer->b.b,
3907 &buf_params, &skip_reloc,
3908 rview->immed_resource_words);
3909 }
3910
3911 static void evergreen_set_hw_atomic_buffers(struct pipe_context *ctx,
3912 unsigned start_slot,
3913 unsigned count,
3914 const struct pipe_shader_buffer *buffers)
3915 {
3916 struct r600_context *rctx = (struct r600_context *)ctx;
3917 struct r600_atomic_buffer_state *astate;
3918 int i, idx;
3919
3920 astate = &rctx->atomic_buffer_state;
3921
3922 /* we'd probably like to expand this to 8 later so put the logic in */
3923 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
3924 const struct pipe_shader_buffer *buf;
3925 struct pipe_shader_buffer *abuf;
3926
3927 abuf = &astate->buffer[i];
3928
3929 if (!buffers || !buffers[idx].buffer) {
3930 pipe_resource_reference(&abuf->buffer, NULL);
3931 astate->enabled_mask &= ~(1 << i);
3932 continue;
3933 }
3934 buf = &buffers[idx];
3935
3936 pipe_resource_reference(&abuf->buffer, buf->buffer);
3937 abuf->buffer_offset = buf->buffer_offset;
3938 abuf->buffer_size = buf->buffer_size;
3939 astate->enabled_mask |= (1 << i);
3940 }
3941 }
3942
3943 static void evergreen_set_shader_buffers(struct pipe_context *ctx,
3944 enum pipe_shader_type shader, unsigned start_slot,
3945 unsigned count,
3946 const struct pipe_shader_buffer *buffers)
3947 {
3948 struct r600_context *rctx = (struct r600_context *)ctx;
3949 struct r600_image_state *istate = NULL;
3950 struct r600_image_view *rview;
3951 struct r600_tex_color_info color;
3952 struct eg_buf_res_params buf_params;
3953 struct r600_resource *resource;
3954 int i, idx;
3955 unsigned old_mask;
3956
3957 if (shader != PIPE_SHADER_FRAGMENT &&
3958 shader != PIPE_SHADER_COMPUTE && count == 0)
3959 return;
3960
3961 if (shader == PIPE_SHADER_FRAGMENT)
3962 istate = &rctx->fragment_buffers;
3963 else if (shader == PIPE_SHADER_COMPUTE)
3964 istate = &rctx->compute_buffers;
3965
3966 old_mask = istate->enabled_mask;
3967 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
3968 const struct pipe_shader_buffer *buf;
3969 unsigned res_type;
3970
3971 rview = &istate->views[i];
3972
3973 if (!buffers || !buffers[idx].buffer) {
3974 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
3975 istate->enabled_mask &= ~(1 << i);
3976 continue;
3977 }
3978
3979 buf = &buffers[idx];
3980 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, buf->buffer);
3981
3982 resource = (struct r600_resource *)rview->base.resource;
3983
3984 evergreen_setup_immed_buffer(rctx, rview, PIPE_FORMAT_R32_UINT);
3985
3986 color.offset = 0;
3987 color.view = 0;
3988 evergreen_set_color_surface_buffer(rctx, resource,
3989 PIPE_FORMAT_R32_UINT,
3990 buf->buffer_offset,
3991 buf->buffer_offset + buf->buffer_size,
3992 &color);
3993
3994 res_type = V_028C70_BUFFER;
3995
3996 rview->cb_color_base = color.offset;
3997 rview->cb_color_dim = color.dim;
3998 rview->cb_color_info = color.info |
3999 S_028C70_RAT(1) |
4000 S_028C70_RESOURCE_TYPE(res_type);
4001 rview->cb_color_pitch = color.pitch;
4002 rview->cb_color_slice = color.slice;
4003 rview->cb_color_view = color.view;
4004 rview->cb_color_attrib = color.attrib;
4005 rview->cb_color_fmask = color.fmask;
4006 rview->cb_color_fmask_slice = color.fmask_slice;
4007
4008 memset(&buf_params, 0, sizeof(buf_params));
4009 buf_params.pipe_format = PIPE_FORMAT_R32_UINT;
4010 buf_params.offset = buf->buffer_offset;
4011 buf_params.size = buf->buffer_size;
4012 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
4013 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
4014 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
4015 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
4016 buf_params.force_swizzle = true;
4017 buf_params.uncached = 1;
4018 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4019 &buf_params,
4020 &rview->skip_mip_address_reloc,
4021 rview->resource_words);
4022
4023 istate->enabled_mask |= (1 << i);
4024 }
4025
4026 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
4027
4028 if (old_mask != istate->enabled_mask)
4029 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4030
4031 if (rctx->cb_misc_state.nr_buffer_rats != util_bitcount(istate->enabled_mask)) {
4032 rctx->cb_misc_state.nr_buffer_rats = util_bitcount(istate->enabled_mask);
4033 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4034 }
4035
4036 r600_mark_atom_dirty(rctx, &istate->atom);
4037 }
4038
4039 static void evergreen_set_shader_images(struct pipe_context *ctx,
4040 enum pipe_shader_type shader, unsigned start_slot,
4041 unsigned count,
4042 const struct pipe_image_view *images)
4043 {
4044 struct r600_context *rctx = (struct r600_context *)ctx;
4045 int i;
4046 struct r600_image_view *rview;
4047 struct pipe_resource *image;
4048 struct r600_resource *resource;
4049 struct r600_tex_color_info color;
4050 struct eg_buf_res_params buf_params;
4051 struct eg_tex_res_params tex_params;
4052 unsigned old_mask;
4053 struct r600_image_state *istate = NULL;
4054 int idx;
4055 if (shader != PIPE_SHADER_FRAGMENT && shader != PIPE_SHADER_COMPUTE && count == 0)
4056 return;
4057
4058 if (shader == PIPE_SHADER_FRAGMENT)
4059 istate = &rctx->fragment_images;
4060 else if (shader == PIPE_SHADER_COMPUTE)
4061 istate = &rctx->compute_images;
4062
4063 assert (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE);
4064
4065 old_mask = istate->enabled_mask;
4066 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4067 unsigned res_type;
4068 const struct pipe_image_view *iview;
4069 rview = &istate->views[i];
4070
4071 if (!images || !images[idx].resource) {
4072 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
4073 istate->enabled_mask &= ~(1 << i);
4074 istate->compressed_colortex_mask &= ~(1 << i);
4075 istate->compressed_depthtex_mask &= ~(1 << i);
4076 continue;
4077 }
4078
4079 iview = &images[idx];
4080 image = iview->resource;
4081 resource = (struct r600_resource *)image;
4082
4083 r600_context_add_resource_size(ctx, image);
4084
4085 rview->base = *iview;
4086 rview->base.resource = NULL;
4087 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, image);
4088
4089 evergreen_setup_immed_buffer(rctx, rview, iview->format);
4090
4091 bool is_buffer = image->target == PIPE_BUFFER;
4092 struct r600_texture *rtex = (struct r600_texture *)image;
4093 if (!is_buffer & rtex->db_compatible)
4094 istate->compressed_depthtex_mask |= 1 << i;
4095 else
4096 istate->compressed_depthtex_mask &= ~(1 << i);
4097
4098 if (!is_buffer && rtex->cmask.size)
4099 istate->compressed_colortex_mask |= 1 << i;
4100 else
4101 istate->compressed_colortex_mask &= ~(1 << i);
4102 if (!is_buffer) {
4103
4104 evergreen_set_color_surface_common(rctx, rtex,
4105 iview->u.tex.level,
4106 iview->u.tex.first_layer,
4107 iview->u.tex.last_layer,
4108 iview->format,
4109 &color);
4110 color.dim = S_028C78_WIDTH_MAX(u_minify(image->width0, iview->u.tex.level) - 1) |
4111 S_028C78_HEIGHT_MAX(u_minify(image->height0, iview->u.tex.level) - 1);
4112 } else {
4113 color.offset = 0;
4114 color.view = 0;
4115 evergreen_set_color_surface_buffer(rctx, resource,
4116 iview->format,
4117 iview->u.buf.offset,
4118 iview->u.buf.size,
4119 &color);
4120 }
4121
4122 switch (image->target) {
4123 case PIPE_BUFFER:
4124 res_type = V_028C70_BUFFER;
4125 break;
4126 case PIPE_TEXTURE_1D:
4127 res_type = V_028C70_TEXTURE1D;
4128 break;
4129 case PIPE_TEXTURE_1D_ARRAY:
4130 res_type = V_028C70_TEXTURE1DARRAY;
4131 break;
4132 case PIPE_TEXTURE_2D:
4133 case PIPE_TEXTURE_RECT:
4134 res_type = V_028C70_TEXTURE2D;
4135 break;
4136 case PIPE_TEXTURE_3D:
4137 res_type = V_028C70_TEXTURE3D;
4138 break;
4139 case PIPE_TEXTURE_2D_ARRAY:
4140 case PIPE_TEXTURE_CUBE:
4141 case PIPE_TEXTURE_CUBE_ARRAY:
4142 res_type = V_028C70_TEXTURE2DARRAY;
4143 break;
4144 default:
4145 assert(0);
4146 res_type = 0;
4147 break;
4148 }
4149
4150 rview->cb_color_base = color.offset;
4151 rview->cb_color_dim = color.dim;
4152 rview->cb_color_info = color.info |
4153 S_028C70_RAT(1) |
4154 S_028C70_RESOURCE_TYPE(res_type);
4155 rview->cb_color_pitch = color.pitch;
4156 rview->cb_color_slice = color.slice;
4157 rview->cb_color_view = color.view;
4158 rview->cb_color_attrib = color.attrib;
4159 rview->cb_color_fmask = color.fmask;
4160 rview->cb_color_fmask_slice = color.fmask_slice;
4161
4162 if (image->target != PIPE_BUFFER) {
4163 memset(&tex_params, 0, sizeof(tex_params));
4164 tex_params.pipe_format = iview->format;
4165 tex_params.force_level = 0;
4166 tex_params.width0 = image->width0;
4167 tex_params.height0 = image->height0;
4168 tex_params.first_level = iview->u.tex.level;
4169 tex_params.last_level = iview->u.tex.level;
4170 tex_params.first_layer = iview->u.tex.first_layer;
4171 tex_params.last_layer = iview->u.tex.last_layer;
4172 tex_params.target = image->target;
4173 tex_params.swizzle[0] = PIPE_SWIZZLE_X;
4174 tex_params.swizzle[1] = PIPE_SWIZZLE_Y;
4175 tex_params.swizzle[2] = PIPE_SWIZZLE_Z;
4176 tex_params.swizzle[3] = PIPE_SWIZZLE_W;
4177 evergreen_fill_tex_resource_words(rctx, &resource->b.b, &tex_params,
4178 &rview->skip_mip_address_reloc,
4179 rview->resource_words);
4180
4181 } else {
4182 memset(&buf_params, 0, sizeof(buf_params));
4183 buf_params.pipe_format = iview->format;
4184 buf_params.size = iview->u.buf.size;
4185 buf_params.offset = iview->u.buf.offset;
4186 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
4187 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
4188 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
4189 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
4190 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4191 &buf_params,
4192 &rview->skip_mip_address_reloc,
4193 rview->resource_words);
4194 }
4195 istate->enabled_mask |= (1 << i);
4196 }
4197
4198 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
4199 istate->dirty_buffer_constants = TRUE;
4200 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
4201 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
4202 R600_CONTEXT_FLUSH_AND_INV_CB_META;
4203
4204 if (old_mask != istate->enabled_mask)
4205 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4206
4207 if (rctx->cb_misc_state.nr_image_rats != util_bitcount(istate->enabled_mask)) {
4208 rctx->cb_misc_state.nr_image_rats = util_bitcount(istate->enabled_mask);
4209 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4210 }
4211
4212 r600_mark_atom_dirty(rctx, &istate->atom);
4213 }
4214
4215 void evergreen_init_state_functions(struct r600_context *rctx)
4216 {
4217 unsigned id = 1;
4218 unsigned i;
4219 /* !!!
4220 * To avoid GPU lockup registers must be emitted in a specific order
4221 * (no kidding ...). The order below is important and have been
4222 * partially inferred from analyzing fglrx command stream.
4223 *
4224 * Don't reorder atom without carefully checking the effect (GPU lockup
4225 * or piglit regression).
4226 * !!!
4227 */
4228 if (rctx->b.chip_class == EVERGREEN) {
4229 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
4230 rctx->config_state.dyn_gpr_enabled = true;
4231 }
4232 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
4233 r600_init_atom(rctx, &rctx->fragment_images.atom, id++, evergreen_emit_fragment_image_state, 0);
4234 r600_init_atom(rctx, &rctx->compute_images.atom, id++, evergreen_emit_compute_image_state, 0);
4235 r600_init_atom(rctx, &rctx->fragment_buffers.atom, id++, evergreen_emit_fragment_buffer_state, 0);
4236 r600_init_atom(rctx, &rctx->compute_buffers.atom, id++, evergreen_emit_compute_buffer_state, 0);
4237 /* shader const */
4238 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
4239 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
4240 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
4241 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
4242 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
4243 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
4244 /* shader program */
4245 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
4246 /* sampler */
4247 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
4248 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
4249 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
4250 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
4251 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
4252 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
4253 /* resources */
4254 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
4255 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
4256 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
4257 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
4258 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
4259 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
4260 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
4261 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
4262
4263 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
4264
4265 if (rctx->b.chip_class == EVERGREEN) {
4266 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
4267 } else {
4268 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
4269 }
4270 rctx->sample_mask.sample_mask = ~0;
4271
4272 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
4273 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
4274 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
4275 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
4276 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
4277 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
4278 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
4279 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
4280 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
4281 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9);
4282 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
4283 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
4284 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
4285 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
4286 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
4287 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
4288 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
4289 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
4290 for (i = 0; i < EG_NUM_HW_STAGES; i++)
4291 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
4292 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
4293 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
4294
4295 rctx->b.b.create_blend_state = evergreen_create_blend_state;
4296 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
4297 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
4298 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
4299 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
4300 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
4301 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
4302 rctx->b.b.set_min_samples = evergreen_set_min_samples;
4303 rctx->b.b.set_tess_state = evergreen_set_tess_state;
4304 rctx->b.b.set_hw_atomic_buffers = evergreen_set_hw_atomic_buffers;
4305 rctx->b.b.set_shader_images = evergreen_set_shader_images;
4306 rctx->b.b.set_shader_buffers = evergreen_set_shader_buffers;
4307 if (rctx->b.chip_class == EVERGREEN)
4308 rctx->b.b.get_sample_position = evergreen_get_sample_position;
4309 else
4310 rctx->b.b.get_sample_position = cayman_get_sample_position;
4311 rctx->b.dma_copy = evergreen_dma_copy;
4312
4313 evergreen_init_compute_state_functions(rctx);
4314 }
4315
4316 /**
4317 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
4318 *
4319 * The information about LDS and other non-compile-time parameters is then
4320 * written to the const buffer.
4321
4322 * const buffer contains -
4323 * uint32_t input_patch_size
4324 * uint32_t input_vertex_size
4325 * uint32_t num_tcs_input_cp
4326 * uint32_t num_tcs_output_cp;
4327 * uint32_t output_patch_size
4328 * uint32_t output_vertex_size
4329 * uint32_t output_patch0_offset
4330 * uint32_t perpatch_output_offset
4331 * and the same constbuf is bound to LS/HS/VS(ES).
4332 */
4333 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
4334 {
4335 struct pipe_constant_buffer constbuf = {0};
4336 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
4337 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
4338 unsigned num_tcs_input_cp = info->vertices_per_patch;
4339 unsigned num_tcs_outputs;
4340 unsigned num_tcs_output_cp;
4341 unsigned num_tcs_patch_outputs;
4342 unsigned num_tcs_inputs;
4343 unsigned input_vertex_size, output_vertex_size;
4344 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
4345 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
4346 uint32_t values[8];
4347 unsigned num_waves;
4348 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
4349 unsigned wave_divisor = (16 * num_pipes);
4350
4351 *num_patches = 1;
4352
4353 if (!rctx->tes_shader) {
4354 rctx->lds_alloc = 0;
4355 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4356 R600_LDS_INFO_CONST_BUFFER, NULL);
4357 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4358 R600_LDS_INFO_CONST_BUFFER, NULL);
4359 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4360 R600_LDS_INFO_CONST_BUFFER, NULL);
4361 return;
4362 }
4363
4364 if (rctx->lds_alloc != 0 &&
4365 rctx->last_ls == ls &&
4366 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
4367 rctx->last_tcs == tcs)
4368 return;
4369
4370 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
4371
4372 if (rctx->tcs_shader) {
4373 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
4374 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
4375 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
4376 } else {
4377 num_tcs_outputs = num_tcs_inputs;
4378 num_tcs_output_cp = num_tcs_input_cp;
4379 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
4380 }
4381
4382 /* size in bytes */
4383 input_vertex_size = num_tcs_inputs * 16;
4384 output_vertex_size = num_tcs_outputs * 16;
4385
4386 input_patch_size = num_tcs_input_cp * input_vertex_size;
4387
4388 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
4389 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
4390
4391 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
4392 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
4393
4394 lds_size = output_patch0_offset + output_patch_size * *num_patches;
4395
4396 values[0] = input_patch_size;
4397 values[1] = input_vertex_size;
4398 values[2] = num_tcs_input_cp;
4399 values[3] = num_tcs_output_cp;
4400
4401 values[4] = output_patch_size;
4402 values[5] = output_vertex_size;
4403 values[6] = output_patch0_offset;
4404 values[7] = perpatch_output_offset;
4405
4406 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
4407 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
4408 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
4409
4410 rctx->lds_alloc = (lds_size | (num_waves << 14));
4411
4412 rctx->last_ls = ls;
4413 rctx->last_tcs = tcs;
4414 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
4415
4416 constbuf.user_buffer = values;
4417 constbuf.buffer_size = 8 * 4;
4418
4419 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4420 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4421 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4422 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4423 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4424 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4425 pipe_resource_reference(&constbuf.buffer, NULL);
4426 }
4427
4428 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
4429 const struct pipe_draw_info *info,
4430 unsigned num_patches)
4431 {
4432 unsigned num_output_cp;
4433
4434 if (!rctx->tes_shader)
4435 return 0;
4436
4437 num_output_cp = rctx->tcs_shader ?
4438 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
4439 info->vertices_per_patch;
4440
4441 return S_028B58_NUM_PATCHES(num_patches) |
4442 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
4443 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
4444 }
4445
4446 void evergreen_set_ls_hs_config(struct r600_context *rctx,
4447 struct radeon_winsys_cs *cs,
4448 uint32_t ls_hs_config)
4449 {
4450 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
4451 }
4452
4453 void evergreen_set_lds_alloc(struct r600_context *rctx,
4454 struct radeon_winsys_cs *cs,
4455 uint32_t lds_alloc)
4456 {
4457 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
4458 }
4459
4460 /* on evergreen if you are running tessellation you need to disable dynamic
4461 GPRs to workaround a hardware bug.*/
4462 bool evergreen_adjust_gprs(struct r600_context *rctx)
4463 {
4464 unsigned num_gprs[EG_NUM_HW_STAGES];
4465 unsigned def_gprs[EG_NUM_HW_STAGES];
4466 unsigned cur_gprs[EG_NUM_HW_STAGES];
4467 unsigned new_gprs[EG_NUM_HW_STAGES];
4468 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
4469 unsigned max_gprs;
4470 unsigned i;
4471 unsigned total_gprs;
4472 unsigned tmp[3];
4473 bool rework = false, set_default = false, set_dirty = false;
4474 max_gprs = 0;
4475 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4476 def_gprs[i] = rctx->default_gprs[i];
4477 max_gprs += def_gprs[i];
4478 }
4479 max_gprs += def_num_clause_temp_gprs * 2;
4480
4481 /* if we have no TESS and dyn gpr is enabled then do nothing. */
4482 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
4483 if (rctx->config_state.dyn_gpr_enabled)
4484 return true;
4485
4486 /* transition back to dyn gpr enabled state */
4487 rctx->config_state.dyn_gpr_enabled = true;
4488 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4489 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4490 return true;
4491 }
4492
4493
4494 /* gather required shader gprs */
4495 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4496 if (rctx->hw_shader_stages[i].shader)
4497 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
4498 else
4499 num_gprs[i] = 0;
4500 }
4501
4502 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4503 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4504 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4505 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4506 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4507 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4508
4509 total_gprs = 0;
4510 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4511 new_gprs[i] = num_gprs[i];
4512 total_gprs += num_gprs[i];
4513 }
4514
4515 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
4516 return false;
4517
4518 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4519 if (new_gprs[i] > cur_gprs[i]) {
4520 rework = true;
4521 break;
4522 }
4523 }
4524
4525 if (rctx->config_state.dyn_gpr_enabled) {
4526 set_dirty = true;
4527 rctx->config_state.dyn_gpr_enabled = false;
4528 }
4529
4530 if (rework) {
4531 set_default = true;
4532 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4533 if (new_gprs[i] > def_gprs[i])
4534 set_default = false;
4535 }
4536
4537 if (set_default) {
4538 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4539 new_gprs[i] = def_gprs[i];
4540 }
4541 } else {
4542 unsigned ps_value = max_gprs;
4543
4544 ps_value -= (def_num_clause_temp_gprs * 2);
4545 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
4546 ps_value -= new_gprs[i];
4547
4548 new_gprs[R600_HW_STAGE_PS] = ps_value;
4549 }
4550
4551 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
4552 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
4553 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
4554
4555 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
4556 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
4557
4558 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
4559 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
4560
4561 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
4562 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
4563 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
4564 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
4565 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
4566 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
4567 set_dirty = true;
4568 }
4569 }
4570
4571
4572 if (set_dirty) {
4573 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4574 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4575 }
4576 return true;
4577 }
4578
4579 #define AC_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
4580
4581 void eg_trace_emit(struct r600_context *rctx)
4582 {
4583 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4584 unsigned reloc;
4585
4586 if (rctx->b.chip_class < EVERGREEN)
4587 return;
4588
4589 /* This must be done after r600_need_cs_space. */
4590 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4591 (struct r600_resource*)rctx->trace_buf, RADEON_USAGE_WRITE,
4592 RADEON_PRIO_CP_DMA);
4593
4594 rctx->trace_id++;
4595 radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rctx->trace_buf,
4596 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
4597 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
4598 radeon_emit(cs, rctx->trace_buf->gpu_address);
4599 radeon_emit(cs, rctx->trace_buf->gpu_address >> 32 | MEM_WRITE_32_BITS | MEM_WRITE_CONFIRM);
4600 radeon_emit(cs, rctx->trace_id);
4601 radeon_emit(cs, 0);
4602 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4603 radeon_emit(cs, reloc);
4604 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4605 radeon_emit(cs, AC_ENCODE_TRACE_POINT(rctx->trace_id));
4606 }
4607
4608 static void evergreen_emit_set_append_cnt(struct r600_context *rctx,
4609 struct r600_shader_atomic *atomic,
4610 struct r600_resource *resource,
4611 uint32_t pkt_flags)
4612 {
4613 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4614 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4615 resource,
4616 RADEON_USAGE_READ,
4617 RADEON_PRIO_SHADER_RW_BUFFER);
4618 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4619 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4620
4621 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4 - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
4622
4623 radeon_emit(cs, PKT3(PKT3_SET_APPEND_CNT, 2, 0) | pkt_flags);
4624 radeon_emit(cs, (reg_val << 16) | 0x3);
4625 radeon_emit(cs, dst_offset & 0xfffffffc);
4626 radeon_emit(cs, (dst_offset >> 32) & 0xff);
4627 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4628 radeon_emit(cs, reloc);
4629 }
4630
4631 static void evergreen_emit_event_write_eos(struct r600_context *rctx,
4632 struct r600_shader_atomic *atomic,
4633 struct r600_resource *resource,
4634 uint32_t pkt_flags)
4635 {
4636 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4637 uint32_t event = EVENT_TYPE_PS_DONE;
4638 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4639 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4640 resource,
4641 RADEON_USAGE_WRITE,
4642 RADEON_PRIO_SHADER_RW_BUFFER);
4643 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4644 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4) >> 2;
4645
4646 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4647 event = EVENT_TYPE_CS_DONE;
4648
4649 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4650 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4651 radeon_emit(cs, (dst_offset) & 0xffffffff);
4652 radeon_emit(cs, (0 << 29) | ((dst_offset >> 32) & 0xff));
4653 radeon_emit(cs, reg_val);
4654 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4655 radeon_emit(cs, reloc);
4656 }
4657
4658 static void cayman_emit_event_write_eos(struct r600_context *rctx,
4659 struct r600_shader_atomic *atomic,
4660 struct r600_resource *resource,
4661 uint32_t pkt_flags)
4662 {
4663 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4664 uint32_t event = EVENT_TYPE_PS_DONE;
4665 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4666 resource,
4667 RADEON_USAGE_WRITE,
4668 RADEON_PRIO_SHADER_RW_BUFFER);
4669 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4670
4671 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4672 event = EVENT_TYPE_CS_DONE;
4673
4674 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4675 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4676 radeon_emit(cs, (dst_offset) & 0xffffffff);
4677 radeon_emit(cs, (1 << 29) | ((dst_offset >> 32) & 0xff));
4678 radeon_emit(cs, (atomic->hw_idx) | (1 << 16));
4679 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4680 radeon_emit(cs, reloc);
4681 }
4682
4683 /* writes count from a buffer into GDS */
4684 static void cayman_write_count_to_gds(struct r600_context *rctx,
4685 struct r600_shader_atomic *atomic,
4686 struct r600_resource *resource,
4687 uint32_t pkt_flags)
4688 {
4689 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4690 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4691 resource,
4692 RADEON_USAGE_READ,
4693 RADEON_PRIO_SHADER_RW_BUFFER);
4694 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4695
4696 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0) | pkt_flags);
4697 radeon_emit(cs, dst_offset & 0xffffffff);
4698 radeon_emit(cs, PKT3_CP_DMA_CP_SYNC | PKT3_CP_DMA_DST_SEL(1) | ((dst_offset >> 32) & 0xff));// GDS
4699 radeon_emit(cs, atomic->hw_idx * 4);
4700 radeon_emit(cs, 0);
4701 radeon_emit(cs, PKT3_CP_DMA_CMD_DAS | 4);
4702 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4703 radeon_emit(cs, reloc);
4704 }
4705
4706 bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
4707 struct r600_pipe_shader *cs_shader,
4708 struct r600_shader_atomic *combined_atomics,
4709 uint8_t *atomic_used_mask_p)
4710 {
4711 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4712 unsigned pkt_flags = 0;
4713 uint8_t atomic_used_mask = 0;
4714 int i, j, k;
4715 bool is_compute = cs_shader ? true : false;
4716
4717 if (is_compute)
4718 pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
4719
4720 for (i = 0; i < (is_compute ? 1 : EG_NUM_HW_STAGES); i++) {
4721 uint8_t num_atomic_stage;
4722 struct r600_pipe_shader *pshader;
4723
4724 if (is_compute)
4725 pshader = cs_shader;
4726 else
4727 pshader = rctx->hw_shader_stages[i].shader;
4728 if (!pshader)
4729 continue;
4730
4731 num_atomic_stage = pshader->shader.nhwatomic_ranges;
4732 if (!num_atomic_stage)
4733 continue;
4734
4735 for (j = 0; j < num_atomic_stage; j++) {
4736 struct r600_shader_atomic *atomic = &pshader->shader.atomics[j];
4737 int natomics = atomic->end - atomic->start + 1;
4738
4739 for (k = 0; k < natomics; k++) {
4740 /* seen this in a previous stage */
4741 if (atomic_used_mask & (1u << (atomic->hw_idx + k)))
4742 continue;
4743
4744 combined_atomics[atomic->hw_idx + k].hw_idx = atomic->hw_idx + k;
4745 combined_atomics[atomic->hw_idx + k].buffer_id = atomic->buffer_id;
4746 combined_atomics[atomic->hw_idx + k].start = atomic->start + k;
4747 combined_atomics[atomic->hw_idx + k].end = combined_atomics[atomic->hw_idx + k].start + 1;
4748 atomic_used_mask |= (1u << (atomic->hw_idx + k));
4749 }
4750 }
4751 }
4752
4753 uint32_t mask = atomic_used_mask;
4754 while (mask) {
4755 unsigned atomic_index = u_bit_scan(&mask);
4756 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
4757 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
4758 assert(resource);
4759
4760 if (rctx->b.chip_class == CAYMAN)
4761 cayman_write_count_to_gds(rctx, atomic, resource, pkt_flags);
4762 else
4763 evergreen_emit_set_append_cnt(rctx, atomic, resource, pkt_flags);
4764 }
4765 *atomic_used_mask_p = atomic_used_mask;
4766 return true;
4767 }
4768
4769 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
4770 bool is_compute,
4771 struct r600_shader_atomic *combined_atomics,
4772 uint8_t *atomic_used_mask_p)
4773 {
4774 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4775 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4776 uint32_t pkt_flags = 0;
4777 uint32_t event = EVENT_TYPE_PS_DONE;
4778 uint32_t mask = astate->enabled_mask;
4779 uint64_t dst_offset;
4780 unsigned reloc;
4781
4782 if (is_compute)
4783 pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
4784
4785 mask = *atomic_used_mask_p;
4786 if (!mask)
4787 return;
4788
4789 while (mask) {
4790 unsigned atomic_index = u_bit_scan(&mask);
4791 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
4792 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
4793 assert(resource);
4794
4795 if (rctx->b.chip_class == CAYMAN)
4796 cayman_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
4797 else
4798 evergreen_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
4799 }
4800
4801 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4802 event = EVENT_TYPE_CS_DONE;
4803
4804 ++rctx->append_fence_id;
4805 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4806 r600_resource(rctx->append_fence),
4807 RADEON_USAGE_READWRITE,
4808 RADEON_PRIO_SHADER_RW_BUFFER);
4809 dst_offset = r600_resource(rctx->append_fence)->gpu_address;
4810 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4811 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4812 radeon_emit(cs, dst_offset & 0xffffffff);
4813 radeon_emit(cs, (2 << 29) | ((dst_offset >> 32) & 0xff));
4814 radeon_emit(cs, rctx->append_fence_id);
4815 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4816 radeon_emit(cs, reloc);
4817
4818 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0) | pkt_flags);
4819 radeon_emit(cs, WAIT_REG_MEM_GEQUAL | WAIT_REG_MEM_MEMORY | (1 << 8));
4820 radeon_emit(cs, dst_offset & 0xffffffff);
4821 radeon_emit(cs, ((dst_offset >> 32) & 0xff));
4822 radeon_emit(cs, rctx->append_fence_id);
4823 radeon_emit(cs, 0xffffffff);
4824 radeon_emit(cs, 0xa);
4825 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4826 radeon_emit(cs, reloc);
4827 }