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r600g: simplify r600_set_occlusion_query_state
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static inline unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
39 break;
40 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
41 break;
42 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
43 default:
44 case RADEON_SURF_MODE_LINEAR: return V_028C70_ARRAY_LINEAR_GENERAL;
45 }
46 }
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
174 {
175 switch (dim) {
176 default:
177 case PIPE_TEXTURE_1D:
178 return V_030000_SQ_TEX_DIM_1D;
179 case PIPE_TEXTURE_1D_ARRAY:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY;
181 case PIPE_TEXTURE_2D:
182 case PIPE_TEXTURE_RECT:
183 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
184 V_030000_SQ_TEX_DIM_2D;
185 case PIPE_TEXTURE_2D_ARRAY:
186 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
187 V_030000_SQ_TEX_DIM_2D_ARRAY;
188 case PIPE_TEXTURE_3D:
189 return V_030000_SQ_TEX_DIM_3D;
190 case PIPE_TEXTURE_CUBE:
191 case PIPE_TEXTURE_CUBE_ARRAY:
192 return V_030000_SQ_TEX_DIM_CUBEMAP;
193 }
194 }
195
196 static uint32_t r600_translate_dbformat(enum pipe_format format)
197 {
198 switch (format) {
199 case PIPE_FORMAT_Z16_UNORM:
200 return V_028040_Z_16;
201 case PIPE_FORMAT_Z24X8_UNORM:
202 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
203 case PIPE_FORMAT_X8Z24_UNORM:
204 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
205 return V_028040_Z_24;
206 case PIPE_FORMAT_Z32_FLOAT:
207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
208 return V_028040_Z_32_FLOAT;
209 default:
210 return ~0U;
211 }
212 }
213
214 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
215 {
216 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
217 }
218
219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
220 {
221 return r600_translate_colorformat(chip, format) != ~0U &&
222 r600_translate_colorswap(format) != ~0U;
223 }
224
225 static bool r600_is_zs_format_supported(enum pipe_format format)
226 {
227 return r600_translate_dbformat(format) != ~0U;
228 }
229
230 boolean evergreen_is_format_supported(struct pipe_screen *screen,
231 enum pipe_format format,
232 enum pipe_texture_target target,
233 unsigned sample_count,
234 unsigned usage)
235 {
236 struct r600_screen *rscreen = (struct r600_screen*)screen;
237 unsigned retval = 0;
238
239 if (target >= PIPE_MAX_TEXTURE_TYPES) {
240 R600_ERR("r600: unsupported texture type %d\n", target);
241 return FALSE;
242 }
243
244 if (!util_format_is_supported(format, usage))
245 return FALSE;
246
247 if (sample_count > 1) {
248 if (!rscreen->has_msaa)
249 return FALSE;
250
251 switch (sample_count) {
252 case 2:
253 case 4:
254 case 8:
255 break;
256 default:
257 return FALSE;
258 }
259 }
260
261 if (usage & PIPE_BIND_SAMPLER_VIEW) {
262 if (target == PIPE_BUFFER) {
263 if (r600_is_vertex_format_supported(format))
264 retval |= PIPE_BIND_SAMPLER_VIEW;
265 } else {
266 if (r600_is_sampler_format_supported(screen, format))
267 retval |= PIPE_BIND_SAMPLER_VIEW;
268 }
269 }
270
271 if ((usage & (PIPE_BIND_RENDER_TARGET |
272 PIPE_BIND_DISPLAY_TARGET |
273 PIPE_BIND_SCANOUT |
274 PIPE_BIND_SHARED |
275 PIPE_BIND_BLENDABLE)) &&
276 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
277 retval |= usage &
278 (PIPE_BIND_RENDER_TARGET |
279 PIPE_BIND_DISPLAY_TARGET |
280 PIPE_BIND_SCANOUT |
281 PIPE_BIND_SHARED);
282 if (!util_format_is_pure_integer(format) &&
283 !util_format_is_depth_or_stencil(format))
284 retval |= usage & PIPE_BIND_BLENDABLE;
285 }
286
287 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
288 r600_is_zs_format_supported(format)) {
289 retval |= PIPE_BIND_DEPTH_STENCIL;
290 }
291
292 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
293 r600_is_vertex_format_supported(format)) {
294 retval |= PIPE_BIND_VERTEX_BUFFER;
295 }
296
297 if (usage & PIPE_BIND_TRANSFER_READ)
298 retval |= PIPE_BIND_TRANSFER_READ;
299 if (usage & PIPE_BIND_TRANSFER_WRITE)
300 retval |= PIPE_BIND_TRANSFER_WRITE;
301
302 if ((usage & PIPE_BIND_LINEAR) &&
303 !util_format_is_compressed(format) &&
304 !(usage & PIPE_BIND_DEPTH_STENCIL))
305 retval |= PIPE_BIND_LINEAR;
306
307 return retval == usage;
308 }
309
310 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
311 const struct pipe_blend_state *state, int mode)
312 {
313 uint32_t color_control = 0, target_mask = 0;
314 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
315
316 if (!blend) {
317 return NULL;
318 }
319
320 r600_init_command_buffer(&blend->buffer, 20);
321 r600_init_command_buffer(&blend->buffer_no_blend, 20);
322
323 if (state->logicop_enable) {
324 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
325 } else {
326 color_control |= (0xcc << 16);
327 }
328 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
329 if (state->independent_blend_enable) {
330 for (int i = 0; i < 8; i++) {
331 target_mask |= (state->rt[i].colormask << (4 * i));
332 }
333 } else {
334 for (int i = 0; i < 8; i++) {
335 target_mask |= (state->rt[0].colormask << (4 * i));
336 }
337 }
338
339 /* only have dual source on MRT0 */
340 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
341 blend->cb_target_mask = target_mask;
342 blend->alpha_to_one = state->alpha_to_one;
343
344 if (target_mask)
345 color_control |= S_028808_MODE(mode);
346 else
347 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
348
349
350 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
351 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
352 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
353 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
354 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
355 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
356 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
357 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
358
359 /* Copy over the dwords set so far into buffer_no_blend.
360 * Only the CB_BLENDi_CONTROL registers must be set after this. */
361 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
362 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
363
364 for (int i = 0; i < 8; i++) {
365 /* state->rt entries > 0 only written if independent blending */
366 const int j = state->independent_blend_enable ? i : 0;
367
368 unsigned eqRGB = state->rt[j].rgb_func;
369 unsigned srcRGB = state->rt[j].rgb_src_factor;
370 unsigned dstRGB = state->rt[j].rgb_dst_factor;
371 unsigned eqA = state->rt[j].alpha_func;
372 unsigned srcA = state->rt[j].alpha_src_factor;
373 unsigned dstA = state->rt[j].alpha_dst_factor;
374 uint32_t bc = 0;
375
376 r600_store_value(&blend->buffer_no_blend, 0);
377
378 if (!state->rt[j].blend_enable) {
379 r600_store_value(&blend->buffer, 0);
380 continue;
381 }
382
383 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
384 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
385 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
386 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
387
388 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
389 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
390 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
391 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
392 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
393 }
394 r600_store_value(&blend->buffer, bc);
395 }
396 return blend;
397 }
398
399 static void *evergreen_create_blend_state(struct pipe_context *ctx,
400 const struct pipe_blend_state *state)
401 {
402
403 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
404 }
405
406 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
407 const struct pipe_depth_stencil_alpha_state *state)
408 {
409 unsigned db_depth_control, alpha_test_control, alpha_ref;
410 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
411
412 if (!dsa) {
413 return NULL;
414 }
415
416 r600_init_command_buffer(&dsa->buffer, 3);
417
418 dsa->valuemask[0] = state->stencil[0].valuemask;
419 dsa->valuemask[1] = state->stencil[1].valuemask;
420 dsa->writemask[0] = state->stencil[0].writemask;
421 dsa->writemask[1] = state->stencil[1].writemask;
422 dsa->zwritemask = state->depth.writemask;
423
424 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
425 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
426 S_028800_ZFUNC(state->depth.func);
427
428 /* stencil */
429 if (state->stencil[0].enabled) {
430 db_depth_control |= S_028800_STENCIL_ENABLE(1);
431 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
432 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
433 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
434 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
435
436 if (state->stencil[1].enabled) {
437 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
438 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
439 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
440 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
441 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
442 }
443 }
444
445 /* alpha */
446 alpha_test_control = 0;
447 alpha_ref = 0;
448 if (state->alpha.enabled) {
449 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
450 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
451 alpha_ref = fui(state->alpha.ref_value);
452 }
453 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
454 dsa->alpha_ref = alpha_ref;
455
456 /* misc */
457 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
458 return dsa;
459 }
460
461 static void *evergreen_create_rs_state(struct pipe_context *ctx,
462 const struct pipe_rasterizer_state *state)
463 {
464 struct r600_context *rctx = (struct r600_context *)ctx;
465 unsigned tmp, spi_interp;
466 float psize_min, psize_max;
467 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
468
469 if (!rs) {
470 return NULL;
471 }
472
473 r600_init_command_buffer(&rs->buffer, 30);
474
475 rs->flatshade = state->flatshade;
476 rs->sprite_coord_enable = state->sprite_coord_enable;
477 rs->two_side = state->light_twoside;
478 rs->clip_plane_enable = state->clip_plane_enable;
479 rs->pa_sc_line_stipple = state->line_stipple_enable ?
480 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
481 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
482 rs->pa_cl_clip_cntl =
483 S_028810_PS_UCP_MODE(3) |
484 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
485 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
486 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
487 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
488 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
489 rs->multisample_enable = state->multisample;
490
491 /* offset */
492 rs->offset_units = state->offset_units;
493 rs->offset_scale = state->offset_scale * 16.0f;
494 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
495
496 if (state->point_size_per_vertex) {
497 psize_min = util_get_min_point_size(state);
498 psize_max = 8192;
499 } else {
500 /* Force the point size to be as if the vertex output was disabled. */
501 psize_min = state->point_size;
502 psize_max = state->point_size;
503 }
504
505 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
506 if (state->sprite_coord_enable) {
507 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
508 S_0286D4_PNT_SPRITE_OVRD_X(2) |
509 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
510 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
511 S_0286D4_PNT_SPRITE_OVRD_W(1);
512 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
513 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
514 }
515 }
516
517 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
518 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
519 tmp = r600_pack_float_12p4(state->point_size/2);
520 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
521 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
522 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
523 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
524 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
525 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
526 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
527
528 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
529 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
530 S_028A48_MSAA_ENABLE(state->multisample) |
531 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
532 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
533
534 if (rctx->b.chip_class == CAYMAN) {
535 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
536 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
537 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
538 } else {
539 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
540 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
541 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
542 }
543
544 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
545 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
546 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
547 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
548 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
549 S_028814_FACE(!state->front_ccw) |
550 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
551 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
552 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
553 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
554 state->fill_back != PIPE_POLYGON_MODE_FILL) |
555 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
556 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
557 return rs;
558 }
559
560 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
561 const struct pipe_sampler_state *state)
562 {
563 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
564 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
565
566 if (!ss) {
567 return NULL;
568 }
569
570 ss->border_color_use = sampler_state_needs_border_color(state);
571
572 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
573 ss->tex_sampler_words[0] =
574 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
575 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
576 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
577 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
578 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
579 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
580 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
581 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
582 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
583 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
584 ss->tex_sampler_words[1] =
585 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
586 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
587 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
588 ss->tex_sampler_words[2] =
589 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
590 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
591 S_03C008_TYPE(1);
592
593 if (ss->border_color_use) {
594 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
595 }
596 return ss;
597 }
598
599 static struct pipe_sampler_view *
600 texture_buffer_sampler_view(struct r600_context *rctx,
601 struct r600_pipe_sampler_view *view,
602 unsigned width0, unsigned height0)
603
604 {
605 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
606 uint64_t va;
607 int stride = util_format_get_blocksize(view->base.format);
608 unsigned format, num_format, format_comp, endian;
609 unsigned swizzle_res;
610 unsigned char swizzle[4];
611 const struct util_format_description *desc;
612 unsigned offset = view->base.u.buf.first_element * stride;
613 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
614
615 swizzle[0] = view->base.swizzle_r;
616 swizzle[1] = view->base.swizzle_g;
617 swizzle[2] = view->base.swizzle_b;
618 swizzle[3] = view->base.swizzle_a;
619
620 r600_vertex_data_type(view->base.format,
621 &format, &num_format, &format_comp,
622 &endian);
623
624 desc = util_format_description(view->base.format);
625
626 swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
627
628 va = tmp->resource.gpu_address + offset;
629 view->tex_resource = &tmp->resource;
630
631 view->skip_mip_address_reloc = true;
632 view->tex_resource_words[0] = va;
633 view->tex_resource_words[1] = size - 1;
634 view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
635 S_030008_STRIDE(stride) |
636 S_030008_DATA_FORMAT(format) |
637 S_030008_NUM_FORMAT_ALL(num_format) |
638 S_030008_FORMAT_COMP_ALL(format_comp) |
639 S_030008_ENDIAN_SWAP(endian);
640 view->tex_resource_words[3] = swizzle_res;
641 /*
642 * in theory dword 4 is for number of elements, for use with resinfo,
643 * but it seems to utterly fail to work, the amd gpu shader analyser
644 * uses a const buffer to store the element sizes for buffer txq
645 */
646 view->tex_resource_words[4] = 0;
647 view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
648 view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
649
650 if (tmp->resource.gpu_address)
651 LIST_ADDTAIL(&view->list, &rctx->b.texture_buffers);
652 return &view->base;
653 }
654
655 struct pipe_sampler_view *
656 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
657 struct pipe_resource *texture,
658 const struct pipe_sampler_view *state,
659 unsigned width0, unsigned height0,
660 unsigned force_level)
661 {
662 struct r600_context *rctx = (struct r600_context*)ctx;
663 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
664 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
665 struct r600_texture *tmp = (struct r600_texture*)texture;
666 unsigned format, endian;
667 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
668 unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
669 unsigned height, depth, width;
670 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
671 enum pipe_format pipe_format = state->format;
672 struct radeon_surf_level *surflevel;
673 unsigned base_level, first_level, last_level;
674 unsigned dim, last_layer;
675 uint64_t va;
676
677 if (!view)
678 return NULL;
679
680 /* initialize base object */
681 view->base = *state;
682 view->base.texture = NULL;
683 pipe_reference(NULL, &texture->reference);
684 view->base.texture = texture;
685 view->base.reference.count = 1;
686 view->base.context = ctx;
687
688 if (state->target == PIPE_BUFFER)
689 return texture_buffer_sampler_view(rctx, view, width0, height0);
690
691 swizzle[0] = state->swizzle_r;
692 swizzle[1] = state->swizzle_g;
693 swizzle[2] = state->swizzle_b;
694 swizzle[3] = state->swizzle_a;
695
696 tile_split = tmp->surface.tile_split;
697 surflevel = tmp->surface.level;
698
699 /* Texturing with separate depth and stencil. */
700 if (tmp->is_depth && !tmp->is_flushing_texture) {
701 switch (pipe_format) {
702 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
703 pipe_format = PIPE_FORMAT_Z32_FLOAT;
704 break;
705 case PIPE_FORMAT_X8Z24_UNORM:
706 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
707 /* Z24 is always stored like this. */
708 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
709 break;
710 case PIPE_FORMAT_X24S8_UINT:
711 case PIPE_FORMAT_S8X24_UINT:
712 case PIPE_FORMAT_X32_S8X24_UINT:
713 pipe_format = PIPE_FORMAT_S8_UINT;
714 tile_split = tmp->surface.stencil_tile_split;
715 surflevel = tmp->surface.stencil_level;
716 break;
717 default:;
718 }
719 }
720
721 format = r600_translate_texformat(ctx->screen, pipe_format,
722 swizzle,
723 &word4, &yuv_format);
724 assert(format != ~0);
725 if (format == ~0) {
726 FREE(view);
727 return NULL;
728 }
729
730 endian = r600_colorformat_endian_swap(format);
731
732 base_level = 0;
733 first_level = state->u.tex.first_level;
734 last_level = state->u.tex.last_level;
735 width = width0;
736 height = height0;
737 depth = texture->depth0;
738
739 if (force_level) {
740 base_level = force_level;
741 first_level = 0;
742 last_level = 0;
743 width = u_minify(width, force_level);
744 height = u_minify(height, force_level);
745 depth = u_minify(depth, force_level);
746 }
747
748 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
749 non_disp_tiling = tmp->non_disp_tiling;
750
751 switch (surflevel[base_level].mode) {
752 case RADEON_SURF_MODE_LINEAR_ALIGNED:
753 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
754 break;
755 case RADEON_SURF_MODE_2D:
756 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
757 break;
758 case RADEON_SURF_MODE_1D:
759 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
760 break;
761 case RADEON_SURF_MODE_LINEAR:
762 default:
763 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
764 break;
765 }
766 macro_aspect = tmp->surface.mtilea;
767 bankw = tmp->surface.bankw;
768 bankh = tmp->surface.bankh;
769 tile_split = eg_tile_split(tile_split);
770 macro_aspect = eg_macro_tile_aspect(macro_aspect);
771 bankw = eg_bank_wh(bankw);
772 bankh = eg_bank_wh(bankh);
773 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
774
775 /* 128 bit formats require tile type = 1 */
776 if (rscreen->b.chip_class == CAYMAN) {
777 if (util_format_get_blocksize(pipe_format) >= 16)
778 non_disp_tiling = 1;
779 }
780 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
781
782 if (state->target == PIPE_TEXTURE_1D_ARRAY) {
783 height = 1;
784 depth = texture->array_size;
785 } else if (state->target == PIPE_TEXTURE_2D_ARRAY) {
786 depth = texture->array_size;
787 } else if (state->target == PIPE_TEXTURE_CUBE_ARRAY)
788 depth = texture->array_size / 6;
789
790 va = tmp->resource.gpu_address;
791
792 if (state->format == PIPE_FORMAT_X24S8_UINT ||
793 state->format == PIPE_FORMAT_S8X24_UINT ||
794 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
795 state->format == PIPE_FORMAT_S8_UINT)
796 view->is_stencil_sampler = true;
797
798 view->tex_resource = &tmp->resource;
799
800 /* array type views and views into array types need to use layer offset */
801 dim = state->target;
802 if (state->target != PIPE_TEXTURE_CUBE)
803 dim = MAX2(state->target, texture->target);
804
805 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(dim, texture->nr_samples)) |
806 S_030000_PITCH((pitch / 8) - 1) |
807 S_030000_TEX_WIDTH(width - 1));
808 if (rscreen->b.chip_class == CAYMAN)
809 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
810 else
811 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
812 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
813 S_030004_TEX_DEPTH(depth - 1) |
814 S_030004_ARRAY_MODE(array_mode));
815 view->tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
816
817 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
818 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
819 if (tmp->is_depth) {
820 /* disable FMASK (0 = disabled) */
821 view->tex_resource_words[3] = 0;
822 view->skip_mip_address_reloc = true;
823 } else {
824 /* FMASK should be in MIP_ADDRESS for multisample textures */
825 view->tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
826 }
827 } else if (last_level && texture->nr_samples <= 1) {
828 view->tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
829 } else {
830 view->tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
831 }
832
833 last_layer = state->u.tex.last_layer;
834 if (state->target != texture->target && depth == 1) {
835 last_layer = state->u.tex.first_layer;
836 }
837 view->tex_resource_words[4] = (word4 |
838 S_030010_ENDIAN_SWAP(endian));
839 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
840 S_030014_LAST_ARRAY(last_layer);
841 view->tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
842
843 if (texture->nr_samples > 1) {
844 unsigned log_samples = util_logbase2(texture->nr_samples);
845 if (rscreen->b.chip_class == CAYMAN) {
846 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
847 }
848 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
849 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
850 view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
851 } else {
852 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
853 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
854 /* aniso max 16 samples */
855 view->tex_resource_words[6] |= S_030018_MAX_ANISO(4);
856 }
857
858 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
859 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
860 S_03001C_BANK_WIDTH(bankw) |
861 S_03001C_BANK_HEIGHT(bankh) |
862 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
863 S_03001C_NUM_BANKS(nbanks) |
864 S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
865 return &view->base;
866 }
867
868 static struct pipe_sampler_view *
869 evergreen_create_sampler_view(struct pipe_context *ctx,
870 struct pipe_resource *tex,
871 const struct pipe_sampler_view *state)
872 {
873 return evergreen_create_sampler_view_custom(ctx, tex, state,
874 tex->width0, tex->height0, 0);
875 }
876
877 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
878 {
879 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
880 struct r600_config_state *a = (struct r600_config_state*)atom;
881
882 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
883 if (a->dyn_gpr_enabled) {
884 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
885 radeon_emit(cs, 0);
886 radeon_emit(cs, 0);
887 } else {
888 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
889 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
890 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
891 }
892 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
893 if (a->dyn_gpr_enabled) {
894 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
895 S_028838_PS_GPRS(0x1e) |
896 S_028838_VS_GPRS(0x1e) |
897 S_028838_GS_GPRS(0x1e) |
898 S_028838_ES_GPRS(0x1e) |
899 S_028838_HS_GPRS(0x1e) |
900 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
901 }
902 }
903
904 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
905 {
906 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
907 struct pipe_clip_state *state = &rctx->clip_state.state;
908
909 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
910 radeon_emit_array(cs, (unsigned*)state, 6*4);
911 }
912
913 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
914 const struct pipe_poly_stipple *state)
915 {
916 }
917
918 static void evergreen_get_scissor_rect(struct r600_context *rctx,
919 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
920 uint32_t *tl, uint32_t *br)
921 {
922 /* EG hw workaround */
923 if (br_x == 0)
924 tl_x = 1;
925 if (br_y == 0)
926 tl_y = 1;
927
928 /* cayman hw workaround */
929 if (rctx->b.chip_class == CAYMAN) {
930 if (br_x == 1 && br_y == 1)
931 br_x = 2;
932 }
933
934 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
935 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
936 }
937
938 static void evergreen_set_scissor_states(struct pipe_context *ctx,
939 unsigned start_slot,
940 unsigned num_scissors,
941 const struct pipe_scissor_state *state)
942 {
943 struct r600_context *rctx = (struct r600_context *)ctx;
944 struct r600_scissor_state *rstate = &rctx->scissor;
945 int i;
946
947 for (i = start_slot; i < start_slot + num_scissors; i++)
948 rstate->scissor[i] = state[i - start_slot];
949 rstate->dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
950 rstate->atom.num_dw = util_bitcount(rstate->dirty_mask) * 4;
951 r600_mark_atom_dirty(rctx, &rstate->atom);
952 }
953
954 static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
955 {
956 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
957 struct r600_scissor_state *rstate = &rctx->scissor;
958 struct pipe_scissor_state *state;
959 uint32_t dirty_mask;
960 unsigned i, offset;
961 uint32_t tl, br;
962
963 dirty_mask = rstate->dirty_mask;
964 while (dirty_mask != 0) {
965 i = u_bit_scan(&dirty_mask);
966 state = &rstate->scissor[i];
967 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
968
969 offset = i * 4 * 2;
970 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
971 radeon_emit(cs, tl);
972 radeon_emit(cs, br);
973 }
974 rstate->dirty_mask = 0;
975 rstate->atom.num_dw = 0;
976 }
977
978 /**
979 * This function intializes the CB* register values for RATs. It is meant
980 * to be used for 1D aligned buffers that do not have an associated
981 * radeon_surf.
982 */
983 void evergreen_init_color_surface_rat(struct r600_context *rctx,
984 struct r600_surface *surf)
985 {
986 struct pipe_resource *pipe_buffer = surf->base.texture;
987 unsigned format = r600_translate_colorformat(rctx->b.chip_class,
988 surf->base.format);
989 unsigned endian = r600_colorformat_endian_swap(format);
990 unsigned swap = r600_translate_colorswap(surf->base.format);
991 unsigned block_size =
992 align(util_format_get_blocksize(pipe_buffer->format), 4);
993 unsigned pitch_alignment =
994 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
995 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
996
997 surf->cb_color_base = r600_resource(pipe_buffer)->gpu_address >> 8;
998
999 surf->cb_color_pitch = (pitch / 8) - 1;
1000
1001 surf->cb_color_slice = 0;
1002
1003 surf->cb_color_view = 0;
1004
1005 surf->cb_color_info =
1006 S_028C70_ENDIAN(endian)
1007 | S_028C70_FORMAT(format)
1008 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
1009 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
1010 | S_028C70_COMP_SWAP(swap)
1011 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
1012 * are using NUMBER_UINT */
1013 | S_028C70_RAT(1)
1014 ;
1015
1016 surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1017
1018 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
1019 * elements. */
1020 surf->cb_color_dim = pipe_buffer->width0;
1021
1022 /* Set the buffer range the GPU will have access to: */
1023 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
1024 0, pipe_buffer->width0);
1025
1026 surf->cb_color_fmask = surf->cb_color_base;
1027 surf->cb_color_fmask_slice = 0;
1028 }
1029
1030 void evergreen_init_color_surface(struct r600_context *rctx,
1031 struct r600_surface *surf)
1032 {
1033 struct r600_screen *rscreen = rctx->screen;
1034 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1035 unsigned level = surf->base.u.tex.level;
1036 unsigned pitch, slice;
1037 unsigned color_info, color_attrib, color_dim = 0, color_view;
1038 unsigned format, swap, ntype, endian;
1039 uint64_t offset, base_offset;
1040 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1041 const struct util_format_description *desc;
1042 int i;
1043 bool blend_clamp = 0, blend_bypass = 0;
1044
1045 offset = rtex->surface.level[level].offset;
1046 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1047 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1048 offset += rtex->surface.level[level].slice_size *
1049 surf->base.u.tex.first_layer;
1050 color_view = 0;
1051 } else
1052 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1053 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1054
1055 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1056 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1057 if (slice) {
1058 slice = slice - 1;
1059 }
1060 color_info = 0;
1061 switch (rtex->surface.level[level].mode) {
1062 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1063 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1064 non_disp_tiling = 1;
1065 break;
1066 case RADEON_SURF_MODE_1D:
1067 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1068 non_disp_tiling = rtex->non_disp_tiling;
1069 break;
1070 case RADEON_SURF_MODE_2D:
1071 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1072 non_disp_tiling = rtex->non_disp_tiling;
1073 break;
1074 case RADEON_SURF_MODE_LINEAR:
1075 default:
1076 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1077 non_disp_tiling = 1;
1078 break;
1079 }
1080 tile_split = rtex->surface.tile_split;
1081 macro_aspect = rtex->surface.mtilea;
1082 bankw = rtex->surface.bankw;
1083 bankh = rtex->surface.bankh;
1084 if (rtex->fmask.size)
1085 fmask_bankh = rtex->fmask.bank_height;
1086 else
1087 fmask_bankh = rtex->surface.bankh;
1088 tile_split = eg_tile_split(tile_split);
1089 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1090 bankw = eg_bank_wh(bankw);
1091 bankh = eg_bank_wh(bankh);
1092 fmask_bankh = eg_bank_wh(fmask_bankh);
1093
1094 /* 128 bit formats require tile type = 1 */
1095 if (rscreen->b.chip_class == CAYMAN) {
1096 if (util_format_get_blocksize(surf->base.format) >= 16)
1097 non_disp_tiling = 1;
1098 }
1099 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1100 desc = util_format_description(surf->base.format);
1101 for (i = 0; i < 4; i++) {
1102 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1103 break;
1104 }
1105 }
1106
1107 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1108 S_028C74_NUM_BANKS(nbanks) |
1109 S_028C74_BANK_WIDTH(bankw) |
1110 S_028C74_BANK_HEIGHT(bankh) |
1111 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1112 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1113 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1114
1115 if (rctx->b.chip_class == CAYMAN) {
1116 color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1117 UTIL_FORMAT_SWIZZLE_1);
1118
1119 if (rtex->resource.b.b.nr_samples > 1) {
1120 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1121 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1122 S_028C74_NUM_FRAGMENTS(log_samples);
1123 }
1124 }
1125
1126 ntype = V_028C70_NUMBER_UNORM;
1127 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1128 ntype = V_028C70_NUMBER_SRGB;
1129 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1130 if (desc->channel[i].normalized)
1131 ntype = V_028C70_NUMBER_SNORM;
1132 else if (desc->channel[i].pure_integer)
1133 ntype = V_028C70_NUMBER_SINT;
1134 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1135 if (desc->channel[i].normalized)
1136 ntype = V_028C70_NUMBER_UNORM;
1137 else if (desc->channel[i].pure_integer)
1138 ntype = V_028C70_NUMBER_UINT;
1139 }
1140
1141 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
1142 assert(format != ~0);
1143
1144 swap = r600_translate_colorswap(surf->base.format);
1145 assert(swap != ~0);
1146
1147 endian = r600_colorformat_endian_swap(format);
1148
1149 /* blend clamp should be set for all NORM/SRGB types */
1150 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1151 ntype == V_028C70_NUMBER_SRGB)
1152 blend_clamp = 1;
1153
1154 /* set blend bypass according to docs if SINT/UINT or
1155 8/24 COLOR variants */
1156 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1157 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1158 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1159 blend_clamp = 0;
1160 blend_bypass = 1;
1161 }
1162
1163 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1164
1165 color_info |= S_028C70_FORMAT(format) |
1166 S_028C70_COMP_SWAP(swap) |
1167 S_028C70_BLEND_CLAMP(blend_clamp) |
1168 S_028C70_BLEND_BYPASS(blend_bypass) |
1169 S_028C70_NUMBER_TYPE(ntype) |
1170 S_028C70_ENDIAN(endian);
1171
1172 /* EXPORT_NORM is an optimzation that can be enabled for better
1173 * performance in certain cases.
1174 * EXPORT_NORM can be enabled if:
1175 * - 11-bit or smaller UNORM/SNORM/SRGB
1176 * - 16-bit or smaller FLOAT
1177 */
1178 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1179 ((desc->channel[i].size < 12 &&
1180 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1181 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1182 (desc->channel[i].size < 17 &&
1183 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1184 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1185 surf->export_16bpc = true;
1186 }
1187
1188 if (rtex->fmask.size) {
1189 color_info |= S_028C70_COMPRESSION(1);
1190 }
1191
1192 base_offset = rtex->resource.gpu_address;
1193
1194 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1195 surf->cb_color_base = (base_offset + offset) >> 8;
1196 surf->cb_color_dim = color_dim;
1197 surf->cb_color_info = color_info;
1198 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1199 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1200 surf->cb_color_view = color_view;
1201 surf->cb_color_attrib = color_attrib;
1202 if (rtex->fmask.size) {
1203 surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8;
1204 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1205 } else {
1206 surf->cb_color_fmask = surf->cb_color_base;
1207 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1208 }
1209
1210 surf->color_initialized = true;
1211 }
1212
1213 static void evergreen_init_depth_surface(struct r600_context *rctx,
1214 struct r600_surface *surf)
1215 {
1216 struct r600_screen *rscreen = rctx->screen;
1217 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1218 unsigned level = surf->base.u.tex.level;
1219 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1220 uint64_t offset;
1221 unsigned format, array_mode;
1222 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1223
1224
1225 format = r600_translate_dbformat(surf->base.format);
1226 assert(format != ~0);
1227
1228 offset = rtex->resource.gpu_address;
1229 offset += rtex->surface.level[level].offset;
1230
1231 switch (rtex->surface.level[level].mode) {
1232 case RADEON_SURF_MODE_2D:
1233 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1234 break;
1235 case RADEON_SURF_MODE_1D:
1236 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1237 case RADEON_SURF_MODE_LINEAR:
1238 default:
1239 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1240 break;
1241 }
1242 tile_split = rtex->surface.tile_split;
1243 macro_aspect = rtex->surface.mtilea;
1244 bankw = rtex->surface.bankw;
1245 bankh = rtex->surface.bankh;
1246 tile_split = eg_tile_split(tile_split);
1247 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1248 bankw = eg_bank_wh(bankw);
1249 bankh = eg_bank_wh(bankh);
1250 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1251 offset >>= 8;
1252
1253 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1254 S_028040_FORMAT(format) |
1255 S_028040_TILE_SPLIT(tile_split)|
1256 S_028040_NUM_BANKS(nbanks) |
1257 S_028040_BANK_WIDTH(bankw) |
1258 S_028040_BANK_HEIGHT(bankh) |
1259 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1260 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1261 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1262 }
1263
1264 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1265
1266 surf->db_depth_base = offset;
1267 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1268 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1269 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1270 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1271 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1272 levelinfo->nblk_y / 64 - 1);
1273
1274 switch (surf->base.format) {
1275 case PIPE_FORMAT_Z24X8_UNORM:
1276 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1277 case PIPE_FORMAT_X8Z24_UNORM:
1278 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1279 surf->pa_su_poly_offset_db_fmt_cntl =
1280 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1281 break;
1282 case PIPE_FORMAT_Z32_FLOAT:
1283 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1284 surf->pa_su_poly_offset_db_fmt_cntl =
1285 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1286 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1287 break;
1288 case PIPE_FORMAT_Z16_UNORM:
1289 surf->pa_su_poly_offset_db_fmt_cntl =
1290 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1291 break;
1292 default:;
1293 }
1294
1295 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1296 uint64_t stencil_offset;
1297 unsigned stile_split = rtex->surface.stencil_tile_split;
1298
1299 stile_split = eg_tile_split(stile_split);
1300
1301 stencil_offset = rtex->surface.stencil_level[level].offset;
1302 stencil_offset += rtex->resource.gpu_address;
1303
1304 surf->db_stencil_base = stencil_offset >> 8;
1305 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1306 S_028044_TILE_SPLIT(stile_split);
1307 } else {
1308 surf->db_stencil_base = offset;
1309 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1310 * Older kernels are out of luck. */
1311 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1312 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1313 S_028044_FORMAT(V_028044_STENCIL_8);
1314 }
1315
1316 /* use htile only for first level */
1317 if (rtex->htile_buffer && !level) {
1318 uint64_t va = rtex->htile_buffer->gpu_address;
1319 surf->db_htile_data_base = va >> 8;
1320 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1321 S_028ABC_HTILE_HEIGHT(1) |
1322 S_028ABC_FULL_CACHE(1);
1323 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1324 surf->db_preload_control = 0;
1325 }
1326
1327 surf->depth_initialized = true;
1328 }
1329
1330 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1331 const struct pipe_framebuffer_state *state)
1332 {
1333 struct r600_context *rctx = (struct r600_context *)ctx;
1334 struct r600_surface *surf;
1335 struct r600_texture *rtex;
1336 uint32_t i, log_samples;
1337
1338 if (rctx->framebuffer.state.nr_cbufs) {
1339 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1340 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1341 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1342 }
1343 if (rctx->framebuffer.state.zsbuf) {
1344 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1345 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1346
1347 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1348 if (rtex->htile_buffer) {
1349 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1350 }
1351 }
1352
1353 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1354
1355 /* Colorbuffers. */
1356 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1357 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1358 util_format_is_pure_integer(state->cbufs[0]->format);
1359 rctx->framebuffer.compressed_cb_mask = 0;
1360 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1361
1362 for (i = 0; i < state->nr_cbufs; i++) {
1363 surf = (struct r600_surface*)state->cbufs[i];
1364 if (!surf)
1365 continue;
1366
1367 rtex = (struct r600_texture*)surf->base.texture;
1368
1369 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1370
1371 if (!surf->color_initialized) {
1372 evergreen_init_color_surface(rctx, surf);
1373 }
1374
1375 if (!surf->export_16bpc) {
1376 rctx->framebuffer.export_16bpc = false;
1377 }
1378
1379 if (rtex->fmask.size && rtex->cmask.size) {
1380 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1381 }
1382 }
1383
1384 /* Update alpha-test state dependencies.
1385 * Alpha-test is done on the first colorbuffer only. */
1386 if (state->nr_cbufs) {
1387 bool alphatest_bypass = false;
1388 bool export_16bpc = true;
1389
1390 surf = (struct r600_surface*)state->cbufs[0];
1391 if (surf) {
1392 alphatest_bypass = surf->alphatest_bypass;
1393 export_16bpc = surf->export_16bpc;
1394 }
1395
1396 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1397 rctx->alphatest_state.bypass = alphatest_bypass;
1398 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1399 }
1400 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1401 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1402 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1403 }
1404 }
1405
1406 /* ZS buffer. */
1407 if (state->zsbuf) {
1408 surf = (struct r600_surface*)state->zsbuf;
1409
1410 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1411
1412 if (!surf->depth_initialized) {
1413 evergreen_init_depth_surface(rctx, surf);
1414 }
1415
1416 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1417 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1418 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1419 }
1420
1421 if (rctx->db_state.rsurf != surf) {
1422 rctx->db_state.rsurf = surf;
1423 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1424 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1425 }
1426 } else if (rctx->db_state.rsurf) {
1427 rctx->db_state.rsurf = NULL;
1428 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1429 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1430 }
1431
1432 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1433 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1434 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1435 }
1436
1437 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1438 rctx->alphatest_state.bypass = false;
1439 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1440 }
1441
1442 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1443 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1444 if ((rctx->b.chip_class == CAYMAN ||
1445 rctx->b.family == CHIP_RV770) &&
1446 rctx->db_misc_state.log_samples != log_samples) {
1447 rctx->db_misc_state.log_samples = log_samples;
1448 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1449 }
1450
1451
1452 /* Calculate the CS size. */
1453 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1454
1455 /* MSAA. */
1456 if (rctx->b.chip_class == EVERGREEN)
1457 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1458 else
1459 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1460
1461 /* Colorbuffers. */
1462 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1463 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1464 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1465
1466 /* ZS buffer. */
1467 if (state->zsbuf) {
1468 rctx->framebuffer.atom.num_dw += 24;
1469 rctx->framebuffer.atom.num_dw += 2;
1470 } else if (rctx->screen->b.info.drm_minor >= 18) {
1471 rctx->framebuffer.atom.num_dw += 4;
1472 }
1473
1474 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1475
1476 r600_set_sample_locations_constant_buffer(rctx);
1477 }
1478
1479 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1480 {
1481 struct r600_context *rctx = (struct r600_context *)ctx;
1482
1483 if (rctx->ps_iter_samples == min_samples)
1484 return;
1485
1486 rctx->ps_iter_samples = min_samples;
1487 if (rctx->framebuffer.nr_samples > 1) {
1488 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1489 }
1490 }
1491
1492 /* 8xMSAA */
1493 static uint32_t sample_locs_8x[] = {
1494 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1495 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1496 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1497 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1498 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1499 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1500 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1501 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1502 };
1503 static unsigned max_dist_8x = 7;
1504
1505 static void evergreen_get_sample_position(struct pipe_context *ctx,
1506 unsigned sample_count,
1507 unsigned sample_index,
1508 float *out_value)
1509 {
1510 int offset, index;
1511 struct {
1512 int idx:4;
1513 } val;
1514 switch (sample_count) {
1515 case 1:
1516 default:
1517 out_value[0] = out_value[1] = 0.5;
1518 break;
1519 case 2:
1520 offset = 4 * (sample_index * 2);
1521 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1522 out_value[0] = (float)(val.idx + 8) / 16.0f;
1523 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1524 out_value[1] = (float)(val.idx + 8) / 16.0f;
1525 break;
1526 case 4:
1527 offset = 4 * (sample_index * 2);
1528 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1529 out_value[0] = (float)(val.idx + 8) / 16.0f;
1530 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1531 out_value[1] = (float)(val.idx + 8) / 16.0f;
1532 break;
1533 case 8:
1534 offset = 4 * (sample_index % 4 * 2);
1535 index = (sample_index / 4);
1536 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1537 out_value[0] = (float)(val.idx + 8) / 16.0f;
1538 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1539 out_value[1] = (float)(val.idx + 8) / 16.0f;
1540 break;
1541 }
1542 }
1543
1544 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1545 {
1546
1547 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1548 unsigned max_dist = 0;
1549
1550 switch (nr_samples) {
1551 default:
1552 nr_samples = 0;
1553 break;
1554 case 2:
1555 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_2x));
1556 radeon_emit_array(cs, eg_sample_locs_2x, Elements(eg_sample_locs_2x));
1557 max_dist = eg_max_dist_2x;
1558 break;
1559 case 4:
1560 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_4x));
1561 radeon_emit_array(cs, eg_sample_locs_4x, Elements(eg_sample_locs_4x));
1562 max_dist = eg_max_dist_4x;
1563 break;
1564 case 8:
1565 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1566 radeon_emit_array(cs, sample_locs_8x, Elements(sample_locs_8x));
1567 max_dist = max_dist_8x;
1568 break;
1569 }
1570
1571 if (nr_samples > 1) {
1572 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1573 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1574 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1575 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1576 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1577 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1578 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1579 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1580 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1581 } else {
1582 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1583 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1584 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1585 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1586 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1587 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1588 }
1589 }
1590
1591 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1592 {
1593 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1594 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1595 unsigned nr_cbufs = state->nr_cbufs;
1596 unsigned i, tl, br;
1597 struct r600_texture *tex = NULL;
1598 struct r600_surface *cb = NULL;
1599
1600 /* XXX support more colorbuffers once we need them */
1601 assert(nr_cbufs <= 8);
1602 if (nr_cbufs > 8)
1603 nr_cbufs = 8;
1604
1605 /* Colorbuffers. */
1606 for (i = 0; i < nr_cbufs; i++) {
1607 unsigned reloc, cmask_reloc;
1608
1609 cb = (struct r600_surface*)state->cbufs[i];
1610 if (!cb) {
1611 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1612 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1613 continue;
1614 }
1615
1616 tex = (struct r600_texture *)cb->base.texture;
1617 reloc = radeon_add_to_buffer_list(&rctx->b,
1618 &rctx->b.gfx,
1619 (struct r600_resource*)cb->base.texture,
1620 RADEON_USAGE_READWRITE,
1621 tex->surface.nsamples > 1 ?
1622 RADEON_PRIO_COLOR_BUFFER_MSAA :
1623 RADEON_PRIO_COLOR_BUFFER);
1624
1625 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1626 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1627 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1628 RADEON_PRIO_CMASK);
1629 } else {
1630 cmask_reloc = reloc;
1631 }
1632
1633 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1634 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1635 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1636 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1637 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1638 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1639 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1640 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1641 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1642 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1643 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1644 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1645 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1646 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1647
1648 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1649 radeon_emit(cs, reloc);
1650
1651 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1652 radeon_emit(cs, reloc);
1653
1654 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1655 radeon_emit(cs, cmask_reloc);
1656
1657 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1658 radeon_emit(cs, reloc);
1659 }
1660 /* set CB_COLOR1_INFO for possible dual-src blending */
1661 if (i == 1 && state->cbufs[0]) {
1662 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1663 cb->cb_color_info | tex->cb_color_info);
1664 i++;
1665 }
1666 for (; i < 8 ; i++)
1667 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1668 for (; i < 12; i++)
1669 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1670
1671 /* ZS buffer. */
1672 if (state->zsbuf) {
1673 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1674 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1675 &rctx->b.gfx,
1676 (struct r600_resource*)state->zsbuf->texture,
1677 RADEON_USAGE_READWRITE,
1678 zb->base.texture->nr_samples > 1 ?
1679 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1680 RADEON_PRIO_DEPTH_BUFFER);
1681
1682 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1683 zb->pa_su_poly_offset_db_fmt_cntl);
1684 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1685
1686 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1687 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1688 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1689 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1690 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1691 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1692 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1693 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1694 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1695
1696 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1697 radeon_emit(cs, reloc);
1698
1699 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1700 radeon_emit(cs, reloc);
1701
1702 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1703 radeon_emit(cs, reloc);
1704
1705 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1706 radeon_emit(cs, reloc);
1707 } else if (rctx->screen->b.info.drm_minor >= 18) {
1708 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1709 * Older kernels are out of luck. */
1710 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1711 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1712 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1713 }
1714
1715 /* Framebuffer dimensions. */
1716 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1717
1718 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1719 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1720 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1721
1722 if (rctx->b.chip_class == EVERGREEN) {
1723 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1724 } else {
1725 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1726 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples, rctx->ps_iter_samples, 0);
1727 }
1728 }
1729
1730 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1731 {
1732 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1733 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1734 float offset_units = state->offset_units;
1735 float offset_scale = state->offset_scale;
1736
1737 switch (state->zs_format) {
1738 case PIPE_FORMAT_Z24X8_UNORM:
1739 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1740 case PIPE_FORMAT_X8Z24_UNORM:
1741 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1742 offset_units *= 2.0f;
1743 break;
1744 case PIPE_FORMAT_Z16_UNORM:
1745 offset_units *= 4.0f;
1746 break;
1747 default:;
1748 }
1749
1750 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1751 radeon_emit(cs, fui(offset_scale));
1752 radeon_emit(cs, fui(offset_units));
1753 radeon_emit(cs, fui(offset_scale));
1754 radeon_emit(cs, fui(offset_units));
1755 }
1756
1757 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1758 {
1759 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1760 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1761 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1762 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1763
1764 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1765 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1766 /* This must match the used export instructions exactly.
1767 * Other values may lead to undefined behavior and hangs.
1768 */
1769 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
1770 }
1771
1772 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1773 {
1774 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1775 struct r600_db_state *a = (struct r600_db_state*)atom;
1776
1777 if (a->rsurf && a->rsurf->db_htile_surface) {
1778 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1779 unsigned reloc_idx;
1780
1781 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1782 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1783 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
1784 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1785 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1786 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1787 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1788 cs->buf[cs->cdw++] = reloc_idx;
1789 } else {
1790 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
1791 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
1792 }
1793 }
1794
1795 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1796 {
1797 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1798 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1799 unsigned db_render_control = 0;
1800 unsigned db_count_control = 0;
1801 unsigned db_render_override =
1802 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1803 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1804
1805 if (rctx->b.num_occlusion_queries > 0) {
1806 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1807 if (rctx->b.chip_class == CAYMAN) {
1808 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1809 }
1810 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1811 }
1812
1813 /* This is to fix a lockup when hyperz and alpha test are enabled at
1814 * the same time somehow GPU get confuse on which order to pick for
1815 * z test
1816 */
1817 if (rctx->alphatest_state.sx_alpha_test_control)
1818 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
1819
1820 if (a->flush_depthstencil_through_cb) {
1821 assert(a->copy_depth || a->copy_stencil);
1822
1823 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1824 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1825 S_028000_COPY_CENTROID(1) |
1826 S_028000_COPY_SAMPLE(a->copy_sample);
1827 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1828 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1829 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1830 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1831 }
1832 if (a->htile_clear) {
1833 /* FIXME we might want to disable cliprect here */
1834 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
1835 }
1836
1837 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1838 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1839 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1840 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1841 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1842 }
1843
1844 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1845 struct r600_vertexbuf_state *state,
1846 unsigned resource_offset,
1847 unsigned pkt_flags)
1848 {
1849 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1850 uint32_t dirty_mask = state->dirty_mask;
1851
1852 while (dirty_mask) {
1853 struct pipe_vertex_buffer *vb;
1854 struct r600_resource *rbuffer;
1855 uint64_t va;
1856 unsigned buffer_index = u_bit_scan(&dirty_mask);
1857
1858 vb = &state->vb[buffer_index];
1859 rbuffer = (struct r600_resource*)vb->buffer;
1860 assert(rbuffer);
1861
1862 va = rbuffer->gpu_address + vb->buffer_offset;
1863
1864 /* fetch resources start at index 992 */
1865 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1866 radeon_emit(cs, (resource_offset + buffer_index) * 8);
1867 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1868 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1869 radeon_emit(cs, /* RESOURCEi_WORD2 */
1870 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1871 S_030008_STRIDE(vb->stride) |
1872 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1873 radeon_emit(cs, /* RESOURCEi_WORD3 */
1874 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1875 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1876 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1877 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1878 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1879 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1880 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1881 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1882
1883 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1884 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1885 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1886 }
1887 state->dirty_mask = 0;
1888 }
1889
1890 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1891 {
1892 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
1893 }
1894
1895 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1896 {
1897 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
1898 RADEON_CP_PACKET3_COMPUTE_MODE);
1899 }
1900
1901 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1902 struct r600_constbuf_state *state,
1903 unsigned buffer_id_base,
1904 unsigned reg_alu_constbuf_size,
1905 unsigned reg_alu_const_cache,
1906 unsigned pkt_flags)
1907 {
1908 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1909 uint32_t dirty_mask = state->dirty_mask;
1910
1911 while (dirty_mask) {
1912 struct pipe_constant_buffer *cb;
1913 struct r600_resource *rbuffer;
1914 uint64_t va;
1915 unsigned buffer_index = ffs(dirty_mask) - 1;
1916 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1917
1918 cb = &state->cb[buffer_index];
1919 rbuffer = (struct r600_resource*)cb->buffer;
1920 assert(rbuffer);
1921
1922 va = rbuffer->gpu_address + cb->buffer_offset;
1923
1924 if (!gs_ring_buffer) {
1925 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
1926 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
1927 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
1928 pkt_flags);
1929 }
1930
1931 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1932 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1933 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1934
1935 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1936 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
1937 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1938 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1939 radeon_emit(cs, /* RESOURCEi_WORD2 */
1940 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1941 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
1942 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
1943 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
1944 radeon_emit(cs, /* RESOURCEi_WORD3 */
1945 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
1946 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1947 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1948 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1949 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1950 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1951 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1952 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1953 radeon_emit(cs, /* RESOURCEi_WORD7 */
1954 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
1955
1956 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1957 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1958 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1959
1960 dirty_mask &= ~(1 << buffer_index);
1961 }
1962 state->dirty_mask = 0;
1963 }
1964
1965 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
1966 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1967 {
1968 if (rctx->vs_shader->current->shader.vs_as_ls) {
1969 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1970 EG_FETCH_CONSTANTS_OFFSET_LS,
1971 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
1972 R_028F40_ALU_CONST_CACHE_LS_0,
1973 0 /* PKT3 flags */);
1974 } else {
1975 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1976 EG_FETCH_CONSTANTS_OFFSET_VS,
1977 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1978 R_028980_ALU_CONST_CACHE_VS_0,
1979 0 /* PKT3 flags */);
1980 }
1981 }
1982
1983 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1984 {
1985 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1986 EG_FETCH_CONSTANTS_OFFSET_GS,
1987 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1988 R_0289C0_ALU_CONST_CACHE_GS_0,
1989 0 /* PKT3 flags */);
1990 }
1991
1992 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1993 {
1994 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1995 EG_FETCH_CONSTANTS_OFFSET_PS,
1996 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1997 R_028940_ALU_CONST_CACHE_PS_0,
1998 0 /* PKT3 flags */);
1999 }
2000
2001 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2002 {
2003 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
2004 EG_FETCH_CONSTANTS_OFFSET_CS,
2005 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2006 R_028F40_ALU_CONST_CACHE_LS_0,
2007 RADEON_CP_PACKET3_COMPUTE_MODE);
2008 }
2009
2010 /* tes constants can be emitted to VS or ES - which are common */
2011 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2012 {
2013 if (!rctx->tes_shader)
2014 return;
2015 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2016 EG_FETCH_CONSTANTS_OFFSET_VS,
2017 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2018 R_028980_ALU_CONST_CACHE_VS_0,
2019 0);
2020 }
2021
2022 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2023 {
2024 if (!rctx->tes_shader)
2025 return;
2026 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2027 EG_FETCH_CONSTANTS_OFFSET_HS,
2028 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
2029 R_028F00_ALU_CONST_CACHE_HS_0,
2030 0);
2031 }
2032
2033 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2034 struct r600_samplerview_state *state,
2035 unsigned resource_id_base, unsigned pkt_flags)
2036 {
2037 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2038 uint32_t dirty_mask = state->dirty_mask;
2039
2040 while (dirty_mask) {
2041 struct r600_pipe_sampler_view *rview;
2042 unsigned resource_index = u_bit_scan(&dirty_mask);
2043 unsigned reloc;
2044
2045 rview = state->views[resource_index];
2046 assert(rview);
2047
2048 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2049 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2050 radeon_emit_array(cs, rview->tex_resource_words, 8);
2051
2052 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2053 RADEON_USAGE_READ,
2054 r600_get_sampler_view_priority(rview->tex_resource));
2055 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2056 radeon_emit(cs, reloc);
2057
2058 if (!rview->skip_mip_address_reloc) {
2059 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2060 radeon_emit(cs, reloc);
2061 }
2062 }
2063 state->dirty_mask = 0;
2064 }
2065
2066 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2067 {
2068 if (rctx->vs_shader->current->shader.vs_as_ls) {
2069 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2070 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2071 } else {
2072 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2073 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2074 }
2075 }
2076
2077 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2078 {
2079 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2080 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2081 }
2082
2083 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2084 {
2085 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2086 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2087 }
2088
2089 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2090 {
2091 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2092 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2093 }
2094
2095 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2096 {
2097 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2098 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2099 }
2100
2101 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2102 {
2103 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2104 EG_FETCH_CONSTANTS_OFFSET_CS + 2, RADEON_CP_PACKET3_COMPUTE_MODE);
2105 }
2106
2107 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2108 struct r600_textures_info *texinfo,
2109 unsigned resource_id_base,
2110 unsigned border_index_reg,
2111 unsigned pkt_flags)
2112 {
2113 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2114 uint32_t dirty_mask = texinfo->states.dirty_mask;
2115
2116 while (dirty_mask) {
2117 struct r600_pipe_sampler_state *rstate;
2118 unsigned i = u_bit_scan(&dirty_mask);
2119
2120 rstate = texinfo->states.states[i];
2121 assert(rstate);
2122
2123 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2124 radeon_emit(cs, (resource_id_base + i) * 3);
2125 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2126
2127 if (rstate->border_color_use) {
2128 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2129 radeon_emit(cs, i);
2130 radeon_emit_array(cs, rstate->border_color.ui, 4);
2131 }
2132 }
2133 texinfo->states.dirty_mask = 0;
2134 }
2135
2136 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2137 {
2138 if (rctx->vs_shader->current->shader.vs_as_ls) {
2139 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2140 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2141 } else {
2142 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2143 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2144 }
2145 }
2146
2147 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2148 {
2149 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2150 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2151 }
2152
2153 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2154 {
2155 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2156 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2157 }
2158
2159 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2160 {
2161 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2162 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2163 }
2164
2165 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2166 {
2167 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2168 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2169 }
2170
2171 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2172 {
2173 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2174 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2175 RADEON_CP_PACKET3_COMPUTE_MODE);
2176 }
2177
2178 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2179 {
2180 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2181 uint8_t mask = s->sample_mask;
2182
2183 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2184 mask | (mask << 8) | (mask << 16) | (mask << 24));
2185 }
2186
2187 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2188 {
2189 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2190 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2191 uint16_t mask = s->sample_mask;
2192
2193 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2194 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2195 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2196 }
2197
2198 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2199 {
2200 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2201 struct r600_cso_state *state = (struct r600_cso_state*)a;
2202 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2203
2204 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2205 (shader->buffer->gpu_address + shader->offset) >> 8);
2206 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2207 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2208 RADEON_USAGE_READ,
2209 RADEON_PRIO_INTERNAL_SHADER));
2210 }
2211
2212 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2213 {
2214 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2215 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2216
2217 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2218
2219 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2220 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2221 primid = 1;
2222 }
2223
2224 if (state->geom_enable) {
2225 uint32_t cut_val;
2226
2227 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2228 cut_val = V_028A40_GS_CUT_128;
2229 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2230 cut_val = V_028A40_GS_CUT_256;
2231 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2232 cut_val = V_028A40_GS_CUT_512;
2233 else
2234 cut_val = V_028A40_GS_CUT_1024;
2235
2236 v = S_028B54_GS_EN(1) |
2237 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2238 if (!rctx->tes_shader)
2239 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2240
2241 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2242 S_028A40_CUT_MODE(cut_val);
2243
2244 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2245 primid = 1;
2246 }
2247
2248 if (rctx->tes_shader) {
2249 uint32_t type, partitioning, topology;
2250 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2251 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2252 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2253 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2254 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2255 switch (tes_prim_mode) {
2256 case PIPE_PRIM_LINES:
2257 type = V_028B6C_TESS_ISOLINE;
2258 break;
2259 case PIPE_PRIM_TRIANGLES:
2260 type = V_028B6C_TESS_TRIANGLE;
2261 break;
2262 case PIPE_PRIM_QUADS:
2263 type = V_028B6C_TESS_QUAD;
2264 break;
2265 default:
2266 assert(0);
2267 return;
2268 }
2269
2270 switch (tes_spacing) {
2271 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2272 partitioning = V_028B6C_PART_FRAC_ODD;
2273 break;
2274 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2275 partitioning = V_028B6C_PART_FRAC_EVEN;
2276 break;
2277 case PIPE_TESS_SPACING_EQUAL:
2278 partitioning = V_028B6C_PART_INTEGER;
2279 break;
2280 default:
2281 assert(0);
2282 return;
2283 }
2284
2285 if (tes_point_mode)
2286 topology = V_028B6C_OUTPUT_POINT;
2287 else if (tes_prim_mode == PIPE_PRIM_LINES)
2288 topology = V_028B6C_OUTPUT_LINE;
2289 else if (tes_vertex_order_cw)
2290 /* XXX follow radeonsi and invert */
2291 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2292 else
2293 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2294
2295 tf_param = S_028B6C_TYPE(type) |
2296 S_028B6C_PARTITIONING(partitioning) |
2297 S_028B6C_TOPOLOGY(topology);
2298 }
2299
2300 if (rctx->tes_shader) {
2301 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2302 S_028B54_HS_EN(1);
2303 if (!state->geom_enable)
2304 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2305 else
2306 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2307 }
2308
2309 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2310 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2311 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2312 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2313 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2314 }
2315
2316 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2317 {
2318 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2319 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2320 struct r600_resource *rbuffer;
2321
2322 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2323 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2324 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2325
2326 if (state->enable) {
2327 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2328 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2329 rbuffer->gpu_address >> 8);
2330 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2331 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2332 RADEON_USAGE_READWRITE,
2333 RADEON_PRIO_RINGS_STREAMOUT));
2334 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2335 state->esgs_ring.buffer_size >> 8);
2336
2337 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2338 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2339 rbuffer->gpu_address >> 8);
2340 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2341 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2342 RADEON_USAGE_READWRITE,
2343 RADEON_PRIO_RINGS_STREAMOUT));
2344 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2345 state->gsvs_ring.buffer_size >> 8);
2346 } else {
2347 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2348 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2349 }
2350
2351 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2352 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2353 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2354 }
2355
2356 void cayman_init_common_regs(struct r600_command_buffer *cb,
2357 enum chip_class ctx_chip_class,
2358 enum radeon_family ctx_family,
2359 int ctx_drm_minor)
2360 {
2361 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2362 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2363 /* always set the temp clauses */
2364 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2365
2366 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2367 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2368 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2369
2370 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2371
2372 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2373 r600_store_value(cb, 0);
2374 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2375
2376 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2377 }
2378
2379 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2380 {
2381 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2382 int tmp, i;
2383
2384 r600_init_command_buffer(cb, 338);
2385
2386 /* This must be first. */
2387 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2388 r600_store_value(cb, 0x80000000);
2389 r600_store_value(cb, 0x80000000);
2390
2391 /* We're setting config registers here. */
2392 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2393 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2394
2395 cayman_init_common_regs(cb, rctx->b.chip_class,
2396 rctx->b.family, rctx->screen->b.info.drm_minor);
2397
2398 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2399 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2400
2401 /* remove LS/HS from one SIMD for hw workaround */
2402 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2403 r600_store_value(cb, 0xffffffff);
2404 r600_store_value(cb, 0xffffffff);
2405 r600_store_value(cb, 0xfffffffe);
2406
2407 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2408 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2409 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2410 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2411 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2412 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2413 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2414
2415 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2416 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2417 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2418 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2419 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2420
2421 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2422 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2423 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2424 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2425 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2426 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2427 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2428 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2429 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2430 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2431 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2432 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2433 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2434 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2435
2436 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2437
2438 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2439
2440 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2441 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2442 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2443
2444 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2445 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2446 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2447
2448 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2449
2450 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2451 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2452 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2453
2454 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2455
2456 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2457
2458 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2459
2460 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2461 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2462 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2463 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2464
2465 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2466 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2467
2468 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2469 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2470 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2471 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2472 }
2473
2474 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2475 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2476
2477 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2478 r600_store_value(cb, fui(1.0)); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2479 r600_store_value(cb, fui(1.0)); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2480 r600_store_value(cb, fui(1.0)); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2481 r600_store_value(cb, fui(1.0)); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2482
2483 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2484 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2485 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2486
2487 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2488 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2489 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2490
2491 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2492 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2493 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2494 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2495 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2496 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2497
2498 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2499
2500 /* to avoid GPU doing any preloading of constant from random address */
2501 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2502 for (i = 0; i < 16; i++)
2503 r600_store_value(cb, 0);
2504
2505 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2506 for (i = 0; i < 16; i++)
2507 r600_store_value(cb, 0);
2508
2509 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2510 for (i = 0; i < 16; i++)
2511 r600_store_value(cb, 0);
2512
2513 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2514 for (i = 0; i < 16; i++)
2515 r600_store_value(cb, 0);
2516
2517 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2518 for (i = 0; i < 16; i++)
2519 r600_store_value(cb, 0);
2520
2521 if (rctx->screen->b.has_streamout) {
2522 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2523 }
2524
2525 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2526 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2527 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2528 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2529 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2530 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2531
2532 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2533 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2534 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2535 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2536 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2537 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2538 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2539 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2540 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2541 }
2542
2543 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2544 enum chip_class ctx_chip_class,
2545 enum radeon_family ctx_family,
2546 int ctx_drm_minor)
2547 {
2548 int ps_prio;
2549 int vs_prio;
2550 int gs_prio;
2551 int es_prio;
2552
2553 int hs_prio;
2554 int cs_prio;
2555 int ls_prio;
2556
2557 unsigned tmp;
2558
2559 ps_prio = 0;
2560 vs_prio = 1;
2561 gs_prio = 2;
2562 es_prio = 3;
2563 hs_prio = 3;
2564 ls_prio = 3;
2565 cs_prio = 0;
2566
2567 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2568 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2569 rctx->r6xx_num_clause_temp_gprs = 4;
2570 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2571 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2572 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2573 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2574
2575 tmp = 0;
2576 switch (ctx_family) {
2577 case CHIP_CEDAR:
2578 case CHIP_PALM:
2579 case CHIP_SUMO:
2580 case CHIP_SUMO2:
2581 case CHIP_CAICOS:
2582 break;
2583 default:
2584 tmp |= S_008C00_VC_ENABLE(1);
2585 break;
2586 }
2587 tmp |= S_008C00_EXPORT_SRC_C(1);
2588 tmp |= S_008C00_CS_PRIO(cs_prio);
2589 tmp |= S_008C00_LS_PRIO(ls_prio);
2590 tmp |= S_008C00_HS_PRIO(hs_prio);
2591 tmp |= S_008C00_PS_PRIO(ps_prio);
2592 tmp |= S_008C00_VS_PRIO(vs_prio);
2593 tmp |= S_008C00_GS_PRIO(gs_prio);
2594 tmp |= S_008C00_ES_PRIO(es_prio);
2595
2596 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2597 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2598
2599 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2600 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2601 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2602
2603 /* The cs checker requires this register to be set. */
2604 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2605
2606 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2607 r600_store_value(cb, 0);
2608 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2609
2610 return;
2611 }
2612
2613 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2614 {
2615 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2616 int num_ps_threads;
2617 int num_vs_threads;
2618 int num_gs_threads;
2619 int num_es_threads;
2620 int num_hs_threads;
2621 int num_ls_threads;
2622
2623 int num_ps_stack_entries;
2624 int num_vs_stack_entries;
2625 int num_gs_stack_entries;
2626 int num_es_stack_entries;
2627 int num_hs_stack_entries;
2628 int num_ls_stack_entries;
2629 enum radeon_family family;
2630 unsigned tmp, i;
2631
2632 if (rctx->b.chip_class == CAYMAN) {
2633 cayman_init_atom_start_cs(rctx);
2634 return;
2635 }
2636
2637 r600_init_command_buffer(cb, 338);
2638
2639 /* This must be first. */
2640 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2641 r600_store_value(cb, 0x80000000);
2642 r600_store_value(cb, 0x80000000);
2643
2644 /* We're setting config registers here. */
2645 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2646 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2647
2648 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2649 rctx->b.family, rctx->screen->b.info.drm_minor);
2650
2651 family = rctx->b.family;
2652 switch (family) {
2653 case CHIP_CEDAR:
2654 default:
2655 num_ps_threads = 96;
2656 num_vs_threads = 16;
2657 num_gs_threads = 16;
2658 num_es_threads = 16;
2659 num_hs_threads = 16;
2660 num_ls_threads = 16;
2661 num_ps_stack_entries = 42;
2662 num_vs_stack_entries = 42;
2663 num_gs_stack_entries = 42;
2664 num_es_stack_entries = 42;
2665 num_hs_stack_entries = 42;
2666 num_ls_stack_entries = 42;
2667 break;
2668 case CHIP_REDWOOD:
2669 num_ps_threads = 128;
2670 num_vs_threads = 20;
2671 num_gs_threads = 20;
2672 num_es_threads = 20;
2673 num_hs_threads = 20;
2674 num_ls_threads = 20;
2675 num_ps_stack_entries = 42;
2676 num_vs_stack_entries = 42;
2677 num_gs_stack_entries = 42;
2678 num_es_stack_entries = 42;
2679 num_hs_stack_entries = 42;
2680 num_ls_stack_entries = 42;
2681 break;
2682 case CHIP_JUNIPER:
2683 num_ps_threads = 128;
2684 num_vs_threads = 20;
2685 num_gs_threads = 20;
2686 num_es_threads = 20;
2687 num_hs_threads = 20;
2688 num_ls_threads = 20;
2689 num_ps_stack_entries = 85;
2690 num_vs_stack_entries = 85;
2691 num_gs_stack_entries = 85;
2692 num_es_stack_entries = 85;
2693 num_hs_stack_entries = 85;
2694 num_ls_stack_entries = 85;
2695 break;
2696 case CHIP_CYPRESS:
2697 case CHIP_HEMLOCK:
2698 num_ps_threads = 128;
2699 num_vs_threads = 20;
2700 num_gs_threads = 20;
2701 num_es_threads = 20;
2702 num_hs_threads = 20;
2703 num_ls_threads = 20;
2704 num_ps_stack_entries = 85;
2705 num_vs_stack_entries = 85;
2706 num_gs_stack_entries = 85;
2707 num_es_stack_entries = 85;
2708 num_hs_stack_entries = 85;
2709 num_ls_stack_entries = 85;
2710 break;
2711 case CHIP_PALM:
2712 num_ps_threads = 96;
2713 num_vs_threads = 16;
2714 num_gs_threads = 16;
2715 num_es_threads = 16;
2716 num_hs_threads = 16;
2717 num_ls_threads = 16;
2718 num_ps_stack_entries = 42;
2719 num_vs_stack_entries = 42;
2720 num_gs_stack_entries = 42;
2721 num_es_stack_entries = 42;
2722 num_hs_stack_entries = 42;
2723 num_ls_stack_entries = 42;
2724 break;
2725 case CHIP_SUMO:
2726 num_ps_threads = 96;
2727 num_vs_threads = 25;
2728 num_gs_threads = 25;
2729 num_es_threads = 25;
2730 num_hs_threads = 16;
2731 num_ls_threads = 16;
2732 num_ps_stack_entries = 42;
2733 num_vs_stack_entries = 42;
2734 num_gs_stack_entries = 42;
2735 num_es_stack_entries = 42;
2736 num_hs_stack_entries = 42;
2737 num_ls_stack_entries = 42;
2738 break;
2739 case CHIP_SUMO2:
2740 num_ps_threads = 96;
2741 num_vs_threads = 25;
2742 num_gs_threads = 25;
2743 num_es_threads = 25;
2744 num_hs_threads = 16;
2745 num_ls_threads = 16;
2746 num_ps_stack_entries = 85;
2747 num_vs_stack_entries = 85;
2748 num_gs_stack_entries = 85;
2749 num_es_stack_entries = 85;
2750 num_hs_stack_entries = 85;
2751 num_ls_stack_entries = 85;
2752 break;
2753 case CHIP_BARTS:
2754 num_ps_threads = 128;
2755 num_vs_threads = 20;
2756 num_gs_threads = 20;
2757 num_es_threads = 20;
2758 num_hs_threads = 20;
2759 num_ls_threads = 20;
2760 num_ps_stack_entries = 85;
2761 num_vs_stack_entries = 85;
2762 num_gs_stack_entries = 85;
2763 num_es_stack_entries = 85;
2764 num_hs_stack_entries = 85;
2765 num_ls_stack_entries = 85;
2766 break;
2767 case CHIP_TURKS:
2768 num_ps_threads = 128;
2769 num_vs_threads = 20;
2770 num_gs_threads = 20;
2771 num_es_threads = 20;
2772 num_hs_threads = 20;
2773 num_ls_threads = 20;
2774 num_ps_stack_entries = 42;
2775 num_vs_stack_entries = 42;
2776 num_gs_stack_entries = 42;
2777 num_es_stack_entries = 42;
2778 num_hs_stack_entries = 42;
2779 num_ls_stack_entries = 42;
2780 break;
2781 case CHIP_CAICOS:
2782 num_ps_threads = 96;
2783 num_vs_threads = 10;
2784 num_gs_threads = 10;
2785 num_es_threads = 10;
2786 num_hs_threads = 10;
2787 num_ls_threads = 10;
2788 num_ps_stack_entries = 42;
2789 num_vs_stack_entries = 42;
2790 num_gs_stack_entries = 42;
2791 num_es_stack_entries = 42;
2792 num_hs_stack_entries = 42;
2793 num_ls_stack_entries = 42;
2794 break;
2795 }
2796
2797 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2798 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2799 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2800 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2801
2802 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2803 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2804
2805 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2806 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2807 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2808
2809 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2810 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2811 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2812
2813 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2814 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2815 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2816
2817 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2818 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2819 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2820
2821 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2822 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2823
2824 /* remove LS/HS from one SIMD for hw workaround */
2825 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2826 r600_store_value(cb, 0xffffffff);
2827 r600_store_value(cb, 0xffffffff);
2828 r600_store_value(cb, 0xfffffffe);
2829
2830 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2831 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2832
2833 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2834 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2835 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2836 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2837 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2838 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2839 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2840
2841 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2842 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2843 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2844 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2845 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2846
2847 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2848 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2849 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2850 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2851 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2852 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2853 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2854 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2855 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2856 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2857 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2858 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2859 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2860 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2861
2862 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2863
2864 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2865
2866 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2867 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2868 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2869
2870 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2871
2872 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2873
2874 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2875 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2876 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2877
2878 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2879 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2880 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2881 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2882 }
2883
2884 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2885 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2886
2887 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2888 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2889 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2890 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2891
2892 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2893 r600_store_value(cb, fui(1.0)); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2894 r600_store_value(cb, fui(1.0)); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2895 r600_store_value(cb, fui(1.0)); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2896 r600_store_value(cb, fui(1.0)); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2897
2898 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2899 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2900 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2901
2902 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2903 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2904 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2905
2906 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2907 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2908 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2909 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2910 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2911 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2912 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2913
2914 /* to avoid GPU doing any preloading of constant from random address */
2915 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2916 for (i = 0; i < 16; i++)
2917 r600_store_value(cb, 0);
2918
2919 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2920 for (i = 0; i < 16; i++)
2921 r600_store_value(cb, 0);
2922
2923 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2924 for (i = 0; i < 16; i++)
2925 r600_store_value(cb, 0);
2926
2927 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2928 for (i = 0; i < 16; i++)
2929 r600_store_value(cb, 0);
2930
2931 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2932 for (i = 0; i < 16; i++)
2933 r600_store_value(cb, 0);
2934
2935 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2936
2937 if (rctx->screen->b.has_streamout) {
2938 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2939 }
2940
2941 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2942 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2943 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2944 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2945 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2946 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2947
2948 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2949 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2950 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2951
2952 if (rctx->b.family == CHIP_CAICOS) {
2953 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2954 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2955 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2956 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2957 } else {
2958 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
2959 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2960 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2961 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
2962 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
2963 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
2964 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
2965 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
2966 }
2967
2968 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2969 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2970 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2971 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2972 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2973 }
2974
2975 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2976 {
2977 struct r600_context *rctx = (struct r600_context *)ctx;
2978 struct r600_command_buffer *cb = &shader->command_buffer;
2979 struct r600_shader *rshader = &shader->shader;
2980 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
2981 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2982 int ninterp = 0;
2983 boolean have_perspective = FALSE, have_linear = FALSE;
2984 static const unsigned spi_baryc_enable_bit[6] = {
2985 S_0286E0_PERSP_SAMPLE_ENA(1),
2986 S_0286E0_PERSP_CENTER_ENA(1),
2987 S_0286E0_PERSP_CENTROID_ENA(1),
2988 S_0286E0_LINEAR_SAMPLE_ENA(1),
2989 S_0286E0_LINEAR_CENTER_ENA(1),
2990 S_0286E0_LINEAR_CENTROID_ENA(1)
2991 };
2992 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
2993 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2994 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2995 uint32_t spi_ps_input_cntl[32];
2996
2997 if (!cb->buf) {
2998 r600_init_command_buffer(cb, 64);
2999 } else {
3000 cb->num_dw = 0;
3001 }
3002
3003 for (i = 0; i < rshader->ninput; i++) {
3004 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3005 POSITION goes via GPRs from the SC so isn't counted */
3006 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3007 pos_index = i;
3008 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
3009 if (face_index == -1)
3010 face_index = i;
3011 }
3012 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3013 if (face_index == -1)
3014 face_index = i; /* lives in same register, same enable bit */
3015 }
3016 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
3017 fixed_pt_position_index = i;
3018 }
3019 else {
3020 ninterp++;
3021 int k = eg_get_interpolator_index(
3022 rshader->input[i].interpolate,
3023 rshader->input[i].interpolate_location);
3024 if (k >= 0) {
3025 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3026 have_perspective |= k < 3;
3027 have_linear |= !(k < 3);
3028 }
3029 }
3030
3031 sid = rshader->input[i].spi_sid;
3032
3033 if (sid) {
3034 tmp = S_028644_SEMANTIC(sid);
3035
3036 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3037 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3038 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3039 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3040 tmp |= S_028644_FLAT_SHADE(1);
3041 }
3042
3043 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3044 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3045 tmp |= S_028644_PT_SPRITE_TEX(1);
3046 }
3047
3048 spi_ps_input_cntl[num++] = tmp;
3049 }
3050 }
3051
3052 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3053 r600_store_array(cb, num, spi_ps_input_cntl);
3054
3055 for (i = 0; i < rshader->noutput; i++) {
3056 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3057 z_export = 1;
3058 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3059 stencil_export = 1;
3060 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3061 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3062 mask_export = 1;
3063 }
3064 if (rshader->uses_kill)
3065 db_shader_control |= S_02880C_KILL_ENABLE(1);
3066
3067 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3068 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3069 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3070
3071 switch (rshader->ps_conservative_z) {
3072 default: /* fall through */
3073 case TGSI_FS_DEPTH_LAYOUT_ANY:
3074 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3075 break;
3076 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3077 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3078 break;
3079 case TGSI_FS_DEPTH_LAYOUT_LESS:
3080 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3081 break;
3082 }
3083
3084 exports_ps = 0;
3085 for (i = 0; i < rshader->noutput; i++) {
3086 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3087 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3088 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3089 exports_ps |= 1;
3090 }
3091
3092 num_cout = rshader->nr_ps_color_exports;
3093
3094 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3095 if (!exports_ps) {
3096 /* always at least export 1 component per pixel */
3097 exports_ps = 2;
3098 }
3099 shader->nr_ps_color_outputs = num_cout;
3100 if (ninterp == 0) {
3101 ninterp = 1;
3102 have_perspective = TRUE;
3103 }
3104 if (!spi_baryc_cntl)
3105 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3106
3107 if (!have_perspective && !have_linear)
3108 have_perspective = TRUE;
3109
3110 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3111 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3112 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3113 spi_input_z = 0;
3114 if (pos_index != -1) {
3115 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3116 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3117 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3118 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3119 }
3120
3121 spi_ps_in_control_1 = 0;
3122 if (face_index != -1) {
3123 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3124 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3125 }
3126 if (fixed_pt_position_index != -1) {
3127 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3128 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3129 }
3130
3131 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3132 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3133 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3134
3135 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3136 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3137 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3138
3139 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3140 r600_store_value(cb, shader->bo->gpu_address >> 8);
3141 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3142 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3143 S_028844_PRIME_CACHE_ON_DRAW(1) |
3144 S_028844_STACK_SIZE(rshader->bc.nstack));
3145 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3146
3147 shader->db_shader_control = db_shader_control;
3148 shader->ps_depth_export = z_export | stencil_export | mask_export;
3149
3150 shader->sprite_coord_enable = sprite_coord_enable;
3151 if (rctx->rasterizer)
3152 shader->flatshade = rctx->rasterizer->flatshade;
3153 }
3154
3155 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3156 {
3157 struct r600_command_buffer *cb = &shader->command_buffer;
3158 struct r600_shader *rshader = &shader->shader;
3159
3160 r600_init_command_buffer(cb, 32);
3161
3162 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3163 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3164 S_028890_STACK_SIZE(rshader->bc.nstack));
3165 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3166 shader->bo->gpu_address >> 8);
3167 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3168 }
3169
3170 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3171 {
3172 struct r600_context *rctx = (struct r600_context *)ctx;
3173 struct r600_command_buffer *cb = &shader->command_buffer;
3174 struct r600_shader *rshader = &shader->shader;
3175 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3176 unsigned gsvs_itemsizes[4] = {
3177 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3178 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3179 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3180 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3181 };
3182
3183 r600_init_command_buffer(cb, 64);
3184
3185 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3186
3187
3188 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3189 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3190 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3191 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3192
3193 if (rctx->screen->b.info.drm_minor >= 35) {
3194 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3195 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3196 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3197 }
3198 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3199 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3200 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3201 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3202 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3203
3204 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3205 (rshader->ring_item_sizes[0]) >> 2);
3206
3207 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3208 gsvs_itemsizes[0] +
3209 gsvs_itemsizes[1] +
3210 gsvs_itemsizes[2] +
3211 gsvs_itemsizes[3]);
3212
3213 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3214 r600_store_value(cb, gsvs_itemsizes[0]);
3215 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3216 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3217
3218 /* FIXME calculate these values somehow ??? */
3219 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3220 r600_store_value(cb, 0x80); /* GS_PER_ES */
3221 r600_store_value(cb, 0x100); /* ES_PER_GS */
3222 r600_store_value(cb, 0x2); /* GS_PER_VS */
3223
3224 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3225 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3226 S_028878_STACK_SIZE(rshader->bc.nstack));
3227 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3228 shader->bo->gpu_address >> 8);
3229 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3230 }
3231
3232
3233 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3234 {
3235 struct r600_command_buffer *cb = &shader->command_buffer;
3236 struct r600_shader *rshader = &shader->shader;
3237 unsigned spi_vs_out_id[10] = {};
3238 unsigned i, tmp, nparams = 0;
3239
3240 for (i = 0; i < rshader->noutput; i++) {
3241 if (rshader->output[i].spi_sid) {
3242 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3243 spi_vs_out_id[nparams / 4] |= tmp;
3244 nparams++;
3245 }
3246 }
3247
3248 r600_init_command_buffer(cb, 32);
3249
3250 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3251 for (i = 0; i < 10; i++) {
3252 r600_store_value(cb, spi_vs_out_id[i]);
3253 }
3254
3255 /* Certain attributes (position, psize, etc.) don't count as params.
3256 * VS is required to export at least one param and r600_shader_from_tgsi()
3257 * takes care of adding a dummy export.
3258 */
3259 if (nparams < 1)
3260 nparams = 1;
3261
3262 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3263 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3264 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3265 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3266 S_028860_STACK_SIZE(rshader->bc.nstack));
3267 if (rshader->vs_position_window_space) {
3268 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3269 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3270 } else {
3271 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3272 S_028818_VTX_W0_FMT(1) |
3273 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3274 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3275 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3276
3277 }
3278 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3279 shader->bo->gpu_address >> 8);
3280 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3281
3282 shader->pa_cl_vs_out_cntl =
3283 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3284 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3285 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3286 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3287 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3288 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3289 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3290 }
3291
3292 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3293 {
3294 struct r600_command_buffer *cb = &shader->command_buffer;
3295 struct r600_shader *rshader = &shader->shader;
3296
3297 r600_init_command_buffer(cb, 32);
3298 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3299 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3300 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3301 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3302 shader->bo->gpu_address >> 8);
3303 }
3304
3305 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3306 {
3307 struct r600_command_buffer *cb = &shader->command_buffer;
3308 struct r600_shader *rshader = &shader->shader;
3309
3310 r600_init_command_buffer(cb, 32);
3311 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3312 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3313 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3314 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3315 shader->bo->gpu_address >> 8);
3316 }
3317 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3318 {
3319 struct pipe_blend_state blend;
3320
3321 memset(&blend, 0, sizeof(blend));
3322 blend.independent_blend_enable = true;
3323 blend.rt[0].colormask = 0xf;
3324 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3325 }
3326
3327 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3328 {
3329 struct pipe_blend_state blend;
3330 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3331 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3332
3333 memset(&blend, 0, sizeof(blend));
3334 blend.independent_blend_enable = true;
3335 blend.rt[0].colormask = 0xf;
3336 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3337 }
3338
3339 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3340 {
3341 struct pipe_blend_state blend;
3342 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3343
3344 memset(&blend, 0, sizeof(blend));
3345 blend.independent_blend_enable = true;
3346 blend.rt[0].colormask = 0xf;
3347 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3348 }
3349
3350 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3351 {
3352 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3353
3354 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3355 }
3356
3357 void evergreen_update_db_shader_control(struct r600_context * rctx)
3358 {
3359 bool dual_export;
3360 unsigned db_shader_control;
3361
3362 if (!rctx->ps_shader) {
3363 return;
3364 }
3365
3366 dual_export = rctx->framebuffer.export_16bpc &&
3367 !rctx->ps_shader->current->ps_depth_export;
3368
3369 db_shader_control = rctx->ps_shader->current->db_shader_control |
3370 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3371 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3372 V_02880C_EXPORT_DB_FULL) |
3373 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3374
3375 /* When alpha test is enabled we can't trust the hw to make the proper
3376 * decision on the order in which ztest should be run related to fragment
3377 * shader execution.
3378 *
3379 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3380 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3381 * execution and thus after alpha test so if discarded by the alpha test
3382 * the z value is not written.
3383 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3384 * get a hang unless you flush the DB in between. For now just use
3385 * LATE_Z.
3386 */
3387 if (rctx->alphatest_state.sx_alpha_test_control) {
3388 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3389 } else {
3390 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3391 }
3392
3393 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3394 rctx->db_misc_state.db_shader_control = db_shader_control;
3395 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3396 }
3397 }
3398
3399 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3400 struct pipe_resource *dst,
3401 unsigned dst_level,
3402 unsigned dst_x,
3403 unsigned dst_y,
3404 unsigned dst_z,
3405 struct pipe_resource *src,
3406 unsigned src_level,
3407 unsigned src_x,
3408 unsigned src_y,
3409 unsigned src_z,
3410 unsigned copy_height,
3411 unsigned pitch,
3412 unsigned bpp)
3413 {
3414 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3415 struct r600_texture *rsrc = (struct r600_texture*)src;
3416 struct r600_texture *rdst = (struct r600_texture*)dst;
3417 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3418 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3419 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3420 uint64_t base, addr;
3421
3422 dst_mode = rdst->surface.level[dst_level].mode;
3423 src_mode = rsrc->surface.level[src_level].mode;
3424 /* downcast linear aligned to linear to simplify test */
3425 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3426 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3427 assert(dst_mode != src_mode);
3428
3429 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3430 if (util_format_has_depth(util_format_description(src->format)))
3431 non_disp_tiling = 1;
3432
3433 y = 0;
3434 sub_cmd = EG_DMA_COPY_TILED;
3435 lbpp = util_logbase2(bpp);
3436 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3437 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3438
3439 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
3440 /* T2L */
3441 array_mode = evergreen_array_mode(src_mode);
3442 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
3443 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3444 /* linear height must be the same as the slice tile max height, it's ok even
3445 * if the linear destination/source have smaller heigh as the size of the
3446 * dma packet will be using the copy_height which is always smaller or equal
3447 * to the linear height
3448 */
3449 height = rsrc->surface.level[src_level].npix_y;
3450 detile = 1;
3451 x = src_x;
3452 y = src_y;
3453 z = src_z;
3454 base = rsrc->surface.level[src_level].offset;
3455 addr = rdst->surface.level[dst_level].offset;
3456 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3457 addr += dst_y * pitch + dst_x * bpp;
3458 bank_h = eg_bank_wh(rsrc->surface.bankh);
3459 bank_w = eg_bank_wh(rsrc->surface.bankw);
3460 mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
3461 tile_split = eg_tile_split(rsrc->surface.tile_split);
3462 base += rsrc->resource.gpu_address;
3463 addr += rdst->resource.gpu_address;
3464 } else {
3465 /* L2T */
3466 array_mode = evergreen_array_mode(dst_mode);
3467 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
3468 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3469 /* linear height must be the same as the slice tile max height, it's ok even
3470 * if the linear destination/source have smaller heigh as the size of the
3471 * dma packet will be using the copy_height which is always smaller or equal
3472 * to the linear height
3473 */
3474 height = rdst->surface.level[dst_level].npix_y;
3475 detile = 0;
3476 x = dst_x;
3477 y = dst_y;
3478 z = dst_z;
3479 base = rdst->surface.level[dst_level].offset;
3480 addr = rsrc->surface.level[src_level].offset;
3481 addr += rsrc->surface.level[src_level].slice_size * src_z;
3482 addr += src_y * pitch + src_x * bpp;
3483 bank_h = eg_bank_wh(rdst->surface.bankh);
3484 bank_w = eg_bank_wh(rdst->surface.bankw);
3485 mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
3486 tile_split = eg_tile_split(rdst->surface.tile_split);
3487 base += rdst->resource.gpu_address;
3488 addr += rsrc->resource.gpu_address;
3489 }
3490
3491 size = (copy_height * pitch) / 4;
3492 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3493 r600_need_dma_space(&rctx->b, ncopy * 9);
3494
3495 for (i = 0; i < ncopy; i++) {
3496 cheight = copy_height;
3497 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3498 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3499 }
3500 size = (cheight * pitch) / 4;
3501 /* emit reloc before writing cs so that cs is always in consistent state */
3502 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3503 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3504 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3505 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3506 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
3507 cs->buf[cs->cdw++] = base >> 8;
3508 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3509 (lbpp << 24) | (bank_h << 21) |
3510 (bank_w << 18) | (mt_aspect << 16);
3511 cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
3512 cs->buf[cs->cdw++] = (slice_tile_max << 0);
3513 cs->buf[cs->cdw++] = (x << 0) | (z << 18);
3514 cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28);
3515 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3516 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3517 copy_height -= cheight;
3518 addr += cheight * pitch;
3519 y += cheight;
3520 }
3521 }
3522
3523 static void evergreen_dma_copy(struct pipe_context *ctx,
3524 struct pipe_resource *dst,
3525 unsigned dst_level,
3526 unsigned dstx, unsigned dsty, unsigned dstz,
3527 struct pipe_resource *src,
3528 unsigned src_level,
3529 const struct pipe_box *src_box)
3530 {
3531 struct r600_context *rctx = (struct r600_context *)ctx;
3532 struct r600_texture *rsrc = (struct r600_texture*)src;
3533 struct r600_texture *rdst = (struct r600_texture*)dst;
3534 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3535 unsigned src_w, dst_w;
3536 unsigned src_x, src_y;
3537 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3538
3539 if (rctx->b.dma.cs == NULL) {
3540 goto fallback;
3541 }
3542
3543 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3544 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3545 return;
3546 }
3547
3548 if (src->format != dst->format || src_box->depth > 1 ||
3549 (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level)) {
3550 goto fallback;
3551 }
3552
3553 if (rsrc->dirty_level_mask & (1 << src_level)) {
3554 ctx->flush_resource(ctx, src);
3555 }
3556
3557 src_x = util_format_get_nblocksx(src->format, src_box->x);
3558 dst_x = util_format_get_nblocksx(src->format, dst_x);
3559 src_y = util_format_get_nblocksy(src->format, src_box->y);
3560 dst_y = util_format_get_nblocksy(src->format, dst_y);
3561
3562 bpp = rdst->surface.bpe;
3563 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3564 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3565 src_w = rsrc->surface.level[src_level].npix_x;
3566 dst_w = rdst->surface.level[dst_level].npix_x;
3567 copy_height = src_box->height / rsrc->surface.blk_h;
3568
3569 dst_mode = rdst->surface.level[dst_level].mode;
3570 src_mode = rsrc->surface.level[src_level].mode;
3571 /* downcast linear aligned to linear to simplify test */
3572 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3573 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3574
3575 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3576 /* FIXME evergreen can do partial blit */
3577 goto fallback;
3578 }
3579 /* the x test here are currently useless (because we don't support partial blit)
3580 * but keep them around so we don't forget about those
3581 */
3582 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3583 goto fallback;
3584 }
3585
3586 /* 128 bpp surfaces require non_disp_tiling for both
3587 * tiled and linear buffers on cayman. However, async
3588 * DMA only supports it on the tiled side. As such
3589 * the tile order is backwards after a L2T/T2L packet.
3590 */
3591 if ((rctx->b.chip_class == CAYMAN) &&
3592 (src_mode != dst_mode) &&
3593 (util_format_get_blocksize(src->format) >= 16)) {
3594 goto fallback;
3595 }
3596
3597 if (src_mode == dst_mode) {
3598 uint64_t dst_offset, src_offset;
3599 /* simple dma blit would do NOTE code here assume :
3600 * src_box.x/y == 0
3601 * dst_x/y == 0
3602 * dst_pitch == src_pitch
3603 */
3604 src_offset= rsrc->surface.level[src_level].offset;
3605 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3606 src_offset += src_y * src_pitch + src_x * bpp;
3607 dst_offset = rdst->surface.level[dst_level].offset;
3608 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3609 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3610 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3611 src_box->height * src_pitch);
3612 } else {
3613 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3614 src, src_level, src_x, src_y, src_box->z,
3615 copy_height, dst_pitch, bpp);
3616 }
3617 return;
3618
3619 fallback:
3620 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3621 src, src_level, src_box);
3622 }
3623
3624 static void evergreen_set_tess_state(struct pipe_context *ctx,
3625 const float default_outer_level[4],
3626 const float default_inner_level[2])
3627 {
3628 struct r600_context *rctx = (struct r600_context *)ctx;
3629
3630 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3631 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3632 rctx->tess_state_dirty = true;
3633 }
3634
3635 void evergreen_init_state_functions(struct r600_context *rctx)
3636 {
3637 unsigned id = 1;
3638 unsigned i;
3639 /* !!!
3640 * To avoid GPU lockup registers must be emitted in a specific order
3641 * (no kidding ...). The order below is important and have been
3642 * partially inferred from analyzing fglrx command stream.
3643 *
3644 * Don't reorder atom without carefully checking the effect (GPU lockup
3645 * or piglit regression).
3646 * !!!
3647 */
3648 if (rctx->b.chip_class == EVERGREEN) {
3649 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
3650 rctx->config_state.dyn_gpr_enabled = true;
3651 }
3652 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
3653 /* shader const */
3654 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
3655 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
3656 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
3657 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
3658 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
3659 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
3660 /* shader program */
3661 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
3662 /* sampler */
3663 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
3664 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
3665 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
3666 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
3667 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
3668 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
3669 /* resources */
3670 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
3671 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
3672 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
3673 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
3674 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
3675 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
3676 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
3677 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
3678
3679 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3680
3681 if (rctx->b.chip_class == EVERGREEN) {
3682 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
3683 } else {
3684 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
3685 }
3686 rctx->sample_mask.sample_mask = ~0;
3687
3688 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3689 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3690 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3691 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
3692 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
3693 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
3694 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
3695 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
3696 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3697 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
3698 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3699 r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 0);
3700 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 0);
3701 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3702 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
3703 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3704 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3705 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3706 for (i = 0; i < EG_NUM_HW_STAGES; i++)
3707 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3708 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
3709 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
3710
3711 rctx->b.b.create_blend_state = evergreen_create_blend_state;
3712 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
3713 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
3714 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
3715 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
3716 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
3717 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
3718 rctx->b.b.set_min_samples = evergreen_set_min_samples;
3719 rctx->b.b.set_scissor_states = evergreen_set_scissor_states;
3720 rctx->b.b.set_tess_state = evergreen_set_tess_state;
3721 if (rctx->b.chip_class == EVERGREEN)
3722 rctx->b.b.get_sample_position = evergreen_get_sample_position;
3723 else
3724 rctx->b.b.get_sample_position = cayman_get_sample_position;
3725 rctx->b.dma_copy = evergreen_dma_copy;
3726
3727 evergreen_init_compute_state_functions(rctx);
3728 }
3729
3730 /**
3731 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
3732 *
3733 * The information about LDS and other non-compile-time parameters is then
3734 * written to the const buffer.
3735
3736 * const buffer contains -
3737 * uint32_t input_patch_size
3738 * uint32_t input_vertex_size
3739 * uint32_t num_tcs_input_cp
3740 * uint32_t num_tcs_output_cp;
3741 * uint32_t output_patch_size
3742 * uint32_t output_vertex_size
3743 * uint32_t output_patch0_offset
3744 * uint32_t perpatch_output_offset
3745 * and the same constbuf is bound to LS/HS/VS(ES).
3746 */
3747 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
3748 {
3749 struct pipe_constant_buffer constbuf = {0};
3750 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
3751 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
3752 unsigned num_tcs_input_cp = info->vertices_per_patch;
3753 unsigned num_tcs_outputs;
3754 unsigned num_tcs_output_cp;
3755 unsigned num_tcs_patch_outputs;
3756 unsigned num_tcs_inputs;
3757 unsigned input_vertex_size, output_vertex_size;
3758 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
3759 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
3760 uint32_t values[16];
3761 unsigned num_waves;
3762 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
3763 unsigned wave_divisor = (16 * num_pipes);
3764
3765 *num_patches = 1;
3766
3767 if (!rctx->tes_shader) {
3768 rctx->lds_alloc = 0;
3769 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3770 R600_LDS_INFO_CONST_BUFFER, NULL);
3771 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3772 R600_LDS_INFO_CONST_BUFFER, NULL);
3773 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3774 R600_LDS_INFO_CONST_BUFFER, NULL);
3775 return;
3776 }
3777
3778 if (rctx->lds_alloc != 0 &&
3779 rctx->last_ls == ls &&
3780 !rctx->tess_state_dirty &&
3781 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
3782 rctx->last_tcs == tcs)
3783 return;
3784
3785 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
3786
3787 if (rctx->tcs_shader) {
3788 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
3789 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
3790 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
3791 } else {
3792 num_tcs_outputs = num_tcs_inputs;
3793 num_tcs_output_cp = num_tcs_input_cp;
3794 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
3795 }
3796
3797 /* size in bytes */
3798 input_vertex_size = num_tcs_inputs * 16;
3799 output_vertex_size = num_tcs_outputs * 16;
3800
3801 input_patch_size = num_tcs_input_cp * input_vertex_size;
3802
3803 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
3804 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3805
3806 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
3807 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
3808
3809 lds_size = output_patch0_offset + output_patch_size * *num_patches;
3810
3811 values[0] = input_patch_size;
3812 values[1] = input_vertex_size;
3813 values[2] = num_tcs_input_cp;
3814 values[3] = num_tcs_output_cp;
3815
3816 values[4] = output_patch_size;
3817 values[5] = output_vertex_size;
3818 values[6] = output_patch0_offset;
3819 values[7] = perpatch_output_offset;
3820
3821 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
3822 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
3823 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
3824
3825 rctx->lds_alloc = (lds_size | (num_waves << 14));
3826
3827 memcpy(&values[8], rctx->tess_state, 6 * sizeof(float));
3828 values[14] = 0;
3829 values[15] = 0;
3830
3831 rctx->tess_state_dirty = false;
3832 rctx->last_ls = ls;
3833 rctx->last_tcs = tcs;
3834 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
3835
3836 constbuf.user_buffer = values;
3837 constbuf.buffer_size = 16 * 4;
3838
3839 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3840 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3841 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3842 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3843 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3844 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3845 pipe_resource_reference(&constbuf.buffer, NULL);
3846 }
3847
3848 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
3849 const struct pipe_draw_info *info,
3850 unsigned num_patches)
3851 {
3852 unsigned num_output_cp;
3853
3854 if (!rctx->tes_shader)
3855 return 0;
3856
3857 num_output_cp = rctx->tcs_shader ?
3858 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
3859 info->vertices_per_patch;
3860
3861 return S_028B58_NUM_PATCHES(num_patches) |
3862 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
3863 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
3864 }
3865
3866 void evergreen_set_ls_hs_config(struct r600_context *rctx,
3867 struct radeon_winsys_cs *cs,
3868 uint32_t ls_hs_config)
3869 {
3870 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
3871 }
3872
3873 void evergreen_set_lds_alloc(struct r600_context *rctx,
3874 struct radeon_winsys_cs *cs,
3875 uint32_t lds_alloc)
3876 {
3877 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
3878 }
3879
3880 /* on evergreen if you are running tessellation you need to disable dynamic
3881 GPRs to workaround a hardware bug.*/
3882 bool evergreen_adjust_gprs(struct r600_context *rctx)
3883 {
3884 unsigned num_gprs[EG_NUM_HW_STAGES];
3885 unsigned def_gprs[EG_NUM_HW_STAGES];
3886 unsigned cur_gprs[EG_NUM_HW_STAGES];
3887 unsigned new_gprs[EG_NUM_HW_STAGES];
3888 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
3889 unsigned max_gprs;
3890 unsigned i;
3891 unsigned total_gprs;
3892 unsigned tmp[3];
3893 bool rework = false, set_default = false, set_dirty = false;
3894 max_gprs = 0;
3895 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3896 def_gprs[i] = rctx->default_gprs[i];
3897 max_gprs += def_gprs[i];
3898 }
3899 max_gprs += def_num_clause_temp_gprs * 2;
3900
3901 /* if we have no TESS and dyn gpr is enabled then do nothing. */
3902 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
3903 if (rctx->config_state.dyn_gpr_enabled)
3904 return true;
3905
3906 /* transition back to dyn gpr enabled state */
3907 rctx->config_state.dyn_gpr_enabled = true;
3908 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3909 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3910 return true;
3911 }
3912
3913
3914 /* gather required shader gprs */
3915 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3916 if (rctx->hw_shader_stages[i].shader)
3917 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
3918 else
3919 num_gprs[i] = 0;
3920 }
3921
3922 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3923 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3924 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3925 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3926 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3927 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3928
3929 total_gprs = 0;
3930 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3931 new_gprs[i] = num_gprs[i];
3932 total_gprs += num_gprs[i];
3933 }
3934
3935 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
3936 return false;
3937
3938 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3939 if (new_gprs[i] > cur_gprs[i]) {
3940 rework = true;
3941 break;
3942 }
3943 }
3944
3945 if (rctx->config_state.dyn_gpr_enabled) {
3946 set_dirty = true;
3947 rctx->config_state.dyn_gpr_enabled = false;
3948 }
3949
3950 if (rework) {
3951 set_default = true;
3952 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3953 if (new_gprs[i] > def_gprs[i])
3954 set_default = false;
3955 }
3956
3957 if (set_default) {
3958 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3959 new_gprs[i] = def_gprs[i];
3960 }
3961 } else {
3962 unsigned ps_value = max_gprs;
3963
3964 ps_value -= (def_num_clause_temp_gprs * 2);
3965 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
3966 ps_value -= new_gprs[i];
3967
3968 new_gprs[R600_HW_STAGE_PS] = ps_value;
3969 }
3970
3971 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
3972 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
3973 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
3974
3975 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
3976 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
3977
3978 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
3979 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
3980
3981 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
3982 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
3983 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
3984 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
3985 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
3986 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
3987 set_dirty = true;
3988 }
3989 }
3990
3991
3992 if (set_dirty) {
3993 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3994 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3995 }
3996 return true;
3997 }