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r600g: add support for separately allocated CMASKs
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static INLINE unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
39 break;
40 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
41 break;
42 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
43 default:
44 case RADEON_SURF_MODE_LINEAR: return V_028C70_ARRAY_LINEAR_GENERAL;
45 }
46 }
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
174 {
175 switch (dim) {
176 default:
177 case PIPE_TEXTURE_1D:
178 return V_030000_SQ_TEX_DIM_1D;
179 case PIPE_TEXTURE_1D_ARRAY:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY;
181 case PIPE_TEXTURE_2D:
182 case PIPE_TEXTURE_RECT:
183 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
184 V_030000_SQ_TEX_DIM_2D;
185 case PIPE_TEXTURE_2D_ARRAY:
186 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
187 V_030000_SQ_TEX_DIM_2D_ARRAY;
188 case PIPE_TEXTURE_3D:
189 return V_030000_SQ_TEX_DIM_3D;
190 case PIPE_TEXTURE_CUBE:
191 case PIPE_TEXTURE_CUBE_ARRAY:
192 return V_030000_SQ_TEX_DIM_CUBEMAP;
193 }
194 }
195
196 static uint32_t r600_translate_dbformat(enum pipe_format format)
197 {
198 switch (format) {
199 case PIPE_FORMAT_Z16_UNORM:
200 return V_028040_Z_16;
201 case PIPE_FORMAT_Z24X8_UNORM:
202 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
203 case PIPE_FORMAT_X8Z24_UNORM:
204 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
205 return V_028040_Z_24;
206 case PIPE_FORMAT_Z32_FLOAT:
207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
208 return V_028040_Z_32_FLOAT;
209 default:
210 return ~0U;
211 }
212 }
213
214 static uint32_t r600_translate_colorswap(enum pipe_format format)
215 {
216 switch (format) {
217 /* 8-bit buffers. */
218 case PIPE_FORMAT_L4A4_UNORM:
219 case PIPE_FORMAT_A4R4_UNORM:
220 return V_028C70_SWAP_ALT;
221
222 case PIPE_FORMAT_A8_UNORM:
223 case PIPE_FORMAT_A8_SNORM:
224 case PIPE_FORMAT_A8_UINT:
225 case PIPE_FORMAT_A8_SINT:
226 case PIPE_FORMAT_A16_UNORM:
227 case PIPE_FORMAT_A16_SNORM:
228 case PIPE_FORMAT_A16_UINT:
229 case PIPE_FORMAT_A16_SINT:
230 case PIPE_FORMAT_A16_FLOAT:
231 case PIPE_FORMAT_A32_UINT:
232 case PIPE_FORMAT_A32_SINT:
233 case PIPE_FORMAT_A32_FLOAT:
234 case PIPE_FORMAT_R4A4_UNORM:
235 return V_028C70_SWAP_ALT_REV;
236 case PIPE_FORMAT_I8_UNORM:
237 case PIPE_FORMAT_I8_SNORM:
238 case PIPE_FORMAT_I8_UINT:
239 case PIPE_FORMAT_I8_SINT:
240 case PIPE_FORMAT_I16_UNORM:
241 case PIPE_FORMAT_I16_SNORM:
242 case PIPE_FORMAT_I16_UINT:
243 case PIPE_FORMAT_I16_SINT:
244 case PIPE_FORMAT_I16_FLOAT:
245 case PIPE_FORMAT_I32_UINT:
246 case PIPE_FORMAT_I32_SINT:
247 case PIPE_FORMAT_I32_FLOAT:
248 case PIPE_FORMAT_L8_UNORM:
249 case PIPE_FORMAT_L8_SNORM:
250 case PIPE_FORMAT_L8_UINT:
251 case PIPE_FORMAT_L8_SINT:
252 case PIPE_FORMAT_L8_SRGB:
253 case PIPE_FORMAT_L16_UNORM:
254 case PIPE_FORMAT_L16_SNORM:
255 case PIPE_FORMAT_L16_UINT:
256 case PIPE_FORMAT_L16_SINT:
257 case PIPE_FORMAT_L16_FLOAT:
258 case PIPE_FORMAT_L32_UINT:
259 case PIPE_FORMAT_L32_SINT:
260 case PIPE_FORMAT_L32_FLOAT:
261 case PIPE_FORMAT_R8_UNORM:
262 case PIPE_FORMAT_R8_SNORM:
263 case PIPE_FORMAT_R8_UINT:
264 case PIPE_FORMAT_R8_SINT:
265 return V_028C70_SWAP_STD;
266
267 /* 16-bit buffers. */
268 case PIPE_FORMAT_B5G6R5_UNORM:
269 return V_028C70_SWAP_STD_REV;
270
271 case PIPE_FORMAT_B5G5R5A1_UNORM:
272 case PIPE_FORMAT_B5G5R5X1_UNORM:
273 return V_028C70_SWAP_ALT;
274
275 case PIPE_FORMAT_B4G4R4A4_UNORM:
276 case PIPE_FORMAT_B4G4R4X4_UNORM:
277 return V_028C70_SWAP_ALT;
278
279 case PIPE_FORMAT_Z16_UNORM:
280 return V_028C70_SWAP_STD;
281
282 case PIPE_FORMAT_L8A8_UNORM:
283 case PIPE_FORMAT_L8A8_SNORM:
284 case PIPE_FORMAT_L8A8_UINT:
285 case PIPE_FORMAT_L8A8_SINT:
286 case PIPE_FORMAT_L8A8_SRGB:
287 case PIPE_FORMAT_L16A16_UNORM:
288 case PIPE_FORMAT_L16A16_SNORM:
289 case PIPE_FORMAT_L16A16_UINT:
290 case PIPE_FORMAT_L16A16_SINT:
291 case PIPE_FORMAT_L16A16_FLOAT:
292 case PIPE_FORMAT_L32A32_UINT:
293 case PIPE_FORMAT_L32A32_SINT:
294 case PIPE_FORMAT_L32A32_FLOAT:
295 case PIPE_FORMAT_R8A8_UNORM:
296 case PIPE_FORMAT_R8A8_SNORM:
297 case PIPE_FORMAT_R8A8_UINT:
298 case PIPE_FORMAT_R8A8_SINT:
299 case PIPE_FORMAT_R16A16_UNORM:
300 case PIPE_FORMAT_R16A16_SNORM:
301 case PIPE_FORMAT_R16A16_UINT:
302 case PIPE_FORMAT_R16A16_SINT:
303 case PIPE_FORMAT_R16A16_FLOAT:
304 case PIPE_FORMAT_R32A32_UINT:
305 case PIPE_FORMAT_R32A32_SINT:
306 case PIPE_FORMAT_R32A32_FLOAT:
307 return V_028C70_SWAP_ALT;
308 case PIPE_FORMAT_R8G8_UNORM:
309 case PIPE_FORMAT_R8G8_SNORM:
310 case PIPE_FORMAT_R8G8_UINT:
311 case PIPE_FORMAT_R8G8_SINT:
312 return V_028C70_SWAP_STD;
313
314 case PIPE_FORMAT_R16_UNORM:
315 case PIPE_FORMAT_R16_SNORM:
316 case PIPE_FORMAT_R16_UINT:
317 case PIPE_FORMAT_R16_SINT:
318 case PIPE_FORMAT_R16_FLOAT:
319 return V_028C70_SWAP_STD;
320
321 /* 32-bit buffers. */
322 case PIPE_FORMAT_A8B8G8R8_SRGB:
323 return V_028C70_SWAP_STD_REV;
324 case PIPE_FORMAT_B8G8R8A8_SRGB:
325 return V_028C70_SWAP_ALT;
326
327 case PIPE_FORMAT_B8G8R8A8_UNORM:
328 case PIPE_FORMAT_B8G8R8X8_UNORM:
329 return V_028C70_SWAP_ALT;
330
331 case PIPE_FORMAT_A8R8G8B8_UNORM:
332 case PIPE_FORMAT_X8R8G8B8_UNORM:
333 return V_028C70_SWAP_ALT_REV;
334 case PIPE_FORMAT_R8G8B8A8_SNORM:
335 case PIPE_FORMAT_R8G8B8A8_UNORM:
336 case PIPE_FORMAT_R8G8B8A8_SINT:
337 case PIPE_FORMAT_R8G8B8A8_UINT:
338 case PIPE_FORMAT_R8G8B8X8_UNORM:
339 case PIPE_FORMAT_R8G8B8X8_SNORM:
340 case PIPE_FORMAT_R8G8B8X8_SRGB:
341 case PIPE_FORMAT_R8G8B8X8_UINT:
342 case PIPE_FORMAT_R8G8B8X8_SINT:
343 return V_028C70_SWAP_STD;
344
345 case PIPE_FORMAT_A8B8G8R8_UNORM:
346 case PIPE_FORMAT_X8B8G8R8_UNORM:
347 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
348 return V_028C70_SWAP_STD_REV;
349
350 case PIPE_FORMAT_Z24X8_UNORM:
351 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
352 return V_028C70_SWAP_STD;
353
354 case PIPE_FORMAT_X8Z24_UNORM:
355 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
356 return V_028C70_SWAP_STD_REV;
357
358 case PIPE_FORMAT_R10G10B10A2_UNORM:
359 case PIPE_FORMAT_R10G10B10X2_SNORM:
360 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
361 return V_028C70_SWAP_STD;
362
363 case PIPE_FORMAT_B10G10R10A2_UNORM:
364 case PIPE_FORMAT_B10G10R10A2_UINT:
365 case PIPE_FORMAT_B10G10R10X2_UNORM:
366 return V_028C70_SWAP_ALT;
367
368 case PIPE_FORMAT_R11G11B10_FLOAT:
369 case PIPE_FORMAT_R32_FLOAT:
370 case PIPE_FORMAT_R32_UINT:
371 case PIPE_FORMAT_R32_SINT:
372 case PIPE_FORMAT_Z32_FLOAT:
373 case PIPE_FORMAT_R16G16_FLOAT:
374 case PIPE_FORMAT_R16G16_UNORM:
375 case PIPE_FORMAT_R16G16_SNORM:
376 case PIPE_FORMAT_R16G16_UINT:
377 case PIPE_FORMAT_R16G16_SINT:
378 return V_028C70_SWAP_STD;
379
380 /* 64-bit buffers. */
381 case PIPE_FORMAT_R32G32_FLOAT:
382 case PIPE_FORMAT_R32G32_UINT:
383 case PIPE_FORMAT_R32G32_SINT:
384 case PIPE_FORMAT_R16G16B16A16_UNORM:
385 case PIPE_FORMAT_R16G16B16A16_SNORM:
386 case PIPE_FORMAT_R16G16B16A16_UINT:
387 case PIPE_FORMAT_R16G16B16A16_SINT:
388 case PIPE_FORMAT_R16G16B16A16_FLOAT:
389 case PIPE_FORMAT_R16G16B16X16_UNORM:
390 case PIPE_FORMAT_R16G16B16X16_SNORM:
391 case PIPE_FORMAT_R16G16B16X16_FLOAT:
392 case PIPE_FORMAT_R16G16B16X16_UINT:
393 case PIPE_FORMAT_R16G16B16X16_SINT:
394 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
395
396 /* 128-bit buffers. */
397 case PIPE_FORMAT_R32G32B32A32_FLOAT:
398 case PIPE_FORMAT_R32G32B32A32_SNORM:
399 case PIPE_FORMAT_R32G32B32A32_UNORM:
400 case PIPE_FORMAT_R32G32B32A32_SINT:
401 case PIPE_FORMAT_R32G32B32A32_UINT:
402 case PIPE_FORMAT_R32G32B32X32_FLOAT:
403 case PIPE_FORMAT_R32G32B32X32_UINT:
404 case PIPE_FORMAT_R32G32B32X32_SINT:
405 return V_028C70_SWAP_STD;
406 default:
407 R600_ERR("unsupported colorswap format %d\n", format);
408 return ~0U;
409 }
410 return ~0U;
411 }
412
413 static uint32_t r600_translate_colorformat(enum pipe_format format)
414 {
415 switch (format) {
416 /* 8-bit buffers. */
417 case PIPE_FORMAT_A8_UNORM:
418 case PIPE_FORMAT_A8_SNORM:
419 case PIPE_FORMAT_A8_UINT:
420 case PIPE_FORMAT_A8_SINT:
421 case PIPE_FORMAT_I8_UNORM:
422 case PIPE_FORMAT_I8_SNORM:
423 case PIPE_FORMAT_I8_UINT:
424 case PIPE_FORMAT_I8_SINT:
425 case PIPE_FORMAT_L8_UNORM:
426 case PIPE_FORMAT_L8_SNORM:
427 case PIPE_FORMAT_L8_UINT:
428 case PIPE_FORMAT_L8_SINT:
429 case PIPE_FORMAT_L8_SRGB:
430 case PIPE_FORMAT_R8_UNORM:
431 case PIPE_FORMAT_R8_SNORM:
432 case PIPE_FORMAT_R8_UINT:
433 case PIPE_FORMAT_R8_SINT:
434 return V_028C70_COLOR_8;
435
436 /* 16-bit buffers. */
437 case PIPE_FORMAT_B5G6R5_UNORM:
438 return V_028C70_COLOR_5_6_5;
439
440 case PIPE_FORMAT_B5G5R5A1_UNORM:
441 case PIPE_FORMAT_B5G5R5X1_UNORM:
442 return V_028C70_COLOR_1_5_5_5;
443
444 case PIPE_FORMAT_B4G4R4A4_UNORM:
445 case PIPE_FORMAT_B4G4R4X4_UNORM:
446 return V_028C70_COLOR_4_4_4_4;
447
448 case PIPE_FORMAT_Z16_UNORM:
449 return V_028C70_COLOR_16;
450
451 case PIPE_FORMAT_L8A8_UNORM:
452 case PIPE_FORMAT_L8A8_SNORM:
453 case PIPE_FORMAT_L8A8_UINT:
454 case PIPE_FORMAT_L8A8_SINT:
455 case PIPE_FORMAT_L8A8_SRGB:
456 case PIPE_FORMAT_R8G8_UNORM:
457 case PIPE_FORMAT_R8G8_SNORM:
458 case PIPE_FORMAT_R8G8_UINT:
459 case PIPE_FORMAT_R8G8_SINT:
460 case PIPE_FORMAT_R8A8_UNORM:
461 case PIPE_FORMAT_R8A8_SNORM:
462 case PIPE_FORMAT_R8A8_UINT:
463 case PIPE_FORMAT_R8A8_SINT:
464 return V_028C70_COLOR_8_8;
465
466 case PIPE_FORMAT_R16_UNORM:
467 case PIPE_FORMAT_R16_SNORM:
468 case PIPE_FORMAT_R16_UINT:
469 case PIPE_FORMAT_R16_SINT:
470 case PIPE_FORMAT_A16_UNORM:
471 case PIPE_FORMAT_A16_SNORM:
472 case PIPE_FORMAT_A16_UINT:
473 case PIPE_FORMAT_A16_SINT:
474 case PIPE_FORMAT_L16_UNORM:
475 case PIPE_FORMAT_L16_SNORM:
476 case PIPE_FORMAT_L16_UINT:
477 case PIPE_FORMAT_L16_SINT:
478 case PIPE_FORMAT_I16_UNORM:
479 case PIPE_FORMAT_I16_SNORM:
480 case PIPE_FORMAT_I16_UINT:
481 case PIPE_FORMAT_I16_SINT:
482 return V_028C70_COLOR_16;
483
484 case PIPE_FORMAT_R16_FLOAT:
485 case PIPE_FORMAT_A16_FLOAT:
486 case PIPE_FORMAT_L16_FLOAT:
487 case PIPE_FORMAT_I16_FLOAT:
488 return V_028C70_COLOR_16_FLOAT;
489
490 /* 32-bit buffers. */
491 case PIPE_FORMAT_A8B8G8R8_SRGB:
492 case PIPE_FORMAT_A8B8G8R8_UNORM:
493 case PIPE_FORMAT_A8R8G8B8_UNORM:
494 case PIPE_FORMAT_B8G8R8A8_SRGB:
495 case PIPE_FORMAT_B8G8R8A8_UNORM:
496 case PIPE_FORMAT_B8G8R8X8_UNORM:
497 case PIPE_FORMAT_R8G8B8A8_SNORM:
498 case PIPE_FORMAT_R8G8B8A8_UNORM:
499 case PIPE_FORMAT_R8G8B8X8_UNORM:
500 case PIPE_FORMAT_R8G8B8X8_SNORM:
501 case PIPE_FORMAT_R8G8B8X8_SRGB:
502 case PIPE_FORMAT_R8G8B8X8_UINT:
503 case PIPE_FORMAT_R8G8B8X8_SINT:
504 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
505 case PIPE_FORMAT_X8B8G8R8_UNORM:
506 case PIPE_FORMAT_X8R8G8B8_UNORM:
507 case PIPE_FORMAT_R8G8B8_UNORM:
508 case PIPE_FORMAT_R8G8B8A8_SINT:
509 case PIPE_FORMAT_R8G8B8A8_UINT:
510 return V_028C70_COLOR_8_8_8_8;
511
512 case PIPE_FORMAT_R10G10B10A2_UNORM:
513 case PIPE_FORMAT_R10G10B10X2_SNORM:
514 case PIPE_FORMAT_B10G10R10A2_UNORM:
515 case PIPE_FORMAT_B10G10R10A2_UINT:
516 case PIPE_FORMAT_B10G10R10X2_UNORM:
517 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
518 return V_028C70_COLOR_2_10_10_10;
519
520 case PIPE_FORMAT_Z24X8_UNORM:
521 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
522 return V_028C70_COLOR_8_24;
523
524 case PIPE_FORMAT_X8Z24_UNORM:
525 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
526 return V_028C70_COLOR_24_8;
527
528 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
529 return V_028C70_COLOR_X24_8_32_FLOAT;
530
531 case PIPE_FORMAT_R32_UINT:
532 case PIPE_FORMAT_R32_SINT:
533 case PIPE_FORMAT_A32_UINT:
534 case PIPE_FORMAT_A32_SINT:
535 case PIPE_FORMAT_L32_UINT:
536 case PIPE_FORMAT_L32_SINT:
537 case PIPE_FORMAT_I32_UINT:
538 case PIPE_FORMAT_I32_SINT:
539 return V_028C70_COLOR_32;
540
541 case PIPE_FORMAT_R32_FLOAT:
542 case PIPE_FORMAT_A32_FLOAT:
543 case PIPE_FORMAT_L32_FLOAT:
544 case PIPE_FORMAT_I32_FLOAT:
545 case PIPE_FORMAT_Z32_FLOAT:
546 return V_028C70_COLOR_32_FLOAT;
547
548 case PIPE_FORMAT_R16G16_FLOAT:
549 case PIPE_FORMAT_L16A16_FLOAT:
550 case PIPE_FORMAT_R16A16_FLOAT:
551 return V_028C70_COLOR_16_16_FLOAT;
552
553 case PIPE_FORMAT_R16G16_UNORM:
554 case PIPE_FORMAT_R16G16_SNORM:
555 case PIPE_FORMAT_R16G16_UINT:
556 case PIPE_FORMAT_R16G16_SINT:
557 case PIPE_FORMAT_L16A16_UNORM:
558 case PIPE_FORMAT_L16A16_SNORM:
559 case PIPE_FORMAT_L16A16_UINT:
560 case PIPE_FORMAT_L16A16_SINT:
561 case PIPE_FORMAT_R16A16_UNORM:
562 case PIPE_FORMAT_R16A16_SNORM:
563 case PIPE_FORMAT_R16A16_UINT:
564 case PIPE_FORMAT_R16A16_SINT:
565 return V_028C70_COLOR_16_16;
566
567 case PIPE_FORMAT_R11G11B10_FLOAT:
568 return V_028C70_COLOR_10_11_11_FLOAT;
569
570 /* 64-bit buffers. */
571 case PIPE_FORMAT_R16G16B16A16_UINT:
572 case PIPE_FORMAT_R16G16B16A16_SINT:
573 case PIPE_FORMAT_R16G16B16A16_UNORM:
574 case PIPE_FORMAT_R16G16B16A16_SNORM:
575 case PIPE_FORMAT_R16G16B16X16_UNORM:
576 case PIPE_FORMAT_R16G16B16X16_SNORM:
577 case PIPE_FORMAT_R16G16B16X16_UINT:
578 case PIPE_FORMAT_R16G16B16X16_SINT:
579 return V_028C70_COLOR_16_16_16_16;
580
581 case PIPE_FORMAT_R16G16B16A16_FLOAT:
582 case PIPE_FORMAT_R16G16B16X16_FLOAT:
583 return V_028C70_COLOR_16_16_16_16_FLOAT;
584
585 case PIPE_FORMAT_R32G32_FLOAT:
586 case PIPE_FORMAT_L32A32_FLOAT:
587 case PIPE_FORMAT_R32A32_FLOAT:
588 return V_028C70_COLOR_32_32_FLOAT;
589
590 case PIPE_FORMAT_R32G32_SINT:
591 case PIPE_FORMAT_R32G32_UINT:
592 case PIPE_FORMAT_L32A32_UINT:
593 case PIPE_FORMAT_L32A32_SINT:
594 return V_028C70_COLOR_32_32;
595
596 /* 128-bit buffers. */
597 case PIPE_FORMAT_R32G32B32A32_SNORM:
598 case PIPE_FORMAT_R32G32B32A32_UNORM:
599 case PIPE_FORMAT_R32G32B32A32_SINT:
600 case PIPE_FORMAT_R32G32B32A32_UINT:
601 case PIPE_FORMAT_R32G32B32X32_UINT:
602 case PIPE_FORMAT_R32G32B32X32_SINT:
603 return V_028C70_COLOR_32_32_32_32;
604 case PIPE_FORMAT_R32G32B32A32_FLOAT:
605 case PIPE_FORMAT_R32G32B32X32_FLOAT:
606 return V_028C70_COLOR_32_32_32_32_FLOAT;
607
608 /* YUV buffers. */
609 case PIPE_FORMAT_UYVY:
610 case PIPE_FORMAT_YUYV:
611 default:
612 return ~0U; /* Unsupported. */
613 }
614 }
615
616 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
617 {
618 if (R600_BIG_ENDIAN) {
619 switch(colorformat) {
620
621 /* 8-bit buffers. */
622 case V_028C70_COLOR_8:
623 return ENDIAN_NONE;
624
625 /* 16-bit buffers. */
626 case V_028C70_COLOR_5_6_5:
627 case V_028C70_COLOR_1_5_5_5:
628 case V_028C70_COLOR_4_4_4_4:
629 case V_028C70_COLOR_16:
630 case V_028C70_COLOR_8_8:
631 return ENDIAN_8IN16;
632
633 /* 32-bit buffers. */
634 case V_028C70_COLOR_8_8_8_8:
635 case V_028C70_COLOR_2_10_10_10:
636 case V_028C70_COLOR_8_24:
637 case V_028C70_COLOR_24_8:
638 case V_028C70_COLOR_32_FLOAT:
639 case V_028C70_COLOR_16_16_FLOAT:
640 case V_028C70_COLOR_16_16:
641 return ENDIAN_8IN32;
642
643 /* 64-bit buffers. */
644 case V_028C70_COLOR_16_16_16_16:
645 case V_028C70_COLOR_16_16_16_16_FLOAT:
646 return ENDIAN_8IN16;
647
648 case V_028C70_COLOR_32_32_FLOAT:
649 case V_028C70_COLOR_32_32:
650 case V_028C70_COLOR_X24_8_32_FLOAT:
651 return ENDIAN_8IN32;
652
653 /* 96-bit buffers. */
654 case V_028C70_COLOR_32_32_32_FLOAT:
655 /* 128-bit buffers. */
656 case V_028C70_COLOR_32_32_32_32_FLOAT:
657 case V_028C70_COLOR_32_32_32_32:
658 return ENDIAN_8IN32;
659 default:
660 return ENDIAN_NONE; /* Unsupported. */
661 }
662 } else {
663 return ENDIAN_NONE;
664 }
665 }
666
667 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
668 {
669 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
670 }
671
672 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
673 {
674 return r600_translate_colorformat(format) != ~0U &&
675 r600_translate_colorswap(format) != ~0U;
676 }
677
678 static bool r600_is_zs_format_supported(enum pipe_format format)
679 {
680 return r600_translate_dbformat(format) != ~0U;
681 }
682
683 boolean evergreen_is_format_supported(struct pipe_screen *screen,
684 enum pipe_format format,
685 enum pipe_texture_target target,
686 unsigned sample_count,
687 unsigned usage)
688 {
689 struct r600_screen *rscreen = (struct r600_screen*)screen;
690 unsigned retval = 0;
691
692 if (target >= PIPE_MAX_TEXTURE_TYPES) {
693 R600_ERR("r600: unsupported texture type %d\n", target);
694 return FALSE;
695 }
696
697 if (!util_format_is_supported(format, usage))
698 return FALSE;
699
700 if (sample_count > 1) {
701 if (!rscreen->has_msaa)
702 return FALSE;
703
704 switch (sample_count) {
705 case 2:
706 case 4:
707 case 8:
708 break;
709 default:
710 return FALSE;
711 }
712 }
713
714 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
715 r600_is_sampler_format_supported(screen, format)) {
716 retval |= PIPE_BIND_SAMPLER_VIEW;
717 }
718
719 if ((usage & (PIPE_BIND_RENDER_TARGET |
720 PIPE_BIND_DISPLAY_TARGET |
721 PIPE_BIND_SCANOUT |
722 PIPE_BIND_SHARED)) &&
723 r600_is_colorbuffer_format_supported(format)) {
724 retval |= usage &
725 (PIPE_BIND_RENDER_TARGET |
726 PIPE_BIND_DISPLAY_TARGET |
727 PIPE_BIND_SCANOUT |
728 PIPE_BIND_SHARED);
729 }
730
731 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
732 r600_is_zs_format_supported(format)) {
733 retval |= PIPE_BIND_DEPTH_STENCIL;
734 }
735
736 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
737 r600_is_vertex_format_supported(format)) {
738 retval |= PIPE_BIND_VERTEX_BUFFER;
739 }
740
741 if (usage & PIPE_BIND_TRANSFER_READ)
742 retval |= PIPE_BIND_TRANSFER_READ;
743 if (usage & PIPE_BIND_TRANSFER_WRITE)
744 retval |= PIPE_BIND_TRANSFER_WRITE;
745
746 return retval == usage;
747 }
748
749 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
750 const struct pipe_blend_state *state, int mode)
751 {
752 uint32_t color_control = 0, target_mask = 0;
753 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
754
755 if (!blend) {
756 return NULL;
757 }
758
759 r600_init_command_buffer(&blend->buffer, 20);
760 r600_init_command_buffer(&blend->buffer_no_blend, 20);
761
762 if (state->logicop_enable) {
763 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
764 } else {
765 color_control |= (0xcc << 16);
766 }
767 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
768 if (state->independent_blend_enable) {
769 for (int i = 0; i < 8; i++) {
770 target_mask |= (state->rt[i].colormask << (4 * i));
771 }
772 } else {
773 for (int i = 0; i < 8; i++) {
774 target_mask |= (state->rt[0].colormask << (4 * i));
775 }
776 }
777
778 /* only have dual source on MRT0 */
779 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
780 blend->cb_target_mask = target_mask;
781 blend->alpha_to_one = state->alpha_to_one;
782
783 if (target_mask)
784 color_control |= S_028808_MODE(mode);
785 else
786 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
787
788
789 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
790 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
791 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
792 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
793 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
794 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
795 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
796 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
797
798 /* Copy over the dwords set so far into buffer_no_blend.
799 * Only the CB_BLENDi_CONTROL registers must be set after this. */
800 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
801 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
802
803 for (int i = 0; i < 8; i++) {
804 /* state->rt entries > 0 only written if independent blending */
805 const int j = state->independent_blend_enable ? i : 0;
806
807 unsigned eqRGB = state->rt[j].rgb_func;
808 unsigned srcRGB = state->rt[j].rgb_src_factor;
809 unsigned dstRGB = state->rt[j].rgb_dst_factor;
810 unsigned eqA = state->rt[j].alpha_func;
811 unsigned srcA = state->rt[j].alpha_src_factor;
812 unsigned dstA = state->rt[j].alpha_dst_factor;
813 uint32_t bc = 0;
814
815 r600_store_value(&blend->buffer_no_blend, 0);
816
817 if (!state->rt[j].blend_enable) {
818 r600_store_value(&blend->buffer, 0);
819 continue;
820 }
821
822 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
823 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
824 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
825 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
826
827 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
828 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
829 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
830 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
831 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
832 }
833 r600_store_value(&blend->buffer, bc);
834 }
835 return blend;
836 }
837
838 static void *evergreen_create_blend_state(struct pipe_context *ctx,
839 const struct pipe_blend_state *state)
840 {
841
842 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
843 }
844
845 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
846 const struct pipe_depth_stencil_alpha_state *state)
847 {
848 unsigned db_depth_control, alpha_test_control, alpha_ref;
849 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
850
851 if (dsa == NULL) {
852 return NULL;
853 }
854
855 r600_init_command_buffer(&dsa->buffer, 3);
856
857 dsa->valuemask[0] = state->stencil[0].valuemask;
858 dsa->valuemask[1] = state->stencil[1].valuemask;
859 dsa->writemask[0] = state->stencil[0].writemask;
860 dsa->writemask[1] = state->stencil[1].writemask;
861 dsa->zwritemask = state->depth.writemask;
862
863 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
864 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
865 S_028800_ZFUNC(state->depth.func);
866
867 /* stencil */
868 if (state->stencil[0].enabled) {
869 db_depth_control |= S_028800_STENCIL_ENABLE(1);
870 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
871 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
872 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
873 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
874
875 if (state->stencil[1].enabled) {
876 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
877 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
878 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
879 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
880 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
881 }
882 }
883
884 /* alpha */
885 alpha_test_control = 0;
886 alpha_ref = 0;
887 if (state->alpha.enabled) {
888 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
889 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
890 alpha_ref = fui(state->alpha.ref_value);
891 }
892 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
893 dsa->alpha_ref = alpha_ref;
894
895 /* misc */
896 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
897 return dsa;
898 }
899
900 static void *evergreen_create_rs_state(struct pipe_context *ctx,
901 const struct pipe_rasterizer_state *state)
902 {
903 struct r600_context *rctx = (struct r600_context *)ctx;
904 unsigned tmp, spi_interp;
905 float psize_min, psize_max;
906 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
907
908 if (rs == NULL) {
909 return NULL;
910 }
911
912 r600_init_command_buffer(&rs->buffer, 30);
913
914 rs->flatshade = state->flatshade;
915 rs->sprite_coord_enable = state->sprite_coord_enable;
916 rs->two_side = state->light_twoside;
917 rs->clip_plane_enable = state->clip_plane_enable;
918 rs->pa_sc_line_stipple = state->line_stipple_enable ?
919 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
920 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
921 rs->pa_cl_clip_cntl =
922 S_028810_PS_UCP_MODE(3) |
923 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
924 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
925 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
926 rs->multisample_enable = state->multisample;
927
928 /* offset */
929 rs->offset_units = state->offset_units;
930 rs->offset_scale = state->offset_scale * 12.0f;
931 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
932
933 if (state->point_size_per_vertex) {
934 psize_min = util_get_min_point_size(state);
935 psize_max = 8192;
936 } else {
937 /* Force the point size to be as if the vertex output was disabled. */
938 psize_min = state->point_size;
939 psize_max = state->point_size;
940 }
941
942 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
943 if (state->sprite_coord_enable) {
944 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
945 S_0286D4_PNT_SPRITE_OVRD_X(2) |
946 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
947 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
948 S_0286D4_PNT_SPRITE_OVRD_W(1);
949 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
950 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
951 }
952 }
953
954 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
955 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
956 tmp = r600_pack_float_12p4(state->point_size/2);
957 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
958 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
959 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
960 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
961 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
962 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
963 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
964
965 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
966 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
967 S_028A48_MSAA_ENABLE(state->multisample) |
968 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
969 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
970
971 if (rctx->b.chip_class == CAYMAN) {
972 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
973 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
974 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
975 } else {
976 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
977 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
978 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
979 }
980
981 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
982 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
983 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
984 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
985 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
986 S_028814_FACE(!state->front_ccw) |
987 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
988 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
989 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
990 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
991 state->fill_back != PIPE_POLYGON_MODE_FILL) |
992 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
993 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
994 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
995 return rs;
996 }
997
998 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
999 const struct pipe_sampler_state *state)
1000 {
1001 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
1002 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
1003
1004 if (ss == NULL) {
1005 return NULL;
1006 }
1007
1008 ss->border_color_use = sampler_state_needs_border_color(state);
1009
1010 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
1011 ss->tex_sampler_words[0] =
1012 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1013 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1014 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1015 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1016 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1017 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1018 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1019 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1020 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
1021 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
1022 ss->tex_sampler_words[1] =
1023 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
1024 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
1025 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
1026 ss->tex_sampler_words[2] =
1027 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
1028 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
1029 S_03C008_TYPE(1);
1030
1031 if (ss->border_color_use) {
1032 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
1033 }
1034 return ss;
1035 }
1036
1037 static struct pipe_sampler_view *
1038 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
1039 unsigned width0, unsigned height0)
1040
1041 {
1042 struct pipe_context *ctx = view->base.context;
1043 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
1044 uint64_t va;
1045 int stride = util_format_get_blocksize(view->base.format);
1046 unsigned format, num_format, format_comp, endian;
1047 unsigned swizzle_res;
1048 unsigned char swizzle[4];
1049 const struct util_format_description *desc;
1050 unsigned offset = view->base.u.buf.first_element * stride;
1051 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
1052
1053 swizzle[0] = view->base.swizzle_r;
1054 swizzle[1] = view->base.swizzle_g;
1055 swizzle[2] = view->base.swizzle_b;
1056 swizzle[3] = view->base.swizzle_a;
1057
1058 r600_vertex_data_type(view->base.format,
1059 &format, &num_format, &format_comp,
1060 &endian);
1061
1062 desc = util_format_description(view->base.format);
1063
1064 swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
1065
1066 va = r600_resource_va(ctx->screen, view->base.texture) + offset;
1067 view->tex_resource = &tmp->resource;
1068
1069 view->skip_mip_address_reloc = true;
1070 view->tex_resource_words[0] = va;
1071 view->tex_resource_words[1] = size - 1;
1072 view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
1073 S_030008_STRIDE(stride) |
1074 S_030008_DATA_FORMAT(format) |
1075 S_030008_NUM_FORMAT_ALL(num_format) |
1076 S_030008_FORMAT_COMP_ALL(format_comp) |
1077 S_030008_SRF_MODE_ALL(1) |
1078 S_030008_ENDIAN_SWAP(endian);
1079 view->tex_resource_words[3] = swizzle_res;
1080 /*
1081 * in theory dword 4 is for number of elements, for use with resinfo,
1082 * but it seems to utterly fail to work, the amd gpu shader analyser
1083 * uses a const buffer to store the element sizes for buffer txq
1084 */
1085 view->tex_resource_words[4] = 0;
1086 view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
1087 view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
1088 return &view->base;
1089 }
1090
1091 struct pipe_sampler_view *
1092 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
1093 struct pipe_resource *texture,
1094 const struct pipe_sampler_view *state,
1095 unsigned width0, unsigned height0)
1096 {
1097 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
1098 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1099 struct r600_texture *tmp = (struct r600_texture*)texture;
1100 unsigned format, endian;
1101 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1102 unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
1103 unsigned height, depth, width;
1104 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
1105 enum pipe_format pipe_format = state->format;
1106 struct radeon_surface_level *surflevel;
1107
1108 if (view == NULL)
1109 return NULL;
1110
1111 /* initialize base object */
1112 view->base = *state;
1113 view->base.texture = NULL;
1114 pipe_reference(NULL, &texture->reference);
1115 view->base.texture = texture;
1116 view->base.reference.count = 1;
1117 view->base.context = ctx;
1118
1119 if (texture->target == PIPE_BUFFER)
1120 return texture_buffer_sampler_view(view, width0, height0);
1121
1122 swizzle[0] = state->swizzle_r;
1123 swizzle[1] = state->swizzle_g;
1124 swizzle[2] = state->swizzle_b;
1125 swizzle[3] = state->swizzle_a;
1126
1127 tile_split = tmp->surface.tile_split;
1128 surflevel = tmp->surface.level;
1129
1130 /* Texturing with separate depth and stencil. */
1131 if (tmp->is_depth && !tmp->is_flushing_texture) {
1132 switch (pipe_format) {
1133 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1134 pipe_format = PIPE_FORMAT_Z32_FLOAT;
1135 break;
1136 case PIPE_FORMAT_X8Z24_UNORM:
1137 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1138 /* Z24 is always stored like this. */
1139 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
1140 break;
1141 case PIPE_FORMAT_X24S8_UINT:
1142 case PIPE_FORMAT_S8X24_UINT:
1143 case PIPE_FORMAT_X32_S8X24_UINT:
1144 pipe_format = PIPE_FORMAT_S8_UINT;
1145 tile_split = tmp->surface.stencil_tile_split;
1146 surflevel = tmp->surface.stencil_level;
1147 break;
1148 default:;
1149 }
1150 }
1151
1152 format = r600_translate_texformat(ctx->screen, pipe_format,
1153 swizzle,
1154 &word4, &yuv_format);
1155 assert(format != ~0);
1156 if (format == ~0) {
1157 FREE(view);
1158 return NULL;
1159 }
1160
1161 endian = r600_colorformat_endian_swap(format);
1162
1163 width = width0;
1164 height = height0;
1165 depth = texture->depth0;
1166 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
1167 non_disp_tiling = tmp->non_disp_tiling;
1168
1169 switch (surflevel[0].mode) {
1170 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1171 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1172 break;
1173 case RADEON_SURF_MODE_2D:
1174 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1175 break;
1176 case RADEON_SURF_MODE_1D:
1177 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1178 break;
1179 case RADEON_SURF_MODE_LINEAR:
1180 default:
1181 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1182 break;
1183 }
1184 macro_aspect = tmp->surface.mtilea;
1185 bankw = tmp->surface.bankw;
1186 bankh = tmp->surface.bankh;
1187 tile_split = eg_tile_split(tile_split);
1188 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1189 bankw = eg_bank_wh(bankw);
1190 bankh = eg_bank_wh(bankh);
1191 fmask_bankh = eg_bank_wh(tmp->fmask_bank_height);
1192
1193 /* 128 bit formats require tile type = 1 */
1194 if (rscreen->b.chip_class == CAYMAN) {
1195 if (util_format_get_blocksize(pipe_format) >= 16)
1196 non_disp_tiling = 1;
1197 }
1198 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1199
1200 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1201 height = 1;
1202 depth = texture->array_size;
1203 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1204 depth = texture->array_size;
1205 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
1206 depth = texture->array_size / 6;
1207
1208 view->tex_resource = &tmp->resource;
1209 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1210 S_030000_PITCH((pitch / 8) - 1) |
1211 S_030000_TEX_WIDTH(width - 1));
1212 if (rscreen->b.chip_class == CAYMAN)
1213 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
1214 else
1215 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
1216 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1217 S_030004_TEX_DEPTH(depth - 1) |
1218 S_030004_ARRAY_MODE(array_mode));
1219 view->tex_resource_words[2] = (surflevel[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1220
1221 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
1222 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
1223 if (tmp->is_depth) {
1224 /* disable FMASK (0 = disabled) */
1225 view->tex_resource_words[3] = 0;
1226 view->skip_mip_address_reloc = true;
1227 } else {
1228 /* FMASK should be in MIP_ADDRESS for multisample textures */
1229 view->tex_resource_words[3] = (tmp->fmask_offset + r600_resource_va(ctx->screen, texture)) >> 8;
1230 }
1231 } else if (state->u.tex.last_level && texture->nr_samples <= 1) {
1232 view->tex_resource_words[3] = (surflevel[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1233 } else {
1234 view->tex_resource_words[3] = (surflevel[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1235 }
1236
1237 view->tex_resource_words[4] = (word4 |
1238 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1239 S_030010_ENDIAN_SWAP(endian));
1240 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1241 S_030014_LAST_ARRAY(state->u.tex.last_layer);
1242 view->tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
1243
1244 if (texture->nr_samples > 1) {
1245 unsigned log_samples = util_logbase2(texture->nr_samples);
1246 if (rscreen->b.chip_class == CAYMAN) {
1247 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
1248 }
1249 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1250 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
1251 view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
1252 } else {
1253 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(state->u.tex.first_level);
1254 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(state->u.tex.last_level);
1255 /* aniso max 16 samples */
1256 view->tex_resource_words[6] |= S_030018_MAX_ANISO(4);
1257 }
1258
1259 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1260 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1261 S_03001C_BANK_WIDTH(bankw) |
1262 S_03001C_BANK_HEIGHT(bankh) |
1263 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1264 S_03001C_NUM_BANKS(nbanks) |
1265 S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
1266 return &view->base;
1267 }
1268
1269 static struct pipe_sampler_view *
1270 evergreen_create_sampler_view(struct pipe_context *ctx,
1271 struct pipe_resource *tex,
1272 const struct pipe_sampler_view *state)
1273 {
1274 return evergreen_create_sampler_view_custom(ctx, tex, state,
1275 tex->width0, tex->height0);
1276 }
1277
1278 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1279 {
1280 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1281 struct pipe_clip_state *state = &rctx->clip_state.state;
1282
1283 r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
1284 radeon_emit_array(cs, (unsigned*)state, 6*4);
1285 }
1286
1287 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1288 const struct pipe_poly_stipple *state)
1289 {
1290 }
1291
1292 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1293 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1294 uint32_t *tl, uint32_t *br)
1295 {
1296 /* EG hw workaround */
1297 if (br_x == 0)
1298 tl_x = 1;
1299 if (br_y == 0)
1300 tl_y = 1;
1301
1302 /* cayman hw workaround */
1303 if (rctx->b.chip_class == CAYMAN) {
1304 if (br_x == 1 && br_y == 1)
1305 br_x = 2;
1306 }
1307
1308 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1309 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1310 }
1311
1312 static void evergreen_set_scissor_states(struct pipe_context *ctx,
1313 unsigned start_slot,
1314 unsigned num_scissors,
1315 const struct pipe_scissor_state *state)
1316 {
1317 struct r600_context *rctx = (struct r600_context *)ctx;
1318
1319 rctx->scissor.scissor = *state;
1320 rctx->scissor.atom.dirty = true;
1321 }
1322
1323 static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
1324 {
1325 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1326 struct pipe_scissor_state *state = &rctx->scissor.scissor;
1327 uint32_t tl, br;
1328
1329 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1330
1331 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1332 radeon_emit(cs, tl);
1333 radeon_emit(cs, br);
1334 }
1335
1336 /**
1337 * This function intializes the CB* register values for RATs. It is meant
1338 * to be used for 1D aligned buffers that do not have an associated
1339 * radeon_surface.
1340 */
1341 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1342 struct r600_surface *surf)
1343 {
1344 struct pipe_resource *pipe_buffer = surf->base.texture;
1345 unsigned format = r600_translate_colorformat(surf->base.format);
1346 unsigned endian = r600_colorformat_endian_swap(format);
1347 unsigned swap = r600_translate_colorswap(surf->base.format);
1348 unsigned block_size =
1349 align(util_format_get_blocksize(pipe_buffer->format), 4);
1350 unsigned pitch_alignment =
1351 MAX2(64, rctx->screen->tiling_info.group_bytes / block_size);
1352 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
1353
1354 /* XXX: This is copied from evergreen_init_color_surface(). I don't
1355 * know why this is necessary.
1356 */
1357 if (pipe_buffer->usage == PIPE_USAGE_STAGING) {
1358 endian = ENDIAN_NONE;
1359 }
1360
1361 surf->cb_color_base =
1362 r600_resource_va(rctx->b.b.screen, pipe_buffer) >> 8;
1363
1364 surf->cb_color_pitch = (pitch / 8) - 1;
1365
1366 surf->cb_color_slice = 0;
1367
1368 surf->cb_color_view = 0;
1369
1370 surf->cb_color_info =
1371 S_028C70_ENDIAN(endian)
1372 | S_028C70_FORMAT(format)
1373 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
1374 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
1375 | S_028C70_COMP_SWAP(swap)
1376 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
1377 * are using NUMBER_UINT */
1378 | S_028C70_RAT(1)
1379 ;
1380
1381 surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1382
1383 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
1384 * elements. */
1385 surf->cb_color_dim = pipe_buffer->width0;
1386
1387 /* Set the buffer range the GPU will have access to: */
1388 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
1389 0, pipe_buffer->width0);
1390
1391 surf->cb_color_cmask = surf->cb_color_base;
1392 surf->cb_color_cmask_slice = 0;
1393 surf->cb_color_fmask = surf->cb_color_base;
1394 surf->cb_color_fmask_slice = 0;
1395 }
1396
1397 void evergreen_init_color_surface(struct r600_context *rctx,
1398 struct r600_surface *surf)
1399 {
1400 struct r600_screen *rscreen = rctx->screen;
1401 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1402 struct pipe_resource *pipe_tex = surf->base.texture;
1403 unsigned level = surf->base.u.tex.level;
1404 unsigned pitch, slice;
1405 unsigned color_info, color_attrib, color_dim = 0;
1406 unsigned format, swap, ntype, endian;
1407 uint64_t offset, base_offset;
1408 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1409 const struct util_format_description *desc;
1410 int i;
1411 bool blend_clamp = 0, blend_bypass = 0;
1412
1413 offset = rtex->surface.level[level].offset;
1414 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1415 offset += rtex->surface.level[level].slice_size *
1416 surf->base.u.tex.first_layer;
1417 }
1418 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1419 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1420 if (slice) {
1421 slice = slice - 1;
1422 }
1423 color_info = 0;
1424 switch (rtex->surface.level[level].mode) {
1425 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1426 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1427 non_disp_tiling = 1;
1428 break;
1429 case RADEON_SURF_MODE_1D:
1430 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1431 non_disp_tiling = rtex->non_disp_tiling;
1432 break;
1433 case RADEON_SURF_MODE_2D:
1434 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1435 non_disp_tiling = rtex->non_disp_tiling;
1436 break;
1437 case RADEON_SURF_MODE_LINEAR:
1438 default:
1439 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1440 non_disp_tiling = 1;
1441 break;
1442 }
1443 tile_split = rtex->surface.tile_split;
1444 macro_aspect = rtex->surface.mtilea;
1445 bankw = rtex->surface.bankw;
1446 bankh = rtex->surface.bankh;
1447 fmask_bankh = rtex->fmask_bank_height;
1448 tile_split = eg_tile_split(tile_split);
1449 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1450 bankw = eg_bank_wh(bankw);
1451 bankh = eg_bank_wh(bankh);
1452 fmask_bankh = eg_bank_wh(fmask_bankh);
1453
1454 /* 128 bit formats require tile type = 1 */
1455 if (rscreen->b.chip_class == CAYMAN) {
1456 if (util_format_get_blocksize(surf->base.format) >= 16)
1457 non_disp_tiling = 1;
1458 }
1459 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1460 desc = util_format_description(surf->base.format);
1461 for (i = 0; i < 4; i++) {
1462 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1463 break;
1464 }
1465 }
1466
1467 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1468 S_028C74_NUM_BANKS(nbanks) |
1469 S_028C74_BANK_WIDTH(bankw) |
1470 S_028C74_BANK_HEIGHT(bankh) |
1471 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1472 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1473 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1474
1475 if (rctx->b.chip_class == CAYMAN) {
1476 color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1477 UTIL_FORMAT_SWIZZLE_1);
1478
1479 if (rtex->resource.b.b.nr_samples > 1) {
1480 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1481 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1482 S_028C74_NUM_FRAGMENTS(log_samples);
1483 }
1484 }
1485
1486 ntype = V_028C70_NUMBER_UNORM;
1487 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1488 ntype = V_028C70_NUMBER_SRGB;
1489 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1490 if (desc->channel[i].normalized)
1491 ntype = V_028C70_NUMBER_SNORM;
1492 else if (desc->channel[i].pure_integer)
1493 ntype = V_028C70_NUMBER_SINT;
1494 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1495 if (desc->channel[i].normalized)
1496 ntype = V_028C70_NUMBER_UNORM;
1497 else if (desc->channel[i].pure_integer)
1498 ntype = V_028C70_NUMBER_UINT;
1499 }
1500
1501 format = r600_translate_colorformat(surf->base.format);
1502 assert(format != ~0);
1503
1504 swap = r600_translate_colorswap(surf->base.format);
1505 assert(swap != ~0);
1506
1507 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1508 endian = ENDIAN_NONE;
1509 } else {
1510 endian = r600_colorformat_endian_swap(format);
1511 }
1512
1513 /* blend clamp should be set for all NORM/SRGB types */
1514 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1515 ntype == V_028C70_NUMBER_SRGB)
1516 blend_clamp = 1;
1517
1518 /* set blend bypass according to docs if SINT/UINT or
1519 8/24 COLOR variants */
1520 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1521 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1522 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1523 blend_clamp = 0;
1524 blend_bypass = 1;
1525 }
1526
1527 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1528
1529 color_info |= S_028C70_FORMAT(format) |
1530 S_028C70_COMP_SWAP(swap) |
1531 S_028C70_BLEND_CLAMP(blend_clamp) |
1532 S_028C70_BLEND_BYPASS(blend_bypass) |
1533 S_028C70_NUMBER_TYPE(ntype) |
1534 S_028C70_ENDIAN(endian);
1535
1536 if (rtex->is_rat) {
1537 color_info |= S_028C70_RAT(1);
1538 color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0 & 0xffff)
1539 | S_028C78_HEIGHT_MAX((pipe_tex->width0 >> 16) & 0xffff);
1540 }
1541
1542 /* EXPORT_NORM is an optimzation that can be enabled for better
1543 * performance in certain cases.
1544 * EXPORT_NORM can be enabled if:
1545 * - 11-bit or smaller UNORM/SNORM/SRGB
1546 * - 16-bit or smaller FLOAT
1547 */
1548 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1549 ((desc->channel[i].size < 12 &&
1550 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1551 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1552 (desc->channel[i].size < 17 &&
1553 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1554 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1555 surf->export_16bpc = true;
1556 }
1557
1558 if (rtex->fmask_size) {
1559 color_info |= S_028C70_COMPRESSION(1);
1560 }
1561 if (rtex->cmask_size) {
1562 color_info |= S_028C70_FAST_CLEAR(1);
1563 }
1564
1565 base_offset = r600_resource_va(rctx->b.b.screen, pipe_tex);
1566
1567 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1568 surf->cb_color_base = (base_offset + offset) >> 8;
1569 surf->cb_color_dim = color_dim;
1570 surf->cb_color_info = color_info;
1571 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1572 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1573 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1574 surf->cb_color_view = 0;
1575 } else {
1576 surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1577 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1578 }
1579 surf->cb_color_attrib = color_attrib;
1580 if (rtex->fmask_size) {
1581 surf->cb_color_fmask = (base_offset + rtex->fmask_offset) >> 8;
1582 } else {
1583 surf->cb_color_fmask = surf->cb_color_base;
1584 }
1585 if (rtex->cmask_size) {
1586 uint64_t va = r600_resource_va(rctx->b.b.screen, &rtex->cmask->b.b);
1587 surf->cb_color_cmask = (va + rtex->cmask_offset) >> 8;
1588 } else {
1589 surf->cb_color_cmask = surf->cb_color_base;
1590 }
1591 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask_slice_tile_max);
1592 surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask_slice_tile_max);
1593
1594 surf->color_initialized = true;
1595 }
1596
1597 static void evergreen_init_depth_surface(struct r600_context *rctx,
1598 struct r600_surface *surf)
1599 {
1600 struct r600_screen *rscreen = rctx->screen;
1601 struct pipe_screen *screen = &rscreen->b.b;
1602 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1603 uint64_t offset;
1604 unsigned level, pitch, slice, format, array_mode;
1605 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1606
1607 level = surf->base.u.tex.level;
1608 format = r600_translate_dbformat(surf->base.format);
1609 assert(format != ~0);
1610
1611 offset = r600_resource_va(screen, surf->base.texture);
1612 offset += rtex->surface.level[level].offset;
1613 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1614 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1615 if (slice) {
1616 slice = slice - 1;
1617 }
1618 switch (rtex->surface.level[level].mode) {
1619 case RADEON_SURF_MODE_2D:
1620 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1621 break;
1622 case RADEON_SURF_MODE_1D:
1623 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1624 case RADEON_SURF_MODE_LINEAR:
1625 default:
1626 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1627 break;
1628 }
1629 tile_split = rtex->surface.tile_split;
1630 macro_aspect = rtex->surface.mtilea;
1631 bankw = rtex->surface.bankw;
1632 bankh = rtex->surface.bankh;
1633 tile_split = eg_tile_split(tile_split);
1634 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1635 bankw = eg_bank_wh(bankw);
1636 bankh = eg_bank_wh(bankh);
1637 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1638 offset >>= 8;
1639
1640 surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1641 S_028040_FORMAT(format) |
1642 S_028040_TILE_SPLIT(tile_split)|
1643 S_028040_NUM_BANKS(nbanks) |
1644 S_028040_BANK_WIDTH(bankw) |
1645 S_028040_BANK_HEIGHT(bankh) |
1646 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1647 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1648 surf->db_depth_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1649 }
1650 surf->db_depth_base = offset;
1651 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1652 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1653 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1654 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1655
1656 switch (surf->base.format) {
1657 case PIPE_FORMAT_Z24X8_UNORM:
1658 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1659 case PIPE_FORMAT_X8Z24_UNORM:
1660 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1661 surf->pa_su_poly_offset_db_fmt_cntl =
1662 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1663 break;
1664 case PIPE_FORMAT_Z32_FLOAT:
1665 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1666 surf->pa_su_poly_offset_db_fmt_cntl =
1667 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1668 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1669 break;
1670 case PIPE_FORMAT_Z16_UNORM:
1671 surf->pa_su_poly_offset_db_fmt_cntl =
1672 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1673 break;
1674 default:;
1675 }
1676
1677 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1678 uint64_t stencil_offset;
1679 unsigned stile_split = rtex->surface.stencil_tile_split;
1680
1681 stile_split = eg_tile_split(stile_split);
1682
1683 stencil_offset = rtex->surface.stencil_level[level].offset;
1684 stencil_offset += r600_resource_va(screen, surf->base.texture);
1685
1686 surf->db_stencil_base = stencil_offset >> 8;
1687 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1688 S_028044_TILE_SPLIT(stile_split);
1689 } else {
1690 surf->db_stencil_base = offset;
1691 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1692 * Older kernels are out of luck. */
1693 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1694 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1695 S_028044_FORMAT(V_028044_STENCIL_8);
1696 }
1697
1698 surf->htile_enabled = 0;
1699 /* use htile only for first level */
1700 if (rtex->htile && !level) {
1701 uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile->b.b);
1702 surf->htile_enabled = 1;
1703 surf->db_htile_data_base = va >> 8;
1704 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1705 S_028ABC_HTILE_HEIGHT(1) |
1706 S_028ABC_FULL_CACHE(1) |
1707 S_028ABC_LINEAR(1);
1708 surf->db_depth_info |= S_028040_TILE_SURFACE_ENABLE(1);
1709 surf->db_preload_control = 0;
1710 }
1711
1712 surf->depth_initialized = true;
1713 }
1714
1715 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1716 const struct pipe_framebuffer_state *state)
1717 {
1718 struct r600_context *rctx = (struct r600_context *)ctx;
1719 struct r600_surface *surf;
1720 struct r600_texture *rtex;
1721 uint32_t i, log_samples;
1722
1723 if (rctx->framebuffer.state.nr_cbufs) {
1724 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1725 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB;
1726
1727 if (rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1728 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1729 }
1730 }
1731 if (rctx->framebuffer.state.zsbuf) {
1732 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1733 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1734
1735 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1736 if (rtex->htile) {
1737 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1738 }
1739 }
1740
1741 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1742
1743 /* Colorbuffers. */
1744 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1745 rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1746 util_format_is_pure_integer(state->cbufs[0]->format);
1747 rctx->framebuffer.compressed_cb_mask = 0;
1748
1749 if (state->nr_cbufs)
1750 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1751 else if (state->zsbuf)
1752 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1753 else
1754 rctx->framebuffer.nr_samples = 0;
1755
1756 for (i = 0; i < state->nr_cbufs; i++) {
1757 surf = (struct r600_surface*)state->cbufs[i];
1758 rtex = (struct r600_texture*)surf->base.texture;
1759
1760 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1761
1762 if (!surf->color_initialized) {
1763 evergreen_init_color_surface(rctx, surf);
1764 }
1765
1766 if (!surf->export_16bpc) {
1767 rctx->framebuffer.export_16bpc = false;
1768 }
1769
1770 if (rtex->fmask_size && rtex->cmask_size) {
1771 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1772 }
1773 }
1774
1775 /* Update alpha-test state dependencies.
1776 * Alpha-test is done on the first colorbuffer only. */
1777 if (state->nr_cbufs) {
1778 surf = (struct r600_surface*)state->cbufs[0];
1779 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1780 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1781 rctx->alphatest_state.atom.dirty = true;
1782 }
1783 if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
1784 rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
1785 rctx->alphatest_state.atom.dirty = true;
1786 }
1787 }
1788
1789 /* ZS buffer. */
1790 if (state->zsbuf) {
1791 surf = (struct r600_surface*)state->zsbuf;
1792
1793 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1794
1795 if (!surf->depth_initialized) {
1796 evergreen_init_depth_surface(rctx, surf);
1797 }
1798
1799 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1800 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1801 rctx->poly_offset_state.atom.dirty = true;
1802 }
1803
1804 if (rctx->db_state.rsurf != surf) {
1805 rctx->db_state.rsurf = surf;
1806 rctx->db_state.atom.dirty = true;
1807 rctx->db_misc_state.atom.dirty = true;
1808 }
1809 } else if (rctx->db_state.rsurf) {
1810 rctx->db_state.rsurf = NULL;
1811 rctx->db_state.atom.dirty = true;
1812 rctx->db_misc_state.atom.dirty = true;
1813 }
1814
1815 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1816 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1817 rctx->cb_misc_state.atom.dirty = true;
1818 }
1819
1820 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1821 rctx->alphatest_state.bypass = false;
1822 rctx->alphatest_state.atom.dirty = true;
1823 }
1824
1825 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1826 if (rctx->b.chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) {
1827 rctx->db_misc_state.log_samples = log_samples;
1828 rctx->db_misc_state.atom.dirty = true;
1829 }
1830
1831 evergreen_update_db_shader_control(rctx);
1832
1833 /* Calculate the CS size. */
1834 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1835
1836 /* MSAA. */
1837 if (rctx->b.chip_class == EVERGREEN) {
1838 switch (rctx->framebuffer.nr_samples) {
1839 case 2:
1840 case 4:
1841 rctx->framebuffer.atom.num_dw += 6;
1842 break;
1843 case 8:
1844 rctx->framebuffer.atom.num_dw += 10;
1845 break;
1846 }
1847 rctx->framebuffer.atom.num_dw += 4;
1848 } else {
1849 switch (rctx->framebuffer.nr_samples) {
1850 case 2:
1851 case 4:
1852 rctx->framebuffer.atom.num_dw += 12;
1853 break;
1854 case 8:
1855 rctx->framebuffer.atom.num_dw += 16;
1856 break;
1857 case 16:
1858 rctx->framebuffer.atom.num_dw += 18;
1859 break;
1860 }
1861 rctx->framebuffer.atom.num_dw += 7;
1862 }
1863
1864 /* Colorbuffers. */
1865 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1866 if (rctx->keep_tiling_flags)
1867 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1868 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1869
1870 /* ZS buffer. */
1871 if (state->zsbuf) {
1872 rctx->framebuffer.atom.num_dw += 24;
1873 if (rctx->keep_tiling_flags)
1874 rctx->framebuffer.atom.num_dw += 2;
1875 } else if (rctx->screen->b.info.drm_minor >= 18) {
1876 rctx->framebuffer.atom.num_dw += 4;
1877 }
1878
1879 rctx->framebuffer.atom.dirty = true;
1880 }
1881
1882 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1883 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1884 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1885 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1886 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1887
1888 /* 2xMSAA
1889 * There are two locations (-4, 4), (4, -4). */
1890 static uint32_t sample_locs_2x[] = {
1891 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1892 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1893 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1894 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1895 };
1896 static unsigned max_dist_2x = 4;
1897 /* 4xMSAA
1898 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1899 static uint32_t sample_locs_4x[] = {
1900 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1901 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1902 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1903 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1904 };
1905 static unsigned max_dist_4x = 6;
1906 /* 8xMSAA */
1907 static uint32_t sample_locs_8x[] = {
1908 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1909 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1910 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1911 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1912 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1913 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1914 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1915 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1916 };
1917 static unsigned max_dist_8x = 7;
1918
1919 static void evergreen_get_sample_position(struct pipe_context *ctx,
1920 unsigned sample_count,
1921 unsigned sample_index,
1922 float *out_value)
1923 {
1924 int offset, index;
1925 struct {
1926 int idx:4;
1927 } val;
1928 switch (sample_count) {
1929 case 1:
1930 default:
1931 out_value[0] = out_value[1] = 0.5;
1932 break;
1933 case 2:
1934 offset = 4 * (sample_index * 2);
1935 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1936 out_value[0] = (float)(val.idx + 8) / 16.0f;
1937 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1938 out_value[1] = (float)(val.idx + 8) / 16.0f;
1939 break;
1940 case 4:
1941 offset = 4 * (sample_index * 2);
1942 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1943 out_value[0] = (float)(val.idx + 8) / 16.0f;
1944 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1945 out_value[1] = (float)(val.idx + 8) / 16.0f;
1946 break;
1947 case 8:
1948 offset = 4 * (sample_index % 4 * 2);
1949 index = (sample_index / 4);
1950 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1951 out_value[0] = (float)(val.idx + 8) / 16.0f;
1952 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1953 out_value[1] = (float)(val.idx + 8) / 16.0f;
1954 break;
1955 }
1956 }
1957
1958 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1959 {
1960
1961 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1962 unsigned max_dist = 0;
1963
1964 switch (nr_samples) {
1965 default:
1966 nr_samples = 0;
1967 break;
1968 case 2:
1969 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_2x));
1970 radeon_emit_array(cs, sample_locs_2x, Elements(sample_locs_2x));
1971 max_dist = max_dist_2x;
1972 break;
1973 case 4:
1974 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_4x));
1975 radeon_emit_array(cs, sample_locs_4x, Elements(sample_locs_4x));
1976 max_dist = max_dist_4x;
1977 break;
1978 case 8:
1979 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1980 radeon_emit_array(cs, sample_locs_8x, Elements(sample_locs_8x));
1981 max_dist = max_dist_8x;
1982 break;
1983 }
1984
1985 if (nr_samples > 1) {
1986 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1987 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1988 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1989 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1990 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1991 } else {
1992 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1993 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1994 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1995 }
1996 }
1997
1998 /* Cayman 8xMSAA */
1999 static uint32_t cm_sample_locs_8x[] = {
2000 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2001 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2002 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2003 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2004 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2005 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2006 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2007 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2008 };
2009 static unsigned cm_max_dist_8x = 8;
2010 /* Cayman 16xMSAA */
2011 static uint32_t cm_sample_locs_16x[] = {
2012 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2013 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2014 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2015 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2016 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2017 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2018 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2019 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2020 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2021 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2022 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2023 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2024 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2025 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2026 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2027 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2028 };
2029 static unsigned cm_max_dist_16x = 8;
2030 static void cayman_get_sample_position(struct pipe_context *ctx,
2031 unsigned sample_count,
2032 unsigned sample_index,
2033 float *out_value)
2034 {
2035 int offset, index;
2036 struct {
2037 int idx:4;
2038 } val;
2039 switch (sample_count) {
2040 case 1:
2041 default:
2042 out_value[0] = out_value[1] = 0.5;
2043 break;
2044 case 2:
2045 offset = 4 * (sample_index * 2);
2046 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
2047 out_value[0] = (float)(val.idx + 8) / 16.0f;
2048 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
2049 out_value[1] = (float)(val.idx + 8) / 16.0f;
2050 break;
2051 case 4:
2052 offset = 4 * (sample_index * 2);
2053 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
2054 out_value[0] = (float)(val.idx + 8) / 16.0f;
2055 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
2056 out_value[1] = (float)(val.idx + 8) / 16.0f;
2057 break;
2058 case 8:
2059 offset = 4 * (sample_index % 4 * 2);
2060 index = (sample_index / 4) * 4;
2061 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
2062 out_value[0] = (float)(val.idx + 8) / 16.0f;
2063 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
2064 out_value[1] = (float)(val.idx + 8) / 16.0f;
2065 break;
2066 case 16:
2067 offset = 4 * (sample_index % 4 * 2);
2068 index = (sample_index / 4) * 4;
2069 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
2070 out_value[0] = (float)(val.idx + 8) / 16.0f;
2071 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
2072 out_value[1] = (float)(val.idx + 8) / 16.0f;
2073 break;
2074 }
2075 }
2076
2077 static void cayman_emit_msaa_state(struct r600_context *rctx, int nr_samples)
2078 {
2079
2080
2081 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2082 unsigned max_dist = 0;
2083
2084 switch (nr_samples) {
2085 default:
2086 nr_samples = 0;
2087 break;
2088 case 2:
2089 r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
2090 r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
2091 r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
2092 r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
2093 max_dist = max_dist_2x;
2094 break;
2095 case 4:
2096 r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
2097 r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
2098 r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
2099 r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
2100 max_dist = max_dist_4x;
2101 break;
2102 case 8:
2103 r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
2104 radeon_emit(cs, cm_sample_locs_8x[0]);
2105 radeon_emit(cs, cm_sample_locs_8x[4]);
2106 radeon_emit(cs, 0);
2107 radeon_emit(cs, 0);
2108 radeon_emit(cs, cm_sample_locs_8x[1]);
2109 radeon_emit(cs, cm_sample_locs_8x[5]);
2110 radeon_emit(cs, 0);
2111 radeon_emit(cs, 0);
2112 radeon_emit(cs, cm_sample_locs_8x[2]);
2113 radeon_emit(cs, cm_sample_locs_8x[6]);
2114 radeon_emit(cs, 0);
2115 radeon_emit(cs, 0);
2116 radeon_emit(cs, cm_sample_locs_8x[3]);
2117 radeon_emit(cs, cm_sample_locs_8x[7]);
2118 max_dist = cm_max_dist_8x;
2119 break;
2120 case 16:
2121 r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
2122 radeon_emit(cs, cm_sample_locs_16x[0]);
2123 radeon_emit(cs, cm_sample_locs_16x[4]);
2124 radeon_emit(cs, cm_sample_locs_16x[8]);
2125 radeon_emit(cs, cm_sample_locs_16x[12]);
2126 radeon_emit(cs, cm_sample_locs_16x[1]);
2127 radeon_emit(cs, cm_sample_locs_16x[5]);
2128 radeon_emit(cs, cm_sample_locs_16x[9]);
2129 radeon_emit(cs, cm_sample_locs_16x[13]);
2130 radeon_emit(cs, cm_sample_locs_16x[2]);
2131 radeon_emit(cs, cm_sample_locs_16x[6]);
2132 radeon_emit(cs, cm_sample_locs_16x[10]);
2133 radeon_emit(cs, cm_sample_locs_16x[14]);
2134 radeon_emit(cs, cm_sample_locs_16x[3]);
2135 radeon_emit(cs, cm_sample_locs_16x[7]);
2136 radeon_emit(cs, cm_sample_locs_16x[11]);
2137 radeon_emit(cs, cm_sample_locs_16x[15]);
2138 max_dist = cm_max_dist_16x;
2139 break;
2140 }
2141
2142 if (nr_samples > 1) {
2143 unsigned log_samples = util_logbase2(nr_samples);
2144
2145 r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
2146 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
2147 S_028C00_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2148 radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
2149 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
2150 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2151
2152 r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
2153 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2154 S_028804_PS_ITER_SAMPLES(log_samples) |
2155 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2156 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2157 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2158 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2159 } else {
2160 r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
2161 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2162 radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2163
2164 r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
2165 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2166 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2167 }
2168 }
2169
2170 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
2171 {
2172 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2173 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
2174 unsigned nr_cbufs = state->nr_cbufs;
2175 unsigned i, tl, br;
2176
2177 /* XXX support more colorbuffers once we need them */
2178 assert(nr_cbufs <= 8);
2179 if (nr_cbufs > 8)
2180 nr_cbufs = 8;
2181
2182 /* Colorbuffers. */
2183 for (i = 0; i < nr_cbufs; i++) {
2184 struct r600_surface *cb = (struct r600_surface*)state->cbufs[i];
2185 struct r600_texture *tex = (struct r600_texture *)cb->base.texture;
2186 unsigned reloc = r600_context_bo_reloc(&rctx->b,
2187 &rctx->b.rings.gfx,
2188 (struct r600_resource*)cb->base.texture,
2189 RADEON_USAGE_READWRITE);
2190 unsigned cmask_reloc = 0;
2191 if (tex->cmask && tex->cmask != &tex->resource) {
2192 cmask_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
2193 tex->cmask, RADEON_USAGE_READWRITE);
2194 } else {
2195 cmask_reloc = reloc;
2196 }
2197
2198 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
2199 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2200 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2201 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2202 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2203 radeon_emit(cs, cb->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2204 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2205 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
2206 radeon_emit(cs, cb->cb_color_cmask); /* R_028C7C_CB_COLOR0_CMASK */
2207 radeon_emit(cs, cb->cb_color_cmask_slice); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2208 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2209 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2210 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2211 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2212
2213 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
2214 radeon_emit(cs, reloc);
2215
2216 if (!rctx->keep_tiling_flags) {
2217 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
2218 radeon_emit(cs, reloc);
2219 }
2220
2221 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
2222 radeon_emit(cs, reloc);
2223
2224 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
2225 radeon_emit(cs, cmask_reloc);
2226
2227 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
2228 radeon_emit(cs, reloc);
2229 }
2230 /* set CB_COLOR1_INFO for possible dual-src blending */
2231 if (i == 1 && !((struct r600_texture*)state->cbufs[0]->texture)->is_rat) {
2232 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2233 ((struct r600_surface*)state->cbufs[0])->cb_color_info);
2234
2235 if (!rctx->keep_tiling_flags) {
2236 unsigned reloc = r600_context_bo_reloc(&rctx->b,
2237 &rctx->b.rings.gfx,
2238 (struct r600_resource*)state->cbufs[0]->texture,
2239 RADEON_USAGE_READWRITE);
2240
2241 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
2242 radeon_emit(cs, reloc);
2243 }
2244 i++;
2245 }
2246 if (rctx->keep_tiling_flags) {
2247 for (; i < 8 ; i++) {
2248 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2249 }
2250 for (; i < 12; i++) {
2251 r600_write_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
2252 }
2253 }
2254
2255 /* ZS buffer. */
2256 if (state->zsbuf) {
2257 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2258 unsigned reloc = r600_context_bo_reloc(&rctx->b,
2259 &rctx->b.rings.gfx,
2260 (struct r600_resource*)state->zsbuf->texture,
2261 RADEON_USAGE_READWRITE);
2262
2263 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2264 zb->pa_su_poly_offset_db_fmt_cntl);
2265 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2266
2267 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
2268 radeon_emit(cs, zb->db_depth_info); /* R_028040_DB_Z_INFO */
2269 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2270 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2271 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2272 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2273 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2274 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2275 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2276
2277 if (!rctx->keep_tiling_flags) {
2278 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
2279 radeon_emit(cs, reloc);
2280 }
2281
2282 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
2283 radeon_emit(cs, reloc);
2284
2285 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
2286 radeon_emit(cs, reloc);
2287
2288 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
2289 radeon_emit(cs, reloc);
2290
2291 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
2292 radeon_emit(cs, reloc);
2293 } else if (rctx->screen->b.info.drm_minor >= 18) {
2294 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
2295 * Older kernels are out of luck. */
2296 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2297 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2298 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2299 }
2300
2301 /* Framebuffer dimensions. */
2302 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
2303
2304 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
2305 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
2306 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
2307
2308 if (rctx->b.chip_class == EVERGREEN) {
2309 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
2310 } else {
2311 cayman_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
2312 }
2313 }
2314
2315 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
2316 {
2317 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2318 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
2319 float offset_units = state->offset_units;
2320 float offset_scale = state->offset_scale;
2321
2322 switch (state->zs_format) {
2323 case PIPE_FORMAT_Z24X8_UNORM:
2324 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2325 case PIPE_FORMAT_X8Z24_UNORM:
2326 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2327 offset_units *= 2.0f;
2328 break;
2329 case PIPE_FORMAT_Z16_UNORM:
2330 offset_units *= 4.0f;
2331 break;
2332 default:;
2333 }
2334
2335 r600_write_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
2336 radeon_emit(cs, fui(offset_scale));
2337 radeon_emit(cs, fui(offset_units));
2338 radeon_emit(cs, fui(offset_scale));
2339 radeon_emit(cs, fui(offset_units));
2340 }
2341
2342 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2343 {
2344 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2345 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
2346 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
2347 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
2348
2349 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
2350 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
2351 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
2352 * will assure that the alpha-test will work even if there is
2353 * no colorbuffer bound. */
2354 radeon_emit(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
2355 }
2356
2357 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
2358 {
2359 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2360 struct r600_db_state *a = (struct r600_db_state*)atom;
2361
2362 if (a->rsurf && a->rsurf->htile_enabled) {
2363 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
2364 unsigned reloc_idx;
2365
2366 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear));
2367 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
2368 r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
2369 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
2370 reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile, RADEON_USAGE_READWRITE);
2371 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
2372 cs->buf[cs->cdw++] = reloc_idx;
2373 } else {
2374 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
2375 r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
2376 }
2377 }
2378
2379 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2380 {
2381 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2382 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2383 unsigned db_render_control = 0;
2384 unsigned db_count_control = 0;
2385 unsigned db_render_override =
2386 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2387 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2388
2389 if (a->occlusion_query_enabled) {
2390 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
2391 if (rctx->b.chip_class == CAYMAN) {
2392 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
2393 }
2394 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
2395 }
2396 /* FIXME we should be able to use hyperz even if we are not writing to
2397 * zbuffer but somehow this trigger GPU lockup. See :
2398 *
2399 * https://bugs.freedesktop.org/show_bug.cgi?id=60848
2400 *
2401 * Disable hyperz for now if not writing to zbuffer.
2402 */
2403 if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled && rctx->zwritemask) {
2404 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
2405 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
2406 /* This is to fix a lockup when hyperz and alpha test are enabled at
2407 * the same time somehow GPU get confuse on which order to pick for
2408 * z test
2409 */
2410 if (rctx->alphatest_state.sx_alpha_test_control) {
2411 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
2412 }
2413 } else {
2414 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
2415 }
2416 if (a->flush_depthstencil_through_cb) {
2417 assert(a->copy_depth || a->copy_stencil);
2418
2419 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
2420 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
2421 S_028000_COPY_CENTROID(1) |
2422 S_028000_COPY_SAMPLE(a->copy_sample);
2423 } else if (a->flush_depthstencil_in_place) {
2424 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(1) |
2425 S_028000_STENCIL_COMPRESS_DISABLE(1);
2426 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2427 }
2428 if (a->htile_clear) {
2429 /* FIXME we might want to disable cliprect here */
2430 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
2431 }
2432
2433 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
2434 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
2435 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
2436 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2437 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2438 }
2439
2440 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
2441 struct r600_vertexbuf_state *state,
2442 unsigned resource_offset,
2443 unsigned pkt_flags)
2444 {
2445 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2446 uint32_t dirty_mask = state->dirty_mask;
2447
2448 while (dirty_mask) {
2449 struct pipe_vertex_buffer *vb;
2450 struct r600_resource *rbuffer;
2451 uint64_t va;
2452 unsigned buffer_index = u_bit_scan(&dirty_mask);
2453
2454 vb = &state->vb[buffer_index];
2455 rbuffer = (struct r600_resource*)vb->buffer;
2456 assert(rbuffer);
2457
2458 va = r600_resource_va(&rctx->screen->b.b, &rbuffer->b.b);
2459 va += vb->buffer_offset;
2460
2461 /* fetch resources start at index 992 */
2462 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2463 radeon_emit(cs, (resource_offset + buffer_index) * 8);
2464 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2465 radeon_emit(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2466 radeon_emit(cs, /* RESOURCEi_WORD2 */
2467 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2468 S_030008_STRIDE(vb->stride) |
2469 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2470 radeon_emit(cs, /* RESOURCEi_WORD3 */
2471 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2472 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2473 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2474 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2475 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2476 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2477 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2478 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2479
2480 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2481 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
2482 }
2483 state->dirty_mask = 0;
2484 }
2485
2486 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2487 {
2488 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
2489 }
2490
2491 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2492 {
2493 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
2494 RADEON_CP_PACKET3_COMPUTE_MODE);
2495 }
2496
2497 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2498 struct r600_constbuf_state *state,
2499 unsigned buffer_id_base,
2500 unsigned reg_alu_constbuf_size,
2501 unsigned reg_alu_const_cache,
2502 unsigned pkt_flags)
2503 {
2504 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2505 uint32_t dirty_mask = state->dirty_mask;
2506
2507 while (dirty_mask) {
2508 struct pipe_constant_buffer *cb;
2509 struct r600_resource *rbuffer;
2510 uint64_t va;
2511 unsigned buffer_index = ffs(dirty_mask) - 1;
2512
2513 cb = &state->cb[buffer_index];
2514 rbuffer = (struct r600_resource*)cb->buffer;
2515 assert(rbuffer);
2516
2517 va = r600_resource_va(&rctx->screen->b.b, &rbuffer->b.b);
2518 va += cb->buffer_offset;
2519
2520 r600_write_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
2521 ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags);
2522 r600_write_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
2523 pkt_flags);
2524
2525 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2526 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
2527
2528 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2529 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
2530 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2531 radeon_emit(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2532 radeon_emit(cs, /* RESOURCEi_WORD2 */
2533 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2534 S_030008_STRIDE(16) |
2535 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2536 radeon_emit(cs, /* RESOURCEi_WORD3 */
2537 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2538 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2539 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2540 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2541 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2542 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2543 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2544 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2545
2546 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2547 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
2548
2549 dirty_mask &= ~(1 << buffer_index);
2550 }
2551 state->dirty_mask = 0;
2552 }
2553
2554 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2555 {
2556 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 176,
2557 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2558 R_028980_ALU_CONST_CACHE_VS_0,
2559 0 /* PKT3 flags */);
2560 }
2561
2562 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2563 {
2564 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
2565 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2566 R_0289C0_ALU_CONST_CACHE_GS_0,
2567 0 /* PKT3 flags */);
2568 }
2569
2570 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2571 {
2572 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
2573 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2574 R_028940_ALU_CONST_CACHE_PS_0,
2575 0 /* PKT3 flags */);
2576 }
2577
2578 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2579 {
2580 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE], 816,
2581 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2582 R_028F40_ALU_CONST_CACHE_LS_0,
2583 RADEON_CP_PACKET3_COMPUTE_MODE);
2584 }
2585
2586 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2587 struct r600_samplerview_state *state,
2588 unsigned resource_id_base)
2589 {
2590 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2591 uint32_t dirty_mask = state->dirty_mask;
2592
2593 while (dirty_mask) {
2594 struct r600_pipe_sampler_view *rview;
2595 unsigned resource_index = u_bit_scan(&dirty_mask);
2596 unsigned reloc;
2597
2598 rview = state->views[resource_index];
2599 assert(rview);
2600
2601 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2602 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2603 radeon_emit_array(cs, rview->tex_resource_words, 8);
2604
2605 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
2606 RADEON_USAGE_READ);
2607 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2608 radeon_emit(cs, reloc);
2609
2610 if (!rview->skip_mip_address_reloc) {
2611 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2612 radeon_emit(cs, reloc);
2613 }
2614 }
2615 state->dirty_mask = 0;
2616 }
2617
2618 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2619 {
2620 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 176 + R600_MAX_CONST_BUFFERS);
2621 }
2622
2623 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2624 {
2625 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2626 }
2627
2628 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2629 {
2630 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2631 }
2632
2633 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2634 struct r600_textures_info *texinfo,
2635 unsigned resource_id_base,
2636 unsigned border_index_reg)
2637 {
2638 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2639 uint32_t dirty_mask = texinfo->states.dirty_mask;
2640
2641 while (dirty_mask) {
2642 struct r600_pipe_sampler_state *rstate;
2643 unsigned i = u_bit_scan(&dirty_mask);
2644
2645 rstate = texinfo->states.states[i];
2646 assert(rstate);
2647
2648 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2649 radeon_emit(cs, (resource_id_base + i) * 3);
2650 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2651
2652 if (rstate->border_color_use) {
2653 r600_write_config_reg_seq(cs, border_index_reg, 5);
2654 radeon_emit(cs, i);
2655 radeon_emit_array(cs, rstate->border_color.ui, 4);
2656 }
2657 }
2658 texinfo->states.dirty_mask = 0;
2659 }
2660
2661 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2662 {
2663 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
2664 }
2665
2666 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2667 {
2668 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX);
2669 }
2670
2671 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2672 {
2673 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
2674 }
2675
2676 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2677 {
2678 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2679 uint8_t mask = s->sample_mask;
2680
2681 r600_write_context_reg(rctx->b.rings.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2682 mask | (mask << 8) | (mask << 16) | (mask << 24));
2683 }
2684
2685 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2686 {
2687 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2688 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2689 uint16_t mask = s->sample_mask;
2690
2691 r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2692 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2693 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2694 }
2695
2696 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2697 {
2698 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2699 struct r600_cso_state *state = (struct r600_cso_state*)a;
2700 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2701
2702 r600_write_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2703 (r600_resource_va(rctx->b.b.screen, &shader->buffer->b.b) + shader->offset) >> 8);
2704 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2705 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer, RADEON_USAGE_READ));
2706 }
2707
2708 void cayman_init_common_regs(struct r600_command_buffer *cb,
2709 enum chip_class ctx_chip_class,
2710 enum radeon_family ctx_family,
2711 int ctx_drm_minor)
2712 {
2713 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2714 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2715 /* always set the temp clauses */
2716 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2717
2718 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2719 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2720 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2721
2722 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2723
2724 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2725
2726 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2727
2728 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2729 }
2730
2731 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2732 {
2733 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2734
2735 r600_init_command_buffer(cb, 256);
2736
2737 /* This must be first. */
2738 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2739 r600_store_value(cb, 0x80000000);
2740 r600_store_value(cb, 0x80000000);
2741
2742 /* We're setting config registers here. */
2743 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2744 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2745
2746 cayman_init_common_regs(cb, rctx->b.chip_class,
2747 rctx->b.family, rctx->screen->b.info.drm_minor);
2748
2749 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2750 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2751
2752 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2753 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2754 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2755 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2756 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2757 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2758 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2759
2760 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2761 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2762 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2763 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2764 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2765
2766 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2767 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2768 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2769 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2770 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2771 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2772 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2773 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2774 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2775 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2776 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2777 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2778 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2779 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2780
2781 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2782 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2783 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2784
2785 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2786 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2787 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2788
2789 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2790
2791 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2792
2793 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2794 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2795 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2796
2797 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
2798 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2799 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2800
2801 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2802
2803 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2804 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2805 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2806
2807 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2808
2809 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2810
2811 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2812
2813 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2814 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2815 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2816 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2817
2818 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2819 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2820
2821 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2822 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2823 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2824
2825 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2826 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2827 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2828
2829 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2830 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2831 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2832 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2833 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2834
2835 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2836 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2837 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2838
2839 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2840 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2841 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2842
2843 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2844 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2845 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2846
2847 /* to avoid GPU doing any preloading of constant from random address */
2848 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2849 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2850 r600_store_value(cb, 0);
2851 r600_store_value(cb, 0);
2852 r600_store_value(cb, 0);
2853 r600_store_value(cb, 0);
2854 r600_store_value(cb, 0);
2855 r600_store_value(cb, 0);
2856 r600_store_value(cb, 0);
2857 r600_store_value(cb, 0);
2858 r600_store_value(cb, 0);
2859 r600_store_value(cb, 0);
2860 r600_store_value(cb, 0);
2861 r600_store_value(cb, 0);
2862 r600_store_value(cb, 0);
2863 r600_store_value(cb, 0);
2864 r600_store_value(cb, 0);
2865
2866 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2867 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2868 r600_store_value(cb, 0);
2869 r600_store_value(cb, 0);
2870 r600_store_value(cb, 0);
2871 r600_store_value(cb, 0);
2872 r600_store_value(cb, 0);
2873 r600_store_value(cb, 0);
2874 r600_store_value(cb, 0);
2875 r600_store_value(cb, 0);
2876 r600_store_value(cb, 0);
2877 r600_store_value(cb, 0);
2878 r600_store_value(cb, 0);
2879 r600_store_value(cb, 0);
2880 r600_store_value(cb, 0);
2881 r600_store_value(cb, 0);
2882 r600_store_value(cb, 0);
2883
2884 if (rctx->screen->has_streamout) {
2885 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2886 }
2887
2888 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2889 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2890 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2891 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2892 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2893 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2894 r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
2895
2896 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2897 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2898 }
2899
2900 void evergreen_init_common_regs(struct r600_command_buffer *cb,
2901 enum chip_class ctx_chip_class,
2902 enum radeon_family ctx_family,
2903 int ctx_drm_minor)
2904 {
2905 int ps_prio;
2906 int vs_prio;
2907 int gs_prio;
2908 int es_prio;
2909
2910 int hs_prio;
2911 int cs_prio;
2912 int ls_prio;
2913
2914 int num_ps_gprs;
2915 int num_vs_gprs;
2916 int num_gs_gprs;
2917 int num_es_gprs;
2918 int num_hs_gprs;
2919 int num_ls_gprs;
2920 int num_temp_gprs;
2921
2922 unsigned tmp;
2923
2924 ps_prio = 0;
2925 vs_prio = 1;
2926 gs_prio = 2;
2927 es_prio = 3;
2928 hs_prio = 0;
2929 ls_prio = 0;
2930 cs_prio = 0;
2931
2932 num_ps_gprs = 93;
2933 num_vs_gprs = 46;
2934 num_temp_gprs = 4;
2935 num_gs_gprs = 31;
2936 num_es_gprs = 31;
2937 num_hs_gprs = 23;
2938 num_ls_gprs = 23;
2939
2940 tmp = 0;
2941 switch (ctx_family) {
2942 case CHIP_CEDAR:
2943 case CHIP_PALM:
2944 case CHIP_SUMO:
2945 case CHIP_SUMO2:
2946 case CHIP_CAICOS:
2947 break;
2948 default:
2949 tmp |= S_008C00_VC_ENABLE(1);
2950 break;
2951 }
2952 tmp |= S_008C00_EXPORT_SRC_C(1);
2953 tmp |= S_008C00_CS_PRIO(cs_prio);
2954 tmp |= S_008C00_LS_PRIO(ls_prio);
2955 tmp |= S_008C00_HS_PRIO(hs_prio);
2956 tmp |= S_008C00_PS_PRIO(ps_prio);
2957 tmp |= S_008C00_VS_PRIO(vs_prio);
2958 tmp |= S_008C00_GS_PRIO(gs_prio);
2959 tmp |= S_008C00_ES_PRIO(es_prio);
2960
2961 /* enable dynamic GPR resource management */
2962 if (ctx_drm_minor >= 7) {
2963 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2964 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2965 /* always set temp clauses */
2966 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2967 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2968 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2969 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2970 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2971 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2972 S_028838_PS_GPRS(0x1e) |
2973 S_028838_VS_GPRS(0x1e) |
2974 S_028838_GS_GPRS(0x1e) |
2975 S_028838_ES_GPRS(0x1e) |
2976 S_028838_HS_GPRS(0x1e) |
2977 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2978 } else {
2979 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2980 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2981
2982 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2983 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2984 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2985 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2986
2987 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2988 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2989 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2990
2991 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2992 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2993 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2994 }
2995
2996 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2997
2998 /* The cs checker requires this register to be set. */
2999 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
3000
3001 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
3002
3003 return;
3004 }
3005
3006 void evergreen_init_atom_start_cs(struct r600_context *rctx)
3007 {
3008 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
3009 int num_ps_threads;
3010 int num_vs_threads;
3011 int num_gs_threads;
3012 int num_es_threads;
3013 int num_hs_threads;
3014 int num_ls_threads;
3015
3016 int num_ps_stack_entries;
3017 int num_vs_stack_entries;
3018 int num_gs_stack_entries;
3019 int num_es_stack_entries;
3020 int num_hs_stack_entries;
3021 int num_ls_stack_entries;
3022 enum radeon_family family;
3023 unsigned tmp;
3024
3025 if (rctx->b.chip_class == CAYMAN) {
3026 cayman_init_atom_start_cs(rctx);
3027 return;
3028 }
3029
3030 r600_init_command_buffer(cb, 256);
3031
3032 /* This must be first. */
3033 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
3034 r600_store_value(cb, 0x80000000);
3035 r600_store_value(cb, 0x80000000);
3036
3037 /* We're setting config registers here. */
3038 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
3039 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3040
3041 evergreen_init_common_regs(cb, rctx->b.chip_class,
3042 rctx->b.family, rctx->screen->b.info.drm_minor);
3043
3044 family = rctx->b.family;
3045 switch (family) {
3046 case CHIP_CEDAR:
3047 default:
3048 num_ps_threads = 96;
3049 num_vs_threads = 16;
3050 num_gs_threads = 16;
3051 num_es_threads = 16;
3052 num_hs_threads = 16;
3053 num_ls_threads = 16;
3054 num_ps_stack_entries = 42;
3055 num_vs_stack_entries = 42;
3056 num_gs_stack_entries = 42;
3057 num_es_stack_entries = 42;
3058 num_hs_stack_entries = 42;
3059 num_ls_stack_entries = 42;
3060 break;
3061 case CHIP_REDWOOD:
3062 num_ps_threads = 128;
3063 num_vs_threads = 20;
3064 num_gs_threads = 20;
3065 num_es_threads = 20;
3066 num_hs_threads = 20;
3067 num_ls_threads = 20;
3068 num_ps_stack_entries = 42;
3069 num_vs_stack_entries = 42;
3070 num_gs_stack_entries = 42;
3071 num_es_stack_entries = 42;
3072 num_hs_stack_entries = 42;
3073 num_ls_stack_entries = 42;
3074 break;
3075 case CHIP_JUNIPER:
3076 num_ps_threads = 128;
3077 num_vs_threads = 20;
3078 num_gs_threads = 20;
3079 num_es_threads = 20;
3080 num_hs_threads = 20;
3081 num_ls_threads = 20;
3082 num_ps_stack_entries = 85;
3083 num_vs_stack_entries = 85;
3084 num_gs_stack_entries = 85;
3085 num_es_stack_entries = 85;
3086 num_hs_stack_entries = 85;
3087 num_ls_stack_entries = 85;
3088 break;
3089 case CHIP_CYPRESS:
3090 case CHIP_HEMLOCK:
3091 num_ps_threads = 128;
3092 num_vs_threads = 20;
3093 num_gs_threads = 20;
3094 num_es_threads = 20;
3095 num_hs_threads = 20;
3096 num_ls_threads = 20;
3097 num_ps_stack_entries = 85;
3098 num_vs_stack_entries = 85;
3099 num_gs_stack_entries = 85;
3100 num_es_stack_entries = 85;
3101 num_hs_stack_entries = 85;
3102 num_ls_stack_entries = 85;
3103 break;
3104 case CHIP_PALM:
3105 num_ps_threads = 96;
3106 num_vs_threads = 16;
3107 num_gs_threads = 16;
3108 num_es_threads = 16;
3109 num_hs_threads = 16;
3110 num_ls_threads = 16;
3111 num_ps_stack_entries = 42;
3112 num_vs_stack_entries = 42;
3113 num_gs_stack_entries = 42;
3114 num_es_stack_entries = 42;
3115 num_hs_stack_entries = 42;
3116 num_ls_stack_entries = 42;
3117 break;
3118 case CHIP_SUMO:
3119 num_ps_threads = 96;
3120 num_vs_threads = 25;
3121 num_gs_threads = 25;
3122 num_es_threads = 25;
3123 num_hs_threads = 25;
3124 num_ls_threads = 25;
3125 num_ps_stack_entries = 42;
3126 num_vs_stack_entries = 42;
3127 num_gs_stack_entries = 42;
3128 num_es_stack_entries = 42;
3129 num_hs_stack_entries = 42;
3130 num_ls_stack_entries = 42;
3131 break;
3132 case CHIP_SUMO2:
3133 num_ps_threads = 96;
3134 num_vs_threads = 25;
3135 num_gs_threads = 25;
3136 num_es_threads = 25;
3137 num_hs_threads = 25;
3138 num_ls_threads = 25;
3139 num_ps_stack_entries = 85;
3140 num_vs_stack_entries = 85;
3141 num_gs_stack_entries = 85;
3142 num_es_stack_entries = 85;
3143 num_hs_stack_entries = 85;
3144 num_ls_stack_entries = 85;
3145 break;
3146 case CHIP_BARTS:
3147 num_ps_threads = 128;
3148 num_vs_threads = 20;
3149 num_gs_threads = 20;
3150 num_es_threads = 20;
3151 num_hs_threads = 20;
3152 num_ls_threads = 20;
3153 num_ps_stack_entries = 85;
3154 num_vs_stack_entries = 85;
3155 num_gs_stack_entries = 85;
3156 num_es_stack_entries = 85;
3157 num_hs_stack_entries = 85;
3158 num_ls_stack_entries = 85;
3159 break;
3160 case CHIP_TURKS:
3161 num_ps_threads = 128;
3162 num_vs_threads = 20;
3163 num_gs_threads = 20;
3164 num_es_threads = 20;
3165 num_hs_threads = 20;
3166 num_ls_threads = 20;
3167 num_ps_stack_entries = 42;
3168 num_vs_stack_entries = 42;
3169 num_gs_stack_entries = 42;
3170 num_es_stack_entries = 42;
3171 num_hs_stack_entries = 42;
3172 num_ls_stack_entries = 42;
3173 break;
3174 case CHIP_CAICOS:
3175 num_ps_threads = 128;
3176 num_vs_threads = 10;
3177 num_gs_threads = 10;
3178 num_es_threads = 10;
3179 num_hs_threads = 10;
3180 num_ls_threads = 10;
3181 num_ps_stack_entries = 42;
3182 num_vs_stack_entries = 42;
3183 num_gs_stack_entries = 42;
3184 num_es_stack_entries = 42;
3185 num_hs_stack_entries = 42;
3186 num_ls_stack_entries = 42;
3187 break;
3188 }
3189
3190 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
3191 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
3192 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
3193 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
3194
3195 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
3196 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3197
3198 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
3199 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
3200 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3201
3202 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
3203 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
3204 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3205
3206 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
3207 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
3208 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3209
3210 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
3211 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
3212 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3213
3214 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
3215 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
3216
3217 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
3218 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
3219
3220 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
3221 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3222 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3223 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3224 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3225 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3226 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3227
3228 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3229 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3230 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3231 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3232 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3233
3234 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
3235 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3236 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
3237 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3238 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3239 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3240 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3241 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3242 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
3243 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3244 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3245 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3246 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3247 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
3248
3249 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
3250 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
3251 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
3252
3253 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
3254
3255 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
3256
3257 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
3258 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3259 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
3260
3261 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
3262
3263 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
3264
3265 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
3266 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3267 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3268
3269 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
3270 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
3271 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
3272
3273 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
3274 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3275 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
3276
3277 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
3278 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3279 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3280 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3281
3282 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
3283 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
3284 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
3285 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
3286 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
3287
3288 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
3289 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3290 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3291
3292 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
3293 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3294 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3295
3296 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3297 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3298 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
3299
3300 /* to avoid GPU doing any preloading of constant from random address */
3301 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
3302 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
3303 r600_store_value(cb, 0);
3304 r600_store_value(cb, 0);
3305 r600_store_value(cb, 0);
3306 r600_store_value(cb, 0);
3307 r600_store_value(cb, 0);
3308 r600_store_value(cb, 0);
3309 r600_store_value(cb, 0);
3310 r600_store_value(cb, 0);
3311 r600_store_value(cb, 0);
3312 r600_store_value(cb, 0);
3313 r600_store_value(cb, 0);
3314 r600_store_value(cb, 0);
3315 r600_store_value(cb, 0);
3316 r600_store_value(cb, 0);
3317 r600_store_value(cb, 0);
3318
3319 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
3320 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
3321 r600_store_value(cb, 0);
3322 r600_store_value(cb, 0);
3323 r600_store_value(cb, 0);
3324 r600_store_value(cb, 0);
3325 r600_store_value(cb, 0);
3326 r600_store_value(cb, 0);
3327 r600_store_value(cb, 0);
3328 r600_store_value(cb, 0);
3329 r600_store_value(cb, 0);
3330 r600_store_value(cb, 0);
3331 r600_store_value(cb, 0);
3332 r600_store_value(cb, 0);
3333 r600_store_value(cb, 0);
3334 r600_store_value(cb, 0);
3335 r600_store_value(cb, 0);
3336
3337 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
3338 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
3339 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
3340
3341 if (rctx->screen->has_streamout) {
3342 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3343 }
3344
3345 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
3346 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3347 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
3348 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
3349 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3350 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3351 r600_store_context_reg(cb, R_0288EC_SQ_LDS_ALLOC_PS, 0);
3352 r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
3353
3354 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3355 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3356 }
3357
3358 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3359 {
3360 struct r600_context *rctx = (struct r600_context *)ctx;
3361 struct r600_command_buffer *cb = &shader->command_buffer;
3362 struct r600_shader *rshader = &shader->shader;
3363 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
3364 int pos_index = -1, face_index = -1;
3365 int ninterp = 0;
3366 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
3367 unsigned spi_baryc_cntl, sid, tmp, num = 0;
3368 unsigned z_export = 0, stencil_export = 0;
3369 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3370 uint32_t spi_ps_input_cntl[32];
3371
3372 if (!cb->buf) {
3373 r600_init_command_buffer(cb, 64);
3374 } else {
3375 cb->num_dw = 0;
3376 }
3377
3378 for (i = 0; i < rshader->ninput; i++) {
3379 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3380 POSITION goes via GPRs from the SC so isn't counted */
3381 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3382 pos_index = i;
3383 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
3384 face_index = i;
3385 else {
3386 ninterp++;
3387 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
3388 have_linear = TRUE;
3389 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
3390 have_perspective = TRUE;
3391 if (rshader->input[i].centroid)
3392 have_centroid = TRUE;
3393 }
3394
3395 sid = rshader->input[i].spi_sid;
3396
3397 if (sid) {
3398 tmp = S_028644_SEMANTIC(sid);
3399
3400 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3401 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3402 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3403 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3404 tmp |= S_028644_FLAT_SHADE(1);
3405 }
3406
3407 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3408 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3409 tmp |= S_028644_PT_SPRITE_TEX(1);
3410 }
3411
3412 spi_ps_input_cntl[num++] = tmp;
3413 }
3414 }
3415
3416 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3417 r600_store_array(cb, num, spi_ps_input_cntl);
3418
3419 for (i = 0; i < rshader->noutput; i++) {
3420 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3421 z_export = 1;
3422 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3423 stencil_export = 1;
3424 }
3425 if (rshader->uses_kill)
3426 db_shader_control |= S_02880C_KILL_ENABLE(1);
3427
3428 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3429 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3430
3431 exports_ps = 0;
3432 for (i = 0; i < rshader->noutput; i++) {
3433 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3434 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3435 exports_ps |= 1;
3436 }
3437
3438 num_cout = rshader->nr_ps_color_exports;
3439
3440 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3441 if (!exports_ps) {
3442 /* always at least export 1 component per pixel */
3443 exports_ps = 2;
3444 }
3445 shader->nr_ps_color_outputs = num_cout;
3446 if (ninterp == 0) {
3447 ninterp = 1;
3448 have_perspective = TRUE;
3449 }
3450
3451 if (!have_perspective && !have_linear)
3452 have_perspective = TRUE;
3453
3454 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3455 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3456 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3457 spi_input_z = 0;
3458 if (pos_index != -1) {
3459 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3460 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
3461 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3462 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3463 }
3464
3465 spi_ps_in_control_1 = 0;
3466 if (face_index != -1) {
3467 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3468 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3469 }
3470
3471 spi_baryc_cntl = 0;
3472 if (have_perspective)
3473 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
3474 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
3475 if (have_linear)
3476 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
3477 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
3478
3479 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3480 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3481 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3482
3483 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3484 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3485 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3486
3487 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3488 r600_store_value(cb, r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
3489 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3490 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3491 S_028844_PRIME_CACHE_ON_DRAW(1) |
3492 S_028844_STACK_SIZE(rshader->bc.nstack));
3493 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3494
3495 shader->db_shader_control = db_shader_control;
3496 shader->ps_depth_export = z_export | stencil_export;
3497
3498 shader->sprite_coord_enable = sprite_coord_enable;
3499 if (rctx->rasterizer)
3500 shader->flatshade = rctx->rasterizer->flatshade;
3501 }
3502
3503 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3504 {
3505 struct r600_command_buffer *cb = &shader->command_buffer;
3506 struct r600_shader *rshader = &shader->shader;
3507 unsigned spi_vs_out_id[10] = {};
3508 unsigned i, tmp, nparams = 0;
3509
3510 for (i = 0; i < rshader->noutput; i++) {
3511 if (rshader->output[i].spi_sid) {
3512 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3513 spi_vs_out_id[nparams / 4] |= tmp;
3514 nparams++;
3515 }
3516 }
3517
3518 r600_init_command_buffer(cb, 32);
3519
3520 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3521 for (i = 0; i < 10; i++) {
3522 r600_store_value(cb, spi_vs_out_id[i]);
3523 }
3524
3525 /* Certain attributes (position, psize, etc.) don't count as params.
3526 * VS is required to export at least one param and r600_shader_from_tgsi()
3527 * takes care of adding a dummy export.
3528 */
3529 if (nparams < 1)
3530 nparams = 1;
3531
3532 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3533 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3534 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3535 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3536 S_028860_STACK_SIZE(rshader->bc.nstack));
3537 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3538 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
3539 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3540
3541 shader->pa_cl_vs_out_cntl =
3542 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3543 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3544 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3545 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
3546 }
3547
3548 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3549 {
3550 struct pipe_blend_state blend;
3551
3552 memset(&blend, 0, sizeof(blend));
3553 blend.independent_blend_enable = true;
3554 blend.rt[0].colormask = 0xf;
3555 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3556 }
3557
3558 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3559 {
3560 struct pipe_blend_state blend;
3561 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3562 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3563
3564 memset(&blend, 0, sizeof(blend));
3565 blend.independent_blend_enable = true;
3566 blend.rt[0].colormask = 0xf;
3567 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3568 }
3569
3570 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3571 {
3572 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3573
3574 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3575 }
3576
3577 void evergreen_update_db_shader_control(struct r600_context * rctx)
3578 {
3579 bool dual_export = rctx->framebuffer.export_16bpc &&
3580 !rctx->ps_shader->current->ps_depth_export;
3581
3582 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
3583 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3584 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3585 V_02880C_EXPORT_DB_FULL) |
3586 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3587
3588 /* When alpha test is enabled we can't trust the hw to make the proper
3589 * decision on the order in which ztest should be run related to fragment
3590 * shader execution.
3591 *
3592 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3593 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3594 * execution and thus after alpha test so if discarded by the alpha test
3595 * the z value is not written.
3596 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3597 * get a hang unless you flush the DB in between. For now just use
3598 * LATE_Z.
3599 */
3600 if (rctx->alphatest_state.sx_alpha_test_control) {
3601 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3602 } else {
3603 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3604 }
3605
3606 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3607 rctx->db_misc_state.db_shader_control = db_shader_control;
3608 rctx->db_misc_state.atom.dirty = true;
3609 }
3610 }
3611
3612 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3613 struct pipe_resource *dst,
3614 unsigned dst_level,
3615 unsigned dst_x,
3616 unsigned dst_y,
3617 unsigned dst_z,
3618 struct pipe_resource *src,
3619 unsigned src_level,
3620 unsigned src_x,
3621 unsigned src_y,
3622 unsigned src_z,
3623 unsigned copy_height,
3624 unsigned pitch,
3625 unsigned bpp)
3626 {
3627 struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
3628 struct r600_texture *rsrc = (struct r600_texture*)src;
3629 struct r600_texture *rdst = (struct r600_texture*)dst;
3630 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3631 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3632 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3633 uint64_t base, addr;
3634
3635 /* make sure that the dma ring is only one active */
3636 rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
3637
3638 dst_mode = rdst->surface.level[dst_level].mode;
3639 src_mode = rsrc->surface.level[src_level].mode;
3640 /* downcast linear aligned to linear to simplify test */
3641 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3642 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3643 assert(dst_mode != src_mode);
3644
3645 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3646 if (util_format_has_depth(util_format_description(src->format)))
3647 non_disp_tiling = 1;
3648
3649 y = 0;
3650 sub_cmd = 0x8;
3651 lbpp = util_logbase2(bpp);
3652 pitch_tile_max = ((pitch / bpp) >> 3) - 1;
3653 nbanks = eg_num_banks(rctx->screen->tiling_info.num_banks);
3654
3655 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
3656 /* T2L */
3657 array_mode = evergreen_array_mode(src_mode);
3658 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) >> 6;
3659 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3660 /* linear height must be the same as the slice tile max height, it's ok even
3661 * if the linear destination/source have smaller heigh as the size of the
3662 * dma packet will be using the copy_height which is always smaller or equal
3663 * to the linear height
3664 */
3665 height = rsrc->surface.level[src_level].npix_y;
3666 detile = 1;
3667 x = src_x;
3668 y = src_y;
3669 z = src_z;
3670 base = rsrc->surface.level[src_level].offset;
3671 addr = rdst->surface.level[dst_level].offset;
3672 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3673 addr += dst_y * pitch + dst_x * bpp;
3674 bank_h = eg_bank_wh(rsrc->surface.bankh);
3675 bank_w = eg_bank_wh(rsrc->surface.bankw);
3676 mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
3677 tile_split = eg_tile_split(rsrc->surface.tile_split);
3678 base += r600_resource_va(&rctx->screen->b.b, src);
3679 addr += r600_resource_va(&rctx->screen->b.b, dst);
3680 } else {
3681 /* L2T */
3682 array_mode = evergreen_array_mode(dst_mode);
3683 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) >> 6;
3684 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3685 /* linear height must be the same as the slice tile max height, it's ok even
3686 * if the linear destination/source have smaller heigh as the size of the
3687 * dma packet will be using the copy_height which is always smaller or equal
3688 * to the linear height
3689 */
3690 height = rdst->surface.level[dst_level].npix_y;
3691 detile = 0;
3692 x = dst_x;
3693 y = dst_y;
3694 z = dst_z;
3695 base = rdst->surface.level[dst_level].offset;
3696 addr = rsrc->surface.level[src_level].offset;
3697 addr += rsrc->surface.level[src_level].slice_size * src_z;
3698 addr += src_y * pitch + src_x * bpp;
3699 bank_h = eg_bank_wh(rdst->surface.bankh);
3700 bank_w = eg_bank_wh(rdst->surface.bankw);
3701 mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
3702 tile_split = eg_tile_split(rdst->surface.tile_split);
3703 base += r600_resource_va(&rctx->screen->b.b, dst);
3704 addr += r600_resource_va(&rctx->screen->b.b, src);
3705 }
3706
3707 size = (copy_height * pitch) >> 2;
3708 ncopy = (size / 0x000fffff) + !!(size % 0x000fffff);
3709 r600_need_dma_space(rctx, ncopy * 9);
3710
3711 for (i = 0; i < ncopy; i++) {
3712 cheight = copy_height;
3713 if (((cheight * pitch) >> 2) > 0x000fffff) {
3714 cheight = (0x000fffff << 2) / pitch;
3715 }
3716 size = (cheight * pitch) >> 2;
3717 /* emit reloc before writting cs so that cs is always in consistent state */
3718 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ);
3719 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE);
3720 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
3721 cs->buf[cs->cdw++] = base >> 8;
3722 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3723 (lbpp << 24) | (bank_h << 21) |
3724 (bank_w << 18) | (mt_aspect << 16);
3725 cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
3726 cs->buf[cs->cdw++] = (slice_tile_max << 0);
3727 cs->buf[cs->cdw++] = (x << 0) | (z << 18);
3728 cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28);
3729 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3730 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3731 copy_height -= cheight;
3732 addr += cheight * pitch;
3733 y += cheight;
3734 }
3735 }
3736
3737 boolean evergreen_dma_blit(struct pipe_context *ctx,
3738 struct pipe_resource *dst,
3739 unsigned dst_level,
3740 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3741 struct pipe_resource *src,
3742 unsigned src_level,
3743 const struct pipe_box *src_box)
3744 {
3745 struct r600_context *rctx = (struct r600_context *)ctx;
3746 struct r600_texture *rsrc = (struct r600_texture*)src;
3747 struct r600_texture *rdst = (struct r600_texture*)dst;
3748 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3749 unsigned src_w, dst_w;
3750 unsigned src_x, src_y;
3751
3752 if (rctx->b.rings.dma.cs == NULL) {
3753 return FALSE;
3754 }
3755 if (src->format != dst->format) {
3756 return FALSE;
3757 }
3758
3759 src_x = util_format_get_nblocksx(src->format, src_box->x);
3760 dst_x = util_format_get_nblocksx(src->format, dst_x);
3761 src_y = util_format_get_nblocksy(src->format, src_box->y);
3762 dst_y = util_format_get_nblocksy(src->format, dst_y);
3763
3764 bpp = rdst->surface.bpe;
3765 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3766 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3767 src_w = rsrc->surface.level[src_level].npix_x;
3768 dst_w = rdst->surface.level[dst_level].npix_x;
3769 copy_height = src_box->height / rsrc->surface.blk_h;
3770
3771 dst_mode = rdst->surface.level[dst_level].mode;
3772 src_mode = rsrc->surface.level[src_level].mode;
3773 /* downcast linear aligned to linear to simplify test */
3774 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3775 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3776
3777 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3778 /* FIXME evergreen can do partial blit */
3779 return FALSE;
3780 }
3781 /* the x test here are currently useless (because we don't support partial blit)
3782 * but keep them around so we don't forget about those
3783 */
3784 if ((src_pitch & 0x7) || (src_box->x & 0x7) || (dst_x & 0x7) || (src_box->y & 0x7) || (dst_y & 0x7)) {
3785 return FALSE;
3786 }
3787
3788 /* 128 bpp surfaces require non_disp_tiling for both
3789 * tiled and linear buffers on cayman. However, async
3790 * DMA only supports it on the tiled side. As such
3791 * the tile order is backwards after a L2T/T2L packet.
3792 */
3793 if ((rctx->b.chip_class == CAYMAN) &&
3794 (src_mode != dst_mode) &&
3795 (util_format_get_blocksize(src->format) >= 16)) {
3796 return FALSE;
3797 }
3798
3799 if (src_mode == dst_mode) {
3800 uint64_t dst_offset, src_offset;
3801 /* simple dma blit would do NOTE code here assume :
3802 * src_box.x/y == 0
3803 * dst_x/y == 0
3804 * dst_pitch == src_pitch
3805 */
3806 src_offset= rsrc->surface.level[src_level].offset;
3807 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3808 src_offset += src_y * src_pitch + src_x * bpp;
3809 dst_offset = rdst->surface.level[dst_level].offset;
3810 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3811 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3812 evergreen_dma_copy(rctx, dst, src, dst_offset, src_offset,
3813 src_box->height * src_pitch);
3814 } else {
3815 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3816 src, src_level, src_x, src_y, src_box->z,
3817 copy_height, dst_pitch, bpp);
3818 }
3819 return TRUE;
3820 }
3821
3822 void evergreen_init_state_functions(struct r600_context *rctx)
3823 {
3824 unsigned id = 4;
3825
3826 /* !!!
3827 * To avoid GPU lockup registers must be emited in a specific order
3828 * (no kidding ...). The order below is important and have been
3829 * partialy infered from analyzing fglrx command stream.
3830 *
3831 * Don't reorder atom without carefully checking the effect (GPU lockup
3832 * or piglit regression).
3833 * !!!
3834 */
3835
3836 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
3837 /* shader const */
3838 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
3839 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
3840 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
3841 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
3842 /* shader program */
3843 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
3844 /* sampler */
3845 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
3846 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
3847 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
3848 /* resources */
3849 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
3850 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
3851 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
3852 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
3853 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
3854
3855 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 7);
3856
3857 if (rctx->b.chip_class == EVERGREEN) {
3858 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
3859 } else {
3860 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
3861 }
3862 rctx->sample_mask.sample_mask = ~0;
3863
3864 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3865 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3866 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3867 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
3868 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3869 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
3870 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
3871 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
3872 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3873 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
3874 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3875 r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 4);
3876 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3877 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
3878 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
3879 rctx->atoms[id++] = &rctx->b.streamout.begin_atom;
3880 r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23);
3881 r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0);
3882
3883 rctx->b.b.create_blend_state = evergreen_create_blend_state;
3884 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
3885 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
3886 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
3887 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
3888 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
3889 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
3890 rctx->b.b.set_scissor_states = evergreen_set_scissor_states;
3891
3892 if (rctx->b.chip_class == EVERGREEN)
3893 rctx->b.b.get_sample_position = evergreen_get_sample_position;
3894 else
3895 rctx->b.b.get_sample_position = cayman_get_sample_position;
3896 evergreen_init_compute_state_functions(rctx);
3897 }