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r600g: fix up the rules for enabling SOURCE_FORMAT(EXPORT_NORM)
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "eg_state_inlines.h"
50
51 static void evergreen_set_blend_color(struct pipe_context *ctx,
52 const struct pipe_blend_color *state)
53 {
54 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
55 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
56
57 if (rstate == NULL)
58 return;
59
60 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
61 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
62 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
63 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
65
66 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
67 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
68 r600_context_pipe_state_set(&rctx->ctx, rstate);
69 }
70
71 static void *evergreen_create_blend_state(struct pipe_context *ctx,
72 const struct pipe_blend_state *state)
73 {
74 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
75 struct r600_pipe_state *rstate;
76 u32 color_control, target_mask;
77 /* FIXME there is more then 8 framebuffer */
78 unsigned blend_cntl[8];
79
80 if (blend == NULL) {
81 return NULL;
82 }
83 rstate = &blend->rstate;
84
85 rstate->id = R600_PIPE_STATE_BLEND;
86
87 target_mask = 0;
88 color_control = S_028808_MODE(1);
89 if (state->logicop_enable) {
90 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
91 } else {
92 color_control |= (0xcc << 16);
93 }
94 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
95 if (state->independent_blend_enable) {
96 for (int i = 0; i < 8; i++) {
97 target_mask |= (state->rt[i].colormask << (4 * i));
98 }
99 } else {
100 for (int i = 0; i < 8; i++) {
101 target_mask |= (state->rt[0].colormask << (4 * i));
102 }
103 }
104 blend->cb_target_mask = target_mask;
105 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
106 color_control, 0xFFFFFFFD, NULL);
107 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
108
109 for (int i = 0; i < 8; i++) {
110 /* state->rt entries > 0 only written if independent blending */
111 const int j = state->independent_blend_enable ? i : 0;
112
113 unsigned eqRGB = state->rt[j].rgb_func;
114 unsigned srcRGB = state->rt[j].rgb_src_factor;
115 unsigned dstRGB = state->rt[j].rgb_dst_factor;
116 unsigned eqA = state->rt[j].alpha_func;
117 unsigned srcA = state->rt[j].alpha_src_factor;
118 unsigned dstA = state->rt[j].alpha_dst_factor;
119
120 blend_cntl[i] = 0;
121 if (!state->rt[j].blend_enable)
122 continue;
123
124 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
125 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
126 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
127 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
128
129 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
130 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
131 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
132 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
133 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
134 }
135 }
136 for (int i = 0; i < 8; i++) {
137 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
138 }
139
140 return rstate;
141 }
142
143 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
144 const struct pipe_depth_stencil_alpha_state *state)
145 {
146 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
147 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
148 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
149 struct r600_pipe_state *rstate;
150
151 if (dsa == NULL) {
152 return NULL;
153 }
154
155 rstate = &dsa->rstate;
156
157 rstate->id = R600_PIPE_STATE_DSA;
158 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
159 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
160 stencil_ref_mask = 0;
161 stencil_ref_mask_bf = 0;
162 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
163 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
164 S_028800_ZFUNC(state->depth.func);
165
166 /* stencil */
167 if (state->stencil[0].enabled) {
168 db_depth_control |= S_028800_STENCIL_ENABLE(1);
169 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
170 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
171 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
172 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
173
174
175 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
176 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
177 if (state->stencil[1].enabled) {
178 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
179 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
180 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
181 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
182 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
183 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
184 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
185 }
186 }
187
188 /* alpha */
189 alpha_test_control = 0;
190 alpha_ref = 0;
191 if (state->alpha.enabled) {
192 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
193 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
194 alpha_ref = fui(state->alpha.ref_value);
195 }
196 dsa->alpha_ref = alpha_ref;
197
198 /* misc */
199 db_render_control = 0;
200 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
201 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
202 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
203 /* TODO db_render_override depends on query */
204 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
205 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
206 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
207 r600_pipe_state_add_reg(rstate,
208 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
209 0xFFFFFFFF & C_028430_STENCILREF, NULL);
210 r600_pipe_state_add_reg(rstate,
211 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
212 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
213 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
214 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
215 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
216 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
217 * evergreen_pipe_shader_ps().*/
218 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL);
219 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
220 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
221 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
222 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
223 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
224 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
225
226 return rstate;
227 }
228
229 static void *evergreen_create_rs_state(struct pipe_context *ctx,
230 const struct pipe_rasterizer_state *state)
231 {
232 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
233 struct r600_pipe_state *rstate;
234 unsigned tmp;
235 unsigned prov_vtx = 1, polygon_dual_mode;
236 unsigned clip_rule;
237
238 if (rs == NULL) {
239 return NULL;
240 }
241
242 rstate = &rs->rstate;
243 rs->flatshade = state->flatshade;
244 rs->sprite_coord_enable = state->sprite_coord_enable;
245
246 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
247
248 /* offset */
249 rs->offset_units = state->offset_units;
250 rs->offset_scale = state->offset_scale * 12.0f;
251
252 rstate->id = R600_PIPE_STATE_RASTERIZER;
253 if (state->flatshade_first)
254 prov_vtx = 0;
255 tmp = S_0286D4_FLAT_SHADE_ENA(1);
256 if (state->sprite_coord_enable) {
257 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
258 S_0286D4_PNT_SPRITE_OVRD_X(2) |
259 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
260 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
261 S_0286D4_PNT_SPRITE_OVRD_W(1);
262 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
263 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
264 }
265 }
266 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
267
268 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
269 state->fill_back != PIPE_POLYGON_MODE_FILL);
270 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
271 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
272 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
273 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
274 S_028814_FACE(!state->front_ccw) |
275 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
276 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
277 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
278 S_028814_POLY_MODE(polygon_dual_mode) |
279 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
280 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
281 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
282 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
283 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
284 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
285 /* point size 12.4 fixed point */
286 tmp = (unsigned)(state->point_size * 8.0);
287 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
288 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
289
290 tmp = (unsigned)state->line_width * 8;
291 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
292
293 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
294 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
295 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
296 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
297 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
298 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
299
300 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
301 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
302 0xFFFFFFFF, NULL);
303
304 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
305 return rstate;
306 }
307
308 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
309 const struct pipe_sampler_state *state)
310 {
311 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
312 union util_color uc;
313
314 if (rstate == NULL) {
315 return NULL;
316 }
317
318 rstate->id = R600_PIPE_STATE_SAMPLER;
319 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
320 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
321 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
322 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
323 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
324 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
325 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
326 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
327 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
328 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
329 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
330 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
331 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
332 0xFFFFFFFF, NULL);
333 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
334 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
335 S_03C008_TYPE(1),
336 0xFFFFFFFF, NULL);
337
338 if (uc.ui) {
339 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
340 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
341 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
342 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
343 }
344 return rstate;
345 }
346
347 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
348 struct pipe_resource *texture,
349 const struct pipe_sampler_view *state)
350 {
351 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
352 struct r600_pipe_state *rstate;
353 const struct util_format_description *desc;
354 struct r600_resource_texture *tmp;
355 struct r600_resource *rbuffer;
356 unsigned format, endian;
357 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
358 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
359 struct r600_bo *bo[2];
360
361 if (resource == NULL)
362 return NULL;
363 rstate = &resource->state;
364
365 /* initialize base object */
366 resource->base = *state;
367 resource->base.texture = NULL;
368 pipe_reference(NULL, &texture->reference);
369 resource->base.texture = texture;
370 resource->base.reference.count = 1;
371 resource->base.context = ctx;
372
373 swizzle[0] = state->swizzle_r;
374 swizzle[1] = state->swizzle_g;
375 swizzle[2] = state->swizzle_b;
376 swizzle[3] = state->swizzle_a;
377 format = r600_translate_texformat(ctx->screen, state->format,
378 swizzle,
379 &word4, &yuv_format);
380 if (format == ~0) {
381 format = 0;
382 }
383 desc = util_format_description(state->format);
384 if (desc == NULL) {
385 R600_ERR("unknow format %d\n", state->format);
386 }
387 tmp = (struct r600_resource_texture *)texture;
388 if (tmp->depth && !tmp->is_flushing_texture) {
389 r600_texture_depth_flush(ctx, texture, TRUE);
390 tmp = tmp->flushed_depth_texture;
391 }
392
393 endian = r600_colorformat_endian_swap(format);
394
395 if (tmp->force_int_type) {
396 word4 &= C_030010_NUM_FORMAT_ALL;
397 word4 |= S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_INT);
398 }
399
400 rbuffer = &tmp->resource;
401 bo[0] = rbuffer->bo;
402 bo[1] = rbuffer->bo;
403
404 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
405 array_mode = tmp->array_mode[0];
406 tile_type = tmp->tile_type;
407
408 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
409 S_030000_DIM(r600_tex_dim(texture->target)) |
410 S_030000_PITCH((pitch / 8) - 1) |
411 S_030000_NON_DISP_TILING_ORDER(tile_type) |
412 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
413 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
414 S_030004_TEX_HEIGHT(texture->height0 - 1) |
415 S_030004_TEX_DEPTH(texture->depth0 - 1) |
416 S_030004_ARRAY_MODE(array_mode),
417 0xFFFFFFFF, NULL);
418 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
419 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
420 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
421 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
422 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
423 word4 |
424 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_NO_ZERO) |
425 S_030010_ENDIAN_SWAP(endian) |
426 S_030010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
427 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
428 S_030014_LAST_LEVEL(state->u.tex.last_level) |
429 S_030014_BASE_ARRAY(0) |
430 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
431 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
432 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
433 S_03001C_DATA_FORMAT(format) |
434 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
435
436 return &resource->base;
437 }
438
439 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
440 struct pipe_sampler_view **views)
441 {
442 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
443 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
444
445 for (int i = 0; i < count; i++) {
446 if (resource[i]) {
447 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
448 i + R600_MAX_CONST_BUFFERS);
449 }
450 }
451 }
452
453 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
454 struct pipe_sampler_view **views)
455 {
456 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
457 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
458 int i;
459
460 for (i = 0; i < count; i++) {
461 if (&rctx->ps_samplers.views[i]->base != views[i]) {
462 if (resource[i])
463 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
464 i + R600_MAX_CONST_BUFFERS);
465 else
466 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
467 i + R600_MAX_CONST_BUFFERS);
468
469 pipe_sampler_view_reference(
470 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
471 views[i]);
472 }
473 }
474 for (i = count; i < NUM_TEX_UNITS; i++) {
475 if (rctx->ps_samplers.views[i]) {
476 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
477 i + R600_MAX_CONST_BUFFERS);
478 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
479 }
480 }
481 rctx->ps_samplers.n_views = count;
482 }
483
484 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
485 {
486 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
487 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
488
489
490 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
491 rctx->ps_samplers.n_samplers = count;
492
493 for (int i = 0; i < count; i++) {
494 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
495 }
496 }
497
498 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
499 {
500 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
501 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
502
503 for (int i = 0; i < count; i++) {
504 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
505 }
506 }
507
508 static void evergreen_set_clip_state(struct pipe_context *ctx,
509 const struct pipe_clip_state *state)
510 {
511 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
512 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
513
514 if (rstate == NULL)
515 return;
516
517 rctx->clip = *state;
518 rstate->id = R600_PIPE_STATE_CLIP;
519 for (int i = 0; i < state->nr; i++) {
520 r600_pipe_state_add_reg(rstate,
521 R_0285BC_PA_CL_UCP0_X + i * 16,
522 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
523 r600_pipe_state_add_reg(rstate,
524 R_0285C0_PA_CL_UCP0_Y + i * 16,
525 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
526 r600_pipe_state_add_reg(rstate,
527 R_0285C4_PA_CL_UCP0_Z + i * 16,
528 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
529 r600_pipe_state_add_reg(rstate,
530 R_0285C8_PA_CL_UCP0_W + i * 16,
531 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
532 }
533 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
534 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
535 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
536 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
537
538 free(rctx->states[R600_PIPE_STATE_CLIP]);
539 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
540 r600_context_pipe_state_set(&rctx->ctx, rstate);
541 }
542
543 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
544 const struct pipe_poly_stipple *state)
545 {
546 }
547
548 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
549 {
550 }
551
552 static void evergreen_set_scissor_state(struct pipe_context *ctx,
553 const struct pipe_scissor_state *state)
554 {
555 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
556 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
557 u32 tl, br;
558
559 if (rstate == NULL)
560 return;
561
562 rstate->id = R600_PIPE_STATE_SCISSOR;
563 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
564 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
565 r600_pipe_state_add_reg(rstate,
566 R_028210_PA_SC_CLIPRECT_0_TL, tl,
567 0xFFFFFFFF, NULL);
568 r600_pipe_state_add_reg(rstate,
569 R_028214_PA_SC_CLIPRECT_0_BR, br,
570 0xFFFFFFFF, NULL);
571 r600_pipe_state_add_reg(rstate,
572 R_028218_PA_SC_CLIPRECT_1_TL, tl,
573 0xFFFFFFFF, NULL);
574 r600_pipe_state_add_reg(rstate,
575 R_02821C_PA_SC_CLIPRECT_1_BR, br,
576 0xFFFFFFFF, NULL);
577 r600_pipe_state_add_reg(rstate,
578 R_028220_PA_SC_CLIPRECT_2_TL, tl,
579 0xFFFFFFFF, NULL);
580 r600_pipe_state_add_reg(rstate,
581 R_028224_PA_SC_CLIPRECT_2_BR, br,
582 0xFFFFFFFF, NULL);
583 r600_pipe_state_add_reg(rstate,
584 R_028228_PA_SC_CLIPRECT_3_TL, tl,
585 0xFFFFFFFF, NULL);
586 r600_pipe_state_add_reg(rstate,
587 R_02822C_PA_SC_CLIPRECT_3_BR, br,
588 0xFFFFFFFF, NULL);
589
590 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
591 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
592 r600_context_pipe_state_set(&rctx->ctx, rstate);
593 }
594
595 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
596 const struct pipe_stencil_ref *state)
597 {
598 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
599 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
600 u32 tmp;
601
602 if (rstate == NULL)
603 return;
604
605 rctx->stencil_ref = *state;
606 rstate->id = R600_PIPE_STATE_STENCIL_REF;
607 tmp = S_028430_STENCILREF(state->ref_value[0]);
608 r600_pipe_state_add_reg(rstate,
609 R_028430_DB_STENCILREFMASK, tmp,
610 ~C_028430_STENCILREF, NULL);
611 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
612 r600_pipe_state_add_reg(rstate,
613 R_028434_DB_STENCILREFMASK_BF, tmp,
614 ~C_028434_STENCILREF_BF, NULL);
615
616 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
617 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
618 r600_context_pipe_state_set(&rctx->ctx, rstate);
619 }
620
621 static void evergreen_set_viewport_state(struct pipe_context *ctx,
622 const struct pipe_viewport_state *state)
623 {
624 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
625 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
626
627 if (rstate == NULL)
628 return;
629
630 rctx->viewport = *state;
631 rstate->id = R600_PIPE_STATE_VIEWPORT;
632 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
633 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
634 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
635 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
636 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
637 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
638 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
639 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
640 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
641
642 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
643 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
644 r600_context_pipe_state_set(&rctx->ctx, rstate);
645 }
646
647 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
648 const struct pipe_framebuffer_state *state, int cb)
649 {
650 struct r600_resource_texture *rtex;
651 struct r600_resource *rbuffer;
652 struct r600_surface *surf;
653 unsigned level = state->cbufs[cb]->u.tex.level;
654 unsigned pitch, slice;
655 unsigned color_info;
656 unsigned format, swap, ntype, endian;
657 unsigned offset;
658 unsigned tile_type;
659 const struct util_format_description *desc;
660 struct r600_bo *bo[3];
661 int i;
662
663 surf = (struct r600_surface *)state->cbufs[cb];
664 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
665
666 if (rtex->depth && !rtex->is_flushing_texture) {
667 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
668 rtex = rtex->flushed_depth_texture;
669 }
670
671 rbuffer = &rtex->resource;
672 bo[0] = rbuffer->bo;
673 bo[1] = rbuffer->bo;
674 bo[2] = rbuffer->bo;
675
676 /* XXX quite sure for dx10+ hw don't need any offset hacks */
677 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
678 level, state->cbufs[cb]->u.tex.first_layer);
679 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
680 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
681 desc = util_format_description(surf->base.format);
682 for (i = 0; i < 4; i++) {
683 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
684 break;
685 }
686 }
687 ntype = V_028C70_NUMBER_UNORM;
688 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
689 ntype = V_028C70_NUMBER_SRGB;
690 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
691 ntype = V_028C70_NUMBER_SNORM;
692
693 format = r600_translate_colorformat(surf->base.format);
694 swap = r600_translate_colorswap(surf->base.format);
695 if (rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
696 endian = ENDIAN_NONE;
697 } else {
698 endian = r600_colorformat_endian_swap(format);
699 }
700
701 /* disable when gallium grows int textures */
702 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
703 ntype = V_028C70_NUMBER_UINT;
704
705 color_info = S_028C70_FORMAT(format) |
706 S_028C70_COMP_SWAP(swap) |
707 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
708 S_028C70_BLEND_CLAMP(1) |
709 S_028C70_NUMBER_TYPE(ntype) |
710 S_028C70_ENDIAN(endian);
711
712
713 /* EXPORT_NORM is an optimzation that can be enabled for better
714 * performance in certain cases.
715 * EXPORT_NORM can be enabled if:
716 * - 11-bit or smaller UNORM/SNORM/SRGB
717 * - 16-bit or smaller FLOAT
718 */
719 /* FIXME: This should probably be the same for all CBs if we want
720 * useful alpha tests. */
721 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
722 ((desc->channel[i].size < 12 &&
723 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
724 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
725 (desc->channel[i].size < 17 &&
726 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
727 rctx->export_16bpc = true;
728 } else {
729 rctx->export_16bpc = false;
730 }
731 rctx->alpha_ref_dirty = true;
732
733 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
734 tile_type = rtex->tile_type;
735 } else /* workaround for linear buffers */
736 tile_type = 1;
737
738 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
739 r600_pipe_state_add_reg(rstate,
740 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
741 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
742 r600_pipe_state_add_reg(rstate,
743 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
744 0x0, 0xFFFFFFFF, NULL);
745 r600_pipe_state_add_reg(rstate,
746 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
747 color_info, 0xFFFFFFFF, bo[0]);
748 r600_pipe_state_add_reg(rstate,
749 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
750 S_028C64_PITCH_TILE_MAX(pitch),
751 0xFFFFFFFF, NULL);
752 r600_pipe_state_add_reg(rstate,
753 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
754 S_028C68_SLICE_TILE_MAX(slice),
755 0xFFFFFFFF, NULL);
756 r600_pipe_state_add_reg(rstate,
757 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
758 0x00000000, 0xFFFFFFFF, NULL);
759 r600_pipe_state_add_reg(rstate,
760 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
761 S_028C74_NON_DISP_TILING_ORDER(tile_type),
762 0xFFFFFFFF, bo[0]);
763 }
764
765 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
766 const struct pipe_framebuffer_state *state)
767 {
768 struct r600_resource_texture *rtex;
769 struct r600_resource *rbuffer;
770 struct r600_surface *surf;
771 unsigned level;
772 unsigned pitch, slice, format, stencil_format;
773 unsigned offset;
774
775 if (state->zsbuf == NULL)
776 return;
777
778 level = state->zsbuf->u.tex.level;
779
780 surf = (struct r600_surface *)state->zsbuf;
781 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
782
783 rbuffer = &rtex->resource;
784
785 /* XXX quite sure for dx10+ hw don't need any offset hacks */
786 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
787 level, state->zsbuf->u.tex.first_layer);
788 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
789 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
790 format = r600_translate_dbformat(state->zsbuf->texture->format);
791 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
792
793 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
794 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
795 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
796 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
797
798 if (stencil_format) {
799 uint32_t stencil_offset;
800
801 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
802 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
803 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
804 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
805 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
806 }
807
808 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
809 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
810 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
811
812 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
813 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
814 0xFFFFFFFF, rbuffer->bo);
815 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
816 S_028058_PITCH_TILE_MAX(pitch),
817 0xFFFFFFFF, NULL);
818 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
819 S_02805C_SLICE_TILE_MAX(slice),
820 0xFFFFFFFF, NULL);
821 }
822
823 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
824 const struct pipe_framebuffer_state *state)
825 {
826 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
827 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
828 u32 shader_mask, tl, br, target_mask;
829
830 if (rstate == NULL)
831 return;
832
833 evergreen_context_flush_dest_caches(&rctx->ctx);
834 rctx->ctx.num_dest_buffers = state->nr_cbufs;
835
836 /* unreference old buffer and reference new one */
837 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
838
839 util_copy_framebuffer_state(&rctx->framebuffer, state);
840
841 /* build states */
842 for (int i = 0; i < state->nr_cbufs; i++) {
843 evergreen_cb(rctx, rstate, state, i);
844 }
845 if (state->zsbuf) {
846 evergreen_db(rctx, rstate, state);
847 rctx->ctx.num_dest_buffers++;
848 }
849
850 target_mask = 0x00000000;
851 target_mask = 0xFFFFFFFF;
852 shader_mask = 0;
853 for (int i = 0; i < state->nr_cbufs; i++) {
854 target_mask ^= 0xf << (i * 4);
855 shader_mask |= 0xf << (i * 4);
856 }
857 tl = S_028240_TL_X(0) | S_028240_TL_Y(0);
858 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
859
860 r600_pipe_state_add_reg(rstate,
861 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
862 0xFFFFFFFF, NULL);
863 r600_pipe_state_add_reg(rstate,
864 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
865 0xFFFFFFFF, NULL);
866 r600_pipe_state_add_reg(rstate,
867 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
868 0xFFFFFFFF, NULL);
869 r600_pipe_state_add_reg(rstate,
870 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
871 0xFFFFFFFF, NULL);
872 r600_pipe_state_add_reg(rstate,
873 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
874 0xFFFFFFFF, NULL);
875 r600_pipe_state_add_reg(rstate,
876 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
877 0xFFFFFFFF, NULL);
878 r600_pipe_state_add_reg(rstate,
879 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
880 0xFFFFFFFF, NULL);
881 r600_pipe_state_add_reg(rstate,
882 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
883 0xFFFFFFFF, NULL);
884 r600_pipe_state_add_reg(rstate,
885 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
886 0xFFFFFFFF, NULL);
887 r600_pipe_state_add_reg(rstate,
888 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
889 0xFFFFFFFF, NULL);
890
891 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
892 0x00000000, target_mask, NULL);
893 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
894 shader_mask, 0xFFFFFFFF, NULL);
895 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
896 0x00000000, 0xFFFFFFFF, NULL);
897 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
898 0x00000000, 0xFFFFFFFF, NULL);
899
900 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
901 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
902 r600_context_pipe_state_set(&rctx->ctx, rstate);
903
904 if (state->zsbuf) {
905 evergreen_polygon_offset_update(rctx);
906 }
907 }
908
909 static void evergreen_texture_barrier(struct pipe_context *ctx)
910 {
911 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
912
913 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
914 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
915 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
916 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
917 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
918 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
919 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
920 }
921
922 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
923 {
924 rctx->context.create_blend_state = evergreen_create_blend_state;
925 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
926 rctx->context.create_fs_state = r600_create_shader_state;
927 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
928 rctx->context.create_sampler_state = evergreen_create_sampler_state;
929 rctx->context.create_sampler_view = evergreen_create_sampler_view;
930 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
931 rctx->context.create_vs_state = r600_create_shader_state;
932 rctx->context.bind_blend_state = r600_bind_blend_state;
933 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
934 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
935 rctx->context.bind_fs_state = r600_bind_ps_shader;
936 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
937 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
938 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
939 rctx->context.bind_vs_state = r600_bind_vs_shader;
940 rctx->context.delete_blend_state = r600_delete_state;
941 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
942 rctx->context.delete_fs_state = r600_delete_ps_shader;
943 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
944 rctx->context.delete_sampler_state = r600_delete_state;
945 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
946 rctx->context.delete_vs_state = r600_delete_vs_shader;
947 rctx->context.set_blend_color = evergreen_set_blend_color;
948 rctx->context.set_clip_state = evergreen_set_clip_state;
949 rctx->context.set_constant_buffer = r600_set_constant_buffer;
950 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
951 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
952 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
953 rctx->context.set_sample_mask = evergreen_set_sample_mask;
954 rctx->context.set_scissor_state = evergreen_set_scissor_state;
955 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
956 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
957 rctx->context.set_index_buffer = r600_set_index_buffer;
958 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
959 rctx->context.set_viewport_state = evergreen_set_viewport_state;
960 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
961 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
962 rctx->context.texture_barrier = evergreen_texture_barrier;
963 }
964
965 void evergreen_init_config(struct r600_pipe_context *rctx)
966 {
967 struct r600_pipe_state *rstate = &rctx->config;
968 int ps_prio;
969 int vs_prio;
970 int gs_prio;
971 int es_prio;
972 int hs_prio, cs_prio, ls_prio;
973 int num_ps_gprs;
974 int num_vs_gprs;
975 int num_gs_gprs;
976 int num_es_gprs;
977 int num_hs_gprs;
978 int num_ls_gprs;
979 int num_temp_gprs;
980 int num_ps_threads;
981 int num_vs_threads;
982 int num_gs_threads;
983 int num_es_threads;
984 int num_hs_threads;
985 int num_ls_threads;
986 int num_ps_stack_entries;
987 int num_vs_stack_entries;
988 int num_gs_stack_entries;
989 int num_es_stack_entries;
990 int num_hs_stack_entries;
991 int num_ls_stack_entries;
992 enum radeon_family family;
993 unsigned tmp;
994
995 family = r600_get_family(rctx->radeon);
996 ps_prio = 0;
997 vs_prio = 1;
998 gs_prio = 2;
999 es_prio = 3;
1000 hs_prio = 0;
1001 ls_prio = 0;
1002 cs_prio = 0;
1003
1004 switch (family) {
1005 case CHIP_CEDAR:
1006 default:
1007 num_ps_gprs = 93;
1008 num_vs_gprs = 46;
1009 num_temp_gprs = 4;
1010 num_gs_gprs = 31;
1011 num_es_gprs = 31;
1012 num_hs_gprs = 23;
1013 num_ls_gprs = 23;
1014 num_ps_threads = 96;
1015 num_vs_threads = 16;
1016 num_gs_threads = 16;
1017 num_es_threads = 16;
1018 num_hs_threads = 16;
1019 num_ls_threads = 16;
1020 num_ps_stack_entries = 42;
1021 num_vs_stack_entries = 42;
1022 num_gs_stack_entries = 42;
1023 num_es_stack_entries = 42;
1024 num_hs_stack_entries = 42;
1025 num_ls_stack_entries = 42;
1026 break;
1027 case CHIP_REDWOOD:
1028 num_ps_gprs = 93;
1029 num_vs_gprs = 46;
1030 num_temp_gprs = 4;
1031 num_gs_gprs = 31;
1032 num_es_gprs = 31;
1033 num_hs_gprs = 23;
1034 num_ls_gprs = 23;
1035 num_ps_threads = 128;
1036 num_vs_threads = 20;
1037 num_gs_threads = 20;
1038 num_es_threads = 20;
1039 num_hs_threads = 20;
1040 num_ls_threads = 20;
1041 num_ps_stack_entries = 42;
1042 num_vs_stack_entries = 42;
1043 num_gs_stack_entries = 42;
1044 num_es_stack_entries = 42;
1045 num_hs_stack_entries = 42;
1046 num_ls_stack_entries = 42;
1047 break;
1048 case CHIP_JUNIPER:
1049 num_ps_gprs = 93;
1050 num_vs_gprs = 46;
1051 num_temp_gprs = 4;
1052 num_gs_gprs = 31;
1053 num_es_gprs = 31;
1054 num_hs_gprs = 23;
1055 num_ls_gprs = 23;
1056 num_ps_threads = 128;
1057 num_vs_threads = 20;
1058 num_gs_threads = 20;
1059 num_es_threads = 20;
1060 num_hs_threads = 20;
1061 num_ls_threads = 20;
1062 num_ps_stack_entries = 85;
1063 num_vs_stack_entries = 85;
1064 num_gs_stack_entries = 85;
1065 num_es_stack_entries = 85;
1066 num_hs_stack_entries = 85;
1067 num_ls_stack_entries = 85;
1068 break;
1069 case CHIP_CYPRESS:
1070 case CHIP_HEMLOCK:
1071 num_ps_gprs = 93;
1072 num_vs_gprs = 46;
1073 num_temp_gprs = 4;
1074 num_gs_gprs = 31;
1075 num_es_gprs = 31;
1076 num_hs_gprs = 23;
1077 num_ls_gprs = 23;
1078 num_ps_threads = 128;
1079 num_vs_threads = 20;
1080 num_gs_threads = 20;
1081 num_es_threads = 20;
1082 num_hs_threads = 20;
1083 num_ls_threads = 20;
1084 num_ps_stack_entries = 85;
1085 num_vs_stack_entries = 85;
1086 num_gs_stack_entries = 85;
1087 num_es_stack_entries = 85;
1088 num_hs_stack_entries = 85;
1089 num_ls_stack_entries = 85;
1090 break;
1091 case CHIP_PALM:
1092 num_ps_gprs = 93;
1093 num_vs_gprs = 46;
1094 num_temp_gprs = 4;
1095 num_gs_gprs = 31;
1096 num_es_gprs = 31;
1097 num_hs_gprs = 23;
1098 num_ls_gprs = 23;
1099 num_ps_threads = 96;
1100 num_vs_threads = 16;
1101 num_gs_threads = 16;
1102 num_es_threads = 16;
1103 num_hs_threads = 16;
1104 num_ls_threads = 16;
1105 num_ps_stack_entries = 42;
1106 num_vs_stack_entries = 42;
1107 num_gs_stack_entries = 42;
1108 num_es_stack_entries = 42;
1109 num_hs_stack_entries = 42;
1110 num_ls_stack_entries = 42;
1111 break;
1112 case CHIP_BARTS:
1113 num_ps_gprs = 93;
1114 num_vs_gprs = 46;
1115 num_temp_gprs = 4;
1116 num_gs_gprs = 31;
1117 num_es_gprs = 31;
1118 num_hs_gprs = 23;
1119 num_ls_gprs = 23;
1120 num_ps_threads = 128;
1121 num_vs_threads = 20;
1122 num_gs_threads = 20;
1123 num_es_threads = 20;
1124 num_hs_threads = 20;
1125 num_ls_threads = 20;
1126 num_ps_stack_entries = 85;
1127 num_vs_stack_entries = 85;
1128 num_gs_stack_entries = 85;
1129 num_es_stack_entries = 85;
1130 num_hs_stack_entries = 85;
1131 num_ls_stack_entries = 85;
1132 break;
1133 case CHIP_TURKS:
1134 num_ps_gprs = 93;
1135 num_vs_gprs = 46;
1136 num_temp_gprs = 4;
1137 num_gs_gprs = 31;
1138 num_es_gprs = 31;
1139 num_hs_gprs = 23;
1140 num_ls_gprs = 23;
1141 num_ps_threads = 128;
1142 num_vs_threads = 20;
1143 num_gs_threads = 20;
1144 num_es_threads = 20;
1145 num_hs_threads = 20;
1146 num_ls_threads = 20;
1147 num_ps_stack_entries = 42;
1148 num_vs_stack_entries = 42;
1149 num_gs_stack_entries = 42;
1150 num_es_stack_entries = 42;
1151 num_hs_stack_entries = 42;
1152 num_ls_stack_entries = 42;
1153 break;
1154 case CHIP_CAICOS:
1155 num_ps_gprs = 93;
1156 num_vs_gprs = 46;
1157 num_temp_gprs = 4;
1158 num_gs_gprs = 31;
1159 num_es_gprs = 31;
1160 num_hs_gprs = 23;
1161 num_ls_gprs = 23;
1162 num_ps_threads = 128;
1163 num_vs_threads = 10;
1164 num_gs_threads = 10;
1165 num_es_threads = 10;
1166 num_hs_threads = 10;
1167 num_ls_threads = 10;
1168 num_ps_stack_entries = 42;
1169 num_vs_stack_entries = 42;
1170 num_gs_stack_entries = 42;
1171 num_es_stack_entries = 42;
1172 num_hs_stack_entries = 42;
1173 num_ls_stack_entries = 42;
1174 break;
1175 }
1176
1177 tmp = 0x00000000;
1178 switch (family) {
1179 case CHIP_CEDAR:
1180 case CHIP_PALM:
1181 case CHIP_CAICOS:
1182 break;
1183 default:
1184 tmp |= S_008C00_VC_ENABLE(1);
1185 break;
1186 }
1187 tmp |= S_008C00_EXPORT_SRC_C(1);
1188 tmp |= S_008C00_CS_PRIO(cs_prio);
1189 tmp |= S_008C00_LS_PRIO(ls_prio);
1190 tmp |= S_008C00_HS_PRIO(hs_prio);
1191 tmp |= S_008C00_PS_PRIO(ps_prio);
1192 tmp |= S_008C00_VS_PRIO(vs_prio);
1193 tmp |= S_008C00_GS_PRIO(gs_prio);
1194 tmp |= S_008C00_ES_PRIO(es_prio);
1195 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1196
1197 tmp = 0;
1198 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1199 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1200 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1201 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1202
1203 tmp = 0;
1204 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1205 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1206 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1207
1208 tmp = 0;
1209 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1210 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1211 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1212
1213 tmp = 0;
1214 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1215 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1216 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1217 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1218 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1219
1220 tmp = 0;
1221 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1222 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1223 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1224
1225 tmp = 0;
1226 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1227 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1228 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1229
1230 tmp = 0;
1231 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1232 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1233 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1234
1235 tmp = 0;
1236 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1237 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1238 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1239
1240 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1241 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1242
1243 #if 0
1244 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1245
1246 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1247 #endif
1248 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1249 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1250
1251 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1252 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1253 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1254 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1255 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1256 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1257
1258 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1259 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1260 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1261 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1262
1263 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1264 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1265 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1266 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1267 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1268 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1269 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1270 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1271 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1272 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1273 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1274 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1275 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1276 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1277 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1278 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1279 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1280 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1281
1282 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1283 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1284 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1285 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1286 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1287 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1288 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1289 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1290 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1291 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1292 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1293 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1294 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1295 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1296 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1297 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1298 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1299 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1300 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1301 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1302 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1303 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1304 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1305 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1306 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1307 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1308 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1309 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1310 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1311 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1312 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1313 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1314
1315 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
1316
1317 r600_context_pipe_state_set(&rctx->ctx, rstate);
1318 }
1319
1320 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
1321 {
1322 struct r600_pipe_state state;
1323
1324 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
1325 state.nregs = 0;
1326 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1327 float offset_units = rctx->rasterizer->offset_units;
1328 unsigned offset_db_fmt_cntl = 0, depth;
1329
1330 switch (rctx->framebuffer.zsbuf->texture->format) {
1331 case PIPE_FORMAT_Z24X8_UNORM:
1332 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1333 depth = -24;
1334 offset_units *= 2.0f;
1335 break;
1336 case PIPE_FORMAT_Z32_FLOAT:
1337 depth = -23;
1338 offset_units *= 1.0f;
1339 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1340 break;
1341 case PIPE_FORMAT_Z16_UNORM:
1342 depth = -16;
1343 offset_units *= 4.0f;
1344 break;
1345 default:
1346 return;
1347 }
1348 /* FIXME some of those reg can be computed with cso */
1349 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1350 r600_pipe_state_add_reg(&state,
1351 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1352 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1353 r600_pipe_state_add_reg(&state,
1354 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1355 fui(offset_units), 0xFFFFFFFF, NULL);
1356 r600_pipe_state_add_reg(&state,
1357 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1358 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1359 r600_pipe_state_add_reg(&state,
1360 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1361 fui(offset_units), 0xFFFFFFFF, NULL);
1362 r600_pipe_state_add_reg(&state,
1363 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1364 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1365 r600_context_pipe_state_set(&rctx->ctx, &state);
1366 }
1367 }
1368
1369 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1370 {
1371 struct r600_pipe_state *rstate = &shader->rstate;
1372 struct r600_shader *rshader = &shader->shader;
1373 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
1374 int pos_index = -1, face_index = -1;
1375 int ninterp = 0;
1376 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1377 unsigned spi_baryc_cntl;
1378
1379 rstate->nregs = 0;
1380
1381 db_shader_control = 0;
1382 for (i = 0; i < rshader->ninput; i++) {
1383 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1384 POSITION goes via GPRs from the SC so isn't counted */
1385 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1386 pos_index = i;
1387 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1388 face_index = i;
1389 else {
1390 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
1391 rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1392 ninterp++;
1393 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1394 have_linear = TRUE;
1395 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1396 have_perspective = TRUE;
1397 if (rshader->input[i].centroid)
1398 have_centroid = TRUE;
1399 }
1400 }
1401 for (i = 0; i < rshader->noutput; i++) {
1402 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1403 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1404 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1405 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
1406 }
1407 if (rshader->uses_kill)
1408 db_shader_control |= S_02880C_KILL_ENABLE(1);
1409
1410 exports_ps = 0;
1411 num_cout = 0;
1412 for (i = 0; i < rshader->noutput; i++) {
1413 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1414 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1415 exports_ps |= 1;
1416 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1417 num_cout++;
1418 }
1419 }
1420 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1421 if (!exports_ps) {
1422 /* always at least export 1 component per pixel */
1423 exports_ps = 2;
1424 }
1425
1426 if (ninterp == 0) {
1427 ninterp = 1;
1428 have_perspective = TRUE;
1429 }
1430
1431 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
1432 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
1433 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
1434 spi_input_z = 0;
1435 if (pos_index != -1) {
1436 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
1437 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1438 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
1439 spi_input_z |= 1;
1440 }
1441
1442 spi_ps_in_control_1 = 0;
1443 if (face_index != -1) {
1444 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1445 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1446 }
1447
1448 spi_baryc_cntl = 0;
1449 if (have_perspective)
1450 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
1451 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
1452 if (have_linear)
1453 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
1454 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
1455
1456 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1457 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1458 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1459 spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1460 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
1461 0, 0xFFFFFFFF, NULL);
1462 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1463 r600_pipe_state_add_reg(rstate,
1464 R_0286E0_SPI_BARYC_CNTL,
1465 spi_baryc_cntl,
1466 0xFFFFFFFF, NULL);
1467
1468 r600_pipe_state_add_reg(rstate,
1469 R_028840_SQ_PGM_START_PS,
1470 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1471 r600_pipe_state_add_reg(rstate,
1472 R_028844_SQ_PGM_RESOURCES_PS,
1473 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1474 S_028844_PRIME_CACHE_ON_DRAW(1) |
1475 S_028844_STACK_SIZE(rshader->bc.nstack),
1476 0xFFFFFFFF, NULL);
1477 r600_pipe_state_add_reg(rstate,
1478 R_028848_SQ_PGM_RESOURCES_2_PS,
1479 0x0, 0xFFFFFFFF, NULL);
1480 r600_pipe_state_add_reg(rstate,
1481 R_02884C_SQ_PGM_EXPORTS_PS,
1482 exports_ps, 0xFFFFFFFF, NULL);
1483 /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */
1484 /* only set some bits here, the other bits are set in the dsa state */
1485 r600_pipe_state_add_reg(rstate,
1486 R_02880C_DB_SHADER_CONTROL,
1487 db_shader_control,
1488 S_02880C_Z_EXPORT_ENABLE(1) |
1489 S_02880C_STENCIL_EXPORT_ENABLE(1) |
1490 S_02880C_KILL_ENABLE(1),
1491 NULL);
1492 r600_pipe_state_add_reg(rstate,
1493 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
1494 0xFFFFFFFF, NULL);
1495 }
1496
1497 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1498 {
1499 struct r600_pipe_state *rstate = &shader->rstate;
1500 struct r600_shader *rshader = &shader->shader;
1501 unsigned spi_vs_out_id[10];
1502 unsigned i, tmp;
1503
1504 /* clear previous register */
1505 rstate->nregs = 0;
1506
1507 /* so far never got proper semantic id from tgsi */
1508 for (i = 0; i < 10; i++) {
1509 spi_vs_out_id[i] = 0;
1510 }
1511 for (i = 0; i < 32; i++) {
1512 tmp = i << ((i & 3) * 8);
1513 spi_vs_out_id[i / 4] |= tmp;
1514 }
1515 for (i = 0; i < 10; i++) {
1516 r600_pipe_state_add_reg(rstate,
1517 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1518 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1519 }
1520
1521 r600_pipe_state_add_reg(rstate,
1522 R_0286C4_SPI_VS_OUT_CONFIG,
1523 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1524 0xFFFFFFFF, NULL);
1525 r600_pipe_state_add_reg(rstate,
1526 R_028860_SQ_PGM_RESOURCES_VS,
1527 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1528 S_028860_STACK_SIZE(rshader->bc.nstack),
1529 0xFFFFFFFF, NULL);
1530 r600_pipe_state_add_reg(rstate,
1531 R_028864_SQ_PGM_RESOURCES_2_VS,
1532 0x0, 0xFFFFFFFF, NULL);
1533 r600_pipe_state_add_reg(rstate,
1534 R_02885C_SQ_PGM_START_VS,
1535 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1536
1537 r600_pipe_state_add_reg(rstate,
1538 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1539 0xFFFFFFFF, NULL);
1540 }
1541
1542 void evergreen_fetch_shader(struct r600_vertex_element *ve)
1543 {
1544 struct r600_pipe_state *rstate = &ve->rstate;
1545 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1546 rstate->nregs = 0;
1547 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
1548 0x00000000, 0xFFFFFFFF, NULL);
1549 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
1550 (r600_bo_offset(ve->fetch_shader)) >> 8,
1551 0xFFFFFFFF, ve->fetch_shader);
1552 }
1553
1554 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1555 {
1556 struct pipe_depth_stencil_alpha_state dsa;
1557 struct r600_pipe_state *rstate;
1558
1559 memset(&dsa, 0, sizeof(dsa));
1560
1561 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1562 r600_pipe_state_add_reg(rstate,
1563 R_02880C_DB_SHADER_CONTROL,
1564 0x0,
1565 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1566 r600_pipe_state_add_reg(rstate,
1567 R_028000_DB_RENDER_CONTROL,
1568 S_028000_DEPTH_COPY_ENABLE(1) |
1569 S_028000_STENCIL_COPY_ENABLE(1) |
1570 S_028000_COPY_CENTROID(1),
1571 S_028000_DEPTH_COPY_ENABLE(1) |
1572 S_028000_STENCIL_COPY_ENABLE(1) |
1573 S_028000_COPY_CENTROID(1), NULL);
1574 return rstate;
1575 }
1576
1577 void evergreen_pipe_set_buffer_resource(struct r600_pipe_context *rctx,
1578 struct r600_pipe_state *rstate,
1579 struct r600_resource *rbuffer,
1580 unsigned offset, unsigned stride)
1581 {
1582 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
1583 offset, 0xFFFFFFFF, rbuffer->bo);
1584 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
1585 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
1586 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
1587 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1588 S_030008_STRIDE(stride), 0xFFFFFFFF, NULL);
1589 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
1590 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1591 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1592 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1593 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W),
1594 0xFFFFFFFF, NULL);
1595 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
1596 0x00000000, 0xFFFFFFFF, NULL);
1597 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
1598 0x00000000, 0xFFFFFFFF, NULL);
1599 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
1600 0x00000000, 0xFFFFFFFF, NULL);
1601 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
1602 0xC0000000, 0xFFFFFFFF, NULL);
1603 }