2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * - fix mask for depth control & cull for query
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_blitter.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
38 #include "util/u_surface.h"
39 #include "util/u_pack_color.h"
40 #include "util/u_memory.h"
41 #include "util/u_inlines.h"
42 #include "util/u_framebuffer.h"
43 #include "pipebuffer/pb_buffer.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "r600_formats.h"
51 static uint32_t r600_translate_blend_function(int blend_func
)
55 return V_028780_COMB_DST_PLUS_SRC
;
56 case PIPE_BLEND_SUBTRACT
:
57 return V_028780_COMB_SRC_MINUS_DST
;
58 case PIPE_BLEND_REVERSE_SUBTRACT
:
59 return V_028780_COMB_DST_MINUS_SRC
;
61 return V_028780_COMB_MIN_DST_SRC
;
63 return V_028780_COMB_MAX_DST_SRC
;
65 R600_ERR("Unknown blend function %d\n", blend_func
);
72 static uint32_t r600_translate_blend_factor(int blend_fact
)
75 case PIPE_BLENDFACTOR_ONE
:
76 return V_028780_BLEND_ONE
;
77 case PIPE_BLENDFACTOR_SRC_COLOR
:
78 return V_028780_BLEND_SRC_COLOR
;
79 case PIPE_BLENDFACTOR_SRC_ALPHA
:
80 return V_028780_BLEND_SRC_ALPHA
;
81 case PIPE_BLENDFACTOR_DST_ALPHA
:
82 return V_028780_BLEND_DST_ALPHA
;
83 case PIPE_BLENDFACTOR_DST_COLOR
:
84 return V_028780_BLEND_DST_COLOR
;
85 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
86 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
87 case PIPE_BLENDFACTOR_CONST_COLOR
:
88 return V_028780_BLEND_CONST_COLOR
;
89 case PIPE_BLENDFACTOR_CONST_ALPHA
:
90 return V_028780_BLEND_CONST_ALPHA
;
91 case PIPE_BLENDFACTOR_ZERO
:
92 return V_028780_BLEND_ZERO
;
93 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
94 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
95 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
96 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
97 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
98 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
99 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
100 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
101 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
102 return V_028780_BLEND_ONE_MINUS_CONST_COLOR
;
103 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
104 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA
;
105 case PIPE_BLENDFACTOR_SRC1_COLOR
:
106 return V_028780_BLEND_SRC1_COLOR
;
107 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
108 return V_028780_BLEND_SRC1_ALPHA
;
109 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
110 return V_028780_BLEND_INV_SRC1_COLOR
;
111 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
112 return V_028780_BLEND_INV_SRC1_ALPHA
;
114 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
121 static uint32_t r600_translate_stencil_op(int s_op
)
124 case PIPE_STENCIL_OP_KEEP
:
125 return V_028800_STENCIL_KEEP
;
126 case PIPE_STENCIL_OP_ZERO
:
127 return V_028800_STENCIL_ZERO
;
128 case PIPE_STENCIL_OP_REPLACE
:
129 return V_028800_STENCIL_REPLACE
;
130 case PIPE_STENCIL_OP_INCR
:
131 return V_028800_STENCIL_INCR
;
132 case PIPE_STENCIL_OP_DECR
:
133 return V_028800_STENCIL_DECR
;
134 case PIPE_STENCIL_OP_INCR_WRAP
:
135 return V_028800_STENCIL_INCR_WRAP
;
136 case PIPE_STENCIL_OP_DECR_WRAP
:
137 return V_028800_STENCIL_DECR_WRAP
;
138 case PIPE_STENCIL_OP_INVERT
:
139 return V_028800_STENCIL_INVERT
;
141 R600_ERR("Unknown stencil op %d", s_op
);
148 static uint32_t r600_translate_fill(uint32_t func
)
151 case PIPE_POLYGON_MODE_FILL
:
153 case PIPE_POLYGON_MODE_LINE
:
155 case PIPE_POLYGON_MODE_POINT
:
163 /* translates straight */
164 static uint32_t r600_translate_ds_func(int func
)
169 static unsigned r600_tex_wrap(unsigned wrap
)
173 case PIPE_TEX_WRAP_REPEAT
:
174 return V_03C000_SQ_TEX_WRAP
;
175 case PIPE_TEX_WRAP_CLAMP
:
176 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
177 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
178 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
179 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
180 return V_03C000_SQ_TEX_CLAMP_BORDER
;
181 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
182 return V_03C000_SQ_TEX_MIRROR
;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
184 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
186 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
187 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
188 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
192 static unsigned r600_tex_filter(unsigned filter
)
196 case PIPE_TEX_FILTER_NEAREST
:
197 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
198 case PIPE_TEX_FILTER_LINEAR
:
199 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
203 static unsigned r600_tex_mipfilter(unsigned filter
)
206 case PIPE_TEX_MIPFILTER_NEAREST
:
207 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
208 case PIPE_TEX_MIPFILTER_LINEAR
:
209 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
211 case PIPE_TEX_MIPFILTER_NONE
:
212 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
216 static unsigned r600_tex_compare(unsigned compare
)
220 case PIPE_FUNC_NEVER
:
221 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
223 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
224 case PIPE_FUNC_EQUAL
:
225 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
226 case PIPE_FUNC_LEQUAL
:
227 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
228 case PIPE_FUNC_GREATER
:
229 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
230 case PIPE_FUNC_NOTEQUAL
:
231 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
232 case PIPE_FUNC_GEQUAL
:
233 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
234 case PIPE_FUNC_ALWAYS
:
235 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
239 static unsigned r600_tex_dim(unsigned dim
)
243 case PIPE_TEXTURE_1D
:
244 return V_030000_SQ_TEX_DIM_1D
;
245 case PIPE_TEXTURE_1D_ARRAY
:
246 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
247 case PIPE_TEXTURE_2D
:
248 case PIPE_TEXTURE_RECT
:
249 return V_030000_SQ_TEX_DIM_2D
;
250 case PIPE_TEXTURE_2D_ARRAY
:
251 return V_030000_SQ_TEX_DIM_2D_ARRAY
;
252 case PIPE_TEXTURE_3D
:
253 return V_030000_SQ_TEX_DIM_3D
;
254 case PIPE_TEXTURE_CUBE
:
255 return V_030000_SQ_TEX_DIM_CUBEMAP
;
259 static uint32_t r600_translate_dbformat(enum pipe_format format
)
262 case PIPE_FORMAT_Z16_UNORM
:
263 return V_028040_Z_16
;
264 case PIPE_FORMAT_Z24X8_UNORM
:
265 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
266 return V_028040_Z_24
;
267 case PIPE_FORMAT_Z32_FLOAT
:
268 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
269 return V_028040_Z_32_FLOAT
;
275 static uint32_t r600_translate_colorswap(enum pipe_format format
)
279 case PIPE_FORMAT_L4A4_UNORM
:
280 case PIPE_FORMAT_A4R4_UNORM
:
281 return V_028C70_SWAP_ALT
;
283 case PIPE_FORMAT_A8_UNORM
:
284 case PIPE_FORMAT_A8_UINT
:
285 case PIPE_FORMAT_A8_SINT
:
286 case PIPE_FORMAT_R4A4_UNORM
:
287 return V_028C70_SWAP_ALT_REV
;
288 case PIPE_FORMAT_I8_UNORM
:
289 case PIPE_FORMAT_L8_UNORM
:
290 case PIPE_FORMAT_I8_UINT
:
291 case PIPE_FORMAT_I8_SINT
:
292 case PIPE_FORMAT_L8_UINT
:
293 case PIPE_FORMAT_L8_SINT
:
294 case PIPE_FORMAT_L8_SRGB
:
295 case PIPE_FORMAT_R8_UNORM
:
296 case PIPE_FORMAT_R8_SNORM
:
297 return V_028C70_SWAP_STD
;
299 /* 16-bit buffers. */
300 case PIPE_FORMAT_B5G6R5_UNORM
:
301 return V_028C70_SWAP_STD_REV
;
303 case PIPE_FORMAT_B5G5R5A1_UNORM
:
304 case PIPE_FORMAT_B5G5R5X1_UNORM
:
305 return V_028C70_SWAP_ALT
;
307 case PIPE_FORMAT_B4G4R4A4_UNORM
:
308 case PIPE_FORMAT_B4G4R4X4_UNORM
:
309 return V_028C70_SWAP_ALT
;
311 case PIPE_FORMAT_Z16_UNORM
:
312 return V_028C70_SWAP_STD
;
314 case PIPE_FORMAT_L8A8_UNORM
:
315 case PIPE_FORMAT_L8A8_UINT
:
316 case PIPE_FORMAT_L8A8_SINT
:
317 case PIPE_FORMAT_L8A8_SRGB
:
318 return V_028C70_SWAP_ALT
;
319 case PIPE_FORMAT_R8G8_UNORM
:
320 case PIPE_FORMAT_R8G8_UINT
:
321 case PIPE_FORMAT_R8G8_SINT
:
322 return V_028C70_SWAP_STD
;
324 case PIPE_FORMAT_R16_UNORM
:
325 case PIPE_FORMAT_R16_UINT
:
326 case PIPE_FORMAT_R16_SINT
:
327 case PIPE_FORMAT_R16_FLOAT
:
328 return V_028C70_SWAP_STD
;
330 /* 32-bit buffers. */
331 case PIPE_FORMAT_A8B8G8R8_SRGB
:
332 return V_028C70_SWAP_STD_REV
;
333 case PIPE_FORMAT_B8G8R8A8_SRGB
:
334 return V_028C70_SWAP_ALT
;
336 case PIPE_FORMAT_B8G8R8A8_UNORM
:
337 case PIPE_FORMAT_B8G8R8X8_UNORM
:
338 return V_028C70_SWAP_ALT
;
340 case PIPE_FORMAT_A8R8G8B8_UNORM
:
341 case PIPE_FORMAT_X8R8G8B8_UNORM
:
342 return V_028C70_SWAP_ALT_REV
;
343 case PIPE_FORMAT_R8G8B8A8_SNORM
:
344 case PIPE_FORMAT_R8G8B8A8_UNORM
:
345 case PIPE_FORMAT_R8G8B8A8_SSCALED
:
346 case PIPE_FORMAT_R8G8B8A8_USCALED
:
347 case PIPE_FORMAT_R8G8B8A8_SINT
:
348 case PIPE_FORMAT_R8G8B8A8_UINT
:
349 case PIPE_FORMAT_R8G8B8X8_UNORM
:
350 return V_028C70_SWAP_STD
;
352 case PIPE_FORMAT_A8B8G8R8_UNORM
:
353 case PIPE_FORMAT_X8B8G8R8_UNORM
:
354 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
355 return V_028C70_SWAP_STD_REV
;
357 case PIPE_FORMAT_Z24X8_UNORM
:
358 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
359 return V_028C70_SWAP_STD
;
361 case PIPE_FORMAT_X8Z24_UNORM
:
362 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
363 return V_028C70_SWAP_STD
;
365 case PIPE_FORMAT_R10G10B10A2_UNORM
:
366 case PIPE_FORMAT_R10G10B10X2_SNORM
:
367 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
368 return V_028C70_SWAP_STD
;
370 case PIPE_FORMAT_B10G10R10A2_UNORM
:
371 return V_028C70_SWAP_ALT
;
373 case PIPE_FORMAT_R11G11B10_FLOAT
:
374 case PIPE_FORMAT_R32_FLOAT
:
375 case PIPE_FORMAT_R32_UINT
:
376 case PIPE_FORMAT_R32_SINT
:
377 case PIPE_FORMAT_Z32_FLOAT
:
378 case PIPE_FORMAT_R16G16_FLOAT
:
379 case PIPE_FORMAT_R16G16_UNORM
:
380 case PIPE_FORMAT_R16G16_UINT
:
381 case PIPE_FORMAT_R16G16_SINT
:
382 return V_028C70_SWAP_STD
;
384 /* 64-bit buffers. */
385 case PIPE_FORMAT_R32G32_FLOAT
:
386 case PIPE_FORMAT_R32G32_UINT
:
387 case PIPE_FORMAT_R32G32_SINT
:
388 case PIPE_FORMAT_R16G16B16A16_UNORM
:
389 case PIPE_FORMAT_R16G16B16A16_SNORM
:
390 case PIPE_FORMAT_R16G16B16A16_USCALED
:
391 case PIPE_FORMAT_R16G16B16A16_SSCALED
:
392 case PIPE_FORMAT_R16G16B16A16_UINT
:
393 case PIPE_FORMAT_R16G16B16A16_SINT
:
394 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
395 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
397 /* 128-bit buffers. */
398 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
399 case PIPE_FORMAT_R32G32B32A32_SNORM
:
400 case PIPE_FORMAT_R32G32B32A32_UNORM
:
401 case PIPE_FORMAT_R32G32B32A32_SSCALED
:
402 case PIPE_FORMAT_R32G32B32A32_USCALED
:
403 case PIPE_FORMAT_R32G32B32A32_SINT
:
404 case PIPE_FORMAT_R32G32B32A32_UINT
:
405 return V_028C70_SWAP_STD
;
407 R600_ERR("unsupported colorswap format %d\n", format
);
413 static uint32_t r600_translate_colorformat(enum pipe_format format
)
417 case PIPE_FORMAT_L4A4_UNORM
:
418 case PIPE_FORMAT_R4A4_UNORM
:
419 case PIPE_FORMAT_A4R4_UNORM
:
420 return V_028C70_COLOR_4_4
;
422 case PIPE_FORMAT_A8_UNORM
:
423 case PIPE_FORMAT_A8_UINT
:
424 case PIPE_FORMAT_A8_SINT
:
425 case PIPE_FORMAT_I8_UNORM
:
426 case PIPE_FORMAT_I8_UINT
:
427 case PIPE_FORMAT_I8_SINT
:
428 case PIPE_FORMAT_L8_UNORM
:
429 case PIPE_FORMAT_L8_UINT
:
430 case PIPE_FORMAT_L8_SINT
:
431 case PIPE_FORMAT_L8_SRGB
:
432 case PIPE_FORMAT_R8_UNORM
:
433 case PIPE_FORMAT_R8_SNORM
:
434 case PIPE_FORMAT_R8_UINT
:
435 case PIPE_FORMAT_R8_SINT
:
436 return V_028C70_COLOR_8
;
438 /* 16-bit buffers. */
439 case PIPE_FORMAT_B5G6R5_UNORM
:
440 return V_028C70_COLOR_5_6_5
;
442 case PIPE_FORMAT_B5G5R5A1_UNORM
:
443 case PIPE_FORMAT_B5G5R5X1_UNORM
:
444 return V_028C70_COLOR_1_5_5_5
;
446 case PIPE_FORMAT_B4G4R4A4_UNORM
:
447 case PIPE_FORMAT_B4G4R4X4_UNORM
:
448 return V_028C70_COLOR_4_4_4_4
;
450 case PIPE_FORMAT_Z16_UNORM
:
451 return V_028C70_COLOR_16
;
453 case PIPE_FORMAT_L8A8_UNORM
:
454 case PIPE_FORMAT_L8A8_UINT
:
455 case PIPE_FORMAT_L8A8_SINT
:
456 case PIPE_FORMAT_L8A8_SRGB
:
457 case PIPE_FORMAT_R8G8_UNORM
:
458 case PIPE_FORMAT_R8G8_UINT
:
459 case PIPE_FORMAT_R8G8_SINT
:
460 return V_028C70_COLOR_8_8
;
462 case PIPE_FORMAT_R16_UNORM
:
463 case PIPE_FORMAT_R16_UINT
:
464 case PIPE_FORMAT_R16_SINT
:
465 return V_028C70_COLOR_16
;
467 case PIPE_FORMAT_R16_FLOAT
:
468 return V_028C70_COLOR_16_FLOAT
;
470 /* 32-bit buffers. */
471 case PIPE_FORMAT_A8B8G8R8_SRGB
:
472 case PIPE_FORMAT_A8B8G8R8_UNORM
:
473 case PIPE_FORMAT_A8R8G8B8_UNORM
:
474 case PIPE_FORMAT_B8G8R8A8_SRGB
:
475 case PIPE_FORMAT_B8G8R8A8_UNORM
:
476 case PIPE_FORMAT_B8G8R8X8_UNORM
:
477 case PIPE_FORMAT_R8G8B8A8_SNORM
:
478 case PIPE_FORMAT_R8G8B8A8_UNORM
:
479 case PIPE_FORMAT_R8G8B8X8_UNORM
:
480 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
481 case PIPE_FORMAT_X8B8G8R8_UNORM
:
482 case PIPE_FORMAT_X8R8G8B8_UNORM
:
483 case PIPE_FORMAT_R8G8B8_UNORM
:
484 case PIPE_FORMAT_R8G8B8A8_SSCALED
:
485 case PIPE_FORMAT_R8G8B8A8_USCALED
:
486 case PIPE_FORMAT_R8G8B8A8_SINT
:
487 case PIPE_FORMAT_R8G8B8A8_UINT
:
488 return V_028C70_COLOR_8_8_8_8
;
490 case PIPE_FORMAT_R10G10B10A2_UNORM
:
491 case PIPE_FORMAT_R10G10B10X2_SNORM
:
492 case PIPE_FORMAT_B10G10R10A2_UNORM
:
493 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
494 return V_028C70_COLOR_2_10_10_10
;
496 case PIPE_FORMAT_Z24X8_UNORM
:
497 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
498 return V_028C70_COLOR_8_24
;
500 case PIPE_FORMAT_X8Z24_UNORM
:
501 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
502 return V_028C70_COLOR_24_8
;
504 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
505 return V_028C70_COLOR_X24_8_32_FLOAT
;
507 case PIPE_FORMAT_R32_FLOAT
:
508 case PIPE_FORMAT_Z32_FLOAT
:
509 return V_028C70_COLOR_32_FLOAT
;
511 case PIPE_FORMAT_R16G16_FLOAT
:
512 return V_028C70_COLOR_16_16_FLOAT
;
514 case PIPE_FORMAT_R16G16_SSCALED
:
515 case PIPE_FORMAT_R16G16_UNORM
:
516 case PIPE_FORMAT_R16G16_UINT
:
517 case PIPE_FORMAT_R16G16_SINT
:
518 return V_028C70_COLOR_16_16
;
520 case PIPE_FORMAT_R11G11B10_FLOAT
:
521 return V_028C70_COLOR_10_11_11_FLOAT
;
523 /* 64-bit buffers. */
524 case PIPE_FORMAT_R16G16B16_USCALED
:
525 case PIPE_FORMAT_R16G16B16_SSCALED
:
526 case PIPE_FORMAT_R16G16B16A16_UINT
:
527 case PIPE_FORMAT_R16G16B16A16_SINT
:
528 case PIPE_FORMAT_R16G16B16A16_USCALED
:
529 case PIPE_FORMAT_R16G16B16A16_SSCALED
:
530 case PIPE_FORMAT_R16G16B16A16_UNORM
:
531 case PIPE_FORMAT_R16G16B16A16_SNORM
:
532 return V_028C70_COLOR_16_16_16_16
;
534 case PIPE_FORMAT_R16G16B16_FLOAT
:
535 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
536 return V_028C70_COLOR_16_16_16_16_FLOAT
;
538 case PIPE_FORMAT_R32G32_FLOAT
:
539 return V_028C70_COLOR_32_32_FLOAT
;
541 case PIPE_FORMAT_R32G32_USCALED
:
542 case PIPE_FORMAT_R32G32_SSCALED
:
543 case PIPE_FORMAT_R32G32_SINT
:
544 case PIPE_FORMAT_R32G32_UINT
:
545 return V_028C70_COLOR_32_32
;
547 /* 96-bit buffers. */
548 case PIPE_FORMAT_R32G32B32_FLOAT
:
549 return V_028C70_COLOR_32_32_32_FLOAT
;
551 /* 128-bit buffers. */
552 case PIPE_FORMAT_R32G32B32A32_SNORM
:
553 case PIPE_FORMAT_R32G32B32A32_UNORM
:
554 case PIPE_FORMAT_R32G32B32A32_SSCALED
:
555 case PIPE_FORMAT_R32G32B32A32_USCALED
:
556 case PIPE_FORMAT_R32G32B32A32_SINT
:
557 case PIPE_FORMAT_R32G32B32A32_UINT
:
558 return V_028C70_COLOR_32_32_32_32
;
559 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
560 return V_028C70_COLOR_32_32_32_32_FLOAT
;
563 case PIPE_FORMAT_UYVY
:
564 case PIPE_FORMAT_YUYV
:
566 return ~0U; /* Unsupported. */
570 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
572 if (R600_BIG_ENDIAN
) {
573 switch(colorformat
) {
574 case V_028C70_COLOR_4_4
:
578 case V_028C70_COLOR_8
:
581 /* 16-bit buffers. */
582 case V_028C70_COLOR_5_6_5
:
583 case V_028C70_COLOR_1_5_5_5
:
584 case V_028C70_COLOR_4_4_4_4
:
585 case V_028C70_COLOR_16
:
586 case V_028C70_COLOR_8_8
:
589 /* 32-bit buffers. */
590 case V_028C70_COLOR_8_8_8_8
:
591 case V_028C70_COLOR_2_10_10_10
:
592 case V_028C70_COLOR_8_24
:
593 case V_028C70_COLOR_24_8
:
594 case V_028C70_COLOR_32_FLOAT
:
595 case V_028C70_COLOR_16_16_FLOAT
:
596 case V_028C70_COLOR_16_16
:
599 /* 64-bit buffers. */
600 case V_028C70_COLOR_16_16_16_16
:
601 case V_028C70_COLOR_16_16_16_16_FLOAT
:
604 case V_028C70_COLOR_32_32_FLOAT
:
605 case V_028C70_COLOR_32_32
:
606 case V_028C70_COLOR_X24_8_32_FLOAT
:
609 /* 96-bit buffers. */
610 case V_028C70_COLOR_32_32_32_FLOAT
:
611 /* 128-bit buffers. */
612 case V_028C70_COLOR_32_32_32_32_FLOAT
:
613 case V_028C70_COLOR_32_32_32_32
:
616 return ENDIAN_NONE
; /* Unsupported. */
623 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
625 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
628 static bool r600_is_colorbuffer_format_supported(enum pipe_format format
)
630 return r600_translate_colorformat(format
) != ~0U &&
631 r600_translate_colorswap(format
) != ~0U;
634 static bool r600_is_zs_format_supported(enum pipe_format format
)
636 return r600_translate_dbformat(format
) != ~0U;
639 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
640 enum pipe_format format
,
641 enum pipe_texture_target target
,
642 unsigned sample_count
,
647 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
648 R600_ERR("r600: unsupported texture type %d\n", target
);
652 if (!util_format_is_supported(format
, usage
))
656 if (sample_count
> 1)
659 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
660 r600_is_sampler_format_supported(screen
, format
)) {
661 retval
|= PIPE_BIND_SAMPLER_VIEW
;
664 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
665 PIPE_BIND_DISPLAY_TARGET
|
667 PIPE_BIND_SHARED
)) &&
668 r600_is_colorbuffer_format_supported(format
)) {
670 (PIPE_BIND_RENDER_TARGET
|
671 PIPE_BIND_DISPLAY_TARGET
|
676 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
677 r600_is_zs_format_supported(format
)) {
678 retval
|= PIPE_BIND_DEPTH_STENCIL
;
681 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
682 r600_is_vertex_format_supported(format
)) {
683 retval
|= PIPE_BIND_VERTEX_BUFFER
;
686 if (usage
& PIPE_BIND_TRANSFER_READ
)
687 retval
|= PIPE_BIND_TRANSFER_READ
;
688 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
689 retval
|= PIPE_BIND_TRANSFER_WRITE
;
691 return retval
== usage
;
694 static void evergreen_set_blend_color(struct pipe_context
*ctx
,
695 const struct pipe_blend_color
*state
)
697 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
698 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
703 rstate
->id
= R600_PIPE_STATE_BLEND_COLOR
;
704 r600_pipe_state_add_reg(rstate
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]), 0xFFFFFFFF, NULL
, 0);
705 r600_pipe_state_add_reg(rstate
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]), 0xFFFFFFFF, NULL
, 0);
706 r600_pipe_state_add_reg(rstate
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]), 0xFFFFFFFF, NULL
, 0);
707 r600_pipe_state_add_reg(rstate
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]), 0xFFFFFFFF, NULL
, 0);
709 free(rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
]);
710 rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
] = rstate
;
711 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
714 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
715 const struct pipe_blend_state
*state
)
717 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
718 struct r600_pipe_blend
*blend
= CALLOC_STRUCT(r600_pipe_blend
);
719 struct r600_pipe_state
*rstate
;
720 u32 color_control
, target_mask
;
721 /* FIXME there is more then 8 framebuffer */
722 unsigned blend_cntl
[8];
728 rstate
= &blend
->rstate
;
730 rstate
->id
= R600_PIPE_STATE_BLEND
;
733 color_control
= S_028808_MODE(1);
734 if (state
->logicop_enable
) {
735 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
737 color_control
|= (0xcc << 16);
739 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
740 if (state
->independent_blend_enable
) {
741 for (int i
= 0; i
< 8; i
++) {
742 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
745 for (int i
= 0; i
< 8; i
++) {
746 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
749 blend
->cb_target_mask
= target_mask
;
751 r600_pipe_state_add_reg(rstate
, R_028808_CB_COLOR_CONTROL
,
752 color_control
, 0xFFFFFFFD, NULL
, 0);
754 if (rctx
->chip_class
!= CAYMAN
)
755 r600_pipe_state_add_reg(rstate
, R_028C3C_PA_SC_AA_MASK
, 0xFFFFFFFF, 0xFFFFFFFF, NULL
, 0);
757 r600_pipe_state_add_reg(rstate
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 0xFFFFFFFF, 0xFFFFFFFF, NULL
, 0);
758 r600_pipe_state_add_reg(rstate
, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1
, 0xFFFFFFFF, 0xFFFFFFFF, NULL
, 0);
761 for (int i
= 0; i
< 8; i
++) {
762 /* state->rt entries > 0 only written if independent blending */
763 const int j
= state
->independent_blend_enable
? i
: 0;
765 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
766 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
767 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
768 unsigned eqA
= state
->rt
[j
].alpha_func
;
769 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
770 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
773 if (!state
->rt
[j
].blend_enable
)
776 blend_cntl
[i
] |= S_028780_BLEND_CONTROL_ENABLE(1);
777 blend_cntl
[i
] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
778 blend_cntl
[i
] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
779 blend_cntl
[i
] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
781 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
782 blend_cntl
[i
] |= S_028780_SEPARATE_ALPHA_BLEND(1);
783 blend_cntl
[i
] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
784 blend_cntl
[i
] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
785 blend_cntl
[i
] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
788 for (int i
= 0; i
< 8; i
++) {
789 r600_pipe_state_add_reg(rstate
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
[i
], 0xFFFFFFFF, NULL
, 0);
795 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
796 const struct pipe_depth_stencil_alpha_state
*state
)
798 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
799 struct r600_pipe_dsa
*dsa
= CALLOC_STRUCT(r600_pipe_dsa
);
800 unsigned db_depth_control
, alpha_test_control
, alpha_ref
, db_shader_control
;
801 unsigned stencil_ref_mask
, stencil_ref_mask_bf
, db_render_override
, db_render_control
;
802 struct r600_pipe_state
*rstate
;
808 rstate
= &dsa
->rstate
;
810 rstate
->id
= R600_PIPE_STATE_DSA
;
811 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
812 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
813 stencil_ref_mask
= 0;
814 stencil_ref_mask_bf
= 0;
815 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
816 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
817 S_028800_ZFUNC(state
->depth
.func
);
820 if (state
->stencil
[0].enabled
) {
821 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
822 db_depth_control
|= S_028800_STENCILFUNC(r600_translate_ds_func(state
->stencil
[0].func
));
823 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
824 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
825 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
828 stencil_ref_mask
= S_028430_STENCILMASK(state
->stencil
[0].valuemask
) |
829 S_028430_STENCILWRITEMASK(state
->stencil
[0].writemask
);
830 if (state
->stencil
[1].enabled
) {
831 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
832 db_depth_control
|= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state
->stencil
[1].func
));
833 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
834 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
835 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
836 stencil_ref_mask_bf
= S_028434_STENCILMASK_BF(state
->stencil
[1].valuemask
) |
837 S_028434_STENCILWRITEMASK_BF(state
->stencil
[1].writemask
);
842 alpha_test_control
= 0;
844 if (state
->alpha
.enabled
) {
845 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
846 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
847 alpha_ref
= fui(state
->alpha
.ref_value
);
849 dsa
->alpha_ref
= alpha_ref
;
852 db_render_control
= 0;
853 db_render_override
= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
) |
854 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
855 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
856 /* TODO db_render_override depends on query */
857 r600_pipe_state_add_reg(rstate
, R_028028_DB_STENCIL_CLEAR
, 0x00000000, 0xFFFFFFFF, NULL
, 0);
858 r600_pipe_state_add_reg(rstate
, R_02802C_DB_DEPTH_CLEAR
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
859 r600_pipe_state_add_reg(rstate
, R_028410_SX_ALPHA_TEST_CONTROL
, alpha_test_control
, 0xFFFFFFFF, NULL
, 0);
860 r600_pipe_state_add_reg(rstate
,
861 R_028430_DB_STENCILREFMASK
, stencil_ref_mask
,
862 0xFFFFFFFF & C_028430_STENCILREF
, NULL
, 0);
863 r600_pipe_state_add_reg(rstate
,
864 R_028434_DB_STENCILREFMASK_BF
, stencil_ref_mask_bf
,
865 0xFFFFFFFF & C_028434_STENCILREF_BF
, NULL
, 0);
866 r600_pipe_state_add_reg(rstate
, R_0286DC_SPI_FOG_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
, 0);
867 r600_pipe_state_add_reg(rstate
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
, 0xFFFFFFFF, NULL
, 0);
868 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
869 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
870 * evergreen_pipe_shader_ps().*/
871 r600_pipe_state_add_reg(rstate
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
, 0xFFFFFFBC, NULL
, 0);
872 r600_pipe_state_add_reg(rstate
, R_028000_DB_RENDER_CONTROL
, db_render_control
, 0xFFFFFFFF, NULL
, 0);
873 r600_pipe_state_add_reg(rstate
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
, 0xFFFFFFFF, NULL
, 0);
874 r600_pipe_state_add_reg(rstate
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0, 0xFFFFFFFF, NULL
, 0);
875 r600_pipe_state_add_reg(rstate
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0, 0xFFFFFFFF, NULL
, 0);
876 r600_pipe_state_add_reg(rstate
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0, 0xFFFFFFFF, NULL
, 0);
877 r600_pipe_state_add_reg(rstate
, R_028B70_DB_ALPHA_TO_MASK
, 0x0000AA00, 0xFFFFFFFF, NULL
, 0);
882 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
883 const struct pipe_rasterizer_state
*state
)
885 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
886 struct r600_pipe_rasterizer
*rs
= CALLOC_STRUCT(r600_pipe_rasterizer
);
887 struct r600_pipe_state
*rstate
;
889 unsigned prov_vtx
= 1, polygon_dual_mode
;
896 rstate
= &rs
->rstate
;
897 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
898 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
899 rs
->flatshade
= state
->flatshade
;
900 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
902 clip_rule
= state
->scissor
? 0xAAAA : 0xFFFF;
905 rs
->offset_units
= state
->offset_units
;
906 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
908 rstate
->id
= R600_PIPE_STATE_RASTERIZER
;
909 if (state
->flatshade_first
)
911 tmp
= S_0286D4_FLAT_SHADE_ENA(1);
912 if (state
->sprite_coord_enable
) {
913 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
914 S_0286D4_PNT_SPRITE_OVRD_X(2) |
915 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
916 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
917 S_0286D4_PNT_SPRITE_OVRD_W(1);
918 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
919 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
922 r600_pipe_state_add_reg(rstate
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
, 0xFFFFFFFF, NULL
, 0);
924 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
925 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
926 r600_pipe_state_add_reg(rstate
, R_028814_PA_SU_SC_MODE_CNTL
,
927 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
928 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
929 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
930 S_028814_FACE(!state
->front_ccw
) |
931 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
932 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
933 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
934 S_028814_POLY_MODE(polygon_dual_mode
) |
935 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
936 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)), 0xFFFFFFFF, NULL
, 0);
937 r600_pipe_state_add_reg(rstate
, R_02881C_PA_CL_VS_OUT_CNTL
,
938 S_02881C_USE_VTX_POINT_SIZE(state
->point_size_per_vertex
) |
939 S_02881C_VS_OUT_MISC_VEC_ENA(state
->point_size_per_vertex
), 0xFFFFFFFF, NULL
, 0);
940 r600_pipe_state_add_reg(rstate
, R_028820_PA_CL_NANINF_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
, 0);
941 /* point size 12.4 fixed point */
942 tmp
= (unsigned)(state
->point_size
* 8.0);
943 r600_pipe_state_add_reg(rstate
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
), 0xFFFFFFFF, NULL
, 0);
944 r600_pipe_state_add_reg(rstate
, R_028A04_PA_SU_POINT_MINMAX
, 0x80000000, 0xFFFFFFFF, NULL
, 0);
946 tmp
= (unsigned)state
->line_width
* 8;
947 r600_pipe_state_add_reg(rstate
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
), 0xFFFFFFFF, NULL
, 0);
949 if (rctx
->chip_class
== CAYMAN
) {
950 r600_pipe_state_add_reg(rstate
, CM_R_028BDC_PA_SC_LINE_CNTL
, 0x00000400, 0xFFFFFFFF, NULL
, 0);
951 r600_pipe_state_add_reg(rstate
, CM_R_028BE4_PA_SU_VTX_CNTL
,
952 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
),
953 0xFFFFFFFF, NULL
, 0);
954 r600_pipe_state_add_reg(rstate
, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
955 r600_pipe_state_add_reg(rstate
, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
956 r600_pipe_state_add_reg(rstate
, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
957 r600_pipe_state_add_reg(rstate
, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
961 r600_pipe_state_add_reg(rstate
, R_028C00_PA_SC_LINE_CNTL
, 0x00000400, 0xFFFFFFFF, NULL
, 0);
963 r600_pipe_state_add_reg(rstate
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
964 r600_pipe_state_add_reg(rstate
, R_028C10_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
965 r600_pipe_state_add_reg(rstate
, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
966 r600_pipe_state_add_reg(rstate
, R_028C18_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
968 r600_pipe_state_add_reg(rstate
, R_028C08_PA_SU_VTX_CNTL
,
969 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
),
970 0xFFFFFFFF, NULL
, 0);
972 r600_pipe_state_add_reg(rstate
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
), 0xFFFFFFFF, NULL
, 0);
973 r600_pipe_state_add_reg(rstate
, R_02820C_PA_SC_CLIPRECT_RULE
, clip_rule
, 0xFFFFFFFF, NULL
, 0);
977 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
978 const struct pipe_sampler_state
*state
)
980 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
982 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
984 if (rstate
== NULL
) {
988 rstate
->id
= R600_PIPE_STATE_SAMPLER
;
989 util_pack_color(state
->border_color
.f
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
990 r600_pipe_state_add_reg_noblock(rstate
, R_03C000_SQ_TEX_SAMPLER_WORD0_0
,
991 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
992 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
993 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
994 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
995 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
996 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
997 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
998 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
999 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0), 0xFFFFFFFF, NULL
, 0);
1000 r600_pipe_state_add_reg_noblock(rstate
, R_03C004_SQ_TEX_SAMPLER_WORD1_0
,
1001 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
1002 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)),
1003 0xFFFFFFFF, NULL
, 0);
1004 r600_pipe_state_add_reg_noblock(rstate
, R_03C008_SQ_TEX_SAMPLER_WORD2_0
,
1005 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
1006 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
1008 0xFFFFFFFF, NULL
, 0);
1011 r600_pipe_state_add_reg_noblock(rstate
, R_00A404_TD_PS_SAMPLER0_BORDER_RED
, fui(state
->border_color
.f
[0]), 0xFFFFFFFF, NULL
, 0);
1012 r600_pipe_state_add_reg_noblock(rstate
, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN
, fui(state
->border_color
.f
[1]), 0xFFFFFFFF, NULL
, 0);
1013 r600_pipe_state_add_reg_noblock(rstate
, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE
, fui(state
->border_color
.f
[2]), 0xFFFFFFFF, NULL
, 0);
1014 r600_pipe_state_add_reg_noblock(rstate
, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA
, fui(state
->border_color
.f
[3]), 0xFFFFFFFF, NULL
, 0);
1019 static struct pipe_sampler_view
*evergreen_create_sampler_view(struct pipe_context
*ctx
,
1020 struct pipe_resource
*texture
,
1021 const struct pipe_sampler_view
*state
)
1023 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
1024 struct r600_pipe_resource_state
*rstate
;
1025 struct r600_resource_texture
*tmp
= (struct r600_resource_texture
*)texture
;
1026 unsigned format
, endian
;
1027 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
1028 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
1029 unsigned height
, depth
;
1033 rstate
= &view
->state
;
1035 /* initialize base object */
1036 view
->base
= *state
;
1037 view
->base
.texture
= NULL
;
1038 pipe_reference(NULL
, &texture
->reference
);
1039 view
->base
.texture
= texture
;
1040 view
->base
.reference
.count
= 1;
1041 view
->base
.context
= ctx
;
1043 swizzle
[0] = state
->swizzle_r
;
1044 swizzle
[1] = state
->swizzle_g
;
1045 swizzle
[2] = state
->swizzle_b
;
1046 swizzle
[3] = state
->swizzle_a
;
1048 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
1050 &word4
, &yuv_format
);
1055 if (tmp
->depth
&& !tmp
->is_flushing_texture
) {
1056 r600_texture_depth_flush(ctx
, texture
, TRUE
);
1057 tmp
= tmp
->flushed_depth_texture
;
1060 endian
= r600_colorformat_endian_swap(format
);
1062 height
= texture
->height0
;
1063 depth
= texture
->depth0
;
1065 pitch
= align(tmp
->pitch_in_blocks
[0] *
1066 util_format_get_blockwidth(state
->format
), 8);
1067 array_mode
= tmp
->array_mode
[0];
1068 tile_type
= tmp
->tile_type
;
1070 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
1072 depth
= texture
->array_size
;
1073 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
1074 depth
= texture
->array_size
;
1077 rstate
->bo
[0] = &tmp
->resource
;
1078 rstate
->bo
[1] = &tmp
->resource
;
1079 rstate
->bo_usage
[0] = RADEON_USAGE_READ
;
1080 rstate
->bo_usage
[1] = RADEON_USAGE_READ
;
1082 rstate
->val
[0] = (S_030000_DIM(r600_tex_dim(texture
->target
)) |
1083 S_030000_PITCH((pitch
/ 8) - 1) |
1084 S_030000_NON_DISP_TILING_ORDER(tile_type
) |
1085 S_030000_TEX_WIDTH(texture
->width0
- 1));
1086 rstate
->val
[1] = (S_030004_TEX_HEIGHT(height
- 1) |
1087 S_030004_TEX_DEPTH(depth
- 1) |
1088 S_030004_ARRAY_MODE(array_mode
));
1089 rstate
->val
[2] = tmp
->offset
[0] >> 8;
1090 rstate
->val
[3] = tmp
->offset
[1] >> 8;
1091 rstate
->val
[4] = (word4
|
1092 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
1093 S_030010_ENDIAN_SWAP(endian
) |
1094 S_030010_BASE_LEVEL(state
->u
.tex
.first_level
));
1095 rstate
->val
[5] = (S_030014_LAST_LEVEL(state
->u
.tex
.last_level
) |
1096 S_030014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
1097 S_030014_LAST_ARRAY(state
->u
.tex
.last_layer
));
1098 rstate
->val
[6] = (S_030018_MAX_ANISO(4 /* max 16 samples */));
1099 rstate
->val
[7] = (S_03001C_DATA_FORMAT(format
) |
1100 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
));
1105 static void evergreen_set_vs_sampler_view(struct pipe_context
*ctx
, unsigned count
,
1106 struct pipe_sampler_view
**views
)
1108 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1109 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
1111 for (int i
= 0; i
< count
; i
++) {
1113 evergreen_context_pipe_state_set_vs_resource(&rctx
->ctx
, &resource
[i
]->state
,
1114 i
+ R600_MAX_CONST_BUFFERS
);
1119 static void evergreen_set_ps_sampler_view(struct pipe_context
*ctx
, unsigned count
,
1120 struct pipe_sampler_view
**views
)
1122 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1123 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
1127 for (i
= 0; i
< count
; i
++) {
1128 if (&rctx
->ps_samplers
.views
[i
]->base
!= views
[i
]) {
1130 if (((struct r600_resource_texture
*)resource
[i
]->base
.texture
)->depth
)
1132 evergreen_context_pipe_state_set_ps_resource(&rctx
->ctx
, &resource
[i
]->state
,
1133 i
+ R600_MAX_CONST_BUFFERS
);
1135 evergreen_context_pipe_state_set_ps_resource(&rctx
->ctx
, NULL
,
1136 i
+ R600_MAX_CONST_BUFFERS
);
1138 pipe_sampler_view_reference(
1139 (struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
],
1143 if (((struct r600_resource_texture
*)resource
[i
]->base
.texture
)->depth
)
1148 for (i
= count
; i
< NUM_TEX_UNITS
; i
++) {
1149 if (rctx
->ps_samplers
.views
[i
]) {
1150 evergreen_context_pipe_state_set_ps_resource(&rctx
->ctx
, NULL
,
1151 i
+ R600_MAX_CONST_BUFFERS
);
1152 pipe_sampler_view_reference((struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
], NULL
);
1155 rctx
->have_depth_texture
= has_depth
;
1156 rctx
->ps_samplers
.n_views
= count
;
1159 static void evergreen_bind_ps_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
1161 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1162 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
1165 memcpy(rctx
->ps_samplers
.samplers
, states
, sizeof(void*) * count
);
1166 rctx
->ps_samplers
.n_samplers
= count
;
1168 for (int i
= 0; i
< count
; i
++) {
1169 evergreen_context_pipe_state_set_ps_sampler(&rctx
->ctx
, rstates
[i
], i
);
1173 static void evergreen_bind_vs_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
1175 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1176 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
1178 for (int i
= 0; i
< count
; i
++) {
1179 evergreen_context_pipe_state_set_vs_sampler(&rctx
->ctx
, rstates
[i
], i
);
1183 static void evergreen_set_clip_state(struct pipe_context
*ctx
,
1184 const struct pipe_clip_state
*state
)
1186 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1187 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1192 rctx
->clip
= *state
;
1193 rstate
->id
= R600_PIPE_STATE_CLIP
;
1194 for (int i
= 0; i
< state
->nr
; i
++) {
1195 r600_pipe_state_add_reg(rstate
,
1196 R_0285BC_PA_CL_UCP0_X
+ i
* 16,
1197 fui(state
->ucp
[i
][0]), 0xFFFFFFFF, NULL
, 0);
1198 r600_pipe_state_add_reg(rstate
,
1199 R_0285C0_PA_CL_UCP0_Y
+ i
* 16,
1200 fui(state
->ucp
[i
][1]) , 0xFFFFFFFF, NULL
, 0);
1201 r600_pipe_state_add_reg(rstate
,
1202 R_0285C4_PA_CL_UCP0_Z
+ i
* 16,
1203 fui(state
->ucp
[i
][2]), 0xFFFFFFFF, NULL
, 0);
1204 r600_pipe_state_add_reg(rstate
,
1205 R_0285C8_PA_CL_UCP0_W
+ i
* 16,
1206 fui(state
->ucp
[i
][3]), 0xFFFFFFFF, NULL
, 0);
1208 r600_pipe_state_add_reg(rstate
, R_028810_PA_CL_CLIP_CNTL
,
1209 S_028810_PS_UCP_MODE(3) | ((1 << state
->nr
) - 1) |
1210 S_028810_ZCLIP_NEAR_DISABLE(state
->depth_clamp
) |
1211 S_028810_ZCLIP_FAR_DISABLE(state
->depth_clamp
), 0xFFFFFFFF, NULL
, 0);
1213 free(rctx
->states
[R600_PIPE_STATE_CLIP
]);
1214 rctx
->states
[R600_PIPE_STATE_CLIP
] = rstate
;
1215 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1218 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
1219 const struct pipe_poly_stipple
*state
)
1223 static void evergreen_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1227 static void evergreen_set_scissor_state(struct pipe_context
*ctx
,
1228 const struct pipe_scissor_state
*state
)
1230 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1231 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1237 rstate
->id
= R600_PIPE_STATE_SCISSOR
;
1238 tl
= S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
);
1239 br
= S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
);
1240 r600_pipe_state_add_reg(rstate
,
1241 R_028210_PA_SC_CLIPRECT_0_TL
, tl
,
1242 0xFFFFFFFF, NULL
, 0);
1243 r600_pipe_state_add_reg(rstate
,
1244 R_028214_PA_SC_CLIPRECT_0_BR
, br
,
1245 0xFFFFFFFF, NULL
, 0);
1246 r600_pipe_state_add_reg(rstate
,
1247 R_028218_PA_SC_CLIPRECT_1_TL
, tl
,
1248 0xFFFFFFFF, NULL
, 0);
1249 r600_pipe_state_add_reg(rstate
,
1250 R_02821C_PA_SC_CLIPRECT_1_BR
, br
,
1251 0xFFFFFFFF, NULL
, 0);
1252 r600_pipe_state_add_reg(rstate
,
1253 R_028220_PA_SC_CLIPRECT_2_TL
, tl
,
1254 0xFFFFFFFF, NULL
, 0);
1255 r600_pipe_state_add_reg(rstate
,
1256 R_028224_PA_SC_CLIPRECT_2_BR
, br
,
1257 0xFFFFFFFF, NULL
, 0);
1258 r600_pipe_state_add_reg(rstate
,
1259 R_028228_PA_SC_CLIPRECT_3_TL
, tl
,
1260 0xFFFFFFFF, NULL
, 0);
1261 r600_pipe_state_add_reg(rstate
,
1262 R_02822C_PA_SC_CLIPRECT_3_BR
, br
,
1263 0xFFFFFFFF, NULL
, 0);
1265 free(rctx
->states
[R600_PIPE_STATE_SCISSOR
]);
1266 rctx
->states
[R600_PIPE_STATE_SCISSOR
] = rstate
;
1267 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1270 static void evergreen_set_stencil_ref(struct pipe_context
*ctx
,
1271 const struct pipe_stencil_ref
*state
)
1273 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1274 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1280 rctx
->stencil_ref
= *state
;
1281 rstate
->id
= R600_PIPE_STATE_STENCIL_REF
;
1282 tmp
= S_028430_STENCILREF(state
->ref_value
[0]);
1283 r600_pipe_state_add_reg(rstate
,
1284 R_028430_DB_STENCILREFMASK
, tmp
,
1285 ~C_028430_STENCILREF
, NULL
, 0);
1286 tmp
= S_028434_STENCILREF_BF(state
->ref_value
[1]);
1287 r600_pipe_state_add_reg(rstate
,
1288 R_028434_DB_STENCILREFMASK_BF
, tmp
,
1289 ~C_028434_STENCILREF_BF
, NULL
, 0);
1291 free(rctx
->states
[R600_PIPE_STATE_STENCIL_REF
]);
1292 rctx
->states
[R600_PIPE_STATE_STENCIL_REF
] = rstate
;
1293 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1296 static void evergreen_set_viewport_state(struct pipe_context
*ctx
,
1297 const struct pipe_viewport_state
*state
)
1299 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1300 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1305 rctx
->viewport
= *state
;
1306 rstate
->id
= R600_PIPE_STATE_VIEWPORT
;
1307 r600_pipe_state_add_reg(rstate
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 0x00000000, 0xFFFFFFFF, NULL
, 0);
1308 r600_pipe_state_add_reg(rstate
, R_0282D4_PA_SC_VPORT_ZMAX_0
, 0x3F800000, 0xFFFFFFFF, NULL
, 0);
1309 r600_pipe_state_add_reg(rstate
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]), 0xFFFFFFFF, NULL
, 0);
1310 r600_pipe_state_add_reg(rstate
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]), 0xFFFFFFFF, NULL
, 0);
1311 r600_pipe_state_add_reg(rstate
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]), 0xFFFFFFFF, NULL
, 0);
1312 r600_pipe_state_add_reg(rstate
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]), 0xFFFFFFFF, NULL
, 0);
1313 r600_pipe_state_add_reg(rstate
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]), 0xFFFFFFFF, NULL
, 0);
1314 r600_pipe_state_add_reg(rstate
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]), 0xFFFFFFFF, NULL
, 0);
1315 r600_pipe_state_add_reg(rstate
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F, 0xFFFFFFFF, NULL
, 0);
1317 free(rctx
->states
[R600_PIPE_STATE_VIEWPORT
]);
1318 rctx
->states
[R600_PIPE_STATE_VIEWPORT
] = rstate
;
1319 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1322 static void evergreen_cb(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
1323 const struct pipe_framebuffer_state
*state
, int cb
)
1325 struct r600_resource_texture
*rtex
;
1326 struct r600_surface
*surf
;
1327 unsigned level
= state
->cbufs
[cb
]->u
.tex
.level
;
1328 unsigned pitch
, slice
;
1329 unsigned color_info
;
1330 unsigned format
, swap
, ntype
, endian
;
1333 const struct util_format_description
*desc
;
1335 unsigned blend_clamp
= 0, blend_bypass
= 0;
1337 surf
= (struct r600_surface
*)state
->cbufs
[cb
];
1338 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
1341 rctx
->have_depth_fb
= TRUE
;
1343 if (rtex
->depth
&& !rtex
->is_flushing_texture
) {
1344 r600_texture_depth_flush(&rctx
->context
, state
->cbufs
[cb
]->texture
, TRUE
);
1345 rtex
= rtex
->flushed_depth_texture
;
1348 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1349 offset
= r600_texture_get_offset((struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
,
1350 level
, state
->cbufs
[cb
]->u
.tex
.first_layer
);
1351 pitch
= rtex
->pitch_in_blocks
[level
] / 8 - 1;
1352 slice
= rtex
->pitch_in_blocks
[level
] * surf
->aligned_height
/ 64 - 1;
1353 desc
= util_format_description(surf
->base
.format
);
1354 for (i
= 0; i
< 4; i
++) {
1355 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1360 ntype
= V_028C70_NUMBER_UNORM
;
1361 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1362 ntype
= V_028C70_NUMBER_SRGB
;
1363 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1364 if (desc
->channel
[i
].normalized
)
1365 ntype
= V_028C70_NUMBER_SNORM
;
1366 else if (desc
->channel
[i
].pure_integer
)
1367 ntype
= V_028C70_NUMBER_SINT
;
1368 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1369 if (desc
->channel
[i
].normalized
)
1370 ntype
= V_028C70_NUMBER_UNORM
;
1371 else if (desc
->channel
[i
].pure_integer
)
1372 ntype
= V_028C70_NUMBER_UINT
;
1375 format
= r600_translate_colorformat(surf
->base
.format
);
1376 swap
= r600_translate_colorswap(surf
->base
.format
);
1377 if (rtex
->resource
.b
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1378 endian
= ENDIAN_NONE
;
1380 endian
= r600_colorformat_endian_swap(format
);
1383 /* blend clamp should be set for all NORM/SRGB types */
1384 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
1385 ntype
== V_028C70_NUMBER_SRGB
)
1388 /* set blend bypass according to docs if SINT/UINT or
1389 8/24 COLOR variants */
1390 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1391 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1392 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1397 color_info
= S_028C70_FORMAT(format
) |
1398 S_028C70_COMP_SWAP(swap
) |
1399 S_028C70_ARRAY_MODE(rtex
->array_mode
[level
]) |
1400 S_028C70_BLEND_CLAMP(blend_clamp
) |
1401 S_028C70_BLEND_BYPASS(blend_bypass
) |
1402 S_028C70_NUMBER_TYPE(ntype
) |
1403 S_028C70_ENDIAN(endian
);
1405 /* EXPORT_NORM is an optimzation that can be enabled for better
1406 * performance in certain cases.
1407 * EXPORT_NORM can be enabled if:
1408 * - 11-bit or smaller UNORM/SNORM/SRGB
1409 * - 16-bit or smaller FLOAT
1411 /* FIXME: This should probably be the same for all CBs if we want
1412 * useful alpha tests. */
1413 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1414 ((desc
->channel
[i
].size
< 12 &&
1415 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1416 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
1417 (desc
->channel
[i
].size
< 17 &&
1418 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1419 color_info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
1420 rctx
->export_16bpc
= true;
1422 rctx
->export_16bpc
= false;
1424 rctx
->alpha_ref_dirty
= true;
1426 if (rtex
->array_mode
[level
] > V_028C70_ARRAY_LINEAR_ALIGNED
) {
1427 tile_type
= rtex
->tile_type
;
1428 } else /* workaround for linear buffers */
1431 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1432 r600_pipe_state_add_reg(rstate
,
1433 R_028C60_CB_COLOR0_BASE
+ cb
* 0x3C,
1434 offset
>> 8, 0xFFFFFFFF, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1435 r600_pipe_state_add_reg(rstate
,
1436 R_028C78_CB_COLOR0_DIM
+ cb
* 0x3C,
1437 0x0, 0xFFFFFFFF, NULL
, 0);
1438 r600_pipe_state_add_reg(rstate
,
1439 R_028C70_CB_COLOR0_INFO
+ cb
* 0x3C,
1440 color_info
, 0xFFFFFFFF, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1441 r600_pipe_state_add_reg(rstate
,
1442 R_028C64_CB_COLOR0_PITCH
+ cb
* 0x3C,
1443 S_028C64_PITCH_TILE_MAX(pitch
),
1444 0xFFFFFFFF, NULL
, 0);
1445 r600_pipe_state_add_reg(rstate
,
1446 R_028C68_CB_COLOR0_SLICE
+ cb
* 0x3C,
1447 S_028C68_SLICE_TILE_MAX(slice
),
1448 0xFFFFFFFF, NULL
, 0);
1449 r600_pipe_state_add_reg(rstate
,
1450 R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C,
1451 0x00000000, 0xFFFFFFFF, NULL
, 0);
1452 r600_pipe_state_add_reg(rstate
,
1453 R_028C74_CB_COLOR0_ATTRIB
+ cb
* 0x3C,
1454 S_028C74_NON_DISP_TILING_ORDER(tile_type
),
1455 0xFFFFFFFF, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1458 static void evergreen_db(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
1459 const struct pipe_framebuffer_state
*state
)
1461 struct r600_resource_texture
*rtex
;
1462 struct r600_surface
*surf
;
1463 unsigned level
, first_layer
, pitch
, slice
, format
, offset
, array_mode
;
1465 if (state
->zsbuf
== NULL
)
1468 surf
= (struct r600_surface
*)state
->zsbuf
;
1469 level
= surf
->base
.u
.tex
.level
;
1470 rtex
= (struct r600_resource_texture
*)surf
->base
.texture
;
1472 /* XXX remove this once tiling is properly supported */
1473 array_mode
= rtex
->array_mode
[level
] ? rtex
->array_mode
[level
] :
1474 V_028C70_ARRAY_1D_TILED_THIN1
;
1476 first_layer
= surf
->base
.u
.tex
.first_layer
;
1477 offset
= r600_texture_get_offset(rtex
, level
, first_layer
);
1478 pitch
= rtex
->pitch_in_blocks
[level
] / 8 - 1;
1479 slice
= rtex
->pitch_in_blocks
[level
] * surf
->aligned_height
/ 64 - 1;
1480 format
= r600_translate_dbformat(rtex
->real_format
);
1482 r600_pipe_state_add_reg(rstate
, R_028048_DB_Z_READ_BASE
,
1483 offset
>> 8, 0xFFFFFFFF, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1484 r600_pipe_state_add_reg(rstate
, R_028050_DB_Z_WRITE_BASE
,
1485 offset
>> 8, 0xFFFFFFFF, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1486 r600_pipe_state_add_reg(rstate
, R_028008_DB_DEPTH_VIEW
, 0x00000000, 0xFFFFFFFF, NULL
, 0);
1488 if (rtex
->stencil
) {
1489 uint32_t stencil_offset
=
1490 r600_texture_get_offset(rtex
->stencil
, level
, first_layer
);
1492 r600_pipe_state_add_reg(rstate
, R_02804C_DB_STENCIL_READ_BASE
,
1493 stencil_offset
>> 8, 0xFFFFFFFF, &rtex
->stencil
->resource
, RADEON_USAGE_READWRITE
);
1494 r600_pipe_state_add_reg(rstate
, R_028054_DB_STENCIL_WRITE_BASE
,
1495 stencil_offset
>> 8, 0xFFFFFFFF, &rtex
->stencil
->resource
, RADEON_USAGE_READWRITE
);
1496 r600_pipe_state_add_reg(rstate
, R_028044_DB_STENCIL_INFO
,
1497 1, 0xFFFFFFFF, &rtex
->stencil
->resource
, RADEON_USAGE_READWRITE
);
1499 r600_pipe_state_add_reg(rstate
, R_028044_DB_STENCIL_INFO
,
1500 0, 0xFFFFFFFF, NULL
, RADEON_USAGE_READWRITE
);
1503 r600_pipe_state_add_reg(rstate
, R_028040_DB_Z_INFO
,
1504 S_028040_ARRAY_MODE(array_mode
) | S_028040_FORMAT(format
),
1505 0xFFFFFFFF, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1506 r600_pipe_state_add_reg(rstate
, R_028058_DB_DEPTH_SIZE
,
1507 S_028058_PITCH_TILE_MAX(pitch
),
1508 0xFFFFFFFF, NULL
, 0);
1509 r600_pipe_state_add_reg(rstate
, R_02805C_DB_DEPTH_SLICE
,
1510 S_02805C_SLICE_TILE_MAX(slice
),
1511 0xFFFFFFFF, NULL
, 0);
1514 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
1515 const struct pipe_framebuffer_state
*state
)
1517 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1518 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1519 u32 shader_mask
, tl
, br
, target_mask
;
1520 int tl_x
, tl_y
, br_x
, br_y
;
1525 evergreen_context_flush_dest_caches(&rctx
->ctx
);
1526 rctx
->ctx
.num_dest_buffers
= state
->nr_cbufs
;
1528 /* unreference old buffer and reference new one */
1529 rstate
->id
= R600_PIPE_STATE_FRAMEBUFFER
;
1531 util_copy_framebuffer_state(&rctx
->framebuffer
, state
);
1534 rctx
->have_depth_fb
= 0;
1535 rctx
->nr_cbufs
= state
->nr_cbufs
;
1536 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1537 evergreen_cb(rctx
, rstate
, state
, i
);
1540 evergreen_db(rctx
, rstate
, state
);
1541 rctx
->ctx
.num_dest_buffers
++;
1544 target_mask
= 0x00000000;
1545 target_mask
= 0xFFFFFFFF;
1547 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1548 target_mask
^= 0xf << (i
* 4);
1549 shader_mask
|= 0xf << (i
* 4);
1553 br_x
= state
->width
;
1554 br_y
= state
->height
;
1555 /* EG hw workaround */
1560 /* cayman hw workaround */
1561 if (rctx
->chip_class
== CAYMAN
) {
1562 if (br_x
== 1 && br_y
== 1)
1565 tl
= S_028240_TL_X(tl_x
) | S_028240_TL_Y(tl_y
);
1566 br
= S_028244_BR_X(br_x
) | S_028244_BR_Y(br_y
);
1568 r600_pipe_state_add_reg(rstate
,
1569 R_028240_PA_SC_GENERIC_SCISSOR_TL
, tl
,
1570 0xFFFFFFFF, NULL
, 0);
1571 r600_pipe_state_add_reg(rstate
,
1572 R_028244_PA_SC_GENERIC_SCISSOR_BR
, br
,
1573 0xFFFFFFFF, NULL
, 0);
1574 r600_pipe_state_add_reg(rstate
,
1575 R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
,
1576 0xFFFFFFFF, NULL
, 0);
1577 r600_pipe_state_add_reg(rstate
,
1578 R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
,
1579 0xFFFFFFFF, NULL
, 0);
1580 r600_pipe_state_add_reg(rstate
,
1581 R_028030_PA_SC_SCREEN_SCISSOR_TL
, tl
,
1582 0xFFFFFFFF, NULL
, 0);
1583 r600_pipe_state_add_reg(rstate
,
1584 R_028034_PA_SC_SCREEN_SCISSOR_BR
, br
,
1585 0xFFFFFFFF, NULL
, 0);
1586 r600_pipe_state_add_reg(rstate
,
1587 R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
,
1588 0xFFFFFFFF, NULL
, 0);
1589 r600_pipe_state_add_reg(rstate
,
1590 R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
,
1591 0xFFFFFFFF, NULL
, 0);
1592 r600_pipe_state_add_reg(rstate
,
1593 R_028200_PA_SC_WINDOW_OFFSET
, 0x00000000,
1594 0xFFFFFFFF, NULL
, 0);
1595 r600_pipe_state_add_reg(rstate
,
1596 R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA,
1597 0xFFFFFFFF, NULL
, 0);
1599 r600_pipe_state_add_reg(rstate
, R_028238_CB_TARGET_MASK
,
1600 0x00000000, target_mask
, NULL
, 0);
1601 r600_pipe_state_add_reg(rstate
, R_02823C_CB_SHADER_MASK
,
1602 shader_mask
, 0xFFFFFFFF, NULL
, 0);
1605 if (rctx
->chip_class
== CAYMAN
) {
1606 r600_pipe_state_add_reg(rstate
, CM_R_028BE0_PA_SC_AA_CONFIG
,
1607 0x00000000, 0xFFFFFFFF, NULL
, 0);
1609 r600_pipe_state_add_reg(rstate
, R_028C04_PA_SC_AA_CONFIG
,
1610 0x00000000, 0xFFFFFFFF, NULL
, 0);
1611 r600_pipe_state_add_reg(rstate
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
,
1612 0x00000000, 0xFFFFFFFF, NULL
, 0);
1615 free(rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
]);
1616 rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
] = rstate
;
1617 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1620 evergreen_polygon_offset_update(rctx
);
1624 static void evergreen_texture_barrier(struct pipe_context
*ctx
)
1626 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1628 r600_context_flush_all(&rctx
->ctx
, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1629 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1630 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1631 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1632 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
1633 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
1634 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
1637 void evergreen_init_state_functions(struct r600_pipe_context
*rctx
)
1639 rctx
->context
.create_blend_state
= evergreen_create_blend_state
;
1640 rctx
->context
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
1641 rctx
->context
.create_fs_state
= r600_create_shader_state
;
1642 rctx
->context
.create_rasterizer_state
= evergreen_create_rs_state
;
1643 rctx
->context
.create_sampler_state
= evergreen_create_sampler_state
;
1644 rctx
->context
.create_sampler_view
= evergreen_create_sampler_view
;
1645 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
1646 rctx
->context
.create_vs_state
= r600_create_shader_state
;
1647 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1648 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
1649 rctx
->context
.bind_fragment_sampler_states
= evergreen_bind_ps_sampler
;
1650 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
1651 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1652 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1653 rctx
->context
.bind_vertex_sampler_states
= evergreen_bind_vs_sampler
;
1654 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
1655 rctx
->context
.delete_blend_state
= r600_delete_state
;
1656 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
1657 rctx
->context
.delete_fs_state
= r600_delete_ps_shader
;
1658 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1659 rctx
->context
.delete_sampler_state
= r600_delete_state
;
1660 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
1661 rctx
->context
.delete_vs_state
= r600_delete_vs_shader
;
1662 rctx
->context
.set_blend_color
= evergreen_set_blend_color
;
1663 rctx
->context
.set_clip_state
= evergreen_set_clip_state
;
1664 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1665 rctx
->context
.set_fragment_sampler_views
= evergreen_set_ps_sampler_view
;
1666 rctx
->context
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
1667 rctx
->context
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
1668 rctx
->context
.set_sample_mask
= evergreen_set_sample_mask
;
1669 rctx
->context
.set_scissor_state
= evergreen_set_scissor_state
;
1670 rctx
->context
.set_stencil_ref
= evergreen_set_stencil_ref
;
1671 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1672 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1673 rctx
->context
.set_vertex_sampler_views
= evergreen_set_vs_sampler_view
;
1674 rctx
->context
.set_viewport_state
= evergreen_set_viewport_state
;
1675 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1676 rctx
->context
.redefine_user_buffer
= u_default_redefine_user_buffer
;
1677 rctx
->context
.texture_barrier
= evergreen_texture_barrier
;
1680 static void cayman_init_config(struct r600_pipe_context
*rctx
)
1682 struct r600_pipe_state
*rstate
= &rctx
->config
;
1686 tmp
|= S_008C00_EXPORT_SRC_C(1);
1687 r600_pipe_state_add_reg(rstate
, R_008C00_SQ_CONFIG
, tmp
, 0xFFFFFFFF, NULL
, 0);
1689 /* always set the temp clauses */
1690 r600_pipe_state_add_reg(rstate
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), 0xFFFFFFFF, NULL
, 0);
1691 r600_pipe_state_add_reg(rstate
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 0, 0xFFFFFFFF, NULL
, 0);
1692 r600_pipe_state_add_reg(rstate
, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2
, 0, 0xFFFFFFFF, NULL
, 0);
1693 r600_pipe_state_add_reg(rstate
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8), 0xFFFFFFFF, NULL
, 0);
1695 r600_pipe_state_add_reg(rstate
, R_028A48_PA_SC_MODE_CNTL_0
, 0x0, 0xFFFFFFFF, NULL
, 0);
1696 r600_pipe_state_add_reg(rstate
, R_028A4C_PA_SC_MODE_CNTL_1
, 0x0, 0xFFFFFFFF, NULL
, 0);
1698 r600_pipe_state_add_reg(rstate
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1699 r600_pipe_state_add_reg(rstate
, R_028A14_VGT_HOS_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1700 r600_pipe_state_add_reg(rstate
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1701 r600_pipe_state_add_reg(rstate
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1702 r600_pipe_state_add_reg(rstate
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x0, 0xFFFFFFFF, NULL
, 0);
1703 r600_pipe_state_add_reg(rstate
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x0, 0xFFFFFFFF, NULL
, 0);
1704 r600_pipe_state_add_reg(rstate
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x0, 0xFFFFFFFF, NULL
, 0);
1705 r600_pipe_state_add_reg(rstate
, R_028A2C_VGT_GROUP_DECR
, 0x0, 0xFFFFFFFF, NULL
, 0);
1706 r600_pipe_state_add_reg(rstate
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1707 r600_pipe_state_add_reg(rstate
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1708 r600_pipe_state_add_reg(rstate
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1709 r600_pipe_state_add_reg(rstate
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1710 r600_pipe_state_add_reg(rstate
, R_028A40_VGT_GS_MODE
, 0x0, 0xFFFFFFFF, NULL
, 0);
1711 r600_pipe_state_add_reg(rstate
, R_028B94_VGT_STRMOUT_CONFIG
, 0x0, 0xFFFFFFFF, NULL
, 0);
1712 r600_pipe_state_add_reg(rstate
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0, 0xFFFFFFFF, NULL
, 0);
1713 r600_pipe_state_add_reg(rstate
, R_028AA8_IA_MULTI_VGT_PARAM
, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), 0xFFFFFFFF, NULL
, 0);
1714 r600_pipe_state_add_reg(rstate
, R_028AB4_VGT_REUSE_OFF
, 0x00000000, 0xFFFFFFFF, NULL
, 0);
1715 r600_pipe_state_add_reg(rstate
, R_028AB8_VGT_VTX_CNT_EN
, 0x0, 0xFFFFFFFF, NULL
, 0);
1716 r600_pipe_state_add_reg(rstate
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1, 0xFFFFFFFF, NULL
, 0);
1718 r600_pipe_state_add_reg(rstate
, R_028380_SQ_VTX_SEMANTIC_0
, 0x0, 0xFFFFFFFF, NULL
, 0);
1719 r600_pipe_state_add_reg(rstate
, R_028384_SQ_VTX_SEMANTIC_1
, 0x0, 0xFFFFFFFF, NULL
, 0);
1720 r600_pipe_state_add_reg(rstate
, R_028388_SQ_VTX_SEMANTIC_2
, 0x0, 0xFFFFFFFF, NULL
, 0);
1721 r600_pipe_state_add_reg(rstate
, R_02838C_SQ_VTX_SEMANTIC_3
, 0x0, 0xFFFFFFFF, NULL
, 0);
1722 r600_pipe_state_add_reg(rstate
, R_028390_SQ_VTX_SEMANTIC_4
, 0x0, 0xFFFFFFFF, NULL
, 0);
1723 r600_pipe_state_add_reg(rstate
, R_028394_SQ_VTX_SEMANTIC_5
, 0x0, 0xFFFFFFFF, NULL
, 0);
1724 r600_pipe_state_add_reg(rstate
, R_028398_SQ_VTX_SEMANTIC_6
, 0x0, 0xFFFFFFFF, NULL
, 0);
1725 r600_pipe_state_add_reg(rstate
, R_02839C_SQ_VTX_SEMANTIC_7
, 0x0, 0xFFFFFFFF, NULL
, 0);
1726 r600_pipe_state_add_reg(rstate
, R_0283A0_SQ_VTX_SEMANTIC_8
, 0x0, 0xFFFFFFFF, NULL
, 0);
1727 r600_pipe_state_add_reg(rstate
, R_0283A4_SQ_VTX_SEMANTIC_9
, 0x0, 0xFFFFFFFF, NULL
, 0);
1728 r600_pipe_state_add_reg(rstate
, R_0283A8_SQ_VTX_SEMANTIC_10
, 0x0, 0xFFFFFFFF, NULL
, 0);
1729 r600_pipe_state_add_reg(rstate
, R_0283AC_SQ_VTX_SEMANTIC_11
, 0x0, 0xFFFFFFFF, NULL
, 0);
1730 r600_pipe_state_add_reg(rstate
, R_0283B0_SQ_VTX_SEMANTIC_12
, 0x0, 0xFFFFFFFF, NULL
, 0);
1731 r600_pipe_state_add_reg(rstate
, R_0283B4_SQ_VTX_SEMANTIC_13
, 0x0, 0xFFFFFFFF, NULL
, 0);
1732 r600_pipe_state_add_reg(rstate
, R_0283B8_SQ_VTX_SEMANTIC_14
, 0x0, 0xFFFFFFFF, NULL
, 0);
1733 r600_pipe_state_add_reg(rstate
, R_0283BC_SQ_VTX_SEMANTIC_15
, 0x0, 0xFFFFFFFF, NULL
, 0);
1734 r600_pipe_state_add_reg(rstate
, R_0283C0_SQ_VTX_SEMANTIC_16
, 0x0, 0xFFFFFFFF, NULL
, 0);
1735 r600_pipe_state_add_reg(rstate
, R_0283C4_SQ_VTX_SEMANTIC_17
, 0x0, 0xFFFFFFFF, NULL
, 0);
1736 r600_pipe_state_add_reg(rstate
, R_0283C8_SQ_VTX_SEMANTIC_18
, 0x0, 0xFFFFFFFF, NULL
, 0);
1737 r600_pipe_state_add_reg(rstate
, R_0283CC_SQ_VTX_SEMANTIC_19
, 0x0, 0xFFFFFFFF, NULL
, 0);
1738 r600_pipe_state_add_reg(rstate
, R_0283D0_SQ_VTX_SEMANTIC_20
, 0x0, 0xFFFFFFFF, NULL
, 0);
1739 r600_pipe_state_add_reg(rstate
, R_0283D4_SQ_VTX_SEMANTIC_21
, 0x0, 0xFFFFFFFF, NULL
, 0);
1740 r600_pipe_state_add_reg(rstate
, R_0283D8_SQ_VTX_SEMANTIC_22
, 0x0, 0xFFFFFFFF, NULL
, 0);
1741 r600_pipe_state_add_reg(rstate
, R_0283DC_SQ_VTX_SEMANTIC_23
, 0x0, 0xFFFFFFFF, NULL
, 0);
1742 r600_pipe_state_add_reg(rstate
, R_0283E0_SQ_VTX_SEMANTIC_24
, 0x0, 0xFFFFFFFF, NULL
, 0);
1743 r600_pipe_state_add_reg(rstate
, R_0283E4_SQ_VTX_SEMANTIC_25
, 0x0, 0xFFFFFFFF, NULL
, 0);
1744 r600_pipe_state_add_reg(rstate
, R_0283E8_SQ_VTX_SEMANTIC_26
, 0x0, 0xFFFFFFFF, NULL
, 0);
1745 r600_pipe_state_add_reg(rstate
, R_0283EC_SQ_VTX_SEMANTIC_27
, 0x0, 0xFFFFFFFF, NULL
, 0);
1746 r600_pipe_state_add_reg(rstate
, R_0283F0_SQ_VTX_SEMANTIC_28
, 0x0, 0xFFFFFFFF, NULL
, 0);
1747 r600_pipe_state_add_reg(rstate
, R_0283F4_SQ_VTX_SEMANTIC_29
, 0x0, 0xFFFFFFFF, NULL
, 0);
1748 r600_pipe_state_add_reg(rstate
, R_0283F8_SQ_VTX_SEMANTIC_30
, 0x0, 0xFFFFFFFF, NULL
, 0);
1749 r600_pipe_state_add_reg(rstate
, R_0283FC_SQ_VTX_SEMANTIC_31
, 0x0, 0xFFFFFFFF, NULL
, 0);
1751 r600_pipe_state_add_reg(rstate
, R_028810_PA_CL_CLIP_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
1753 r600_pipe_state_add_reg(rstate
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210, 0xffffffff, NULL
, 0);
1754 r600_pipe_state_add_reg(rstate
, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98, 0xffffffff, NULL
, 0);
1756 r600_pipe_state_add_reg(rstate
, CM_R_0288E8_SQ_LDS_ALLOC
, 0, 0xFFFFFFFF, NULL
, 0);
1757 r600_pipe_state_add_reg(rstate
, R_0288EC_SQ_LDS_ALLOC_PS
, 0, 0xFFFFFFFF, NULL
, 0);
1759 r600_pipe_state_add_reg(rstate
, CM_R_028804_DB_EQAA
, 0x110000, 0xFFFFFFFF, NULL
, 0);
1760 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1763 void evergreen_init_config(struct r600_pipe_context
*rctx
)
1765 struct r600_pipe_state
*rstate
= &rctx
->config
;
1770 int hs_prio
, cs_prio
, ls_prio
;
1784 int num_ps_stack_entries
;
1785 int num_vs_stack_entries
;
1786 int num_gs_stack_entries
;
1787 int num_es_stack_entries
;
1788 int num_hs_stack_entries
;
1789 int num_ls_stack_entries
;
1790 enum radeon_family family
;
1793 family
= rctx
->family
;
1795 if (rctx
->chip_class
== CAYMAN
) {
1796 cayman_init_config(rctx
);
1818 num_ps_threads
= 96;
1819 num_vs_threads
= 16;
1820 num_gs_threads
= 16;
1821 num_es_threads
= 16;
1822 num_hs_threads
= 16;
1823 num_ls_threads
= 16;
1824 num_ps_stack_entries
= 42;
1825 num_vs_stack_entries
= 42;
1826 num_gs_stack_entries
= 42;
1827 num_es_stack_entries
= 42;
1828 num_hs_stack_entries
= 42;
1829 num_ls_stack_entries
= 42;
1839 num_ps_threads
= 128;
1840 num_vs_threads
= 20;
1841 num_gs_threads
= 20;
1842 num_es_threads
= 20;
1843 num_hs_threads
= 20;
1844 num_ls_threads
= 20;
1845 num_ps_stack_entries
= 42;
1846 num_vs_stack_entries
= 42;
1847 num_gs_stack_entries
= 42;
1848 num_es_stack_entries
= 42;
1849 num_hs_stack_entries
= 42;
1850 num_ls_stack_entries
= 42;
1860 num_ps_threads
= 128;
1861 num_vs_threads
= 20;
1862 num_gs_threads
= 20;
1863 num_es_threads
= 20;
1864 num_hs_threads
= 20;
1865 num_ls_threads
= 20;
1866 num_ps_stack_entries
= 85;
1867 num_vs_stack_entries
= 85;
1868 num_gs_stack_entries
= 85;
1869 num_es_stack_entries
= 85;
1870 num_hs_stack_entries
= 85;
1871 num_ls_stack_entries
= 85;
1882 num_ps_threads
= 128;
1883 num_vs_threads
= 20;
1884 num_gs_threads
= 20;
1885 num_es_threads
= 20;
1886 num_hs_threads
= 20;
1887 num_ls_threads
= 20;
1888 num_ps_stack_entries
= 85;
1889 num_vs_stack_entries
= 85;
1890 num_gs_stack_entries
= 85;
1891 num_es_stack_entries
= 85;
1892 num_hs_stack_entries
= 85;
1893 num_ls_stack_entries
= 85;
1903 num_ps_threads
= 96;
1904 num_vs_threads
= 16;
1905 num_gs_threads
= 16;
1906 num_es_threads
= 16;
1907 num_hs_threads
= 16;
1908 num_ls_threads
= 16;
1909 num_ps_stack_entries
= 42;
1910 num_vs_stack_entries
= 42;
1911 num_gs_stack_entries
= 42;
1912 num_es_stack_entries
= 42;
1913 num_hs_stack_entries
= 42;
1914 num_ls_stack_entries
= 42;
1924 num_ps_threads
= 96;
1925 num_vs_threads
= 25;
1926 num_gs_threads
= 25;
1927 num_es_threads
= 25;
1928 num_hs_threads
= 25;
1929 num_ls_threads
= 25;
1930 num_ps_stack_entries
= 42;
1931 num_vs_stack_entries
= 42;
1932 num_gs_stack_entries
= 42;
1933 num_es_stack_entries
= 42;
1934 num_hs_stack_entries
= 42;
1935 num_ls_stack_entries
= 42;
1945 num_ps_threads
= 96;
1946 num_vs_threads
= 25;
1947 num_gs_threads
= 25;
1948 num_es_threads
= 25;
1949 num_hs_threads
= 25;
1950 num_ls_threads
= 25;
1951 num_ps_stack_entries
= 85;
1952 num_vs_stack_entries
= 85;
1953 num_gs_stack_entries
= 85;
1954 num_es_stack_entries
= 85;
1955 num_hs_stack_entries
= 85;
1956 num_ls_stack_entries
= 85;
1966 num_ps_threads
= 128;
1967 num_vs_threads
= 20;
1968 num_gs_threads
= 20;
1969 num_es_threads
= 20;
1970 num_hs_threads
= 20;
1971 num_ls_threads
= 20;
1972 num_ps_stack_entries
= 85;
1973 num_vs_stack_entries
= 85;
1974 num_gs_stack_entries
= 85;
1975 num_es_stack_entries
= 85;
1976 num_hs_stack_entries
= 85;
1977 num_ls_stack_entries
= 85;
1987 num_ps_threads
= 128;
1988 num_vs_threads
= 20;
1989 num_gs_threads
= 20;
1990 num_es_threads
= 20;
1991 num_hs_threads
= 20;
1992 num_ls_threads
= 20;
1993 num_ps_stack_entries
= 42;
1994 num_vs_stack_entries
= 42;
1995 num_gs_stack_entries
= 42;
1996 num_es_stack_entries
= 42;
1997 num_hs_stack_entries
= 42;
1998 num_ls_stack_entries
= 42;
2008 num_ps_threads
= 128;
2009 num_vs_threads
= 10;
2010 num_gs_threads
= 10;
2011 num_es_threads
= 10;
2012 num_hs_threads
= 10;
2013 num_ls_threads
= 10;
2014 num_ps_stack_entries
= 42;
2015 num_vs_stack_entries
= 42;
2016 num_gs_stack_entries
= 42;
2017 num_es_stack_entries
= 42;
2018 num_hs_stack_entries
= 42;
2019 num_ls_stack_entries
= 42;
2032 tmp
|= S_008C00_VC_ENABLE(1);
2035 tmp
|= S_008C00_EXPORT_SRC_C(1);
2036 tmp
|= S_008C00_CS_PRIO(cs_prio
);
2037 tmp
|= S_008C00_LS_PRIO(ls_prio
);
2038 tmp
|= S_008C00_HS_PRIO(hs_prio
);
2039 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2040 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2041 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2042 tmp
|= S_008C00_ES_PRIO(es_prio
);
2043 r600_pipe_state_add_reg(rstate
, R_008C00_SQ_CONFIG
, tmp
, 0xFFFFFFFF, NULL
, 0);
2045 /* enable dynamic GPR resource management */
2046 if (rctx
->screen
->info
.drm_minor
>= 7) {
2047 /* always set temp clauses */
2048 r600_pipe_state_add_reg(rstate
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
,
2049 S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
), 0xFFFFFFFF, NULL
, 0);
2050 r600_pipe_state_add_reg(rstate
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 0, 0xFFFFFFFF, NULL
, 0);
2051 r600_pipe_state_add_reg(rstate
, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2
, 0, 0xFFFFFFFF, NULL
, 0);
2052 r600_pipe_state_add_reg(rstate
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8), 0xFFFFFFFF, NULL
, 0);
2053 r600_pipe_state_add_reg(rstate
, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
,
2054 S_028838_PS_GPRS(0x1e) |
2055 S_028838_VS_GPRS(0x1e) |
2056 S_028838_GS_GPRS(0x1e) |
2057 S_028838_ES_GPRS(0x1e) |
2058 S_028838_HS_GPRS(0x1e) |
2059 S_028838_LS_GPRS(0x1e), 0xFFFFFFFF, NULL
, 0); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2062 tmp
|= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
2063 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
2064 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
2065 r600_pipe_state_add_reg(rstate
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
, 0);
2068 tmp
|= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2069 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2070 r600_pipe_state_add_reg(rstate
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
, 0);
2073 tmp
|= S_008C0C_NUM_HS_GPRS(num_hs_gprs
);
2074 tmp
|= S_008C0C_NUM_HS_GPRS(num_ls_gprs
);
2075 r600_pipe_state_add_reg(rstate
, R_008C0C_SQ_GPR_RESOURCE_MGMT_3
, tmp
, 0xFFFFFFFF, NULL
, 0);
2079 tmp
|= S_008C18_NUM_PS_THREADS(num_ps_threads
);
2080 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
2081 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
2082 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
2083 r600_pipe_state_add_reg(rstate
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
, 0);
2086 tmp
|= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
2087 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
2088 r600_pipe_state_add_reg(rstate
, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
, 0);
2091 tmp
|= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2092 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2093 r600_pipe_state_add_reg(rstate
, R_008C20_SQ_STACK_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
, 0);
2096 tmp
|= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2097 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2098 r600_pipe_state_add_reg(rstate
, R_008C24_SQ_STACK_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
, 0);
2101 tmp
|= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
2102 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
2103 r600_pipe_state_add_reg(rstate
, R_008C28_SQ_STACK_RESOURCE_MGMT_3
, tmp
, 0xFFFFFFFF, NULL
, 0);
2106 tmp
|= S_008E2C_NUM_PS_LDS(0x1000);
2107 tmp
|= S_008E2C_NUM_LS_LDS(0x1000);
2108 r600_pipe_state_add_reg(rstate
, R_008E2C_SQ_LDS_RESOURCE_MGMT
, tmp
, 0xFFFFFFFF, NULL
, 0);
2110 r600_pipe_state_add_reg(rstate
, R_009100_SPI_CONFIG_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2111 r600_pipe_state_add_reg(rstate
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL
, 0);
2114 r600_pipe_state_add_reg(rstate
, R_028350_SX_MISC
, 0x0, 0xFFFFFFFF, NULL
, 0);
2116 r600_pipe_state_add_reg(rstate
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x0, 0xFFFFFFFF, NULL
, 0);
2118 r600_pipe_state_add_reg(rstate
, R_028A48_PA_SC_MODE_CNTL_0
, 0x0, 0xFFFFFFFF, NULL
, 0);
2119 r600_pipe_state_add_reg(rstate
, R_028A4C_PA_SC_MODE_CNTL_1
, 0x0, 0xFFFFFFFF, NULL
, 0);
2121 r600_pipe_state_add_reg(rstate
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2122 r600_pipe_state_add_reg(rstate
, R_028904_SQ_GSVS_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2123 r600_pipe_state_add_reg(rstate
, R_028908_SQ_ESTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2124 r600_pipe_state_add_reg(rstate
, R_02890C_SQ_GSTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2125 r600_pipe_state_add_reg(rstate
, R_028910_SQ_VSTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2126 r600_pipe_state_add_reg(rstate
, R_028914_SQ_PSTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2128 r600_pipe_state_add_reg(rstate
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2129 r600_pipe_state_add_reg(rstate
, R_028920_SQ_GS_VERT_ITEMSIZE_1
, 0x0, 0xFFFFFFFF, NULL
, 0);
2130 r600_pipe_state_add_reg(rstate
, R_028924_SQ_GS_VERT_ITEMSIZE_2
, 0x0, 0xFFFFFFFF, NULL
, 0);
2131 r600_pipe_state_add_reg(rstate
, R_028928_SQ_GS_VERT_ITEMSIZE_3
, 0x0, 0xFFFFFFFF, NULL
, 0);
2133 r600_pipe_state_add_reg(rstate
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2134 r600_pipe_state_add_reg(rstate
, R_028A14_VGT_HOS_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2135 r600_pipe_state_add_reg(rstate
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2136 r600_pipe_state_add_reg(rstate
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2137 r600_pipe_state_add_reg(rstate
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x0, 0xFFFFFFFF, NULL
, 0);
2138 r600_pipe_state_add_reg(rstate
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2139 r600_pipe_state_add_reg(rstate
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x0, 0xFFFFFFFF, NULL
, 0);
2140 r600_pipe_state_add_reg(rstate
, R_028A2C_VGT_GROUP_DECR
, 0x0, 0xFFFFFFFF, NULL
, 0);
2141 r600_pipe_state_add_reg(rstate
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2142 r600_pipe_state_add_reg(rstate
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2143 r600_pipe_state_add_reg(rstate
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2144 r600_pipe_state_add_reg(rstate
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2145 r600_pipe_state_add_reg(rstate
, R_028A40_VGT_GS_MODE
, 0x0, 0xFFFFFFFF, NULL
, 0);
2146 r600_pipe_state_add_reg(rstate
, R_028B94_VGT_STRMOUT_CONFIG
, 0x0, 0xFFFFFFFF, NULL
, 0);
2147 r600_pipe_state_add_reg(rstate
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0, 0xFFFFFFFF, NULL
, 0);
2148 r600_pipe_state_add_reg(rstate
, R_028AB4_VGT_REUSE_OFF
, 0x00000000, 0xFFFFFFFF, NULL
, 0);
2149 r600_pipe_state_add_reg(rstate
, R_028AB8_VGT_VTX_CNT_EN
, 0x0, 0xFFFFFFFF, NULL
, 0);
2150 r600_pipe_state_add_reg(rstate
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1, 0xFFFFFFFF, NULL
, 0);
2152 r600_pipe_state_add_reg(rstate
, R_028380_SQ_VTX_SEMANTIC_0
, 0x0, 0xFFFFFFFF, NULL
, 0);
2153 r600_pipe_state_add_reg(rstate
, R_028384_SQ_VTX_SEMANTIC_1
, 0x0, 0xFFFFFFFF, NULL
, 0);
2154 r600_pipe_state_add_reg(rstate
, R_028388_SQ_VTX_SEMANTIC_2
, 0x0, 0xFFFFFFFF, NULL
, 0);
2155 r600_pipe_state_add_reg(rstate
, R_02838C_SQ_VTX_SEMANTIC_3
, 0x0, 0xFFFFFFFF, NULL
, 0);
2156 r600_pipe_state_add_reg(rstate
, R_028390_SQ_VTX_SEMANTIC_4
, 0x0, 0xFFFFFFFF, NULL
, 0);
2157 r600_pipe_state_add_reg(rstate
, R_028394_SQ_VTX_SEMANTIC_5
, 0x0, 0xFFFFFFFF, NULL
, 0);
2158 r600_pipe_state_add_reg(rstate
, R_028398_SQ_VTX_SEMANTIC_6
, 0x0, 0xFFFFFFFF, NULL
, 0);
2159 r600_pipe_state_add_reg(rstate
, R_02839C_SQ_VTX_SEMANTIC_7
, 0x0, 0xFFFFFFFF, NULL
, 0);
2160 r600_pipe_state_add_reg(rstate
, R_0283A0_SQ_VTX_SEMANTIC_8
, 0x0, 0xFFFFFFFF, NULL
, 0);
2161 r600_pipe_state_add_reg(rstate
, R_0283A4_SQ_VTX_SEMANTIC_9
, 0x0, 0xFFFFFFFF, NULL
, 0);
2162 r600_pipe_state_add_reg(rstate
, R_0283A8_SQ_VTX_SEMANTIC_10
, 0x0, 0xFFFFFFFF, NULL
, 0);
2163 r600_pipe_state_add_reg(rstate
, R_0283AC_SQ_VTX_SEMANTIC_11
, 0x0, 0xFFFFFFFF, NULL
, 0);
2164 r600_pipe_state_add_reg(rstate
, R_0283B0_SQ_VTX_SEMANTIC_12
, 0x0, 0xFFFFFFFF, NULL
, 0);
2165 r600_pipe_state_add_reg(rstate
, R_0283B4_SQ_VTX_SEMANTIC_13
, 0x0, 0xFFFFFFFF, NULL
, 0);
2166 r600_pipe_state_add_reg(rstate
, R_0283B8_SQ_VTX_SEMANTIC_14
, 0x0, 0xFFFFFFFF, NULL
, 0);
2167 r600_pipe_state_add_reg(rstate
, R_0283BC_SQ_VTX_SEMANTIC_15
, 0x0, 0xFFFFFFFF, NULL
, 0);
2168 r600_pipe_state_add_reg(rstate
, R_0283C0_SQ_VTX_SEMANTIC_16
, 0x0, 0xFFFFFFFF, NULL
, 0);
2169 r600_pipe_state_add_reg(rstate
, R_0283C4_SQ_VTX_SEMANTIC_17
, 0x0, 0xFFFFFFFF, NULL
, 0);
2170 r600_pipe_state_add_reg(rstate
, R_0283C8_SQ_VTX_SEMANTIC_18
, 0x0, 0xFFFFFFFF, NULL
, 0);
2171 r600_pipe_state_add_reg(rstate
, R_0283CC_SQ_VTX_SEMANTIC_19
, 0x0, 0xFFFFFFFF, NULL
, 0);
2172 r600_pipe_state_add_reg(rstate
, R_0283D0_SQ_VTX_SEMANTIC_20
, 0x0, 0xFFFFFFFF, NULL
, 0);
2173 r600_pipe_state_add_reg(rstate
, R_0283D4_SQ_VTX_SEMANTIC_21
, 0x0, 0xFFFFFFFF, NULL
, 0);
2174 r600_pipe_state_add_reg(rstate
, R_0283D8_SQ_VTX_SEMANTIC_22
, 0x0, 0xFFFFFFFF, NULL
, 0);
2175 r600_pipe_state_add_reg(rstate
, R_0283DC_SQ_VTX_SEMANTIC_23
, 0x0, 0xFFFFFFFF, NULL
, 0);
2176 r600_pipe_state_add_reg(rstate
, R_0283E0_SQ_VTX_SEMANTIC_24
, 0x0, 0xFFFFFFFF, NULL
, 0);
2177 r600_pipe_state_add_reg(rstate
, R_0283E4_SQ_VTX_SEMANTIC_25
, 0x0, 0xFFFFFFFF, NULL
, 0);
2178 r600_pipe_state_add_reg(rstate
, R_0283E8_SQ_VTX_SEMANTIC_26
, 0x0, 0xFFFFFFFF, NULL
, 0);
2179 r600_pipe_state_add_reg(rstate
, R_0283EC_SQ_VTX_SEMANTIC_27
, 0x0, 0xFFFFFFFF, NULL
, 0);
2180 r600_pipe_state_add_reg(rstate
, R_0283F0_SQ_VTX_SEMANTIC_28
, 0x0, 0xFFFFFFFF, NULL
, 0);
2181 r600_pipe_state_add_reg(rstate
, R_0283F4_SQ_VTX_SEMANTIC_29
, 0x0, 0xFFFFFFFF, NULL
, 0);
2182 r600_pipe_state_add_reg(rstate
, R_0283F8_SQ_VTX_SEMANTIC_30
, 0x0, 0xFFFFFFFF, NULL
, 0);
2183 r600_pipe_state_add_reg(rstate
, R_0283FC_SQ_VTX_SEMANTIC_31
, 0x0, 0xFFFFFFFF, NULL
, 0);
2185 r600_pipe_state_add_reg(rstate
, R_028810_PA_CL_CLIP_CNTL
, 0x0, 0xFFFFFFFF, NULL
, 0);
2187 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
2190 void evergreen_polygon_offset_update(struct r600_pipe_context
*rctx
)
2192 struct r600_pipe_state state
;
2194 state
.id
= R600_PIPE_STATE_POLYGON_OFFSET
;
2196 if (rctx
->rasterizer
&& rctx
->framebuffer
.zsbuf
) {
2197 float offset_units
= rctx
->rasterizer
->offset_units
;
2198 unsigned offset_db_fmt_cntl
= 0, depth
;
2200 switch (rctx
->framebuffer
.zsbuf
->texture
->format
) {
2201 case PIPE_FORMAT_Z24X8_UNORM
:
2202 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2204 offset_units
*= 2.0f
;
2206 case PIPE_FORMAT_Z32_FLOAT
:
2207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2209 offset_units
*= 1.0f
;
2210 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2212 case PIPE_FORMAT_Z16_UNORM
:
2214 offset_units
*= 4.0f
;
2219 /* FIXME some of those reg can be computed with cso */
2220 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
2221 r600_pipe_state_add_reg(&state
,
2222 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
2223 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
, 0);
2224 r600_pipe_state_add_reg(&state
,
2225 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
2226 fui(offset_units
), 0xFFFFFFFF, NULL
, 0);
2227 r600_pipe_state_add_reg(&state
,
2228 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
2229 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
, 0);
2230 r600_pipe_state_add_reg(&state
,
2231 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
2232 fui(offset_units
), 0xFFFFFFFF, NULL
, 0);
2233 r600_pipe_state_add_reg(&state
,
2234 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
2235 offset_db_fmt_cntl
, 0xFFFFFFFF, NULL
, 0);
2236 r600_context_pipe_state_set(&rctx
->ctx
, &state
);
2240 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2242 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
2243 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2244 struct r600_shader
*rshader
= &shader
->shader
;
2245 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
2246 int pos_index
= -1, face_index
= -1;
2248 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
2249 unsigned spi_baryc_cntl
;
2253 db_shader_control
= 0;
2254 for (i
= 0; i
< rshader
->ninput
; i
++) {
2255 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2256 POSITION goes via GPRs from the SC so isn't counted */
2257 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2259 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
2263 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
2265 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
2266 have_perspective
= TRUE
;
2267 if (rshader
->input
[i
].centroid
)
2268 have_centroid
= TRUE
;
2271 for (i
= 0; i
< rshader
->noutput
; i
++) {
2272 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2273 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(1);
2274 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2275 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(1);
2277 if (rshader
->uses_kill
)
2278 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2282 for (i
= 0; i
< rshader
->noutput
; i
++) {
2283 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2284 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2286 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
2287 if (rshader
->fs_write_all
)
2288 num_cout
= rshader
->nr_cbufs
;
2293 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
2295 /* always at least export 1 component per pixel */
2301 have_perspective
= TRUE
;
2304 if (!have_perspective
&& !have_linear
)
2305 have_perspective
= TRUE
;
2307 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
2308 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
2309 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
2311 if (pos_index
!= -1) {
2312 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
2313 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
2314 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
2318 spi_ps_in_control_1
= 0;
2319 if (face_index
!= -1) {
2320 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2321 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2325 if (have_perspective
)
2326 spi_baryc_cntl
|= S_0286E0_PERSP_CENTER_ENA(1) |
2327 S_0286E0_PERSP_CENTROID_ENA(have_centroid
);
2329 spi_baryc_cntl
|= S_0286E0_LINEAR_CENTER_ENA(1) |
2330 S_0286E0_LINEAR_CENTROID_ENA(have_centroid
);
2332 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
,
2333 spi_ps_in_control_0
, 0xFFFFFFFF, NULL
, 0);
2334 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
,
2335 spi_ps_in_control_1
, 0xFFFFFFFF, NULL
, 0);
2336 r600_pipe_state_add_reg(rstate
, R_0286E4_SPI_PS_IN_CONTROL_2
,
2337 0, 0xFFFFFFFF, NULL
, 0);
2338 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
, 0xFFFFFFFF, NULL
, 0);
2339 r600_pipe_state_add_reg(rstate
,
2340 R_0286E0_SPI_BARYC_CNTL
,
2342 0xFFFFFFFF, NULL
, 0);
2344 r600_pipe_state_add_reg(rstate
,
2345 R_028840_SQ_PGM_START_PS
,
2346 0, 0xFFFFFFFF, shader
->bo
, RADEON_USAGE_READ
);
2347 r600_pipe_state_add_reg(rstate
,
2348 R_028844_SQ_PGM_RESOURCES_PS
,
2349 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
2350 S_028844_PRIME_CACHE_ON_DRAW(1) |
2351 S_028844_STACK_SIZE(rshader
->bc
.nstack
),
2352 0xFFFFFFFF, NULL
, 0);
2353 r600_pipe_state_add_reg(rstate
,
2354 R_028848_SQ_PGM_RESOURCES_2_PS
,
2355 0x0, 0xFFFFFFFF, NULL
, 0);
2356 r600_pipe_state_add_reg(rstate
,
2357 R_02884C_SQ_PGM_EXPORTS_PS
,
2358 exports_ps
, 0xFFFFFFFF, NULL
, 0);
2359 /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */
2360 /* only set some bits here, the other bits are set in the dsa state */
2361 r600_pipe_state_add_reg(rstate
,
2362 R_02880C_DB_SHADER_CONTROL
,
2364 S_02880C_Z_EXPORT_ENABLE(1) |
2365 S_02880C_STENCIL_EXPORT_ENABLE(1) |
2366 S_02880C_KILL_ENABLE(1),
2368 r600_pipe_state_add_reg(rstate
,
2369 R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF,
2370 0xFFFFFFFF, NULL
, 0);
2373 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2375 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
2376 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2377 struct r600_shader
*rshader
= &shader
->shader
;
2378 unsigned spi_vs_out_id
[10] = {};
2379 unsigned i
, tmp
, nparams
= 0;
2381 /* clear previous register */
2384 for (i
= 0; i
< rshader
->noutput
; i
++) {
2385 if (rshader
->output
[i
].spi_sid
) {
2386 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
2387 spi_vs_out_id
[nparams
/ 4] |= tmp
;
2392 for (i
= 0; i
< 10; i
++) {
2393 r600_pipe_state_add_reg(rstate
,
2394 R_02861C_SPI_VS_OUT_ID_0
+ i
* 4,
2395 spi_vs_out_id
[i
], 0xFFFFFFFF, NULL
, 0);
2398 /* Certain attributes (position, psize, etc.) don't count as params.
2399 * VS is required to export at least one param and r600_shader_from_tgsi()
2400 * takes care of adding a dummy export.
2405 r600_pipe_state_add_reg(rstate
,
2406 R_0286C4_SPI_VS_OUT_CONFIG
,
2407 S_0286C4_VS_EXPORT_COUNT(nparams
- 1),
2408 0xFFFFFFFF, NULL
, 0);
2409 r600_pipe_state_add_reg(rstate
,
2410 R_028860_SQ_PGM_RESOURCES_VS
,
2411 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
2412 S_028860_STACK_SIZE(rshader
->bc
.nstack
),
2413 0xFFFFFFFF, NULL
, 0);
2414 r600_pipe_state_add_reg(rstate
,
2415 R_028864_SQ_PGM_RESOURCES_2_VS
,
2416 0x0, 0xFFFFFFFF, NULL
, 0);
2417 r600_pipe_state_add_reg(rstate
,
2418 R_02885C_SQ_PGM_START_VS
,
2419 0, 0xFFFFFFFF, shader
->bo
, RADEON_USAGE_READ
);
2421 r600_pipe_state_add_reg(rstate
,
2422 R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF,
2423 0xFFFFFFFF, NULL
, 0);
2426 void evergreen_fetch_shader(struct pipe_context
*ctx
,
2427 struct r600_vertex_element
*ve
)
2429 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
2430 struct r600_pipe_state
*rstate
= &ve
->rstate
;
2431 rstate
->id
= R600_PIPE_STATE_FETCH_SHADER
;
2433 r600_pipe_state_add_reg(rstate
, R_0288A8_SQ_PGM_RESOURCES_FS
,
2434 0x00000000, 0xFFFFFFFF, NULL
, 0);
2435 r600_pipe_state_add_reg(rstate
, R_0288A4_SQ_PGM_START_FS
,
2437 0xFFFFFFFF, ve
->fetch_shader
, RADEON_USAGE_READ
);
2440 void *evergreen_create_db_flush_dsa(struct r600_pipe_context
*rctx
)
2442 struct pipe_depth_stencil_alpha_state dsa
;
2443 struct r600_pipe_state
*rstate
;
2445 memset(&dsa
, 0, sizeof(dsa
));
2447 rstate
= rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
2448 r600_pipe_state_add_reg(rstate
,
2449 R_02880C_DB_SHADER_CONTROL
,
2451 S_02880C_DUAL_EXPORT_ENABLE(1), NULL
, 0);
2452 r600_pipe_state_add_reg(rstate
,
2453 R_028000_DB_RENDER_CONTROL
,
2454 S_028000_DEPTH_COPY_ENABLE(1) |
2455 S_028000_STENCIL_COPY_ENABLE(1) |
2456 S_028000_COPY_CENTROID(1),
2457 S_028000_DEPTH_COPY_ENABLE(1) |
2458 S_028000_STENCIL_COPY_ENABLE(1) |
2459 S_028000_COPY_CENTROID(1), NULL
, 0);
2463 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context
*rctx
,
2464 struct r600_pipe_resource_state
*rstate
)
2466 rstate
->id
= R600_PIPE_STATE_RESOURCE
;
2469 rstate
->bo
[0] = NULL
;
2471 rstate
->val
[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2472 rstate
->val
[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
2473 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
2474 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
2475 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
);
2479 rstate
->val
[7] = 0xc0000000;
2483 void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state
*rstate
,
2484 struct r600_resource
*rbuffer
,
2485 unsigned offset
, unsigned stride
,
2486 enum radeon_bo_usage usage
)
2488 rstate
->bo
[0] = rbuffer
;
2489 rstate
->bo_usage
[0] = usage
;
2490 rstate
->val
[0] = offset
;
2491 rstate
->val
[1] = rbuffer
->buf
->size
- offset
- 1;
2492 rstate
->val
[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2493 S_030008_STRIDE(stride
);