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gallium/radeon: let drivers specify SC_MODE_CNTL_1 fields
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static inline unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 default:
39 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
40 break;
41 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
42 break;
43 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
44 }
45 }
46
47 static uint32_t eg_num_banks(uint32_t nbanks)
48 {
49 switch (nbanks) {
50 case 2:
51 return 0;
52 case 4:
53 return 1;
54 case 8:
55 default:
56 return 2;
57 case 16:
58 return 3;
59 }
60 }
61
62
63 static unsigned eg_tile_split(unsigned tile_split)
64 {
65 switch (tile_split) {
66 case 64: tile_split = 0; break;
67 case 128: tile_split = 1; break;
68 case 256: tile_split = 2; break;
69 case 512: tile_split = 3; break;
70 default:
71 case 1024: tile_split = 4; break;
72 case 2048: tile_split = 5; break;
73 case 4096: tile_split = 6; break;
74 }
75 return tile_split;
76 }
77
78 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
79 {
80 switch (macro_tile_aspect) {
81 default:
82 case 1: macro_tile_aspect = 0; break;
83 case 2: macro_tile_aspect = 1; break;
84 case 4: macro_tile_aspect = 2; break;
85 case 8: macro_tile_aspect = 3; break;
86 }
87 return macro_tile_aspect;
88 }
89
90 static unsigned eg_bank_wh(unsigned bankwh)
91 {
92 switch (bankwh) {
93 default:
94 case 1: bankwh = 0; break;
95 case 2: bankwh = 1; break;
96 case 4: bankwh = 2; break;
97 case 8: bankwh = 3; break;
98 }
99 return bankwh;
100 }
101
102 static uint32_t r600_translate_blend_function(int blend_func)
103 {
104 switch (blend_func) {
105 case PIPE_BLEND_ADD:
106 return V_028780_COMB_DST_PLUS_SRC;
107 case PIPE_BLEND_SUBTRACT:
108 return V_028780_COMB_SRC_MINUS_DST;
109 case PIPE_BLEND_REVERSE_SUBTRACT:
110 return V_028780_COMB_DST_MINUS_SRC;
111 case PIPE_BLEND_MIN:
112 return V_028780_COMB_MIN_DST_SRC;
113 case PIPE_BLEND_MAX:
114 return V_028780_COMB_MAX_DST_SRC;
115 default:
116 R600_ERR("Unknown blend function %d\n", blend_func);
117 assert(0);
118 break;
119 }
120 return 0;
121 }
122
123 static uint32_t r600_translate_blend_factor(int blend_fact)
124 {
125 switch (blend_fact) {
126 case PIPE_BLENDFACTOR_ONE:
127 return V_028780_BLEND_ONE;
128 case PIPE_BLENDFACTOR_SRC_COLOR:
129 return V_028780_BLEND_SRC_COLOR;
130 case PIPE_BLENDFACTOR_SRC_ALPHA:
131 return V_028780_BLEND_SRC_ALPHA;
132 case PIPE_BLENDFACTOR_DST_ALPHA:
133 return V_028780_BLEND_DST_ALPHA;
134 case PIPE_BLENDFACTOR_DST_COLOR:
135 return V_028780_BLEND_DST_COLOR;
136 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
137 return V_028780_BLEND_SRC_ALPHA_SATURATE;
138 case PIPE_BLENDFACTOR_CONST_COLOR:
139 return V_028780_BLEND_CONST_COLOR;
140 case PIPE_BLENDFACTOR_CONST_ALPHA:
141 return V_028780_BLEND_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_ZERO:
143 return V_028780_BLEND_ZERO;
144 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
145 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
146 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
147 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
148 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
149 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
150 case PIPE_BLENDFACTOR_INV_DST_COLOR:
151 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
152 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
153 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
154 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
155 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
156 case PIPE_BLENDFACTOR_SRC1_COLOR:
157 return V_028780_BLEND_SRC1_COLOR;
158 case PIPE_BLENDFACTOR_SRC1_ALPHA:
159 return V_028780_BLEND_SRC1_ALPHA;
160 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
161 return V_028780_BLEND_INV_SRC1_COLOR;
162 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
163 return V_028780_BLEND_INV_SRC1_ALPHA;
164 default:
165 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
166 assert(0);
167 break;
168 }
169 return 0;
170 }
171
172 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
173 {
174 switch (dim) {
175 default:
176 case PIPE_TEXTURE_1D:
177 return V_030000_SQ_TEX_DIM_1D;
178 case PIPE_TEXTURE_1D_ARRAY:
179 return V_030000_SQ_TEX_DIM_1D_ARRAY;
180 case PIPE_TEXTURE_2D:
181 case PIPE_TEXTURE_RECT:
182 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
183 V_030000_SQ_TEX_DIM_2D;
184 case PIPE_TEXTURE_2D_ARRAY:
185 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
186 V_030000_SQ_TEX_DIM_2D_ARRAY;
187 case PIPE_TEXTURE_3D:
188 return V_030000_SQ_TEX_DIM_3D;
189 case PIPE_TEXTURE_CUBE:
190 case PIPE_TEXTURE_CUBE_ARRAY:
191 return V_030000_SQ_TEX_DIM_CUBEMAP;
192 }
193 }
194
195 static uint32_t r600_translate_dbformat(enum pipe_format format)
196 {
197 switch (format) {
198 case PIPE_FORMAT_Z16_UNORM:
199 return V_028040_Z_16;
200 case PIPE_FORMAT_Z24X8_UNORM:
201 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
202 case PIPE_FORMAT_X8Z24_UNORM:
203 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
204 return V_028040_Z_24;
205 case PIPE_FORMAT_Z32_FLOAT:
206 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
207 return V_028040_Z_32_FLOAT;
208 default:
209 return ~0U;
210 }
211 }
212
213 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
214 {
215 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
216 FALSE) != ~0U;
217 }
218
219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
220 {
221 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
222 r600_translate_colorswap(format, FALSE) != ~0U;
223 }
224
225 static bool r600_is_zs_format_supported(enum pipe_format format)
226 {
227 return r600_translate_dbformat(format) != ~0U;
228 }
229
230 boolean evergreen_is_format_supported(struct pipe_screen *screen,
231 enum pipe_format format,
232 enum pipe_texture_target target,
233 unsigned sample_count,
234 unsigned usage)
235 {
236 struct r600_screen *rscreen = (struct r600_screen*)screen;
237 unsigned retval = 0;
238
239 if (target >= PIPE_MAX_TEXTURE_TYPES) {
240 R600_ERR("r600: unsupported texture type %d\n", target);
241 return FALSE;
242 }
243
244 if (!util_format_is_supported(format, usage))
245 return FALSE;
246
247 if (sample_count > 1) {
248 if (!rscreen->has_msaa)
249 return FALSE;
250
251 switch (sample_count) {
252 case 2:
253 case 4:
254 case 8:
255 break;
256 default:
257 return FALSE;
258 }
259 }
260
261 if (usage & PIPE_BIND_SAMPLER_VIEW) {
262 if (target == PIPE_BUFFER) {
263 if (r600_is_vertex_format_supported(format))
264 retval |= PIPE_BIND_SAMPLER_VIEW;
265 } else {
266 if (r600_is_sampler_format_supported(screen, format))
267 retval |= PIPE_BIND_SAMPLER_VIEW;
268 }
269 }
270
271 if ((usage & (PIPE_BIND_RENDER_TARGET |
272 PIPE_BIND_DISPLAY_TARGET |
273 PIPE_BIND_SCANOUT |
274 PIPE_BIND_SHARED |
275 PIPE_BIND_BLENDABLE)) &&
276 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
277 retval |= usage &
278 (PIPE_BIND_RENDER_TARGET |
279 PIPE_BIND_DISPLAY_TARGET |
280 PIPE_BIND_SCANOUT |
281 PIPE_BIND_SHARED);
282 if (!util_format_is_pure_integer(format) &&
283 !util_format_is_depth_or_stencil(format))
284 retval |= usage & PIPE_BIND_BLENDABLE;
285 }
286
287 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
288 r600_is_zs_format_supported(format)) {
289 retval |= PIPE_BIND_DEPTH_STENCIL;
290 }
291
292 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
293 r600_is_vertex_format_supported(format)) {
294 retval |= PIPE_BIND_VERTEX_BUFFER;
295 }
296
297 if (usage & PIPE_BIND_TRANSFER_READ)
298 retval |= PIPE_BIND_TRANSFER_READ;
299 if (usage & PIPE_BIND_TRANSFER_WRITE)
300 retval |= PIPE_BIND_TRANSFER_WRITE;
301
302 if ((usage & PIPE_BIND_LINEAR) &&
303 !util_format_is_compressed(format) &&
304 !(usage & PIPE_BIND_DEPTH_STENCIL))
305 retval |= PIPE_BIND_LINEAR;
306
307 return retval == usage;
308 }
309
310 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
311 const struct pipe_blend_state *state, int mode)
312 {
313 uint32_t color_control = 0, target_mask = 0;
314 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
315
316 if (!blend) {
317 return NULL;
318 }
319
320 r600_init_command_buffer(&blend->buffer, 20);
321 r600_init_command_buffer(&blend->buffer_no_blend, 20);
322
323 if (state->logicop_enable) {
324 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
325 } else {
326 color_control |= (0xcc << 16);
327 }
328 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
329 if (state->independent_blend_enable) {
330 for (int i = 0; i < 8; i++) {
331 target_mask |= (state->rt[i].colormask << (4 * i));
332 }
333 } else {
334 for (int i = 0; i < 8; i++) {
335 target_mask |= (state->rt[0].colormask << (4 * i));
336 }
337 }
338
339 /* only have dual source on MRT0 */
340 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
341 blend->cb_target_mask = target_mask;
342 blend->alpha_to_one = state->alpha_to_one;
343
344 if (target_mask)
345 color_control |= S_028808_MODE(mode);
346 else
347 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
348
349
350 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
351 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
352 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
353 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
354 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
355 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
356 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
357 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
358
359 /* Copy over the dwords set so far into buffer_no_blend.
360 * Only the CB_BLENDi_CONTROL registers must be set after this. */
361 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
362 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
363
364 for (int i = 0; i < 8; i++) {
365 /* state->rt entries > 0 only written if independent blending */
366 const int j = state->independent_blend_enable ? i : 0;
367
368 unsigned eqRGB = state->rt[j].rgb_func;
369 unsigned srcRGB = state->rt[j].rgb_src_factor;
370 unsigned dstRGB = state->rt[j].rgb_dst_factor;
371 unsigned eqA = state->rt[j].alpha_func;
372 unsigned srcA = state->rt[j].alpha_src_factor;
373 unsigned dstA = state->rt[j].alpha_dst_factor;
374 uint32_t bc = 0;
375
376 r600_store_value(&blend->buffer_no_blend, 0);
377
378 if (!state->rt[j].blend_enable) {
379 r600_store_value(&blend->buffer, 0);
380 continue;
381 }
382
383 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
384 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
385 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
386 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
387
388 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
389 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
390 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
391 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
392 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
393 }
394 r600_store_value(&blend->buffer, bc);
395 }
396 return blend;
397 }
398
399 static void *evergreen_create_blend_state(struct pipe_context *ctx,
400 const struct pipe_blend_state *state)
401 {
402
403 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
404 }
405
406 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
407 const struct pipe_depth_stencil_alpha_state *state)
408 {
409 unsigned db_depth_control, alpha_test_control, alpha_ref;
410 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
411
412 if (!dsa) {
413 return NULL;
414 }
415
416 r600_init_command_buffer(&dsa->buffer, 3);
417
418 dsa->valuemask[0] = state->stencil[0].valuemask;
419 dsa->valuemask[1] = state->stencil[1].valuemask;
420 dsa->writemask[0] = state->stencil[0].writemask;
421 dsa->writemask[1] = state->stencil[1].writemask;
422 dsa->zwritemask = state->depth.writemask;
423
424 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
425 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
426 S_028800_ZFUNC(state->depth.func);
427
428 /* stencil */
429 if (state->stencil[0].enabled) {
430 db_depth_control |= S_028800_STENCIL_ENABLE(1);
431 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
432 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
433 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
434 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
435
436 if (state->stencil[1].enabled) {
437 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
438 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
439 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
440 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
441 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
442 }
443 }
444
445 /* alpha */
446 alpha_test_control = 0;
447 alpha_ref = 0;
448 if (state->alpha.enabled) {
449 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
450 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
451 alpha_ref = fui(state->alpha.ref_value);
452 }
453 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
454 dsa->alpha_ref = alpha_ref;
455
456 /* misc */
457 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
458 return dsa;
459 }
460
461 static void *evergreen_create_rs_state(struct pipe_context *ctx,
462 const struct pipe_rasterizer_state *state)
463 {
464 struct r600_context *rctx = (struct r600_context *)ctx;
465 unsigned tmp, spi_interp;
466 float psize_min, psize_max;
467 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
468
469 if (!rs) {
470 return NULL;
471 }
472
473 r600_init_command_buffer(&rs->buffer, 30);
474
475 rs->scissor_enable = state->scissor;
476 rs->flatshade = state->flatshade;
477 rs->sprite_coord_enable = state->sprite_coord_enable;
478 rs->two_side = state->light_twoside;
479 rs->clip_plane_enable = state->clip_plane_enable;
480 rs->pa_sc_line_stipple = state->line_stipple_enable ?
481 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
482 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
483 rs->pa_cl_clip_cntl =
484 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
485 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
486 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
487 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
488 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
489 rs->multisample_enable = state->multisample;
490
491 /* offset */
492 rs->offset_units = state->offset_units;
493 rs->offset_scale = state->offset_scale * 16.0f;
494 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
495
496 if (state->point_size_per_vertex) {
497 psize_min = util_get_min_point_size(state);
498 psize_max = 8192;
499 } else {
500 /* Force the point size to be as if the vertex output was disabled. */
501 psize_min = state->point_size;
502 psize_max = state->point_size;
503 }
504
505 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
506 if (state->sprite_coord_enable) {
507 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
508 S_0286D4_PNT_SPRITE_OVRD_X(2) |
509 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
510 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
511 S_0286D4_PNT_SPRITE_OVRD_W(1);
512 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
513 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
514 }
515 }
516
517 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
518 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
519 tmp = r600_pack_float_12p4(state->point_size/2);
520 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
521 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
522 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
523 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
524 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
525 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
526 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
527
528 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
529 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
530 S_028A48_MSAA_ENABLE(state->multisample) |
531 S_028A48_VPORT_SCISSOR_ENABLE(1) |
532 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
533
534 if (rctx->b.chip_class == CAYMAN) {
535 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
536 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
537 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
538 } else {
539 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
540 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
541 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
542 }
543
544 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
545 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
546 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
547 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
548 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
549 S_028814_FACE(!state->front_ccw) |
550 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
551 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
552 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
553 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
554 state->fill_back != PIPE_POLYGON_MODE_FILL) |
555 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
556 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
557 return rs;
558 }
559
560 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
561 const struct pipe_sampler_state *state)
562 {
563 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
564 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
565 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
566 : state->max_anisotropy;
567 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
568
569 if (!ss) {
570 return NULL;
571 }
572
573 ss->border_color_use = sampler_state_needs_border_color(state);
574
575 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
576 ss->tex_sampler_words[0] =
577 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
578 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
579 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
580 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
581 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
582 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
583 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
584 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
585 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
586 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
587 ss->tex_sampler_words[1] =
588 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
589 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
590 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
591 ss->tex_sampler_words[2] =
592 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
593 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
594 S_03C008_TYPE(1);
595
596 if (ss->border_color_use) {
597 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
598 }
599 return ss;
600 }
601
602 static struct pipe_sampler_view *
603 texture_buffer_sampler_view(struct r600_context *rctx,
604 struct r600_pipe_sampler_view *view,
605 unsigned width0, unsigned height0)
606
607 {
608 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
609 uint64_t va;
610 int stride = util_format_get_blocksize(view->base.format);
611 unsigned format, num_format, format_comp, endian;
612 unsigned swizzle_res;
613 unsigned char swizzle[4];
614 const struct util_format_description *desc;
615 unsigned offset = view->base.u.buf.first_element * stride;
616 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
617
618 swizzle[0] = view->base.swizzle_r;
619 swizzle[1] = view->base.swizzle_g;
620 swizzle[2] = view->base.swizzle_b;
621 swizzle[3] = view->base.swizzle_a;
622
623 r600_vertex_data_type(view->base.format,
624 &format, &num_format, &format_comp,
625 &endian);
626
627 desc = util_format_description(view->base.format);
628
629 swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
630
631 va = tmp->resource.gpu_address + offset;
632 view->tex_resource = &tmp->resource;
633
634 view->skip_mip_address_reloc = true;
635 view->tex_resource_words[0] = va;
636 view->tex_resource_words[1] = size - 1;
637 view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
638 S_030008_STRIDE(stride) |
639 S_030008_DATA_FORMAT(format) |
640 S_030008_NUM_FORMAT_ALL(num_format) |
641 S_030008_FORMAT_COMP_ALL(format_comp) |
642 S_030008_ENDIAN_SWAP(endian);
643 view->tex_resource_words[3] = swizzle_res;
644 /*
645 * in theory dword 4 is for number of elements, for use with resinfo,
646 * but it seems to utterly fail to work, the amd gpu shader analyser
647 * uses a const buffer to store the element sizes for buffer txq
648 */
649 view->tex_resource_words[4] = 0;
650 view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
651 view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
652
653 if (tmp->resource.gpu_address)
654 LIST_ADDTAIL(&view->list, &rctx->b.texture_buffers);
655 return &view->base;
656 }
657
658 struct pipe_sampler_view *
659 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
660 struct pipe_resource *texture,
661 const struct pipe_sampler_view *state,
662 unsigned width0, unsigned height0,
663 unsigned force_level)
664 {
665 struct r600_context *rctx = (struct r600_context*)ctx;
666 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
667 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
668 struct r600_texture *tmp = (struct r600_texture*)texture;
669 unsigned format, endian;
670 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
671 unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
672 unsigned height, depth, width;
673 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
674 enum pipe_format pipe_format = state->format;
675 struct radeon_surf_level *surflevel;
676 unsigned base_level, first_level, last_level;
677 unsigned dim, last_layer;
678 uint64_t va;
679 bool do_endian_swap = FALSE;
680
681 if (!view)
682 return NULL;
683
684 /* initialize base object */
685 view->base = *state;
686 view->base.texture = NULL;
687 pipe_reference(NULL, &texture->reference);
688 view->base.texture = texture;
689 view->base.reference.count = 1;
690 view->base.context = ctx;
691
692 if (state->target == PIPE_BUFFER)
693 return texture_buffer_sampler_view(rctx, view, width0, height0);
694
695 swizzle[0] = state->swizzle_r;
696 swizzle[1] = state->swizzle_g;
697 swizzle[2] = state->swizzle_b;
698 swizzle[3] = state->swizzle_a;
699
700 tile_split = tmp->surface.tile_split;
701 surflevel = tmp->surface.level;
702
703 /* Texturing with separate depth and stencil. */
704 if (tmp->is_depth && !tmp->is_flushing_texture) {
705 switch (pipe_format) {
706 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
707 pipe_format = PIPE_FORMAT_Z32_FLOAT;
708 break;
709 case PIPE_FORMAT_X8Z24_UNORM:
710 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
711 /* Z24 is always stored like this. */
712 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
713 break;
714 case PIPE_FORMAT_X24S8_UINT:
715 case PIPE_FORMAT_S8X24_UINT:
716 case PIPE_FORMAT_X32_S8X24_UINT:
717 pipe_format = PIPE_FORMAT_S8_UINT;
718 tile_split = tmp->surface.stencil_tile_split;
719 surflevel = tmp->surface.stencil_level;
720 break;
721 default:;
722 }
723 }
724
725 if (R600_BIG_ENDIAN)
726 do_endian_swap = !(tmp->is_depth && !tmp->is_flushing_texture);
727
728 format = r600_translate_texformat(ctx->screen, pipe_format,
729 swizzle,
730 &word4, &yuv_format, do_endian_swap);
731 assert(format != ~0);
732 if (format == ~0) {
733 FREE(view);
734 return NULL;
735 }
736
737 endian = r600_colorformat_endian_swap(format, do_endian_swap);
738
739 base_level = 0;
740 first_level = state->u.tex.first_level;
741 last_level = state->u.tex.last_level;
742 width = width0;
743 height = height0;
744 depth = texture->depth0;
745
746 if (force_level) {
747 base_level = force_level;
748 first_level = 0;
749 last_level = 0;
750 width = u_minify(width, force_level);
751 height = u_minify(height, force_level);
752 depth = u_minify(depth, force_level);
753 }
754
755 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
756 non_disp_tiling = tmp->non_disp_tiling;
757
758 switch (surflevel[base_level].mode) {
759 default:
760 case RADEON_SURF_MODE_LINEAR_ALIGNED:
761 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
762 break;
763 case RADEON_SURF_MODE_2D:
764 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
765 break;
766 case RADEON_SURF_MODE_1D:
767 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
768 break;
769 }
770 macro_aspect = tmp->surface.mtilea;
771 bankw = tmp->surface.bankw;
772 bankh = tmp->surface.bankh;
773 tile_split = eg_tile_split(tile_split);
774 macro_aspect = eg_macro_tile_aspect(macro_aspect);
775 bankw = eg_bank_wh(bankw);
776 bankh = eg_bank_wh(bankh);
777 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
778
779 /* 128 bit formats require tile type = 1 */
780 if (rscreen->b.chip_class == CAYMAN) {
781 if (util_format_get_blocksize(pipe_format) >= 16)
782 non_disp_tiling = 1;
783 }
784 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
785
786 if (state->target == PIPE_TEXTURE_1D_ARRAY) {
787 height = 1;
788 depth = texture->array_size;
789 } else if (state->target == PIPE_TEXTURE_2D_ARRAY) {
790 depth = texture->array_size;
791 } else if (state->target == PIPE_TEXTURE_CUBE_ARRAY)
792 depth = texture->array_size / 6;
793
794 va = tmp->resource.gpu_address;
795
796 if (state->format == PIPE_FORMAT_X24S8_UINT ||
797 state->format == PIPE_FORMAT_S8X24_UINT ||
798 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
799 state->format == PIPE_FORMAT_S8_UINT)
800 view->is_stencil_sampler = true;
801
802 view->tex_resource = &tmp->resource;
803
804 /* array type views and views into array types need to use layer offset */
805 dim = state->target;
806 if (state->target != PIPE_TEXTURE_CUBE)
807 dim = MAX2(state->target, texture->target);
808
809 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(dim, texture->nr_samples)) |
810 S_030000_PITCH((pitch / 8) - 1) |
811 S_030000_TEX_WIDTH(width - 1));
812 if (rscreen->b.chip_class == CAYMAN)
813 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
814 else
815 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
816 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
817 S_030004_TEX_DEPTH(depth - 1) |
818 S_030004_ARRAY_MODE(array_mode));
819 view->tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
820
821 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
822 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
823 if (tmp->is_depth) {
824 /* disable FMASK (0 = disabled) */
825 view->tex_resource_words[3] = 0;
826 view->skip_mip_address_reloc = true;
827 } else {
828 /* FMASK should be in MIP_ADDRESS for multisample textures */
829 view->tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
830 }
831 } else if (last_level && texture->nr_samples <= 1) {
832 view->tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
833 } else {
834 view->tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
835 }
836
837 last_layer = state->u.tex.last_layer;
838 if (state->target != texture->target && depth == 1) {
839 last_layer = state->u.tex.first_layer;
840 }
841 view->tex_resource_words[4] = (word4 |
842 S_030010_ENDIAN_SWAP(endian));
843 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
844 S_030014_LAST_ARRAY(last_layer);
845 view->tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
846
847 if (texture->nr_samples > 1) {
848 unsigned log_samples = util_logbase2(texture->nr_samples);
849 if (rscreen->b.chip_class == CAYMAN) {
850 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
851 }
852 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
853 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
854 view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
855 } else {
856 bool no_mip = first_level == last_level;
857
858 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
859 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
860 /* aniso max 16 samples */
861 view->tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
862 }
863
864 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
865 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
866 S_03001C_BANK_WIDTH(bankw) |
867 S_03001C_BANK_HEIGHT(bankh) |
868 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
869 S_03001C_NUM_BANKS(nbanks) |
870 S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
871 return &view->base;
872 }
873
874 static struct pipe_sampler_view *
875 evergreen_create_sampler_view(struct pipe_context *ctx,
876 struct pipe_resource *tex,
877 const struct pipe_sampler_view *state)
878 {
879 return evergreen_create_sampler_view_custom(ctx, tex, state,
880 tex->width0, tex->height0, 0);
881 }
882
883 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
884 {
885 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
886 struct r600_config_state *a = (struct r600_config_state*)atom;
887
888 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
889 if (a->dyn_gpr_enabled) {
890 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
891 radeon_emit(cs, 0);
892 radeon_emit(cs, 0);
893 } else {
894 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
895 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
896 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
897 }
898 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
899 if (a->dyn_gpr_enabled) {
900 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
901 S_028838_PS_GPRS(0x1e) |
902 S_028838_VS_GPRS(0x1e) |
903 S_028838_GS_GPRS(0x1e) |
904 S_028838_ES_GPRS(0x1e) |
905 S_028838_HS_GPRS(0x1e) |
906 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
907 }
908 }
909
910 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
911 {
912 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
913 struct pipe_clip_state *state = &rctx->clip_state.state;
914
915 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
916 radeon_emit_array(cs, (unsigned*)state, 6*4);
917 }
918
919 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
920 const struct pipe_poly_stipple *state)
921 {
922 }
923
924 static void evergreen_get_scissor_rect(struct r600_context *rctx,
925 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
926 uint32_t *tl, uint32_t *br)
927 {
928 struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
929
930 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
931
932 *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
933 *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
934 }
935
936 /**
937 * This function intializes the CB* register values for RATs. It is meant
938 * to be used for 1D aligned buffers that do not have an associated
939 * radeon_surf.
940 */
941 void evergreen_init_color_surface_rat(struct r600_context *rctx,
942 struct r600_surface *surf)
943 {
944 struct pipe_resource *pipe_buffer = surf->base.texture;
945 unsigned format = r600_translate_colorformat(rctx->b.chip_class,
946 surf->base.format, FALSE);
947 unsigned endian = r600_colorformat_endian_swap(format, FALSE);
948 unsigned swap = r600_translate_colorswap(surf->base.format, FALSE);
949 unsigned block_size =
950 align(util_format_get_blocksize(pipe_buffer->format), 4);
951 unsigned pitch_alignment =
952 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
953 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
954
955 surf->cb_color_base = r600_resource(pipe_buffer)->gpu_address >> 8;
956
957 surf->cb_color_pitch = (pitch / 8) - 1;
958
959 surf->cb_color_slice = 0;
960
961 surf->cb_color_view = 0;
962
963 surf->cb_color_info =
964 S_028C70_ENDIAN(endian)
965 | S_028C70_FORMAT(format)
966 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
967 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
968 | S_028C70_COMP_SWAP(swap)
969 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
970 * are using NUMBER_UINT */
971 | S_028C70_RAT(1)
972 ;
973
974 surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
975
976 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
977 * elements. */
978 surf->cb_color_dim = pipe_buffer->width0;
979
980 /* Set the buffer range the GPU will have access to: */
981 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
982 0, pipe_buffer->width0);
983
984 surf->cb_color_fmask = surf->cb_color_base;
985 surf->cb_color_fmask_slice = 0;
986 }
987
988 void evergreen_init_color_surface(struct r600_context *rctx,
989 struct r600_surface *surf)
990 {
991 struct r600_screen *rscreen = rctx->screen;
992 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
993 unsigned level = surf->base.u.tex.level;
994 unsigned pitch, slice;
995 unsigned color_info, color_attrib, color_dim = 0, color_view;
996 unsigned format, swap, ntype, endian;
997 uint64_t offset, base_offset;
998 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
999 const struct util_format_description *desc;
1000 int i;
1001 bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
1002
1003 offset = rtex->surface.level[level].offset;
1004 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1005 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1006
1007 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1008 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1009 if (slice) {
1010 slice = slice - 1;
1011 }
1012 color_info = 0;
1013 switch (rtex->surface.level[level].mode) {
1014 default:
1015 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1016 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1017 non_disp_tiling = 1;
1018 break;
1019 case RADEON_SURF_MODE_1D:
1020 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1021 non_disp_tiling = rtex->non_disp_tiling;
1022 break;
1023 case RADEON_SURF_MODE_2D:
1024 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1025 non_disp_tiling = rtex->non_disp_tiling;
1026 break;
1027 }
1028 tile_split = rtex->surface.tile_split;
1029 macro_aspect = rtex->surface.mtilea;
1030 bankw = rtex->surface.bankw;
1031 bankh = rtex->surface.bankh;
1032 if (rtex->fmask.size)
1033 fmask_bankh = rtex->fmask.bank_height;
1034 else
1035 fmask_bankh = rtex->surface.bankh;
1036 tile_split = eg_tile_split(tile_split);
1037 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1038 bankw = eg_bank_wh(bankw);
1039 bankh = eg_bank_wh(bankh);
1040 fmask_bankh = eg_bank_wh(fmask_bankh);
1041
1042 /* 128 bit formats require tile type = 1 */
1043 if (rscreen->b.chip_class == CAYMAN) {
1044 if (util_format_get_blocksize(surf->base.format) >= 16)
1045 non_disp_tiling = 1;
1046 }
1047 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1048 desc = util_format_description(surf->base.format);
1049 for (i = 0; i < 4; i++) {
1050 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1051 break;
1052 }
1053 }
1054
1055 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1056 S_028C74_NUM_BANKS(nbanks) |
1057 S_028C74_BANK_WIDTH(bankw) |
1058 S_028C74_BANK_HEIGHT(bankh) |
1059 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1060 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1061 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1062
1063 if (rctx->b.chip_class == CAYMAN) {
1064 color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1065 PIPE_SWIZZLE_1);
1066
1067 if (rtex->resource.b.b.nr_samples > 1) {
1068 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1069 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1070 S_028C74_NUM_FRAGMENTS(log_samples);
1071 }
1072 }
1073
1074 ntype = V_028C70_NUMBER_UNORM;
1075 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1076 ntype = V_028C70_NUMBER_SRGB;
1077 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1078 if (desc->channel[i].normalized)
1079 ntype = V_028C70_NUMBER_SNORM;
1080 else if (desc->channel[i].pure_integer)
1081 ntype = V_028C70_NUMBER_SINT;
1082 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1083 if (desc->channel[i].normalized)
1084 ntype = V_028C70_NUMBER_UNORM;
1085 else if (desc->channel[i].pure_integer)
1086 ntype = V_028C70_NUMBER_UINT;
1087 }
1088
1089 if (R600_BIG_ENDIAN)
1090 do_endian_swap = !(rtex->is_depth && !rtex->is_flushing_texture);
1091
1092 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format,
1093 do_endian_swap);
1094 assert(format != ~0);
1095
1096 swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
1097 assert(swap != ~0);
1098
1099 endian = r600_colorformat_endian_swap(format, do_endian_swap);
1100
1101 /* blend clamp should be set for all NORM/SRGB types */
1102 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1103 ntype == V_028C70_NUMBER_SRGB)
1104 blend_clamp = 1;
1105
1106 /* set blend bypass according to docs if SINT/UINT or
1107 8/24 COLOR variants */
1108 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1109 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1110 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1111 blend_clamp = 0;
1112 blend_bypass = 1;
1113 }
1114
1115 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1116
1117 color_info |= S_028C70_FORMAT(format) |
1118 S_028C70_COMP_SWAP(swap) |
1119 S_028C70_BLEND_CLAMP(blend_clamp) |
1120 S_028C70_BLEND_BYPASS(blend_bypass) |
1121 S_028C70_NUMBER_TYPE(ntype) |
1122 S_028C70_ENDIAN(endian);
1123
1124 /* EXPORT_NORM is an optimzation that can be enabled for better
1125 * performance in certain cases.
1126 * EXPORT_NORM can be enabled if:
1127 * - 11-bit or smaller UNORM/SNORM/SRGB
1128 * - 16-bit or smaller FLOAT
1129 */
1130 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1131 ((desc->channel[i].size < 12 &&
1132 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1133 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1134 (desc->channel[i].size < 17 &&
1135 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1136 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1137 surf->export_16bpc = true;
1138 }
1139
1140 if (rtex->fmask.size) {
1141 color_info |= S_028C70_COMPRESSION(1);
1142 }
1143
1144 base_offset = rtex->resource.gpu_address;
1145
1146 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1147 surf->cb_color_base = (base_offset + offset) >> 8;
1148 surf->cb_color_dim = color_dim;
1149 surf->cb_color_info = color_info;
1150 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1151 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1152 surf->cb_color_view = color_view;
1153 surf->cb_color_attrib = color_attrib;
1154 if (rtex->fmask.size) {
1155 surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8;
1156 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1157 } else {
1158 surf->cb_color_fmask = surf->cb_color_base;
1159 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1160 }
1161
1162 surf->color_initialized = true;
1163 }
1164
1165 static void evergreen_init_depth_surface(struct r600_context *rctx,
1166 struct r600_surface *surf)
1167 {
1168 struct r600_screen *rscreen = rctx->screen;
1169 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1170 unsigned level = surf->base.u.tex.level;
1171 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1172 uint64_t offset;
1173 unsigned format, array_mode;
1174 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1175
1176
1177 format = r600_translate_dbformat(surf->base.format);
1178 assert(format != ~0);
1179
1180 offset = rtex->resource.gpu_address;
1181 offset += rtex->surface.level[level].offset;
1182
1183 switch (rtex->surface.level[level].mode) {
1184 case RADEON_SURF_MODE_2D:
1185 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1186 break;
1187 case RADEON_SURF_MODE_1D:
1188 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1189 default:
1190 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1191 break;
1192 }
1193 tile_split = rtex->surface.tile_split;
1194 macro_aspect = rtex->surface.mtilea;
1195 bankw = rtex->surface.bankw;
1196 bankh = rtex->surface.bankh;
1197 tile_split = eg_tile_split(tile_split);
1198 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1199 bankw = eg_bank_wh(bankw);
1200 bankh = eg_bank_wh(bankh);
1201 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1202 offset >>= 8;
1203
1204 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1205 S_028040_FORMAT(format) |
1206 S_028040_TILE_SPLIT(tile_split)|
1207 S_028040_NUM_BANKS(nbanks) |
1208 S_028040_BANK_WIDTH(bankw) |
1209 S_028040_BANK_HEIGHT(bankh) |
1210 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1211 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1212 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1213 }
1214
1215 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1216
1217 surf->db_depth_base = offset;
1218 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1219 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1220 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1221 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1222 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1223 levelinfo->nblk_y / 64 - 1);
1224
1225 switch (surf->base.format) {
1226 case PIPE_FORMAT_Z24X8_UNORM:
1227 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1228 case PIPE_FORMAT_X8Z24_UNORM:
1229 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1230 surf->pa_su_poly_offset_db_fmt_cntl =
1231 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1232 break;
1233 case PIPE_FORMAT_Z32_FLOAT:
1234 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1235 surf->pa_su_poly_offset_db_fmt_cntl =
1236 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1237 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1238 break;
1239 case PIPE_FORMAT_Z16_UNORM:
1240 surf->pa_su_poly_offset_db_fmt_cntl =
1241 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1242 break;
1243 default:;
1244 }
1245
1246 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1247 uint64_t stencil_offset;
1248 unsigned stile_split = rtex->surface.stencil_tile_split;
1249
1250 stile_split = eg_tile_split(stile_split);
1251
1252 stencil_offset = rtex->surface.stencil_level[level].offset;
1253 stencil_offset += rtex->resource.gpu_address;
1254
1255 surf->db_stencil_base = stencil_offset >> 8;
1256 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1257 S_028044_TILE_SPLIT(stile_split);
1258 } else {
1259 surf->db_stencil_base = offset;
1260 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1261 * Older kernels are out of luck. */
1262 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1263 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1264 S_028044_FORMAT(V_028044_STENCIL_8);
1265 }
1266
1267 /* use htile only for first level */
1268 if (rtex->htile_buffer && !level) {
1269 uint64_t va = rtex->htile_buffer->gpu_address;
1270 surf->db_htile_data_base = va >> 8;
1271 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1272 S_028ABC_HTILE_HEIGHT(1) |
1273 S_028ABC_FULL_CACHE(1);
1274 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1275 surf->db_preload_control = 0;
1276 }
1277
1278 surf->depth_initialized = true;
1279 }
1280
1281 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1282 const struct pipe_framebuffer_state *state)
1283 {
1284 struct r600_context *rctx = (struct r600_context *)ctx;
1285 struct r600_surface *surf;
1286 struct r600_texture *rtex;
1287 uint32_t i, log_samples;
1288
1289 /* Flush TC when changing the framebuffer state, because the only
1290 * client not using TC that can change textures is the framebuffer.
1291 * Other places don't typically have to flush TC.
1292 */
1293 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1294 R600_CONTEXT_FLUSH_AND_INV |
1295 R600_CONTEXT_FLUSH_AND_INV_CB |
1296 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1297 R600_CONTEXT_FLUSH_AND_INV_DB |
1298 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1299 R600_CONTEXT_INV_TEX_CACHE;
1300
1301 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1302
1303 /* Colorbuffers. */
1304 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1305 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1306 util_format_is_pure_integer(state->cbufs[0]->format);
1307 rctx->framebuffer.compressed_cb_mask = 0;
1308 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1309
1310 for (i = 0; i < state->nr_cbufs; i++) {
1311 surf = (struct r600_surface*)state->cbufs[i];
1312 if (!surf)
1313 continue;
1314
1315 rtex = (struct r600_texture*)surf->base.texture;
1316
1317 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1318
1319 if (!surf->color_initialized) {
1320 evergreen_init_color_surface(rctx, surf);
1321 }
1322
1323 if (!surf->export_16bpc) {
1324 rctx->framebuffer.export_16bpc = false;
1325 }
1326
1327 if (rtex->fmask.size && rtex->cmask.size) {
1328 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1329 }
1330 }
1331
1332 /* Update alpha-test state dependencies.
1333 * Alpha-test is done on the first colorbuffer only. */
1334 if (state->nr_cbufs) {
1335 bool alphatest_bypass = false;
1336 bool export_16bpc = true;
1337
1338 surf = (struct r600_surface*)state->cbufs[0];
1339 if (surf) {
1340 alphatest_bypass = surf->alphatest_bypass;
1341 export_16bpc = surf->export_16bpc;
1342 }
1343
1344 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1345 rctx->alphatest_state.bypass = alphatest_bypass;
1346 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1347 }
1348 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1349 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1350 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1351 }
1352 }
1353
1354 /* ZS buffer. */
1355 if (state->zsbuf) {
1356 surf = (struct r600_surface*)state->zsbuf;
1357
1358 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1359
1360 if (!surf->depth_initialized) {
1361 evergreen_init_depth_surface(rctx, surf);
1362 }
1363
1364 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1365 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1366 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1367 }
1368
1369 if (rctx->db_state.rsurf != surf) {
1370 rctx->db_state.rsurf = surf;
1371 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1372 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1373 }
1374 } else if (rctx->db_state.rsurf) {
1375 rctx->db_state.rsurf = NULL;
1376 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1377 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1378 }
1379
1380 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1381 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1382 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1383 }
1384
1385 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1386 rctx->alphatest_state.bypass = false;
1387 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1388 }
1389
1390 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1391 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1392 if ((rctx->b.chip_class == CAYMAN ||
1393 rctx->b.family == CHIP_RV770) &&
1394 rctx->db_misc_state.log_samples != log_samples) {
1395 rctx->db_misc_state.log_samples = log_samples;
1396 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1397 }
1398
1399
1400 /* Calculate the CS size. */
1401 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1402
1403 /* MSAA. */
1404 if (rctx->b.chip_class == EVERGREEN)
1405 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1406 else
1407 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1408
1409 /* Colorbuffers. */
1410 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1411 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1412 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1413
1414 /* ZS buffer. */
1415 if (state->zsbuf) {
1416 rctx->framebuffer.atom.num_dw += 24;
1417 rctx->framebuffer.atom.num_dw += 2;
1418 } else if (rctx->screen->b.info.drm_minor >= 18) {
1419 rctx->framebuffer.atom.num_dw += 4;
1420 }
1421
1422 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1423
1424 r600_set_sample_locations_constant_buffer(rctx);
1425 }
1426
1427 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1428 {
1429 struct r600_context *rctx = (struct r600_context *)ctx;
1430
1431 if (rctx->ps_iter_samples == min_samples)
1432 return;
1433
1434 rctx->ps_iter_samples = min_samples;
1435 if (rctx->framebuffer.nr_samples > 1) {
1436 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1437 }
1438 }
1439
1440 /* 8xMSAA */
1441 static uint32_t sample_locs_8x[] = {
1442 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1443 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1444 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1445 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1446 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1447 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1448 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1449 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1450 };
1451 static unsigned max_dist_8x = 7;
1452
1453 static void evergreen_get_sample_position(struct pipe_context *ctx,
1454 unsigned sample_count,
1455 unsigned sample_index,
1456 float *out_value)
1457 {
1458 int offset, index;
1459 struct {
1460 int idx:4;
1461 } val;
1462 switch (sample_count) {
1463 case 1:
1464 default:
1465 out_value[0] = out_value[1] = 0.5;
1466 break;
1467 case 2:
1468 offset = 4 * (sample_index * 2);
1469 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1470 out_value[0] = (float)(val.idx + 8) / 16.0f;
1471 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1472 out_value[1] = (float)(val.idx + 8) / 16.0f;
1473 break;
1474 case 4:
1475 offset = 4 * (sample_index * 2);
1476 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1477 out_value[0] = (float)(val.idx + 8) / 16.0f;
1478 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1479 out_value[1] = (float)(val.idx + 8) / 16.0f;
1480 break;
1481 case 8:
1482 offset = 4 * (sample_index % 4 * 2);
1483 index = (sample_index / 4);
1484 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1485 out_value[0] = (float)(val.idx + 8) / 16.0f;
1486 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1487 out_value[1] = (float)(val.idx + 8) / 16.0f;
1488 break;
1489 }
1490 }
1491
1492 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1493 {
1494
1495 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1496 unsigned max_dist = 0;
1497
1498 switch (nr_samples) {
1499 default:
1500 nr_samples = 0;
1501 break;
1502 case 2:
1503 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x));
1504 radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x));
1505 max_dist = eg_max_dist_2x;
1506 break;
1507 case 4:
1508 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x));
1509 radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x));
1510 max_dist = eg_max_dist_4x;
1511 break;
1512 case 8:
1513 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x));
1514 radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x));
1515 max_dist = max_dist_8x;
1516 break;
1517 }
1518
1519 if (nr_samples > 1) {
1520 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1521 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1522 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1523 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1524 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1525 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1526 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1527 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1528 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1529 } else {
1530 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1531 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1532 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1533 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
1534 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1535 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1536 }
1537 }
1538
1539 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1540 {
1541 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1542 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1543 unsigned nr_cbufs = state->nr_cbufs;
1544 unsigned i, tl, br;
1545 struct r600_texture *tex = NULL;
1546 struct r600_surface *cb = NULL;
1547
1548 /* XXX support more colorbuffers once we need them */
1549 assert(nr_cbufs <= 8);
1550 if (nr_cbufs > 8)
1551 nr_cbufs = 8;
1552
1553 /* Colorbuffers. */
1554 for (i = 0; i < nr_cbufs; i++) {
1555 unsigned reloc, cmask_reloc;
1556
1557 cb = (struct r600_surface*)state->cbufs[i];
1558 if (!cb) {
1559 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1560 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1561 continue;
1562 }
1563
1564 tex = (struct r600_texture *)cb->base.texture;
1565 reloc = radeon_add_to_buffer_list(&rctx->b,
1566 &rctx->b.gfx,
1567 (struct r600_resource*)cb->base.texture,
1568 RADEON_USAGE_READWRITE,
1569 tex->surface.nsamples > 1 ?
1570 RADEON_PRIO_COLOR_BUFFER_MSAA :
1571 RADEON_PRIO_COLOR_BUFFER);
1572
1573 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1574 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1575 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1576 RADEON_PRIO_CMASK);
1577 } else {
1578 cmask_reloc = reloc;
1579 }
1580
1581 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1582 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1583 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1584 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1585 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1586 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1587 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1588 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1589 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1590 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1591 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1592 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1593 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1594 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1595
1596 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1597 radeon_emit(cs, reloc);
1598
1599 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1600 radeon_emit(cs, reloc);
1601
1602 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1603 radeon_emit(cs, cmask_reloc);
1604
1605 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1606 radeon_emit(cs, reloc);
1607 }
1608 /* set CB_COLOR1_INFO for possible dual-src blending */
1609 if (i == 1 && state->cbufs[0]) {
1610 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1611 cb->cb_color_info | tex->cb_color_info);
1612 i++;
1613 }
1614 for (; i < 8 ; i++)
1615 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1616 for (; i < 12; i++)
1617 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1618
1619 /* ZS buffer. */
1620 if (state->zsbuf) {
1621 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1622 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1623 &rctx->b.gfx,
1624 (struct r600_resource*)state->zsbuf->texture,
1625 RADEON_USAGE_READWRITE,
1626 zb->base.texture->nr_samples > 1 ?
1627 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1628 RADEON_PRIO_DEPTH_BUFFER);
1629
1630 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1631 zb->pa_su_poly_offset_db_fmt_cntl);
1632 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1633
1634 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1635 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1636 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1637 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1638 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1639 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1640 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1641 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1642 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1643
1644 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1645 radeon_emit(cs, reloc);
1646
1647 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1648 radeon_emit(cs, reloc);
1649
1650 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1651 radeon_emit(cs, reloc);
1652
1653 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1654 radeon_emit(cs, reloc);
1655 } else if (rctx->screen->b.info.drm_minor >= 18) {
1656 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1657 * Older kernels are out of luck. */
1658 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1659 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1660 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1661 }
1662
1663 /* Framebuffer dimensions. */
1664 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1665
1666 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1667 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1668 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1669
1670 if (rctx->b.chip_class == EVERGREEN) {
1671 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1672 } else {
1673 unsigned sc_mode_cntl_1 =
1674 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1675 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1676
1677 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1678 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples,
1679 rctx->ps_iter_samples, 0, sc_mode_cntl_1);
1680 }
1681 }
1682
1683 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1684 {
1685 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1686 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1687 float offset_units = state->offset_units;
1688 float offset_scale = state->offset_scale;
1689
1690 switch (state->zs_format) {
1691 case PIPE_FORMAT_Z24X8_UNORM:
1692 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1693 case PIPE_FORMAT_X8Z24_UNORM:
1694 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1695 offset_units *= 2.0f;
1696 break;
1697 case PIPE_FORMAT_Z16_UNORM:
1698 offset_units *= 4.0f;
1699 break;
1700 default:;
1701 }
1702
1703 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1704 radeon_emit(cs, fui(offset_scale));
1705 radeon_emit(cs, fui(offset_units));
1706 radeon_emit(cs, fui(offset_scale));
1707 radeon_emit(cs, fui(offset_units));
1708 }
1709
1710 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1711 {
1712 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1713 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1714 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1715 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1716
1717 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1718 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1719 /* This must match the used export instructions exactly.
1720 * Other values may lead to undefined behavior and hangs.
1721 */
1722 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
1723 }
1724
1725 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1726 {
1727 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1728 struct r600_db_state *a = (struct r600_db_state*)atom;
1729
1730 if (a->rsurf && a->rsurf->db_htile_surface) {
1731 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1732 unsigned reloc_idx;
1733
1734 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1735 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1736 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
1737 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1738 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1739 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1740 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1741 radeon_emit(cs, reloc_idx);
1742 } else {
1743 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
1744 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
1745 }
1746 }
1747
1748 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1749 {
1750 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1751 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1752 unsigned db_render_control = 0;
1753 unsigned db_count_control = 0;
1754 unsigned db_render_override =
1755 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1756 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1757
1758 if (rctx->b.num_occlusion_queries > 0 &&
1759 !a->occlusion_queries_disabled) {
1760 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1761 if (rctx->b.chip_class == CAYMAN) {
1762 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1763 }
1764 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1765 } else {
1766 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
1767 }
1768
1769 /* This is to fix a lockup when hyperz and alpha test are enabled at
1770 * the same time somehow GPU get confuse on which order to pick for
1771 * z test
1772 */
1773 if (rctx->alphatest_state.sx_alpha_test_control)
1774 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
1775
1776 if (a->flush_depthstencil_through_cb) {
1777 assert(a->copy_depth || a->copy_stencil);
1778
1779 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1780 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1781 S_028000_COPY_CENTROID(1) |
1782 S_028000_COPY_SAMPLE(a->copy_sample);
1783 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1784 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1785 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1786 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1787 }
1788 if (a->htile_clear) {
1789 /* FIXME we might want to disable cliprect here */
1790 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
1791 }
1792
1793 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1794 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1795 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1796 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1797 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1798 }
1799
1800 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1801 struct r600_vertexbuf_state *state,
1802 unsigned resource_offset,
1803 unsigned pkt_flags)
1804 {
1805 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1806 uint32_t dirty_mask = state->dirty_mask;
1807
1808 while (dirty_mask) {
1809 struct pipe_vertex_buffer *vb;
1810 struct r600_resource *rbuffer;
1811 uint64_t va;
1812 unsigned buffer_index = u_bit_scan(&dirty_mask);
1813
1814 vb = &state->vb[buffer_index];
1815 rbuffer = (struct r600_resource*)vb->buffer;
1816 assert(rbuffer);
1817
1818 va = rbuffer->gpu_address + vb->buffer_offset;
1819
1820 /* fetch resources start at index 992 */
1821 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1822 radeon_emit(cs, (resource_offset + buffer_index) * 8);
1823 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1824 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1825 radeon_emit(cs, /* RESOURCEi_WORD2 */
1826 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1827 S_030008_STRIDE(vb->stride) |
1828 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1829 radeon_emit(cs, /* RESOURCEi_WORD3 */
1830 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1831 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1832 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1833 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1834 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1835 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1836 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1837 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1838
1839 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1840 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1841 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1842 }
1843 state->dirty_mask = 0;
1844 }
1845
1846 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1847 {
1848 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
1849 }
1850
1851 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1852 {
1853 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
1854 RADEON_CP_PACKET3_COMPUTE_MODE);
1855 }
1856
1857 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1858 struct r600_constbuf_state *state,
1859 unsigned buffer_id_base,
1860 unsigned reg_alu_constbuf_size,
1861 unsigned reg_alu_const_cache,
1862 unsigned pkt_flags)
1863 {
1864 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1865 uint32_t dirty_mask = state->dirty_mask;
1866
1867 while (dirty_mask) {
1868 struct pipe_constant_buffer *cb;
1869 struct r600_resource *rbuffer;
1870 uint64_t va;
1871 unsigned buffer_index = ffs(dirty_mask) - 1;
1872 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1873
1874 cb = &state->cb[buffer_index];
1875 rbuffer = (struct r600_resource*)cb->buffer;
1876 assert(rbuffer);
1877
1878 va = rbuffer->gpu_address + cb->buffer_offset;
1879
1880 if (!gs_ring_buffer) {
1881 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
1882 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
1883 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
1884 pkt_flags);
1885 }
1886
1887 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1888 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1889 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1890
1891 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1892 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
1893 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1894 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1895 radeon_emit(cs, /* RESOURCEi_WORD2 */
1896 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1897 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
1898 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
1899 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
1900 radeon_emit(cs, /* RESOURCEi_WORD3 */
1901 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
1902 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1903 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1904 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1905 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1906 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1907 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1908 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1909 radeon_emit(cs, /* RESOURCEi_WORD7 */
1910 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
1911
1912 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1913 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1914 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1915
1916 dirty_mask &= ~(1 << buffer_index);
1917 }
1918 state->dirty_mask = 0;
1919 }
1920
1921 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
1922 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1923 {
1924 if (rctx->vs_shader->current->shader.vs_as_ls) {
1925 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1926 EG_FETCH_CONSTANTS_OFFSET_LS,
1927 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
1928 R_028F40_ALU_CONST_CACHE_LS_0,
1929 0 /* PKT3 flags */);
1930 } else {
1931 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1932 EG_FETCH_CONSTANTS_OFFSET_VS,
1933 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1934 R_028980_ALU_CONST_CACHE_VS_0,
1935 0 /* PKT3 flags */);
1936 }
1937 }
1938
1939 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1940 {
1941 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1942 EG_FETCH_CONSTANTS_OFFSET_GS,
1943 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1944 R_0289C0_ALU_CONST_CACHE_GS_0,
1945 0 /* PKT3 flags */);
1946 }
1947
1948 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1949 {
1950 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1951 EG_FETCH_CONSTANTS_OFFSET_PS,
1952 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1953 R_028940_ALU_CONST_CACHE_PS_0,
1954 0 /* PKT3 flags */);
1955 }
1956
1957 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1958 {
1959 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
1960 EG_FETCH_CONSTANTS_OFFSET_CS,
1961 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
1962 R_028F40_ALU_CONST_CACHE_LS_0,
1963 RADEON_CP_PACKET3_COMPUTE_MODE);
1964 }
1965
1966 /* tes constants can be emitted to VS or ES - which are common */
1967 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1968 {
1969 if (!rctx->tes_shader)
1970 return;
1971 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
1972 EG_FETCH_CONSTANTS_OFFSET_VS,
1973 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1974 R_028980_ALU_CONST_CACHE_VS_0,
1975 0);
1976 }
1977
1978 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1979 {
1980 if (!rctx->tes_shader)
1981 return;
1982 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
1983 EG_FETCH_CONSTANTS_OFFSET_HS,
1984 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
1985 R_028F00_ALU_CONST_CACHE_HS_0,
1986 0);
1987 }
1988
1989 static void evergreen_emit_sampler_views(struct r600_context *rctx,
1990 struct r600_samplerview_state *state,
1991 unsigned resource_id_base, unsigned pkt_flags)
1992 {
1993 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1994 uint32_t dirty_mask = state->dirty_mask;
1995
1996 while (dirty_mask) {
1997 struct r600_pipe_sampler_view *rview;
1998 unsigned resource_index = u_bit_scan(&dirty_mask);
1999 unsigned reloc;
2000
2001 rview = state->views[resource_index];
2002 assert(rview);
2003
2004 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2005 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2006 radeon_emit_array(cs, rview->tex_resource_words, 8);
2007
2008 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2009 RADEON_USAGE_READ,
2010 r600_get_sampler_view_priority(rview->tex_resource));
2011 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2012 radeon_emit(cs, reloc);
2013
2014 if (!rview->skip_mip_address_reloc) {
2015 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2016 radeon_emit(cs, reloc);
2017 }
2018 }
2019 state->dirty_mask = 0;
2020 }
2021
2022 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2023 {
2024 if (rctx->vs_shader->current->shader.vs_as_ls) {
2025 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2026 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2027 } else {
2028 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2029 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2030 }
2031 }
2032
2033 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2034 {
2035 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2036 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2037 }
2038
2039 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2040 {
2041 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2042 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2043 }
2044
2045 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2046 {
2047 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2048 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2049 }
2050
2051 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2052 {
2053 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2054 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2055 }
2056
2057 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2058 {
2059 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2060 EG_FETCH_CONSTANTS_OFFSET_CS + 2, RADEON_CP_PACKET3_COMPUTE_MODE);
2061 }
2062
2063 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2064 struct r600_textures_info *texinfo,
2065 unsigned resource_id_base,
2066 unsigned border_index_reg,
2067 unsigned pkt_flags)
2068 {
2069 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2070 uint32_t dirty_mask = texinfo->states.dirty_mask;
2071
2072 while (dirty_mask) {
2073 struct r600_pipe_sampler_state *rstate;
2074 unsigned i = u_bit_scan(&dirty_mask);
2075
2076 rstate = texinfo->states.states[i];
2077 assert(rstate);
2078
2079 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2080 radeon_emit(cs, (resource_id_base + i) * 3);
2081 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2082
2083 if (rstate->border_color_use) {
2084 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2085 radeon_emit(cs, i);
2086 radeon_emit_array(cs, rstate->border_color.ui, 4);
2087 }
2088 }
2089 texinfo->states.dirty_mask = 0;
2090 }
2091
2092 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2093 {
2094 if (rctx->vs_shader->current->shader.vs_as_ls) {
2095 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2096 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2097 } else {
2098 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2099 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2100 }
2101 }
2102
2103 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2104 {
2105 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2106 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2107 }
2108
2109 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2110 {
2111 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2112 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2113 }
2114
2115 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2116 {
2117 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2118 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2119 }
2120
2121 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2122 {
2123 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2124 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2125 }
2126
2127 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2128 {
2129 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2130 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2131 RADEON_CP_PACKET3_COMPUTE_MODE);
2132 }
2133
2134 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2135 {
2136 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2137 uint8_t mask = s->sample_mask;
2138
2139 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2140 mask | (mask << 8) | (mask << 16) | (mask << 24));
2141 }
2142
2143 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2144 {
2145 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2146 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2147 uint16_t mask = s->sample_mask;
2148
2149 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2150 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2151 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2152 }
2153
2154 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2155 {
2156 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2157 struct r600_cso_state *state = (struct r600_cso_state*)a;
2158 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2159
2160 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2161 (shader->buffer->gpu_address + shader->offset) >> 8);
2162 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2163 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2164 RADEON_USAGE_READ,
2165 RADEON_PRIO_INTERNAL_SHADER));
2166 }
2167
2168 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2169 {
2170 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2171 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2172
2173 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2174
2175 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2176 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2177 primid = 1;
2178 }
2179
2180 if (state->geom_enable) {
2181 uint32_t cut_val;
2182
2183 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2184 cut_val = V_028A40_GS_CUT_128;
2185 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2186 cut_val = V_028A40_GS_CUT_256;
2187 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2188 cut_val = V_028A40_GS_CUT_512;
2189 else
2190 cut_val = V_028A40_GS_CUT_1024;
2191
2192 v = S_028B54_GS_EN(1) |
2193 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2194 if (!rctx->tes_shader)
2195 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2196
2197 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2198 S_028A40_CUT_MODE(cut_val);
2199
2200 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2201 primid = 1;
2202 }
2203
2204 if (rctx->tes_shader) {
2205 uint32_t type, partitioning, topology;
2206 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2207 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2208 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2209 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2210 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2211 switch (tes_prim_mode) {
2212 case PIPE_PRIM_LINES:
2213 type = V_028B6C_TESS_ISOLINE;
2214 break;
2215 case PIPE_PRIM_TRIANGLES:
2216 type = V_028B6C_TESS_TRIANGLE;
2217 break;
2218 case PIPE_PRIM_QUADS:
2219 type = V_028B6C_TESS_QUAD;
2220 break;
2221 default:
2222 assert(0);
2223 return;
2224 }
2225
2226 switch (tes_spacing) {
2227 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2228 partitioning = V_028B6C_PART_FRAC_ODD;
2229 break;
2230 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2231 partitioning = V_028B6C_PART_FRAC_EVEN;
2232 break;
2233 case PIPE_TESS_SPACING_EQUAL:
2234 partitioning = V_028B6C_PART_INTEGER;
2235 break;
2236 default:
2237 assert(0);
2238 return;
2239 }
2240
2241 if (tes_point_mode)
2242 topology = V_028B6C_OUTPUT_POINT;
2243 else if (tes_prim_mode == PIPE_PRIM_LINES)
2244 topology = V_028B6C_OUTPUT_LINE;
2245 else if (tes_vertex_order_cw)
2246 /* XXX follow radeonsi and invert */
2247 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2248 else
2249 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2250
2251 tf_param = S_028B6C_TYPE(type) |
2252 S_028B6C_PARTITIONING(partitioning) |
2253 S_028B6C_TOPOLOGY(topology);
2254 }
2255
2256 if (rctx->tes_shader) {
2257 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2258 S_028B54_HS_EN(1);
2259 if (!state->geom_enable)
2260 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2261 else
2262 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2263 }
2264
2265 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2266 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2267 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2268 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2269 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2270 }
2271
2272 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2273 {
2274 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2275 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2276 struct r600_resource *rbuffer;
2277
2278 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2279 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2280 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2281
2282 if (state->enable) {
2283 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2284 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2285 rbuffer->gpu_address >> 8);
2286 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2287 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2288 RADEON_USAGE_READWRITE,
2289 RADEON_PRIO_RINGS_STREAMOUT));
2290 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2291 state->esgs_ring.buffer_size >> 8);
2292
2293 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2294 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2295 rbuffer->gpu_address >> 8);
2296 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2297 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2298 RADEON_USAGE_READWRITE,
2299 RADEON_PRIO_RINGS_STREAMOUT));
2300 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2301 state->gsvs_ring.buffer_size >> 8);
2302 } else {
2303 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2304 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2305 }
2306
2307 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2308 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2309 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2310 }
2311
2312 void cayman_init_common_regs(struct r600_command_buffer *cb,
2313 enum chip_class ctx_chip_class,
2314 enum radeon_family ctx_family,
2315 int ctx_drm_minor)
2316 {
2317 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2318 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2319 /* always set the temp clauses */
2320 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2321
2322 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2323 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2324 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2325
2326 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2327
2328 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2329 r600_store_value(cb, 0);
2330 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2331
2332 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2333 }
2334
2335 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2336 {
2337 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2338 int tmp, i;
2339
2340 r600_init_command_buffer(cb, 338);
2341
2342 /* This must be first. */
2343 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2344 r600_store_value(cb, 0x80000000);
2345 r600_store_value(cb, 0x80000000);
2346
2347 /* We're setting config registers here. */
2348 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2349 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2350
2351 /* This enables pipeline stat & streamout queries.
2352 * They are only disabled by blits.
2353 */
2354 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2355 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2356
2357 cayman_init_common_regs(cb, rctx->b.chip_class,
2358 rctx->b.family, rctx->screen->b.info.drm_minor);
2359
2360 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2361 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2362
2363 /* remove LS/HS from one SIMD for hw workaround */
2364 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2365 r600_store_value(cb, 0xffffffff);
2366 r600_store_value(cb, 0xffffffff);
2367 r600_store_value(cb, 0xfffffffe);
2368
2369 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2370 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2371 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2372 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2373 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2374 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2375 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2376
2377 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2378 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2379 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2380 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2381 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2382
2383 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2384 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2385 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2386 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2387 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2388 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2389 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2390 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2391 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2392 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2393 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2394 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2395 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2396 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2397
2398 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2399
2400 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2401
2402 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2403 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2404 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2405
2406 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2407 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2408 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2409
2410 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2411
2412 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2413 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2414 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2415
2416 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2417
2418 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2419
2420 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2421
2422 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2423 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2424 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2425 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2426
2427 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2428 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2429
2430 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2431 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2432 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2433 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2434 }
2435
2436 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2437 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2438
2439 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2440 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2441 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2442
2443 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2444 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2445 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2446
2447 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2448 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2449 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2450 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2451 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2452 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2453
2454 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2455
2456 /* to avoid GPU doing any preloading of constant from random address */
2457 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2458 for (i = 0; i < 16; i++)
2459 r600_store_value(cb, 0);
2460
2461 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2462 for (i = 0; i < 16; i++)
2463 r600_store_value(cb, 0);
2464
2465 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2466 for (i = 0; i < 16; i++)
2467 r600_store_value(cb, 0);
2468
2469 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2470 for (i = 0; i < 16; i++)
2471 r600_store_value(cb, 0);
2472
2473 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2474 for (i = 0; i < 16; i++)
2475 r600_store_value(cb, 0);
2476
2477 if (rctx->screen->b.has_streamout) {
2478 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2479 }
2480
2481 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2482 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2483 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2484 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2485 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2486 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2487
2488 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2489 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2490 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2491 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2492 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2493 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2494 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2495 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2496 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2497 }
2498
2499 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2500 enum chip_class ctx_chip_class,
2501 enum radeon_family ctx_family,
2502 int ctx_drm_minor)
2503 {
2504 int ps_prio;
2505 int vs_prio;
2506 int gs_prio;
2507 int es_prio;
2508
2509 int hs_prio;
2510 int cs_prio;
2511 int ls_prio;
2512
2513 unsigned tmp;
2514
2515 ps_prio = 0;
2516 vs_prio = 1;
2517 gs_prio = 2;
2518 es_prio = 3;
2519 hs_prio = 3;
2520 ls_prio = 3;
2521 cs_prio = 0;
2522
2523 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2524 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2525 rctx->r6xx_num_clause_temp_gprs = 4;
2526 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2527 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2528 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2529 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2530
2531 tmp = 0;
2532 switch (ctx_family) {
2533 case CHIP_CEDAR:
2534 case CHIP_PALM:
2535 case CHIP_SUMO:
2536 case CHIP_SUMO2:
2537 case CHIP_CAICOS:
2538 break;
2539 default:
2540 tmp |= S_008C00_VC_ENABLE(1);
2541 break;
2542 }
2543 tmp |= S_008C00_EXPORT_SRC_C(1);
2544 tmp |= S_008C00_CS_PRIO(cs_prio);
2545 tmp |= S_008C00_LS_PRIO(ls_prio);
2546 tmp |= S_008C00_HS_PRIO(hs_prio);
2547 tmp |= S_008C00_PS_PRIO(ps_prio);
2548 tmp |= S_008C00_VS_PRIO(vs_prio);
2549 tmp |= S_008C00_GS_PRIO(gs_prio);
2550 tmp |= S_008C00_ES_PRIO(es_prio);
2551
2552 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2553 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2554
2555 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2556 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2557 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2558
2559 /* The cs checker requires this register to be set. */
2560 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2561
2562 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2563 r600_store_value(cb, 0);
2564 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2565
2566 return;
2567 }
2568
2569 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2570 {
2571 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2572 int num_ps_threads;
2573 int num_vs_threads;
2574 int num_gs_threads;
2575 int num_es_threads;
2576 int num_hs_threads;
2577 int num_ls_threads;
2578
2579 int num_ps_stack_entries;
2580 int num_vs_stack_entries;
2581 int num_gs_stack_entries;
2582 int num_es_stack_entries;
2583 int num_hs_stack_entries;
2584 int num_ls_stack_entries;
2585 enum radeon_family family;
2586 unsigned tmp, i;
2587
2588 if (rctx->b.chip_class == CAYMAN) {
2589 cayman_init_atom_start_cs(rctx);
2590 return;
2591 }
2592
2593 r600_init_command_buffer(cb, 338);
2594
2595 /* This must be first. */
2596 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2597 r600_store_value(cb, 0x80000000);
2598 r600_store_value(cb, 0x80000000);
2599
2600 /* We're setting config registers here. */
2601 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2602 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2603
2604 /* This enables pipeline stat & streamout queries.
2605 * They are only disabled by blits.
2606 */
2607 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2608 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2609
2610 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2611 rctx->b.family, rctx->screen->b.info.drm_minor);
2612
2613 family = rctx->b.family;
2614 switch (family) {
2615 case CHIP_CEDAR:
2616 default:
2617 num_ps_threads = 96;
2618 num_vs_threads = 16;
2619 num_gs_threads = 16;
2620 num_es_threads = 16;
2621 num_hs_threads = 16;
2622 num_ls_threads = 16;
2623 num_ps_stack_entries = 42;
2624 num_vs_stack_entries = 42;
2625 num_gs_stack_entries = 42;
2626 num_es_stack_entries = 42;
2627 num_hs_stack_entries = 42;
2628 num_ls_stack_entries = 42;
2629 break;
2630 case CHIP_REDWOOD:
2631 num_ps_threads = 128;
2632 num_vs_threads = 20;
2633 num_gs_threads = 20;
2634 num_es_threads = 20;
2635 num_hs_threads = 20;
2636 num_ls_threads = 20;
2637 num_ps_stack_entries = 42;
2638 num_vs_stack_entries = 42;
2639 num_gs_stack_entries = 42;
2640 num_es_stack_entries = 42;
2641 num_hs_stack_entries = 42;
2642 num_ls_stack_entries = 42;
2643 break;
2644 case CHIP_JUNIPER:
2645 num_ps_threads = 128;
2646 num_vs_threads = 20;
2647 num_gs_threads = 20;
2648 num_es_threads = 20;
2649 num_hs_threads = 20;
2650 num_ls_threads = 20;
2651 num_ps_stack_entries = 85;
2652 num_vs_stack_entries = 85;
2653 num_gs_stack_entries = 85;
2654 num_es_stack_entries = 85;
2655 num_hs_stack_entries = 85;
2656 num_ls_stack_entries = 85;
2657 break;
2658 case CHIP_CYPRESS:
2659 case CHIP_HEMLOCK:
2660 num_ps_threads = 128;
2661 num_vs_threads = 20;
2662 num_gs_threads = 20;
2663 num_es_threads = 20;
2664 num_hs_threads = 20;
2665 num_ls_threads = 20;
2666 num_ps_stack_entries = 85;
2667 num_vs_stack_entries = 85;
2668 num_gs_stack_entries = 85;
2669 num_es_stack_entries = 85;
2670 num_hs_stack_entries = 85;
2671 num_ls_stack_entries = 85;
2672 break;
2673 case CHIP_PALM:
2674 num_ps_threads = 96;
2675 num_vs_threads = 16;
2676 num_gs_threads = 16;
2677 num_es_threads = 16;
2678 num_hs_threads = 16;
2679 num_ls_threads = 16;
2680 num_ps_stack_entries = 42;
2681 num_vs_stack_entries = 42;
2682 num_gs_stack_entries = 42;
2683 num_es_stack_entries = 42;
2684 num_hs_stack_entries = 42;
2685 num_ls_stack_entries = 42;
2686 break;
2687 case CHIP_SUMO:
2688 num_ps_threads = 96;
2689 num_vs_threads = 25;
2690 num_gs_threads = 25;
2691 num_es_threads = 25;
2692 num_hs_threads = 16;
2693 num_ls_threads = 16;
2694 num_ps_stack_entries = 42;
2695 num_vs_stack_entries = 42;
2696 num_gs_stack_entries = 42;
2697 num_es_stack_entries = 42;
2698 num_hs_stack_entries = 42;
2699 num_ls_stack_entries = 42;
2700 break;
2701 case CHIP_SUMO2:
2702 num_ps_threads = 96;
2703 num_vs_threads = 25;
2704 num_gs_threads = 25;
2705 num_es_threads = 25;
2706 num_hs_threads = 16;
2707 num_ls_threads = 16;
2708 num_ps_stack_entries = 85;
2709 num_vs_stack_entries = 85;
2710 num_gs_stack_entries = 85;
2711 num_es_stack_entries = 85;
2712 num_hs_stack_entries = 85;
2713 num_ls_stack_entries = 85;
2714 break;
2715 case CHIP_BARTS:
2716 num_ps_threads = 128;
2717 num_vs_threads = 20;
2718 num_gs_threads = 20;
2719 num_es_threads = 20;
2720 num_hs_threads = 20;
2721 num_ls_threads = 20;
2722 num_ps_stack_entries = 85;
2723 num_vs_stack_entries = 85;
2724 num_gs_stack_entries = 85;
2725 num_es_stack_entries = 85;
2726 num_hs_stack_entries = 85;
2727 num_ls_stack_entries = 85;
2728 break;
2729 case CHIP_TURKS:
2730 num_ps_threads = 128;
2731 num_vs_threads = 20;
2732 num_gs_threads = 20;
2733 num_es_threads = 20;
2734 num_hs_threads = 20;
2735 num_ls_threads = 20;
2736 num_ps_stack_entries = 42;
2737 num_vs_stack_entries = 42;
2738 num_gs_stack_entries = 42;
2739 num_es_stack_entries = 42;
2740 num_hs_stack_entries = 42;
2741 num_ls_stack_entries = 42;
2742 break;
2743 case CHIP_CAICOS:
2744 num_ps_threads = 96;
2745 num_vs_threads = 10;
2746 num_gs_threads = 10;
2747 num_es_threads = 10;
2748 num_hs_threads = 10;
2749 num_ls_threads = 10;
2750 num_ps_stack_entries = 42;
2751 num_vs_stack_entries = 42;
2752 num_gs_stack_entries = 42;
2753 num_es_stack_entries = 42;
2754 num_hs_stack_entries = 42;
2755 num_ls_stack_entries = 42;
2756 break;
2757 }
2758
2759 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2760 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2761 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2762 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2763
2764 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2765 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2766
2767 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2768 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2769 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2770
2771 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2772 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2773 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2774
2775 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2776 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2777 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2778
2779 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2780 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2781 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2782
2783 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2784 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2785
2786 /* remove LS/HS from one SIMD for hw workaround */
2787 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2788 r600_store_value(cb, 0xffffffff);
2789 r600_store_value(cb, 0xffffffff);
2790 r600_store_value(cb, 0xfffffffe);
2791
2792 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2793 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2794
2795 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2796 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2797 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2798 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2799 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2800 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2801 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2802
2803 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2804 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2805 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2806 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2807 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2808
2809 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2810 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2811 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2812 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2813 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2814 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2815 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2816 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2817 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2818 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2819 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2820 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2821 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2822 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2823
2824 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2825
2826 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2827
2828 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2829 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2830 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2831
2832 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2833
2834 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2835
2836 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2837 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2838 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2839
2840 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2841 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2842 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2843 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2844 }
2845
2846 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2847 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2848
2849 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2850 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2851 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2852 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2853
2854 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2855 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2856 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2857
2858 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2859 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2860 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2861
2862 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2863 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2864 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2865 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2866 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2867 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2868 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2869
2870 /* to avoid GPU doing any preloading of constant from random address */
2871 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2872 for (i = 0; i < 16; i++)
2873 r600_store_value(cb, 0);
2874
2875 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2876 for (i = 0; i < 16; i++)
2877 r600_store_value(cb, 0);
2878
2879 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2880 for (i = 0; i < 16; i++)
2881 r600_store_value(cb, 0);
2882
2883 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2884 for (i = 0; i < 16; i++)
2885 r600_store_value(cb, 0);
2886
2887 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2888 for (i = 0; i < 16; i++)
2889 r600_store_value(cb, 0);
2890
2891 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2892
2893 if (rctx->screen->b.has_streamout) {
2894 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2895 }
2896
2897 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2898 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2899 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2900 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2901 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2902 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2903
2904 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2905 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2906 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2907
2908 if (rctx->b.family == CHIP_CAICOS) {
2909 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2910 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2911 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2912 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2913 } else {
2914 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
2915 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2916 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2917 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
2918 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
2919 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
2920 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
2921 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
2922 }
2923
2924 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2925 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2926 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2927 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2928 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2929 }
2930
2931 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2932 {
2933 struct r600_context *rctx = (struct r600_context *)ctx;
2934 struct r600_command_buffer *cb = &shader->command_buffer;
2935 struct r600_shader *rshader = &shader->shader;
2936 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
2937 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2938 int ninterp = 0;
2939 boolean have_perspective = FALSE, have_linear = FALSE;
2940 static const unsigned spi_baryc_enable_bit[6] = {
2941 S_0286E0_PERSP_SAMPLE_ENA(1),
2942 S_0286E0_PERSP_CENTER_ENA(1),
2943 S_0286E0_PERSP_CENTROID_ENA(1),
2944 S_0286E0_LINEAR_SAMPLE_ENA(1),
2945 S_0286E0_LINEAR_CENTER_ENA(1),
2946 S_0286E0_LINEAR_CENTROID_ENA(1)
2947 };
2948 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
2949 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2950 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2951 uint32_t spi_ps_input_cntl[32];
2952
2953 if (!cb->buf) {
2954 r600_init_command_buffer(cb, 64);
2955 } else {
2956 cb->num_dw = 0;
2957 }
2958
2959 for (i = 0; i < rshader->ninput; i++) {
2960 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2961 POSITION goes via GPRs from the SC so isn't counted */
2962 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2963 pos_index = i;
2964 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
2965 if (face_index == -1)
2966 face_index = i;
2967 }
2968 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2969 if (face_index == -1)
2970 face_index = i; /* lives in same register, same enable bit */
2971 }
2972 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
2973 fixed_pt_position_index = i;
2974 }
2975 else {
2976 ninterp++;
2977 int k = eg_get_interpolator_index(
2978 rshader->input[i].interpolate,
2979 rshader->input[i].interpolate_location);
2980 if (k >= 0) {
2981 spi_baryc_cntl |= spi_baryc_enable_bit[k];
2982 have_perspective |= k < 3;
2983 have_linear |= !(k < 3);
2984 }
2985 }
2986
2987 sid = rshader->input[i].spi_sid;
2988
2989 if (sid) {
2990 tmp = S_028644_SEMANTIC(sid);
2991
2992 /* D3D 9 behaviour. GL is undefined */
2993 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
2994 tmp |= S_028644_DEFAULT_VAL(3);
2995
2996 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2997 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2998 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2999 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3000 tmp |= S_028644_FLAT_SHADE(1);
3001 }
3002
3003 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3004 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3005 tmp |= S_028644_PT_SPRITE_TEX(1);
3006 }
3007
3008 spi_ps_input_cntl[num++] = tmp;
3009 }
3010 }
3011
3012 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3013 r600_store_array(cb, num, spi_ps_input_cntl);
3014
3015 for (i = 0; i < rshader->noutput; i++) {
3016 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3017 z_export = 1;
3018 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3019 stencil_export = 1;
3020 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3021 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3022 mask_export = 1;
3023 }
3024 if (rshader->uses_kill)
3025 db_shader_control |= S_02880C_KILL_ENABLE(1);
3026
3027 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3028 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3029 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3030
3031 switch (rshader->ps_conservative_z) {
3032 default: /* fall through */
3033 case TGSI_FS_DEPTH_LAYOUT_ANY:
3034 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3035 break;
3036 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3037 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3038 break;
3039 case TGSI_FS_DEPTH_LAYOUT_LESS:
3040 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3041 break;
3042 }
3043
3044 exports_ps = 0;
3045 for (i = 0; i < rshader->noutput; i++) {
3046 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3047 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3048 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3049 exports_ps |= 1;
3050 }
3051
3052 num_cout = rshader->nr_ps_color_exports;
3053
3054 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3055 if (!exports_ps) {
3056 /* always at least export 1 component per pixel */
3057 exports_ps = 2;
3058 }
3059 shader->nr_ps_color_outputs = num_cout;
3060 if (ninterp == 0) {
3061 ninterp = 1;
3062 have_perspective = TRUE;
3063 }
3064 if (!spi_baryc_cntl)
3065 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3066
3067 if (!have_perspective && !have_linear)
3068 have_perspective = TRUE;
3069
3070 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3071 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3072 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3073 spi_input_z = 0;
3074 if (pos_index != -1) {
3075 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3076 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3077 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3078 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3079 }
3080
3081 spi_ps_in_control_1 = 0;
3082 if (face_index != -1) {
3083 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3084 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3085 }
3086 if (fixed_pt_position_index != -1) {
3087 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3088 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3089 }
3090
3091 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3092 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3093 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3094
3095 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3096 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3097 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3098
3099 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3100 r600_store_value(cb, shader->bo->gpu_address >> 8);
3101 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3102 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3103 S_028844_PRIME_CACHE_ON_DRAW(1) |
3104 S_028844_STACK_SIZE(rshader->bc.nstack));
3105 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3106
3107 shader->db_shader_control = db_shader_control;
3108 shader->ps_depth_export = z_export | stencil_export | mask_export;
3109
3110 shader->sprite_coord_enable = sprite_coord_enable;
3111 if (rctx->rasterizer)
3112 shader->flatshade = rctx->rasterizer->flatshade;
3113 }
3114
3115 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3116 {
3117 struct r600_command_buffer *cb = &shader->command_buffer;
3118 struct r600_shader *rshader = &shader->shader;
3119
3120 r600_init_command_buffer(cb, 32);
3121
3122 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3123 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3124 S_028890_STACK_SIZE(rshader->bc.nstack));
3125 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3126 shader->bo->gpu_address >> 8);
3127 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3128 }
3129
3130 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3131 {
3132 struct r600_context *rctx = (struct r600_context *)ctx;
3133 struct r600_command_buffer *cb = &shader->command_buffer;
3134 struct r600_shader *rshader = &shader->shader;
3135 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3136 unsigned gsvs_itemsizes[4] = {
3137 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3138 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3139 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3140 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3141 };
3142
3143 r600_init_command_buffer(cb, 64);
3144
3145 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3146
3147
3148 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3149 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3150 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3151 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3152
3153 if (rctx->screen->b.info.drm_minor >= 35) {
3154 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3155 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3156 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3157 }
3158 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3159 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3160 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3161 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3162 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3163
3164 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3165 (rshader->ring_item_sizes[0]) >> 2);
3166
3167 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3168 gsvs_itemsizes[0] +
3169 gsvs_itemsizes[1] +
3170 gsvs_itemsizes[2] +
3171 gsvs_itemsizes[3]);
3172
3173 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3174 r600_store_value(cb, gsvs_itemsizes[0]);
3175 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3176 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3177
3178 /* FIXME calculate these values somehow ??? */
3179 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3180 r600_store_value(cb, 0x80); /* GS_PER_ES */
3181 r600_store_value(cb, 0x100); /* ES_PER_GS */
3182 r600_store_value(cb, 0x2); /* GS_PER_VS */
3183
3184 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3185 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3186 S_028878_STACK_SIZE(rshader->bc.nstack));
3187 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3188 shader->bo->gpu_address >> 8);
3189 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3190 }
3191
3192
3193 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3194 {
3195 struct r600_command_buffer *cb = &shader->command_buffer;
3196 struct r600_shader *rshader = &shader->shader;
3197 unsigned spi_vs_out_id[10] = {};
3198 unsigned i, tmp, nparams = 0;
3199
3200 for (i = 0; i < rshader->noutput; i++) {
3201 if (rshader->output[i].spi_sid) {
3202 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3203 spi_vs_out_id[nparams / 4] |= tmp;
3204 nparams++;
3205 }
3206 }
3207
3208 r600_init_command_buffer(cb, 32);
3209
3210 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3211 for (i = 0; i < 10; i++) {
3212 r600_store_value(cb, spi_vs_out_id[i]);
3213 }
3214
3215 /* Certain attributes (position, psize, etc.) don't count as params.
3216 * VS is required to export at least one param and r600_shader_from_tgsi()
3217 * takes care of adding a dummy export.
3218 */
3219 if (nparams < 1)
3220 nparams = 1;
3221
3222 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3223 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3224 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3225 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3226 S_028860_STACK_SIZE(rshader->bc.nstack));
3227 if (rshader->vs_position_window_space) {
3228 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3229 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3230 } else {
3231 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3232 S_028818_VTX_W0_FMT(1) |
3233 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3234 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3235 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3236
3237 }
3238 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3239 shader->bo->gpu_address >> 8);
3240 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3241
3242 shader->pa_cl_vs_out_cntl =
3243 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3244 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3245 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3246 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3247 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3248 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3249 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3250 }
3251
3252 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3253 {
3254 struct r600_command_buffer *cb = &shader->command_buffer;
3255 struct r600_shader *rshader = &shader->shader;
3256
3257 r600_init_command_buffer(cb, 32);
3258 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3259 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3260 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3261 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3262 shader->bo->gpu_address >> 8);
3263 }
3264
3265 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3266 {
3267 struct r600_command_buffer *cb = &shader->command_buffer;
3268 struct r600_shader *rshader = &shader->shader;
3269
3270 r600_init_command_buffer(cb, 32);
3271 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3272 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3273 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3274 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3275 shader->bo->gpu_address >> 8);
3276 }
3277 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3278 {
3279 struct pipe_blend_state blend;
3280
3281 memset(&blend, 0, sizeof(blend));
3282 blend.independent_blend_enable = true;
3283 blend.rt[0].colormask = 0xf;
3284 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3285 }
3286
3287 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3288 {
3289 struct pipe_blend_state blend;
3290 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3291 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3292
3293 memset(&blend, 0, sizeof(blend));
3294 blend.independent_blend_enable = true;
3295 blend.rt[0].colormask = 0xf;
3296 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3297 }
3298
3299 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3300 {
3301 struct pipe_blend_state blend;
3302 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3303
3304 memset(&blend, 0, sizeof(blend));
3305 blend.independent_blend_enable = true;
3306 blend.rt[0].colormask = 0xf;
3307 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3308 }
3309
3310 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3311 {
3312 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3313
3314 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3315 }
3316
3317 void evergreen_update_db_shader_control(struct r600_context * rctx)
3318 {
3319 bool dual_export;
3320 unsigned db_shader_control;
3321
3322 if (!rctx->ps_shader) {
3323 return;
3324 }
3325
3326 dual_export = rctx->framebuffer.export_16bpc &&
3327 !rctx->ps_shader->current->ps_depth_export;
3328
3329 db_shader_control = rctx->ps_shader->current->db_shader_control |
3330 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3331 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3332 V_02880C_EXPORT_DB_FULL) |
3333 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3334
3335 /* When alpha test is enabled we can't trust the hw to make the proper
3336 * decision on the order in which ztest should be run related to fragment
3337 * shader execution.
3338 *
3339 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3340 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3341 * execution and thus after alpha test so if discarded by the alpha test
3342 * the z value is not written.
3343 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3344 * get a hang unless you flush the DB in between. For now just use
3345 * LATE_Z.
3346 */
3347 if (rctx->alphatest_state.sx_alpha_test_control) {
3348 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3349 } else {
3350 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3351 }
3352
3353 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3354 rctx->db_misc_state.db_shader_control = db_shader_control;
3355 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3356 }
3357 }
3358
3359 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3360 struct pipe_resource *dst,
3361 unsigned dst_level,
3362 unsigned dst_x,
3363 unsigned dst_y,
3364 unsigned dst_z,
3365 struct pipe_resource *src,
3366 unsigned src_level,
3367 unsigned src_x,
3368 unsigned src_y,
3369 unsigned src_z,
3370 unsigned copy_height,
3371 unsigned pitch,
3372 unsigned bpp)
3373 {
3374 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3375 struct r600_texture *rsrc = (struct r600_texture*)src;
3376 struct r600_texture *rdst = (struct r600_texture*)dst;
3377 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3378 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3379 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3380 uint64_t base, addr;
3381
3382 dst_mode = rdst->surface.level[dst_level].mode;
3383 src_mode = rsrc->surface.level[src_level].mode;
3384 assert(dst_mode != src_mode);
3385
3386 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3387 if (util_format_has_depth(util_format_description(src->format)))
3388 non_disp_tiling = 1;
3389
3390 y = 0;
3391 sub_cmd = EG_DMA_COPY_TILED;
3392 lbpp = util_logbase2(bpp);
3393 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3394 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3395
3396 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
3397 /* T2L */
3398 array_mode = evergreen_array_mode(src_mode);
3399 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
3400 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3401 /* linear height must be the same as the slice tile max height, it's ok even
3402 * if the linear destination/source have smaller heigh as the size of the
3403 * dma packet will be using the copy_height which is always smaller or equal
3404 * to the linear height
3405 */
3406 height = rsrc->surface.level[src_level].npix_y;
3407 detile = 1;
3408 x = src_x;
3409 y = src_y;
3410 z = src_z;
3411 base = rsrc->surface.level[src_level].offset;
3412 addr = rdst->surface.level[dst_level].offset;
3413 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3414 addr += dst_y * pitch + dst_x * bpp;
3415 bank_h = eg_bank_wh(rsrc->surface.bankh);
3416 bank_w = eg_bank_wh(rsrc->surface.bankw);
3417 mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
3418 tile_split = eg_tile_split(rsrc->surface.tile_split);
3419 base += rsrc->resource.gpu_address;
3420 addr += rdst->resource.gpu_address;
3421 } else {
3422 /* L2T */
3423 array_mode = evergreen_array_mode(dst_mode);
3424 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
3425 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3426 /* linear height must be the same as the slice tile max height, it's ok even
3427 * if the linear destination/source have smaller heigh as the size of the
3428 * dma packet will be using the copy_height which is always smaller or equal
3429 * to the linear height
3430 */
3431 height = rdst->surface.level[dst_level].npix_y;
3432 detile = 0;
3433 x = dst_x;
3434 y = dst_y;
3435 z = dst_z;
3436 base = rdst->surface.level[dst_level].offset;
3437 addr = rsrc->surface.level[src_level].offset;
3438 addr += rsrc->surface.level[src_level].slice_size * src_z;
3439 addr += src_y * pitch + src_x * bpp;
3440 bank_h = eg_bank_wh(rdst->surface.bankh);
3441 bank_w = eg_bank_wh(rdst->surface.bankw);
3442 mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
3443 tile_split = eg_tile_split(rdst->surface.tile_split);
3444 base += rdst->resource.gpu_address;
3445 addr += rsrc->resource.gpu_address;
3446 }
3447
3448 size = (copy_height * pitch) / 4;
3449 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3450 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
3451
3452 for (i = 0; i < ncopy; i++) {
3453 cheight = copy_height;
3454 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3455 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3456 }
3457 size = (cheight * pitch) / 4;
3458 /* emit reloc before writing cs so that cs is always in consistent state */
3459 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3460 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3461 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3462 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3463 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size));
3464 radeon_emit(cs, base >> 8);
3465 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
3466 (lbpp << 24) | (bank_h << 21) |
3467 (bank_w << 18) | (mt_aspect << 16));
3468 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
3469 radeon_emit(cs, (slice_tile_max << 0));
3470 radeon_emit(cs, (x << 0) | (z << 18));
3471 radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28));
3472 radeon_emit(cs, addr & 0xfffffffc);
3473 radeon_emit(cs, (addr >> 32UL) & 0xff);
3474 copy_height -= cheight;
3475 addr += cheight * pitch;
3476 y += cheight;
3477 }
3478 r600_dma_emit_wait_idle(&rctx->b);
3479 }
3480
3481 static void evergreen_dma_copy(struct pipe_context *ctx,
3482 struct pipe_resource *dst,
3483 unsigned dst_level,
3484 unsigned dstx, unsigned dsty, unsigned dstz,
3485 struct pipe_resource *src,
3486 unsigned src_level,
3487 const struct pipe_box *src_box)
3488 {
3489 struct r600_context *rctx = (struct r600_context *)ctx;
3490 struct r600_texture *rsrc = (struct r600_texture*)src;
3491 struct r600_texture *rdst = (struct r600_texture*)dst;
3492 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3493 unsigned src_w, dst_w;
3494 unsigned src_x, src_y;
3495 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3496
3497 if (rctx->b.dma.cs == NULL) {
3498 goto fallback;
3499 }
3500
3501 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3502 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3503 return;
3504 }
3505
3506 if (src_box->depth > 1 ||
3507 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3508 dstz, rsrc, src_level, src_box))
3509 goto fallback;
3510
3511 src_x = util_format_get_nblocksx(src->format, src_box->x);
3512 dst_x = util_format_get_nblocksx(src->format, dst_x);
3513 src_y = util_format_get_nblocksy(src->format, src_box->y);
3514 dst_y = util_format_get_nblocksy(src->format, dst_y);
3515
3516 bpp = rdst->surface.bpe;
3517 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3518 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3519 src_w = rsrc->surface.level[src_level].npix_x;
3520 dst_w = rdst->surface.level[dst_level].npix_x;
3521 copy_height = src_box->height / rsrc->surface.blk_h;
3522
3523 dst_mode = rdst->surface.level[dst_level].mode;
3524 src_mode = rsrc->surface.level[src_level].mode;
3525
3526 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3527 /* FIXME evergreen can do partial blit */
3528 goto fallback;
3529 }
3530 /* the x test here are currently useless (because we don't support partial blit)
3531 * but keep them around so we don't forget about those
3532 */
3533 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3534 goto fallback;
3535 }
3536
3537 /* 128 bpp surfaces require non_disp_tiling for both
3538 * tiled and linear buffers on cayman. However, async
3539 * DMA only supports it on the tiled side. As such
3540 * the tile order is backwards after a L2T/T2L packet.
3541 */
3542 if ((rctx->b.chip_class == CAYMAN) &&
3543 (src_mode != dst_mode) &&
3544 (util_format_get_blocksize(src->format) >= 16)) {
3545 goto fallback;
3546 }
3547
3548 if (src_mode == dst_mode) {
3549 uint64_t dst_offset, src_offset;
3550 /* simple dma blit would do NOTE code here assume :
3551 * src_box.x/y == 0
3552 * dst_x/y == 0
3553 * dst_pitch == src_pitch
3554 */
3555 src_offset= rsrc->surface.level[src_level].offset;
3556 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3557 src_offset += src_y * src_pitch + src_x * bpp;
3558 dst_offset = rdst->surface.level[dst_level].offset;
3559 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3560 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3561 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3562 src_box->height * src_pitch);
3563 } else {
3564 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3565 src, src_level, src_x, src_y, src_box->z,
3566 copy_height, dst_pitch, bpp);
3567 }
3568 return;
3569
3570 fallback:
3571 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3572 src, src_level, src_box);
3573 }
3574
3575 static void evergreen_set_tess_state(struct pipe_context *ctx,
3576 const float default_outer_level[4],
3577 const float default_inner_level[2])
3578 {
3579 struct r600_context *rctx = (struct r600_context *)ctx;
3580
3581 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3582 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3583 rctx->tess_state_dirty = true;
3584 }
3585
3586 void evergreen_init_state_functions(struct r600_context *rctx)
3587 {
3588 unsigned id = 1;
3589 unsigned i;
3590 /* !!!
3591 * To avoid GPU lockup registers must be emitted in a specific order
3592 * (no kidding ...). The order below is important and have been
3593 * partially inferred from analyzing fglrx command stream.
3594 *
3595 * Don't reorder atom without carefully checking the effect (GPU lockup
3596 * or piglit regression).
3597 * !!!
3598 */
3599 if (rctx->b.chip_class == EVERGREEN) {
3600 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
3601 rctx->config_state.dyn_gpr_enabled = true;
3602 }
3603 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
3604 /* shader const */
3605 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
3606 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
3607 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
3608 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
3609 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
3610 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
3611 /* shader program */
3612 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
3613 /* sampler */
3614 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
3615 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
3616 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
3617 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
3618 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
3619 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
3620 /* resources */
3621 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
3622 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
3623 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
3624 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
3625 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
3626 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
3627 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
3628 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
3629
3630 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3631
3632 if (rctx->b.chip_class == EVERGREEN) {
3633 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
3634 } else {
3635 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
3636 }
3637 rctx->sample_mask.sample_mask = ~0;
3638
3639 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3640 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3641 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3642 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
3643 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
3644 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
3645 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
3646 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
3647 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3648 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
3649 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3650 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3651 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3652 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3653 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
3654 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3655 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3656 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3657 for (i = 0; i < EG_NUM_HW_STAGES; i++)
3658 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3659 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
3660 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
3661
3662 rctx->b.b.create_blend_state = evergreen_create_blend_state;
3663 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
3664 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
3665 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
3666 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
3667 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
3668 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
3669 rctx->b.b.set_min_samples = evergreen_set_min_samples;
3670 rctx->b.b.set_tess_state = evergreen_set_tess_state;
3671 if (rctx->b.chip_class == EVERGREEN)
3672 rctx->b.b.get_sample_position = evergreen_get_sample_position;
3673 else
3674 rctx->b.b.get_sample_position = cayman_get_sample_position;
3675 rctx->b.dma_copy = evergreen_dma_copy;
3676
3677 evergreen_init_compute_state_functions(rctx);
3678 }
3679
3680 /**
3681 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
3682 *
3683 * The information about LDS and other non-compile-time parameters is then
3684 * written to the const buffer.
3685
3686 * const buffer contains -
3687 * uint32_t input_patch_size
3688 * uint32_t input_vertex_size
3689 * uint32_t num_tcs_input_cp
3690 * uint32_t num_tcs_output_cp;
3691 * uint32_t output_patch_size
3692 * uint32_t output_vertex_size
3693 * uint32_t output_patch0_offset
3694 * uint32_t perpatch_output_offset
3695 * and the same constbuf is bound to LS/HS/VS(ES).
3696 */
3697 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
3698 {
3699 struct pipe_constant_buffer constbuf = {0};
3700 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
3701 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
3702 unsigned num_tcs_input_cp = info->vertices_per_patch;
3703 unsigned num_tcs_outputs;
3704 unsigned num_tcs_output_cp;
3705 unsigned num_tcs_patch_outputs;
3706 unsigned num_tcs_inputs;
3707 unsigned input_vertex_size, output_vertex_size;
3708 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
3709 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
3710 uint32_t values[16];
3711 unsigned num_waves;
3712 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
3713 unsigned wave_divisor = (16 * num_pipes);
3714
3715 *num_patches = 1;
3716
3717 if (!rctx->tes_shader) {
3718 rctx->lds_alloc = 0;
3719 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3720 R600_LDS_INFO_CONST_BUFFER, NULL);
3721 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3722 R600_LDS_INFO_CONST_BUFFER, NULL);
3723 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3724 R600_LDS_INFO_CONST_BUFFER, NULL);
3725 return;
3726 }
3727
3728 if (rctx->lds_alloc != 0 &&
3729 rctx->last_ls == ls &&
3730 !rctx->tess_state_dirty &&
3731 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
3732 rctx->last_tcs == tcs)
3733 return;
3734
3735 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
3736
3737 if (rctx->tcs_shader) {
3738 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
3739 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
3740 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
3741 } else {
3742 num_tcs_outputs = num_tcs_inputs;
3743 num_tcs_output_cp = num_tcs_input_cp;
3744 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
3745 }
3746
3747 /* size in bytes */
3748 input_vertex_size = num_tcs_inputs * 16;
3749 output_vertex_size = num_tcs_outputs * 16;
3750
3751 input_patch_size = num_tcs_input_cp * input_vertex_size;
3752
3753 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
3754 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3755
3756 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
3757 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
3758
3759 lds_size = output_patch0_offset + output_patch_size * *num_patches;
3760
3761 values[0] = input_patch_size;
3762 values[1] = input_vertex_size;
3763 values[2] = num_tcs_input_cp;
3764 values[3] = num_tcs_output_cp;
3765
3766 values[4] = output_patch_size;
3767 values[5] = output_vertex_size;
3768 values[6] = output_patch0_offset;
3769 values[7] = perpatch_output_offset;
3770
3771 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
3772 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
3773 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
3774
3775 rctx->lds_alloc = (lds_size | (num_waves << 14));
3776
3777 memcpy(&values[8], rctx->tess_state, 6 * sizeof(float));
3778 values[14] = 0;
3779 values[15] = 0;
3780
3781 rctx->tess_state_dirty = false;
3782 rctx->last_ls = ls;
3783 rctx->last_tcs = tcs;
3784 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
3785
3786 constbuf.user_buffer = values;
3787 constbuf.buffer_size = 16 * 4;
3788
3789 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
3790 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3791 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
3792 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3793 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
3794 R600_LDS_INFO_CONST_BUFFER, &constbuf);
3795 pipe_resource_reference(&constbuf.buffer, NULL);
3796 }
3797
3798 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
3799 const struct pipe_draw_info *info,
3800 unsigned num_patches)
3801 {
3802 unsigned num_output_cp;
3803
3804 if (!rctx->tes_shader)
3805 return 0;
3806
3807 num_output_cp = rctx->tcs_shader ?
3808 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
3809 info->vertices_per_patch;
3810
3811 return S_028B58_NUM_PATCHES(num_patches) |
3812 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
3813 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
3814 }
3815
3816 void evergreen_set_ls_hs_config(struct r600_context *rctx,
3817 struct radeon_winsys_cs *cs,
3818 uint32_t ls_hs_config)
3819 {
3820 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
3821 }
3822
3823 void evergreen_set_lds_alloc(struct r600_context *rctx,
3824 struct radeon_winsys_cs *cs,
3825 uint32_t lds_alloc)
3826 {
3827 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
3828 }
3829
3830 /* on evergreen if you are running tessellation you need to disable dynamic
3831 GPRs to workaround a hardware bug.*/
3832 bool evergreen_adjust_gprs(struct r600_context *rctx)
3833 {
3834 unsigned num_gprs[EG_NUM_HW_STAGES];
3835 unsigned def_gprs[EG_NUM_HW_STAGES];
3836 unsigned cur_gprs[EG_NUM_HW_STAGES];
3837 unsigned new_gprs[EG_NUM_HW_STAGES];
3838 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
3839 unsigned max_gprs;
3840 unsigned i;
3841 unsigned total_gprs;
3842 unsigned tmp[3];
3843 bool rework = false, set_default = false, set_dirty = false;
3844 max_gprs = 0;
3845 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3846 def_gprs[i] = rctx->default_gprs[i];
3847 max_gprs += def_gprs[i];
3848 }
3849 max_gprs += def_num_clause_temp_gprs * 2;
3850
3851 /* if we have no TESS and dyn gpr is enabled then do nothing. */
3852 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
3853 if (rctx->config_state.dyn_gpr_enabled)
3854 return true;
3855
3856 /* transition back to dyn gpr enabled state */
3857 rctx->config_state.dyn_gpr_enabled = true;
3858 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3859 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3860 return true;
3861 }
3862
3863
3864 /* gather required shader gprs */
3865 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3866 if (rctx->hw_shader_stages[i].shader)
3867 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
3868 else
3869 num_gprs[i] = 0;
3870 }
3871
3872 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3873 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
3874 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3875 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
3876 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3877 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
3878
3879 total_gprs = 0;
3880 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3881 new_gprs[i] = num_gprs[i];
3882 total_gprs += num_gprs[i];
3883 }
3884
3885 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
3886 return false;
3887
3888 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3889 if (new_gprs[i] > cur_gprs[i]) {
3890 rework = true;
3891 break;
3892 }
3893 }
3894
3895 if (rctx->config_state.dyn_gpr_enabled) {
3896 set_dirty = true;
3897 rctx->config_state.dyn_gpr_enabled = false;
3898 }
3899
3900 if (rework) {
3901 set_default = true;
3902 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3903 if (new_gprs[i] > def_gprs[i])
3904 set_default = false;
3905 }
3906
3907 if (set_default) {
3908 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
3909 new_gprs[i] = def_gprs[i];
3910 }
3911 } else {
3912 unsigned ps_value = max_gprs;
3913
3914 ps_value -= (def_num_clause_temp_gprs * 2);
3915 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
3916 ps_value -= new_gprs[i];
3917
3918 new_gprs[R600_HW_STAGE_PS] = ps_value;
3919 }
3920
3921 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
3922 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
3923 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
3924
3925 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
3926 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
3927
3928 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
3929 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
3930
3931 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
3932 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
3933 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
3934 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
3935 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
3936 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
3937 set_dirty = true;
3938 }
3939 }
3940
3941
3942 if (set_dirty) {
3943 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
3944 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
3945 }
3946 return true;
3947 }