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r600g: implement two-sided lighting (v3)
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_blitter.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
38 #include "util/u_surface.h"
39 #include "util/u_pack_color.h"
40 #include "util/u_memory.h"
41 #include "util/u_inlines.h"
42 #include "util/u_framebuffer.h"
43 #include "pipebuffer/pb_buffer.h"
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "r600_formats.h"
50
51 static uint32_t r600_translate_blend_function(int blend_func)
52 {
53 switch (blend_func) {
54 case PIPE_BLEND_ADD:
55 return V_028780_COMB_DST_PLUS_SRC;
56 case PIPE_BLEND_SUBTRACT:
57 return V_028780_COMB_SRC_MINUS_DST;
58 case PIPE_BLEND_REVERSE_SUBTRACT:
59 return V_028780_COMB_DST_MINUS_SRC;
60 case PIPE_BLEND_MIN:
61 return V_028780_COMB_MIN_DST_SRC;
62 case PIPE_BLEND_MAX:
63 return V_028780_COMB_MAX_DST_SRC;
64 default:
65 R600_ERR("Unknown blend function %d\n", blend_func);
66 assert(0);
67 break;
68 }
69 return 0;
70 }
71
72 static uint32_t r600_translate_blend_factor(int blend_fact)
73 {
74 switch (blend_fact) {
75 case PIPE_BLENDFACTOR_ONE:
76 return V_028780_BLEND_ONE;
77 case PIPE_BLENDFACTOR_SRC_COLOR:
78 return V_028780_BLEND_SRC_COLOR;
79 case PIPE_BLENDFACTOR_SRC_ALPHA:
80 return V_028780_BLEND_SRC_ALPHA;
81 case PIPE_BLENDFACTOR_DST_ALPHA:
82 return V_028780_BLEND_DST_ALPHA;
83 case PIPE_BLENDFACTOR_DST_COLOR:
84 return V_028780_BLEND_DST_COLOR;
85 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
86 return V_028780_BLEND_SRC_ALPHA_SATURATE;
87 case PIPE_BLENDFACTOR_CONST_COLOR:
88 return V_028780_BLEND_CONST_COLOR;
89 case PIPE_BLENDFACTOR_CONST_ALPHA:
90 return V_028780_BLEND_CONST_ALPHA;
91 case PIPE_BLENDFACTOR_ZERO:
92 return V_028780_BLEND_ZERO;
93 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
94 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
95 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
96 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
97 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
98 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
99 case PIPE_BLENDFACTOR_INV_DST_COLOR:
100 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
101 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
102 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
103 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
104 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
105 case PIPE_BLENDFACTOR_SRC1_COLOR:
106 return V_028780_BLEND_SRC1_COLOR;
107 case PIPE_BLENDFACTOR_SRC1_ALPHA:
108 return V_028780_BLEND_SRC1_ALPHA;
109 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
110 return V_028780_BLEND_INV_SRC1_COLOR;
111 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
112 return V_028780_BLEND_INV_SRC1_ALPHA;
113 default:
114 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
115 assert(0);
116 break;
117 }
118 return 0;
119 }
120
121 static uint32_t r600_translate_stencil_op(int s_op)
122 {
123 switch (s_op) {
124 case PIPE_STENCIL_OP_KEEP:
125 return V_028800_STENCIL_KEEP;
126 case PIPE_STENCIL_OP_ZERO:
127 return V_028800_STENCIL_ZERO;
128 case PIPE_STENCIL_OP_REPLACE:
129 return V_028800_STENCIL_REPLACE;
130 case PIPE_STENCIL_OP_INCR:
131 return V_028800_STENCIL_INCR;
132 case PIPE_STENCIL_OP_DECR:
133 return V_028800_STENCIL_DECR;
134 case PIPE_STENCIL_OP_INCR_WRAP:
135 return V_028800_STENCIL_INCR_WRAP;
136 case PIPE_STENCIL_OP_DECR_WRAP:
137 return V_028800_STENCIL_DECR_WRAP;
138 case PIPE_STENCIL_OP_INVERT:
139 return V_028800_STENCIL_INVERT;
140 default:
141 R600_ERR("Unknown stencil op %d", s_op);
142 assert(0);
143 break;
144 }
145 return 0;
146 }
147
148 static uint32_t r600_translate_fill(uint32_t func)
149 {
150 switch(func) {
151 case PIPE_POLYGON_MODE_FILL:
152 return 2;
153 case PIPE_POLYGON_MODE_LINE:
154 return 1;
155 case PIPE_POLYGON_MODE_POINT:
156 return 0;
157 default:
158 assert(0);
159 return 0;
160 }
161 }
162
163 /* translates straight */
164 static uint32_t r600_translate_ds_func(int func)
165 {
166 return func;
167 }
168
169 static unsigned r600_tex_wrap(unsigned wrap)
170 {
171 switch (wrap) {
172 default:
173 case PIPE_TEX_WRAP_REPEAT:
174 return V_03C000_SQ_TEX_WRAP;
175 case PIPE_TEX_WRAP_CLAMP:
176 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
177 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
178 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
179 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
180 return V_03C000_SQ_TEX_CLAMP_BORDER;
181 case PIPE_TEX_WRAP_MIRROR_REPEAT:
182 return V_03C000_SQ_TEX_MIRROR;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP:
184 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
186 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
187 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
188 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
189 }
190 }
191
192 static unsigned r600_tex_filter(unsigned filter)
193 {
194 switch (filter) {
195 default:
196 case PIPE_TEX_FILTER_NEAREST:
197 return V_03C000_SQ_TEX_XY_FILTER_POINT;
198 case PIPE_TEX_FILTER_LINEAR:
199 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
200 }
201 }
202
203 static unsigned r600_tex_mipfilter(unsigned filter)
204 {
205 switch (filter) {
206 case PIPE_TEX_MIPFILTER_NEAREST:
207 return V_03C000_SQ_TEX_Z_FILTER_POINT;
208 case PIPE_TEX_MIPFILTER_LINEAR:
209 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
210 default:
211 case PIPE_TEX_MIPFILTER_NONE:
212 return V_03C000_SQ_TEX_Z_FILTER_NONE;
213 }
214 }
215
216 static unsigned r600_tex_compare(unsigned compare)
217 {
218 switch (compare) {
219 default:
220 case PIPE_FUNC_NEVER:
221 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
222 case PIPE_FUNC_LESS:
223 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
224 case PIPE_FUNC_EQUAL:
225 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
226 case PIPE_FUNC_LEQUAL:
227 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
228 case PIPE_FUNC_GREATER:
229 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
230 case PIPE_FUNC_NOTEQUAL:
231 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
232 case PIPE_FUNC_GEQUAL:
233 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
234 case PIPE_FUNC_ALWAYS:
235 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
236 }
237 }
238
239 static unsigned r600_tex_dim(unsigned dim)
240 {
241 switch (dim) {
242 default:
243 case PIPE_TEXTURE_1D:
244 return V_030000_SQ_TEX_DIM_1D;
245 case PIPE_TEXTURE_1D_ARRAY:
246 return V_030000_SQ_TEX_DIM_1D_ARRAY;
247 case PIPE_TEXTURE_2D:
248 case PIPE_TEXTURE_RECT:
249 return V_030000_SQ_TEX_DIM_2D;
250 case PIPE_TEXTURE_2D_ARRAY:
251 return V_030000_SQ_TEX_DIM_2D_ARRAY;
252 case PIPE_TEXTURE_3D:
253 return V_030000_SQ_TEX_DIM_3D;
254 case PIPE_TEXTURE_CUBE:
255 return V_030000_SQ_TEX_DIM_CUBEMAP;
256 }
257 }
258
259 static uint32_t r600_translate_dbformat(enum pipe_format format)
260 {
261 switch (format) {
262 case PIPE_FORMAT_Z16_UNORM:
263 return V_028040_Z_16;
264 case PIPE_FORMAT_Z24X8_UNORM:
265 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
266 return V_028040_Z_24;
267 case PIPE_FORMAT_Z32_FLOAT:
268 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
269 return V_028040_Z_32_FLOAT;
270 default:
271 return ~0U;
272 }
273 }
274
275 static uint32_t r600_translate_colorswap(enum pipe_format format)
276 {
277 switch (format) {
278 /* 8-bit buffers. */
279 case PIPE_FORMAT_L4A4_UNORM:
280 case PIPE_FORMAT_A4R4_UNORM:
281 return V_028C70_SWAP_ALT;
282
283 case PIPE_FORMAT_A8_UNORM:
284 case PIPE_FORMAT_A8_UINT:
285 case PIPE_FORMAT_A8_SINT:
286 case PIPE_FORMAT_R4A4_UNORM:
287 return V_028C70_SWAP_ALT_REV;
288 case PIPE_FORMAT_I8_UNORM:
289 case PIPE_FORMAT_L8_UNORM:
290 case PIPE_FORMAT_I8_UINT:
291 case PIPE_FORMAT_I8_SINT:
292 case PIPE_FORMAT_L8_UINT:
293 case PIPE_FORMAT_L8_SINT:
294 case PIPE_FORMAT_L8_SRGB:
295 case PIPE_FORMAT_R8_UNORM:
296 case PIPE_FORMAT_R8_SNORM:
297 case PIPE_FORMAT_R8_UINT:
298 case PIPE_FORMAT_R8_SINT:
299 return V_028C70_SWAP_STD;
300
301 /* 16-bit buffers. */
302 case PIPE_FORMAT_B5G6R5_UNORM:
303 return V_028C70_SWAP_STD_REV;
304
305 case PIPE_FORMAT_B5G5R5A1_UNORM:
306 case PIPE_FORMAT_B5G5R5X1_UNORM:
307 return V_028C70_SWAP_ALT;
308
309 case PIPE_FORMAT_B4G4R4A4_UNORM:
310 case PIPE_FORMAT_B4G4R4X4_UNORM:
311 return V_028C70_SWAP_ALT;
312
313 case PIPE_FORMAT_Z16_UNORM:
314 return V_028C70_SWAP_STD;
315
316 case PIPE_FORMAT_L8A8_UNORM:
317 case PIPE_FORMAT_L8A8_UINT:
318 case PIPE_FORMAT_L8A8_SINT:
319 case PIPE_FORMAT_L8A8_SRGB:
320 return V_028C70_SWAP_ALT;
321 case PIPE_FORMAT_R8G8_UNORM:
322 case PIPE_FORMAT_R8G8_UINT:
323 case PIPE_FORMAT_R8G8_SINT:
324 return V_028C70_SWAP_STD;
325
326 case PIPE_FORMAT_R16_UNORM:
327 case PIPE_FORMAT_R16_UINT:
328 case PIPE_FORMAT_R16_SINT:
329 case PIPE_FORMAT_R16_FLOAT:
330 return V_028C70_SWAP_STD;
331
332 /* 32-bit buffers. */
333 case PIPE_FORMAT_A8B8G8R8_SRGB:
334 return V_028C70_SWAP_STD_REV;
335 case PIPE_FORMAT_B8G8R8A8_SRGB:
336 return V_028C70_SWAP_ALT;
337
338 case PIPE_FORMAT_B8G8R8A8_UNORM:
339 case PIPE_FORMAT_B8G8R8X8_UNORM:
340 return V_028C70_SWAP_ALT;
341
342 case PIPE_FORMAT_A8R8G8B8_UNORM:
343 case PIPE_FORMAT_X8R8G8B8_UNORM:
344 return V_028C70_SWAP_ALT_REV;
345 case PIPE_FORMAT_R8G8B8A8_SNORM:
346 case PIPE_FORMAT_R8G8B8A8_UNORM:
347 case PIPE_FORMAT_R8G8B8A8_SSCALED:
348 case PIPE_FORMAT_R8G8B8A8_USCALED:
349 case PIPE_FORMAT_R8G8B8A8_SINT:
350 case PIPE_FORMAT_R8G8B8A8_UINT:
351 case PIPE_FORMAT_R8G8B8X8_UNORM:
352 return V_028C70_SWAP_STD;
353
354 case PIPE_FORMAT_A8B8G8R8_UNORM:
355 case PIPE_FORMAT_X8B8G8R8_UNORM:
356 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
357 return V_028C70_SWAP_STD_REV;
358
359 case PIPE_FORMAT_Z24X8_UNORM:
360 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
361 return V_028C70_SWAP_STD;
362
363 case PIPE_FORMAT_X8Z24_UNORM:
364 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
365 return V_028C70_SWAP_STD;
366
367 case PIPE_FORMAT_R10G10B10A2_UNORM:
368 case PIPE_FORMAT_R10G10B10X2_SNORM:
369 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
370 return V_028C70_SWAP_STD;
371
372 case PIPE_FORMAT_B10G10R10A2_UNORM:
373 case PIPE_FORMAT_B10G10R10A2_UINT:
374 return V_028C70_SWAP_ALT;
375
376 case PIPE_FORMAT_R11G11B10_FLOAT:
377 case PIPE_FORMAT_R32_FLOAT:
378 case PIPE_FORMAT_R32_UINT:
379 case PIPE_FORMAT_R32_SINT:
380 case PIPE_FORMAT_Z32_FLOAT:
381 case PIPE_FORMAT_R16G16_FLOAT:
382 case PIPE_FORMAT_R16G16_UNORM:
383 case PIPE_FORMAT_R16G16_UINT:
384 case PIPE_FORMAT_R16G16_SINT:
385 return V_028C70_SWAP_STD;
386
387 /* 64-bit buffers. */
388 case PIPE_FORMAT_R32G32_FLOAT:
389 case PIPE_FORMAT_R32G32_UINT:
390 case PIPE_FORMAT_R32G32_SINT:
391 case PIPE_FORMAT_R16G16B16A16_UNORM:
392 case PIPE_FORMAT_R16G16B16A16_SNORM:
393 case PIPE_FORMAT_R16G16B16A16_USCALED:
394 case PIPE_FORMAT_R16G16B16A16_SSCALED:
395 case PIPE_FORMAT_R16G16B16A16_UINT:
396 case PIPE_FORMAT_R16G16B16A16_SINT:
397 case PIPE_FORMAT_R16G16B16A16_FLOAT:
398 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
399
400 /* 128-bit buffers. */
401 case PIPE_FORMAT_R32G32B32A32_FLOAT:
402 case PIPE_FORMAT_R32G32B32A32_SNORM:
403 case PIPE_FORMAT_R32G32B32A32_UNORM:
404 case PIPE_FORMAT_R32G32B32A32_SSCALED:
405 case PIPE_FORMAT_R32G32B32A32_USCALED:
406 case PIPE_FORMAT_R32G32B32A32_SINT:
407 case PIPE_FORMAT_R32G32B32A32_UINT:
408 return V_028C70_SWAP_STD;
409 default:
410 R600_ERR("unsupported colorswap format %d\n", format);
411 return ~0U;
412 }
413 return ~0U;
414 }
415
416 static uint32_t r600_translate_colorformat(enum pipe_format format)
417 {
418 switch (format) {
419 /* 8-bit buffers. */
420 case PIPE_FORMAT_L4A4_UNORM:
421 case PIPE_FORMAT_R4A4_UNORM:
422 case PIPE_FORMAT_A4R4_UNORM:
423 return V_028C70_COLOR_4_4;
424
425 case PIPE_FORMAT_A8_UNORM:
426 case PIPE_FORMAT_A8_UINT:
427 case PIPE_FORMAT_A8_SINT:
428 case PIPE_FORMAT_I8_UNORM:
429 case PIPE_FORMAT_I8_UINT:
430 case PIPE_FORMAT_I8_SINT:
431 case PIPE_FORMAT_L8_UNORM:
432 case PIPE_FORMAT_L8_UINT:
433 case PIPE_FORMAT_L8_SINT:
434 case PIPE_FORMAT_L8_SRGB:
435 case PIPE_FORMAT_R8_UNORM:
436 case PIPE_FORMAT_R8_SNORM:
437 case PIPE_FORMAT_R8_UINT:
438 case PIPE_FORMAT_R8_SINT:
439 return V_028C70_COLOR_8;
440
441 /* 16-bit buffers. */
442 case PIPE_FORMAT_B5G6R5_UNORM:
443 return V_028C70_COLOR_5_6_5;
444
445 case PIPE_FORMAT_B5G5R5A1_UNORM:
446 case PIPE_FORMAT_B5G5R5X1_UNORM:
447 return V_028C70_COLOR_1_5_5_5;
448
449 case PIPE_FORMAT_B4G4R4A4_UNORM:
450 case PIPE_FORMAT_B4G4R4X4_UNORM:
451 return V_028C70_COLOR_4_4_4_4;
452
453 case PIPE_FORMAT_Z16_UNORM:
454 return V_028C70_COLOR_16;
455
456 case PIPE_FORMAT_L8A8_UNORM:
457 case PIPE_FORMAT_L8A8_UINT:
458 case PIPE_FORMAT_L8A8_SINT:
459 case PIPE_FORMAT_L8A8_SRGB:
460 case PIPE_FORMAT_R8G8_UNORM:
461 case PIPE_FORMAT_R8G8_UINT:
462 case PIPE_FORMAT_R8G8_SINT:
463 return V_028C70_COLOR_8_8;
464
465 case PIPE_FORMAT_R16_UNORM:
466 case PIPE_FORMAT_R16_UINT:
467 case PIPE_FORMAT_R16_SINT:
468 return V_028C70_COLOR_16;
469
470 case PIPE_FORMAT_R16_FLOAT:
471 return V_028C70_COLOR_16_FLOAT;
472
473 /* 32-bit buffers. */
474 case PIPE_FORMAT_A8B8G8R8_SRGB:
475 case PIPE_FORMAT_A8B8G8R8_UNORM:
476 case PIPE_FORMAT_A8R8G8B8_UNORM:
477 case PIPE_FORMAT_B8G8R8A8_SRGB:
478 case PIPE_FORMAT_B8G8R8A8_UNORM:
479 case PIPE_FORMAT_B8G8R8X8_UNORM:
480 case PIPE_FORMAT_R8G8B8A8_SNORM:
481 case PIPE_FORMAT_R8G8B8A8_UNORM:
482 case PIPE_FORMAT_R8G8B8X8_UNORM:
483 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
484 case PIPE_FORMAT_X8B8G8R8_UNORM:
485 case PIPE_FORMAT_X8R8G8B8_UNORM:
486 case PIPE_FORMAT_R8G8B8_UNORM:
487 case PIPE_FORMAT_R8G8B8A8_SSCALED:
488 case PIPE_FORMAT_R8G8B8A8_USCALED:
489 case PIPE_FORMAT_R8G8B8A8_SINT:
490 case PIPE_FORMAT_R8G8B8A8_UINT:
491 return V_028C70_COLOR_8_8_8_8;
492
493 case PIPE_FORMAT_R10G10B10A2_UNORM:
494 case PIPE_FORMAT_R10G10B10X2_SNORM:
495 case PIPE_FORMAT_B10G10R10A2_UNORM:
496 case PIPE_FORMAT_B10G10R10A2_UINT:
497 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
498 return V_028C70_COLOR_2_10_10_10;
499
500 case PIPE_FORMAT_Z24X8_UNORM:
501 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
502 return V_028C70_COLOR_8_24;
503
504 case PIPE_FORMAT_X8Z24_UNORM:
505 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
506 return V_028C70_COLOR_24_8;
507
508 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
509 return V_028C70_COLOR_X24_8_32_FLOAT;
510
511 case PIPE_FORMAT_R32_UINT:
512 case PIPE_FORMAT_R32_SINT:
513 return V_028C70_COLOR_32;
514
515 case PIPE_FORMAT_R32_FLOAT:
516 case PIPE_FORMAT_Z32_FLOAT:
517 return V_028C70_COLOR_32_FLOAT;
518
519 case PIPE_FORMAT_R16G16_FLOAT:
520 return V_028C70_COLOR_16_16_FLOAT;
521
522 case PIPE_FORMAT_R16G16_SSCALED:
523 case PIPE_FORMAT_R16G16_UNORM:
524 case PIPE_FORMAT_R16G16_UINT:
525 case PIPE_FORMAT_R16G16_SINT:
526 return V_028C70_COLOR_16_16;
527
528 case PIPE_FORMAT_R11G11B10_FLOAT:
529 return V_028C70_COLOR_10_11_11_FLOAT;
530
531 /* 64-bit buffers. */
532 case PIPE_FORMAT_R16G16B16_USCALED:
533 case PIPE_FORMAT_R16G16B16_SSCALED:
534 case PIPE_FORMAT_R16G16B16A16_UINT:
535 case PIPE_FORMAT_R16G16B16A16_SINT:
536 case PIPE_FORMAT_R16G16B16A16_USCALED:
537 case PIPE_FORMAT_R16G16B16A16_SSCALED:
538 case PIPE_FORMAT_R16G16B16A16_UNORM:
539 case PIPE_FORMAT_R16G16B16A16_SNORM:
540 return V_028C70_COLOR_16_16_16_16;
541
542 case PIPE_FORMAT_R16G16B16_FLOAT:
543 case PIPE_FORMAT_R16G16B16A16_FLOAT:
544 return V_028C70_COLOR_16_16_16_16_FLOAT;
545
546 case PIPE_FORMAT_R32G32_FLOAT:
547 return V_028C70_COLOR_32_32_FLOAT;
548
549 case PIPE_FORMAT_R32G32_USCALED:
550 case PIPE_FORMAT_R32G32_SSCALED:
551 case PIPE_FORMAT_R32G32_SINT:
552 case PIPE_FORMAT_R32G32_UINT:
553 return V_028C70_COLOR_32_32;
554
555 /* 96-bit buffers. */
556 case PIPE_FORMAT_R32G32B32_FLOAT:
557 return V_028C70_COLOR_32_32_32_FLOAT;
558
559 /* 128-bit buffers. */
560 case PIPE_FORMAT_R32G32B32A32_SNORM:
561 case PIPE_FORMAT_R32G32B32A32_UNORM:
562 case PIPE_FORMAT_R32G32B32A32_SSCALED:
563 case PIPE_FORMAT_R32G32B32A32_USCALED:
564 case PIPE_FORMAT_R32G32B32A32_SINT:
565 case PIPE_FORMAT_R32G32B32A32_UINT:
566 return V_028C70_COLOR_32_32_32_32;
567 case PIPE_FORMAT_R32G32B32A32_FLOAT:
568 return V_028C70_COLOR_32_32_32_32_FLOAT;
569
570 /* YUV buffers. */
571 case PIPE_FORMAT_UYVY:
572 case PIPE_FORMAT_YUYV:
573 default:
574 return ~0U; /* Unsupported. */
575 }
576 }
577
578 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
579 {
580 if (R600_BIG_ENDIAN) {
581 switch(colorformat) {
582 case V_028C70_COLOR_4_4:
583 return ENDIAN_NONE;
584
585 /* 8-bit buffers. */
586 case V_028C70_COLOR_8:
587 return ENDIAN_NONE;
588
589 /* 16-bit buffers. */
590 case V_028C70_COLOR_5_6_5:
591 case V_028C70_COLOR_1_5_5_5:
592 case V_028C70_COLOR_4_4_4_4:
593 case V_028C70_COLOR_16:
594 case V_028C70_COLOR_8_8:
595 return ENDIAN_8IN16;
596
597 /* 32-bit buffers. */
598 case V_028C70_COLOR_8_8_8_8:
599 case V_028C70_COLOR_2_10_10_10:
600 case V_028C70_COLOR_8_24:
601 case V_028C70_COLOR_24_8:
602 case V_028C70_COLOR_32_FLOAT:
603 case V_028C70_COLOR_16_16_FLOAT:
604 case V_028C70_COLOR_16_16:
605 return ENDIAN_8IN32;
606
607 /* 64-bit buffers. */
608 case V_028C70_COLOR_16_16_16_16:
609 case V_028C70_COLOR_16_16_16_16_FLOAT:
610 return ENDIAN_8IN16;
611
612 case V_028C70_COLOR_32_32_FLOAT:
613 case V_028C70_COLOR_32_32:
614 case V_028C70_COLOR_X24_8_32_FLOAT:
615 return ENDIAN_8IN32;
616
617 /* 96-bit buffers. */
618 case V_028C70_COLOR_32_32_32_FLOAT:
619 /* 128-bit buffers. */
620 case V_028C70_COLOR_32_32_32_32_FLOAT:
621 case V_028C70_COLOR_32_32_32_32:
622 return ENDIAN_8IN32;
623 default:
624 return ENDIAN_NONE; /* Unsupported. */
625 }
626 } else {
627 return ENDIAN_NONE;
628 }
629 }
630
631 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
632 {
633 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
634 }
635
636 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
637 {
638 return r600_translate_colorformat(format) != ~0U &&
639 r600_translate_colorswap(format) != ~0U;
640 }
641
642 static bool r600_is_zs_format_supported(enum pipe_format format)
643 {
644 return r600_translate_dbformat(format) != ~0U;
645 }
646
647 boolean evergreen_is_format_supported(struct pipe_screen *screen,
648 enum pipe_format format,
649 enum pipe_texture_target target,
650 unsigned sample_count,
651 unsigned usage)
652 {
653 unsigned retval = 0;
654
655 if (target >= PIPE_MAX_TEXTURE_TYPES) {
656 R600_ERR("r600: unsupported texture type %d\n", target);
657 return FALSE;
658 }
659
660 if (!util_format_is_supported(format, usage))
661 return FALSE;
662
663 /* Multisample */
664 if (sample_count > 1)
665 return FALSE;
666
667 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
668 r600_is_sampler_format_supported(screen, format)) {
669 retval |= PIPE_BIND_SAMPLER_VIEW;
670 }
671
672 if ((usage & (PIPE_BIND_RENDER_TARGET |
673 PIPE_BIND_DISPLAY_TARGET |
674 PIPE_BIND_SCANOUT |
675 PIPE_BIND_SHARED)) &&
676 r600_is_colorbuffer_format_supported(format)) {
677 retval |= usage &
678 (PIPE_BIND_RENDER_TARGET |
679 PIPE_BIND_DISPLAY_TARGET |
680 PIPE_BIND_SCANOUT |
681 PIPE_BIND_SHARED);
682 }
683
684 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
685 r600_is_zs_format_supported(format)) {
686 retval |= PIPE_BIND_DEPTH_STENCIL;
687 }
688
689 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
690 r600_is_vertex_format_supported(format)) {
691 retval |= PIPE_BIND_VERTEX_BUFFER;
692 }
693
694 if (usage & PIPE_BIND_TRANSFER_READ)
695 retval |= PIPE_BIND_TRANSFER_READ;
696 if (usage & PIPE_BIND_TRANSFER_WRITE)
697 retval |= PIPE_BIND_TRANSFER_WRITE;
698
699 return retval == usage;
700 }
701
702 static void evergreen_set_blend_color(struct pipe_context *ctx,
703 const struct pipe_blend_color *state)
704 {
705 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
706 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
707
708 if (rstate == NULL)
709 return;
710
711 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
712 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL, 0);
713 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL, 0);
714 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL, 0);
715 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL, 0);
716
717 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
718 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
719 r600_context_pipe_state_set(&rctx->ctx, rstate);
720 }
721
722 static void *evergreen_create_blend_state(struct pipe_context *ctx,
723 const struct pipe_blend_state *state)
724 {
725 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
726 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
727 struct r600_pipe_state *rstate;
728 u32 color_control, target_mask;
729 /* FIXME there is more then 8 framebuffer */
730 unsigned blend_cntl[8];
731
732 if (blend == NULL) {
733 return NULL;
734 }
735
736 rstate = &blend->rstate;
737
738 rstate->id = R600_PIPE_STATE_BLEND;
739
740 target_mask = 0;
741 color_control = S_028808_MODE(1);
742 if (state->logicop_enable) {
743 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
744 } else {
745 color_control |= (0xcc << 16);
746 }
747 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
748 if (state->independent_blend_enable) {
749 for (int i = 0; i < 8; i++) {
750 target_mask |= (state->rt[i].colormask << (4 * i));
751 }
752 } else {
753 for (int i = 0; i < 8; i++) {
754 target_mask |= (state->rt[0].colormask << (4 * i));
755 }
756 }
757 blend->cb_target_mask = target_mask;
758
759 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
760 color_control, 0xFFFFFFFD, NULL, 0);
761
762 if (rctx->chip_class != CAYMAN)
763 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
764 else {
765 r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
766 r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
767 }
768
769 for (int i = 0; i < 8; i++) {
770 /* state->rt entries > 0 only written if independent blending */
771 const int j = state->independent_blend_enable ? i : 0;
772
773 unsigned eqRGB = state->rt[j].rgb_func;
774 unsigned srcRGB = state->rt[j].rgb_src_factor;
775 unsigned dstRGB = state->rt[j].rgb_dst_factor;
776 unsigned eqA = state->rt[j].alpha_func;
777 unsigned srcA = state->rt[j].alpha_src_factor;
778 unsigned dstA = state->rt[j].alpha_dst_factor;
779
780 blend_cntl[i] = 0;
781 if (!state->rt[j].blend_enable)
782 continue;
783
784 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
785 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
786 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
787 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
788
789 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
790 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
791 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
792 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
793 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
794 }
795 }
796 for (int i = 0; i < 8; i++) {
797 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL, 0);
798 }
799
800 return rstate;
801 }
802
803 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
804 const struct pipe_depth_stencil_alpha_state *state)
805 {
806 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
807 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
808 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
809 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
810 struct r600_pipe_state *rstate;
811
812 if (dsa == NULL) {
813 return NULL;
814 }
815
816 rstate = &dsa->rstate;
817
818 rstate->id = R600_PIPE_STATE_DSA;
819 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
820 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
821 stencil_ref_mask = 0;
822 stencil_ref_mask_bf = 0;
823 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
824 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
825 S_028800_ZFUNC(state->depth.func);
826
827 /* stencil */
828 if (state->stencil[0].enabled) {
829 db_depth_control |= S_028800_STENCIL_ENABLE(1);
830 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
831 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
832 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
833 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
834
835
836 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
837 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
838 if (state->stencil[1].enabled) {
839 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
840 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
841 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
842 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
843 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
844 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
845 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
846 }
847 }
848
849 /* alpha */
850 alpha_test_control = 0;
851 alpha_ref = 0;
852 if (state->alpha.enabled) {
853 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
854 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
855 alpha_ref = fui(state->alpha.ref_value);
856 }
857 dsa->alpha_ref = alpha_ref;
858
859 /* misc */
860 db_render_control = 0;
861 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
862 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
863 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
864 /* TODO db_render_override depends on query */
865 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
866 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
867 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
868 r600_pipe_state_add_reg(rstate,
869 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
870 0xFFFFFFFF & C_028430_STENCILREF, NULL, 0);
871 r600_pipe_state_add_reg(rstate,
872 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
873 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL, 0);
874 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
875 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL, 0);
876 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
877 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
878 * evergreen_pipe_shader_ps().*/
879 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL, 0);
880 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL, 0);
881 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL, 0);
882 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL, 0);
883 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL, 0);
884 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL, 0);
885 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL, 0);
886
887 return rstate;
888 }
889
890 static void *evergreen_create_rs_state(struct pipe_context *ctx,
891 const struct pipe_rasterizer_state *state)
892 {
893 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
894 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
895 struct r600_pipe_state *rstate;
896 unsigned tmp;
897 unsigned prov_vtx = 1, polygon_dual_mode;
898 unsigned clip_rule;
899
900 if (rs == NULL) {
901 return NULL;
902 }
903
904 rstate = &rs->rstate;
905 rs->clamp_vertex_color = state->clamp_vertex_color;
906 rs->clamp_fragment_color = state->clamp_fragment_color;
907 rs->flatshade = state->flatshade;
908 rs->sprite_coord_enable = state->sprite_coord_enable;
909 rs->two_side = state->light_twoside;
910
911 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
912
913 /* offset */
914 rs->offset_units = state->offset_units;
915 rs->offset_scale = state->offset_scale * 12.0f;
916
917 rstate->id = R600_PIPE_STATE_RASTERIZER;
918 if (state->flatshade_first)
919 prov_vtx = 0;
920 tmp = S_0286D4_FLAT_SHADE_ENA(state->flatshade);
921 if (state->sprite_coord_enable) {
922 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
923 S_0286D4_PNT_SPRITE_OVRD_X(2) |
924 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
925 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
926 S_0286D4_PNT_SPRITE_OVRD_W(1);
927 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
928 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
929 }
930 }
931 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL, 0);
932
933 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
934 state->fill_back != PIPE_POLYGON_MODE_FILL);
935 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
936 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
937 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
938 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
939 S_028814_FACE(!state->front_ccw) |
940 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
941 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
942 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
943 S_028814_POLY_MODE(polygon_dual_mode) |
944 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
945 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL, 0);
946 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
947 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
948 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL, 0);
949 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
950 /* point size 12.4 fixed point */
951 tmp = (unsigned)(state->point_size * 8.0);
952 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
953 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL, 0);
954
955 tmp = (unsigned)state->line_width * 8;
956 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
957
958 if (state->line_stipple_enable) {
959 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE,
960 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
961 S_028A0C_REPEAT_COUNT(state->line_stipple_factor),
962 0x9FFFFFFF, NULL, 0);
963 }
964
965 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
966 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
967 0xFFFFFFFF, NULL, 0);
968
969 if (rctx->chip_class == CAYMAN) {
970 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
971 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
972 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
973 0xFFFFFFFF, NULL, 0);
974 r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
975 r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
976 r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
977 r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
978
979
980 } else {
981 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
982
983 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
984 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
985 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
986 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
987
988 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
989 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
990 0xFFFFFFFF, NULL, 0);
991 }
992 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), 0xFFFFFFFF, NULL, 0);
993 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0);
994 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
995 S_028810_PS_UCP_MODE(3) | (state->clip_plane_enable & 63) |
996 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
997 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip), 0xFFFFFFFF, NULL, 0);
998 return rstate;
999 }
1000
1001 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
1002 const struct pipe_sampler_state *state)
1003 {
1004 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1005 union util_color uc;
1006 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
1007
1008 if (rstate == NULL) {
1009 return NULL;
1010 }
1011
1012 rstate->id = R600_PIPE_STATE_SAMPLER;
1013 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1014 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1015 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1016 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1017 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1018 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1019 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1020 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1021 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1022 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1023 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL, 0);
1024 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1025 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
1026 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
1027 0xFFFFFFFF, NULL, 0);
1028 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
1029 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
1030 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
1031 S_03C008_TYPE(1),
1032 0xFFFFFFFF, NULL, 0);
1033
1034 if (uc.ui) {
1035 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), 0xFFFFFFFF, NULL, 0);
1036 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), 0xFFFFFFFF, NULL, 0);
1037 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), 0xFFFFFFFF, NULL, 0);
1038 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), 0xFFFFFFFF, NULL, 0);
1039 }
1040 return rstate;
1041 }
1042
1043 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
1044 struct pipe_resource *texture,
1045 const struct pipe_sampler_view *state)
1046 {
1047 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1048 struct r600_pipe_resource_state *rstate;
1049 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1050 unsigned format, endian;
1051 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1052 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1053 unsigned height, depth;
1054
1055 if (view == NULL)
1056 return NULL;
1057 rstate = &view->state;
1058
1059 /* initialize base object */
1060 view->base = *state;
1061 view->base.texture = NULL;
1062 pipe_reference(NULL, &texture->reference);
1063 view->base.texture = texture;
1064 view->base.reference.count = 1;
1065 view->base.context = ctx;
1066
1067 swizzle[0] = state->swizzle_r;
1068 swizzle[1] = state->swizzle_g;
1069 swizzle[2] = state->swizzle_b;
1070 swizzle[3] = state->swizzle_a;
1071
1072 format = r600_translate_texformat(ctx->screen, state->format,
1073 swizzle,
1074 &word4, &yuv_format);
1075 if (format == ~0) {
1076 format = 0;
1077 }
1078
1079 if (tmp->depth && !tmp->is_flushing_texture) {
1080 r600_texture_depth_flush(ctx, texture, TRUE);
1081 tmp = tmp->flushed_depth_texture;
1082 }
1083
1084 endian = r600_colorformat_endian_swap(format);
1085
1086 height = texture->height0;
1087 depth = texture->depth0;
1088
1089 pitch = align(tmp->pitch_in_blocks[0] *
1090 util_format_get_blockwidth(state->format), 8);
1091 array_mode = tmp->array_mode[0];
1092 tile_type = tmp->tile_type;
1093
1094 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1095 height = 1;
1096 depth = texture->array_size;
1097 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1098 depth = texture->array_size;
1099 }
1100
1101 rstate->bo[0] = &tmp->resource;
1102 rstate->bo[1] = &tmp->resource;
1103 rstate->bo_usage[0] = RADEON_USAGE_READ;
1104 rstate->bo_usage[1] = RADEON_USAGE_READ;
1105
1106 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1107 S_030000_PITCH((pitch / 8) - 1) |
1108 S_030000_NON_DISP_TILING_ORDER(tile_type) |
1109 S_030000_TEX_WIDTH(texture->width0 - 1));
1110 rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1111 S_030004_TEX_DEPTH(depth - 1) |
1112 S_030004_ARRAY_MODE(array_mode));
1113 rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1114 rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1115 rstate->val[4] = (word4 |
1116 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1117 S_030010_ENDIAN_SWAP(endian) |
1118 S_030010_BASE_LEVEL(state->u.tex.first_level));
1119 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1120 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1121 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1122 rstate->val[6] = (S_030018_MAX_ANISO(4 /* max 16 samples */));
1123 rstate->val[7] = (S_03001C_DATA_FORMAT(format) |
1124 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE));
1125
1126 return &view->base;
1127 }
1128
1129 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1130 struct pipe_sampler_view **views)
1131 {
1132 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1133 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1134
1135 for (int i = 0; i < count; i++) {
1136 if (resource[i]) {
1137 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
1138 i + R600_MAX_CONST_BUFFERS);
1139 }
1140 }
1141 }
1142
1143 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1144 struct pipe_sampler_view **views)
1145 {
1146 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1147 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1148 int i;
1149 int has_depth = 0;
1150
1151 for (i = 0; i < count; i++) {
1152 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1153 if (resource[i]) {
1154 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1155 has_depth = 1;
1156 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
1157 i + R600_MAX_CONST_BUFFERS);
1158 } else
1159 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1160 i + R600_MAX_CONST_BUFFERS);
1161
1162 pipe_sampler_view_reference(
1163 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1164 views[i]);
1165 } else {
1166 if (resource[i]) {
1167 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1168 has_depth = 1;
1169 }
1170 }
1171 }
1172 for (i = count; i < NUM_TEX_UNITS; i++) {
1173 if (rctx->ps_samplers.views[i]) {
1174 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1175 i + R600_MAX_CONST_BUFFERS);
1176 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1177 }
1178 }
1179 rctx->have_depth_texture = has_depth;
1180 rctx->ps_samplers.n_views = count;
1181 }
1182
1183 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1184 {
1185 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1186 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1187
1188
1189 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1190 rctx->ps_samplers.n_samplers = count;
1191
1192 for (int i = 0; i < count; i++) {
1193 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
1194 }
1195 }
1196
1197 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1198 {
1199 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1200 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1201
1202 for (int i = 0; i < count; i++) {
1203 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
1204 }
1205 }
1206
1207 static void evergreen_set_clip_state(struct pipe_context *ctx,
1208 const struct pipe_clip_state *state)
1209 {
1210 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1211 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1212
1213 if (rstate == NULL)
1214 return;
1215
1216 rctx->clip = *state;
1217 rstate->id = R600_PIPE_STATE_CLIP;
1218 for (int i = 0; i < 6; i++) {
1219 r600_pipe_state_add_reg(rstate,
1220 R_0285BC_PA_CL_UCP0_X + i * 16,
1221 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL, 0);
1222 r600_pipe_state_add_reg(rstate,
1223 R_0285C0_PA_CL_UCP0_Y + i * 16,
1224 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL, 0);
1225 r600_pipe_state_add_reg(rstate,
1226 R_0285C4_PA_CL_UCP0_Z + i * 16,
1227 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL, 0);
1228 r600_pipe_state_add_reg(rstate,
1229 R_0285C8_PA_CL_UCP0_W + i * 16,
1230 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL, 0);
1231 }
1232
1233 free(rctx->states[R600_PIPE_STATE_CLIP]);
1234 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1235 r600_context_pipe_state_set(&rctx->ctx, rstate);
1236 }
1237
1238 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1239 const struct pipe_poly_stipple *state)
1240 {
1241 }
1242
1243 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1244 {
1245 }
1246
1247 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1248 const struct pipe_scissor_state *state)
1249 {
1250 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1251 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1252 u32 tl, br;
1253
1254 if (rstate == NULL)
1255 return;
1256
1257 rstate->id = R600_PIPE_STATE_SCISSOR;
1258 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1259 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1260 r600_pipe_state_add_reg(rstate,
1261 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1262 0xFFFFFFFF, NULL, 0);
1263 r600_pipe_state_add_reg(rstate,
1264 R_028214_PA_SC_CLIPRECT_0_BR, br,
1265 0xFFFFFFFF, NULL, 0);
1266 r600_pipe_state_add_reg(rstate,
1267 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1268 0xFFFFFFFF, NULL, 0);
1269 r600_pipe_state_add_reg(rstate,
1270 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1271 0xFFFFFFFF, NULL, 0);
1272 r600_pipe_state_add_reg(rstate,
1273 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1274 0xFFFFFFFF, NULL, 0);
1275 r600_pipe_state_add_reg(rstate,
1276 R_028224_PA_SC_CLIPRECT_2_BR, br,
1277 0xFFFFFFFF, NULL, 0);
1278 r600_pipe_state_add_reg(rstate,
1279 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1280 0xFFFFFFFF, NULL, 0);
1281 r600_pipe_state_add_reg(rstate,
1282 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1283 0xFFFFFFFF, NULL, 0);
1284
1285 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1286 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1287 r600_context_pipe_state_set(&rctx->ctx, rstate);
1288 }
1289
1290 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
1291 const struct pipe_stencil_ref *state)
1292 {
1293 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1294 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1295 u32 tmp;
1296
1297 if (rstate == NULL)
1298 return;
1299
1300 rctx->stencil_ref = *state;
1301 rstate->id = R600_PIPE_STATE_STENCIL_REF;
1302 tmp = S_028430_STENCILREF(state->ref_value[0]);
1303 r600_pipe_state_add_reg(rstate,
1304 R_028430_DB_STENCILREFMASK, tmp,
1305 ~C_028430_STENCILREF, NULL, 0);
1306 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1307 r600_pipe_state_add_reg(rstate,
1308 R_028434_DB_STENCILREFMASK_BF, tmp,
1309 ~C_028434_STENCILREF_BF, NULL, 0);
1310
1311 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1312 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1313 r600_context_pipe_state_set(&rctx->ctx, rstate);
1314 }
1315
1316 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1317 const struct pipe_viewport_state *state)
1318 {
1319 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1320 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1321
1322 if (rstate == NULL)
1323 return;
1324
1325 rctx->viewport = *state;
1326 rstate->id = R600_PIPE_STATE_VIEWPORT;
1327 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
1328 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1329 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL, 0);
1330 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL, 0);
1331 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL, 0);
1332 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL, 0);
1333 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL, 0);
1334 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL, 0);
1335 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL, 0);
1336
1337 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1338 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1339 r600_context_pipe_state_set(&rctx->ctx, rstate);
1340 }
1341
1342 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1343 const struct pipe_framebuffer_state *state, int cb)
1344 {
1345 struct r600_resource_texture *rtex;
1346 struct r600_surface *surf;
1347 unsigned level = state->cbufs[cb]->u.tex.level;
1348 unsigned pitch, slice;
1349 unsigned color_info;
1350 unsigned format, swap, ntype, endian;
1351 uint64_t offset;
1352 unsigned tile_type;
1353 const struct util_format_description *desc;
1354 int i;
1355 unsigned blend_clamp = 0, blend_bypass = 0;
1356
1357 surf = (struct r600_surface *)state->cbufs[cb];
1358 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1359
1360 if (rtex->depth)
1361 rctx->have_depth_fb = TRUE;
1362
1363 if (rtex->depth && !rtex->is_flushing_texture) {
1364 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1365 rtex = rtex->flushed_depth_texture;
1366 }
1367
1368 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1369 offset = r600_texture_get_offset(rtex,
1370 level, state->cbufs[cb]->u.tex.first_layer);
1371 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1372 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1373 desc = util_format_description(surf->base.format);
1374 for (i = 0; i < 4; i++) {
1375 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1376 break;
1377 }
1378 }
1379
1380 ntype = V_028C70_NUMBER_UNORM;
1381 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1382 ntype = V_028C70_NUMBER_SRGB;
1383 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1384 if (desc->channel[i].normalized)
1385 ntype = V_028C70_NUMBER_SNORM;
1386 else if (desc->channel[i].pure_integer)
1387 ntype = V_028C70_NUMBER_SINT;
1388 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1389 if (desc->channel[i].normalized)
1390 ntype = V_028C70_NUMBER_UNORM;
1391 else if (desc->channel[i].pure_integer)
1392 ntype = V_028C70_NUMBER_UINT;
1393 }
1394
1395 format = r600_translate_colorformat(surf->base.format);
1396 swap = r600_translate_colorswap(surf->base.format);
1397 if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1398 endian = ENDIAN_NONE;
1399 } else {
1400 endian = r600_colorformat_endian_swap(format);
1401 }
1402
1403 /* blend clamp should be set for all NORM/SRGB types */
1404 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1405 ntype == V_028C70_NUMBER_SRGB)
1406 blend_clamp = 1;
1407
1408 /* set blend bypass according to docs if SINT/UINT or
1409 8/24 COLOR variants */
1410 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1411 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1412 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1413 blend_clamp = 0;
1414 blend_bypass = 1;
1415 }
1416
1417 color_info = S_028C70_FORMAT(format) |
1418 S_028C70_COMP_SWAP(swap) |
1419 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
1420 S_028C70_BLEND_CLAMP(blend_clamp) |
1421 S_028C70_BLEND_BYPASS(blend_bypass) |
1422 S_028C70_NUMBER_TYPE(ntype) |
1423 S_028C70_ENDIAN(endian);
1424
1425 /* EXPORT_NORM is an optimzation that can be enabled for better
1426 * performance in certain cases.
1427 * EXPORT_NORM can be enabled if:
1428 * - 11-bit or smaller UNORM/SNORM/SRGB
1429 * - 16-bit or smaller FLOAT
1430 */
1431 /* FIXME: This should probably be the same for all CBs if we want
1432 * useful alpha tests. */
1433 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1434 ((desc->channel[i].size < 12 &&
1435 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1436 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1437 (desc->channel[i].size < 17 &&
1438 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1439 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1440 rctx->export_16bpc = true;
1441 } else {
1442 rctx->export_16bpc = false;
1443 }
1444 rctx->alpha_ref_dirty = true;
1445
1446 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1447 tile_type = rtex->tile_type;
1448 } else /* workaround for linear buffers */
1449 tile_type = 1;
1450
1451 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1452 offset >>= 8;
1453
1454 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1455 r600_pipe_state_add_reg(rstate,
1456 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1457 offset, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1458 r600_pipe_state_add_reg(rstate,
1459 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1460 0x0, 0xFFFFFFFF, NULL, 0);
1461 r600_pipe_state_add_reg(rstate,
1462 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1463 color_info, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1464 r600_pipe_state_add_reg(rstate,
1465 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1466 S_028C64_PITCH_TILE_MAX(pitch),
1467 0xFFFFFFFF, NULL, 0);
1468 r600_pipe_state_add_reg(rstate,
1469 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1470 S_028C68_SLICE_TILE_MAX(slice),
1471 0xFFFFFFFF, NULL, 0);
1472 r600_pipe_state_add_reg(rstate,
1473 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1474 0x00000000, 0xFFFFFFFF, NULL, 0);
1475 r600_pipe_state_add_reg(rstate,
1476 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1477 S_028C74_NON_DISP_TILING_ORDER(tile_type),
1478 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1479 }
1480
1481 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1482 const struct pipe_framebuffer_state *state)
1483 {
1484 struct r600_resource_texture *rtex;
1485 struct r600_surface *surf;
1486 unsigned level, first_layer, pitch, slice, format, array_mode;
1487 uint64_t offset;
1488
1489 if (state->zsbuf == NULL)
1490 return;
1491
1492 surf = (struct r600_surface *)state->zsbuf;
1493 level = surf->base.u.tex.level;
1494 rtex = (struct r600_resource_texture*)surf->base.texture;
1495
1496 /* XXX remove this once tiling is properly supported */
1497 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1498 V_028C70_ARRAY_1D_TILED_THIN1;
1499
1500 first_layer = surf->base.u.tex.first_layer;
1501 offset = r600_texture_get_offset(rtex, level, first_layer);
1502 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1503 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1504 format = r600_translate_dbformat(rtex->real_format);
1505
1506 offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1507 offset >>= 8;
1508
1509 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1510 offset, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1511 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1512 offset, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1513 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0);
1514
1515 if (rtex->stencil) {
1516 uint64_t stencil_offset =
1517 r600_texture_get_offset(rtex->stencil, level, first_layer);
1518
1519 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1520 stencil_offset >>= 8;
1521
1522 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1523 stencil_offset, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1524 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1525 stencil_offset, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1526 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1527 1, 0xFFFFFFFF, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1528 } else {
1529 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1530 0, 0xFFFFFFFF, NULL, RADEON_USAGE_READWRITE);
1531 }
1532
1533 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
1534 S_028040_ARRAY_MODE(array_mode) | S_028040_FORMAT(format),
1535 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1536 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1537 S_028058_PITCH_TILE_MAX(pitch),
1538 0xFFFFFFFF, NULL, 0);
1539 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1540 S_02805C_SLICE_TILE_MAX(slice),
1541 0xFFFFFFFF, NULL, 0);
1542 }
1543
1544 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1545 const struct pipe_framebuffer_state *state)
1546 {
1547 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1548 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1549 u32 shader_mask, tl, br, target_mask;
1550 int tl_x, tl_y, br_x, br_y;
1551
1552 if (rstate == NULL)
1553 return;
1554
1555 evergreen_context_flush_dest_caches(&rctx->ctx);
1556 rctx->ctx.num_dest_buffers = state->nr_cbufs;
1557
1558 /* unreference old buffer and reference new one */
1559 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1560
1561 util_copy_framebuffer_state(&rctx->framebuffer, state);
1562
1563 /* build states */
1564 rctx->have_depth_fb = 0;
1565 rctx->nr_cbufs = state->nr_cbufs;
1566 for (int i = 0; i < state->nr_cbufs; i++) {
1567 evergreen_cb(rctx, rstate, state, i);
1568 }
1569 if (state->zsbuf) {
1570 evergreen_db(rctx, rstate, state);
1571 rctx->ctx.num_dest_buffers++;
1572 }
1573
1574 target_mask = 0x00000000;
1575 target_mask = 0xFFFFFFFF;
1576 shader_mask = 0;
1577 for (int i = 0; i < state->nr_cbufs; i++) {
1578 target_mask ^= 0xf << (i * 4);
1579 shader_mask |= 0xf << (i * 4);
1580 }
1581 tl_x = 0;
1582 tl_y = 0;
1583 br_x = state->width;
1584 br_y = state->height;
1585 /* EG hw workaround */
1586 if (br_x == 0)
1587 tl_x = 1;
1588 if (br_y == 0)
1589 tl_y = 1;
1590 /* cayman hw workaround */
1591 if (rctx->chip_class == CAYMAN) {
1592 if (br_x == 1 && br_y == 1)
1593 br_x = 2;
1594 }
1595 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1596 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1597
1598 r600_pipe_state_add_reg(rstate,
1599 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1600 0xFFFFFFFF, NULL, 0);
1601 r600_pipe_state_add_reg(rstate,
1602 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1603 0xFFFFFFFF, NULL, 0);
1604 r600_pipe_state_add_reg(rstate,
1605 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1606 0xFFFFFFFF, NULL, 0);
1607 r600_pipe_state_add_reg(rstate,
1608 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1609 0xFFFFFFFF, NULL, 0);
1610 r600_pipe_state_add_reg(rstate,
1611 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1612 0xFFFFFFFF, NULL, 0);
1613 r600_pipe_state_add_reg(rstate,
1614 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1615 0xFFFFFFFF, NULL, 0);
1616 r600_pipe_state_add_reg(rstate,
1617 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1618 0xFFFFFFFF, NULL, 0);
1619 r600_pipe_state_add_reg(rstate,
1620 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1621 0xFFFFFFFF, NULL, 0);
1622 r600_pipe_state_add_reg(rstate,
1623 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1624 0xFFFFFFFF, NULL, 0);
1625 r600_pipe_state_add_reg(rstate,
1626 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1627 0xFFFFFFFF, NULL, 0);
1628
1629 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1630 0x00000000, target_mask, NULL, 0);
1631 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1632 shader_mask, 0xFFFFFFFF, NULL, 0);
1633
1634
1635 if (rctx->chip_class == CAYMAN) {
1636 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1637 0x00000000, 0xFFFFFFFF, NULL, 0);
1638 } else {
1639 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1640 0x00000000, 0xFFFFFFFF, NULL, 0);
1641 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1642 0x00000000, 0xFFFFFFFF, NULL, 0);
1643 }
1644
1645 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1646 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1647 r600_context_pipe_state_set(&rctx->ctx, rstate);
1648
1649 if (state->zsbuf) {
1650 evergreen_polygon_offset_update(rctx);
1651 }
1652 }
1653
1654 static void evergreen_texture_barrier(struct pipe_context *ctx)
1655 {
1656 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1657
1658 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1659 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1660 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1661 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1662 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
1663 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
1664 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
1665 }
1666
1667 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
1668 {
1669 rctx->context.create_blend_state = evergreen_create_blend_state;
1670 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1671 rctx->context.create_fs_state = r600_create_shader_state;
1672 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1673 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1674 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1675 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1676 rctx->context.create_vs_state = r600_create_shader_state;
1677 rctx->context.bind_blend_state = r600_bind_blend_state;
1678 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1679 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1680 rctx->context.bind_fs_state = r600_bind_ps_shader;
1681 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1682 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1683 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1684 rctx->context.bind_vs_state = r600_bind_vs_shader;
1685 rctx->context.delete_blend_state = r600_delete_state;
1686 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1687 rctx->context.delete_fs_state = r600_delete_ps_shader;
1688 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1689 rctx->context.delete_sampler_state = r600_delete_state;
1690 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1691 rctx->context.delete_vs_state = r600_delete_vs_shader;
1692 rctx->context.set_blend_color = evergreen_set_blend_color;
1693 rctx->context.set_clip_state = evergreen_set_clip_state;
1694 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1695 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1696 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1697 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1698 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1699 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1700 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1701 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1702 rctx->context.set_index_buffer = r600_set_index_buffer;
1703 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1704 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1705 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1706 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1707 rctx->context.texture_barrier = evergreen_texture_barrier;
1708 rctx->context.create_stream_output_target = r600_create_so_target;
1709 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1710 rctx->context.set_stream_output_targets = r600_set_so_targets;
1711 }
1712
1713 static void cayman_init_config(struct r600_pipe_context *rctx)
1714 {
1715 struct r600_pipe_state *rstate = &rctx->config;
1716 unsigned tmp;
1717
1718 tmp = 0x00000000;
1719 tmp |= S_008C00_EXPORT_SRC_C(1);
1720 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
1721
1722 /* always set the temp clauses */
1723 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), 0xFFFFFFFF, NULL, 0);
1724 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL, 0);
1725 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL, 0);
1726 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL, 0);
1727
1728 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL, 0);
1729
1730 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1731 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1732 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
1733 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
1734 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL, 0);
1735 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL, 0);
1736 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
1737 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
1738 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1739 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1740 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1741 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1742 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL, 0);
1743 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
1744 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
1745 r600_pipe_state_add_reg(rstate, R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), 0xFFFFFFFF, NULL, 0);
1746 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL, 0);
1747 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL, 0);
1748 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL, 0);
1749
1750 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL, 0);
1751 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL, 0);
1752 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL, 0);
1753 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL, 0);
1754 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL, 0);
1755 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL, 0);
1756 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL, 0);
1757 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL, 0);
1758 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL, 0);
1759 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL, 0);
1760 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL, 0);
1761 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL, 0);
1762 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL, 0);
1763 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL, 0);
1764 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL, 0);
1765 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL, 0);
1766 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL, 0);
1767 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL, 0);
1768 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL, 0);
1769 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL, 0);
1770 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL, 0);
1771 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL, 0);
1772 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL, 0);
1773 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL, 0);
1774 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL, 0);
1775 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL, 0);
1776 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL, 0);
1777 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL, 0);
1778 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL, 0);
1779 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL, 0);
1780 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL, 0);
1781 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL, 0);
1782
1783 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
1784
1785 r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, 0xffffffff, NULL, 0);
1786 r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, 0xffffffff, NULL, 0);
1787
1788 r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, 0xFFFFFFFF, NULL, 0);
1789 r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0xFFFFFFFF, NULL, 0);
1790
1791 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, 0xFFFFFFFF, NULL, 0);
1792 r600_context_pipe_state_set(&rctx->ctx, rstate);
1793 }
1794
1795 void evergreen_init_config(struct r600_pipe_context *rctx)
1796 {
1797 struct r600_pipe_state *rstate = &rctx->config;
1798 int ps_prio;
1799 int vs_prio;
1800 int gs_prio;
1801 int es_prio;
1802 int hs_prio, cs_prio, ls_prio;
1803 int num_ps_gprs;
1804 int num_vs_gprs;
1805 int num_gs_gprs;
1806 int num_es_gprs;
1807 int num_hs_gprs;
1808 int num_ls_gprs;
1809 int num_temp_gprs;
1810 int num_ps_threads;
1811 int num_vs_threads;
1812 int num_gs_threads;
1813 int num_es_threads;
1814 int num_hs_threads;
1815 int num_ls_threads;
1816 int num_ps_stack_entries;
1817 int num_vs_stack_entries;
1818 int num_gs_stack_entries;
1819 int num_es_stack_entries;
1820 int num_hs_stack_entries;
1821 int num_ls_stack_entries;
1822 enum radeon_family family;
1823 unsigned tmp;
1824
1825 family = rctx->family;
1826
1827 if (rctx->chip_class == CAYMAN) {
1828 cayman_init_config(rctx);
1829 return;
1830 }
1831
1832 ps_prio = 0;
1833 vs_prio = 1;
1834 gs_prio = 2;
1835 es_prio = 3;
1836 hs_prio = 0;
1837 ls_prio = 0;
1838 cs_prio = 0;
1839
1840 switch (family) {
1841 case CHIP_CEDAR:
1842 default:
1843 num_ps_gprs = 93;
1844 num_vs_gprs = 46;
1845 num_temp_gprs = 4;
1846 num_gs_gprs = 31;
1847 num_es_gprs = 31;
1848 num_hs_gprs = 23;
1849 num_ls_gprs = 23;
1850 num_ps_threads = 96;
1851 num_vs_threads = 16;
1852 num_gs_threads = 16;
1853 num_es_threads = 16;
1854 num_hs_threads = 16;
1855 num_ls_threads = 16;
1856 num_ps_stack_entries = 42;
1857 num_vs_stack_entries = 42;
1858 num_gs_stack_entries = 42;
1859 num_es_stack_entries = 42;
1860 num_hs_stack_entries = 42;
1861 num_ls_stack_entries = 42;
1862 break;
1863 case CHIP_REDWOOD:
1864 num_ps_gprs = 93;
1865 num_vs_gprs = 46;
1866 num_temp_gprs = 4;
1867 num_gs_gprs = 31;
1868 num_es_gprs = 31;
1869 num_hs_gprs = 23;
1870 num_ls_gprs = 23;
1871 num_ps_threads = 128;
1872 num_vs_threads = 20;
1873 num_gs_threads = 20;
1874 num_es_threads = 20;
1875 num_hs_threads = 20;
1876 num_ls_threads = 20;
1877 num_ps_stack_entries = 42;
1878 num_vs_stack_entries = 42;
1879 num_gs_stack_entries = 42;
1880 num_es_stack_entries = 42;
1881 num_hs_stack_entries = 42;
1882 num_ls_stack_entries = 42;
1883 break;
1884 case CHIP_JUNIPER:
1885 num_ps_gprs = 93;
1886 num_vs_gprs = 46;
1887 num_temp_gprs = 4;
1888 num_gs_gprs = 31;
1889 num_es_gprs = 31;
1890 num_hs_gprs = 23;
1891 num_ls_gprs = 23;
1892 num_ps_threads = 128;
1893 num_vs_threads = 20;
1894 num_gs_threads = 20;
1895 num_es_threads = 20;
1896 num_hs_threads = 20;
1897 num_ls_threads = 20;
1898 num_ps_stack_entries = 85;
1899 num_vs_stack_entries = 85;
1900 num_gs_stack_entries = 85;
1901 num_es_stack_entries = 85;
1902 num_hs_stack_entries = 85;
1903 num_ls_stack_entries = 85;
1904 break;
1905 case CHIP_CYPRESS:
1906 case CHIP_HEMLOCK:
1907 num_ps_gprs = 93;
1908 num_vs_gprs = 46;
1909 num_temp_gprs = 4;
1910 num_gs_gprs = 31;
1911 num_es_gprs = 31;
1912 num_hs_gprs = 23;
1913 num_ls_gprs = 23;
1914 num_ps_threads = 128;
1915 num_vs_threads = 20;
1916 num_gs_threads = 20;
1917 num_es_threads = 20;
1918 num_hs_threads = 20;
1919 num_ls_threads = 20;
1920 num_ps_stack_entries = 85;
1921 num_vs_stack_entries = 85;
1922 num_gs_stack_entries = 85;
1923 num_es_stack_entries = 85;
1924 num_hs_stack_entries = 85;
1925 num_ls_stack_entries = 85;
1926 break;
1927 case CHIP_PALM:
1928 num_ps_gprs = 93;
1929 num_vs_gprs = 46;
1930 num_temp_gprs = 4;
1931 num_gs_gprs = 31;
1932 num_es_gprs = 31;
1933 num_hs_gprs = 23;
1934 num_ls_gprs = 23;
1935 num_ps_threads = 96;
1936 num_vs_threads = 16;
1937 num_gs_threads = 16;
1938 num_es_threads = 16;
1939 num_hs_threads = 16;
1940 num_ls_threads = 16;
1941 num_ps_stack_entries = 42;
1942 num_vs_stack_entries = 42;
1943 num_gs_stack_entries = 42;
1944 num_es_stack_entries = 42;
1945 num_hs_stack_entries = 42;
1946 num_ls_stack_entries = 42;
1947 break;
1948 case CHIP_SUMO:
1949 num_ps_gprs = 93;
1950 num_vs_gprs = 46;
1951 num_temp_gprs = 4;
1952 num_gs_gprs = 31;
1953 num_es_gprs = 31;
1954 num_hs_gprs = 23;
1955 num_ls_gprs = 23;
1956 num_ps_threads = 96;
1957 num_vs_threads = 25;
1958 num_gs_threads = 25;
1959 num_es_threads = 25;
1960 num_hs_threads = 25;
1961 num_ls_threads = 25;
1962 num_ps_stack_entries = 42;
1963 num_vs_stack_entries = 42;
1964 num_gs_stack_entries = 42;
1965 num_es_stack_entries = 42;
1966 num_hs_stack_entries = 42;
1967 num_ls_stack_entries = 42;
1968 break;
1969 case CHIP_SUMO2:
1970 num_ps_gprs = 93;
1971 num_vs_gprs = 46;
1972 num_temp_gprs = 4;
1973 num_gs_gprs = 31;
1974 num_es_gprs = 31;
1975 num_hs_gprs = 23;
1976 num_ls_gprs = 23;
1977 num_ps_threads = 96;
1978 num_vs_threads = 25;
1979 num_gs_threads = 25;
1980 num_es_threads = 25;
1981 num_hs_threads = 25;
1982 num_ls_threads = 25;
1983 num_ps_stack_entries = 85;
1984 num_vs_stack_entries = 85;
1985 num_gs_stack_entries = 85;
1986 num_es_stack_entries = 85;
1987 num_hs_stack_entries = 85;
1988 num_ls_stack_entries = 85;
1989 break;
1990 case CHIP_BARTS:
1991 num_ps_gprs = 93;
1992 num_vs_gprs = 46;
1993 num_temp_gprs = 4;
1994 num_gs_gprs = 31;
1995 num_es_gprs = 31;
1996 num_hs_gprs = 23;
1997 num_ls_gprs = 23;
1998 num_ps_threads = 128;
1999 num_vs_threads = 20;
2000 num_gs_threads = 20;
2001 num_es_threads = 20;
2002 num_hs_threads = 20;
2003 num_ls_threads = 20;
2004 num_ps_stack_entries = 85;
2005 num_vs_stack_entries = 85;
2006 num_gs_stack_entries = 85;
2007 num_es_stack_entries = 85;
2008 num_hs_stack_entries = 85;
2009 num_ls_stack_entries = 85;
2010 break;
2011 case CHIP_TURKS:
2012 num_ps_gprs = 93;
2013 num_vs_gprs = 46;
2014 num_temp_gprs = 4;
2015 num_gs_gprs = 31;
2016 num_es_gprs = 31;
2017 num_hs_gprs = 23;
2018 num_ls_gprs = 23;
2019 num_ps_threads = 128;
2020 num_vs_threads = 20;
2021 num_gs_threads = 20;
2022 num_es_threads = 20;
2023 num_hs_threads = 20;
2024 num_ls_threads = 20;
2025 num_ps_stack_entries = 42;
2026 num_vs_stack_entries = 42;
2027 num_gs_stack_entries = 42;
2028 num_es_stack_entries = 42;
2029 num_hs_stack_entries = 42;
2030 num_ls_stack_entries = 42;
2031 break;
2032 case CHIP_CAICOS:
2033 num_ps_gprs = 93;
2034 num_vs_gprs = 46;
2035 num_temp_gprs = 4;
2036 num_gs_gprs = 31;
2037 num_es_gprs = 31;
2038 num_hs_gprs = 23;
2039 num_ls_gprs = 23;
2040 num_ps_threads = 128;
2041 num_vs_threads = 10;
2042 num_gs_threads = 10;
2043 num_es_threads = 10;
2044 num_hs_threads = 10;
2045 num_ls_threads = 10;
2046 num_ps_stack_entries = 42;
2047 num_vs_stack_entries = 42;
2048 num_gs_stack_entries = 42;
2049 num_es_stack_entries = 42;
2050 num_hs_stack_entries = 42;
2051 num_ls_stack_entries = 42;
2052 break;
2053 }
2054
2055 tmp = 0x00000000;
2056 switch (family) {
2057 case CHIP_CEDAR:
2058 case CHIP_PALM:
2059 case CHIP_SUMO:
2060 case CHIP_SUMO2:
2061 case CHIP_CAICOS:
2062 break;
2063 default:
2064 tmp |= S_008C00_VC_ENABLE(1);
2065 break;
2066 }
2067 tmp |= S_008C00_EXPORT_SRC_C(1);
2068 tmp |= S_008C00_CS_PRIO(cs_prio);
2069 tmp |= S_008C00_LS_PRIO(ls_prio);
2070 tmp |= S_008C00_HS_PRIO(hs_prio);
2071 tmp |= S_008C00_PS_PRIO(ps_prio);
2072 tmp |= S_008C00_VS_PRIO(vs_prio);
2073 tmp |= S_008C00_GS_PRIO(gs_prio);
2074 tmp |= S_008C00_ES_PRIO(es_prio);
2075 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
2076
2077 /* enable dynamic GPR resource management */
2078 if (rctx->screen->info.drm_minor >= 7) {
2079 /* always set temp clauses */
2080 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
2081 S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), 0xFFFFFFFF, NULL, 0);
2082 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL, 0);
2083 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL, 0);
2084 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL, 0);
2085 r600_pipe_state_add_reg(rstate, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2086 S_028838_PS_GPRS(0x1e) |
2087 S_028838_VS_GPRS(0x1e) |
2088 S_028838_GS_GPRS(0x1e) |
2089 S_028838_ES_GPRS(0x1e) |
2090 S_028838_HS_GPRS(0x1e) |
2091 S_028838_LS_GPRS(0x1e), 0xFFFFFFFF, NULL, 0); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2092 } else {
2093 tmp = 0;
2094 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2095 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2096 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2097 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2098
2099 tmp = 0;
2100 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
2101 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2102 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2103
2104 tmp = 0;
2105 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2106 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2107 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL, 0);
2108 }
2109
2110 tmp = 0;
2111 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
2112 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2113 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2114 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2115 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2116
2117 tmp = 0;
2118 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
2119 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2120 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2121
2122 tmp = 0;
2123 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2124 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2125 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
2126
2127 tmp = 0;
2128 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2129 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2130 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2131
2132 tmp = 0;
2133 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2134 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2135 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL, 0);
2136
2137 tmp = 0;
2138 tmp |= S_008E2C_NUM_PS_LDS(0x1000);
2139 tmp |= S_008E2C_NUM_LS_LDS(0x1000);
2140 r600_pipe_state_add_reg(rstate, R_008E2C_SQ_LDS_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL, 0);
2141
2142 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2143 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL, 0);
2144
2145 #if 0
2146 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL, 0);
2147
2148 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL, 0);
2149 #endif
2150 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL, 0);
2151
2152 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2153 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2154 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2155 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2156 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2157 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2158
2159 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL, 0);
2160 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL, 0);
2161 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL, 0);
2162 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL, 0);
2163
2164 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2165 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2166 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
2167 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL, 0);
2168 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL, 0);
2169 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL, 0);
2170 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
2171 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL, 0);
2172 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2173 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2174 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2175 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2176 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL, 0);
2177 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
2178 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL, 0);
2179 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL, 0);
2180 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL, 0);
2181 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL, 0);
2182
2183 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL, 0);
2184 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL, 0);
2185 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL, 0);
2186 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL, 0);
2187 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL, 0);
2188 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL, 0);
2189 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL, 0);
2190 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL, 0);
2191 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL, 0);
2192 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL, 0);
2193 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL, 0);
2194 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL, 0);
2195 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL, 0);
2196 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL, 0);
2197 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL, 0);
2198 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL, 0);
2199 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL, 0);
2200 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL, 0);
2201 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL, 0);
2202 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL, 0);
2203 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL, 0);
2204 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL, 0);
2205 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL, 0);
2206 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL, 0);
2207 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL, 0);
2208 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL, 0);
2209 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL, 0);
2210 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL, 0);
2211 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL, 0);
2212 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL, 0);
2213 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL, 0);
2214 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL, 0);
2215
2216 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL, 0);
2217
2218 r600_context_pipe_state_set(&rctx->ctx, rstate);
2219 }
2220
2221 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
2222 {
2223 struct r600_pipe_state state;
2224
2225 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2226 state.nregs = 0;
2227 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2228 float offset_units = rctx->rasterizer->offset_units;
2229 unsigned offset_db_fmt_cntl = 0, depth;
2230
2231 switch (rctx->framebuffer.zsbuf->texture->format) {
2232 case PIPE_FORMAT_Z24X8_UNORM:
2233 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2234 depth = -24;
2235 offset_units *= 2.0f;
2236 break;
2237 case PIPE_FORMAT_Z32_FLOAT:
2238 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2239 depth = -23;
2240 offset_units *= 1.0f;
2241 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2242 break;
2243 case PIPE_FORMAT_Z16_UNORM:
2244 depth = -16;
2245 offset_units *= 4.0f;
2246 break;
2247 default:
2248 return;
2249 }
2250 /* FIXME some of those reg can be computed with cso */
2251 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2252 r600_pipe_state_add_reg(&state,
2253 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2254 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
2255 r600_pipe_state_add_reg(&state,
2256 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2257 fui(offset_units), 0xFFFFFFFF, NULL, 0);
2258 r600_pipe_state_add_reg(&state,
2259 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2260 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
2261 r600_pipe_state_add_reg(&state,
2262 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2263 fui(offset_units), 0xFFFFFFFF, NULL, 0);
2264 r600_pipe_state_add_reg(&state,
2265 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2266 offset_db_fmt_cntl, 0xFFFFFFFF, NULL, 0);
2267 r600_context_pipe_state_set(&rctx->ctx, &state);
2268 }
2269 }
2270
2271 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2272 {
2273 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2274 struct r600_pipe_state *rstate = &shader->rstate;
2275 struct r600_shader *rshader = &shader->shader;
2276 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2277 int pos_index = -1, face_index = -1;
2278 int ninterp = 0;
2279 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2280 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2281
2282 rstate->nregs = 0;
2283
2284 db_shader_control = 0;
2285 for (i = 0; i < rshader->ninput; i++) {
2286 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2287 POSITION goes via GPRs from the SC so isn't counted */
2288 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2289 pos_index = i;
2290 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2291 face_index = i;
2292 else {
2293 ninterp++;
2294 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2295 have_linear = TRUE;
2296 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2297 have_perspective = TRUE;
2298 if (rshader->input[i].centroid)
2299 have_centroid = TRUE;
2300 }
2301
2302 sid = rshader->input[i].spi_sid;
2303
2304 if (sid) {
2305
2306 tmp = S_028644_SEMANTIC(sid);
2307
2308 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
2309 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
2310 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
2311 tmp |= S_028644_FLAT_SHADE(1);
2312 }
2313
2314 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2315 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2316 tmp |= S_028644_PT_SPRITE_TEX(1);
2317 }
2318
2319 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2320 tmp, 0xFFFFFFFF, NULL, 0);
2321
2322 idx++;
2323 }
2324 }
2325
2326 for (i = 0; i < rshader->noutput; i++) {
2327 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2328 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2329 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2330 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2331 }
2332 if (rshader->uses_kill)
2333 db_shader_control |= S_02880C_KILL_ENABLE(1);
2334
2335 exports_ps = 0;
2336 num_cout = 0;
2337 for (i = 0; i < rshader->noutput; i++) {
2338 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2339 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2340 exports_ps |= 1;
2341 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2342 if (rshader->fs_write_all)
2343 num_cout = rshader->nr_cbufs;
2344 else
2345 num_cout++;
2346 }
2347 }
2348 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2349 if (!exports_ps) {
2350 /* always at least export 1 component per pixel */
2351 exports_ps = 2;
2352 }
2353
2354 if (ninterp == 0) {
2355 ninterp = 1;
2356 have_perspective = TRUE;
2357 }
2358
2359 if (!have_perspective && !have_linear)
2360 have_perspective = TRUE;
2361
2362 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2363 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2364 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2365 spi_input_z = 0;
2366 if (pos_index != -1) {
2367 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2368 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2369 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2370 spi_input_z |= 1;
2371 }
2372
2373 spi_ps_in_control_1 = 0;
2374 if (face_index != -1) {
2375 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2376 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2377 }
2378
2379 spi_baryc_cntl = 0;
2380 if (have_perspective)
2381 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2382 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2383 if (have_linear)
2384 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2385 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2386
2387 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2388 spi_ps_in_control_0, 0xFFFFFFFF, NULL, 0);
2389 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2390 spi_ps_in_control_1, 0xFFFFFFFF, NULL, 0);
2391 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2392 0, 0xFFFFFFFF, NULL, 0);
2393 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL, 0);
2394 r600_pipe_state_add_reg(rstate,
2395 R_0286E0_SPI_BARYC_CNTL,
2396 spi_baryc_cntl,
2397 0xFFFFFFFF, NULL, 0);
2398
2399 r600_pipe_state_add_reg(rstate,
2400 R_028840_SQ_PGM_START_PS,
2401 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2402 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2403 r600_pipe_state_add_reg(rstate,
2404 R_028844_SQ_PGM_RESOURCES_PS,
2405 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2406 S_028844_PRIME_CACHE_ON_DRAW(1) |
2407 S_028844_STACK_SIZE(rshader->bc.nstack),
2408 0xFFFFFFFF, NULL, 0);
2409 r600_pipe_state_add_reg(rstate,
2410 R_028848_SQ_PGM_RESOURCES_2_PS,
2411 0x0, 0xFFFFFFFF, NULL, 0);
2412 r600_pipe_state_add_reg(rstate,
2413 R_02884C_SQ_PGM_EXPORTS_PS,
2414 exports_ps, 0xFFFFFFFF, NULL, 0);
2415 /* only set some bits here, the other bits are set in the dsa state */
2416 r600_pipe_state_add_reg(rstate,
2417 R_02880C_DB_SHADER_CONTROL,
2418 db_shader_control,
2419 S_02880C_Z_EXPORT_ENABLE(1) |
2420 S_02880C_STENCIL_EXPORT_ENABLE(1) |
2421 S_02880C_KILL_ENABLE(1),
2422 NULL, 0);
2423 r600_pipe_state_add_reg(rstate,
2424 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
2425 0xFFFFFFFF, NULL, 0);
2426
2427 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2428 }
2429
2430 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2431 {
2432 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2433 struct r600_pipe_state *rstate = &shader->rstate;
2434 struct r600_shader *rshader = &shader->shader;
2435 unsigned spi_vs_out_id[10] = {};
2436 unsigned i, tmp, nparams = 0;
2437
2438 /* clear previous register */
2439 rstate->nregs = 0;
2440
2441 for (i = 0; i < rshader->noutput; i++) {
2442 if (rshader->output[i].spi_sid) {
2443 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2444 spi_vs_out_id[nparams / 4] |= tmp;
2445 nparams++;
2446 }
2447 }
2448
2449 for (i = 0; i < 10; i++) {
2450 r600_pipe_state_add_reg(rstate,
2451 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2452 spi_vs_out_id[i], 0xFFFFFFFF, NULL, 0);
2453 }
2454
2455 /* Certain attributes (position, psize, etc.) don't count as params.
2456 * VS is required to export at least one param and r600_shader_from_tgsi()
2457 * takes care of adding a dummy export.
2458 */
2459 if (nparams < 1)
2460 nparams = 1;
2461
2462 r600_pipe_state_add_reg(rstate,
2463 R_0286C4_SPI_VS_OUT_CONFIG,
2464 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2465 0xFFFFFFFF, NULL, 0);
2466 r600_pipe_state_add_reg(rstate,
2467 R_028860_SQ_PGM_RESOURCES_VS,
2468 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2469 S_028860_STACK_SIZE(rshader->bc.nstack),
2470 0xFFFFFFFF, NULL, 0);
2471 r600_pipe_state_add_reg(rstate,
2472 R_028864_SQ_PGM_RESOURCES_2_VS,
2473 0x0, 0xFFFFFFFF, NULL, 0);
2474 r600_pipe_state_add_reg(rstate,
2475 R_02885C_SQ_PGM_START_VS,
2476 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2477 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2478
2479 r600_pipe_state_add_reg(rstate,
2480 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2481 0xFFFFFFFF, NULL, 0);
2482 }
2483
2484 void evergreen_fetch_shader(struct pipe_context *ctx,
2485 struct r600_vertex_element *ve)
2486 {
2487 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2488 struct r600_pipe_state *rstate = &ve->rstate;
2489 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2490 rstate->nregs = 0;
2491 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
2492 0x00000000, 0xFFFFFFFF, NULL, 0);
2493 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2494 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2495 0xFFFFFFFF, ve->fetch_shader, RADEON_USAGE_READ);
2496 }
2497
2498 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
2499 {
2500 struct pipe_depth_stencil_alpha_state dsa;
2501 struct r600_pipe_state *rstate;
2502
2503 memset(&dsa, 0, sizeof(dsa));
2504
2505 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2506 r600_pipe_state_add_reg(rstate,
2507 R_02880C_DB_SHADER_CONTROL,
2508 0x0,
2509 S_02880C_DUAL_EXPORT_ENABLE(1), NULL, 0);
2510 r600_pipe_state_add_reg(rstate,
2511 R_028000_DB_RENDER_CONTROL,
2512 S_028000_DEPTH_COPY_ENABLE(1) |
2513 S_028000_STENCIL_COPY_ENABLE(1) |
2514 S_028000_COPY_CENTROID(1),
2515 S_028000_DEPTH_COPY_ENABLE(1) |
2516 S_028000_STENCIL_COPY_ENABLE(1) |
2517 S_028000_COPY_CENTROID(1), NULL, 0);
2518 return rstate;
2519 }
2520
2521 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
2522 struct r600_pipe_resource_state *rstate)
2523 {
2524 rstate->id = R600_PIPE_STATE_RESOURCE;
2525
2526 rstate->val[0] = 0;
2527 rstate->bo[0] = NULL;
2528 rstate->val[1] = 0;
2529 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2530 rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2531 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2532 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2533 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2534 rstate->val[4] = 0;
2535 rstate->val[5] = 0;
2536 rstate->val[6] = 0;
2537 rstate->val[7] = 0xc0000000;
2538 }
2539
2540
2541 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
2542 struct r600_pipe_resource_state *rstate,
2543 struct r600_resource *rbuffer,
2544 unsigned offset, unsigned stride,
2545 enum radeon_bo_usage usage)
2546 {
2547 uint64_t va;
2548
2549 va = r600_resource_va(ctx->screen, (void *)rbuffer);
2550 rstate->bo[0] = rbuffer;
2551 rstate->bo_usage[0] = usage;
2552 rstate->val[0] = (offset + va) & 0xFFFFFFFFUL;
2553 rstate->val[1] = rbuffer->buf->size - offset - 1;
2554 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2555 S_030008_STRIDE(stride) |
2556 (((va + offset) >> 32UL) & 0xFF);
2557 }