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Revert "r600g: truncate point sampled texture coordinates"
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "eg_state_inlines.h"
50
51 static void evergreen_set_blend_color(struct pipe_context *ctx,
52 const struct pipe_blend_color *state)
53 {
54 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
55 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
56
57 if (rstate == NULL)
58 return;
59
60 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
61 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
62 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
63 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
65
66 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
67 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
68 r600_context_pipe_state_set(&rctx->ctx, rstate);
69 }
70
71 static void *evergreen_create_blend_state(struct pipe_context *ctx,
72 const struct pipe_blend_state *state)
73 {
74 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
75 struct r600_pipe_state *rstate;
76 u32 color_control, target_mask;
77 /* FIXME there is more then 8 framebuffer */
78 unsigned blend_cntl[8];
79
80 if (blend == NULL) {
81 return NULL;
82 }
83 rstate = &blend->rstate;
84
85 rstate->id = R600_PIPE_STATE_BLEND;
86
87 target_mask = 0;
88 color_control = S_028808_MODE(1);
89 if (state->logicop_enable) {
90 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
91 } else {
92 color_control |= (0xcc << 16);
93 }
94 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
95 if (state->independent_blend_enable) {
96 for (int i = 0; i < 8; i++) {
97 target_mask |= (state->rt[i].colormask << (4 * i));
98 }
99 } else {
100 for (int i = 0; i < 8; i++) {
101 target_mask |= (state->rt[0].colormask << (4 * i));
102 }
103 }
104 blend->cb_target_mask = target_mask;
105 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
106 color_control, 0xFFFFFFFD, NULL);
107 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
108
109 for (int i = 0; i < 8; i++) {
110 /* state->rt entries > 0 only written if independent blending */
111 const int j = state->independent_blend_enable ? i : 0;
112
113 unsigned eqRGB = state->rt[j].rgb_func;
114 unsigned srcRGB = state->rt[j].rgb_src_factor;
115 unsigned dstRGB = state->rt[j].rgb_dst_factor;
116 unsigned eqA = state->rt[j].alpha_func;
117 unsigned srcA = state->rt[j].alpha_src_factor;
118 unsigned dstA = state->rt[j].alpha_dst_factor;
119
120 blend_cntl[i] = 0;
121 if (!state->rt[j].blend_enable)
122 continue;
123
124 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
125 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
126 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
127 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
128
129 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
130 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
131 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
132 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
133 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
134 }
135 }
136 for (int i = 0; i < 8; i++) {
137 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
138 }
139
140 return rstate;
141 }
142
143 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
144 const struct pipe_depth_stencil_alpha_state *state)
145 {
146 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
147 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
148 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
149
150 if (rstate == NULL) {
151 return NULL;
152 }
153
154 rstate->id = R600_PIPE_STATE_DSA;
155 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
156 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
157 stencil_ref_mask = 0;
158 stencil_ref_mask_bf = 0;
159 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
160 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
161 S_028800_ZFUNC(state->depth.func);
162
163 /* stencil */
164 if (state->stencil[0].enabled) {
165 db_depth_control |= S_028800_STENCIL_ENABLE(1);
166 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
167 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
168 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
169 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
170
171
172 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
173 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
174 if (state->stencil[1].enabled) {
175 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
176 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
177 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
178 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
179 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
180 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
181 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
182 }
183 }
184
185 /* alpha */
186 alpha_test_control = 0;
187 alpha_ref = 0;
188 if (state->alpha.enabled) {
189 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
190 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
191 alpha_ref = fui(state->alpha.ref_value);
192 }
193
194 /* misc */
195 db_render_control = 0;
196 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
197 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
198 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
199 /* TODO db_render_override depends on query */
200 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
201 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
202 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
203 r600_pipe_state_add_reg(rstate,
204 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
205 0xFFFFFFFF & C_028430_STENCILREF, NULL);
206 r600_pipe_state_add_reg(rstate,
207 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
208 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
209 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
210 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
211 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
212 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
213 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
214 * evergreen_pipe_shader_ps().*/
215 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL);
216 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
217 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
218 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
219 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
220 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
221 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
222
223 return rstate;
224 }
225
226 static void *evergreen_create_rs_state(struct pipe_context *ctx,
227 const struct pipe_rasterizer_state *state)
228 {
229 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
230 struct r600_pipe_state *rstate;
231 unsigned tmp;
232 unsigned prov_vtx = 1, polygon_dual_mode;
233 unsigned clip_rule;
234
235 if (rs == NULL) {
236 return NULL;
237 }
238
239 rstate = &rs->rstate;
240 rs->flatshade = state->flatshade;
241 rs->sprite_coord_enable = state->sprite_coord_enable;
242
243 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
244
245 /* offset */
246 rs->offset_units = state->offset_units;
247 rs->offset_scale = state->offset_scale * 12.0f;
248
249 rstate->id = R600_PIPE_STATE_RASTERIZER;
250 if (state->flatshade_first)
251 prov_vtx = 0;
252 tmp = S_0286D4_FLAT_SHADE_ENA(1);
253 if (state->sprite_coord_enable) {
254 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
255 S_0286D4_PNT_SPRITE_OVRD_X(2) |
256 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
257 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
258 S_0286D4_PNT_SPRITE_OVRD_W(1);
259 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
260 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
261 }
262 }
263 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
264
265 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
266 state->fill_back != PIPE_POLYGON_MODE_FILL);
267 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
268 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
269 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
270 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
271 S_028814_FACE(!state->front_ccw) |
272 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
273 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
274 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
275 S_028814_POLY_MODE(polygon_dual_mode) |
276 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
277 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
278 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
279 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
280 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
281 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
282 /* point size 12.4 fixed point */
283 tmp = (unsigned)(state->point_size * 8.0);
284 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
285 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
286
287 tmp = (unsigned)state->line_width * 8;
288 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
289
290 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
291 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
292 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
293 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
294 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
295 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
296
297 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
298 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
299 0xFFFFFFFF, NULL);
300
301 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
302 return rstate;
303 }
304
305 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
306 const struct pipe_sampler_state *state)
307 {
308 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
309 union util_color uc;
310
311 if (rstate == NULL) {
312 return NULL;
313 }
314
315 rstate->id = R600_PIPE_STATE_SAMPLER;
316 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
317 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
318 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
319 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
320 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
321 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
322 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
323 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
324 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
325 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
326 /* FIXME LOD it depends on texture base level ... */
327 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
328 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
329 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
330 0xFFFFFFFF, NULL);
331 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
332 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
333 S_03C008_TYPE(1),
334 0xFFFFFFFF, NULL);
335
336 if (uc.ui) {
337 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
338 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
339 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
340 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
341 }
342 return rstate;
343 }
344
345 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
346 struct pipe_resource *texture,
347 const struct pipe_sampler_view *state)
348 {
349 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
350 struct r600_pipe_state *rstate;
351 const struct util_format_description *desc;
352 struct r600_resource_texture *tmp;
353 struct r600_resource *rbuffer;
354 unsigned format, endian;
355 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
356 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
357 struct r600_bo *bo[2];
358
359 if (resource == NULL)
360 return NULL;
361 rstate = &resource->state;
362
363 /* initialize base object */
364 resource->base = *state;
365 resource->base.texture = NULL;
366 pipe_reference(NULL, &texture->reference);
367 resource->base.texture = texture;
368 resource->base.reference.count = 1;
369 resource->base.context = ctx;
370
371 swizzle[0] = state->swizzle_r;
372 swizzle[1] = state->swizzle_g;
373 swizzle[2] = state->swizzle_b;
374 swizzle[3] = state->swizzle_a;
375 format = r600_translate_texformat(ctx->screen, state->format,
376 swizzle,
377 &word4, &yuv_format);
378 if (format == ~0) {
379 format = 0;
380 }
381 desc = util_format_description(state->format);
382 if (desc == NULL) {
383 R600_ERR("unknow format %d\n", state->format);
384 }
385 tmp = (struct r600_resource_texture *)texture;
386 if (tmp->depth && !tmp->is_flushing_texture) {
387 r600_texture_depth_flush(ctx, texture, TRUE);
388 tmp = tmp->flushed_depth_texture;
389 }
390
391 endian = r600_colorformat_endian_swap(format);
392
393 if (tmp->force_int_type) {
394 word4 &= C_030010_NUM_FORMAT_ALL;
395 word4 |= S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_INT);
396 }
397
398 rbuffer = &tmp->resource;
399 bo[0] = rbuffer->bo;
400 bo[1] = rbuffer->bo;
401
402 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
403 array_mode = tmp->array_mode[0];
404 tile_type = tmp->tile_type;
405
406 /* FIXME properly handle first level != 0 */
407 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
408 S_030000_DIM(r600_tex_dim(texture->target)) |
409 S_030000_PITCH((pitch / 8) - 1) |
410 S_030000_NON_DISP_TILING_ORDER(tile_type) |
411 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
412 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
413 S_030004_TEX_HEIGHT(texture->height0 - 1) |
414 S_030004_TEX_DEPTH(texture->depth0 - 1) |
415 S_030004_ARRAY_MODE(array_mode),
416 0xFFFFFFFF, NULL);
417 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
418 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
419 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
420 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
421 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
422 word4 |
423 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_NO_ZERO) |
424 S_030010_ENDIAN_SWAP(endian) |
425 S_030010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
426 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
427 S_030014_LAST_LEVEL(state->u.tex.last_level) |
428 S_030014_BASE_ARRAY(0) |
429 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
430 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
431 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
432 S_03001C_DATA_FORMAT(format) |
433 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
434
435 return &resource->base;
436 }
437
438 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
439 struct pipe_sampler_view **views)
440 {
441 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
442 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
443
444 for (int i = 0; i < count; i++) {
445 if (resource[i]) {
446 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
447 i + R600_MAX_CONST_BUFFERS);
448 }
449 }
450 }
451
452 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
453 struct pipe_sampler_view **views)
454 {
455 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
456 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
457 int i;
458
459 for (i = 0; i < count; i++) {
460 if (&rctx->ps_samplers.views[i]->base != views[i]) {
461 if (resource[i])
462 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
463 i + R600_MAX_CONST_BUFFERS);
464 else
465 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
466 i + R600_MAX_CONST_BUFFERS);
467
468 pipe_sampler_view_reference(
469 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
470 views[i]);
471 }
472 }
473 for (i = count; i < NUM_TEX_UNITS; i++) {
474 if (rctx->ps_samplers.views[i]) {
475 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
476 i + R600_MAX_CONST_BUFFERS);
477 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
478 }
479 }
480 rctx->ps_samplers.n_views = count;
481 }
482
483 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
484 {
485 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
486 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
487
488
489 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
490 rctx->ps_samplers.n_samplers = count;
491
492 for (int i = 0; i < count; i++) {
493 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
494 }
495 }
496
497 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
498 {
499 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
500 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
501
502 for (int i = 0; i < count; i++) {
503 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
504 }
505 }
506
507 static void evergreen_set_clip_state(struct pipe_context *ctx,
508 const struct pipe_clip_state *state)
509 {
510 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
511 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
512
513 if (rstate == NULL)
514 return;
515
516 rctx->clip = *state;
517 rstate->id = R600_PIPE_STATE_CLIP;
518 for (int i = 0; i < state->nr; i++) {
519 r600_pipe_state_add_reg(rstate,
520 R_0285BC_PA_CL_UCP0_X + i * 16,
521 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
522 r600_pipe_state_add_reg(rstate,
523 R_0285C0_PA_CL_UCP0_Y + i * 16,
524 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
525 r600_pipe_state_add_reg(rstate,
526 R_0285C4_PA_CL_UCP0_Z + i * 16,
527 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
528 r600_pipe_state_add_reg(rstate,
529 R_0285C8_PA_CL_UCP0_W + i * 16,
530 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
531 }
532 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
533 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
534 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
535 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
536
537 free(rctx->states[R600_PIPE_STATE_CLIP]);
538 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
539 r600_context_pipe_state_set(&rctx->ctx, rstate);
540 }
541
542 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
543 const struct pipe_poly_stipple *state)
544 {
545 }
546
547 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
548 {
549 }
550
551 static void evergreen_set_scissor_state(struct pipe_context *ctx,
552 const struct pipe_scissor_state *state)
553 {
554 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
555 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
556 u32 tl, br;
557
558 if (rstate == NULL)
559 return;
560
561 rstate->id = R600_PIPE_STATE_SCISSOR;
562 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
563 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
564 r600_pipe_state_add_reg(rstate,
565 R_028210_PA_SC_CLIPRECT_0_TL, tl,
566 0xFFFFFFFF, NULL);
567 r600_pipe_state_add_reg(rstate,
568 R_028214_PA_SC_CLIPRECT_0_BR, br,
569 0xFFFFFFFF, NULL);
570 r600_pipe_state_add_reg(rstate,
571 R_028218_PA_SC_CLIPRECT_1_TL, tl,
572 0xFFFFFFFF, NULL);
573 r600_pipe_state_add_reg(rstate,
574 R_02821C_PA_SC_CLIPRECT_1_BR, br,
575 0xFFFFFFFF, NULL);
576 r600_pipe_state_add_reg(rstate,
577 R_028220_PA_SC_CLIPRECT_2_TL, tl,
578 0xFFFFFFFF, NULL);
579 r600_pipe_state_add_reg(rstate,
580 R_028224_PA_SC_CLIPRECT_2_BR, br,
581 0xFFFFFFFF, NULL);
582 r600_pipe_state_add_reg(rstate,
583 R_028228_PA_SC_CLIPRECT_3_TL, tl,
584 0xFFFFFFFF, NULL);
585 r600_pipe_state_add_reg(rstate,
586 R_02822C_PA_SC_CLIPRECT_3_BR, br,
587 0xFFFFFFFF, NULL);
588
589 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
590 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
591 r600_context_pipe_state_set(&rctx->ctx, rstate);
592 }
593
594 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
595 const struct pipe_stencil_ref *state)
596 {
597 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
598 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
599 u32 tmp;
600
601 if (rstate == NULL)
602 return;
603
604 rctx->stencil_ref = *state;
605 rstate->id = R600_PIPE_STATE_STENCIL_REF;
606 tmp = S_028430_STENCILREF(state->ref_value[0]);
607 r600_pipe_state_add_reg(rstate,
608 R_028430_DB_STENCILREFMASK, tmp,
609 ~C_028430_STENCILREF, NULL);
610 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
611 r600_pipe_state_add_reg(rstate,
612 R_028434_DB_STENCILREFMASK_BF, tmp,
613 ~C_028434_STENCILREF_BF, NULL);
614
615 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
616 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
617 r600_context_pipe_state_set(&rctx->ctx, rstate);
618 }
619
620 static void evergreen_set_viewport_state(struct pipe_context *ctx,
621 const struct pipe_viewport_state *state)
622 {
623 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
624 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
625
626 if (rstate == NULL)
627 return;
628
629 rctx->viewport = *state;
630 rstate->id = R600_PIPE_STATE_VIEWPORT;
631 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
632 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
633 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
634 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
635 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
636 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
637 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
638 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
639 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
640
641 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
642 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
643 r600_context_pipe_state_set(&rctx->ctx, rstate);
644 }
645
646 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
647 const struct pipe_framebuffer_state *state, int cb)
648 {
649 struct r600_resource_texture *rtex;
650 struct r600_resource *rbuffer;
651 struct r600_surface *surf;
652 unsigned level = state->cbufs[cb]->u.tex.level;
653 unsigned pitch, slice;
654 unsigned color_info;
655 unsigned format, swap, ntype, endian;
656 unsigned offset;
657 unsigned tile_type;
658 const struct util_format_description *desc;
659 struct r600_bo *bo[3];
660 int i;
661
662 surf = (struct r600_surface *)state->cbufs[cb];
663 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
664
665 if (rtex->depth && !rtex->is_flushing_texture) {
666 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
667 rtex = rtex->flushed_depth_texture;
668 }
669
670 rbuffer = &rtex->resource;
671 bo[0] = rbuffer->bo;
672 bo[1] = rbuffer->bo;
673 bo[2] = rbuffer->bo;
674
675 /* XXX quite sure for dx10+ hw don't need any offset hacks */
676 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
677 level, state->cbufs[cb]->u.tex.first_layer);
678 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
679 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
680 desc = util_format_description(surf->base.format);
681 for (i = 0; i < 4; i++) {
682 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
683 break;
684 }
685 }
686 ntype = V_028C70_NUMBER_UNORM;
687 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
688 ntype = V_028C70_NUMBER_SRGB;
689 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
690 ntype = V_028C70_NUMBER_SNORM;
691
692 format = r600_translate_colorformat(surf->base.format);
693 swap = r600_translate_colorswap(surf->base.format);
694 if (rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
695 endian = ENDIAN_NONE;
696 } else {
697 endian = r600_colorformat_endian_swap(format);
698 }
699
700 /* disable when gallium grows int textures */
701 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
702 ntype = V_028C70_NUMBER_UINT;
703
704 color_info = S_028C70_FORMAT(format) |
705 S_028C70_COMP_SWAP(swap) |
706 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
707 S_028C70_BLEND_CLAMP(1) |
708 S_028C70_NUMBER_TYPE(ntype) |
709 S_028C70_ENDIAN(endian);
710
711
712 /* we can only set the export size if any thing is snorm/unorm component is > 11 bits,
713 if we aren't a float, sint or uint */
714 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
715 desc->channel[i].size < 12 && desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
716 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT)
717 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
718
719 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
720 tile_type = rtex->tile_type;
721 } else /* workaround for linear buffers */
722 tile_type = 1;
723
724 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
725 r600_pipe_state_add_reg(rstate,
726 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
727 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
728 r600_pipe_state_add_reg(rstate,
729 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
730 0x0, 0xFFFFFFFF, NULL);
731 r600_pipe_state_add_reg(rstate,
732 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
733 color_info, 0xFFFFFFFF, bo[0]);
734 r600_pipe_state_add_reg(rstate,
735 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
736 S_028C64_PITCH_TILE_MAX(pitch),
737 0xFFFFFFFF, NULL);
738 r600_pipe_state_add_reg(rstate,
739 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
740 S_028C68_SLICE_TILE_MAX(slice),
741 0xFFFFFFFF, NULL);
742 r600_pipe_state_add_reg(rstate,
743 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
744 0x00000000, 0xFFFFFFFF, NULL);
745 r600_pipe_state_add_reg(rstate,
746 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
747 S_028C74_NON_DISP_TILING_ORDER(tile_type),
748 0xFFFFFFFF, bo[0]);
749 }
750
751 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
752 const struct pipe_framebuffer_state *state)
753 {
754 struct r600_resource_texture *rtex;
755 struct r600_resource *rbuffer;
756 struct r600_surface *surf;
757 unsigned level;
758 unsigned pitch, slice, format, stencil_format;
759 unsigned offset;
760
761 if (state->zsbuf == NULL)
762 return;
763
764 level = state->zsbuf->u.tex.level;
765
766 surf = (struct r600_surface *)state->zsbuf;
767 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
768
769 rbuffer = &rtex->resource;
770
771 /* XXX quite sure for dx10+ hw don't need any offset hacks */
772 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
773 level, state->zsbuf->u.tex.first_layer);
774 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
775 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
776 format = r600_translate_dbformat(state->zsbuf->texture->format);
777 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
778
779 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
780 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
781 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
782 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
783
784 if (stencil_format) {
785 uint32_t stencil_offset;
786
787 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
788 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
789 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
790 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
791 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
792 }
793
794 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
795 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
796 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
797
798 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
799 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
800 0xFFFFFFFF, rbuffer->bo);
801 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
802 S_028058_PITCH_TILE_MAX(pitch),
803 0xFFFFFFFF, NULL);
804 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
805 S_02805C_SLICE_TILE_MAX(slice),
806 0xFFFFFFFF, NULL);
807 }
808
809 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
810 const struct pipe_framebuffer_state *state)
811 {
812 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
813 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
814 u32 shader_mask, tl, br, target_mask;
815
816 if (rstate == NULL)
817 return;
818
819 evergreen_context_flush_dest_caches(&rctx->ctx);
820 rctx->ctx.num_dest_buffers = state->nr_cbufs;
821
822 /* unreference old buffer and reference new one */
823 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
824
825 util_copy_framebuffer_state(&rctx->framebuffer, state);
826
827 /* build states */
828 for (int i = 0; i < state->nr_cbufs; i++) {
829 evergreen_cb(rctx, rstate, state, i);
830 }
831 if (state->zsbuf) {
832 evergreen_db(rctx, rstate, state);
833 rctx->ctx.num_dest_buffers++;
834 }
835
836 target_mask = 0x00000000;
837 target_mask = 0xFFFFFFFF;
838 shader_mask = 0;
839 for (int i = 0; i < state->nr_cbufs; i++) {
840 target_mask ^= 0xf << (i * 4);
841 shader_mask |= 0xf << (i * 4);
842 }
843 tl = S_028240_TL_X(0) | S_028240_TL_Y(0);
844 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
845
846 r600_pipe_state_add_reg(rstate,
847 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
848 0xFFFFFFFF, NULL);
849 r600_pipe_state_add_reg(rstate,
850 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
851 0xFFFFFFFF, NULL);
852 r600_pipe_state_add_reg(rstate,
853 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
854 0xFFFFFFFF, NULL);
855 r600_pipe_state_add_reg(rstate,
856 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
857 0xFFFFFFFF, NULL);
858 r600_pipe_state_add_reg(rstate,
859 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
860 0xFFFFFFFF, NULL);
861 r600_pipe_state_add_reg(rstate,
862 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
863 0xFFFFFFFF, NULL);
864 r600_pipe_state_add_reg(rstate,
865 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
866 0xFFFFFFFF, NULL);
867 r600_pipe_state_add_reg(rstate,
868 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
869 0xFFFFFFFF, NULL);
870 r600_pipe_state_add_reg(rstate,
871 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
872 0xFFFFFFFF, NULL);
873 r600_pipe_state_add_reg(rstate,
874 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
875 0xFFFFFFFF, NULL);
876
877 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
878 0x00000000, target_mask, NULL);
879 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
880 shader_mask, 0xFFFFFFFF, NULL);
881 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
882 0x00000000, 0xFFFFFFFF, NULL);
883 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
884 0x00000000, 0xFFFFFFFF, NULL);
885
886 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
887 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
888 r600_context_pipe_state_set(&rctx->ctx, rstate);
889
890 if (state->zsbuf) {
891 evergreen_polygon_offset_update(rctx);
892 }
893 }
894
895 static void evergreen_texture_barrier(struct pipe_context *ctx)
896 {
897 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
898
899 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
900 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
901 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
902 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
903 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
904 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
905 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
906 }
907
908 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
909 {
910 rctx->context.create_blend_state = evergreen_create_blend_state;
911 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
912 rctx->context.create_fs_state = r600_create_shader_state;
913 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
914 rctx->context.create_sampler_state = evergreen_create_sampler_state;
915 rctx->context.create_sampler_view = evergreen_create_sampler_view;
916 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
917 rctx->context.create_vs_state = r600_create_shader_state;
918 rctx->context.bind_blend_state = r600_bind_blend_state;
919 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
920 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
921 rctx->context.bind_fs_state = r600_bind_ps_shader;
922 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
923 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
924 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
925 rctx->context.bind_vs_state = r600_bind_vs_shader;
926 rctx->context.delete_blend_state = r600_delete_state;
927 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
928 rctx->context.delete_fs_state = r600_delete_ps_shader;
929 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
930 rctx->context.delete_sampler_state = r600_delete_state;
931 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
932 rctx->context.delete_vs_state = r600_delete_vs_shader;
933 rctx->context.set_blend_color = evergreen_set_blend_color;
934 rctx->context.set_clip_state = evergreen_set_clip_state;
935 rctx->context.set_constant_buffer = r600_set_constant_buffer;
936 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
937 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
938 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
939 rctx->context.set_sample_mask = evergreen_set_sample_mask;
940 rctx->context.set_scissor_state = evergreen_set_scissor_state;
941 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
942 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
943 rctx->context.set_index_buffer = r600_set_index_buffer;
944 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
945 rctx->context.set_viewport_state = evergreen_set_viewport_state;
946 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
947 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
948 rctx->context.texture_barrier = evergreen_texture_barrier;
949 }
950
951 void evergreen_init_config(struct r600_pipe_context *rctx)
952 {
953 struct r600_pipe_state *rstate = &rctx->config;
954 int ps_prio;
955 int vs_prio;
956 int gs_prio;
957 int es_prio;
958 int hs_prio, cs_prio, ls_prio;
959 int num_ps_gprs;
960 int num_vs_gprs;
961 int num_gs_gprs;
962 int num_es_gprs;
963 int num_hs_gprs;
964 int num_ls_gprs;
965 int num_temp_gprs;
966 int num_ps_threads;
967 int num_vs_threads;
968 int num_gs_threads;
969 int num_es_threads;
970 int num_hs_threads;
971 int num_ls_threads;
972 int num_ps_stack_entries;
973 int num_vs_stack_entries;
974 int num_gs_stack_entries;
975 int num_es_stack_entries;
976 int num_hs_stack_entries;
977 int num_ls_stack_entries;
978 enum radeon_family family;
979 unsigned tmp;
980
981 family = r600_get_family(rctx->radeon);
982 ps_prio = 0;
983 vs_prio = 1;
984 gs_prio = 2;
985 es_prio = 3;
986 hs_prio = 0;
987 ls_prio = 0;
988 cs_prio = 0;
989
990 switch (family) {
991 case CHIP_CEDAR:
992 default:
993 num_ps_gprs = 93;
994 num_vs_gprs = 46;
995 num_temp_gprs = 4;
996 num_gs_gprs = 31;
997 num_es_gprs = 31;
998 num_hs_gprs = 23;
999 num_ls_gprs = 23;
1000 num_ps_threads = 96;
1001 num_vs_threads = 16;
1002 num_gs_threads = 16;
1003 num_es_threads = 16;
1004 num_hs_threads = 16;
1005 num_ls_threads = 16;
1006 num_ps_stack_entries = 42;
1007 num_vs_stack_entries = 42;
1008 num_gs_stack_entries = 42;
1009 num_es_stack_entries = 42;
1010 num_hs_stack_entries = 42;
1011 num_ls_stack_entries = 42;
1012 break;
1013 case CHIP_REDWOOD:
1014 num_ps_gprs = 93;
1015 num_vs_gprs = 46;
1016 num_temp_gprs = 4;
1017 num_gs_gprs = 31;
1018 num_es_gprs = 31;
1019 num_hs_gprs = 23;
1020 num_ls_gprs = 23;
1021 num_ps_threads = 128;
1022 num_vs_threads = 20;
1023 num_gs_threads = 20;
1024 num_es_threads = 20;
1025 num_hs_threads = 20;
1026 num_ls_threads = 20;
1027 num_ps_stack_entries = 42;
1028 num_vs_stack_entries = 42;
1029 num_gs_stack_entries = 42;
1030 num_es_stack_entries = 42;
1031 num_hs_stack_entries = 42;
1032 num_ls_stack_entries = 42;
1033 break;
1034 case CHIP_JUNIPER:
1035 num_ps_gprs = 93;
1036 num_vs_gprs = 46;
1037 num_temp_gprs = 4;
1038 num_gs_gprs = 31;
1039 num_es_gprs = 31;
1040 num_hs_gprs = 23;
1041 num_ls_gprs = 23;
1042 num_ps_threads = 128;
1043 num_vs_threads = 20;
1044 num_gs_threads = 20;
1045 num_es_threads = 20;
1046 num_hs_threads = 20;
1047 num_ls_threads = 20;
1048 num_ps_stack_entries = 85;
1049 num_vs_stack_entries = 85;
1050 num_gs_stack_entries = 85;
1051 num_es_stack_entries = 85;
1052 num_hs_stack_entries = 85;
1053 num_ls_stack_entries = 85;
1054 break;
1055 case CHIP_CYPRESS:
1056 case CHIP_HEMLOCK:
1057 num_ps_gprs = 93;
1058 num_vs_gprs = 46;
1059 num_temp_gprs = 4;
1060 num_gs_gprs = 31;
1061 num_es_gprs = 31;
1062 num_hs_gprs = 23;
1063 num_ls_gprs = 23;
1064 num_ps_threads = 128;
1065 num_vs_threads = 20;
1066 num_gs_threads = 20;
1067 num_es_threads = 20;
1068 num_hs_threads = 20;
1069 num_ls_threads = 20;
1070 num_ps_stack_entries = 85;
1071 num_vs_stack_entries = 85;
1072 num_gs_stack_entries = 85;
1073 num_es_stack_entries = 85;
1074 num_hs_stack_entries = 85;
1075 num_ls_stack_entries = 85;
1076 break;
1077 case CHIP_PALM:
1078 num_ps_gprs = 93;
1079 num_vs_gprs = 46;
1080 num_temp_gprs = 4;
1081 num_gs_gprs = 31;
1082 num_es_gprs = 31;
1083 num_hs_gprs = 23;
1084 num_ls_gprs = 23;
1085 num_ps_threads = 96;
1086 num_vs_threads = 16;
1087 num_gs_threads = 16;
1088 num_es_threads = 16;
1089 num_hs_threads = 16;
1090 num_ls_threads = 16;
1091 num_ps_stack_entries = 42;
1092 num_vs_stack_entries = 42;
1093 num_gs_stack_entries = 42;
1094 num_es_stack_entries = 42;
1095 num_hs_stack_entries = 42;
1096 num_ls_stack_entries = 42;
1097 break;
1098 case CHIP_BARTS:
1099 num_ps_gprs = 93;
1100 num_vs_gprs = 46;
1101 num_temp_gprs = 4;
1102 num_gs_gprs = 31;
1103 num_es_gprs = 31;
1104 num_hs_gprs = 23;
1105 num_ls_gprs = 23;
1106 num_ps_threads = 128;
1107 num_vs_threads = 20;
1108 num_gs_threads = 20;
1109 num_es_threads = 20;
1110 num_hs_threads = 20;
1111 num_ls_threads = 20;
1112 num_ps_stack_entries = 85;
1113 num_vs_stack_entries = 85;
1114 num_gs_stack_entries = 85;
1115 num_es_stack_entries = 85;
1116 num_hs_stack_entries = 85;
1117 num_ls_stack_entries = 85;
1118 break;
1119 case CHIP_TURKS:
1120 num_ps_gprs = 93;
1121 num_vs_gprs = 46;
1122 num_temp_gprs = 4;
1123 num_gs_gprs = 31;
1124 num_es_gprs = 31;
1125 num_hs_gprs = 23;
1126 num_ls_gprs = 23;
1127 num_ps_threads = 128;
1128 num_vs_threads = 20;
1129 num_gs_threads = 20;
1130 num_es_threads = 20;
1131 num_hs_threads = 20;
1132 num_ls_threads = 20;
1133 num_ps_stack_entries = 42;
1134 num_vs_stack_entries = 42;
1135 num_gs_stack_entries = 42;
1136 num_es_stack_entries = 42;
1137 num_hs_stack_entries = 42;
1138 num_ls_stack_entries = 42;
1139 break;
1140 case CHIP_CAICOS:
1141 num_ps_gprs = 93;
1142 num_vs_gprs = 46;
1143 num_temp_gprs = 4;
1144 num_gs_gprs = 31;
1145 num_es_gprs = 31;
1146 num_hs_gprs = 23;
1147 num_ls_gprs = 23;
1148 num_ps_threads = 128;
1149 num_vs_threads = 10;
1150 num_gs_threads = 10;
1151 num_es_threads = 10;
1152 num_hs_threads = 10;
1153 num_ls_threads = 10;
1154 num_ps_stack_entries = 42;
1155 num_vs_stack_entries = 42;
1156 num_gs_stack_entries = 42;
1157 num_es_stack_entries = 42;
1158 num_hs_stack_entries = 42;
1159 num_ls_stack_entries = 42;
1160 break;
1161 }
1162
1163 tmp = 0x00000000;
1164 switch (family) {
1165 case CHIP_CEDAR:
1166 case CHIP_PALM:
1167 case CHIP_CAICOS:
1168 break;
1169 default:
1170 tmp |= S_008C00_VC_ENABLE(1);
1171 break;
1172 }
1173 tmp |= S_008C00_EXPORT_SRC_C(1);
1174 tmp |= S_008C00_CS_PRIO(cs_prio);
1175 tmp |= S_008C00_LS_PRIO(ls_prio);
1176 tmp |= S_008C00_HS_PRIO(hs_prio);
1177 tmp |= S_008C00_PS_PRIO(ps_prio);
1178 tmp |= S_008C00_VS_PRIO(vs_prio);
1179 tmp |= S_008C00_GS_PRIO(gs_prio);
1180 tmp |= S_008C00_ES_PRIO(es_prio);
1181 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1182
1183 tmp = 0;
1184 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1185 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1186 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1187 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1188
1189 tmp = 0;
1190 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1191 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1192 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1193
1194 tmp = 0;
1195 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1196 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1197 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1198
1199 tmp = 0;
1200 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1201 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1202 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1203 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1204 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1205
1206 tmp = 0;
1207 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1208 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1209 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1210
1211 tmp = 0;
1212 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1213 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1214 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1215
1216 tmp = 0;
1217 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1218 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1219 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1220
1221 tmp = 0;
1222 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1223 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1224 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1225
1226 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1227 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1228
1229 #if 0
1230 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1231
1232 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1233 #endif
1234 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1235 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1236
1237 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1238 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1239 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1240 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1241 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1242 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1243
1244 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1245 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1246 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1247 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1248
1249 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1250 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1251 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1252 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1253 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1254 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1255 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1256 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1257 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1258 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1259 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1260 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1261 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1262 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1263 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1264 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1265 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1266 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1267
1268 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1269 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1270 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1271 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1272 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1273 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1274 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1275 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1276 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1277 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1278 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1279 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1280 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1281 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1282 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1283 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1284 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1285 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1286 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1287 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1288 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1289 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1290 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1291 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1292 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1293 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1294 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1295 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1296 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1297 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1298 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1299 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1300
1301 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
1302
1303 r600_context_pipe_state_set(&rctx->ctx, rstate);
1304 }
1305
1306 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
1307 {
1308 struct r600_pipe_state state;
1309
1310 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
1311 state.nregs = 0;
1312 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1313 float offset_units = rctx->rasterizer->offset_units;
1314 unsigned offset_db_fmt_cntl = 0, depth;
1315
1316 switch (rctx->framebuffer.zsbuf->texture->format) {
1317 case PIPE_FORMAT_Z24X8_UNORM:
1318 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1319 depth = -24;
1320 offset_units *= 2.0f;
1321 break;
1322 case PIPE_FORMAT_Z32_FLOAT:
1323 depth = -23;
1324 offset_units *= 1.0f;
1325 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1326 break;
1327 case PIPE_FORMAT_Z16_UNORM:
1328 depth = -16;
1329 offset_units *= 4.0f;
1330 break;
1331 default:
1332 return;
1333 }
1334 /* FIXME some of those reg can be computed with cso */
1335 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1336 r600_pipe_state_add_reg(&state,
1337 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1338 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1339 r600_pipe_state_add_reg(&state,
1340 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1341 fui(offset_units), 0xFFFFFFFF, NULL);
1342 r600_pipe_state_add_reg(&state,
1343 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1344 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1345 r600_pipe_state_add_reg(&state,
1346 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1347 fui(offset_units), 0xFFFFFFFF, NULL);
1348 r600_pipe_state_add_reg(&state,
1349 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1350 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1351 r600_context_pipe_state_set(&rctx->ctx, &state);
1352 }
1353 }
1354
1355 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1356 {
1357 struct r600_pipe_state *rstate = &shader->rstate;
1358 struct r600_shader *rshader = &shader->shader;
1359 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
1360 int pos_index = -1, face_index = -1;
1361 int ninterp = 0;
1362 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1363 unsigned spi_baryc_cntl;
1364
1365 rstate->nregs = 0;
1366
1367 db_shader_control = 0;
1368 for (i = 0; i < rshader->ninput; i++) {
1369 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1370 POSITION goes via GPRs from the SC so isn't counted */
1371 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1372 pos_index = i;
1373 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1374 face_index = i;
1375 else {
1376 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
1377 rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1378 ninterp++;
1379 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1380 have_linear = TRUE;
1381 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1382 have_perspective = TRUE;
1383 if (rshader->input[i].centroid)
1384 have_centroid = TRUE;
1385 }
1386 }
1387 for (i = 0; i < rshader->noutput; i++) {
1388 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1389 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1390 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1391 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
1392 }
1393 if (rshader->uses_kill)
1394 db_shader_control |= S_02880C_KILL_ENABLE(1);
1395
1396 exports_ps = 0;
1397 num_cout = 0;
1398 for (i = 0; i < rshader->noutput; i++) {
1399 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1400 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1401 exports_ps |= 1;
1402 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1403 num_cout++;
1404 }
1405 }
1406 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1407 if (!exports_ps) {
1408 /* always at least export 1 component per pixel */
1409 exports_ps = 2;
1410 }
1411
1412 if (ninterp == 0) {
1413 ninterp = 1;
1414 have_perspective = TRUE;
1415 }
1416
1417 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
1418 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
1419 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
1420 spi_input_z = 0;
1421 if (pos_index != -1) {
1422 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
1423 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1424 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
1425 spi_input_z |= 1;
1426 }
1427
1428 spi_ps_in_control_1 = 0;
1429 if (face_index != -1) {
1430 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1431 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1432 }
1433
1434 spi_baryc_cntl = 0;
1435 if (have_perspective)
1436 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
1437 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
1438 if (have_linear)
1439 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
1440 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
1441
1442 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1443 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1444 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1445 spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1446 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
1447 0, 0xFFFFFFFF, NULL);
1448 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1449 r600_pipe_state_add_reg(rstate,
1450 R_0286E0_SPI_BARYC_CNTL,
1451 spi_baryc_cntl,
1452 0xFFFFFFFF, NULL);
1453
1454 r600_pipe_state_add_reg(rstate,
1455 R_028840_SQ_PGM_START_PS,
1456 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1457 r600_pipe_state_add_reg(rstate,
1458 R_028844_SQ_PGM_RESOURCES_PS,
1459 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1460 S_028844_PRIME_CACHE_ON_DRAW(1) |
1461 S_028844_STACK_SIZE(rshader->bc.nstack),
1462 0xFFFFFFFF, NULL);
1463 r600_pipe_state_add_reg(rstate,
1464 R_028848_SQ_PGM_RESOURCES_2_PS,
1465 0x0, 0xFFFFFFFF, NULL);
1466 r600_pipe_state_add_reg(rstate,
1467 R_02884C_SQ_PGM_EXPORTS_PS,
1468 exports_ps, 0xFFFFFFFF, NULL);
1469 /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */
1470 /* only set some bits here, the other bits are set in the dsa state */
1471 r600_pipe_state_add_reg(rstate,
1472 R_02880C_DB_SHADER_CONTROL,
1473 db_shader_control,
1474 S_02880C_Z_EXPORT_ENABLE(1) |
1475 S_02880C_STENCIL_EXPORT_ENABLE(1) |
1476 S_02880C_KILL_ENABLE(1),
1477 NULL);
1478 r600_pipe_state_add_reg(rstate,
1479 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
1480 0xFFFFFFFF, NULL);
1481 }
1482
1483 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1484 {
1485 struct r600_pipe_state *rstate = &shader->rstate;
1486 struct r600_shader *rshader = &shader->shader;
1487 unsigned spi_vs_out_id[10];
1488 unsigned i, tmp;
1489
1490 /* clear previous register */
1491 rstate->nregs = 0;
1492
1493 /* so far never got proper semantic id from tgsi */
1494 for (i = 0; i < 10; i++) {
1495 spi_vs_out_id[i] = 0;
1496 }
1497 for (i = 0; i < 32; i++) {
1498 tmp = i << ((i & 3) * 8);
1499 spi_vs_out_id[i / 4] |= tmp;
1500 }
1501 for (i = 0; i < 10; i++) {
1502 r600_pipe_state_add_reg(rstate,
1503 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1504 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1505 }
1506
1507 r600_pipe_state_add_reg(rstate,
1508 R_0286C4_SPI_VS_OUT_CONFIG,
1509 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1510 0xFFFFFFFF, NULL);
1511 r600_pipe_state_add_reg(rstate,
1512 R_028860_SQ_PGM_RESOURCES_VS,
1513 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1514 S_028860_STACK_SIZE(rshader->bc.nstack),
1515 0xFFFFFFFF, NULL);
1516 r600_pipe_state_add_reg(rstate,
1517 R_028864_SQ_PGM_RESOURCES_2_VS,
1518 0x0, 0xFFFFFFFF, NULL);
1519 r600_pipe_state_add_reg(rstate,
1520 R_02885C_SQ_PGM_START_VS,
1521 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1522
1523 r600_pipe_state_add_reg(rstate,
1524 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1525 0xFFFFFFFF, NULL);
1526 }
1527
1528 void evergreen_fetch_shader(struct r600_vertex_element *ve)
1529 {
1530 struct r600_pipe_state *rstate = &ve->rstate;
1531 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1532 rstate->nregs = 0;
1533 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
1534 0x00000000, 0xFFFFFFFF, NULL);
1535 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
1536 (r600_bo_offset(ve->fetch_shader)) >> 8,
1537 0xFFFFFFFF, ve->fetch_shader);
1538 }
1539
1540 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1541 {
1542 struct pipe_depth_stencil_alpha_state dsa;
1543 struct r600_pipe_state *rstate;
1544
1545 memset(&dsa, 0, sizeof(dsa));
1546
1547 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1548 r600_pipe_state_add_reg(rstate,
1549 R_02880C_DB_SHADER_CONTROL,
1550 0x0,
1551 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1552 r600_pipe_state_add_reg(rstate,
1553 R_028000_DB_RENDER_CONTROL,
1554 S_028000_DEPTH_COPY_ENABLE(1) |
1555 S_028000_STENCIL_COPY_ENABLE(1) |
1556 S_028000_COPY_CENTROID(1),
1557 S_028000_DEPTH_COPY_ENABLE(1) |
1558 S_028000_STENCIL_COPY_ENABLE(1) |
1559 S_028000_COPY_CENTROID(1), NULL);
1560 return rstate;
1561 }
1562
1563 void evergreen_pipe_set_buffer_resource(struct r600_pipe_context *rctx,
1564 struct r600_pipe_state *rstate,
1565 struct r600_resource *rbuffer,
1566 unsigned offset, unsigned stride)
1567 {
1568 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
1569 offset, 0xFFFFFFFF, rbuffer->bo);
1570 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
1571 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
1572 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
1573 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1574 S_030008_STRIDE(stride), 0xFFFFFFFF, NULL);
1575 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
1576 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1577 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1578 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1579 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W),
1580 0xFFFFFFFF, NULL);
1581 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
1582 0x00000000, 0xFFFFFFFF, NULL);
1583 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
1584 0x00000000, 0xFFFFFFFF, NULL);
1585 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
1586 0x00000000, 0xFFFFFFFF, NULL);
1587 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
1588 0xC0000000, 0xFFFFFFFF, NULL);
1589 }