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r600/eg: fix buffer sizing.
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600_query.h"
26 #include "evergreend.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_memory.h"
31 #include "util/u_framebuffer.h"
32 #include "util/u_dual_blend.h"
33 #include "evergreen_compute.h"
34 #include "util/u_math.h"
35
36 static inline unsigned evergreen_array_mode(unsigned mode)
37 {
38 switch (mode) {
39 default:
40 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
41 break;
42 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
43 break;
44 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
45 }
46 }
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(struct r600_texture *rtex,
174 unsigned view_target, unsigned nr_samples)
175 {
176 unsigned res_target = rtex->resource.b.b.target;
177
178 if (view_target == PIPE_TEXTURE_CUBE ||
179 view_target == PIPE_TEXTURE_CUBE_ARRAY)
180 res_target = view_target;
181 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
182 else if (res_target == PIPE_TEXTURE_CUBE ||
183 res_target == PIPE_TEXTURE_CUBE_ARRAY)
184 res_target = PIPE_TEXTURE_2D_ARRAY;
185
186 switch (res_target) {
187 default:
188 case PIPE_TEXTURE_1D:
189 return V_030000_SQ_TEX_DIM_1D;
190 case PIPE_TEXTURE_1D_ARRAY:
191 return V_030000_SQ_TEX_DIM_1D_ARRAY;
192 case PIPE_TEXTURE_2D:
193 case PIPE_TEXTURE_RECT:
194 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
195 V_030000_SQ_TEX_DIM_2D;
196 case PIPE_TEXTURE_2D_ARRAY:
197 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
198 V_030000_SQ_TEX_DIM_2D_ARRAY;
199 case PIPE_TEXTURE_3D:
200 return V_030000_SQ_TEX_DIM_3D;
201 case PIPE_TEXTURE_CUBE:
202 case PIPE_TEXTURE_CUBE_ARRAY:
203 return V_030000_SQ_TEX_DIM_CUBEMAP;
204 }
205 }
206
207 static uint32_t r600_translate_dbformat(enum pipe_format format)
208 {
209 switch (format) {
210 case PIPE_FORMAT_Z16_UNORM:
211 return V_028040_Z_16;
212 case PIPE_FORMAT_Z24X8_UNORM:
213 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
214 case PIPE_FORMAT_X8Z24_UNORM:
215 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
216 return V_028040_Z_24;
217 case PIPE_FORMAT_Z32_FLOAT:
218 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
219 return V_028040_Z_32_FLOAT;
220 default:
221 return ~0U;
222 }
223 }
224
225 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
226 {
227 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
228 FALSE) != ~0U;
229 }
230
231 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
232 {
233 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
234 r600_translate_colorswap(format, FALSE) != ~0U;
235 }
236
237 static bool r600_is_zs_format_supported(enum pipe_format format)
238 {
239 return r600_translate_dbformat(format) != ~0U;
240 }
241
242 boolean evergreen_is_format_supported(struct pipe_screen *screen,
243 enum pipe_format format,
244 enum pipe_texture_target target,
245 unsigned sample_count,
246 unsigned usage)
247 {
248 struct r600_screen *rscreen = (struct r600_screen*)screen;
249 unsigned retval = 0;
250
251 if (target >= PIPE_MAX_TEXTURE_TYPES) {
252 R600_ERR("r600: unsupported texture type %d\n", target);
253 return FALSE;
254 }
255
256 if (!util_format_is_supported(format, usage))
257 return FALSE;
258
259 if (sample_count > 1) {
260 if (!rscreen->has_msaa)
261 return FALSE;
262
263 switch (sample_count) {
264 case 2:
265 case 4:
266 case 8:
267 break;
268 default:
269 return FALSE;
270 }
271 }
272
273 if (usage & PIPE_BIND_SAMPLER_VIEW) {
274 if (target == PIPE_BUFFER) {
275 if (r600_is_vertex_format_supported(format))
276 retval |= PIPE_BIND_SAMPLER_VIEW;
277 } else {
278 if (r600_is_sampler_format_supported(screen, format))
279 retval |= PIPE_BIND_SAMPLER_VIEW;
280 }
281 }
282
283 if ((usage & (PIPE_BIND_RENDER_TARGET |
284 PIPE_BIND_DISPLAY_TARGET |
285 PIPE_BIND_SCANOUT |
286 PIPE_BIND_SHARED |
287 PIPE_BIND_BLENDABLE)) &&
288 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
289 retval |= usage &
290 (PIPE_BIND_RENDER_TARGET |
291 PIPE_BIND_DISPLAY_TARGET |
292 PIPE_BIND_SCANOUT |
293 PIPE_BIND_SHARED);
294 if (!util_format_is_pure_integer(format) &&
295 !util_format_is_depth_or_stencil(format))
296 retval |= usage & PIPE_BIND_BLENDABLE;
297 }
298
299 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
300 r600_is_zs_format_supported(format)) {
301 retval |= PIPE_BIND_DEPTH_STENCIL;
302 }
303
304 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
305 r600_is_vertex_format_supported(format)) {
306 retval |= PIPE_BIND_VERTEX_BUFFER;
307 }
308
309 if ((usage & PIPE_BIND_LINEAR) &&
310 !util_format_is_compressed(format) &&
311 !(usage & PIPE_BIND_DEPTH_STENCIL))
312 retval |= PIPE_BIND_LINEAR;
313
314 return retval == usage;
315 }
316
317 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
318 const struct pipe_blend_state *state, int mode)
319 {
320 uint32_t color_control = 0, target_mask = 0;
321 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
322
323 if (!blend) {
324 return NULL;
325 }
326
327 r600_init_command_buffer(&blend->buffer, 20);
328 r600_init_command_buffer(&blend->buffer_no_blend, 20);
329
330 if (state->logicop_enable) {
331 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
332 } else {
333 color_control |= (0xcc << 16);
334 }
335 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
336 if (state->independent_blend_enable) {
337 for (int i = 0; i < 8; i++) {
338 target_mask |= (state->rt[i].colormask << (4 * i));
339 }
340 } else {
341 for (int i = 0; i < 8; i++) {
342 target_mask |= (state->rt[0].colormask << (4 * i));
343 }
344 }
345
346 /* only have dual source on MRT0 */
347 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
348 blend->cb_target_mask = target_mask;
349 blend->alpha_to_one = state->alpha_to_one;
350
351 if (target_mask)
352 color_control |= S_028808_MODE(mode);
353 else
354 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
355
356
357 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
358 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
359 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
360 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
361 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
362 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
363 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
364 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
365
366 /* Copy over the dwords set so far into buffer_no_blend.
367 * Only the CB_BLENDi_CONTROL registers must be set after this. */
368 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
369 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
370
371 for (int i = 0; i < 8; i++) {
372 /* state->rt entries > 0 only written if independent blending */
373 const int j = state->independent_blend_enable ? i : 0;
374
375 unsigned eqRGB = state->rt[j].rgb_func;
376 unsigned srcRGB = state->rt[j].rgb_src_factor;
377 unsigned dstRGB = state->rt[j].rgb_dst_factor;
378 unsigned eqA = state->rt[j].alpha_func;
379 unsigned srcA = state->rt[j].alpha_src_factor;
380 unsigned dstA = state->rt[j].alpha_dst_factor;
381 uint32_t bc = 0;
382
383 r600_store_value(&blend->buffer_no_blend, 0);
384
385 if (!state->rt[j].blend_enable) {
386 r600_store_value(&blend->buffer, 0);
387 continue;
388 }
389
390 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
391 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
392 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
393 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
394
395 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
396 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
397 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
398 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
399 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
400 }
401 r600_store_value(&blend->buffer, bc);
402 }
403 return blend;
404 }
405
406 static void *evergreen_create_blend_state(struct pipe_context *ctx,
407 const struct pipe_blend_state *state)
408 {
409
410 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
411 }
412
413 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
414 const struct pipe_depth_stencil_alpha_state *state)
415 {
416 unsigned db_depth_control, alpha_test_control, alpha_ref;
417 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
418
419 if (!dsa) {
420 return NULL;
421 }
422
423 r600_init_command_buffer(&dsa->buffer, 3);
424
425 dsa->valuemask[0] = state->stencil[0].valuemask;
426 dsa->valuemask[1] = state->stencil[1].valuemask;
427 dsa->writemask[0] = state->stencil[0].writemask;
428 dsa->writemask[1] = state->stencil[1].writemask;
429 dsa->zwritemask = state->depth.writemask;
430
431 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
432 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
433 S_028800_ZFUNC(state->depth.func);
434
435 /* stencil */
436 if (state->stencil[0].enabled) {
437 db_depth_control |= S_028800_STENCIL_ENABLE(1);
438 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
439 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
440 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
441 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
442
443 if (state->stencil[1].enabled) {
444 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
445 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
446 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
447 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
448 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
449 }
450 }
451
452 /* alpha */
453 alpha_test_control = 0;
454 alpha_ref = 0;
455 if (state->alpha.enabled) {
456 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
457 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
458 alpha_ref = fui(state->alpha.ref_value);
459 }
460 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
461 dsa->alpha_ref = alpha_ref;
462
463 /* misc */
464 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
465 return dsa;
466 }
467
468 static void *evergreen_create_rs_state(struct pipe_context *ctx,
469 const struct pipe_rasterizer_state *state)
470 {
471 struct r600_context *rctx = (struct r600_context *)ctx;
472 unsigned tmp, spi_interp;
473 float psize_min, psize_max;
474 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
475
476 if (!rs) {
477 return NULL;
478 }
479
480 r600_init_command_buffer(&rs->buffer, 30);
481
482 rs->scissor_enable = state->scissor;
483 rs->clip_halfz = state->clip_halfz;
484 rs->flatshade = state->flatshade;
485 rs->sprite_coord_enable = state->sprite_coord_enable;
486 rs->rasterizer_discard = state->rasterizer_discard;
487 rs->two_side = state->light_twoside;
488 rs->clip_plane_enable = state->clip_plane_enable;
489 rs->pa_sc_line_stipple = state->line_stipple_enable ?
490 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
491 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
492 rs->pa_cl_clip_cntl =
493 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
494 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
495 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
496 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
497 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
498 rs->multisample_enable = state->multisample;
499
500 /* offset */
501 rs->offset_units = state->offset_units;
502 rs->offset_scale = state->offset_scale * 16.0f;
503 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
504 rs->offset_units_unscaled = state->offset_units_unscaled;
505
506 if (state->point_size_per_vertex) {
507 psize_min = util_get_min_point_size(state);
508 psize_max = 8192;
509 } else {
510 /* Force the point size to be as if the vertex output was disabled. */
511 psize_min = state->point_size;
512 psize_max = state->point_size;
513 }
514
515 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
516 if (state->sprite_coord_enable) {
517 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
518 S_0286D4_PNT_SPRITE_OVRD_X(2) |
519 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
520 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
521 S_0286D4_PNT_SPRITE_OVRD_W(1);
522 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
523 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
524 }
525 }
526
527 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
528 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
529 tmp = r600_pack_float_12p4(state->point_size/2);
530 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
531 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
532 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
533 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
534 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
535 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
536 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
537
538 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
539 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
540 S_028A48_MSAA_ENABLE(state->multisample) |
541 S_028A48_VPORT_SCISSOR_ENABLE(1) |
542 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
543
544 if (rctx->b.chip_class == CAYMAN) {
545 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
546 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
547 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
548 } else {
549 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
550 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
551 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
552 }
553
554 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
555 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
556 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
557 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
558 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
559 S_028814_FACE(!state->front_ccw) |
560 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
561 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
562 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
563 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
564 state->fill_back != PIPE_POLYGON_MODE_FILL) |
565 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
566 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
567 return rs;
568 }
569
570 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
571 const struct pipe_sampler_state *state)
572 {
573 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
574 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
575 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
576 : state->max_anisotropy;
577 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
578
579 if (!ss) {
580 return NULL;
581 }
582
583 ss->border_color_use = sampler_state_needs_border_color(state);
584
585 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
586 ss->tex_sampler_words[0] =
587 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
588 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
589 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
590 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
591 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
592 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
593 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
594 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
595 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
596 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
597 ss->tex_sampler_words[1] =
598 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
599 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
600 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
601 ss->tex_sampler_words[2] =
602 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
603 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
604 S_03C008_TYPE(1);
605
606 if (ss->border_color_use) {
607 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
608 }
609 return ss;
610 }
611
612 struct eg_buf_res_params {
613 enum pipe_format pipe_format;
614 unsigned offset;
615 unsigned size;
616 unsigned char swizzle[4];
617 bool uncached;
618 bool force_swizzle;
619 bool size_in_bytes;
620 };
621
622 static void evergreen_fill_buffer_resource_words(struct r600_context *rctx,
623 struct pipe_resource *buffer,
624 struct eg_buf_res_params *params,
625 bool *skip_mip_address_reloc,
626 unsigned tex_resource_words[8])
627 {
628 struct r600_texture *tmp = (struct r600_texture*)buffer;
629 uint64_t va;
630 int stride = util_format_get_blocksize(params->pipe_format);
631 unsigned format, num_format, format_comp, endian;
632 unsigned swizzle_res;
633 const struct util_format_description *desc;
634
635 r600_vertex_data_type(params->pipe_format,
636 &format, &num_format, &format_comp,
637 &endian);
638
639 desc = util_format_description(params->pipe_format);
640
641 if (params->force_swizzle)
642 swizzle_res = r600_get_swizzle_combined(params->swizzle, NULL, TRUE);
643 else
644 swizzle_res = r600_get_swizzle_combined(desc->swizzle, params->swizzle, TRUE);
645
646 va = tmp->resource.gpu_address + params->offset;
647 *skip_mip_address_reloc = true;
648 tex_resource_words[0] = va;
649 tex_resource_words[1] = params->size - 1;
650 tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
651 S_030008_STRIDE(stride) |
652 S_030008_DATA_FORMAT(format) |
653 S_030008_NUM_FORMAT_ALL(num_format) |
654 S_030008_FORMAT_COMP_ALL(format_comp) |
655 S_030008_ENDIAN_SWAP(endian);
656 tex_resource_words[3] = swizzle_res | S_03000C_UNCACHED(params->uncached);
657 /*
658 * dword 4 is for number of elements, for use with resinfo,
659 * albeit the amd gpu shader analyser
660 * uses a const buffer to store the element sizes for buffer txq
661 */
662 tex_resource_words[4] = params->size_in_bytes ? params->size : (params->size / stride);
663
664 tex_resource_words[5] = tex_resource_words[6] = 0;
665 tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
666 }
667
668 static struct pipe_sampler_view *
669 texture_buffer_sampler_view(struct r600_context *rctx,
670 struct r600_pipe_sampler_view *view,
671 unsigned width0, unsigned height0)
672 {
673 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
674 struct eg_buf_res_params params;
675
676 memset(&params, 0, sizeof(params));
677
678 params.pipe_format = view->base.format;
679 params.offset = view->base.u.buf.offset;
680 params.size = view->base.u.buf.size;
681 params.swizzle[0] = view->base.swizzle_r;
682 params.swizzle[1] = view->base.swizzle_g;
683 params.swizzle[2] = view->base.swizzle_b;
684 params.swizzle[3] = view->base.swizzle_a;
685
686 evergreen_fill_buffer_resource_words(rctx, view->base.texture,
687 &params, &view->skip_mip_address_reloc,
688 view->tex_resource_words);
689 view->tex_resource = &tmp->resource;
690
691 if (tmp->resource.gpu_address)
692 LIST_ADDTAIL(&view->list, &rctx->texture_buffers);
693 return &view->base;
694 }
695
696 struct eg_tex_res_params {
697 enum pipe_format pipe_format;
698 int force_level;
699 unsigned width0;
700 unsigned height0;
701 unsigned first_level;
702 unsigned last_level;
703 unsigned first_layer;
704 unsigned last_layer;
705 unsigned target;
706 unsigned char swizzle[4];
707 };
708
709 static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
710 struct pipe_resource *texture,
711 struct eg_tex_res_params *params,
712 bool *skip_mip_address_reloc,
713 unsigned tex_resource_words[8])
714 {
715 struct r600_screen *rscreen = (struct r600_screen*)rctx->b.b.screen;
716 struct r600_texture *tmp = (struct r600_texture*)texture;
717 unsigned format, endian;
718 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
719 unsigned char array_mode = 0, non_disp_tiling = 0;
720 unsigned height, depth, width;
721 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
722 struct legacy_surf_level *surflevel;
723 unsigned base_level, first_level, last_level;
724 unsigned dim, last_layer;
725 uint64_t va;
726 bool do_endian_swap = FALSE;
727
728 tile_split = tmp->surface.u.legacy.tile_split;
729 surflevel = tmp->surface.u.legacy.level;
730
731 /* Texturing with separate depth and stencil. */
732 if (tmp->db_compatible) {
733 switch (params->pipe_format) {
734 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
735 params->pipe_format = PIPE_FORMAT_Z32_FLOAT;
736 break;
737 case PIPE_FORMAT_X8Z24_UNORM:
738 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
739 /* Z24 is always stored like this for DB
740 * compatibility.
741 */
742 params->pipe_format = PIPE_FORMAT_Z24X8_UNORM;
743 break;
744 case PIPE_FORMAT_X24S8_UINT:
745 case PIPE_FORMAT_S8X24_UINT:
746 case PIPE_FORMAT_X32_S8X24_UINT:
747 params->pipe_format = PIPE_FORMAT_S8_UINT;
748 tile_split = tmp->surface.u.legacy.stencil_tile_split;
749 surflevel = tmp->surface.u.legacy.stencil_level;
750 break;
751 default:;
752 }
753 }
754
755 if (R600_BIG_ENDIAN)
756 do_endian_swap = !tmp->db_compatible;
757
758 format = r600_translate_texformat(rctx->b.b.screen, params->pipe_format,
759 params->swizzle,
760 &word4, &yuv_format, do_endian_swap);
761 assert(format != ~0);
762 if (format == ~0) {
763 return -1;
764 }
765
766 endian = r600_colorformat_endian_swap(format, do_endian_swap);
767
768 base_level = 0;
769 first_level = params->first_level;
770 last_level = params->last_level;
771 width = params->width0;
772 height = params->height0;
773 depth = texture->depth0;
774
775 if (params->force_level) {
776 base_level = params->force_level;
777 first_level = 0;
778 last_level = 0;
779 width = u_minify(width, params->force_level);
780 height = u_minify(height, params->force_level);
781 depth = u_minify(depth, params->force_level);
782 }
783
784 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(params->pipe_format);
785 non_disp_tiling = tmp->non_disp_tiling;
786
787 switch (surflevel[base_level].mode) {
788 default:
789 case RADEON_SURF_MODE_LINEAR_ALIGNED:
790 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
791 break;
792 case RADEON_SURF_MODE_2D:
793 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
794 break;
795 case RADEON_SURF_MODE_1D:
796 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
797 break;
798 }
799 macro_aspect = tmp->surface.u.legacy.mtilea;
800 bankw = tmp->surface.u.legacy.bankw;
801 bankh = tmp->surface.u.legacy.bankh;
802 tile_split = eg_tile_split(tile_split);
803 macro_aspect = eg_macro_tile_aspect(macro_aspect);
804 bankw = eg_bank_wh(bankw);
805 bankh = eg_bank_wh(bankh);
806 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
807
808 /* 128 bit formats require tile type = 1 */
809 if (rscreen->b.chip_class == CAYMAN) {
810 if (util_format_get_blocksize(params->pipe_format) >= 16)
811 non_disp_tiling = 1;
812 }
813 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
814
815
816 va = tmp->resource.gpu_address;
817
818 /* array type views and views into array types need to use layer offset */
819 dim = r600_tex_dim(tmp, params->target, texture->nr_samples);
820
821 if (dim == V_030000_SQ_TEX_DIM_1D_ARRAY) {
822 height = 1;
823 depth = texture->array_size;
824 } else if (dim == V_030000_SQ_TEX_DIM_2D_ARRAY ||
825 dim == V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA) {
826 depth = texture->array_size;
827 } else if (dim == V_030000_SQ_TEX_DIM_CUBEMAP)
828 depth = texture->array_size / 6;
829
830 tex_resource_words[0] = (S_030000_DIM(dim) |
831 S_030000_PITCH((pitch / 8) - 1) |
832 S_030000_TEX_WIDTH(width - 1));
833 if (rscreen->b.chip_class == CAYMAN)
834 tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
835 else
836 tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
837 tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
838 S_030004_TEX_DEPTH(depth - 1) |
839 S_030004_ARRAY_MODE(array_mode));
840 tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
841
842 *skip_mip_address_reloc = false;
843 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
844 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
845 if (tmp->is_depth) {
846 /* disable FMASK (0 = disabled) */
847 tex_resource_words[3] = 0;
848 *skip_mip_address_reloc = true;
849 } else {
850 /* FMASK should be in MIP_ADDRESS for multisample textures */
851 tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
852 }
853 } else if (last_level && texture->nr_samples <= 1) {
854 tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
855 } else {
856 tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
857 }
858
859 last_layer = params->last_layer;
860 if (params->target != texture->target && depth == 1) {
861 last_layer = params->first_layer;
862 }
863 tex_resource_words[4] = (word4 |
864 S_030010_ENDIAN_SWAP(endian));
865 tex_resource_words[5] = S_030014_BASE_ARRAY(params->first_layer) |
866 S_030014_LAST_ARRAY(last_layer);
867 tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
868
869 if (texture->nr_samples > 1) {
870 unsigned log_samples = util_logbase2(texture->nr_samples);
871 if (rscreen->b.chip_class == CAYMAN) {
872 tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
873 }
874 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
875 tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
876 tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
877 } else {
878 bool no_mip = first_level == last_level;
879
880 tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
881 tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
882 /* aniso max 16 samples */
883 tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
884 }
885
886 tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
887 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
888 S_03001C_BANK_WIDTH(bankw) |
889 S_03001C_BANK_HEIGHT(bankh) |
890 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
891 S_03001C_NUM_BANKS(nbanks) |
892 S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible);
893 return 0;
894 }
895
896 struct pipe_sampler_view *
897 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
898 struct pipe_resource *texture,
899 const struct pipe_sampler_view *state,
900 unsigned width0, unsigned height0,
901 unsigned force_level)
902 {
903 struct r600_context *rctx = (struct r600_context*)ctx;
904 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
905 struct r600_texture *tmp = (struct r600_texture*)texture;
906 struct eg_tex_res_params params;
907 int ret;
908
909 if (!view)
910 return NULL;
911
912 /* initialize base object */
913 view->base = *state;
914 view->base.texture = NULL;
915 pipe_reference(NULL, &texture->reference);
916 view->base.texture = texture;
917 view->base.reference.count = 1;
918 view->base.context = ctx;
919
920 if (state->target == PIPE_BUFFER)
921 return texture_buffer_sampler_view(rctx, view, width0, height0);
922
923 memset(&params, 0, sizeof(params));
924 params.pipe_format = state->format;
925 params.force_level = force_level;
926 params.width0 = width0;
927 params.height0 = height0;
928 params.first_level = state->u.tex.first_level;
929 params.last_level = state->u.tex.last_level;
930 params.first_layer = state->u.tex.first_layer;
931 params.last_layer = state->u.tex.last_layer;
932 params.target = state->target;
933 params.swizzle[0] = state->swizzle_r;
934 params.swizzle[1] = state->swizzle_g;
935 params.swizzle[2] = state->swizzle_b;
936 params.swizzle[3] = state->swizzle_a;
937
938 ret = evergreen_fill_tex_resource_words(rctx, texture, &params,
939 &view->skip_mip_address_reloc,
940 view->tex_resource_words);
941 if (ret != 0) {
942 FREE(view);
943 return NULL;
944 }
945
946 if (state->format == PIPE_FORMAT_X24S8_UINT ||
947 state->format == PIPE_FORMAT_S8X24_UINT ||
948 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
949 state->format == PIPE_FORMAT_S8_UINT)
950 view->is_stencil_sampler = true;
951
952 view->tex_resource = &tmp->resource;
953
954 return &view->base;
955 }
956
957 static struct pipe_sampler_view *
958 evergreen_create_sampler_view(struct pipe_context *ctx,
959 struct pipe_resource *tex,
960 const struct pipe_sampler_view *state)
961 {
962 return evergreen_create_sampler_view_custom(ctx, tex, state,
963 tex->width0, tex->height0, 0);
964 }
965
966 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
967 {
968 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
969 struct r600_config_state *a = (struct r600_config_state*)atom;
970
971 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
972 if (a->dyn_gpr_enabled) {
973 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
974 radeon_emit(cs, 0);
975 radeon_emit(cs, 0);
976 } else {
977 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
978 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
979 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
980 }
981 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
982 if (a->dyn_gpr_enabled) {
983 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
984 S_028838_PS_GPRS(0x1e) |
985 S_028838_VS_GPRS(0x1e) |
986 S_028838_GS_GPRS(0x1e) |
987 S_028838_ES_GPRS(0x1e) |
988 S_028838_HS_GPRS(0x1e) |
989 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
990 }
991 }
992
993 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
994 {
995 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
996 struct pipe_clip_state *state = &rctx->clip_state.state;
997
998 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
999 radeon_emit_array(cs, (unsigned*)state, 6*4);
1000 }
1001
1002 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1003 const struct pipe_poly_stipple *state)
1004 {
1005 }
1006
1007 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1008 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1009 uint32_t *tl, uint32_t *br)
1010 {
1011 struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
1012
1013 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
1014
1015 *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
1016 *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
1017 }
1018
1019 struct r600_tex_color_info {
1020 unsigned info;
1021 unsigned view;
1022 unsigned dim;
1023 unsigned pitch;
1024 unsigned slice;
1025 unsigned attrib;
1026 unsigned ntype;
1027 unsigned fmask;
1028 unsigned fmask_slice;
1029 uint64_t offset;
1030 boolean export_16bpc;
1031 };
1032
1033 static void evergreen_set_color_surface_buffer(struct r600_context *rctx,
1034 struct r600_resource *res,
1035 enum pipe_format pformat,
1036 unsigned first_element,
1037 unsigned last_element,
1038 struct r600_tex_color_info *color)
1039 {
1040 unsigned format, swap, ntype, endian;
1041 const struct util_format_description *desc;
1042 unsigned block_size = util_format_get_blocksize(res->b.b.format);
1043 unsigned pitch_alignment =
1044 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
1045 unsigned pitch = align(res->b.b.width0, pitch_alignment);
1046 int i;
1047 unsigned width_elements;
1048
1049 width_elements = last_element - first_element + 1;
1050
1051 format = r600_translate_colorformat(rctx->b.chip_class, pformat, FALSE);
1052 swap = r600_translate_colorswap(pformat, FALSE);
1053
1054 endian = r600_colorformat_endian_swap(format, FALSE);
1055
1056 desc = util_format_description(pformat);
1057 for (i = 0; i < 4; i++) {
1058 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1059 break;
1060 }
1061 }
1062 ntype = V_028C70_NUMBER_UNORM;
1063 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1064 ntype = V_028C70_NUMBER_SRGB;
1065 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1066 if (desc->channel[i].normalized)
1067 ntype = V_028C70_NUMBER_SNORM;
1068 else if (desc->channel[i].pure_integer)
1069 ntype = V_028C70_NUMBER_SINT;
1070 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1071 if (desc->channel[i].normalized)
1072 ntype = V_028C70_NUMBER_UNORM;
1073 else if (desc->channel[i].pure_integer)
1074 ntype = V_028C70_NUMBER_UINT;
1075 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1076 ntype = V_028C70_NUMBER_FLOAT;
1077 }
1078
1079 pitch = (pitch / 8) - 1;
1080 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1081
1082 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1083 color->info |= S_028C70_FORMAT(format) |
1084 S_028C70_COMP_SWAP(swap) |
1085 S_028C70_BLEND_CLAMP(0) |
1086 S_028C70_BLEND_BYPASS(1) |
1087 S_028C70_NUMBER_TYPE(ntype) |
1088 S_028C70_ENDIAN(endian);
1089 color->attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1090 color->ntype = ntype;
1091 color->export_16bpc = false;
1092 color->dim = width_elements - 1;
1093 color->slice = 0; /* (width_elements / 64) - 1;*/
1094 color->view = 0;
1095 color->offset = (res->gpu_address + first_element) >> 8;
1096
1097 color->fmask = color->offset;
1098 color->fmask_slice = 0;
1099 }
1100
1101 static void evergreen_set_color_surface_common(struct r600_context *rctx,
1102 struct r600_texture *rtex,
1103 unsigned level,
1104 unsigned first_layer,
1105 unsigned last_layer,
1106 enum pipe_format pformat,
1107 struct r600_tex_color_info *color)
1108 {
1109 struct r600_screen *rscreen = rctx->screen;
1110 unsigned pitch, slice;
1111 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1112 unsigned format, swap, ntype, endian;
1113 const struct util_format_description *desc;
1114 bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
1115 int i;
1116
1117 color->offset = rtex->surface.u.legacy.level[level].offset;
1118 color->view = S_028C6C_SLICE_START(first_layer) |
1119 S_028C6C_SLICE_MAX(last_layer);
1120
1121 color->offset += rtex->resource.gpu_address;
1122 color->offset >>= 8;
1123
1124 color->dim = 0;
1125 pitch = (rtex->surface.u.legacy.level[level].nblk_x) / 8 - 1;
1126 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1127 if (slice) {
1128 slice = slice - 1;
1129 }
1130
1131 color->info = 0;
1132 switch (rtex->surface.u.legacy.level[level].mode) {
1133 default:
1134 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1135 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1136 non_disp_tiling = 1;
1137 break;
1138 case RADEON_SURF_MODE_1D:
1139 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1140 non_disp_tiling = rtex->non_disp_tiling;
1141 break;
1142 case RADEON_SURF_MODE_2D:
1143 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1144 non_disp_tiling = rtex->non_disp_tiling;
1145 break;
1146 }
1147 tile_split = rtex->surface.u.legacy.tile_split;
1148 macro_aspect = rtex->surface.u.legacy.mtilea;
1149 bankw = rtex->surface.u.legacy.bankw;
1150 bankh = rtex->surface.u.legacy.bankh;
1151 if (rtex->fmask.size)
1152 fmask_bankh = rtex->fmask.bank_height;
1153 else
1154 fmask_bankh = rtex->surface.u.legacy.bankh;
1155 tile_split = eg_tile_split(tile_split);
1156 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1157 bankw = eg_bank_wh(bankw);
1158 bankh = eg_bank_wh(bankh);
1159 fmask_bankh = eg_bank_wh(fmask_bankh);
1160
1161 if (rscreen->b.chip_class == CAYMAN) {
1162 if (util_format_get_blocksize(pformat) >= 16)
1163 non_disp_tiling = 1;
1164 }
1165 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1166 desc = util_format_description(pformat);
1167 for (i = 0; i < 4; i++) {
1168 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1169 break;
1170 }
1171 }
1172 color->attrib = S_028C74_TILE_SPLIT(tile_split)|
1173 S_028C74_NUM_BANKS(nbanks) |
1174 S_028C74_BANK_WIDTH(bankw) |
1175 S_028C74_BANK_HEIGHT(bankh) |
1176 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1177 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1178 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1179
1180 if (rctx->b.chip_class == CAYMAN) {
1181 color->attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1182 PIPE_SWIZZLE_1);
1183
1184 if (rtex->resource.b.b.nr_samples > 1) {
1185 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1186 color->attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1187 S_028C74_NUM_FRAGMENTS(log_samples);
1188 }
1189 }
1190
1191 ntype = V_028C70_NUMBER_UNORM;
1192 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1193 ntype = V_028C70_NUMBER_SRGB;
1194 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1195 if (desc->channel[i].normalized)
1196 ntype = V_028C70_NUMBER_SNORM;
1197 else if (desc->channel[i].pure_integer)
1198 ntype = V_028C70_NUMBER_SINT;
1199 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1200 if (desc->channel[i].normalized)
1201 ntype = V_028C70_NUMBER_UNORM;
1202 else if (desc->channel[i].pure_integer)
1203 ntype = V_028C70_NUMBER_UINT;
1204 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1205 ntype = V_028C70_NUMBER_FLOAT;
1206 }
1207
1208 if (R600_BIG_ENDIAN)
1209 do_endian_swap = !rtex->db_compatible;
1210
1211 format = r600_translate_colorformat(rctx->b.chip_class, pformat, do_endian_swap);
1212 assert(format != ~0);
1213 swap = r600_translate_colorswap(pformat, do_endian_swap);
1214 assert(swap != ~0);
1215
1216 endian = r600_colorformat_endian_swap(format, do_endian_swap);
1217
1218 /* blend clamp should be set for all NORM/SRGB types */
1219 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1220 ntype == V_028C70_NUMBER_SRGB)
1221 blend_clamp = 1;
1222
1223 /* set blend bypass according to docs if SINT/UINT or
1224 8/24 COLOR variants */
1225 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1226 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1227 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1228 blend_clamp = 0;
1229 blend_bypass = 1;
1230 }
1231
1232 color->ntype = ntype;
1233 color->info |= S_028C70_FORMAT(format) |
1234 S_028C70_COMP_SWAP(swap) |
1235 S_028C70_BLEND_CLAMP(blend_clamp) |
1236 S_028C70_BLEND_BYPASS(blend_bypass) |
1237 S_028C70_SIMPLE_FLOAT(1) |
1238 S_028C70_NUMBER_TYPE(ntype) |
1239 S_028C70_ENDIAN(endian);
1240
1241 if (rtex->fmask.size) {
1242 color->info |= S_028C70_COMPRESSION(1);
1243 }
1244
1245 /* EXPORT_NORM is an optimzation that can be enabled for better
1246 * performance in certain cases.
1247 * EXPORT_NORM can be enabled if:
1248 * - 11-bit or smaller UNORM/SNORM/SRGB
1249 * - 16-bit or smaller FLOAT
1250 */
1251 color->export_16bpc = false;
1252 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1253 ((desc->channel[i].size < 12 &&
1254 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1255 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1256 (desc->channel[i].size < 17 &&
1257 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1258 color->info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1259 color->export_16bpc = true;
1260 }
1261
1262 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1263 color->slice = S_028C68_SLICE_TILE_MAX(slice);
1264
1265 if (rtex->fmask.size) {
1266 color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8;
1267 color->fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1268 } else {
1269 color->fmask = color->offset;
1270 color->fmask_slice = S_028C88_TILE_MAX(slice);
1271 }
1272 }
1273
1274 /**
1275 * This function intializes the CB* register values for RATs. It is meant
1276 * to be used for 1D aligned buffers that do not have an associated
1277 * radeon_surf.
1278 */
1279 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1280 struct r600_surface *surf)
1281 {
1282 struct pipe_resource *pipe_buffer = surf->base.texture;
1283 struct r600_tex_color_info color;
1284
1285 evergreen_set_color_surface_buffer(rctx, (struct r600_resource *)surf->base.texture,
1286 surf->base.format, 0, pipe_buffer->width0,
1287 &color);
1288
1289 surf->cb_color_base = color.offset;
1290 surf->cb_color_dim = color.dim;
1291 surf->cb_color_info = color.info | S_028C70_RAT(1);
1292 surf->cb_color_pitch = color.pitch;
1293 surf->cb_color_slice = color.slice;
1294 surf->cb_color_view = color.view;
1295 surf->cb_color_attrib = color.attrib;
1296 surf->cb_color_fmask = color.fmask;
1297 surf->cb_color_fmask_slice = color.fmask_slice;
1298
1299 surf->cb_color_view = 0;
1300
1301 /* Set the buffer range the GPU will have access to: */
1302 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
1303 0, pipe_buffer->width0);
1304 }
1305
1306
1307 void evergreen_init_color_surface(struct r600_context *rctx,
1308 struct r600_surface *surf)
1309 {
1310 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1311 unsigned level = surf->base.u.tex.level;
1312 struct r600_tex_color_info color;
1313
1314 evergreen_set_color_surface_common(rctx, rtex, level,
1315 surf->base.u.tex.first_layer,
1316 surf->base.u.tex.last_layer,
1317 surf->base.format,
1318 &color);
1319
1320 surf->alphatest_bypass = color.ntype == V_028C70_NUMBER_UINT ||
1321 color.ntype == V_028C70_NUMBER_SINT;
1322 surf->export_16bpc = color.export_16bpc;
1323
1324 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1325 surf->cb_color_base = color.offset;
1326 surf->cb_color_dim = color.dim;
1327 surf->cb_color_info = color.info;
1328 surf->cb_color_pitch = color.pitch;
1329 surf->cb_color_slice = color.slice;
1330 surf->cb_color_view = color.view;
1331 surf->cb_color_attrib = color.attrib;
1332 surf->cb_color_fmask = color.fmask;
1333 surf->cb_color_fmask_slice = color.fmask_slice;
1334
1335 surf->color_initialized = true;
1336 }
1337
1338 static void evergreen_init_depth_surface(struct r600_context *rctx,
1339 struct r600_surface *surf)
1340 {
1341 struct r600_screen *rscreen = rctx->screen;
1342 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1343 unsigned level = surf->base.u.tex.level;
1344 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
1345 uint64_t offset;
1346 unsigned format, array_mode;
1347 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1348
1349
1350 format = r600_translate_dbformat(surf->base.format);
1351 assert(format != ~0);
1352
1353 offset = rtex->resource.gpu_address;
1354 offset += rtex->surface.u.legacy.level[level].offset;
1355
1356 switch (rtex->surface.u.legacy.level[level].mode) {
1357 case RADEON_SURF_MODE_2D:
1358 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1359 break;
1360 case RADEON_SURF_MODE_1D:
1361 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1362 default:
1363 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1364 break;
1365 }
1366 tile_split = rtex->surface.u.legacy.tile_split;
1367 macro_aspect = rtex->surface.u.legacy.mtilea;
1368 bankw = rtex->surface.u.legacy.bankw;
1369 bankh = rtex->surface.u.legacy.bankh;
1370 tile_split = eg_tile_split(tile_split);
1371 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1372 bankw = eg_bank_wh(bankw);
1373 bankh = eg_bank_wh(bankh);
1374 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1375 offset >>= 8;
1376
1377 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1378 S_028040_FORMAT(format) |
1379 S_028040_TILE_SPLIT(tile_split)|
1380 S_028040_NUM_BANKS(nbanks) |
1381 S_028040_BANK_WIDTH(bankw) |
1382 S_028040_BANK_HEIGHT(bankh) |
1383 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1384 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1385 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1386 }
1387
1388 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1389
1390 surf->db_depth_base = offset;
1391 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1392 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1393 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1394 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1395 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1396 levelinfo->nblk_y / 64 - 1);
1397
1398 if (rtex->surface.has_stencil) {
1399 uint64_t stencil_offset;
1400 unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split;
1401
1402 stile_split = eg_tile_split(stile_split);
1403
1404 stencil_offset = rtex->surface.u.legacy.stencil_level[level].offset;
1405 stencil_offset += rtex->resource.gpu_address;
1406
1407 surf->db_stencil_base = stencil_offset >> 8;
1408 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1409 S_028044_TILE_SPLIT(stile_split);
1410 } else {
1411 surf->db_stencil_base = offset;
1412 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1413 * Older kernels are out of luck. */
1414 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1415 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1416 S_028044_FORMAT(V_028044_STENCIL_8);
1417 }
1418
1419 if (r600_htile_enabled(rtex, level)) {
1420 uint64_t va = rtex->resource.gpu_address + rtex->htile_offset;
1421 surf->db_htile_data_base = va >> 8;
1422 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1423 S_028ABC_HTILE_HEIGHT(1) |
1424 S_028ABC_FULL_CACHE(1);
1425 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1426 surf->db_preload_control = 0;
1427 }
1428
1429 surf->depth_initialized = true;
1430 }
1431
1432 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1433 const struct pipe_framebuffer_state *state)
1434 {
1435 struct r600_context *rctx = (struct r600_context *)ctx;
1436 struct r600_surface *surf;
1437 struct r600_texture *rtex;
1438 uint32_t i, log_samples;
1439
1440 /* Flush TC when changing the framebuffer state, because the only
1441 * client not using TC that can change textures is the framebuffer.
1442 * Other places don't typically have to flush TC.
1443 */
1444 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1445 R600_CONTEXT_FLUSH_AND_INV |
1446 R600_CONTEXT_FLUSH_AND_INV_CB |
1447 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1448 R600_CONTEXT_FLUSH_AND_INV_DB |
1449 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1450 R600_CONTEXT_INV_TEX_CACHE;
1451
1452 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1453
1454 /* Colorbuffers. */
1455 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1456 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1457 util_format_is_pure_integer(state->cbufs[0]->format);
1458 rctx->framebuffer.compressed_cb_mask = 0;
1459 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1460
1461 for (i = 0; i < state->nr_cbufs; i++) {
1462 surf = (struct r600_surface*)state->cbufs[i];
1463 if (!surf)
1464 continue;
1465
1466 rtex = (struct r600_texture*)surf->base.texture;
1467
1468 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1469
1470 if (!surf->color_initialized) {
1471 evergreen_init_color_surface(rctx, surf);
1472 }
1473
1474 if (!surf->export_16bpc) {
1475 rctx->framebuffer.export_16bpc = false;
1476 }
1477
1478 if (rtex->fmask.size) {
1479 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1480 }
1481 }
1482
1483 /* Update alpha-test state dependencies.
1484 * Alpha-test is done on the first colorbuffer only. */
1485 if (state->nr_cbufs) {
1486 bool alphatest_bypass = false;
1487 bool export_16bpc = true;
1488
1489 surf = (struct r600_surface*)state->cbufs[0];
1490 if (surf) {
1491 alphatest_bypass = surf->alphatest_bypass;
1492 export_16bpc = surf->export_16bpc;
1493 }
1494
1495 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1496 rctx->alphatest_state.bypass = alphatest_bypass;
1497 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1498 }
1499 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1500 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1501 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1502 }
1503 }
1504
1505 /* ZS buffer. */
1506 if (state->zsbuf) {
1507 surf = (struct r600_surface*)state->zsbuf;
1508
1509 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1510
1511 if (!surf->depth_initialized) {
1512 evergreen_init_depth_surface(rctx, surf);
1513 }
1514
1515 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1516 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1517 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1518 }
1519
1520 if (rctx->db_state.rsurf != surf) {
1521 rctx->db_state.rsurf = surf;
1522 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1523 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1524 }
1525 } else if (rctx->db_state.rsurf) {
1526 rctx->db_state.rsurf = NULL;
1527 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1528 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1529 }
1530
1531 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1532 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1533 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1534 }
1535
1536 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1537 rctx->alphatest_state.bypass = false;
1538 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1539 }
1540
1541 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1542 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1543 if ((rctx->b.chip_class == CAYMAN ||
1544 rctx->b.family == CHIP_RV770) &&
1545 rctx->db_misc_state.log_samples != log_samples) {
1546 rctx->db_misc_state.log_samples = log_samples;
1547 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1548 }
1549
1550
1551 /* Calculate the CS size. */
1552 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1553
1554 /* MSAA. */
1555 if (rctx->b.chip_class == EVERGREEN)
1556 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1557 else
1558 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1559
1560 /* Colorbuffers. */
1561 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1562 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1563 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1564
1565 /* ZS buffer. */
1566 if (state->zsbuf) {
1567 rctx->framebuffer.atom.num_dw += 24;
1568 rctx->framebuffer.atom.num_dw += 2;
1569 } else if (rctx->screen->b.info.drm_minor >= 18) {
1570 rctx->framebuffer.atom.num_dw += 4;
1571 }
1572
1573 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1574
1575 r600_set_sample_locations_constant_buffer(rctx);
1576 rctx->framebuffer.do_update_surf_dirtiness = true;
1577 }
1578
1579 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1580 {
1581 struct r600_context *rctx = (struct r600_context *)ctx;
1582
1583 if (rctx->ps_iter_samples == min_samples)
1584 return;
1585
1586 rctx->ps_iter_samples = min_samples;
1587 if (rctx->framebuffer.nr_samples > 1) {
1588 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1589 }
1590 }
1591
1592 /* 8xMSAA */
1593 static uint32_t sample_locs_8x[] = {
1594 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1595 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1596 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1597 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1598 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1599 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1600 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1601 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1602 };
1603 static unsigned max_dist_8x = 7;
1604
1605 static void evergreen_get_sample_position(struct pipe_context *ctx,
1606 unsigned sample_count,
1607 unsigned sample_index,
1608 float *out_value)
1609 {
1610 int offset, index;
1611 struct {
1612 int idx:4;
1613 } val;
1614 switch (sample_count) {
1615 case 1:
1616 default:
1617 out_value[0] = out_value[1] = 0.5;
1618 break;
1619 case 2:
1620 offset = 4 * (sample_index * 2);
1621 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1622 out_value[0] = (float)(val.idx + 8) / 16.0f;
1623 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1624 out_value[1] = (float)(val.idx + 8) / 16.0f;
1625 break;
1626 case 4:
1627 offset = 4 * (sample_index * 2);
1628 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1629 out_value[0] = (float)(val.idx + 8) / 16.0f;
1630 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1631 out_value[1] = (float)(val.idx + 8) / 16.0f;
1632 break;
1633 case 8:
1634 offset = 4 * (sample_index % 4 * 2);
1635 index = (sample_index / 4);
1636 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1637 out_value[0] = (float)(val.idx + 8) / 16.0f;
1638 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1639 out_value[1] = (float)(val.idx + 8) / 16.0f;
1640 break;
1641 }
1642 }
1643
1644 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1645 {
1646
1647 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1648 unsigned max_dist = 0;
1649
1650 switch (nr_samples) {
1651 default:
1652 nr_samples = 0;
1653 break;
1654 case 2:
1655 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x));
1656 radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x));
1657 max_dist = eg_max_dist_2x;
1658 break;
1659 case 4:
1660 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x));
1661 radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x));
1662 max_dist = eg_max_dist_4x;
1663 break;
1664 case 8:
1665 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x));
1666 radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x));
1667 max_dist = max_dist_8x;
1668 break;
1669 }
1670
1671 if (nr_samples > 1) {
1672 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1673 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1674 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1675 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1676 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1677 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1678 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1679 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1680 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1681 } else {
1682 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1683 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1684 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1685 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1686 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1687 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1688 }
1689 }
1690
1691 static void evergreen_emit_image_state(struct r600_context *rctx, struct r600_atom *atom,
1692 int immed_id_base, int res_id_base, int offset, uint32_t pkt_flags)
1693 {
1694 struct r600_image_state *state = (struct r600_image_state *)atom;
1695 struct pipe_framebuffer_state *fb_state = &rctx->framebuffer.state;
1696 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1697 struct r600_texture *rtex;
1698 struct r600_resource *resource;
1699 int i;
1700
1701 for (i = 0; i < R600_MAX_IMAGES; i++) {
1702 struct r600_image_view *image = &state->views[i];
1703 unsigned reloc, immed_reloc;
1704 int idx = i + offset;
1705
1706 if (!pkt_flags)
1707 idx += fb_state->nr_cbufs + (rctx->dual_src_blend ? 1 : 0);
1708 if (!image->base.resource)
1709 continue;
1710
1711 resource = (struct r600_resource *)image->base.resource;
1712 if (resource->b.b.target != PIPE_BUFFER)
1713 rtex = (struct r600_texture *)image->base.resource;
1714 else
1715 rtex = NULL;
1716
1717 reloc = radeon_add_to_buffer_list(&rctx->b,
1718 &rctx->b.gfx,
1719 resource,
1720 RADEON_USAGE_READWRITE,
1721 RADEON_PRIO_SHADER_RW_BUFFER);
1722
1723 immed_reloc = radeon_add_to_buffer_list(&rctx->b,
1724 &rctx->b.gfx,
1725 resource->immed_buffer,
1726 RADEON_USAGE_READWRITE,
1727 RADEON_PRIO_SHADER_RW_BUFFER);
1728
1729 if (pkt_flags)
1730 radeon_compute_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13);
1731 else
1732 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13);
1733
1734 radeon_emit(cs, image->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1735 radeon_emit(cs, image->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1736 radeon_emit(cs, image->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1737 radeon_emit(cs, image->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1738 radeon_emit(cs, image->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1739 radeon_emit(cs, image->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1740 radeon_emit(cs, image->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1741 radeon_emit(cs, rtex ? rtex->cmask.base_address_reg : image->cb_color_base); /* R_028C7C_CB_COLOR0_CMASK */
1742 radeon_emit(cs, rtex ? rtex->cmask.slice_tile_max : 0); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1743 radeon_emit(cs, image->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1744 radeon_emit(cs, image->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1745 radeon_emit(cs, rtex ? rtex->color_clear_value[0] : 0); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1746 radeon_emit(cs, rtex ? rtex->color_clear_value[1] : 0); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1747
1748 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1749 radeon_emit(cs, reloc);
1750
1751 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1752 radeon_emit(cs, reloc);
1753
1754 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1755 radeon_emit(cs, reloc);
1756
1757 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1758 radeon_emit(cs, reloc);
1759
1760 if (pkt_flags)
1761 radeon_compute_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1762 else
1763 radeon_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1764
1765 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /**/
1766 radeon_emit(cs, immed_reloc);
1767
1768 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1769 radeon_emit(cs, (immed_id_base + i + offset) * 8);
1770 radeon_emit_array(cs, image->immed_resource_words, 8);
1771
1772 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1773 radeon_emit(cs, immed_reloc);
1774
1775 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1776 radeon_emit(cs, (res_id_base + i + offset) * 8);
1777 radeon_emit_array(cs, image->resource_words, 8);
1778
1779 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1780 radeon_emit(cs, reloc);
1781
1782 if (!image->skip_mip_address_reloc) {
1783 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1784 radeon_emit(cs, reloc);
1785 }
1786 }
1787 }
1788
1789 static void evergreen_emit_fragment_image_state(struct r600_context *rctx, struct r600_atom *atom)
1790 {
1791 evergreen_emit_image_state(rctx, atom,
1792 R600_IMAGE_IMMED_RESOURCE_OFFSET,
1793 R600_IMAGE_REAL_RESOURCE_OFFSET, 0, 0);
1794 }
1795
1796 static void evergreen_emit_compute_image_state(struct r600_context *rctx, struct r600_atom *atom)
1797 {
1798 evergreen_emit_image_state(rctx, atom,
1799 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_IMMED_RESOURCE_OFFSET,
1800 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_REAL_RESOURCE_OFFSET,
1801 0, RADEON_CP_PACKET3_COMPUTE_MODE);
1802 }
1803
1804 static void evergreen_emit_fragment_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1805 {
1806 int offset = util_bitcount(rctx->fragment_images.enabled_mask);
1807 evergreen_emit_image_state(rctx, atom,
1808 R600_IMAGE_IMMED_RESOURCE_OFFSET,
1809 R600_IMAGE_REAL_RESOURCE_OFFSET, offset, 0);
1810 }
1811
1812 static void evergreen_emit_compute_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1813 {
1814 int offset = util_bitcount(rctx->compute_images.enabled_mask);
1815 evergreen_emit_image_state(rctx, atom,
1816 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_IMMED_RESOURCE_OFFSET,
1817 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_REAL_RESOURCE_OFFSET,
1818 offset, RADEON_CP_PACKET3_COMPUTE_MODE);
1819 }
1820
1821 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1822 {
1823 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1824 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1825 unsigned nr_cbufs = state->nr_cbufs;
1826 unsigned i, tl, br;
1827 struct r600_texture *tex = NULL;
1828 struct r600_surface *cb = NULL;
1829
1830 /* XXX support more colorbuffers once we need them */
1831 assert(nr_cbufs <= 8);
1832 if (nr_cbufs > 8)
1833 nr_cbufs = 8;
1834
1835 /* Colorbuffers. */
1836 for (i = 0; i < nr_cbufs; i++) {
1837 unsigned reloc, cmask_reloc;
1838
1839 cb = (struct r600_surface*)state->cbufs[i];
1840 if (!cb) {
1841 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1842 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1843 continue;
1844 }
1845
1846 tex = (struct r600_texture *)cb->base.texture;
1847 reloc = radeon_add_to_buffer_list(&rctx->b,
1848 &rctx->b.gfx,
1849 (struct r600_resource*)cb->base.texture,
1850 RADEON_USAGE_READWRITE,
1851 tex->resource.b.b.nr_samples > 1 ?
1852 RADEON_PRIO_COLOR_BUFFER_MSAA :
1853 RADEON_PRIO_COLOR_BUFFER);
1854
1855 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1856 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1857 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1858 RADEON_PRIO_CMASK);
1859 } else {
1860 cmask_reloc = reloc;
1861 }
1862
1863 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1864 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1865 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1866 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1867 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1868 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1869 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1870 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1871 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1872 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1873 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1874 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1875 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1876 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1877
1878 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1879 radeon_emit(cs, reloc);
1880
1881 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1882 radeon_emit(cs, reloc);
1883
1884 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1885 radeon_emit(cs, cmask_reloc);
1886
1887 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1888 radeon_emit(cs, reloc);
1889 }
1890 /* set CB_COLOR1_INFO for possible dual-src blending */
1891 if (rctx->framebuffer.dual_src_blend && i == 1 && state->cbufs[0]) {
1892 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1893 cb->cb_color_info | tex->cb_color_info);
1894 i++;
1895 }
1896 i += util_bitcount(rctx->fragment_images.enabled_mask);
1897 i += util_bitcount(rctx->fragment_buffers.enabled_mask);
1898 for (; i < 8 ; i++)
1899 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1900 for (; i < 12; i++)
1901 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1902
1903 /* ZS buffer. */
1904 if (state->zsbuf) {
1905 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1906 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1907 &rctx->b.gfx,
1908 (struct r600_resource*)state->zsbuf->texture,
1909 RADEON_USAGE_READWRITE,
1910 zb->base.texture->nr_samples > 1 ?
1911 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1912 RADEON_PRIO_DEPTH_BUFFER);
1913
1914 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1915
1916 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1917 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1918 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1919 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1920 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1921 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1922 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1923 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1924 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1925
1926 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1927 radeon_emit(cs, reloc);
1928
1929 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1930 radeon_emit(cs, reloc);
1931
1932 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1933 radeon_emit(cs, reloc);
1934
1935 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1936 radeon_emit(cs, reloc);
1937 } else if (rctx->screen->b.info.drm_minor >= 18) {
1938 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1939 * Older kernels are out of luck. */
1940 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1941 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1942 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1943 }
1944
1945 /* Framebuffer dimensions. */
1946 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1947
1948 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1949 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1950 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1951
1952 if (rctx->b.chip_class == EVERGREEN) {
1953 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1954 } else {
1955 unsigned sc_mode_cntl_1 =
1956 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1957 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1958
1959 if (rctx->framebuffer.nr_samples > 1)
1960 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1961 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples,
1962 rctx->ps_iter_samples, 0, sc_mode_cntl_1);
1963 }
1964 }
1965
1966 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1967 {
1968 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1969 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1970 float offset_units = state->offset_units;
1971 float offset_scale = state->offset_scale;
1972 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
1973
1974 if (!state->offset_units_unscaled) {
1975 switch (state->zs_format) {
1976 case PIPE_FORMAT_Z24X8_UNORM:
1977 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1978 case PIPE_FORMAT_X8Z24_UNORM:
1979 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1980 offset_units *= 2.0f;
1981 pa_su_poly_offset_db_fmt_cntl =
1982 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1983 break;
1984 case PIPE_FORMAT_Z16_UNORM:
1985 offset_units *= 4.0f;
1986 pa_su_poly_offset_db_fmt_cntl =
1987 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1988 break;
1989 default:
1990 pa_su_poly_offset_db_fmt_cntl =
1991 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1992 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1993 }
1994 }
1995
1996 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1997 radeon_emit(cs, fui(offset_scale));
1998 radeon_emit(cs, fui(offset_units));
1999 radeon_emit(cs, fui(offset_scale));
2000 radeon_emit(cs, fui(offset_units));
2001
2002 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2003 pa_su_poly_offset_db_fmt_cntl);
2004 }
2005
2006 uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a,
2007 unsigned nr_cbufs)
2008 {
2009 unsigned base_mask = 0;
2010 unsigned dirty_mask = a->image_rat_enabled_mask;
2011 while (dirty_mask) {
2012 unsigned idx = u_bit_scan(&dirty_mask);
2013 base_mask |= (0xf << (idx * 4));
2014 }
2015 unsigned offset = util_last_bit(a->image_rat_enabled_mask);
2016 dirty_mask = a->buffer_rat_enabled_mask;
2017 while (dirty_mask) {
2018 unsigned idx = u_bit_scan(&dirty_mask);
2019 base_mask |= (0xf << (idx + offset) * 4);
2020 }
2021 return base_mask << (nr_cbufs * 4);
2022 }
2023
2024 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2025 {
2026 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2027 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
2028 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
2029 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
2030 unsigned rat_colormask = evergreen_construct_rat_mask(rctx, a, a->nr_cbufs);
2031 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
2032 radeon_emit(cs, (a->blend_colormask & fb_colormask) | rat_colormask); /* R_028238_CB_TARGET_MASK */
2033 /* This must match the used export instructions exactly.
2034 * Other values may lead to undefined behavior and hangs.
2035 */
2036 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
2037 }
2038
2039 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
2040 {
2041 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2042 struct r600_db_state *a = (struct r600_db_state*)atom;
2043
2044 if (a->rsurf && a->rsurf->db_htile_surface) {
2045 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
2046 unsigned reloc_idx;
2047
2048 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2049 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
2050 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
2051 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
2052 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
2053 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
2054 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2055 radeon_emit(cs, reloc_idx);
2056 } else {
2057 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
2058 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
2059 }
2060 }
2061
2062 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2063 {
2064 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2065 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2066 unsigned db_render_control = 0;
2067 unsigned db_count_control = 0;
2068 unsigned db_render_override =
2069 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2070 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2071
2072 if (rctx->b.num_occlusion_queries > 0 &&
2073 !a->occlusion_queries_disabled) {
2074 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
2075 if (rctx->b.chip_class == CAYMAN) {
2076 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
2077 }
2078 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
2079 } else {
2080 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
2081 }
2082
2083 /* This is to fix a lockup when hyperz and alpha test are enabled at
2084 * the same time somehow GPU get confuse on which order to pick for
2085 * z test
2086 */
2087 if (rctx->alphatest_state.sx_alpha_test_control)
2088 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
2089
2090 if (a->flush_depthstencil_through_cb) {
2091 assert(a->copy_depth || a->copy_stencil);
2092
2093 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
2094 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
2095 S_028000_COPY_CENTROID(1) |
2096 S_028000_COPY_SAMPLE(a->copy_sample);
2097 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
2098 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
2099 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
2100 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2101 }
2102 if (a->htile_clear) {
2103 /* FIXME we might want to disable cliprect here */
2104 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
2105 }
2106
2107 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
2108 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
2109 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
2110 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2111 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2112 }
2113
2114 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
2115 struct r600_vertexbuf_state *state,
2116 unsigned resource_offset,
2117 unsigned pkt_flags)
2118 {
2119 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2120 uint32_t dirty_mask = state->dirty_mask;
2121
2122 while (dirty_mask) {
2123 struct pipe_vertex_buffer *vb;
2124 struct r600_resource *rbuffer;
2125 uint64_t va;
2126 unsigned buffer_index = u_bit_scan(&dirty_mask);
2127
2128 vb = &state->vb[buffer_index];
2129 rbuffer = (struct r600_resource*)vb->buffer.resource;
2130 assert(rbuffer);
2131
2132 va = rbuffer->gpu_address + vb->buffer_offset;
2133
2134 /* fetch resources start at index 992 */
2135 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2136 radeon_emit(cs, (resource_offset + buffer_index) * 8);
2137 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2138 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2139 radeon_emit(cs, /* RESOURCEi_WORD2 */
2140 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2141 S_030008_STRIDE(vb->stride) |
2142 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2143 radeon_emit(cs, /* RESOURCEi_WORD3 */
2144 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2145 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2146 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2147 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2148 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2149 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2150 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2151 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2152
2153 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2154 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2155 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
2156 }
2157 state->dirty_mask = 0;
2158 }
2159
2160 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2161 {
2162 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
2163 }
2164
2165 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2166 {
2167 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
2168 RADEON_CP_PACKET3_COMPUTE_MODE);
2169 }
2170
2171 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2172 struct r600_constbuf_state *state,
2173 unsigned buffer_id_base,
2174 unsigned reg_alu_constbuf_size,
2175 unsigned reg_alu_const_cache,
2176 unsigned pkt_flags)
2177 {
2178 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2179 uint32_t dirty_mask = state->dirty_mask;
2180
2181 while (dirty_mask) {
2182 struct pipe_constant_buffer *cb;
2183 struct r600_resource *rbuffer;
2184 uint64_t va;
2185 unsigned buffer_index = ffs(dirty_mask) - 1;
2186 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
2187
2188 cb = &state->cb[buffer_index];
2189 rbuffer = (struct r600_resource*)cb->buffer;
2190 assert(rbuffer);
2191
2192 va = rbuffer->gpu_address + cb->buffer_offset;
2193
2194 if (buffer_index < R600_MAX_HW_CONST_BUFFERS) {
2195 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
2196 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
2197 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
2198 pkt_flags);
2199 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2200 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2201 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2202 }
2203
2204 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2205 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
2206 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2207 radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2208 radeon_emit(cs, /* RESOURCEi_WORD2 */
2209 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
2210 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
2211 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
2212 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
2213 radeon_emit(cs, /* RESOURCEi_WORD3 */
2214 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
2215 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2216 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2217 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2218 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2219 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2220 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2221 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2222 radeon_emit(cs, /* RESOURCEi_WORD7 */
2223 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
2224
2225 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2226 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2227 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
2228
2229 dirty_mask &= ~(1 << buffer_index);
2230 }
2231 state->dirty_mask = 0;
2232 }
2233
2234 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
2235 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2236 {
2237 if (rctx->vs_shader->current->shader.vs_as_ls) {
2238 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2239 EG_FETCH_CONSTANTS_OFFSET_LS,
2240 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2241 R_028F40_ALU_CONST_CACHE_LS_0,
2242 0 /* PKT3 flags */);
2243 } else {
2244 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2245 EG_FETCH_CONSTANTS_OFFSET_VS,
2246 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2247 R_028980_ALU_CONST_CACHE_VS_0,
2248 0 /* PKT3 flags */);
2249 }
2250 }
2251
2252 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2253 {
2254 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
2255 EG_FETCH_CONSTANTS_OFFSET_GS,
2256 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2257 R_0289C0_ALU_CONST_CACHE_GS_0,
2258 0 /* PKT3 flags */);
2259 }
2260
2261 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2262 {
2263 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
2264 EG_FETCH_CONSTANTS_OFFSET_PS,
2265 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2266 R_028940_ALU_CONST_CACHE_PS_0,
2267 0 /* PKT3 flags */);
2268 }
2269
2270 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2271 {
2272 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
2273 EG_FETCH_CONSTANTS_OFFSET_CS,
2274 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2275 R_028F40_ALU_CONST_CACHE_LS_0,
2276 RADEON_CP_PACKET3_COMPUTE_MODE);
2277 }
2278
2279 /* tes constants can be emitted to VS or ES - which are common */
2280 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2281 {
2282 if (!rctx->tes_shader)
2283 return;
2284 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2285 EG_FETCH_CONSTANTS_OFFSET_VS,
2286 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2287 R_028980_ALU_CONST_CACHE_VS_0,
2288 0);
2289 }
2290
2291 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2292 {
2293 if (!rctx->tes_shader)
2294 return;
2295 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2296 EG_FETCH_CONSTANTS_OFFSET_HS,
2297 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
2298 R_028F00_ALU_CONST_CACHE_HS_0,
2299 0);
2300 }
2301
2302 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2303 struct r600_samplerview_state *state,
2304 unsigned resource_id_base, unsigned pkt_flags)
2305 {
2306 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2307 uint32_t dirty_mask = state->dirty_mask;
2308
2309 while (dirty_mask) {
2310 struct r600_pipe_sampler_view *rview;
2311 unsigned resource_index = u_bit_scan(&dirty_mask);
2312 unsigned reloc;
2313
2314 rview = state->views[resource_index];
2315 assert(rview);
2316
2317 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2318 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2319 radeon_emit_array(cs, rview->tex_resource_words, 8);
2320
2321 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2322 RADEON_USAGE_READ,
2323 r600_get_sampler_view_priority(rview->tex_resource));
2324 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2325 radeon_emit(cs, reloc);
2326
2327 if (!rview->skip_mip_address_reloc) {
2328 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2329 radeon_emit(cs, reloc);
2330 }
2331 }
2332 state->dirty_mask = 0;
2333 }
2334
2335 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2336 {
2337 if (rctx->vs_shader->current->shader.vs_as_ls) {
2338 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2339 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2340 } else {
2341 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2342 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2343 }
2344 }
2345
2346 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2347 {
2348 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2349 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2350 }
2351
2352 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2353 {
2354 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2355 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2356 }
2357
2358 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2359 {
2360 if (!rctx->tes_shader)
2361 return;
2362 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2363 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2364 }
2365
2366 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2367 {
2368 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2369 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2370 }
2371
2372 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2373 {
2374 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2375 EG_FETCH_CONSTANTS_OFFSET_CS + R600_MAX_CONST_BUFFERS, RADEON_CP_PACKET3_COMPUTE_MODE);
2376 }
2377
2378 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2379 struct r600_textures_info *texinfo,
2380 unsigned resource_id_base,
2381 unsigned border_index_reg,
2382 unsigned pkt_flags)
2383 {
2384 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2385 uint32_t dirty_mask = texinfo->states.dirty_mask;
2386
2387 while (dirty_mask) {
2388 struct r600_pipe_sampler_state *rstate;
2389 unsigned i = u_bit_scan(&dirty_mask);
2390
2391 rstate = texinfo->states.states[i];
2392 assert(rstate);
2393
2394 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2395 radeon_emit(cs, (resource_id_base + i) * 3);
2396 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2397
2398 if (rstate->border_color_use) {
2399 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2400 radeon_emit(cs, i);
2401 radeon_emit_array(cs, rstate->border_color.ui, 4);
2402 }
2403 }
2404 texinfo->states.dirty_mask = 0;
2405 }
2406
2407 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2408 {
2409 if (rctx->vs_shader->current->shader.vs_as_ls) {
2410 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2411 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2412 } else {
2413 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2414 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2415 }
2416 }
2417
2418 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2419 {
2420 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2421 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2422 }
2423
2424 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2425 {
2426 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2427 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2428 }
2429
2430 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2431 {
2432 if (!rctx->tes_shader)
2433 return;
2434 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2435 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2436 }
2437
2438 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2439 {
2440 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2441 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2442 }
2443
2444 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2445 {
2446 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2447 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2448 RADEON_CP_PACKET3_COMPUTE_MODE);
2449 }
2450
2451 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2452 {
2453 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2454 uint8_t mask = s->sample_mask;
2455
2456 radeon_set_context_reg(rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2457 mask | (mask << 8) | (mask << 16) | (mask << 24));
2458 }
2459
2460 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2461 {
2462 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2463 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2464 uint16_t mask = s->sample_mask;
2465
2466 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2467 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2468 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2469 }
2470
2471 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2472 {
2473 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2474 struct r600_cso_state *state = (struct r600_cso_state*)a;
2475 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2476
2477 if (!shader)
2478 return;
2479
2480 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2481 (shader->buffer->gpu_address + shader->offset) >> 8);
2482 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2483 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2484 RADEON_USAGE_READ,
2485 RADEON_PRIO_SHADER_BINARY));
2486 }
2487
2488 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2489 {
2490 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2491 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2492
2493 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2494
2495 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2496 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2497 primid = 1;
2498 }
2499
2500 if (state->geom_enable) {
2501 uint32_t cut_val;
2502
2503 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2504 cut_val = V_028A40_GS_CUT_128;
2505 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2506 cut_val = V_028A40_GS_CUT_256;
2507 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2508 cut_val = V_028A40_GS_CUT_512;
2509 else
2510 cut_val = V_028A40_GS_CUT_1024;
2511
2512 v = S_028B54_GS_EN(1) |
2513 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2514 if (!rctx->tes_shader)
2515 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2516
2517 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2518 S_028A40_CUT_MODE(cut_val);
2519
2520 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2521 primid = 1;
2522 }
2523
2524 if (rctx->tes_shader) {
2525 uint32_t type, partitioning, topology;
2526 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2527 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2528 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2529 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2530 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2531 switch (tes_prim_mode) {
2532 case PIPE_PRIM_LINES:
2533 type = V_028B6C_TESS_ISOLINE;
2534 break;
2535 case PIPE_PRIM_TRIANGLES:
2536 type = V_028B6C_TESS_TRIANGLE;
2537 break;
2538 case PIPE_PRIM_QUADS:
2539 type = V_028B6C_TESS_QUAD;
2540 break;
2541 default:
2542 assert(0);
2543 return;
2544 }
2545
2546 switch (tes_spacing) {
2547 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2548 partitioning = V_028B6C_PART_FRAC_ODD;
2549 break;
2550 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2551 partitioning = V_028B6C_PART_FRAC_EVEN;
2552 break;
2553 case PIPE_TESS_SPACING_EQUAL:
2554 partitioning = V_028B6C_PART_INTEGER;
2555 break;
2556 default:
2557 assert(0);
2558 return;
2559 }
2560
2561 if (tes_point_mode)
2562 topology = V_028B6C_OUTPUT_POINT;
2563 else if (tes_prim_mode == PIPE_PRIM_LINES)
2564 topology = V_028B6C_OUTPUT_LINE;
2565 else if (tes_vertex_order_cw)
2566 /* XXX follow radeonsi and invert */
2567 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2568 else
2569 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2570
2571 tf_param = S_028B6C_TYPE(type) |
2572 S_028B6C_PARTITIONING(partitioning) |
2573 S_028B6C_TOPOLOGY(topology);
2574 }
2575
2576 if (rctx->tes_shader) {
2577 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2578 S_028B54_HS_EN(1);
2579 if (!state->geom_enable)
2580 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2581 else
2582 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2583 }
2584
2585 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2586 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2587 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2588 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2589 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2590 }
2591
2592 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2593 {
2594 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2595 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2596 struct r600_resource *rbuffer;
2597
2598 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2599 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2600 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2601
2602 if (state->enable) {
2603 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2604 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2605 rbuffer->gpu_address >> 8);
2606 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2607 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2608 RADEON_USAGE_READWRITE,
2609 RADEON_PRIO_SHADER_RINGS));
2610 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2611 state->esgs_ring.buffer_size >> 8);
2612
2613 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2614 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2615 rbuffer->gpu_address >> 8);
2616 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2617 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2618 RADEON_USAGE_READWRITE,
2619 RADEON_PRIO_SHADER_RINGS));
2620 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2621 state->gsvs_ring.buffer_size >> 8);
2622 } else {
2623 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2624 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2625 }
2626
2627 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2628 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2629 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2630 }
2631
2632 void cayman_init_common_regs(struct r600_command_buffer *cb,
2633 enum chip_class ctx_chip_class,
2634 enum radeon_family ctx_family,
2635 int ctx_drm_minor)
2636 {
2637 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2638 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2639 /* always set the temp clauses */
2640 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2641
2642 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2643 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2644 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2645
2646 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2647
2648 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2649 r600_store_value(cb, 0);
2650 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2651
2652 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2653 }
2654
2655 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2656 {
2657 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2658 int i;
2659
2660 r600_init_command_buffer(cb, 338);
2661
2662 /* This must be first. */
2663 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2664 r600_store_value(cb, 0x80000000);
2665 r600_store_value(cb, 0x80000000);
2666
2667 /* We're setting config registers here. */
2668 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2669 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2670
2671 /* This enables pipeline stat & streamout queries.
2672 * They are only disabled by blits.
2673 */
2674 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2675 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2676
2677 cayman_init_common_regs(cb, rctx->b.chip_class,
2678 rctx->b.family, rctx->screen->b.info.drm_minor);
2679
2680 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2681 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2682
2683 /* remove LS/HS from one SIMD for hw workaround */
2684 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2685 r600_store_value(cb, 0xffffffff);
2686 r600_store_value(cb, 0xffffffff);
2687 r600_store_value(cb, 0xfffffffe);
2688
2689 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2690 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2691 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2692 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2693 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2694 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2695 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2696
2697 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2698 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2699 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2700 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2701 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2702
2703 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2704 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2705 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2706 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2707 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2708 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2709 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2710 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2711 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2712 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2713 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2714 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2715 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2716 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2717
2718 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2719
2720 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2721
2722 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2723 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2724 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2725
2726 r600_store_context_reg(cb, R_028724_GDS_ADDR_SIZE, 0x3fff);
2727 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2728 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2729 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2730
2731 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2732
2733 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2734 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2735 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2736
2737 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2738
2739 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2740
2741 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2742
2743 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2744 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2745 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2746 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2747
2748 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2749 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2750
2751 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2752 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2753
2754 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2755 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2756 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2757
2758 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2759 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2760 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2761
2762 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2763 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2764 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2765 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2766 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2767 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2768
2769 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2770
2771 /* to avoid GPU doing any preloading of constant from random address */
2772 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2773 for (i = 0; i < 16; i++)
2774 r600_store_value(cb, 0);
2775
2776 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2777 for (i = 0; i < 16; i++)
2778 r600_store_value(cb, 0);
2779
2780 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2781 for (i = 0; i < 16; i++)
2782 r600_store_value(cb, 0);
2783
2784 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2785 for (i = 0; i < 16; i++)
2786 r600_store_value(cb, 0);
2787
2788 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2789 for (i = 0; i < 16; i++)
2790 r600_store_value(cb, 0);
2791
2792 if (rctx->screen->b.has_streamout) {
2793 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2794 }
2795
2796 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2797 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2798 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2799 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2800 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2801 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2802
2803 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2804 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2805 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2806 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2807 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2808 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2809 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2810 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2811 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2812 }
2813
2814 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2815 enum chip_class ctx_chip_class,
2816 enum radeon_family ctx_family,
2817 int ctx_drm_minor)
2818 {
2819 int ps_prio;
2820 int vs_prio;
2821 int gs_prio;
2822 int es_prio;
2823
2824 int hs_prio;
2825 int cs_prio;
2826 int ls_prio;
2827
2828 unsigned tmp;
2829
2830 ps_prio = 0;
2831 vs_prio = 1;
2832 gs_prio = 2;
2833 es_prio = 3;
2834 hs_prio = 3;
2835 ls_prio = 3;
2836 cs_prio = 0;
2837
2838 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2839 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2840 rctx->r6xx_num_clause_temp_gprs = 4;
2841 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2842 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2843 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2844 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2845
2846 tmp = 0;
2847 switch (ctx_family) {
2848 case CHIP_CEDAR:
2849 case CHIP_PALM:
2850 case CHIP_SUMO:
2851 case CHIP_SUMO2:
2852 case CHIP_CAICOS:
2853 break;
2854 default:
2855 tmp |= S_008C00_VC_ENABLE(1);
2856 break;
2857 }
2858 tmp |= S_008C00_EXPORT_SRC_C(1);
2859 tmp |= S_008C00_CS_PRIO(cs_prio);
2860 tmp |= S_008C00_LS_PRIO(ls_prio);
2861 tmp |= S_008C00_HS_PRIO(hs_prio);
2862 tmp |= S_008C00_PS_PRIO(ps_prio);
2863 tmp |= S_008C00_VS_PRIO(vs_prio);
2864 tmp |= S_008C00_GS_PRIO(gs_prio);
2865 tmp |= S_008C00_ES_PRIO(es_prio);
2866
2867 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
2868 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2869
2870 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2871 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2872 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2873
2874 /* The cs checker requires this register to be set. */
2875 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2876
2877 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2878 r600_store_value(cb, 0);
2879 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2880
2881 return;
2882 }
2883
2884 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2885 {
2886 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2887 int num_ps_threads;
2888 int num_vs_threads;
2889 int num_gs_threads;
2890 int num_es_threads;
2891 int num_hs_threads;
2892 int num_ls_threads;
2893
2894 int num_ps_stack_entries;
2895 int num_vs_stack_entries;
2896 int num_gs_stack_entries;
2897 int num_es_stack_entries;
2898 int num_hs_stack_entries;
2899 int num_ls_stack_entries;
2900 enum radeon_family family;
2901 unsigned tmp, i;
2902
2903 if (rctx->b.chip_class == CAYMAN) {
2904 cayman_init_atom_start_cs(rctx);
2905 return;
2906 }
2907
2908 r600_init_command_buffer(cb, 338);
2909
2910 /* This must be first. */
2911 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2912 r600_store_value(cb, 0x80000000);
2913 r600_store_value(cb, 0x80000000);
2914
2915 /* We're setting config registers here. */
2916 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2917 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2918
2919 /* This enables pipeline stat & streamout queries.
2920 * They are only disabled by blits.
2921 */
2922 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2923 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2924
2925 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class,
2926 rctx->b.family, rctx->screen->b.info.drm_minor);
2927
2928 family = rctx->b.family;
2929 switch (family) {
2930 case CHIP_CEDAR:
2931 default:
2932 num_ps_threads = 96;
2933 num_vs_threads = 16;
2934 num_gs_threads = 16;
2935 num_es_threads = 16;
2936 num_hs_threads = 16;
2937 num_ls_threads = 16;
2938 num_ps_stack_entries = 42;
2939 num_vs_stack_entries = 42;
2940 num_gs_stack_entries = 42;
2941 num_es_stack_entries = 42;
2942 num_hs_stack_entries = 42;
2943 num_ls_stack_entries = 42;
2944 break;
2945 case CHIP_REDWOOD:
2946 num_ps_threads = 128;
2947 num_vs_threads = 20;
2948 num_gs_threads = 20;
2949 num_es_threads = 20;
2950 num_hs_threads = 20;
2951 num_ls_threads = 20;
2952 num_ps_stack_entries = 42;
2953 num_vs_stack_entries = 42;
2954 num_gs_stack_entries = 42;
2955 num_es_stack_entries = 42;
2956 num_hs_stack_entries = 42;
2957 num_ls_stack_entries = 42;
2958 break;
2959 case CHIP_JUNIPER:
2960 num_ps_threads = 128;
2961 num_vs_threads = 20;
2962 num_gs_threads = 20;
2963 num_es_threads = 20;
2964 num_hs_threads = 20;
2965 num_ls_threads = 20;
2966 num_ps_stack_entries = 85;
2967 num_vs_stack_entries = 85;
2968 num_gs_stack_entries = 85;
2969 num_es_stack_entries = 85;
2970 num_hs_stack_entries = 85;
2971 num_ls_stack_entries = 85;
2972 break;
2973 case CHIP_CYPRESS:
2974 case CHIP_HEMLOCK:
2975 num_ps_threads = 128;
2976 num_vs_threads = 20;
2977 num_gs_threads = 20;
2978 num_es_threads = 20;
2979 num_hs_threads = 20;
2980 num_ls_threads = 20;
2981 num_ps_stack_entries = 85;
2982 num_vs_stack_entries = 85;
2983 num_gs_stack_entries = 85;
2984 num_es_stack_entries = 85;
2985 num_hs_stack_entries = 85;
2986 num_ls_stack_entries = 85;
2987 break;
2988 case CHIP_PALM:
2989 num_ps_threads = 96;
2990 num_vs_threads = 16;
2991 num_gs_threads = 16;
2992 num_es_threads = 16;
2993 num_hs_threads = 16;
2994 num_ls_threads = 16;
2995 num_ps_stack_entries = 42;
2996 num_vs_stack_entries = 42;
2997 num_gs_stack_entries = 42;
2998 num_es_stack_entries = 42;
2999 num_hs_stack_entries = 42;
3000 num_ls_stack_entries = 42;
3001 break;
3002 case CHIP_SUMO:
3003 num_ps_threads = 96;
3004 num_vs_threads = 25;
3005 num_gs_threads = 25;
3006 num_es_threads = 25;
3007 num_hs_threads = 16;
3008 num_ls_threads = 16;
3009 num_ps_stack_entries = 42;
3010 num_vs_stack_entries = 42;
3011 num_gs_stack_entries = 42;
3012 num_es_stack_entries = 42;
3013 num_hs_stack_entries = 42;
3014 num_ls_stack_entries = 42;
3015 break;
3016 case CHIP_SUMO2:
3017 num_ps_threads = 96;
3018 num_vs_threads = 25;
3019 num_gs_threads = 25;
3020 num_es_threads = 25;
3021 num_hs_threads = 16;
3022 num_ls_threads = 16;
3023 num_ps_stack_entries = 85;
3024 num_vs_stack_entries = 85;
3025 num_gs_stack_entries = 85;
3026 num_es_stack_entries = 85;
3027 num_hs_stack_entries = 85;
3028 num_ls_stack_entries = 85;
3029 break;
3030 case CHIP_BARTS:
3031 num_ps_threads = 128;
3032 num_vs_threads = 20;
3033 num_gs_threads = 20;
3034 num_es_threads = 20;
3035 num_hs_threads = 20;
3036 num_ls_threads = 20;
3037 num_ps_stack_entries = 85;
3038 num_vs_stack_entries = 85;
3039 num_gs_stack_entries = 85;
3040 num_es_stack_entries = 85;
3041 num_hs_stack_entries = 85;
3042 num_ls_stack_entries = 85;
3043 break;
3044 case CHIP_TURKS:
3045 num_ps_threads = 128;
3046 num_vs_threads = 20;
3047 num_gs_threads = 20;
3048 num_es_threads = 20;
3049 num_hs_threads = 20;
3050 num_ls_threads = 20;
3051 num_ps_stack_entries = 42;
3052 num_vs_stack_entries = 42;
3053 num_gs_stack_entries = 42;
3054 num_es_stack_entries = 42;
3055 num_hs_stack_entries = 42;
3056 num_ls_stack_entries = 42;
3057 break;
3058 case CHIP_CAICOS:
3059 num_ps_threads = 96;
3060 num_vs_threads = 10;
3061 num_gs_threads = 10;
3062 num_es_threads = 10;
3063 num_hs_threads = 10;
3064 num_ls_threads = 10;
3065 num_ps_stack_entries = 42;
3066 num_vs_stack_entries = 42;
3067 num_gs_stack_entries = 42;
3068 num_es_stack_entries = 42;
3069 num_hs_stack_entries = 42;
3070 num_ls_stack_entries = 42;
3071 break;
3072 }
3073
3074 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
3075 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
3076 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
3077 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
3078
3079 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
3080 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3081
3082 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
3083 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
3084 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3085
3086 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
3087 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
3088 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3089
3090 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
3091 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
3092 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3093
3094 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
3095 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
3096 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3097
3098 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
3099 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
3100
3101 /* remove LS/HS from one SIMD for hw workaround */
3102 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
3103 r600_store_value(cb, 0xffffffff);
3104 r600_store_value(cb, 0xffffffff);
3105 r600_store_value(cb, 0xfffffffe);
3106
3107 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
3108 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
3109
3110 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
3111 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3112 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3113 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3114 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3115 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3116 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3117
3118 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3119 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3120 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3121 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3122 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3123
3124 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
3125 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3126 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
3127 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3128 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3129 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3130 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3131 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3132 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
3133 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3134 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3135 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3136 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3137 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
3138
3139 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
3140
3141 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
3142
3143 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
3144 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3145 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
3146
3147 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
3148
3149 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
3150
3151 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
3152 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3153 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3154
3155 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
3156 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
3157
3158 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
3159 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3160 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3161 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3162
3163 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
3164 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3165 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3166
3167 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
3168 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3169 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3170
3171 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3172 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3173 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3174 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3175 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
3176 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3177 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3178
3179 /* to avoid GPU doing any preloading of constant from random address */
3180 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
3181 for (i = 0; i < 16; i++)
3182 r600_store_value(cb, 0);
3183
3184 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
3185 for (i = 0; i < 16; i++)
3186 r600_store_value(cb, 0);
3187
3188 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
3189 for (i = 0; i < 16; i++)
3190 r600_store_value(cb, 0);
3191
3192 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
3193 for (i = 0; i < 16; i++)
3194 r600_store_value(cb, 0);
3195
3196 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
3197 for (i = 0; i < 16; i++)
3198 r600_store_value(cb, 0);
3199
3200 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
3201
3202 if (rctx->screen->b.has_streamout) {
3203 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3204 }
3205
3206 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
3207 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3208 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
3209 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
3210 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3211 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3212
3213 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
3214 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
3215 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
3216
3217 if (rctx->b.family == CHIP_CAICOS) {
3218 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
3219 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3220 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3221 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
3222 } else {
3223 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
3224 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3225 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3226 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
3227 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
3228 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
3229 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
3230 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
3231 }
3232
3233 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3234 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3235 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
3236 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
3237 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
3238 }
3239
3240 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3241 {
3242 struct r600_context *rctx = (struct r600_context *)ctx;
3243 struct r600_command_buffer *cb = &shader->command_buffer;
3244 struct r600_shader *rshader = &shader->shader;
3245 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
3246 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
3247 int ninterp = 0;
3248 boolean have_perspective = FALSE, have_linear = FALSE;
3249 static const unsigned spi_baryc_enable_bit[6] = {
3250 S_0286E0_PERSP_SAMPLE_ENA(1),
3251 S_0286E0_PERSP_CENTER_ENA(1),
3252 S_0286E0_PERSP_CENTROID_ENA(1),
3253 S_0286E0_LINEAR_SAMPLE_ENA(1),
3254 S_0286E0_LINEAR_CENTER_ENA(1),
3255 S_0286E0_LINEAR_CENTROID_ENA(1)
3256 };
3257 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
3258 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
3259 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3260 uint32_t spi_ps_input_cntl[32];
3261
3262 if (!cb->buf) {
3263 r600_init_command_buffer(cb, 64);
3264 } else {
3265 cb->num_dw = 0;
3266 }
3267
3268 for (i = 0; i < rshader->ninput; i++) {
3269 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3270 POSITION goes via GPRs from the SC so isn't counted */
3271 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3272 pos_index = i;
3273 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
3274 if (face_index == -1)
3275 face_index = i;
3276 }
3277 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3278 if (face_index == -1)
3279 face_index = i; /* lives in same register, same enable bit */
3280 }
3281 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) {
3282 fixed_pt_position_index = i;
3283 }
3284 else {
3285 ninterp++;
3286 int k = eg_get_interpolator_index(
3287 rshader->input[i].interpolate,
3288 rshader->input[i].interpolate_location);
3289 if (k >= 0) {
3290 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3291 have_perspective |= k < 3;
3292 have_linear |= !(k < 3);
3293 }
3294 }
3295
3296 sid = rshader->input[i].spi_sid;
3297
3298 if (sid) {
3299 tmp = S_028644_SEMANTIC(sid);
3300
3301 /* D3D 9 behaviour. GL is undefined */
3302 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
3303 tmp |= S_028644_DEFAULT_VAL(3);
3304
3305 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3306 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3307 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3308 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3309 tmp |= S_028644_FLAT_SHADE(1);
3310 }
3311
3312 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3313 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3314 tmp |= S_028644_PT_SPRITE_TEX(1);
3315 }
3316
3317 spi_ps_input_cntl[num++] = tmp;
3318 }
3319 }
3320
3321 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3322 r600_store_array(cb, num, spi_ps_input_cntl);
3323
3324 for (i = 0; i < rshader->noutput; i++) {
3325 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3326 z_export = 1;
3327 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3328 stencil_export = 1;
3329 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
3330 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
3331 mask_export = 1;
3332 }
3333 if (rshader->uses_kill)
3334 db_shader_control |= S_02880C_KILL_ENABLE(1);
3335
3336 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3337 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3338 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3339
3340 if (shader->selector->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
3341 db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
3342 S_02880C_EXEC_ON_NOOP(shader->selector->info.writes_memory);
3343 } else if (shader->selector->info.writes_memory) {
3344 db_shader_control |= S_02880C_EXEC_ON_HIER_FAIL(1);
3345 }
3346
3347 switch (rshader->ps_conservative_z) {
3348 default: /* fall through */
3349 case TGSI_FS_DEPTH_LAYOUT_ANY:
3350 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3351 break;
3352 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3353 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3354 break;
3355 case TGSI_FS_DEPTH_LAYOUT_LESS:
3356 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3357 break;
3358 }
3359
3360 exports_ps = 0;
3361 for (i = 0; i < rshader->noutput; i++) {
3362 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3363 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
3364 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK)
3365 exports_ps |= 1;
3366 }
3367
3368 num_cout = rshader->nr_ps_color_exports;
3369
3370 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3371 if (!exports_ps) {
3372 /* always at least export 1 component per pixel */
3373 exports_ps = 2;
3374 }
3375 shader->nr_ps_color_outputs = num_cout;
3376 if (ninterp == 0) {
3377 ninterp = 1;
3378 have_perspective = TRUE;
3379 }
3380 if (!spi_baryc_cntl)
3381 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3382
3383 if (!have_perspective && !have_linear)
3384 have_perspective = TRUE;
3385
3386 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3387 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3388 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3389 spi_input_z = 0;
3390 if (pos_index != -1) {
3391 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3392 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3393 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3394 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3395 }
3396
3397 spi_ps_in_control_1 = 0;
3398 if (face_index != -1) {
3399 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3400 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3401 }
3402 if (fixed_pt_position_index != -1) {
3403 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3404 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3405 }
3406
3407 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3408 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3409 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3410
3411 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3412 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3413 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3414
3415 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3416 r600_store_value(cb, shader->bo->gpu_address >> 8);
3417 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3418 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3419 S_028844_PRIME_CACHE_ON_DRAW(1) |
3420 S_028844_DX10_CLAMP(1) |
3421 S_028844_STACK_SIZE(rshader->bc.nstack));
3422 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3423
3424 shader->db_shader_control = db_shader_control;
3425 shader->ps_depth_export = z_export | stencil_export | mask_export;
3426
3427 shader->sprite_coord_enable = sprite_coord_enable;
3428 if (rctx->rasterizer)
3429 shader->flatshade = rctx->rasterizer->flatshade;
3430 }
3431
3432 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3433 {
3434 struct r600_command_buffer *cb = &shader->command_buffer;
3435 struct r600_shader *rshader = &shader->shader;
3436
3437 r600_init_command_buffer(cb, 32);
3438
3439 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3440 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3441 S_028890_DX10_CLAMP(1) |
3442 S_028890_STACK_SIZE(rshader->bc.nstack));
3443 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3444 shader->bo->gpu_address >> 8);
3445 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3446 }
3447
3448 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3449 {
3450 struct r600_context *rctx = (struct r600_context *)ctx;
3451 struct r600_command_buffer *cb = &shader->command_buffer;
3452 struct r600_shader *rshader = &shader->shader;
3453 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3454 unsigned gsvs_itemsizes[4] = {
3455 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3456 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3457 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3458 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3459 };
3460
3461 r600_init_command_buffer(cb, 64);
3462
3463 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3464
3465
3466 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3467 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3468 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3469 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3470
3471 if (rctx->screen->b.info.drm_minor >= 35) {
3472 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3473 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3474 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3475 }
3476 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3477 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3478 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3479 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3480 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3481
3482 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3483 (rshader->ring_item_sizes[0]) >> 2);
3484
3485 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3486 gsvs_itemsizes[0] +
3487 gsvs_itemsizes[1] +
3488 gsvs_itemsizes[2] +
3489 gsvs_itemsizes[3]);
3490
3491 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3492 r600_store_value(cb, gsvs_itemsizes[0]);
3493 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3494 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3495
3496 /* FIXME calculate these values somehow ??? */
3497 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3498 r600_store_value(cb, 0x80); /* GS_PER_ES */
3499 r600_store_value(cb, 0x100); /* ES_PER_GS */
3500 r600_store_value(cb, 0x2); /* GS_PER_VS */
3501
3502 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3503 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3504 S_028878_DX10_CLAMP(1) |
3505 S_028878_STACK_SIZE(rshader->bc.nstack));
3506 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3507 shader->bo->gpu_address >> 8);
3508 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3509 }
3510
3511
3512 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3513 {
3514 struct r600_command_buffer *cb = &shader->command_buffer;
3515 struct r600_shader *rshader = &shader->shader;
3516 unsigned spi_vs_out_id[10] = {};
3517 unsigned i, tmp, nparams = 0;
3518
3519 for (i = 0; i < rshader->noutput; i++) {
3520 if (rshader->output[i].spi_sid) {
3521 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3522 spi_vs_out_id[nparams / 4] |= tmp;
3523 nparams++;
3524 }
3525 }
3526
3527 r600_init_command_buffer(cb, 32);
3528
3529 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3530 for (i = 0; i < 10; i++) {
3531 r600_store_value(cb, spi_vs_out_id[i]);
3532 }
3533
3534 /* Certain attributes (position, psize, etc.) don't count as params.
3535 * VS is required to export at least one param and r600_shader_from_tgsi()
3536 * takes care of adding a dummy export.
3537 */
3538 if (nparams < 1)
3539 nparams = 1;
3540
3541 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3542 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3543 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3544 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3545 S_028860_DX10_CLAMP(1) |
3546 S_028860_STACK_SIZE(rshader->bc.nstack));
3547 if (rshader->vs_position_window_space) {
3548 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3549 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3550 } else {
3551 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3552 S_028818_VTX_W0_FMT(1) |
3553 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3554 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3555 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3556
3557 }
3558 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3559 shader->bo->gpu_address >> 8);
3560 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3561
3562 shader->pa_cl_vs_out_cntl =
3563 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->cc_dist_mask & 0x0F) != 0) |
3564 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->cc_dist_mask & 0xF0) != 0) |
3565 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3566 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3567 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3568 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3569 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3570 }
3571
3572 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3573 {
3574 struct r600_command_buffer *cb = &shader->command_buffer;
3575 struct r600_shader *rshader = &shader->shader;
3576
3577 r600_init_command_buffer(cb, 32);
3578 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3579 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3580 S_0288BC_DX10_CLAMP(1) |
3581 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3582 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3583 shader->bo->gpu_address >> 8);
3584 }
3585
3586 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3587 {
3588 struct r600_command_buffer *cb = &shader->command_buffer;
3589 struct r600_shader *rshader = &shader->shader;
3590
3591 r600_init_command_buffer(cb, 32);
3592 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3593 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3594 S_0288D4_DX10_CLAMP(1) |
3595 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3596 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3597 shader->bo->gpu_address >> 8);
3598 }
3599 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3600 {
3601 struct pipe_blend_state blend;
3602
3603 memset(&blend, 0, sizeof(blend));
3604 blend.independent_blend_enable = true;
3605 blend.rt[0].colormask = 0xf;
3606 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3607 }
3608
3609 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3610 {
3611 struct pipe_blend_state blend;
3612 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3613 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3614
3615 memset(&blend, 0, sizeof(blend));
3616 blend.independent_blend_enable = true;
3617 blend.rt[0].colormask = 0xf;
3618 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3619 }
3620
3621 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3622 {
3623 struct pipe_blend_state blend;
3624 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3625
3626 memset(&blend, 0, sizeof(blend));
3627 blend.independent_blend_enable = true;
3628 blend.rt[0].colormask = 0xf;
3629 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3630 }
3631
3632 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3633 {
3634 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3635
3636 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3637 }
3638
3639 void evergreen_update_db_shader_control(struct r600_context * rctx)
3640 {
3641 bool dual_export;
3642 unsigned db_shader_control;
3643
3644 if (!rctx->ps_shader) {
3645 return;
3646 }
3647
3648 dual_export = rctx->framebuffer.export_16bpc &&
3649 !rctx->ps_shader->current->ps_depth_export;
3650
3651 db_shader_control = rctx->ps_shader->current->db_shader_control |
3652 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3653 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3654 V_02880C_EXPORT_DB_FULL) |
3655 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3656
3657 /* When alpha test is enabled we can't trust the hw to make the proper
3658 * decision on the order in which ztest should be run related to fragment
3659 * shader execution.
3660 *
3661 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3662 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3663 * execution and thus after alpha test so if discarded by the alpha test
3664 * the z value is not written.
3665 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3666 * get a hang unless you flush the DB in between. For now just use
3667 * LATE_Z.
3668 */
3669 if (rctx->alphatest_state.sx_alpha_test_control || rctx->ps_shader->info.writes_memory) {
3670 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3671 } else {
3672 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3673 }
3674
3675 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3676 rctx->db_misc_state.db_shader_control = db_shader_control;
3677 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3678 }
3679 }
3680
3681 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3682 struct pipe_resource *dst,
3683 unsigned dst_level,
3684 unsigned dst_x,
3685 unsigned dst_y,
3686 unsigned dst_z,
3687 struct pipe_resource *src,
3688 unsigned src_level,
3689 unsigned src_x,
3690 unsigned src_y,
3691 unsigned src_z,
3692 unsigned copy_height,
3693 unsigned pitch,
3694 unsigned bpp)
3695 {
3696 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
3697 struct r600_texture *rsrc = (struct r600_texture*)src;
3698 struct r600_texture *rdst = (struct r600_texture*)dst;
3699 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3700 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3701 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3702 uint64_t base, addr;
3703
3704 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3705 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3706 assert(dst_mode != src_mode);
3707
3708 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3709 if (util_format_has_depth(util_format_description(src->format)))
3710 non_disp_tiling = 1;
3711
3712 y = 0;
3713 sub_cmd = EG_DMA_COPY_TILED;
3714 lbpp = util_logbase2(bpp);
3715 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3716 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3717
3718 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
3719 /* T2L */
3720 array_mode = evergreen_array_mode(src_mode);
3721 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
3722 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3723 /* linear height must be the same as the slice tile max height, it's ok even
3724 * if the linear destination/source have smaller heigh as the size of the
3725 * dma packet will be using the copy_height which is always smaller or equal
3726 * to the linear height
3727 */
3728 height = u_minify(rsrc->resource.b.b.height0, src_level);
3729 detile = 1;
3730 x = src_x;
3731 y = src_y;
3732 z = src_z;
3733 base = rsrc->surface.u.legacy.level[src_level].offset;
3734 addr = rdst->surface.u.legacy.level[dst_level].offset;
3735 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3736 addr += dst_y * pitch + dst_x * bpp;
3737 bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh);
3738 bank_w = eg_bank_wh(rsrc->surface.u.legacy.bankw);
3739 mt_aspect = eg_macro_tile_aspect(rsrc->surface.u.legacy.mtilea);
3740 tile_split = eg_tile_split(rsrc->surface.u.legacy.tile_split);
3741 base += rsrc->resource.gpu_address;
3742 addr += rdst->resource.gpu_address;
3743 } else {
3744 /* L2T */
3745 array_mode = evergreen_array_mode(dst_mode);
3746 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
3747 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3748 /* linear height must be the same as the slice tile max height, it's ok even
3749 * if the linear destination/source have smaller heigh as the size of the
3750 * dma packet will be using the copy_height which is always smaller or equal
3751 * to the linear height
3752 */
3753 height = u_minify(rdst->resource.b.b.height0, dst_level);
3754 detile = 0;
3755 x = dst_x;
3756 y = dst_y;
3757 z = dst_z;
3758 base = rdst->surface.u.legacy.level[dst_level].offset;
3759 addr = rsrc->surface.u.legacy.level[src_level].offset;
3760 addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z;
3761 addr += src_y * pitch + src_x * bpp;
3762 bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh);
3763 bank_w = eg_bank_wh(rdst->surface.u.legacy.bankw);
3764 mt_aspect = eg_macro_tile_aspect(rdst->surface.u.legacy.mtilea);
3765 tile_split = eg_tile_split(rdst->surface.u.legacy.tile_split);
3766 base += rdst->resource.gpu_address;
3767 addr += rsrc->resource.gpu_address;
3768 }
3769
3770 size = (copy_height * pitch) / 4;
3771 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3772 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
3773
3774 for (i = 0; i < ncopy; i++) {
3775 cheight = copy_height;
3776 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3777 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3778 }
3779 size = (cheight * pitch) / 4;
3780 /* emit reloc before writing cs so that cs is always in consistent state */
3781 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3782 RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
3783 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3784 RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
3785 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size));
3786 radeon_emit(cs, base >> 8);
3787 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
3788 (lbpp << 24) | (bank_h << 21) |
3789 (bank_w << 18) | (mt_aspect << 16));
3790 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
3791 radeon_emit(cs, (slice_tile_max << 0));
3792 radeon_emit(cs, (x << 0) | (z << 18));
3793 radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28));
3794 radeon_emit(cs, addr & 0xfffffffc);
3795 radeon_emit(cs, (addr >> 32UL) & 0xff);
3796 copy_height -= cheight;
3797 addr += cheight * pitch;
3798 y += cheight;
3799 }
3800 }
3801
3802 static void evergreen_dma_copy(struct pipe_context *ctx,
3803 struct pipe_resource *dst,
3804 unsigned dst_level,
3805 unsigned dstx, unsigned dsty, unsigned dstz,
3806 struct pipe_resource *src,
3807 unsigned src_level,
3808 const struct pipe_box *src_box)
3809 {
3810 struct r600_context *rctx = (struct r600_context *)ctx;
3811 struct r600_texture *rsrc = (struct r600_texture*)src;
3812 struct r600_texture *rdst = (struct r600_texture*)dst;
3813 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3814 unsigned src_w, dst_w;
3815 unsigned src_x, src_y;
3816 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3817
3818 if (rctx->b.dma.cs == NULL) {
3819 goto fallback;
3820 }
3821
3822 if (rctx->cmd_buf_is_compute) {
3823 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
3824 rctx->cmd_buf_is_compute = false;
3825 }
3826
3827 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3828 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3829 return;
3830 }
3831
3832 if (src_box->depth > 1 ||
3833 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3834 dstz, rsrc, src_level, src_box))
3835 goto fallback;
3836
3837 src_x = util_format_get_nblocksx(src->format, src_box->x);
3838 dst_x = util_format_get_nblocksx(src->format, dst_x);
3839 src_y = util_format_get_nblocksy(src->format, src_box->y);
3840 dst_y = util_format_get_nblocksy(src->format, dst_y);
3841
3842 bpp = rdst->surface.bpe;
3843 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
3844 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
3845 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
3846 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
3847 copy_height = src_box->height / rsrc->surface.blk_h;
3848
3849 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3850 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3851
3852 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3853 /* FIXME evergreen can do partial blit */
3854 goto fallback;
3855 }
3856 /* the x test here are currently useless (because we don't support partial blit)
3857 * but keep them around so we don't forget about those
3858 */
3859 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3860 goto fallback;
3861 }
3862
3863 /* 128 bpp surfaces require non_disp_tiling for both
3864 * tiled and linear buffers on cayman. However, async
3865 * DMA only supports it on the tiled side. As such
3866 * the tile order is backwards after a L2T/T2L packet.
3867 */
3868 if ((rctx->b.chip_class == CAYMAN) &&
3869 (src_mode != dst_mode) &&
3870 (util_format_get_blocksize(src->format) >= 16)) {
3871 goto fallback;
3872 }
3873
3874 if (src_mode == dst_mode) {
3875 uint64_t dst_offset, src_offset;
3876 /* simple dma blit would do NOTE code here assume :
3877 * src_box.x/y == 0
3878 * dst_x/y == 0
3879 * dst_pitch == src_pitch
3880 */
3881 src_offset= rsrc->surface.u.legacy.level[src_level].offset;
3882 src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
3883 src_offset += src_y * src_pitch + src_x * bpp;
3884 dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
3885 dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3886 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3887 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3888 src_box->height * src_pitch);
3889 } else {
3890 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3891 src, src_level, src_x, src_y, src_box->z,
3892 copy_height, dst_pitch, bpp);
3893 }
3894 return;
3895
3896 fallback:
3897 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3898 src, src_level, src_box);
3899 }
3900
3901 static void evergreen_set_tess_state(struct pipe_context *ctx,
3902 const float default_outer_level[4],
3903 const float default_inner_level[2])
3904 {
3905 struct r600_context *rctx = (struct r600_context *)ctx;
3906
3907 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3908 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3909 rctx->driver_consts[PIPE_SHADER_TESS_CTRL].tcs_default_levels_dirty = true;
3910 }
3911
3912 static void evergreen_setup_immed_buffer(struct r600_context *rctx,
3913 struct r600_image_view *rview,
3914 enum pipe_format pformat)
3915 {
3916 struct r600_screen *rscreen = (struct r600_screen *)rctx->b.b.screen;
3917 uint32_t immed_size = rscreen->b.info.max_se * 256 * 64 * util_format_get_blocksize(pformat);
3918 struct eg_buf_res_params buf_params;
3919 bool skip_reloc = false;
3920 struct r600_resource *resource = (struct r600_resource *)rview->base.resource;
3921 if (!resource->immed_buffer) {
3922 eg_resource_alloc_immed(&rscreen->b, resource, immed_size);
3923 }
3924
3925 memset(&buf_params, 0, sizeof(buf_params));
3926 buf_params.pipe_format = pformat;
3927 buf_params.size = resource->immed_buffer->b.b.width0;
3928 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
3929 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
3930 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
3931 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
3932 buf_params.uncached = 1;
3933 evergreen_fill_buffer_resource_words(rctx, &resource->immed_buffer->b.b,
3934 &buf_params, &skip_reloc,
3935 rview->immed_resource_words);
3936 }
3937
3938 static void evergreen_set_hw_atomic_buffers(struct pipe_context *ctx,
3939 unsigned start_slot,
3940 unsigned count,
3941 const struct pipe_shader_buffer *buffers)
3942 {
3943 struct r600_context *rctx = (struct r600_context *)ctx;
3944 struct r600_atomic_buffer_state *astate;
3945 int i, idx;
3946
3947 astate = &rctx->atomic_buffer_state;
3948
3949 /* we'd probably like to expand this to 8 later so put the logic in */
3950 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
3951 const struct pipe_shader_buffer *buf;
3952 struct pipe_shader_buffer *abuf;
3953
3954 abuf = &astate->buffer[i];
3955
3956 if (!buffers || !buffers[idx].buffer) {
3957 pipe_resource_reference(&abuf->buffer, NULL);
3958 astate->enabled_mask &= ~(1 << i);
3959 continue;
3960 }
3961 buf = &buffers[idx];
3962
3963 pipe_resource_reference(&abuf->buffer, buf->buffer);
3964 abuf->buffer_offset = buf->buffer_offset;
3965 abuf->buffer_size = buf->buffer_size;
3966 astate->enabled_mask |= (1 << i);
3967 }
3968 }
3969
3970 static void evergreen_set_shader_buffers(struct pipe_context *ctx,
3971 enum pipe_shader_type shader, unsigned start_slot,
3972 unsigned count,
3973 const struct pipe_shader_buffer *buffers)
3974 {
3975 struct r600_context *rctx = (struct r600_context *)ctx;
3976 struct r600_image_state *istate = NULL;
3977 struct r600_image_view *rview;
3978 struct r600_tex_color_info color;
3979 struct eg_buf_res_params buf_params;
3980 struct r600_resource *resource;
3981 int i, idx;
3982 unsigned old_mask;
3983
3984 if (shader != PIPE_SHADER_FRAGMENT &&
3985 shader != PIPE_SHADER_COMPUTE && count == 0)
3986 return;
3987
3988 if (shader == PIPE_SHADER_FRAGMENT)
3989 istate = &rctx->fragment_buffers;
3990 else if (shader == PIPE_SHADER_COMPUTE)
3991 istate = &rctx->compute_buffers;
3992
3993 old_mask = istate->enabled_mask;
3994 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
3995 const struct pipe_shader_buffer *buf;
3996 unsigned res_type;
3997
3998 rview = &istate->views[i];
3999
4000 if (!buffers || !buffers[idx].buffer) {
4001 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
4002 istate->enabled_mask &= ~(1 << i);
4003 continue;
4004 }
4005
4006 buf = &buffers[idx];
4007 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, buf->buffer);
4008
4009 resource = (struct r600_resource *)rview->base.resource;
4010
4011 evergreen_setup_immed_buffer(rctx, rview, PIPE_FORMAT_R32_UINT);
4012
4013 color.offset = 0;
4014 color.view = 0;
4015 evergreen_set_color_surface_buffer(rctx, resource,
4016 PIPE_FORMAT_R32_UINT,
4017 buf->buffer_offset,
4018 buf->buffer_offset + buf->buffer_size,
4019 &color);
4020
4021 res_type = V_028C70_BUFFER;
4022
4023 rview->cb_color_base = color.offset;
4024 rview->cb_color_dim = color.dim;
4025 rview->cb_color_info = color.info |
4026 S_028C70_RAT(1) |
4027 S_028C70_RESOURCE_TYPE(res_type);
4028 rview->cb_color_pitch = color.pitch;
4029 rview->cb_color_slice = color.slice;
4030 rview->cb_color_view = color.view;
4031 rview->cb_color_attrib = color.attrib;
4032 rview->cb_color_fmask = color.fmask;
4033 rview->cb_color_fmask_slice = color.fmask_slice;
4034
4035 memset(&buf_params, 0, sizeof(buf_params));
4036 buf_params.pipe_format = PIPE_FORMAT_R32_UINT;
4037 buf_params.offset = buf->buffer_offset;
4038 buf_params.size = buf->buffer_size;
4039 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
4040 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
4041 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
4042 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
4043 buf_params.force_swizzle = true;
4044 buf_params.uncached = 1;
4045 buf_params.size_in_bytes = true;
4046 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4047 &buf_params,
4048 &rview->skip_mip_address_reloc,
4049 rview->resource_words);
4050
4051 istate->enabled_mask |= (1 << i);
4052 }
4053
4054 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
4055
4056 if (old_mask != istate->enabled_mask)
4057 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4058
4059 /* construct the target mask */
4060 if (rctx->cb_misc_state.buffer_rat_enabled_mask != istate->enabled_mask) {
4061 rctx->cb_misc_state.buffer_rat_enabled_mask = istate->enabled_mask;
4062 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4063 }
4064
4065 if (shader == PIPE_SHADER_FRAGMENT)
4066 r600_mark_atom_dirty(rctx, &istate->atom);
4067 }
4068
4069 static void evergreen_set_shader_images(struct pipe_context *ctx,
4070 enum pipe_shader_type shader, unsigned start_slot,
4071 unsigned count,
4072 const struct pipe_image_view *images)
4073 {
4074 struct r600_context *rctx = (struct r600_context *)ctx;
4075 int i;
4076 struct r600_image_view *rview;
4077 struct pipe_resource *image;
4078 struct r600_resource *resource;
4079 struct r600_tex_color_info color;
4080 struct eg_buf_res_params buf_params;
4081 struct eg_tex_res_params tex_params;
4082 unsigned old_mask;
4083 struct r600_image_state *istate = NULL;
4084 int idx;
4085 if (shader != PIPE_SHADER_FRAGMENT && shader != PIPE_SHADER_COMPUTE && count == 0)
4086 return;
4087
4088 if (shader == PIPE_SHADER_FRAGMENT)
4089 istate = &rctx->fragment_images;
4090 else if (shader == PIPE_SHADER_COMPUTE)
4091 istate = &rctx->compute_images;
4092
4093 assert (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE);
4094
4095 old_mask = istate->enabled_mask;
4096 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4097 unsigned res_type;
4098 const struct pipe_image_view *iview;
4099 rview = &istate->views[i];
4100
4101 if (!images || !images[idx].resource) {
4102 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
4103 istate->enabled_mask &= ~(1 << i);
4104 istate->compressed_colortex_mask &= ~(1 << i);
4105 istate->compressed_depthtex_mask &= ~(1 << i);
4106 continue;
4107 }
4108
4109 iview = &images[idx];
4110 image = iview->resource;
4111 resource = (struct r600_resource *)image;
4112
4113 r600_context_add_resource_size(ctx, image);
4114
4115 rview->base = *iview;
4116 rview->base.resource = NULL;
4117 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, image);
4118
4119 evergreen_setup_immed_buffer(rctx, rview, iview->format);
4120
4121 bool is_buffer = image->target == PIPE_BUFFER;
4122 struct r600_texture *rtex = (struct r600_texture *)image;
4123 if (!is_buffer & rtex->db_compatible)
4124 istate->compressed_depthtex_mask |= 1 << i;
4125 else
4126 istate->compressed_depthtex_mask &= ~(1 << i);
4127
4128 if (!is_buffer && rtex->cmask.size)
4129 istate->compressed_colortex_mask |= 1 << i;
4130 else
4131 istate->compressed_colortex_mask &= ~(1 << i);
4132 if (!is_buffer) {
4133
4134 evergreen_set_color_surface_common(rctx, rtex,
4135 iview->u.tex.level,
4136 iview->u.tex.first_layer,
4137 iview->u.tex.last_layer,
4138 iview->format,
4139 &color);
4140 color.dim = S_028C78_WIDTH_MAX(u_minify(image->width0, iview->u.tex.level) - 1) |
4141 S_028C78_HEIGHT_MAX(u_minify(image->height0, iview->u.tex.level) - 1);
4142 } else {
4143 color.offset = 0;
4144 color.view = 0;
4145 evergreen_set_color_surface_buffer(rctx, resource,
4146 iview->format,
4147 iview->u.buf.offset,
4148 iview->u.buf.size,
4149 &color);
4150 }
4151
4152 switch (image->target) {
4153 case PIPE_BUFFER:
4154 res_type = V_028C70_BUFFER;
4155 break;
4156 case PIPE_TEXTURE_1D:
4157 res_type = V_028C70_TEXTURE1D;
4158 break;
4159 case PIPE_TEXTURE_1D_ARRAY:
4160 res_type = V_028C70_TEXTURE1DARRAY;
4161 break;
4162 case PIPE_TEXTURE_2D:
4163 case PIPE_TEXTURE_RECT:
4164 res_type = V_028C70_TEXTURE2D;
4165 break;
4166 case PIPE_TEXTURE_3D:
4167 res_type = V_028C70_TEXTURE3D;
4168 break;
4169 case PIPE_TEXTURE_2D_ARRAY:
4170 case PIPE_TEXTURE_CUBE:
4171 case PIPE_TEXTURE_CUBE_ARRAY:
4172 res_type = V_028C70_TEXTURE2DARRAY;
4173 break;
4174 default:
4175 assert(0);
4176 res_type = 0;
4177 break;
4178 }
4179
4180 rview->cb_color_base = color.offset;
4181 rview->cb_color_dim = color.dim;
4182 rview->cb_color_info = color.info |
4183 S_028C70_RAT(1) |
4184 S_028C70_RESOURCE_TYPE(res_type);
4185 rview->cb_color_pitch = color.pitch;
4186 rview->cb_color_slice = color.slice;
4187 rview->cb_color_view = color.view;
4188 rview->cb_color_attrib = color.attrib;
4189 rview->cb_color_fmask = color.fmask;
4190 rview->cb_color_fmask_slice = color.fmask_slice;
4191
4192 if (image->target != PIPE_BUFFER) {
4193 memset(&tex_params, 0, sizeof(tex_params));
4194 tex_params.pipe_format = iview->format;
4195 tex_params.force_level = 0;
4196 tex_params.width0 = image->width0;
4197 tex_params.height0 = image->height0;
4198 tex_params.first_level = iview->u.tex.level;
4199 tex_params.last_level = iview->u.tex.level;
4200 tex_params.first_layer = iview->u.tex.first_layer;
4201 tex_params.last_layer = iview->u.tex.last_layer;
4202 tex_params.target = image->target;
4203 tex_params.swizzle[0] = PIPE_SWIZZLE_X;
4204 tex_params.swizzle[1] = PIPE_SWIZZLE_Y;
4205 tex_params.swizzle[2] = PIPE_SWIZZLE_Z;
4206 tex_params.swizzle[3] = PIPE_SWIZZLE_W;
4207 evergreen_fill_tex_resource_words(rctx, &resource->b.b, &tex_params,
4208 &rview->skip_mip_address_reloc,
4209 rview->resource_words);
4210
4211 } else {
4212 memset(&buf_params, 0, sizeof(buf_params));
4213 buf_params.pipe_format = iview->format;
4214 buf_params.size = iview->u.buf.size;
4215 buf_params.offset = iview->u.buf.offset;
4216 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
4217 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
4218 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
4219 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
4220 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4221 &buf_params,
4222 &rview->skip_mip_address_reloc,
4223 rview->resource_words);
4224 }
4225 istate->enabled_mask |= (1 << i);
4226 }
4227
4228 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
4229 istate->dirty_buffer_constants = TRUE;
4230 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
4231 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
4232 R600_CONTEXT_FLUSH_AND_INV_CB_META;
4233
4234 if (old_mask != istate->enabled_mask)
4235 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4236
4237 if (rctx->cb_misc_state.image_rat_enabled_mask != istate->enabled_mask) {
4238 rctx->cb_misc_state.image_rat_enabled_mask = istate->enabled_mask;
4239 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4240 }
4241
4242 if (shader == PIPE_SHADER_FRAGMENT)
4243 r600_mark_atom_dirty(rctx, &istate->atom);
4244 }
4245
4246 static void evergreen_get_pipe_constant_buffer(struct r600_context *rctx,
4247 enum pipe_shader_type shader, uint slot,
4248 struct pipe_constant_buffer *cbuf)
4249 {
4250 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
4251 struct pipe_constant_buffer *cb;
4252 cbuf->user_buffer = NULL;
4253
4254 cb = &state->cb[slot];
4255
4256 cbuf->buffer_size = cb->buffer_size;
4257 pipe_resource_reference(&cbuf->buffer, cb->buffer);
4258 }
4259
4260 static void evergreen_get_shader_buffers(struct r600_context *rctx,
4261 enum pipe_shader_type shader,
4262 uint start_slot, uint count,
4263 struct pipe_shader_buffer *sbuf)
4264 {
4265 assert(shader == PIPE_SHADER_COMPUTE);
4266 int idx, i;
4267 struct r600_image_state *istate = &rctx->compute_buffers;
4268 struct r600_image_view *rview;
4269
4270 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4271
4272 rview = &istate->views[i];
4273
4274 pipe_resource_reference(&sbuf[idx].buffer, rview->base.resource);
4275 if (rview->base.resource) {
4276 uint64_t rview_va = ((struct r600_resource *)rview->base.resource)->gpu_address;
4277
4278 uint64_t prog_va = rview->resource_words[0];
4279
4280 prog_va += ((uint64_t)G_030008_BASE_ADDRESS_HI(rview->resource_words[2])) << 32;
4281 prog_va -= rview_va;
4282
4283 sbuf[idx].buffer_offset = prog_va & 0xffffffff;
4284 sbuf[idx].buffer_size = rview->resource_words[1] + 1;;
4285 } else {
4286 sbuf[idx].buffer_offset = 0;
4287 sbuf[idx].buffer_size = 0;
4288 }
4289 }
4290 }
4291
4292 static void evergreen_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
4293 {
4294 struct r600_context *rctx = (struct r600_context *)ctx;
4295 st->saved_compute = rctx->cs_shader_state.shader;
4296
4297 /* save constant buffer 0 */
4298 evergreen_get_pipe_constant_buffer(rctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
4299 /* save ssbo 0 */
4300 evergreen_get_shader_buffers(rctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
4301 }
4302
4303
4304 void evergreen_init_state_functions(struct r600_context *rctx)
4305 {
4306 unsigned id = 1;
4307 unsigned i;
4308 /* !!!
4309 * To avoid GPU lockup registers must be emitted in a specific order
4310 * (no kidding ...). The order below is important and have been
4311 * partially inferred from analyzing fglrx command stream.
4312 *
4313 * Don't reorder atom without carefully checking the effect (GPU lockup
4314 * or piglit regression).
4315 * !!!
4316 */
4317 if (rctx->b.chip_class == EVERGREEN) {
4318 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
4319 rctx->config_state.dyn_gpr_enabled = true;
4320 }
4321 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
4322 r600_init_atom(rctx, &rctx->fragment_images.atom, id++, evergreen_emit_fragment_image_state, 0);
4323 r600_init_atom(rctx, &rctx->compute_images.atom, id++, evergreen_emit_compute_image_state, 0);
4324 r600_init_atom(rctx, &rctx->fragment_buffers.atom, id++, evergreen_emit_fragment_buffer_state, 0);
4325 r600_init_atom(rctx, &rctx->compute_buffers.atom, id++, evergreen_emit_compute_buffer_state, 0);
4326 /* shader const */
4327 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
4328 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
4329 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
4330 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
4331 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
4332 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
4333 /* shader program */
4334 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
4335 /* sampler */
4336 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
4337 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
4338 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
4339 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
4340 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
4341 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
4342 /* resources */
4343 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
4344 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
4345 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
4346 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
4347 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
4348 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
4349 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
4350 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
4351
4352 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
4353
4354 if (rctx->b.chip_class == EVERGREEN) {
4355 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
4356 } else {
4357 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
4358 }
4359 rctx->sample_mask.sample_mask = ~0;
4360
4361 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
4362 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
4363 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
4364 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
4365 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
4366 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
4367 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
4368 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
4369 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
4370 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9);
4371 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
4372 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
4373 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
4374 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
4375 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
4376 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
4377 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
4378 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
4379 for (i = 0; i < EG_NUM_HW_STAGES; i++)
4380 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
4381 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
4382 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
4383
4384 rctx->b.b.create_blend_state = evergreen_create_blend_state;
4385 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
4386 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
4387 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
4388 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
4389 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
4390 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
4391 rctx->b.b.set_min_samples = evergreen_set_min_samples;
4392 rctx->b.b.set_tess_state = evergreen_set_tess_state;
4393 rctx->b.b.set_hw_atomic_buffers = evergreen_set_hw_atomic_buffers;
4394 rctx->b.b.set_shader_images = evergreen_set_shader_images;
4395 rctx->b.b.set_shader_buffers = evergreen_set_shader_buffers;
4396 if (rctx->b.chip_class == EVERGREEN)
4397 rctx->b.b.get_sample_position = evergreen_get_sample_position;
4398 else
4399 rctx->b.b.get_sample_position = cayman_get_sample_position;
4400 rctx->b.dma_copy = evergreen_dma_copy;
4401 rctx->b.save_qbo_state = evergreen_save_qbo_state;
4402
4403 evergreen_init_compute_state_functions(rctx);
4404 }
4405
4406 /**
4407 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
4408 *
4409 * The information about LDS and other non-compile-time parameters is then
4410 * written to the const buffer.
4411
4412 * const buffer contains -
4413 * uint32_t input_patch_size
4414 * uint32_t input_vertex_size
4415 * uint32_t num_tcs_input_cp
4416 * uint32_t num_tcs_output_cp;
4417 * uint32_t output_patch_size
4418 * uint32_t output_vertex_size
4419 * uint32_t output_patch0_offset
4420 * uint32_t perpatch_output_offset
4421 * and the same constbuf is bound to LS/HS/VS(ES).
4422 */
4423 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
4424 {
4425 struct pipe_constant_buffer constbuf = {0};
4426 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
4427 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
4428 unsigned num_tcs_input_cp = info->vertices_per_patch;
4429 unsigned num_tcs_outputs;
4430 unsigned num_tcs_output_cp;
4431 unsigned num_tcs_patch_outputs;
4432 unsigned num_tcs_inputs;
4433 unsigned input_vertex_size, output_vertex_size;
4434 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
4435 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
4436 uint32_t values[8];
4437 unsigned num_waves;
4438 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
4439 unsigned wave_divisor = (16 * num_pipes);
4440
4441 *num_patches = 1;
4442
4443 if (!rctx->tes_shader) {
4444 rctx->lds_alloc = 0;
4445 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4446 R600_LDS_INFO_CONST_BUFFER, NULL);
4447 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4448 R600_LDS_INFO_CONST_BUFFER, NULL);
4449 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4450 R600_LDS_INFO_CONST_BUFFER, NULL);
4451 return;
4452 }
4453
4454 if (rctx->lds_alloc != 0 &&
4455 rctx->last_ls == ls &&
4456 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
4457 rctx->last_tcs == tcs)
4458 return;
4459
4460 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
4461
4462 if (rctx->tcs_shader) {
4463 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
4464 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
4465 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
4466 } else {
4467 num_tcs_outputs = num_tcs_inputs;
4468 num_tcs_output_cp = num_tcs_input_cp;
4469 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
4470 }
4471
4472 /* size in bytes */
4473 input_vertex_size = num_tcs_inputs * 16;
4474 output_vertex_size = num_tcs_outputs * 16;
4475
4476 input_patch_size = num_tcs_input_cp * input_vertex_size;
4477
4478 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
4479 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
4480
4481 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
4482 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
4483
4484 lds_size = output_patch0_offset + output_patch_size * *num_patches;
4485
4486 values[0] = input_patch_size;
4487 values[1] = input_vertex_size;
4488 values[2] = num_tcs_input_cp;
4489 values[3] = num_tcs_output_cp;
4490
4491 values[4] = output_patch_size;
4492 values[5] = output_vertex_size;
4493 values[6] = output_patch0_offset;
4494 values[7] = perpatch_output_offset;
4495
4496 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
4497 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
4498 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
4499
4500 rctx->lds_alloc = (lds_size | (num_waves << 14));
4501
4502 rctx->last_ls = ls;
4503 rctx->last_tcs = tcs;
4504 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
4505
4506 constbuf.user_buffer = values;
4507 constbuf.buffer_size = 8 * 4;
4508
4509 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4510 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4511 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4512 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4513 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4514 R600_LDS_INFO_CONST_BUFFER, &constbuf);
4515 pipe_resource_reference(&constbuf.buffer, NULL);
4516 }
4517
4518 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
4519 const struct pipe_draw_info *info,
4520 unsigned num_patches)
4521 {
4522 unsigned num_output_cp;
4523
4524 if (!rctx->tes_shader)
4525 return 0;
4526
4527 num_output_cp = rctx->tcs_shader ?
4528 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
4529 info->vertices_per_patch;
4530
4531 return S_028B58_NUM_PATCHES(num_patches) |
4532 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
4533 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
4534 }
4535
4536 void evergreen_set_ls_hs_config(struct r600_context *rctx,
4537 struct radeon_winsys_cs *cs,
4538 uint32_t ls_hs_config)
4539 {
4540 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
4541 }
4542
4543 void evergreen_set_lds_alloc(struct r600_context *rctx,
4544 struct radeon_winsys_cs *cs,
4545 uint32_t lds_alloc)
4546 {
4547 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
4548 }
4549
4550 /* on evergreen if you are running tessellation you need to disable dynamic
4551 GPRs to workaround a hardware bug.*/
4552 bool evergreen_adjust_gprs(struct r600_context *rctx)
4553 {
4554 unsigned num_gprs[EG_NUM_HW_STAGES];
4555 unsigned def_gprs[EG_NUM_HW_STAGES];
4556 unsigned cur_gprs[EG_NUM_HW_STAGES];
4557 unsigned new_gprs[EG_NUM_HW_STAGES];
4558 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
4559 unsigned max_gprs;
4560 unsigned i;
4561 unsigned total_gprs;
4562 unsigned tmp[3];
4563 bool rework = false, set_default = false, set_dirty = false;
4564 max_gprs = 0;
4565 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4566 def_gprs[i] = rctx->default_gprs[i];
4567 max_gprs += def_gprs[i];
4568 }
4569 max_gprs += def_num_clause_temp_gprs * 2;
4570
4571 /* if we have no TESS and dyn gpr is enabled then do nothing. */
4572 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
4573 if (rctx->config_state.dyn_gpr_enabled)
4574 return true;
4575
4576 /* transition back to dyn gpr enabled state */
4577 rctx->config_state.dyn_gpr_enabled = true;
4578 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4579 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4580 return true;
4581 }
4582
4583
4584 /* gather required shader gprs */
4585 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4586 if (rctx->hw_shader_stages[i].shader)
4587 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
4588 else
4589 num_gprs[i] = 0;
4590 }
4591
4592 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4593 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4594 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4595 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4596 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4597 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4598
4599 total_gprs = 0;
4600 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4601 new_gprs[i] = num_gprs[i];
4602 total_gprs += num_gprs[i];
4603 }
4604
4605 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
4606 return false;
4607
4608 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4609 if (new_gprs[i] > cur_gprs[i]) {
4610 rework = true;
4611 break;
4612 }
4613 }
4614
4615 if (rctx->config_state.dyn_gpr_enabled) {
4616 set_dirty = true;
4617 rctx->config_state.dyn_gpr_enabled = false;
4618 }
4619
4620 if (rework) {
4621 set_default = true;
4622 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4623 if (new_gprs[i] > def_gprs[i])
4624 set_default = false;
4625 }
4626
4627 if (set_default) {
4628 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4629 new_gprs[i] = def_gprs[i];
4630 }
4631 } else {
4632 unsigned ps_value = max_gprs;
4633
4634 ps_value -= (def_num_clause_temp_gprs * 2);
4635 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
4636 ps_value -= new_gprs[i];
4637
4638 new_gprs[R600_HW_STAGE_PS] = ps_value;
4639 }
4640
4641 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
4642 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
4643 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
4644
4645 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
4646 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
4647
4648 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
4649 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
4650
4651 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
4652 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
4653 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
4654 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
4655 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
4656 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
4657 set_dirty = true;
4658 }
4659 }
4660
4661
4662 if (set_dirty) {
4663 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4664 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4665 }
4666 return true;
4667 }
4668
4669 #define AC_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
4670
4671 void eg_trace_emit(struct r600_context *rctx)
4672 {
4673 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4674 unsigned reloc;
4675
4676 if (rctx->b.chip_class < EVERGREEN)
4677 return;
4678
4679 /* This must be done after r600_need_cs_space. */
4680 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4681 (struct r600_resource*)rctx->trace_buf, RADEON_USAGE_WRITE,
4682 RADEON_PRIO_CP_DMA);
4683
4684 rctx->trace_id++;
4685 radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rctx->trace_buf,
4686 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
4687 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
4688 radeon_emit(cs, rctx->trace_buf->gpu_address);
4689 radeon_emit(cs, rctx->trace_buf->gpu_address >> 32 | MEM_WRITE_32_BITS | MEM_WRITE_CONFIRM);
4690 radeon_emit(cs, rctx->trace_id);
4691 radeon_emit(cs, 0);
4692 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4693 radeon_emit(cs, reloc);
4694 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4695 radeon_emit(cs, AC_ENCODE_TRACE_POINT(rctx->trace_id));
4696 }
4697
4698 static void evergreen_emit_set_append_cnt(struct r600_context *rctx,
4699 struct r600_shader_atomic *atomic,
4700 struct r600_resource *resource,
4701 uint32_t pkt_flags)
4702 {
4703 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4704 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4705 resource,
4706 RADEON_USAGE_READ,
4707 RADEON_PRIO_SHADER_RW_BUFFER);
4708 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4709 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4710
4711 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4 - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
4712
4713 radeon_emit(cs, PKT3(PKT3_SET_APPEND_CNT, 2, 0) | pkt_flags);
4714 radeon_emit(cs, (reg_val << 16) | 0x3);
4715 radeon_emit(cs, dst_offset & 0xfffffffc);
4716 radeon_emit(cs, (dst_offset >> 32) & 0xff);
4717 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4718 radeon_emit(cs, reloc);
4719 }
4720
4721 static void evergreen_emit_event_write_eos(struct r600_context *rctx,
4722 struct r600_shader_atomic *atomic,
4723 struct r600_resource *resource,
4724 uint32_t pkt_flags)
4725 {
4726 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4727 uint32_t event = EVENT_TYPE_PS_DONE;
4728 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4729 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4730 resource,
4731 RADEON_USAGE_WRITE,
4732 RADEON_PRIO_SHADER_RW_BUFFER);
4733 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4734 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4) >> 2;
4735
4736 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4737 event = EVENT_TYPE_CS_DONE;
4738
4739 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4740 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4741 radeon_emit(cs, (dst_offset) & 0xffffffff);
4742 radeon_emit(cs, (0 << 29) | ((dst_offset >> 32) & 0xff));
4743 radeon_emit(cs, reg_val);
4744 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4745 radeon_emit(cs, reloc);
4746 }
4747
4748 static void cayman_emit_event_write_eos(struct r600_context *rctx,
4749 struct r600_shader_atomic *atomic,
4750 struct r600_resource *resource,
4751 uint32_t pkt_flags)
4752 {
4753 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4754 uint32_t event = EVENT_TYPE_PS_DONE;
4755 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4756 resource,
4757 RADEON_USAGE_WRITE,
4758 RADEON_PRIO_SHADER_RW_BUFFER);
4759 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4760
4761 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4762 event = EVENT_TYPE_CS_DONE;
4763
4764 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4765 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4766 radeon_emit(cs, (dst_offset) & 0xffffffff);
4767 radeon_emit(cs, (1 << 29) | ((dst_offset >> 32) & 0xff));
4768 radeon_emit(cs, (atomic->hw_idx) | (1 << 16));
4769 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4770 radeon_emit(cs, reloc);
4771 }
4772
4773 /* writes count from a buffer into GDS */
4774 static void cayman_write_count_to_gds(struct r600_context *rctx,
4775 struct r600_shader_atomic *atomic,
4776 struct r600_resource *resource,
4777 uint32_t pkt_flags)
4778 {
4779 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4780 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4781 resource,
4782 RADEON_USAGE_READ,
4783 RADEON_PRIO_SHADER_RW_BUFFER);
4784 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4785
4786 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0) | pkt_flags);
4787 radeon_emit(cs, dst_offset & 0xffffffff);
4788 radeon_emit(cs, PKT3_CP_DMA_CP_SYNC | PKT3_CP_DMA_DST_SEL(1) | ((dst_offset >> 32) & 0xff));// GDS
4789 radeon_emit(cs, atomic->hw_idx * 4);
4790 radeon_emit(cs, 0);
4791 radeon_emit(cs, PKT3_CP_DMA_CMD_DAS | 4);
4792 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4793 radeon_emit(cs, reloc);
4794 }
4795
4796 bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
4797 struct r600_pipe_shader *cs_shader,
4798 struct r600_shader_atomic *combined_atomics,
4799 uint8_t *atomic_used_mask_p)
4800 {
4801 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4802 unsigned pkt_flags = 0;
4803 uint8_t atomic_used_mask = 0;
4804 int i, j, k;
4805 bool is_compute = cs_shader ? true : false;
4806
4807 if (is_compute)
4808 pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
4809
4810 for (i = 0; i < (is_compute ? 1 : EG_NUM_HW_STAGES); i++) {
4811 uint8_t num_atomic_stage;
4812 struct r600_pipe_shader *pshader;
4813
4814 if (is_compute)
4815 pshader = cs_shader;
4816 else
4817 pshader = rctx->hw_shader_stages[i].shader;
4818 if (!pshader)
4819 continue;
4820
4821 num_atomic_stage = pshader->shader.nhwatomic_ranges;
4822 if (!num_atomic_stage)
4823 continue;
4824
4825 for (j = 0; j < num_atomic_stage; j++) {
4826 struct r600_shader_atomic *atomic = &pshader->shader.atomics[j];
4827 int natomics = atomic->end - atomic->start + 1;
4828
4829 for (k = 0; k < natomics; k++) {
4830 /* seen this in a previous stage */
4831 if (atomic_used_mask & (1u << (atomic->hw_idx + k)))
4832 continue;
4833
4834 combined_atomics[atomic->hw_idx + k].hw_idx = atomic->hw_idx + k;
4835 combined_atomics[atomic->hw_idx + k].buffer_id = atomic->buffer_id;
4836 combined_atomics[atomic->hw_idx + k].start = atomic->start + k;
4837 combined_atomics[atomic->hw_idx + k].end = combined_atomics[atomic->hw_idx + k].start + 1;
4838 atomic_used_mask |= (1u << (atomic->hw_idx + k));
4839 }
4840 }
4841 }
4842
4843 uint32_t mask = atomic_used_mask;
4844 while (mask) {
4845 unsigned atomic_index = u_bit_scan(&mask);
4846 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
4847 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
4848 assert(resource);
4849
4850 if (rctx->b.chip_class == CAYMAN)
4851 cayman_write_count_to_gds(rctx, atomic, resource, pkt_flags);
4852 else
4853 evergreen_emit_set_append_cnt(rctx, atomic, resource, pkt_flags);
4854 }
4855 *atomic_used_mask_p = atomic_used_mask;
4856 return true;
4857 }
4858
4859 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
4860 bool is_compute,
4861 struct r600_shader_atomic *combined_atomics,
4862 uint8_t *atomic_used_mask_p)
4863 {
4864 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
4865 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4866 uint32_t pkt_flags = 0;
4867 uint32_t event = EVENT_TYPE_PS_DONE;
4868 uint32_t mask = astate->enabled_mask;
4869 uint64_t dst_offset;
4870 unsigned reloc;
4871
4872 if (is_compute)
4873 pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
4874
4875 mask = *atomic_used_mask_p;
4876 if (!mask)
4877 return;
4878
4879 while (mask) {
4880 unsigned atomic_index = u_bit_scan(&mask);
4881 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
4882 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
4883 assert(resource);
4884
4885 if (rctx->b.chip_class == CAYMAN)
4886 cayman_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
4887 else
4888 evergreen_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
4889 }
4890
4891 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4892 event = EVENT_TYPE_CS_DONE;
4893
4894 ++rctx->append_fence_id;
4895 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4896 r600_resource(rctx->append_fence),
4897 RADEON_USAGE_READWRITE,
4898 RADEON_PRIO_SHADER_RW_BUFFER);
4899 dst_offset = r600_resource(rctx->append_fence)->gpu_address;
4900 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4901 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4902 radeon_emit(cs, dst_offset & 0xffffffff);
4903 radeon_emit(cs, (2 << 29) | ((dst_offset >> 32) & 0xff));
4904 radeon_emit(cs, rctx->append_fence_id);
4905 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4906 radeon_emit(cs, reloc);
4907
4908 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0) | pkt_flags);
4909 radeon_emit(cs, WAIT_REG_MEM_GEQUAL | WAIT_REG_MEM_MEMORY | (1 << 8));
4910 radeon_emit(cs, dst_offset & 0xffffffff);
4911 radeon_emit(cs, ((dst_offset >> 32) & 0xff));
4912 radeon_emit(cs, rctx->append_fence_id);
4913 radeon_emit(cs, 0xffffffff);
4914 radeon_emit(cs, 0xa);
4915 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4916 radeon_emit(cs, reloc);
4917 }