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Revert "r600g: rework rasterizer discard for evergreen"
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "evergreend.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30
31 static uint32_t eg_num_banks(uint32_t nbanks)
32 {
33 switch (nbanks) {
34 case 2:
35 return 0;
36 case 4:
37 return 1;
38 case 8:
39 default:
40 return 2;
41 case 16:
42 return 3;
43 }
44 }
45
46
47 static unsigned eg_tile_split(unsigned tile_split)
48 {
49 switch (tile_split) {
50 case 64: tile_split = 0; break;
51 case 128: tile_split = 1; break;
52 case 256: tile_split = 2; break;
53 case 512: tile_split = 3; break;
54 default:
55 case 1024: tile_split = 4; break;
56 case 2048: tile_split = 5; break;
57 case 4096: tile_split = 6; break;
58 }
59 return tile_split;
60 }
61
62 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
63 {
64 switch (macro_tile_aspect) {
65 default:
66 case 1: macro_tile_aspect = 0; break;
67 case 2: macro_tile_aspect = 1; break;
68 case 4: macro_tile_aspect = 2; break;
69 case 8: macro_tile_aspect = 3; break;
70 }
71 return macro_tile_aspect;
72 }
73
74 static unsigned eg_bank_wh(unsigned bankwh)
75 {
76 switch (bankwh) {
77 default:
78 case 1: bankwh = 0; break;
79 case 2: bankwh = 1; break;
80 case 4: bankwh = 2; break;
81 case 8: bankwh = 3; break;
82 }
83 return bankwh;
84 }
85
86 static uint32_t r600_translate_blend_function(int blend_func)
87 {
88 switch (blend_func) {
89 case PIPE_BLEND_ADD:
90 return V_028780_COMB_DST_PLUS_SRC;
91 case PIPE_BLEND_SUBTRACT:
92 return V_028780_COMB_SRC_MINUS_DST;
93 case PIPE_BLEND_REVERSE_SUBTRACT:
94 return V_028780_COMB_DST_MINUS_SRC;
95 case PIPE_BLEND_MIN:
96 return V_028780_COMB_MIN_DST_SRC;
97 case PIPE_BLEND_MAX:
98 return V_028780_COMB_MAX_DST_SRC;
99 default:
100 R600_ERR("Unknown blend function %d\n", blend_func);
101 assert(0);
102 break;
103 }
104 return 0;
105 }
106
107 static uint32_t r600_translate_blend_factor(int blend_fact)
108 {
109 switch (blend_fact) {
110 case PIPE_BLENDFACTOR_ONE:
111 return V_028780_BLEND_ONE;
112 case PIPE_BLENDFACTOR_SRC_COLOR:
113 return V_028780_BLEND_SRC_COLOR;
114 case PIPE_BLENDFACTOR_SRC_ALPHA:
115 return V_028780_BLEND_SRC_ALPHA;
116 case PIPE_BLENDFACTOR_DST_ALPHA:
117 return V_028780_BLEND_DST_ALPHA;
118 case PIPE_BLENDFACTOR_DST_COLOR:
119 return V_028780_BLEND_DST_COLOR;
120 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
121 return V_028780_BLEND_SRC_ALPHA_SATURATE;
122 case PIPE_BLENDFACTOR_CONST_COLOR:
123 return V_028780_BLEND_CONST_COLOR;
124 case PIPE_BLENDFACTOR_CONST_ALPHA:
125 return V_028780_BLEND_CONST_ALPHA;
126 case PIPE_BLENDFACTOR_ZERO:
127 return V_028780_BLEND_ZERO;
128 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
129 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
130 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
131 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
132 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
133 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
134 case PIPE_BLENDFACTOR_INV_DST_COLOR:
135 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
136 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
137 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
138 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
139 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
140 case PIPE_BLENDFACTOR_SRC1_COLOR:
141 return V_028780_BLEND_SRC1_COLOR;
142 case PIPE_BLENDFACTOR_SRC1_ALPHA:
143 return V_028780_BLEND_SRC1_ALPHA;
144 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
145 return V_028780_BLEND_INV_SRC1_COLOR;
146 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
147 return V_028780_BLEND_INV_SRC1_ALPHA;
148 default:
149 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
150 assert(0);
151 break;
152 }
153 return 0;
154 }
155
156 static unsigned r600_tex_dim(unsigned dim)
157 {
158 switch (dim) {
159 default:
160 case PIPE_TEXTURE_1D:
161 return V_030000_SQ_TEX_DIM_1D;
162 case PIPE_TEXTURE_1D_ARRAY:
163 return V_030000_SQ_TEX_DIM_1D_ARRAY;
164 case PIPE_TEXTURE_2D:
165 case PIPE_TEXTURE_RECT:
166 return V_030000_SQ_TEX_DIM_2D;
167 case PIPE_TEXTURE_2D_ARRAY:
168 return V_030000_SQ_TEX_DIM_2D_ARRAY;
169 case PIPE_TEXTURE_3D:
170 return V_030000_SQ_TEX_DIM_3D;
171 case PIPE_TEXTURE_CUBE:
172 return V_030000_SQ_TEX_DIM_CUBEMAP;
173 }
174 }
175
176 static uint32_t r600_translate_dbformat(enum pipe_format format)
177 {
178 switch (format) {
179 case PIPE_FORMAT_Z16_UNORM:
180 return V_028040_Z_16;
181 case PIPE_FORMAT_Z24X8_UNORM:
182 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
183 return V_028040_Z_24;
184 case PIPE_FORMAT_Z32_FLOAT:
185 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
186 return V_028040_Z_32_FLOAT;
187 default:
188 return ~0U;
189 }
190 }
191
192 static uint32_t r600_translate_colorswap(enum pipe_format format)
193 {
194 switch (format) {
195 /* 8-bit buffers. */
196 case PIPE_FORMAT_L4A4_UNORM:
197 case PIPE_FORMAT_A4R4_UNORM:
198 return V_028C70_SWAP_ALT;
199
200 case PIPE_FORMAT_A8_UNORM:
201 case PIPE_FORMAT_A8_SNORM:
202 case PIPE_FORMAT_A8_UINT:
203 case PIPE_FORMAT_A8_SINT:
204 case PIPE_FORMAT_A16_UNORM:
205 case PIPE_FORMAT_A16_SNORM:
206 case PIPE_FORMAT_A16_UINT:
207 case PIPE_FORMAT_A16_SINT:
208 case PIPE_FORMAT_A16_FLOAT:
209 case PIPE_FORMAT_A32_UINT:
210 case PIPE_FORMAT_A32_SINT:
211 case PIPE_FORMAT_A32_FLOAT:
212 case PIPE_FORMAT_R4A4_UNORM:
213 return V_028C70_SWAP_ALT_REV;
214 case PIPE_FORMAT_I8_UNORM:
215 case PIPE_FORMAT_I8_SNORM:
216 case PIPE_FORMAT_I8_UINT:
217 case PIPE_FORMAT_I8_SINT:
218 case PIPE_FORMAT_I16_UNORM:
219 case PIPE_FORMAT_I16_SNORM:
220 case PIPE_FORMAT_I16_UINT:
221 case PIPE_FORMAT_I16_SINT:
222 case PIPE_FORMAT_I16_FLOAT:
223 case PIPE_FORMAT_I32_UINT:
224 case PIPE_FORMAT_I32_SINT:
225 case PIPE_FORMAT_I32_FLOAT:
226 case PIPE_FORMAT_L8_UNORM:
227 case PIPE_FORMAT_L8_SNORM:
228 case PIPE_FORMAT_L8_UINT:
229 case PIPE_FORMAT_L8_SINT:
230 case PIPE_FORMAT_L8_SRGB:
231 case PIPE_FORMAT_L16_UNORM:
232 case PIPE_FORMAT_L16_SNORM:
233 case PIPE_FORMAT_L16_UINT:
234 case PIPE_FORMAT_L16_SINT:
235 case PIPE_FORMAT_L16_FLOAT:
236 case PIPE_FORMAT_L32_UINT:
237 case PIPE_FORMAT_L32_SINT:
238 case PIPE_FORMAT_L32_FLOAT:
239 case PIPE_FORMAT_R8_UNORM:
240 case PIPE_FORMAT_R8_SNORM:
241 case PIPE_FORMAT_R8_UINT:
242 case PIPE_FORMAT_R8_SINT:
243 return V_028C70_SWAP_STD;
244
245 /* 16-bit buffers. */
246 case PIPE_FORMAT_B5G6R5_UNORM:
247 return V_028C70_SWAP_STD_REV;
248
249 case PIPE_FORMAT_B5G5R5A1_UNORM:
250 case PIPE_FORMAT_B5G5R5X1_UNORM:
251 return V_028C70_SWAP_ALT;
252
253 case PIPE_FORMAT_B4G4R4A4_UNORM:
254 case PIPE_FORMAT_B4G4R4X4_UNORM:
255 return V_028C70_SWAP_ALT;
256
257 case PIPE_FORMAT_Z16_UNORM:
258 return V_028C70_SWAP_STD;
259
260 case PIPE_FORMAT_L8A8_UNORM:
261 case PIPE_FORMAT_L8A8_SNORM:
262 case PIPE_FORMAT_L8A8_UINT:
263 case PIPE_FORMAT_L8A8_SINT:
264 case PIPE_FORMAT_L8A8_SRGB:
265 case PIPE_FORMAT_L16A16_UNORM:
266 case PIPE_FORMAT_L16A16_SNORM:
267 case PIPE_FORMAT_L16A16_UINT:
268 case PIPE_FORMAT_L16A16_SINT:
269 case PIPE_FORMAT_L16A16_FLOAT:
270 case PIPE_FORMAT_L32A32_UINT:
271 case PIPE_FORMAT_L32A32_SINT:
272 case PIPE_FORMAT_L32A32_FLOAT:
273 return V_028C70_SWAP_ALT;
274 case PIPE_FORMAT_R8G8_UNORM:
275 case PIPE_FORMAT_R8G8_SNORM:
276 case PIPE_FORMAT_R8G8_UINT:
277 case PIPE_FORMAT_R8G8_SINT:
278 return V_028C70_SWAP_STD;
279
280 case PIPE_FORMAT_R16_UNORM:
281 case PIPE_FORMAT_R16_SNORM:
282 case PIPE_FORMAT_R16_UINT:
283 case PIPE_FORMAT_R16_SINT:
284 case PIPE_FORMAT_R16_FLOAT:
285 return V_028C70_SWAP_STD;
286
287 /* 32-bit buffers. */
288 case PIPE_FORMAT_A8B8G8R8_SRGB:
289 return V_028C70_SWAP_STD_REV;
290 case PIPE_FORMAT_B8G8R8A8_SRGB:
291 return V_028C70_SWAP_ALT;
292
293 case PIPE_FORMAT_B8G8R8A8_UNORM:
294 case PIPE_FORMAT_B8G8R8X8_UNORM:
295 return V_028C70_SWAP_ALT;
296
297 case PIPE_FORMAT_A8R8G8B8_UNORM:
298 case PIPE_FORMAT_X8R8G8B8_UNORM:
299 return V_028C70_SWAP_ALT_REV;
300 case PIPE_FORMAT_R8G8B8A8_SNORM:
301 case PIPE_FORMAT_R8G8B8A8_UNORM:
302 case PIPE_FORMAT_R8G8B8A8_SINT:
303 case PIPE_FORMAT_R8G8B8A8_UINT:
304 case PIPE_FORMAT_R8G8B8X8_UNORM:
305 return V_028C70_SWAP_STD;
306
307 case PIPE_FORMAT_A8B8G8R8_UNORM:
308 case PIPE_FORMAT_X8B8G8R8_UNORM:
309 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
310 return V_028C70_SWAP_STD_REV;
311
312 case PIPE_FORMAT_Z24X8_UNORM:
313 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
314 return V_028C70_SWAP_STD;
315
316 case PIPE_FORMAT_X8Z24_UNORM:
317 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
318 return V_028C70_SWAP_STD;
319
320 case PIPE_FORMAT_R10G10B10A2_UNORM:
321 case PIPE_FORMAT_R10G10B10X2_SNORM:
322 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
323 return V_028C70_SWAP_STD;
324
325 case PIPE_FORMAT_B10G10R10A2_UNORM:
326 case PIPE_FORMAT_B10G10R10A2_UINT:
327 return V_028C70_SWAP_ALT;
328
329 case PIPE_FORMAT_R11G11B10_FLOAT:
330 case PIPE_FORMAT_R32_FLOAT:
331 case PIPE_FORMAT_R32_UINT:
332 case PIPE_FORMAT_R32_SINT:
333 case PIPE_FORMAT_Z32_FLOAT:
334 case PIPE_FORMAT_R16G16_FLOAT:
335 case PIPE_FORMAT_R16G16_UNORM:
336 case PIPE_FORMAT_R16G16_SNORM:
337 case PIPE_FORMAT_R16G16_UINT:
338 case PIPE_FORMAT_R16G16_SINT:
339 return V_028C70_SWAP_STD;
340
341 /* 64-bit buffers. */
342 case PIPE_FORMAT_R32G32_FLOAT:
343 case PIPE_FORMAT_R32G32_UINT:
344 case PIPE_FORMAT_R32G32_SINT:
345 case PIPE_FORMAT_R16G16B16A16_UNORM:
346 case PIPE_FORMAT_R16G16B16A16_SNORM:
347 case PIPE_FORMAT_R16G16B16A16_UINT:
348 case PIPE_FORMAT_R16G16B16A16_SINT:
349 case PIPE_FORMAT_R16G16B16A16_FLOAT:
350 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
351
352 /* 128-bit buffers. */
353 case PIPE_FORMAT_R32G32B32A32_FLOAT:
354 case PIPE_FORMAT_R32G32B32A32_SNORM:
355 case PIPE_FORMAT_R32G32B32A32_UNORM:
356 case PIPE_FORMAT_R32G32B32A32_SINT:
357 case PIPE_FORMAT_R32G32B32A32_UINT:
358 return V_028C70_SWAP_STD;
359 default:
360 R600_ERR("unsupported colorswap format %d\n", format);
361 return ~0U;
362 }
363 return ~0U;
364 }
365
366 static uint32_t r600_translate_colorformat(enum pipe_format format)
367 {
368 switch (format) {
369 /* 8-bit buffers. */
370 case PIPE_FORMAT_A8_UNORM:
371 case PIPE_FORMAT_A8_SNORM:
372 case PIPE_FORMAT_A8_UINT:
373 case PIPE_FORMAT_A8_SINT:
374 case PIPE_FORMAT_I8_UNORM:
375 case PIPE_FORMAT_I8_SNORM:
376 case PIPE_FORMAT_I8_UINT:
377 case PIPE_FORMAT_I8_SINT:
378 case PIPE_FORMAT_L8_UNORM:
379 case PIPE_FORMAT_L8_SNORM:
380 case PIPE_FORMAT_L8_UINT:
381 case PIPE_FORMAT_L8_SINT:
382 case PIPE_FORMAT_L8_SRGB:
383 case PIPE_FORMAT_R8_UNORM:
384 case PIPE_FORMAT_R8_SNORM:
385 case PIPE_FORMAT_R8_UINT:
386 case PIPE_FORMAT_R8_SINT:
387 return V_028C70_COLOR_8;
388
389 /* 16-bit buffers. */
390 case PIPE_FORMAT_B5G6R5_UNORM:
391 return V_028C70_COLOR_5_6_5;
392
393 case PIPE_FORMAT_B5G5R5A1_UNORM:
394 case PIPE_FORMAT_B5G5R5X1_UNORM:
395 return V_028C70_COLOR_1_5_5_5;
396
397 case PIPE_FORMAT_B4G4R4A4_UNORM:
398 case PIPE_FORMAT_B4G4R4X4_UNORM:
399 return V_028C70_COLOR_4_4_4_4;
400
401 case PIPE_FORMAT_Z16_UNORM:
402 return V_028C70_COLOR_16;
403
404 case PIPE_FORMAT_L8A8_UNORM:
405 case PIPE_FORMAT_L8A8_SNORM:
406 case PIPE_FORMAT_L8A8_UINT:
407 case PIPE_FORMAT_L8A8_SINT:
408 case PIPE_FORMAT_L8A8_SRGB:
409 case PIPE_FORMAT_R8G8_UNORM:
410 case PIPE_FORMAT_R8G8_SNORM:
411 case PIPE_FORMAT_R8G8_UINT:
412 case PIPE_FORMAT_R8G8_SINT:
413 return V_028C70_COLOR_8_8;
414
415 case PIPE_FORMAT_R16_UNORM:
416 case PIPE_FORMAT_R16_SNORM:
417 case PIPE_FORMAT_R16_UINT:
418 case PIPE_FORMAT_R16_SINT:
419 case PIPE_FORMAT_A16_UNORM:
420 case PIPE_FORMAT_A16_SNORM:
421 case PIPE_FORMAT_A16_UINT:
422 case PIPE_FORMAT_A16_SINT:
423 case PIPE_FORMAT_L16_UNORM:
424 case PIPE_FORMAT_L16_SNORM:
425 case PIPE_FORMAT_L16_UINT:
426 case PIPE_FORMAT_L16_SINT:
427 case PIPE_FORMAT_I16_UNORM:
428 case PIPE_FORMAT_I16_SNORM:
429 case PIPE_FORMAT_I16_UINT:
430 case PIPE_FORMAT_I16_SINT:
431 return V_028C70_COLOR_16;
432
433 case PIPE_FORMAT_R16_FLOAT:
434 case PIPE_FORMAT_A16_FLOAT:
435 case PIPE_FORMAT_L16_FLOAT:
436 case PIPE_FORMAT_I16_FLOAT:
437 return V_028C70_COLOR_16_FLOAT;
438
439 /* 32-bit buffers. */
440 case PIPE_FORMAT_A8B8G8R8_SRGB:
441 case PIPE_FORMAT_A8B8G8R8_UNORM:
442 case PIPE_FORMAT_A8R8G8B8_UNORM:
443 case PIPE_FORMAT_B8G8R8A8_SRGB:
444 case PIPE_FORMAT_B8G8R8A8_UNORM:
445 case PIPE_FORMAT_B8G8R8X8_UNORM:
446 case PIPE_FORMAT_R8G8B8A8_SNORM:
447 case PIPE_FORMAT_R8G8B8A8_UNORM:
448 case PIPE_FORMAT_R8G8B8X8_UNORM:
449 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
450 case PIPE_FORMAT_X8B8G8R8_UNORM:
451 case PIPE_FORMAT_X8R8G8B8_UNORM:
452 case PIPE_FORMAT_R8G8B8_UNORM:
453 case PIPE_FORMAT_R8G8B8A8_SINT:
454 case PIPE_FORMAT_R8G8B8A8_UINT:
455 return V_028C70_COLOR_8_8_8_8;
456
457 case PIPE_FORMAT_R10G10B10A2_UNORM:
458 case PIPE_FORMAT_R10G10B10X2_SNORM:
459 case PIPE_FORMAT_B10G10R10A2_UNORM:
460 case PIPE_FORMAT_B10G10R10A2_UINT:
461 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
462 return V_028C70_COLOR_2_10_10_10;
463
464 case PIPE_FORMAT_Z24X8_UNORM:
465 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
466 return V_028C70_COLOR_8_24;
467
468 case PIPE_FORMAT_X8Z24_UNORM:
469 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
470 return V_028C70_COLOR_24_8;
471
472 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
473 return V_028C70_COLOR_X24_8_32_FLOAT;
474
475 case PIPE_FORMAT_R32_UINT:
476 case PIPE_FORMAT_R32_SINT:
477 case PIPE_FORMAT_A32_UINT:
478 case PIPE_FORMAT_A32_SINT:
479 case PIPE_FORMAT_L32_UINT:
480 case PIPE_FORMAT_L32_SINT:
481 case PIPE_FORMAT_I32_UINT:
482 case PIPE_FORMAT_I32_SINT:
483 return V_028C70_COLOR_32;
484
485 case PIPE_FORMAT_R32_FLOAT:
486 case PIPE_FORMAT_A32_FLOAT:
487 case PIPE_FORMAT_L32_FLOAT:
488 case PIPE_FORMAT_I32_FLOAT:
489 case PIPE_FORMAT_Z32_FLOAT:
490 return V_028C70_COLOR_32_FLOAT;
491
492 case PIPE_FORMAT_R16G16_FLOAT:
493 case PIPE_FORMAT_L16A16_FLOAT:
494 return V_028C70_COLOR_16_16_FLOAT;
495
496 case PIPE_FORMAT_R16G16_UNORM:
497 case PIPE_FORMAT_R16G16_SNORM:
498 case PIPE_FORMAT_R16G16_UINT:
499 case PIPE_FORMAT_R16G16_SINT:
500 case PIPE_FORMAT_L16A16_UNORM:
501 case PIPE_FORMAT_L16A16_SNORM:
502 case PIPE_FORMAT_L16A16_UINT:
503 case PIPE_FORMAT_L16A16_SINT:
504 return V_028C70_COLOR_16_16;
505
506 case PIPE_FORMAT_R11G11B10_FLOAT:
507 return V_028C70_COLOR_10_11_11_FLOAT;
508
509 /* 64-bit buffers. */
510 case PIPE_FORMAT_R16G16B16A16_UINT:
511 case PIPE_FORMAT_R16G16B16A16_SINT:
512 case PIPE_FORMAT_R16G16B16A16_UNORM:
513 case PIPE_FORMAT_R16G16B16A16_SNORM:
514 return V_028C70_COLOR_16_16_16_16;
515
516 case PIPE_FORMAT_R16G16B16_FLOAT:
517 case PIPE_FORMAT_R16G16B16A16_FLOAT:
518 return V_028C70_COLOR_16_16_16_16_FLOAT;
519
520 case PIPE_FORMAT_R32G32_FLOAT:
521 case PIPE_FORMAT_L32A32_FLOAT:
522 return V_028C70_COLOR_32_32_FLOAT;
523
524 case PIPE_FORMAT_R32G32_SINT:
525 case PIPE_FORMAT_R32G32_UINT:
526 case PIPE_FORMAT_L32A32_UINT:
527 case PIPE_FORMAT_L32A32_SINT:
528 return V_028C70_COLOR_32_32;
529
530 /* 96-bit buffers. */
531 case PIPE_FORMAT_R32G32B32_FLOAT:
532 return V_028C70_COLOR_32_32_32_FLOAT;
533
534 /* 128-bit buffers. */
535 case PIPE_FORMAT_R32G32B32A32_SNORM:
536 case PIPE_FORMAT_R32G32B32A32_UNORM:
537 case PIPE_FORMAT_R32G32B32A32_SINT:
538 case PIPE_FORMAT_R32G32B32A32_UINT:
539 return V_028C70_COLOR_32_32_32_32;
540 case PIPE_FORMAT_R32G32B32A32_FLOAT:
541 return V_028C70_COLOR_32_32_32_32_FLOAT;
542
543 /* YUV buffers. */
544 case PIPE_FORMAT_UYVY:
545 case PIPE_FORMAT_YUYV:
546 default:
547 return ~0U; /* Unsupported. */
548 }
549 }
550
551 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
552 {
553 if (R600_BIG_ENDIAN) {
554 switch(colorformat) {
555
556 /* 8-bit buffers. */
557 case V_028C70_COLOR_8:
558 return ENDIAN_NONE;
559
560 /* 16-bit buffers. */
561 case V_028C70_COLOR_5_6_5:
562 case V_028C70_COLOR_1_5_5_5:
563 case V_028C70_COLOR_4_4_4_4:
564 case V_028C70_COLOR_16:
565 case V_028C70_COLOR_8_8:
566 return ENDIAN_8IN16;
567
568 /* 32-bit buffers. */
569 case V_028C70_COLOR_8_8_8_8:
570 case V_028C70_COLOR_2_10_10_10:
571 case V_028C70_COLOR_8_24:
572 case V_028C70_COLOR_24_8:
573 case V_028C70_COLOR_32_FLOAT:
574 case V_028C70_COLOR_16_16_FLOAT:
575 case V_028C70_COLOR_16_16:
576 return ENDIAN_8IN32;
577
578 /* 64-bit buffers. */
579 case V_028C70_COLOR_16_16_16_16:
580 case V_028C70_COLOR_16_16_16_16_FLOAT:
581 return ENDIAN_8IN16;
582
583 case V_028C70_COLOR_32_32_FLOAT:
584 case V_028C70_COLOR_32_32:
585 case V_028C70_COLOR_X24_8_32_FLOAT:
586 return ENDIAN_8IN32;
587
588 /* 96-bit buffers. */
589 case V_028C70_COLOR_32_32_32_FLOAT:
590 /* 128-bit buffers. */
591 case V_028C70_COLOR_32_32_32_32_FLOAT:
592 case V_028C70_COLOR_32_32_32_32:
593 return ENDIAN_8IN32;
594 default:
595 return ENDIAN_NONE; /* Unsupported. */
596 }
597 } else {
598 return ENDIAN_NONE;
599 }
600 }
601
602 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
603 {
604 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
605 }
606
607 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
608 {
609 return r600_translate_colorformat(format) != ~0U &&
610 r600_translate_colorswap(format) != ~0U;
611 }
612
613 static bool r600_is_zs_format_supported(enum pipe_format format)
614 {
615 return r600_translate_dbformat(format) != ~0U;
616 }
617
618 boolean evergreen_is_format_supported(struct pipe_screen *screen,
619 enum pipe_format format,
620 enum pipe_texture_target target,
621 unsigned sample_count,
622 unsigned usage)
623 {
624 unsigned retval = 0;
625
626 if (target >= PIPE_MAX_TEXTURE_TYPES) {
627 R600_ERR("r600: unsupported texture type %d\n", target);
628 return FALSE;
629 }
630
631 if (!util_format_is_supported(format, usage))
632 return FALSE;
633
634 /* Multisample */
635 if (sample_count > 1)
636 return FALSE;
637
638 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
639 r600_is_sampler_format_supported(screen, format)) {
640 retval |= PIPE_BIND_SAMPLER_VIEW;
641 }
642
643 if ((usage & (PIPE_BIND_RENDER_TARGET |
644 PIPE_BIND_DISPLAY_TARGET |
645 PIPE_BIND_SCANOUT |
646 PIPE_BIND_SHARED)) &&
647 r600_is_colorbuffer_format_supported(format)) {
648 retval |= usage &
649 (PIPE_BIND_RENDER_TARGET |
650 PIPE_BIND_DISPLAY_TARGET |
651 PIPE_BIND_SCANOUT |
652 PIPE_BIND_SHARED);
653 }
654
655 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
656 r600_is_zs_format_supported(format)) {
657 retval |= PIPE_BIND_DEPTH_STENCIL;
658 }
659
660 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
661 r600_is_vertex_format_supported(format)) {
662 retval |= PIPE_BIND_VERTEX_BUFFER;
663 }
664
665 if (usage & PIPE_BIND_TRANSFER_READ)
666 retval |= PIPE_BIND_TRANSFER_READ;
667 if (usage & PIPE_BIND_TRANSFER_WRITE)
668 retval |= PIPE_BIND_TRANSFER_WRITE;
669
670 return retval == usage;
671 }
672
673 static void *evergreen_create_blend_state(struct pipe_context *ctx,
674 const struct pipe_blend_state *state)
675 {
676 struct r600_context *rctx = (struct r600_context *)ctx;
677 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
678 struct r600_pipe_state *rstate;
679 uint32_t color_control, target_mask;
680 /* XXX there is more then 8 framebuffer */
681 unsigned blend_cntl[8];
682
683 if (blend == NULL) {
684 return NULL;
685 }
686
687 rstate = &blend->rstate;
688
689 rstate->id = R600_PIPE_STATE_BLEND;
690
691 target_mask = 0;
692 color_control = S_028808_MODE(1);
693 if (state->logicop_enable) {
694 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
695 } else {
696 color_control |= (0xcc << 16);
697 }
698 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
699 if (state->independent_blend_enable) {
700 for (int i = 0; i < 8; i++) {
701 target_mask |= (state->rt[i].colormask << (4 * i));
702 }
703 } else {
704 for (int i = 0; i < 8; i++) {
705 target_mask |= (state->rt[0].colormask << (4 * i));
706 }
707 }
708 blend->cb_target_mask = target_mask;
709
710 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
711 color_control, NULL, 0);
712
713 for (int i = 0; i < 8; i++) {
714 /* state->rt entries > 0 only written if independent blending */
715 const int j = state->independent_blend_enable ? i : 0;
716
717 unsigned eqRGB = state->rt[j].rgb_func;
718 unsigned srcRGB = state->rt[j].rgb_src_factor;
719 unsigned dstRGB = state->rt[j].rgb_dst_factor;
720 unsigned eqA = state->rt[j].alpha_func;
721 unsigned srcA = state->rt[j].alpha_src_factor;
722 unsigned dstA = state->rt[j].alpha_dst_factor;
723
724 blend_cntl[i] = 0;
725 if (!state->rt[j].blend_enable)
726 continue;
727
728 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
729 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
730 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
731 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
732
733 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
734 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
735 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
736 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
737 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
738 }
739 }
740 for (int i = 0; i < 8; i++) {
741 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], NULL, 0);
742 }
743
744 return rstate;
745 }
746
747 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
748 const struct pipe_depth_stencil_alpha_state *state)
749 {
750 struct r600_context *rctx = (struct r600_context *)ctx;
751 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
752 unsigned db_depth_control, alpha_test_control, alpha_ref;
753 unsigned db_render_control;
754 struct r600_pipe_state *rstate;
755
756 if (dsa == NULL) {
757 return NULL;
758 }
759
760 dsa->valuemask[0] = state->stencil[0].valuemask;
761 dsa->valuemask[1] = state->stencil[1].valuemask;
762 dsa->writemask[0] = state->stencil[0].writemask;
763 dsa->writemask[1] = state->stencil[1].writemask;
764
765 rstate = &dsa->rstate;
766
767 rstate->id = R600_PIPE_STATE_DSA;
768 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
769 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
770 S_028800_ZFUNC(state->depth.func);
771
772 /* stencil */
773 if (state->stencil[0].enabled) {
774 db_depth_control |= S_028800_STENCIL_ENABLE(1);
775 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
776 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
777 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
778 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
779
780 if (state->stencil[1].enabled) {
781 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
782 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
783 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
784 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
785 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
786 }
787 }
788
789 /* alpha */
790 alpha_test_control = 0;
791 alpha_ref = 0;
792 if (state->alpha.enabled) {
793 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
794 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
795 alpha_ref = fui(state->alpha.ref_value);
796 }
797 dsa->alpha_ref = alpha_ref;
798
799 /* misc */
800 db_render_control = 0;
801 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
802 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
803 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0);
804 return rstate;
805 }
806
807 static void *evergreen_create_rs_state(struct pipe_context *ctx,
808 const struct pipe_rasterizer_state *state)
809 {
810 struct r600_context *rctx = (struct r600_context *)ctx;
811 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
812 struct r600_pipe_state *rstate;
813 unsigned tmp;
814 unsigned prov_vtx = 1, polygon_dual_mode;
815 float psize_min, psize_max;
816
817 if (rs == NULL) {
818 return NULL;
819 }
820
821 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
822 state->fill_back != PIPE_POLYGON_MODE_FILL);
823
824 if (state->flatshade_first)
825 prov_vtx = 0;
826
827 rstate = &rs->rstate;
828 rs->flatshade = state->flatshade;
829 rs->sprite_coord_enable = state->sprite_coord_enable;
830 rs->two_side = state->light_twoside;
831 rs->clip_plane_enable = state->clip_plane_enable;
832 rs->pa_sc_line_stipple = state->line_stipple_enable ?
833 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
834 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
835 rs->pa_cl_clip_cntl =
836 S_028810_PS_UCP_MODE(3) |
837 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
838 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
839 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
840
841 /* offset */
842 rs->offset_units = state->offset_units;
843 rs->offset_scale = state->offset_scale * 12.0f;
844
845 rstate->id = R600_PIPE_STATE_RASTERIZER;
846 tmp = S_0286D4_FLAT_SHADE_ENA(1);
847 if (state->sprite_coord_enable) {
848 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
849 S_0286D4_PNT_SPRITE_OVRD_X(2) |
850 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
851 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
852 S_0286D4_PNT_SPRITE_OVRD_W(1);
853 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
854 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
855 }
856 }
857 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
858
859 /* point size 12.4 fixed point */
860 tmp = (unsigned)(state->point_size * 8.0);
861 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
862
863 if (state->point_size_per_vertex) {
864 psize_min = util_get_min_point_size(state);
865 psize_max = 8192;
866 } else {
867 /* Force the point size to be as if the vertex output was disabled. */
868 psize_min = state->point_size;
869 psize_max = state->point_size;
870 }
871 /* Divide by two, because 0.5 = 1 pixel. */
872 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
873 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
874 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
875 NULL, 0);
876
877 tmp = (unsigned)state->line_width * 8;
878 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
879 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
880 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
881 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
882 NULL, 0);
883
884 if (rctx->chip_class == CAYMAN) {
885 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
886 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
887 NULL, 0);
888 } else {
889 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
890 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
891 NULL, 0);
892 }
893 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
894 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
895 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
896 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
897 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
898 S_028814_FACE(!state->front_ccw) |
899 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
900 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
901 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
902 S_028814_POLY_MODE(polygon_dual_mode) |
903 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
904 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)),
905 NULL, 0);
906 return rstate;
907 }
908
909 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
910 const struct pipe_sampler_state *state)
911 {
912 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
913 union util_color uc;
914 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
915
916 if (rstate == NULL) {
917 return NULL;
918 }
919
920 rstate->id = R600_PIPE_STATE_SAMPLER;
921 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
922 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
923 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
924 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
925 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
926 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
927 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
928 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
929 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
930 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
931 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
932 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
933 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
934 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
935 NULL, 0);
936 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
937 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
938 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
939 S_03C008_TYPE(1),
940 NULL, 0);
941
942 if (uc.ui) {
943 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
944 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
945 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
946 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
947 }
948 return rstate;
949 }
950
951 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
952 struct pipe_resource *texture,
953 const struct pipe_sampler_view *state)
954 {
955 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
956 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
957 struct r600_pipe_resource_state *rstate;
958 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
959 unsigned format, endian;
960 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
961 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
962 unsigned height, depth, width;
963 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
964
965 if (view == NULL)
966 return NULL;
967 rstate = &view->state;
968
969 /* initialize base object */
970 view->base = *state;
971 view->base.texture = NULL;
972 pipe_reference(NULL, &texture->reference);
973 view->base.texture = texture;
974 view->base.reference.count = 1;
975 view->base.context = ctx;
976
977 swizzle[0] = state->swizzle_r;
978 swizzle[1] = state->swizzle_g;
979 swizzle[2] = state->swizzle_b;
980 swizzle[3] = state->swizzle_a;
981
982 format = r600_translate_texformat(ctx->screen, state->format,
983 swizzle,
984 &word4, &yuv_format);
985 if (format == ~0) {
986 format = 0;
987 }
988
989 if (tmp->is_depth && !tmp->is_flushing_texture) {
990 r600_texture_depth_flush(ctx, texture, TRUE);
991 tmp = tmp->flushed_depth_texture;
992 }
993
994 endian = r600_colorformat_endian_swap(format);
995
996 if (!rscreen->use_surface_alloc) {
997 height = texture->height0;
998 depth = texture->depth0;
999 width = texture->width0;
1000 pitch = align(tmp->pitch_in_blocks[0] *
1001 util_format_get_blockwidth(state->format), 8);
1002 array_mode = tmp->array_mode[0];
1003 tile_type = tmp->tile_type;
1004 tile_split = 0;
1005 macro_aspect = 0;
1006 bankw = 0;
1007 bankh = 0;
1008 } else {
1009 width = tmp->surface.level[0].npix_x;
1010 height = tmp->surface.level[0].npix_y;
1011 depth = tmp->surface.level[0].npix_z;
1012 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1013 tile_type = tmp->tile_type;
1014
1015 switch (tmp->surface.level[0].mode) {
1016 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1017 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1018 break;
1019 case RADEON_SURF_MODE_2D:
1020 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1021 break;
1022 case RADEON_SURF_MODE_1D:
1023 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1024 break;
1025 case RADEON_SURF_MODE_LINEAR:
1026 default:
1027 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1028 break;
1029 }
1030 tile_split = tmp->surface.tile_split;
1031 macro_aspect = tmp->surface.mtilea;
1032 bankw = tmp->surface.bankw;
1033 bankh = tmp->surface.bankh;
1034 tile_split = eg_tile_split(tile_split);
1035 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1036 bankw = eg_bank_wh(bankw);
1037 bankh = eg_bank_wh(bankh);
1038 }
1039 /* 128 bit formats require tile type = 1 */
1040 if (rscreen->chip_class == CAYMAN) {
1041 if (util_format_get_blocksize(state->format) >= 16)
1042 tile_type = 1;
1043 }
1044 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1045
1046 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1047 height = 1;
1048 depth = texture->array_size;
1049 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1050 depth = texture->array_size;
1051 }
1052
1053 rstate->bo[0] = &tmp->resource;
1054 rstate->bo[1] = &tmp->resource;
1055 rstate->bo_usage[0] = RADEON_USAGE_READ;
1056 rstate->bo_usage[1] = RADEON_USAGE_READ;
1057
1058 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1059 S_030000_PITCH((pitch / 8) - 1) |
1060 S_030000_TEX_WIDTH(width - 1));
1061 if (rscreen->chip_class == CAYMAN)
1062 rstate->val[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1063 else
1064 rstate->val[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1065 rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1066 S_030004_TEX_DEPTH(depth - 1) |
1067 S_030004_ARRAY_MODE(array_mode));
1068 rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1069 if (state->u.tex.last_level) {
1070 rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1071 } else {
1072 rstate->val[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1073 }
1074 rstate->val[4] = (word4 |
1075 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1076 S_030010_ENDIAN_SWAP(endian) |
1077 S_030010_BASE_LEVEL(state->u.tex.first_level));
1078 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1079 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1080 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1081 /* aniso max 16 samples */
1082 rstate->val[6] = (S_030018_MAX_ANISO(4)) |
1083 (S_030018_TILE_SPLIT(tile_split));
1084 rstate->val[7] = S_03001C_DATA_FORMAT(format) |
1085 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1086 S_03001C_BANK_WIDTH(bankw) |
1087 S_03001C_BANK_HEIGHT(bankh) |
1088 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1089 S_03001C_NUM_BANKS(nbanks);
1090
1091 return &view->base;
1092 }
1093
1094 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1095 struct pipe_sampler_view **views)
1096 {
1097 struct r600_context *rctx = (struct r600_context *)ctx;
1098 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1099
1100 for (int i = 0; i < count; i++) {
1101 if (resource[i]) {
1102 r600_context_pipe_state_set_vs_resource(rctx, &resource[i]->state,
1103 i + R600_MAX_CONST_BUFFERS);
1104 }
1105 }
1106 }
1107
1108 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1109 struct pipe_sampler_view **views)
1110 {
1111 struct r600_context *rctx = (struct r600_context *)ctx;
1112 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1113 int i;
1114 int has_depth = 0;
1115
1116 for (i = 0; i < count; i++) {
1117 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1118 if (resource[i]) {
1119 if (((struct r600_resource_texture *)resource[i]->base.texture)->is_depth)
1120 has_depth = 1;
1121 r600_context_pipe_state_set_ps_resource(rctx, &resource[i]->state,
1122 i + R600_MAX_CONST_BUFFERS);
1123 } else
1124 r600_context_pipe_state_set_ps_resource(rctx, NULL,
1125 i + R600_MAX_CONST_BUFFERS);
1126
1127 pipe_sampler_view_reference(
1128 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1129 views[i]);
1130 } else {
1131 if (resource[i]) {
1132 if (((struct r600_resource_texture *)resource[i]->base.texture)->is_depth)
1133 has_depth = 1;
1134 }
1135 }
1136 }
1137 for (i = count; i < NUM_TEX_UNITS; i++) {
1138 if (rctx->ps_samplers.views[i]) {
1139 r600_context_pipe_state_set_ps_resource(rctx, NULL,
1140 i + R600_MAX_CONST_BUFFERS);
1141 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1142 }
1143 }
1144 rctx->have_depth_texture = has_depth;
1145 rctx->ps_samplers.n_views = count;
1146 }
1147
1148 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1149 {
1150 struct r600_context *rctx = (struct r600_context *)ctx;
1151 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1152
1153 if (count)
1154 r600_inval_texture_cache(rctx);
1155
1156 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1157 rctx->ps_samplers.n_samplers = count;
1158
1159 for (int i = 0; i < count; i++) {
1160 evergreen_context_pipe_state_set_ps_sampler(rctx, rstates[i], i);
1161 }
1162 }
1163
1164 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1165 {
1166 struct r600_context *rctx = (struct r600_context *)ctx;
1167 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1168
1169 if (count)
1170 r600_inval_texture_cache(rctx);
1171
1172 for (int i = 0; i < count; i++) {
1173 evergreen_context_pipe_state_set_vs_sampler(rctx, rstates[i], i);
1174 }
1175 }
1176
1177 static void evergreen_set_clip_state(struct pipe_context *ctx,
1178 const struct pipe_clip_state *state)
1179 {
1180 struct r600_context *rctx = (struct r600_context *)ctx;
1181 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1182 struct pipe_resource *cbuf;
1183
1184 if (rstate == NULL)
1185 return;
1186
1187 rctx->clip = *state;
1188 rstate->id = R600_PIPE_STATE_CLIP;
1189 for (int i = 0; i < 6; i++) {
1190 r600_pipe_state_add_reg(rstate,
1191 R_0285BC_PA_CL_UCP0_X + i * 16,
1192 fui(state->ucp[i][0]), NULL, 0);
1193 r600_pipe_state_add_reg(rstate,
1194 R_0285C0_PA_CL_UCP0_Y + i * 16,
1195 fui(state->ucp[i][1]) , NULL, 0);
1196 r600_pipe_state_add_reg(rstate,
1197 R_0285C4_PA_CL_UCP0_Z + i * 16,
1198 fui(state->ucp[i][2]), NULL, 0);
1199 r600_pipe_state_add_reg(rstate,
1200 R_0285C8_PA_CL_UCP0_W + i * 16,
1201 fui(state->ucp[i][3]), NULL, 0);
1202 }
1203
1204 free(rctx->states[R600_PIPE_STATE_CLIP]);
1205 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1206 r600_context_pipe_state_set(rctx, rstate);
1207
1208 cbuf = pipe_user_buffer_create(ctx->screen,
1209 state->ucp,
1210 4*4*8, /* 8*4 floats */
1211 PIPE_BIND_CONSTANT_BUFFER);
1212 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
1213 pipe_resource_reference(&cbuf, NULL);
1214 }
1215
1216 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1217 const struct pipe_poly_stipple *state)
1218 {
1219 }
1220
1221 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1222 {
1223 }
1224
1225 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1226 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1227 uint32_t *tl, uint32_t *br)
1228 {
1229 /* EG hw workaround */
1230 if (br_x == 0)
1231 tl_x = 1;
1232 if (br_y == 0)
1233 tl_y = 1;
1234
1235 /* cayman hw workaround */
1236 if (rctx->chip_class == CAYMAN) {
1237 if (br_x == 1 && br_y == 1)
1238 br_x = 2;
1239 }
1240
1241 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1242 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1243 }
1244
1245 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1246 const struct pipe_scissor_state *state)
1247 {
1248 struct r600_context *rctx = (struct r600_context *)ctx;
1249 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1250 uint32_t tl, br;
1251
1252 if (rstate == NULL)
1253 return;
1254
1255 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1256
1257 rstate->id = R600_PIPE_STATE_SCISSOR;
1258 r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl, NULL, 0);
1259 r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br, NULL, 0);
1260
1261 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1262 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1263 r600_context_pipe_state_set(rctx, rstate);
1264 }
1265
1266 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1267 const struct pipe_viewport_state *state)
1268 {
1269 struct r600_context *rctx = (struct r600_context *)ctx;
1270 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1271
1272 if (rstate == NULL)
1273 return;
1274
1275 rctx->viewport = *state;
1276 rstate->id = R600_PIPE_STATE_VIEWPORT;
1277 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
1278 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
1279 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
1280 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
1281 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
1282 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
1283
1284 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1285 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1286 r600_context_pipe_state_set(rctx, rstate);
1287 }
1288
1289 static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1290 const struct pipe_framebuffer_state *state, int cb)
1291 {
1292 struct r600_screen *rscreen = rctx->screen;
1293 struct r600_resource_texture *rtex;
1294 struct r600_surface *surf;
1295 unsigned level = state->cbufs[cb]->u.tex.level;
1296 unsigned pitch, slice;
1297 unsigned color_info, color_attrib;
1298 unsigned format, swap, ntype, endian;
1299 uint64_t offset;
1300 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1301 const struct util_format_description *desc;
1302 int i;
1303 unsigned blend_clamp = 0, blend_bypass = 0;
1304
1305 surf = (struct r600_surface *)state->cbufs[cb];
1306 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1307
1308 if (rtex->is_depth)
1309 rctx->have_depth_fb = TRUE;
1310
1311 if (rtex->is_depth && !rtex->is_flushing_texture) {
1312 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1313 rtex = rtex->flushed_depth_texture;
1314 }
1315
1316 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1317 if (!rscreen->use_surface_alloc) {
1318 offset = r600_texture_get_offset(rtex,
1319 level, state->cbufs[cb]->u.tex.first_layer);
1320 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1321 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1322 if (slice) {
1323 slice = slice - 1;
1324 }
1325 color_info = S_028C70_ARRAY_MODE(rtex->array_mode[level]);
1326 tile_split = 0;
1327 macro_aspect = 0;
1328 bankw = 0;
1329 bankh = 0;
1330 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1331 tile_type = rtex->tile_type;
1332 } else {
1333 /* workaround for linear buffers */
1334 tile_type = 1;
1335 }
1336 } else {
1337 offset = rtex->surface.level[level].offset;
1338 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1339 offset += rtex->surface.level[level].slice_size *
1340 state->cbufs[cb]->u.tex.first_layer;
1341 }
1342 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1343 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1344 if (slice) {
1345 slice = slice - 1;
1346 }
1347 color_info = 0;
1348 switch (rtex->surface.level[level].mode) {
1349 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1350 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1351 tile_type = 1;
1352 break;
1353 case RADEON_SURF_MODE_1D:
1354 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1355 tile_type = rtex->tile_type;
1356 break;
1357 case RADEON_SURF_MODE_2D:
1358 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1359 tile_type = rtex->tile_type;
1360 break;
1361 case RADEON_SURF_MODE_LINEAR:
1362 default:
1363 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1364 tile_type = 1;
1365 break;
1366 }
1367 tile_split = rtex->surface.tile_split;
1368 macro_aspect = rtex->surface.mtilea;
1369 bankw = rtex->surface.bankw;
1370 bankh = rtex->surface.bankh;
1371 tile_split = eg_tile_split(tile_split);
1372 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1373 bankw = eg_bank_wh(bankw);
1374 bankh = eg_bank_wh(bankh);
1375 }
1376 /* 128 bit formats require tile type = 1 */
1377 if (rscreen->chip_class == CAYMAN) {
1378 if (util_format_get_blocksize(surf->base.format) >= 16)
1379 tile_type = 1;
1380 }
1381 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1382 desc = util_format_description(surf->base.format);
1383 for (i = 0; i < 4; i++) {
1384 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1385 break;
1386 }
1387 }
1388
1389 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1390 S_028C74_NUM_BANKS(nbanks) |
1391 S_028C74_BANK_WIDTH(bankw) |
1392 S_028C74_BANK_HEIGHT(bankh) |
1393 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1394 S_028C74_NON_DISP_TILING_ORDER(tile_type);
1395
1396 ntype = V_028C70_NUMBER_UNORM;
1397 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1398 ntype = V_028C70_NUMBER_SRGB;
1399 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1400 if (desc->channel[i].normalized)
1401 ntype = V_028C70_NUMBER_SNORM;
1402 else if (desc->channel[i].pure_integer)
1403 ntype = V_028C70_NUMBER_SINT;
1404 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1405 if (desc->channel[i].normalized)
1406 ntype = V_028C70_NUMBER_UNORM;
1407 else if (desc->channel[i].pure_integer)
1408 ntype = V_028C70_NUMBER_UINT;
1409 }
1410
1411 format = r600_translate_colorformat(surf->base.format);
1412 swap = r600_translate_colorswap(surf->base.format);
1413 if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1414 endian = ENDIAN_NONE;
1415 } else {
1416 endian = r600_colorformat_endian_swap(format);
1417 }
1418
1419 /* blend clamp should be set for all NORM/SRGB types */
1420 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1421 ntype == V_028C70_NUMBER_SRGB)
1422 blend_clamp = 1;
1423
1424 /* set blend bypass according to docs if SINT/UINT or
1425 8/24 COLOR variants */
1426 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1427 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1428 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1429 blend_clamp = 0;
1430 blend_bypass = 1;
1431 }
1432
1433 color_info |= S_028C70_FORMAT(format) |
1434 S_028C70_COMP_SWAP(swap) |
1435 S_028C70_BLEND_CLAMP(blend_clamp) |
1436 S_028C70_BLEND_BYPASS(blend_bypass) |
1437 S_028C70_NUMBER_TYPE(ntype) |
1438 S_028C70_ENDIAN(endian);
1439
1440 /* EXPORT_NORM is an optimzation that can be enabled for better
1441 * performance in certain cases.
1442 * EXPORT_NORM can be enabled if:
1443 * - 11-bit or smaller UNORM/SNORM/SRGB
1444 * - 16-bit or smaller FLOAT
1445 */
1446 /* XXX: This should probably be the same for all CBs if we want
1447 * useful alpha tests. */
1448 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1449 ((desc->channel[i].size < 12 &&
1450 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1451 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1452 (desc->channel[i].size < 17 &&
1453 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1454 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1455 rctx->export_16bpc = true;
1456 } else {
1457 rctx->export_16bpc = false;
1458 }
1459 rctx->alpha_ref_dirty = true;
1460
1461
1462 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1463 offset >>= 8;
1464
1465 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1466 r600_pipe_state_add_reg(rstate,
1467 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1468 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1469 r600_pipe_state_add_reg(rstate,
1470 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1471 0x0, NULL, 0);
1472 r600_pipe_state_add_reg(rstate,
1473 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1474 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1475 r600_pipe_state_add_reg(rstate,
1476 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1477 S_028C64_PITCH_TILE_MAX(pitch),
1478 NULL, 0);
1479 r600_pipe_state_add_reg(rstate,
1480 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1481 S_028C68_SLICE_TILE_MAX(slice),
1482 NULL, 0);
1483 if (!rscreen->use_surface_alloc) {
1484 r600_pipe_state_add_reg(rstate,
1485 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1486 0x00000000, NULL, 0);
1487 } else {
1488 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1489 r600_pipe_state_add_reg(rstate,
1490 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1491 0x00000000, NULL, 0);
1492 } else {
1493 r600_pipe_state_add_reg(rstate,
1494 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1495 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1496 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
1497 NULL, 0);
1498 }
1499 }
1500 r600_pipe_state_add_reg(rstate,
1501 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1502 color_attrib,
1503 &rtex->resource, RADEON_USAGE_READWRITE);
1504 }
1505
1506 static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1507 const struct pipe_framebuffer_state *state)
1508 {
1509 struct r600_screen *rscreen = rctx->screen;
1510 struct r600_resource_texture *rtex;
1511 struct r600_surface *surf;
1512 uint64_t offset;
1513 unsigned level, first_layer, pitch, slice, format, array_mode;
1514 unsigned macro_aspect, tile_split, bankh, bankw, z_info, nbanks;
1515
1516 if (state->zsbuf == NULL)
1517 return;
1518
1519 surf = (struct r600_surface *)state->zsbuf;
1520 level = surf->base.u.tex.level;
1521 rtex = (struct r600_resource_texture*)surf->base.texture;
1522 first_layer = surf->base.u.tex.first_layer;
1523 format = r600_translate_dbformat(rtex->real_format);
1524
1525 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1526 /* XXX remove this once tiling is properly supported */
1527 if (!rscreen->use_surface_alloc) {
1528 /* XXX remove this once tiling is properly supported */
1529 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1530 V_028C70_ARRAY_1D_TILED_THIN1;
1531
1532 offset += r600_texture_get_offset(rtex, level, first_layer);
1533 pitch = (rtex->pitch_in_blocks[level] / 8) - 1;
1534 slice = ((rtex->pitch_in_blocks[level] * surf->aligned_height) / 64);
1535 if (slice) {
1536 slice = slice - 1;
1537 }
1538 tile_split = 0;
1539 macro_aspect = 0;
1540 bankw = 0;
1541 bankh = 0;
1542 } else {
1543 offset += rtex->surface.level[level].offset;
1544 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1545 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1546 if (slice) {
1547 slice = slice - 1;
1548 }
1549 switch (rtex->surface.level[level].mode) {
1550 case RADEON_SURF_MODE_2D:
1551 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1552 break;
1553 case RADEON_SURF_MODE_1D:
1554 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1555 case RADEON_SURF_MODE_LINEAR:
1556 default:
1557 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1558 break;
1559 }
1560 tile_split = rtex->surface.tile_split;
1561 macro_aspect = rtex->surface.mtilea;
1562 bankw = rtex->surface.bankw;
1563 bankh = rtex->surface.bankh;
1564 tile_split = eg_tile_split(tile_split);
1565 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1566 bankw = eg_bank_wh(bankw);
1567 bankh = eg_bank_wh(bankh);
1568 }
1569 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1570 offset >>= 8;
1571
1572 z_info = S_028040_ARRAY_MODE(array_mode) |
1573 S_028040_FORMAT(format) |
1574 S_028040_TILE_SPLIT(tile_split)|
1575 S_028040_NUM_BANKS(nbanks) |
1576 S_028040_BANK_WIDTH(bankw) |
1577 S_028040_BANK_HEIGHT(bankh) |
1578 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1579
1580 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1581 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1582 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1583 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1584 if (!rscreen->use_surface_alloc) {
1585 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1586 0x00000000, NULL, 0);
1587 } else {
1588 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1589 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1590 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer),
1591 NULL, 0);
1592 }
1593
1594 if (rtex->stencil) {
1595 uint64_t stencil_offset =
1596 r600_texture_get_offset(rtex->stencil, level, first_layer);
1597 unsigned stile_split;
1598
1599 stile_split = eg_tile_split(rtex->stencil->surface.tile_split);
1600 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1601 stencil_offset >>= 8;
1602
1603 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1604 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1605 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1606 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1607 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1608 1 | S_028044_TILE_SPLIT(stile_split),
1609 &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1610 } else {
1611 if (rscreen->use_surface_alloc && rtex->surface.flags & RADEON_SURF_SBUFFER) {
1612 uint64_t stencil_offset = rtex->surface.stencil_offset;
1613 unsigned stile_split = rtex->surface.stencil_tile_split;
1614
1615 stile_split = eg_tile_split(stile_split);
1616 stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1617 stencil_offset += rtex->surface.level[level].offset / 4;
1618 stencil_offset >>= 8;
1619
1620 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1621 stencil_offset, &rtex->resource,
1622 RADEON_USAGE_READWRITE);
1623 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1624 stencil_offset, &rtex->resource,
1625 RADEON_USAGE_READWRITE);
1626 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1627 1 | S_028044_TILE_SPLIT(stile_split),
1628 &rtex->resource,
1629 RADEON_USAGE_READWRITE);
1630 } else {
1631 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1632 offset, &rtex->resource,
1633 RADEON_USAGE_READWRITE);
1634 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1635 offset, &rtex->resource,
1636 RADEON_USAGE_READWRITE);
1637 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1638 0, NULL, RADEON_USAGE_READWRITE);
1639 }
1640 }
1641
1642 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, z_info,
1643 &rtex->resource, RADEON_USAGE_READWRITE);
1644 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1645 S_028058_PITCH_TILE_MAX(pitch),
1646 NULL, 0);
1647 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1648 S_02805C_SLICE_TILE_MAX(slice),
1649 NULL, 0);
1650 }
1651
1652 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1653 const struct pipe_framebuffer_state *state)
1654 {
1655 struct r600_context *rctx = (struct r600_context *)ctx;
1656 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1657 uint32_t shader_mask, tl, br;
1658
1659 if (rstate == NULL)
1660 return;
1661
1662 r600_flush_framebuffer(rctx, false);
1663
1664 /* unreference old buffer and reference new one */
1665 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1666
1667 util_copy_framebuffer_state(&rctx->framebuffer, state);
1668
1669 /* build states */
1670 rctx->have_depth_fb = 0;
1671 rctx->nr_cbufs = state->nr_cbufs;
1672 for (int i = 0; i < state->nr_cbufs; i++) {
1673 evergreen_cb(rctx, rstate, state, i);
1674 }
1675 if (state->zsbuf) {
1676 evergreen_db(rctx, rstate, state);
1677 }
1678
1679 shader_mask = 0;
1680 for (int i = 0; i < state->nr_cbufs; i++) {
1681 shader_mask |= 0xf << (i * 4);
1682 }
1683
1684 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1685
1686 r600_pipe_state_add_reg(rstate,
1687 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1688 NULL, 0);
1689 r600_pipe_state_add_reg(rstate,
1690 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1691 NULL, 0);
1692 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1693 shader_mask, NULL, 0);
1694
1695 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1696 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1697 r600_context_pipe_state_set(rctx, rstate);
1698
1699 if (state->zsbuf) {
1700 evergreen_polygon_offset_update(rctx);
1701 }
1702 }
1703
1704 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1705 {
1706 struct radeon_winsys_cs *cs = rctx->cs;
1707 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1708 unsigned db_count_control = 0;
1709 unsigned db_render_override =
1710 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1711 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1712 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1713
1714 if (a->occlusion_query_enabled) {
1715 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1716 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1717 }
1718
1719 r600_write_context_reg(cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1720 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1721 }
1722
1723 void evergreen_init_state_functions(struct r600_context *rctx)
1724 {
1725 r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 6, 0);
1726 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1727
1728 rctx->context.create_blend_state = evergreen_create_blend_state;
1729 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1730 rctx->context.create_fs_state = r600_create_shader_state;
1731 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1732 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1733 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1734 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1735 rctx->context.create_vs_state = r600_create_shader_state;
1736 rctx->context.bind_blend_state = r600_bind_blend_state;
1737 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1738 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1739 rctx->context.bind_fs_state = r600_bind_ps_shader;
1740 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1741 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1742 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1743 rctx->context.bind_vs_state = r600_bind_vs_shader;
1744 rctx->context.delete_blend_state = r600_delete_state;
1745 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1746 rctx->context.delete_fs_state = r600_delete_ps_shader;
1747 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1748 rctx->context.delete_sampler_state = r600_delete_state;
1749 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1750 rctx->context.delete_vs_state = r600_delete_vs_shader;
1751 rctx->context.set_blend_color = r600_set_blend_color;
1752 rctx->context.set_clip_state = evergreen_set_clip_state;
1753 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1754 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1755 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1756 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1757 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1758 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1759 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1760 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1761 rctx->context.set_index_buffer = r600_set_index_buffer;
1762 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1763 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1764 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1765 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1766 rctx->context.texture_barrier = r600_texture_barrier;
1767 rctx->context.create_stream_output_target = r600_create_so_target;
1768 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1769 rctx->context.set_stream_output_targets = r600_set_so_targets;
1770 }
1771
1772 static void cayman_init_atom_start_cs(struct r600_context *rctx)
1773 {
1774 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1775
1776 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1777
1778 /* This must be first. */
1779 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1780 r600_store_value(cb, 0x80000000);
1781 r600_store_value(cb, 0x80000000);
1782
1783 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
1784 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
1785 /* always set the temp clauses */
1786 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
1787
1788 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
1789 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
1790 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
1791
1792 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
1793
1794 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
1795
1796 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
1797 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
1798 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
1799 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
1800 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
1801 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
1802 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
1803 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
1804 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
1805 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
1806 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
1807 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
1808 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
1809 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
1810
1811 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
1812 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
1813 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
1814
1815 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
1816 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
1817 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
1818
1819 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
1820
1821 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
1822
1823 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1824 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
1825 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
1826
1827 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
1828 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
1829 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
1830
1831 r600_store_context_reg(cb, CM_R_028804_DB_EQAA, 0x110000);
1832
1833 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
1834 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
1835 r600_store_value(cb, 0);
1836 r600_store_value(cb, 0);
1837 r600_store_value(cb, 0);
1838 r600_store_value(cb, 0);
1839 r600_store_value(cb, 0);
1840 r600_store_value(cb, 0);
1841 r600_store_value(cb, 0);
1842 r600_store_value(cb, 0);
1843 r600_store_value(cb, 0);
1844 r600_store_value(cb, 0);
1845 r600_store_value(cb, 0);
1846 r600_store_value(cb, 0);
1847 r600_store_value(cb, 0);
1848 r600_store_value(cb, 0);
1849 r600_store_value(cb, 0);
1850 r600_store_value(cb, 0);
1851 r600_store_value(cb, 0);
1852 r600_store_value(cb, 0);
1853 r600_store_value(cb, 0);
1854 r600_store_value(cb, 0);
1855 r600_store_value(cb, 0);
1856 r600_store_value(cb, 0);
1857 r600_store_value(cb, 0);
1858 r600_store_value(cb, 0);
1859 r600_store_value(cb, 0);
1860 r600_store_value(cb, 0);
1861 r600_store_value(cb, 0);
1862 r600_store_value(cb, 0);
1863 r600_store_value(cb, 0);
1864 r600_store_value(cb, 0);
1865 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
1866 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
1867 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
1868
1869 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
1870
1871 r600_store_context_reg_seq(cb, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
1872 r600_store_value(cb, ~0); /* CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 */
1873 r600_store_value(cb, ~0); /* CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 */
1874
1875 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
1876 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
1877 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
1878
1879 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
1880
1881 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
1882 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
1883 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
1884 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
1885
1886 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
1887 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
1888
1889 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
1890 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
1891 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
1892
1893 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1894 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
1895 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
1896 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
1897
1898 r600_store_context_reg_seq(cb, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
1899 r600_store_value(cb, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1900 r600_store_value(cb, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1901
1902 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
1903 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
1904 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
1905 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
1906 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
1907
1908 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
1909 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
1910 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
1911
1912 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
1913 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
1914 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
1915
1916 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
1917 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
1918 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
1919
1920 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
1921 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
1922
1923 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
1924 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
1925 }
1926
1927 void evergreen_init_atom_start_cs(struct r600_context *rctx)
1928 {
1929 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1930 int ps_prio;
1931 int vs_prio;
1932 int gs_prio;
1933 int es_prio;
1934 int hs_prio, cs_prio, ls_prio;
1935 int num_ps_gprs;
1936 int num_vs_gprs;
1937 int num_gs_gprs;
1938 int num_es_gprs;
1939 int num_hs_gprs;
1940 int num_ls_gprs;
1941 int num_temp_gprs;
1942 int num_ps_threads;
1943 int num_vs_threads;
1944 int num_gs_threads;
1945 int num_es_threads;
1946 int num_hs_threads;
1947 int num_ls_threads;
1948 int num_ps_stack_entries;
1949 int num_vs_stack_entries;
1950 int num_gs_stack_entries;
1951 int num_es_stack_entries;
1952 int num_hs_stack_entries;
1953 int num_ls_stack_entries;
1954 enum radeon_family family;
1955 unsigned tmp;
1956
1957 if (rctx->chip_class == CAYMAN) {
1958 cayman_init_atom_start_cs(rctx);
1959 return;
1960 }
1961
1962 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1963
1964 /* This must be first. */
1965 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1966 r600_store_value(cb, 0x80000000);
1967 r600_store_value(cb, 0x80000000);
1968
1969 family = rctx->family;
1970 ps_prio = 0;
1971 vs_prio = 1;
1972 gs_prio = 2;
1973 es_prio = 3;
1974 hs_prio = 0;
1975 ls_prio = 0;
1976 cs_prio = 0;
1977
1978 switch (family) {
1979 case CHIP_CEDAR:
1980 default:
1981 num_ps_gprs = 93;
1982 num_vs_gprs = 46;
1983 num_temp_gprs = 4;
1984 num_gs_gprs = 31;
1985 num_es_gprs = 31;
1986 num_hs_gprs = 23;
1987 num_ls_gprs = 23;
1988 num_ps_threads = 96;
1989 num_vs_threads = 16;
1990 num_gs_threads = 16;
1991 num_es_threads = 16;
1992 num_hs_threads = 16;
1993 num_ls_threads = 16;
1994 num_ps_stack_entries = 42;
1995 num_vs_stack_entries = 42;
1996 num_gs_stack_entries = 42;
1997 num_es_stack_entries = 42;
1998 num_hs_stack_entries = 42;
1999 num_ls_stack_entries = 42;
2000 break;
2001 case CHIP_REDWOOD:
2002 num_ps_gprs = 93;
2003 num_vs_gprs = 46;
2004 num_temp_gprs = 4;
2005 num_gs_gprs = 31;
2006 num_es_gprs = 31;
2007 num_hs_gprs = 23;
2008 num_ls_gprs = 23;
2009 num_ps_threads = 128;
2010 num_vs_threads = 20;
2011 num_gs_threads = 20;
2012 num_es_threads = 20;
2013 num_hs_threads = 20;
2014 num_ls_threads = 20;
2015 num_ps_stack_entries = 42;
2016 num_vs_stack_entries = 42;
2017 num_gs_stack_entries = 42;
2018 num_es_stack_entries = 42;
2019 num_hs_stack_entries = 42;
2020 num_ls_stack_entries = 42;
2021 break;
2022 case CHIP_JUNIPER:
2023 num_ps_gprs = 93;
2024 num_vs_gprs = 46;
2025 num_temp_gprs = 4;
2026 num_gs_gprs = 31;
2027 num_es_gprs = 31;
2028 num_hs_gprs = 23;
2029 num_ls_gprs = 23;
2030 num_ps_threads = 128;
2031 num_vs_threads = 20;
2032 num_gs_threads = 20;
2033 num_es_threads = 20;
2034 num_hs_threads = 20;
2035 num_ls_threads = 20;
2036 num_ps_stack_entries = 85;
2037 num_vs_stack_entries = 85;
2038 num_gs_stack_entries = 85;
2039 num_es_stack_entries = 85;
2040 num_hs_stack_entries = 85;
2041 num_ls_stack_entries = 85;
2042 break;
2043 case CHIP_CYPRESS:
2044 case CHIP_HEMLOCK:
2045 num_ps_gprs = 93;
2046 num_vs_gprs = 46;
2047 num_temp_gprs = 4;
2048 num_gs_gprs = 31;
2049 num_es_gprs = 31;
2050 num_hs_gprs = 23;
2051 num_ls_gprs = 23;
2052 num_ps_threads = 128;
2053 num_vs_threads = 20;
2054 num_gs_threads = 20;
2055 num_es_threads = 20;
2056 num_hs_threads = 20;
2057 num_ls_threads = 20;
2058 num_ps_stack_entries = 85;
2059 num_vs_stack_entries = 85;
2060 num_gs_stack_entries = 85;
2061 num_es_stack_entries = 85;
2062 num_hs_stack_entries = 85;
2063 num_ls_stack_entries = 85;
2064 break;
2065 case CHIP_PALM:
2066 num_ps_gprs = 93;
2067 num_vs_gprs = 46;
2068 num_temp_gprs = 4;
2069 num_gs_gprs = 31;
2070 num_es_gprs = 31;
2071 num_hs_gprs = 23;
2072 num_ls_gprs = 23;
2073 num_ps_threads = 96;
2074 num_vs_threads = 16;
2075 num_gs_threads = 16;
2076 num_es_threads = 16;
2077 num_hs_threads = 16;
2078 num_ls_threads = 16;
2079 num_ps_stack_entries = 42;
2080 num_vs_stack_entries = 42;
2081 num_gs_stack_entries = 42;
2082 num_es_stack_entries = 42;
2083 num_hs_stack_entries = 42;
2084 num_ls_stack_entries = 42;
2085 break;
2086 case CHIP_SUMO:
2087 num_ps_gprs = 93;
2088 num_vs_gprs = 46;
2089 num_temp_gprs = 4;
2090 num_gs_gprs = 31;
2091 num_es_gprs = 31;
2092 num_hs_gprs = 23;
2093 num_ls_gprs = 23;
2094 num_ps_threads = 96;
2095 num_vs_threads = 25;
2096 num_gs_threads = 25;
2097 num_es_threads = 25;
2098 num_hs_threads = 25;
2099 num_ls_threads = 25;
2100 num_ps_stack_entries = 42;
2101 num_vs_stack_entries = 42;
2102 num_gs_stack_entries = 42;
2103 num_es_stack_entries = 42;
2104 num_hs_stack_entries = 42;
2105 num_ls_stack_entries = 42;
2106 break;
2107 case CHIP_SUMO2:
2108 num_ps_gprs = 93;
2109 num_vs_gprs = 46;
2110 num_temp_gprs = 4;
2111 num_gs_gprs = 31;
2112 num_es_gprs = 31;
2113 num_hs_gprs = 23;
2114 num_ls_gprs = 23;
2115 num_ps_threads = 96;
2116 num_vs_threads = 25;
2117 num_gs_threads = 25;
2118 num_es_threads = 25;
2119 num_hs_threads = 25;
2120 num_ls_threads = 25;
2121 num_ps_stack_entries = 85;
2122 num_vs_stack_entries = 85;
2123 num_gs_stack_entries = 85;
2124 num_es_stack_entries = 85;
2125 num_hs_stack_entries = 85;
2126 num_ls_stack_entries = 85;
2127 break;
2128 case CHIP_BARTS:
2129 num_ps_gprs = 93;
2130 num_vs_gprs = 46;
2131 num_temp_gprs = 4;
2132 num_gs_gprs = 31;
2133 num_es_gprs = 31;
2134 num_hs_gprs = 23;
2135 num_ls_gprs = 23;
2136 num_ps_threads = 128;
2137 num_vs_threads = 20;
2138 num_gs_threads = 20;
2139 num_es_threads = 20;
2140 num_hs_threads = 20;
2141 num_ls_threads = 20;
2142 num_ps_stack_entries = 85;
2143 num_vs_stack_entries = 85;
2144 num_gs_stack_entries = 85;
2145 num_es_stack_entries = 85;
2146 num_hs_stack_entries = 85;
2147 num_ls_stack_entries = 85;
2148 break;
2149 case CHIP_TURKS:
2150 num_ps_gprs = 93;
2151 num_vs_gprs = 46;
2152 num_temp_gprs = 4;
2153 num_gs_gprs = 31;
2154 num_es_gprs = 31;
2155 num_hs_gprs = 23;
2156 num_ls_gprs = 23;
2157 num_ps_threads = 128;
2158 num_vs_threads = 20;
2159 num_gs_threads = 20;
2160 num_es_threads = 20;
2161 num_hs_threads = 20;
2162 num_ls_threads = 20;
2163 num_ps_stack_entries = 42;
2164 num_vs_stack_entries = 42;
2165 num_gs_stack_entries = 42;
2166 num_es_stack_entries = 42;
2167 num_hs_stack_entries = 42;
2168 num_ls_stack_entries = 42;
2169 break;
2170 case CHIP_CAICOS:
2171 num_ps_gprs = 93;
2172 num_vs_gprs = 46;
2173 num_temp_gprs = 4;
2174 num_gs_gprs = 31;
2175 num_es_gprs = 31;
2176 num_hs_gprs = 23;
2177 num_ls_gprs = 23;
2178 num_ps_threads = 128;
2179 num_vs_threads = 10;
2180 num_gs_threads = 10;
2181 num_es_threads = 10;
2182 num_hs_threads = 10;
2183 num_ls_threads = 10;
2184 num_ps_stack_entries = 42;
2185 num_vs_stack_entries = 42;
2186 num_gs_stack_entries = 42;
2187 num_es_stack_entries = 42;
2188 num_hs_stack_entries = 42;
2189 num_ls_stack_entries = 42;
2190 break;
2191 }
2192
2193 tmp = 0;
2194 switch (family) {
2195 case CHIP_CEDAR:
2196 case CHIP_PALM:
2197 case CHIP_SUMO:
2198 case CHIP_SUMO2:
2199 case CHIP_CAICOS:
2200 break;
2201 default:
2202 tmp |= S_008C00_VC_ENABLE(1);
2203 break;
2204 }
2205 tmp |= S_008C00_EXPORT_SRC_C(1);
2206 tmp |= S_008C00_CS_PRIO(cs_prio);
2207 tmp |= S_008C00_LS_PRIO(ls_prio);
2208 tmp |= S_008C00_HS_PRIO(hs_prio);
2209 tmp |= S_008C00_PS_PRIO(ps_prio);
2210 tmp |= S_008C00_VS_PRIO(vs_prio);
2211 tmp |= S_008C00_GS_PRIO(gs_prio);
2212 tmp |= S_008C00_ES_PRIO(es_prio);
2213
2214 /* enable dynamic GPR resource management */
2215 if (rctx->screen->info.drm_minor >= 7) {
2216 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2217 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2218 /* always set temp clauses */
2219 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2220 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2221 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2222 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2223 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2224 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2225 S_028838_PS_GPRS(0x1e) |
2226 S_028838_VS_GPRS(0x1e) |
2227 S_028838_GS_GPRS(0x1e) |
2228 S_028838_ES_GPRS(0x1e) |
2229 S_028838_HS_GPRS(0x1e) |
2230 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2231 } else {
2232 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2233 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2234
2235 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2236 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2237 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2238 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2239
2240 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2241 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2242 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2243
2244 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2245 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2246 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2247 }
2248
2249 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2250 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2251 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2252 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2253 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2254 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2255
2256 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2257 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2258 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2259
2260 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2261 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2262 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2263
2264 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2265 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2266 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2267
2268 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2269 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2270 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2271
2272 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2273 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2274
2275 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2276 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2277
2278 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2279
2280 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2281 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2282 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2283 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2284 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2285 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2286 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2287
2288 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2289 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2290 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2291 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2292 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2293
2294 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2295 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2296 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2297 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2298 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2299 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2300 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2301 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2302 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2303 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2304 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2305 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2306 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2307 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2308
2309 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2310 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2311 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2312
2313 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2314 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2315 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2316
2317 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2318
2319 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2320 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2321 r600_store_value(cb, 0);
2322 r600_store_value(cb, 0);
2323 r600_store_value(cb, 0);
2324 r600_store_value(cb, 0);
2325 r600_store_value(cb, 0);
2326 r600_store_value(cb, 0);
2327 r600_store_value(cb, 0);
2328 r600_store_value(cb, 0);
2329 r600_store_value(cb, 0);
2330 r600_store_value(cb, 0);
2331 r600_store_value(cb, 0);
2332 r600_store_value(cb, 0);
2333 r600_store_value(cb, 0);
2334 r600_store_value(cb, 0);
2335 r600_store_value(cb, 0);
2336 r600_store_value(cb, 0);
2337 r600_store_value(cb, 0);
2338 r600_store_value(cb, 0);
2339 r600_store_value(cb, 0);
2340 r600_store_value(cb, 0);
2341 r600_store_value(cb, 0);
2342 r600_store_value(cb, 0);
2343 r600_store_value(cb, 0);
2344 r600_store_value(cb, 0);
2345 r600_store_value(cb, 0);
2346 r600_store_value(cb, 0);
2347 r600_store_value(cb, 0);
2348 r600_store_value(cb, 0);
2349 r600_store_value(cb, 0);
2350 r600_store_value(cb, 0);
2351 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2352 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2353 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2354
2355 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2356
2357 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2358 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2359 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2360
2361 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2362 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2363 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2364
2365 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2366 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2367 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2368
2369 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2370 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2371 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2372
2373 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2374 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2375 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2376 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2377
2378 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2379
2380 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2381 r600_store_value(cb, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
2382 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2383
2384 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 5);
2385 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2386 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2387 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2388 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2389 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
2390
2391 r600_store_context_reg(cb, R_028C3C_PA_SC_AA_MASK, ~0);
2392
2393 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2394 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2395 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2396
2397 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2398 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2399 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2400
2401 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
2402 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
2403 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2404
2405 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2406 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2407
2408 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2409 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2410 }
2411
2412 void evergreen_polygon_offset_update(struct r600_context *rctx)
2413 {
2414 struct r600_pipe_state state;
2415
2416 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2417 state.nregs = 0;
2418 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2419 float offset_units = rctx->rasterizer->offset_units;
2420 unsigned offset_db_fmt_cntl = 0, depth;
2421
2422 switch (rctx->framebuffer.zsbuf->texture->format) {
2423 case PIPE_FORMAT_Z24X8_UNORM:
2424 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2425 depth = -24;
2426 offset_units *= 2.0f;
2427 break;
2428 case PIPE_FORMAT_Z32_FLOAT:
2429 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2430 depth = -23;
2431 offset_units *= 1.0f;
2432 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2433 break;
2434 case PIPE_FORMAT_Z16_UNORM:
2435 depth = -16;
2436 offset_units *= 4.0f;
2437 break;
2438 default:
2439 return;
2440 }
2441 /* XXX some of those reg can be computed with cso */
2442 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2443 r600_pipe_state_add_reg(&state,
2444 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2445 fui(rctx->rasterizer->offset_scale), NULL, 0);
2446 r600_pipe_state_add_reg(&state,
2447 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2448 fui(offset_units), NULL, 0);
2449 r600_pipe_state_add_reg(&state,
2450 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2451 fui(rctx->rasterizer->offset_scale), NULL, 0);
2452 r600_pipe_state_add_reg(&state,
2453 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2454 fui(offset_units), NULL, 0);
2455 r600_pipe_state_add_reg(&state,
2456 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2457 offset_db_fmt_cntl, NULL, 0);
2458 r600_context_pipe_state_set(rctx, &state);
2459 }
2460 }
2461
2462 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2463 {
2464 struct r600_context *rctx = (struct r600_context *)ctx;
2465 struct r600_pipe_state *rstate = &shader->rstate;
2466 struct r600_shader *rshader = &shader->shader;
2467 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2468 int pos_index = -1, face_index = -1;
2469 int ninterp = 0;
2470 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2471 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2472
2473 rstate->nregs = 0;
2474
2475 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2476 for (i = 0; i < rshader->ninput; i++) {
2477 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2478 POSITION goes via GPRs from the SC so isn't counted */
2479 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2480 pos_index = i;
2481 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2482 face_index = i;
2483 else {
2484 ninterp++;
2485 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2486 have_linear = TRUE;
2487 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2488 have_perspective = TRUE;
2489 if (rshader->input[i].centroid)
2490 have_centroid = TRUE;
2491 }
2492
2493 sid = rshader->input[i].spi_sid;
2494
2495 if (sid) {
2496
2497 tmp = S_028644_SEMANTIC(sid);
2498
2499 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2500 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2501 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2502 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2503 tmp |= S_028644_FLAT_SHADE(1);
2504 }
2505
2506 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2507 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2508 tmp |= S_028644_PT_SPRITE_TEX(1);
2509 }
2510
2511 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2512 tmp, NULL, 0);
2513
2514 idx++;
2515 }
2516 }
2517
2518 for (i = 0; i < rshader->noutput; i++) {
2519 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2520 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2521 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2522 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2523 }
2524 if (rshader->uses_kill)
2525 db_shader_control |= S_02880C_KILL_ENABLE(1);
2526
2527 exports_ps = 0;
2528 num_cout = 0;
2529 for (i = 0; i < rshader->noutput; i++) {
2530 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2531 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2532 exports_ps |= 1;
2533 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2534 if (rshader->fs_write_all)
2535 num_cout = rshader->nr_cbufs;
2536 else
2537 num_cout++;
2538 }
2539 }
2540 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2541 if (!exports_ps) {
2542 /* always at least export 1 component per pixel */
2543 exports_ps = 2;
2544 }
2545
2546 if (ninterp == 0) {
2547 ninterp = 1;
2548 have_perspective = TRUE;
2549 }
2550
2551 if (!have_perspective && !have_linear)
2552 have_perspective = TRUE;
2553
2554 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2555 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2556 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2557 spi_input_z = 0;
2558 if (pos_index != -1) {
2559 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2560 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2561 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2562 spi_input_z |= 1;
2563 }
2564
2565 spi_ps_in_control_1 = 0;
2566 if (face_index != -1) {
2567 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2568 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2569 }
2570
2571 spi_baryc_cntl = 0;
2572 if (have_perspective)
2573 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2574 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2575 if (have_linear)
2576 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2577 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2578
2579 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2580 spi_ps_in_control_0, NULL, 0);
2581 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2582 spi_ps_in_control_1, NULL, 0);
2583 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2584 0, NULL, 0);
2585 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0);
2586 r600_pipe_state_add_reg(rstate,
2587 R_0286E0_SPI_BARYC_CNTL,
2588 spi_baryc_cntl,
2589 NULL, 0);
2590
2591 r600_pipe_state_add_reg(rstate,
2592 R_028840_SQ_PGM_START_PS,
2593 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2594 shader->bo, RADEON_USAGE_READ);
2595 r600_pipe_state_add_reg(rstate,
2596 R_028844_SQ_PGM_RESOURCES_PS,
2597 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2598 S_028844_PRIME_CACHE_ON_DRAW(1) |
2599 S_028844_STACK_SIZE(rshader->bc.nstack),
2600 NULL, 0);
2601 r600_pipe_state_add_reg(rstate,
2602 R_02884C_SQ_PGM_EXPORTS_PS,
2603 exports_ps, NULL, 0);
2604 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2605 db_shader_control,
2606 NULL, 0);
2607
2608 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2609 if (rctx->rasterizer)
2610 shader->flatshade = rctx->rasterizer->flatshade;
2611 }
2612
2613 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2614 {
2615 struct r600_context *rctx = (struct r600_context *)ctx;
2616 struct r600_pipe_state *rstate = &shader->rstate;
2617 struct r600_shader *rshader = &shader->shader;
2618 unsigned spi_vs_out_id[10] = {};
2619 unsigned i, tmp, nparams = 0;
2620
2621 /* clear previous register */
2622 rstate->nregs = 0;
2623
2624 for (i = 0; i < rshader->noutput; i++) {
2625 if (rshader->output[i].spi_sid) {
2626 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2627 spi_vs_out_id[nparams / 4] |= tmp;
2628 nparams++;
2629 }
2630 }
2631
2632 for (i = 0; i < 10; i++) {
2633 r600_pipe_state_add_reg(rstate,
2634 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2635 spi_vs_out_id[i], NULL, 0);
2636 }
2637
2638 /* Certain attributes (position, psize, etc.) don't count as params.
2639 * VS is required to export at least one param and r600_shader_from_tgsi()
2640 * takes care of adding a dummy export.
2641 */
2642 if (nparams < 1)
2643 nparams = 1;
2644
2645 r600_pipe_state_add_reg(rstate,
2646 R_0286C4_SPI_VS_OUT_CONFIG,
2647 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2648 NULL, 0);
2649 r600_pipe_state_add_reg(rstate,
2650 R_028860_SQ_PGM_RESOURCES_VS,
2651 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2652 S_028860_STACK_SIZE(rshader->bc.nstack),
2653 NULL, 0);
2654 r600_pipe_state_add_reg(rstate,
2655 R_02885C_SQ_PGM_START_VS,
2656 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2657 shader->bo, RADEON_USAGE_READ);
2658
2659 shader->pa_cl_vs_out_cntl =
2660 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2661 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2662 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2663 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2664 }
2665
2666 void evergreen_fetch_shader(struct pipe_context *ctx,
2667 struct r600_vertex_element *ve)
2668 {
2669 struct r600_context *rctx = (struct r600_context *)ctx;
2670 struct r600_pipe_state *rstate = &ve->rstate;
2671 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2672 rstate->nregs = 0;
2673 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2674 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2675 ve->fetch_shader, RADEON_USAGE_READ);
2676 }
2677
2678 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2679 {
2680 struct pipe_depth_stencil_alpha_state dsa;
2681 struct r600_pipe_state *rstate;
2682
2683 memset(&dsa, 0, sizeof(dsa));
2684
2685 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2686 r600_pipe_state_add_reg(rstate,
2687 R_028000_DB_RENDER_CONTROL,
2688 S_028000_DEPTH_COPY_ENABLE(1) |
2689 S_028000_STENCIL_COPY_ENABLE(1) |
2690 S_028000_COPY_CENTROID(1),
2691 NULL, 0);
2692 /* Don't set the 'is_flush' flag in r600_pipe_dsa, evergreen doesn't need it. */
2693 return rstate;
2694 }
2695
2696 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
2697 struct r600_pipe_resource_state *rstate)
2698 {
2699 rstate->id = R600_PIPE_STATE_RESOURCE;
2700
2701 rstate->val[0] = 0;
2702 rstate->bo[0] = NULL;
2703 rstate->val[1] = 0;
2704 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2705 rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2706 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2707 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2708 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2709 rstate->val[4] = 0;
2710 rstate->val[5] = 0;
2711 rstate->val[6] = 0;
2712 rstate->val[7] = 0xc0000000;
2713 }
2714
2715
2716 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
2717 struct r600_pipe_resource_state *rstate,
2718 struct r600_resource *rbuffer,
2719 unsigned offset, unsigned stride,
2720 enum radeon_bo_usage usage)
2721 {
2722 uint64_t va;
2723
2724 va = r600_resource_va(ctx->screen, (void *)rbuffer);
2725 rstate->bo[0] = rbuffer;
2726 rstate->bo_usage[0] = usage;
2727 rstate->val[0] = (offset + va) & 0xFFFFFFFFUL;
2728 rstate->val[1] = rbuffer->buf->size - offset - 1;
2729 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2730 S_030008_STRIDE(stride) |
2731 (((va + offset) >> 32UL) & 0xFF);
2732 }