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Merge remote-tracking branch 'origin/master' into pipe-video
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "eg_state_inlines.h"
50
51 static void evergreen_set_blend_color(struct pipe_context *ctx,
52 const struct pipe_blend_color *state)
53 {
54 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
55 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
56
57 if (rstate == NULL)
58 return;
59
60 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
61 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
62 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
63 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
65
66 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
67 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
68 r600_context_pipe_state_set(&rctx->ctx, rstate);
69 }
70
71 static void *evergreen_create_blend_state(struct pipe_context *ctx,
72 const struct pipe_blend_state *state)
73 {
74 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
75 struct r600_pipe_state *rstate;
76 u32 color_control, target_mask;
77 /* FIXME there is more then 8 framebuffer */
78 unsigned blend_cntl[8];
79
80 if (blend == NULL) {
81 return NULL;
82 }
83 rstate = &blend->rstate;
84
85 rstate->id = R600_PIPE_STATE_BLEND;
86
87 target_mask = 0;
88 color_control = S_028808_MODE(1);
89 if (state->logicop_enable) {
90 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
91 } else {
92 color_control |= (0xcc << 16);
93 }
94 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
95 if (state->independent_blend_enable) {
96 for (int i = 0; i < 8; i++) {
97 target_mask |= (state->rt[i].colormask << (4 * i));
98 }
99 } else {
100 for (int i = 0; i < 8; i++) {
101 target_mask |= (state->rt[0].colormask << (4 * i));
102 }
103 }
104 blend->cb_target_mask = target_mask;
105 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
106 color_control, 0xFFFFFFFD, NULL);
107 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
108
109 for (int i = 0; i < 8; i++) {
110 /* state->rt entries > 0 only written if independent blending */
111 const int j = state->independent_blend_enable ? i : 0;
112
113 unsigned eqRGB = state->rt[j].rgb_func;
114 unsigned srcRGB = state->rt[j].rgb_src_factor;
115 unsigned dstRGB = state->rt[j].rgb_dst_factor;
116 unsigned eqA = state->rt[j].alpha_func;
117 unsigned srcA = state->rt[j].alpha_src_factor;
118 unsigned dstA = state->rt[j].alpha_dst_factor;
119
120 blend_cntl[i] = 0;
121 if (!state->rt[j].blend_enable)
122 continue;
123
124 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
125 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
126 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
127 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
128
129 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
130 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
131 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
132 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
133 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
134 }
135 }
136 for (int i = 0; i < 8; i++) {
137 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
138 }
139
140 return rstate;
141 }
142
143 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
144 const struct pipe_depth_stencil_alpha_state *state)
145 {
146 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
147 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
148 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
149 struct r600_pipe_state *rstate;
150
151 if (dsa == NULL) {
152 return NULL;
153 }
154
155 rstate = &dsa->rstate;
156
157 rstate->id = R600_PIPE_STATE_DSA;
158 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
159 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
160 stencil_ref_mask = 0;
161 stencil_ref_mask_bf = 0;
162 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
163 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
164 S_028800_ZFUNC(state->depth.func);
165
166 /* stencil */
167 if (state->stencil[0].enabled) {
168 db_depth_control |= S_028800_STENCIL_ENABLE(1);
169 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
170 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
171 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
172 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
173
174
175 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
176 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
177 if (state->stencil[1].enabled) {
178 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
179 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
180 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
181 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
182 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
183 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
184 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
185 }
186 }
187
188 /* alpha */
189 alpha_test_control = 0;
190 alpha_ref = 0;
191 if (state->alpha.enabled) {
192 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
193 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
194 alpha_ref = fui(state->alpha.ref_value);
195 }
196 dsa->alpha_ref = alpha_ref;
197
198 /* misc */
199 db_render_control = 0;
200 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
201 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
202 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
203 /* TODO db_render_override depends on query */
204 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
205 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
206 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
207 r600_pipe_state_add_reg(rstate,
208 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
209 0xFFFFFFFF & C_028430_STENCILREF, NULL);
210 r600_pipe_state_add_reg(rstate,
211 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
212 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
213 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
214 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
215 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
216 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
217 * evergreen_pipe_shader_ps().*/
218 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL);
219 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
220 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
221 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
222 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
223 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
224 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
225
226 return rstate;
227 }
228
229 static void *evergreen_create_rs_state(struct pipe_context *ctx,
230 const struct pipe_rasterizer_state *state)
231 {
232 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
233 struct r600_pipe_state *rstate;
234 unsigned tmp;
235 unsigned prov_vtx = 1, polygon_dual_mode;
236 unsigned clip_rule;
237
238 if (rs == NULL) {
239 return NULL;
240 }
241
242 rstate = &rs->rstate;
243 rs->flatshade = state->flatshade;
244 rs->sprite_coord_enable = state->sprite_coord_enable;
245
246 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
247
248 /* offset */
249 rs->offset_units = state->offset_units;
250 rs->offset_scale = state->offset_scale * 12.0f;
251
252 rstate->id = R600_PIPE_STATE_RASTERIZER;
253 if (state->flatshade_first)
254 prov_vtx = 0;
255 tmp = S_0286D4_FLAT_SHADE_ENA(1);
256 if (state->sprite_coord_enable) {
257 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
258 S_0286D4_PNT_SPRITE_OVRD_X(2) |
259 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
260 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
261 S_0286D4_PNT_SPRITE_OVRD_W(1);
262 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
263 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
264 }
265 }
266 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
267
268 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
269 state->fill_back != PIPE_POLYGON_MODE_FILL);
270 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
271 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
272 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
273 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
274 S_028814_FACE(!state->front_ccw) |
275 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
276 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
277 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
278 S_028814_POLY_MODE(polygon_dual_mode) |
279 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
280 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
281 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
282 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
283 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
284 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
285 /* point size 12.4 fixed point */
286 tmp = (unsigned)(state->point_size * 8.0);
287 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
288 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
289
290 tmp = (unsigned)state->line_width * 8;
291 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
292
293 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
294 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
295 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
296 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
297 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
298 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
299
300 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
301 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
302 0xFFFFFFFF, NULL);
303
304 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
305 return rstate;
306 }
307
308 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
309 const struct pipe_sampler_state *state)
310 {
311 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
312 union util_color uc;
313 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
314
315 if (rstate == NULL) {
316 return NULL;
317 }
318
319 rstate->id = R600_PIPE_STATE_SAMPLER;
320 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
321 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
322 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
323 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
324 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
325 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
326 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
327 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
328 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
329 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
330 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
331 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
332 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
333 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
334 0xFFFFFFFF, NULL);
335 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
336 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
337 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
338 S_03C008_TYPE(1),
339 0xFFFFFFFF, NULL);
340
341 if (uc.ui) {
342 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
343 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
344 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
345 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
346 }
347 return rstate;
348 }
349
350 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
351 struct pipe_resource *texture,
352 const struct pipe_sampler_view *state)
353 {
354 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
355 struct r600_pipe_state *rstate;
356 const struct util_format_description *desc;
357 struct r600_resource_texture *tmp;
358 struct r600_resource *rbuffer;
359 unsigned format, endian;
360 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
361 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
362 struct r600_bo *bo[2];
363
364 if (resource == NULL)
365 return NULL;
366 rstate = &resource->state;
367
368 /* initialize base object */
369 resource->base = *state;
370 resource->base.texture = NULL;
371 pipe_reference(NULL, &texture->reference);
372 resource->base.texture = texture;
373 resource->base.reference.count = 1;
374 resource->base.context = ctx;
375
376 swizzle[0] = state->swizzle_r;
377 swizzle[1] = state->swizzle_g;
378 swizzle[2] = state->swizzle_b;
379 swizzle[3] = state->swizzle_a;
380 format = r600_translate_texformat(ctx->screen, state->format,
381 swizzle,
382 &word4, &yuv_format);
383 if (format == ~0) {
384 format = 0;
385 }
386 desc = util_format_description(state->format);
387 if (desc == NULL) {
388 R600_ERR("unknow format %d\n", state->format);
389 }
390 tmp = (struct r600_resource_texture *)texture;
391 if (tmp->depth && !tmp->is_flushing_texture) {
392 r600_texture_depth_flush(ctx, texture, TRUE);
393 tmp = tmp->flushed_depth_texture;
394 }
395
396 endian = r600_colorformat_endian_swap(format);
397
398 if (tmp->force_int_type) {
399 word4 &= C_030010_NUM_FORMAT_ALL;
400 word4 |= S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_INT);
401 }
402
403 rbuffer = &tmp->resource;
404 bo[0] = rbuffer->bo;
405 bo[1] = rbuffer->bo;
406
407 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
408 array_mode = tmp->array_mode[0];
409 tile_type = tmp->tile_type;
410
411 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
412 S_030000_DIM(r600_tex_dim(texture->target)) |
413 S_030000_PITCH((pitch / 8) - 1) |
414 S_030000_NON_DISP_TILING_ORDER(tile_type) |
415 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
416 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
417 S_030004_TEX_HEIGHT(texture->height0 - 1) |
418 S_030004_TEX_DEPTH(texture->depth0 - 1) |
419 S_030004_ARRAY_MODE(array_mode),
420 0xFFFFFFFF, NULL);
421 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
422 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
423 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
424 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
425 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
426 word4 |
427 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_NO_ZERO) |
428 S_030010_ENDIAN_SWAP(endian) |
429 S_030010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
430 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
431 S_030014_LAST_LEVEL(state->u.tex.last_level) |
432 S_030014_BASE_ARRAY(0) |
433 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
434 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
435 S_030018_MAX_ANISO(4 /* max 16 samples */),
436 0xFFFFFFFF, NULL);
437 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
438 S_03001C_DATA_FORMAT(format) |
439 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
440
441 return &resource->base;
442 }
443
444 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
445 struct pipe_sampler_view **views)
446 {
447 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
448 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
449
450 for (int i = 0; i < count; i++) {
451 if (resource[i]) {
452 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
453 i + R600_MAX_CONST_BUFFERS);
454 }
455 }
456 }
457
458 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
459 struct pipe_sampler_view **views)
460 {
461 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
462 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
463 int i;
464
465 for (i = 0; i < count; i++) {
466 if (&rctx->ps_samplers.views[i]->base != views[i]) {
467 if (resource[i])
468 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
469 i + R600_MAX_CONST_BUFFERS);
470 else
471 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
472 i + R600_MAX_CONST_BUFFERS);
473
474 pipe_sampler_view_reference(
475 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
476 views[i]);
477 }
478 }
479 for (i = count; i < NUM_TEX_UNITS; i++) {
480 if (rctx->ps_samplers.views[i]) {
481 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
482 i + R600_MAX_CONST_BUFFERS);
483 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
484 }
485 }
486 rctx->ps_samplers.n_views = count;
487 }
488
489 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
490 {
491 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
492 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
493
494
495 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
496 rctx->ps_samplers.n_samplers = count;
497
498 for (int i = 0; i < count; i++) {
499 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
500 }
501 }
502
503 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
504 {
505 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
506 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
507
508 for (int i = 0; i < count; i++) {
509 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
510 }
511 }
512
513 static void evergreen_set_clip_state(struct pipe_context *ctx,
514 const struct pipe_clip_state *state)
515 {
516 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
517 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
518
519 if (rstate == NULL)
520 return;
521
522 rctx->clip = *state;
523 rstate->id = R600_PIPE_STATE_CLIP;
524 for (int i = 0; i < state->nr; i++) {
525 r600_pipe_state_add_reg(rstate,
526 R_0285BC_PA_CL_UCP0_X + i * 16,
527 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
528 r600_pipe_state_add_reg(rstate,
529 R_0285C0_PA_CL_UCP0_Y + i * 16,
530 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
531 r600_pipe_state_add_reg(rstate,
532 R_0285C4_PA_CL_UCP0_Z + i * 16,
533 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
534 r600_pipe_state_add_reg(rstate,
535 R_0285C8_PA_CL_UCP0_W + i * 16,
536 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
537 }
538 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
539 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
540 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
541 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
542
543 free(rctx->states[R600_PIPE_STATE_CLIP]);
544 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
545 r600_context_pipe_state_set(&rctx->ctx, rstate);
546 }
547
548 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
549 const struct pipe_poly_stipple *state)
550 {
551 }
552
553 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
554 {
555 }
556
557 static void evergreen_set_scissor_state(struct pipe_context *ctx,
558 const struct pipe_scissor_state *state)
559 {
560 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
561 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
562 u32 tl, br;
563
564 if (rstate == NULL)
565 return;
566
567 rstate->id = R600_PIPE_STATE_SCISSOR;
568 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
569 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
570 r600_pipe_state_add_reg(rstate,
571 R_028210_PA_SC_CLIPRECT_0_TL, tl,
572 0xFFFFFFFF, NULL);
573 r600_pipe_state_add_reg(rstate,
574 R_028214_PA_SC_CLIPRECT_0_BR, br,
575 0xFFFFFFFF, NULL);
576 r600_pipe_state_add_reg(rstate,
577 R_028218_PA_SC_CLIPRECT_1_TL, tl,
578 0xFFFFFFFF, NULL);
579 r600_pipe_state_add_reg(rstate,
580 R_02821C_PA_SC_CLIPRECT_1_BR, br,
581 0xFFFFFFFF, NULL);
582 r600_pipe_state_add_reg(rstate,
583 R_028220_PA_SC_CLIPRECT_2_TL, tl,
584 0xFFFFFFFF, NULL);
585 r600_pipe_state_add_reg(rstate,
586 R_028224_PA_SC_CLIPRECT_2_BR, br,
587 0xFFFFFFFF, NULL);
588 r600_pipe_state_add_reg(rstate,
589 R_028228_PA_SC_CLIPRECT_3_TL, tl,
590 0xFFFFFFFF, NULL);
591 r600_pipe_state_add_reg(rstate,
592 R_02822C_PA_SC_CLIPRECT_3_BR, br,
593 0xFFFFFFFF, NULL);
594
595 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
596 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
597 r600_context_pipe_state_set(&rctx->ctx, rstate);
598 }
599
600 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
601 const struct pipe_stencil_ref *state)
602 {
603 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
604 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
605 u32 tmp;
606
607 if (rstate == NULL)
608 return;
609
610 rctx->stencil_ref = *state;
611 rstate->id = R600_PIPE_STATE_STENCIL_REF;
612 tmp = S_028430_STENCILREF(state->ref_value[0]);
613 r600_pipe_state_add_reg(rstate,
614 R_028430_DB_STENCILREFMASK, tmp,
615 ~C_028430_STENCILREF, NULL);
616 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
617 r600_pipe_state_add_reg(rstate,
618 R_028434_DB_STENCILREFMASK_BF, tmp,
619 ~C_028434_STENCILREF_BF, NULL);
620
621 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
622 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
623 r600_context_pipe_state_set(&rctx->ctx, rstate);
624 }
625
626 static void evergreen_set_viewport_state(struct pipe_context *ctx,
627 const struct pipe_viewport_state *state)
628 {
629 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
630 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
631
632 if (rstate == NULL)
633 return;
634
635 rctx->viewport = *state;
636 rstate->id = R600_PIPE_STATE_VIEWPORT;
637 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
638 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
639 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
640 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
641 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
642 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
643 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
644 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
645 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
646
647 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
648 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
649 r600_context_pipe_state_set(&rctx->ctx, rstate);
650 }
651
652 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
653 const struct pipe_framebuffer_state *state, int cb)
654 {
655 struct r600_resource_texture *rtex;
656 struct r600_resource *rbuffer;
657 struct r600_surface *surf;
658 unsigned level = state->cbufs[cb]->u.tex.level;
659 unsigned pitch, slice;
660 unsigned color_info;
661 unsigned format, swap, ntype, endian;
662 unsigned offset;
663 unsigned tile_type;
664 const struct util_format_description *desc;
665 struct r600_bo *bo[3];
666 int i;
667
668 surf = (struct r600_surface *)state->cbufs[cb];
669 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
670
671 if (rtex->depth && !rtex->is_flushing_texture) {
672 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
673 rtex = rtex->flushed_depth_texture;
674 }
675
676 rbuffer = &rtex->resource;
677 bo[0] = rbuffer->bo;
678 bo[1] = rbuffer->bo;
679 bo[2] = rbuffer->bo;
680
681 /* XXX quite sure for dx10+ hw don't need any offset hacks */
682 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
683 level, state->cbufs[cb]->u.tex.first_layer);
684 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
685 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
686 desc = util_format_description(surf->base.format);
687 for (i = 0; i < 4; i++) {
688 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
689 break;
690 }
691 }
692 ntype = V_028C70_NUMBER_UNORM;
693 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
694 ntype = V_028C70_NUMBER_SRGB;
695 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
696 ntype = V_028C70_NUMBER_SNORM;
697
698 format = r600_translate_colorformat(surf->base.format);
699 swap = r600_translate_colorswap(surf->base.format);
700 if (rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
701 endian = ENDIAN_NONE;
702 } else {
703 endian = r600_colorformat_endian_swap(format);
704 }
705
706 /* disable when gallium grows int textures */
707 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
708 ntype = V_028C70_NUMBER_UINT;
709
710 color_info = S_028C70_FORMAT(format) |
711 S_028C70_COMP_SWAP(swap) |
712 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
713 S_028C70_BLEND_CLAMP(1) |
714 S_028C70_NUMBER_TYPE(ntype) |
715 S_028C70_ENDIAN(endian);
716
717
718 /* EXPORT_NORM is an optimzation that can be enabled for better
719 * performance in certain cases.
720 * EXPORT_NORM can be enabled if:
721 * - 11-bit or smaller UNORM/SNORM/SRGB
722 * - 16-bit or smaller FLOAT
723 */
724 /* FIXME: This should probably be the same for all CBs if we want
725 * useful alpha tests. */
726 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
727 ((desc->channel[i].size < 12 &&
728 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
729 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
730 (desc->channel[i].size < 17 &&
731 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
732 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
733 rctx->export_16bpc = true;
734 } else {
735 rctx->export_16bpc = false;
736 }
737 rctx->alpha_ref_dirty = true;
738
739 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
740 tile_type = rtex->tile_type;
741 } else /* workaround for linear buffers */
742 tile_type = 1;
743
744 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
745 r600_pipe_state_add_reg(rstate,
746 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
747 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
748 r600_pipe_state_add_reg(rstate,
749 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
750 0x0, 0xFFFFFFFF, NULL);
751 r600_pipe_state_add_reg(rstate,
752 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
753 color_info, 0xFFFFFFFF, bo[0]);
754 r600_pipe_state_add_reg(rstate,
755 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
756 S_028C64_PITCH_TILE_MAX(pitch),
757 0xFFFFFFFF, NULL);
758 r600_pipe_state_add_reg(rstate,
759 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
760 S_028C68_SLICE_TILE_MAX(slice),
761 0xFFFFFFFF, NULL);
762 r600_pipe_state_add_reg(rstate,
763 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
764 0x00000000, 0xFFFFFFFF, NULL);
765 r600_pipe_state_add_reg(rstate,
766 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
767 S_028C74_NON_DISP_TILING_ORDER(tile_type),
768 0xFFFFFFFF, bo[0]);
769 }
770
771 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
772 const struct pipe_framebuffer_state *state)
773 {
774 struct r600_resource_texture *rtex;
775 struct r600_resource *rbuffer;
776 struct r600_surface *surf;
777 unsigned level;
778 unsigned pitch, slice, format, stencil_format;
779 unsigned offset;
780
781 if (state->zsbuf == NULL)
782 return;
783
784 level = state->zsbuf->u.tex.level;
785
786 surf = (struct r600_surface *)state->zsbuf;
787 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
788
789 rbuffer = &rtex->resource;
790
791 /* XXX quite sure for dx10+ hw don't need any offset hacks */
792 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
793 level, state->zsbuf->u.tex.first_layer);
794 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
795 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
796 format = r600_translate_dbformat(state->zsbuf->texture->format);
797 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
798
799 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
800 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
801 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
802 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
803
804 if (stencil_format) {
805 uint32_t stencil_offset;
806
807 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
808 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
809 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
810 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
811 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
812 }
813
814 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
815 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
816 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
817
818 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
819 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
820 0xFFFFFFFF, rbuffer->bo);
821 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
822 S_028058_PITCH_TILE_MAX(pitch),
823 0xFFFFFFFF, NULL);
824 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
825 S_02805C_SLICE_TILE_MAX(slice),
826 0xFFFFFFFF, NULL);
827 }
828
829 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
830 const struct pipe_framebuffer_state *state)
831 {
832 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
833 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
834 u32 shader_mask, tl, br, target_mask;
835
836 if (rstate == NULL)
837 return;
838
839 evergreen_context_flush_dest_caches(&rctx->ctx);
840 rctx->ctx.num_dest_buffers = state->nr_cbufs;
841
842 /* unreference old buffer and reference new one */
843 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
844
845 util_copy_framebuffer_state(&rctx->framebuffer, state);
846
847 /* build states */
848 for (int i = 0; i < state->nr_cbufs; i++) {
849 evergreen_cb(rctx, rstate, state, i);
850 }
851 if (state->zsbuf) {
852 evergreen_db(rctx, rstate, state);
853 rctx->ctx.num_dest_buffers++;
854 }
855
856 target_mask = 0x00000000;
857 target_mask = 0xFFFFFFFF;
858 shader_mask = 0;
859 for (int i = 0; i < state->nr_cbufs; i++) {
860 target_mask ^= 0xf << (i * 4);
861 shader_mask |= 0xf << (i * 4);
862 }
863 tl = S_028240_TL_X(0) | S_028240_TL_Y(0);
864 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
865
866 r600_pipe_state_add_reg(rstate,
867 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
868 0xFFFFFFFF, NULL);
869 r600_pipe_state_add_reg(rstate,
870 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
871 0xFFFFFFFF, NULL);
872 r600_pipe_state_add_reg(rstate,
873 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
874 0xFFFFFFFF, NULL);
875 r600_pipe_state_add_reg(rstate,
876 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
877 0xFFFFFFFF, NULL);
878 r600_pipe_state_add_reg(rstate,
879 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
880 0xFFFFFFFF, NULL);
881 r600_pipe_state_add_reg(rstate,
882 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
883 0xFFFFFFFF, NULL);
884 r600_pipe_state_add_reg(rstate,
885 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
886 0xFFFFFFFF, NULL);
887 r600_pipe_state_add_reg(rstate,
888 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
889 0xFFFFFFFF, NULL);
890 r600_pipe_state_add_reg(rstate,
891 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
892 0xFFFFFFFF, NULL);
893 r600_pipe_state_add_reg(rstate,
894 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
895 0xFFFFFFFF, NULL);
896
897 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
898 0x00000000, target_mask, NULL);
899 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
900 shader_mask, 0xFFFFFFFF, NULL);
901 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
902 0x00000000, 0xFFFFFFFF, NULL);
903 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
904 0x00000000, 0xFFFFFFFF, NULL);
905
906 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
907 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
908 r600_context_pipe_state_set(&rctx->ctx, rstate);
909
910 if (state->zsbuf) {
911 evergreen_polygon_offset_update(rctx);
912 }
913 }
914
915 static void evergreen_texture_barrier(struct pipe_context *ctx)
916 {
917 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
918
919 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
920 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
921 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
922 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
923 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
924 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
925 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
926 }
927
928 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
929 {
930 rctx->context.create_blend_state = evergreen_create_blend_state;
931 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
932 rctx->context.create_fs_state = r600_create_shader_state;
933 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
934 rctx->context.create_sampler_state = evergreen_create_sampler_state;
935 rctx->context.create_sampler_view = evergreen_create_sampler_view;
936 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
937 rctx->context.create_vs_state = r600_create_shader_state;
938 rctx->context.bind_blend_state = r600_bind_blend_state;
939 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
940 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
941 rctx->context.bind_fs_state = r600_bind_ps_shader;
942 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
943 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
944 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
945 rctx->context.bind_vs_state = r600_bind_vs_shader;
946 rctx->context.delete_blend_state = r600_delete_state;
947 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
948 rctx->context.delete_fs_state = r600_delete_ps_shader;
949 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
950 rctx->context.delete_sampler_state = r600_delete_state;
951 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
952 rctx->context.delete_vs_state = r600_delete_vs_shader;
953 rctx->context.set_blend_color = evergreen_set_blend_color;
954 rctx->context.set_clip_state = evergreen_set_clip_state;
955 rctx->context.set_constant_buffer = r600_set_constant_buffer;
956 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
957 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
958 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
959 rctx->context.set_sample_mask = evergreen_set_sample_mask;
960 rctx->context.set_scissor_state = evergreen_set_scissor_state;
961 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
962 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
963 rctx->context.set_index_buffer = r600_set_index_buffer;
964 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
965 rctx->context.set_viewport_state = evergreen_set_viewport_state;
966 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
967 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
968 rctx->context.texture_barrier = evergreen_texture_barrier;
969 }
970
971 void evergreen_init_config(struct r600_pipe_context *rctx)
972 {
973 struct r600_pipe_state *rstate = &rctx->config;
974 int ps_prio;
975 int vs_prio;
976 int gs_prio;
977 int es_prio;
978 int hs_prio, cs_prio, ls_prio;
979 int num_ps_gprs;
980 int num_vs_gprs;
981 int num_gs_gprs;
982 int num_es_gprs;
983 int num_hs_gprs;
984 int num_ls_gprs;
985 int num_temp_gprs;
986 int num_ps_threads;
987 int num_vs_threads;
988 int num_gs_threads;
989 int num_es_threads;
990 int num_hs_threads;
991 int num_ls_threads;
992 int num_ps_stack_entries;
993 int num_vs_stack_entries;
994 int num_gs_stack_entries;
995 int num_es_stack_entries;
996 int num_hs_stack_entries;
997 int num_ls_stack_entries;
998 enum radeon_family family;
999 unsigned tmp;
1000
1001 family = r600_get_family(rctx->radeon);
1002 ps_prio = 0;
1003 vs_prio = 1;
1004 gs_prio = 2;
1005 es_prio = 3;
1006 hs_prio = 0;
1007 ls_prio = 0;
1008 cs_prio = 0;
1009
1010 switch (family) {
1011 case CHIP_CEDAR:
1012 default:
1013 num_ps_gprs = 93;
1014 num_vs_gprs = 46;
1015 num_temp_gprs = 4;
1016 num_gs_gprs = 31;
1017 num_es_gprs = 31;
1018 num_hs_gprs = 23;
1019 num_ls_gprs = 23;
1020 num_ps_threads = 96;
1021 num_vs_threads = 16;
1022 num_gs_threads = 16;
1023 num_es_threads = 16;
1024 num_hs_threads = 16;
1025 num_ls_threads = 16;
1026 num_ps_stack_entries = 42;
1027 num_vs_stack_entries = 42;
1028 num_gs_stack_entries = 42;
1029 num_es_stack_entries = 42;
1030 num_hs_stack_entries = 42;
1031 num_ls_stack_entries = 42;
1032 break;
1033 case CHIP_REDWOOD:
1034 num_ps_gprs = 93;
1035 num_vs_gprs = 46;
1036 num_temp_gprs = 4;
1037 num_gs_gprs = 31;
1038 num_es_gprs = 31;
1039 num_hs_gprs = 23;
1040 num_ls_gprs = 23;
1041 num_ps_threads = 128;
1042 num_vs_threads = 20;
1043 num_gs_threads = 20;
1044 num_es_threads = 20;
1045 num_hs_threads = 20;
1046 num_ls_threads = 20;
1047 num_ps_stack_entries = 42;
1048 num_vs_stack_entries = 42;
1049 num_gs_stack_entries = 42;
1050 num_es_stack_entries = 42;
1051 num_hs_stack_entries = 42;
1052 num_ls_stack_entries = 42;
1053 break;
1054 case CHIP_JUNIPER:
1055 num_ps_gprs = 93;
1056 num_vs_gprs = 46;
1057 num_temp_gprs = 4;
1058 num_gs_gprs = 31;
1059 num_es_gprs = 31;
1060 num_hs_gprs = 23;
1061 num_ls_gprs = 23;
1062 num_ps_threads = 128;
1063 num_vs_threads = 20;
1064 num_gs_threads = 20;
1065 num_es_threads = 20;
1066 num_hs_threads = 20;
1067 num_ls_threads = 20;
1068 num_ps_stack_entries = 85;
1069 num_vs_stack_entries = 85;
1070 num_gs_stack_entries = 85;
1071 num_es_stack_entries = 85;
1072 num_hs_stack_entries = 85;
1073 num_ls_stack_entries = 85;
1074 break;
1075 case CHIP_CYPRESS:
1076 case CHIP_HEMLOCK:
1077 num_ps_gprs = 93;
1078 num_vs_gprs = 46;
1079 num_temp_gprs = 4;
1080 num_gs_gprs = 31;
1081 num_es_gprs = 31;
1082 num_hs_gprs = 23;
1083 num_ls_gprs = 23;
1084 num_ps_threads = 128;
1085 num_vs_threads = 20;
1086 num_gs_threads = 20;
1087 num_es_threads = 20;
1088 num_hs_threads = 20;
1089 num_ls_threads = 20;
1090 num_ps_stack_entries = 85;
1091 num_vs_stack_entries = 85;
1092 num_gs_stack_entries = 85;
1093 num_es_stack_entries = 85;
1094 num_hs_stack_entries = 85;
1095 num_ls_stack_entries = 85;
1096 break;
1097 case CHIP_PALM:
1098 num_ps_gprs = 93;
1099 num_vs_gprs = 46;
1100 num_temp_gprs = 4;
1101 num_gs_gprs = 31;
1102 num_es_gprs = 31;
1103 num_hs_gprs = 23;
1104 num_ls_gprs = 23;
1105 num_ps_threads = 96;
1106 num_vs_threads = 16;
1107 num_gs_threads = 16;
1108 num_es_threads = 16;
1109 num_hs_threads = 16;
1110 num_ls_threads = 16;
1111 num_ps_stack_entries = 42;
1112 num_vs_stack_entries = 42;
1113 num_gs_stack_entries = 42;
1114 num_es_stack_entries = 42;
1115 num_hs_stack_entries = 42;
1116 num_ls_stack_entries = 42;
1117 break;
1118 case CHIP_BARTS:
1119 num_ps_gprs = 93;
1120 num_vs_gprs = 46;
1121 num_temp_gprs = 4;
1122 num_gs_gprs = 31;
1123 num_es_gprs = 31;
1124 num_hs_gprs = 23;
1125 num_ls_gprs = 23;
1126 num_ps_threads = 128;
1127 num_vs_threads = 20;
1128 num_gs_threads = 20;
1129 num_es_threads = 20;
1130 num_hs_threads = 20;
1131 num_ls_threads = 20;
1132 num_ps_stack_entries = 85;
1133 num_vs_stack_entries = 85;
1134 num_gs_stack_entries = 85;
1135 num_es_stack_entries = 85;
1136 num_hs_stack_entries = 85;
1137 num_ls_stack_entries = 85;
1138 break;
1139 case CHIP_TURKS:
1140 num_ps_gprs = 93;
1141 num_vs_gprs = 46;
1142 num_temp_gprs = 4;
1143 num_gs_gprs = 31;
1144 num_es_gprs = 31;
1145 num_hs_gprs = 23;
1146 num_ls_gprs = 23;
1147 num_ps_threads = 128;
1148 num_vs_threads = 20;
1149 num_gs_threads = 20;
1150 num_es_threads = 20;
1151 num_hs_threads = 20;
1152 num_ls_threads = 20;
1153 num_ps_stack_entries = 42;
1154 num_vs_stack_entries = 42;
1155 num_gs_stack_entries = 42;
1156 num_es_stack_entries = 42;
1157 num_hs_stack_entries = 42;
1158 num_ls_stack_entries = 42;
1159 break;
1160 case CHIP_CAICOS:
1161 num_ps_gprs = 93;
1162 num_vs_gprs = 46;
1163 num_temp_gprs = 4;
1164 num_gs_gprs = 31;
1165 num_es_gprs = 31;
1166 num_hs_gprs = 23;
1167 num_ls_gprs = 23;
1168 num_ps_threads = 128;
1169 num_vs_threads = 10;
1170 num_gs_threads = 10;
1171 num_es_threads = 10;
1172 num_hs_threads = 10;
1173 num_ls_threads = 10;
1174 num_ps_stack_entries = 42;
1175 num_vs_stack_entries = 42;
1176 num_gs_stack_entries = 42;
1177 num_es_stack_entries = 42;
1178 num_hs_stack_entries = 42;
1179 num_ls_stack_entries = 42;
1180 break;
1181 }
1182
1183 tmp = 0x00000000;
1184 switch (family) {
1185 case CHIP_CEDAR:
1186 case CHIP_PALM:
1187 case CHIP_CAICOS:
1188 break;
1189 default:
1190 tmp |= S_008C00_VC_ENABLE(1);
1191 break;
1192 }
1193 tmp |= S_008C00_EXPORT_SRC_C(1);
1194 tmp |= S_008C00_CS_PRIO(cs_prio);
1195 tmp |= S_008C00_LS_PRIO(ls_prio);
1196 tmp |= S_008C00_HS_PRIO(hs_prio);
1197 tmp |= S_008C00_PS_PRIO(ps_prio);
1198 tmp |= S_008C00_VS_PRIO(vs_prio);
1199 tmp |= S_008C00_GS_PRIO(gs_prio);
1200 tmp |= S_008C00_ES_PRIO(es_prio);
1201 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1202
1203 tmp = 0;
1204 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1205 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1206 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1207 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1208
1209 tmp = 0;
1210 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1211 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1212 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1213
1214 tmp = 0;
1215 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1216 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1217 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1218
1219 tmp = 0;
1220 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1221 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1222 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1223 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1224 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1225
1226 tmp = 0;
1227 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1228 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1229 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1230
1231 tmp = 0;
1232 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1233 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1234 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1235
1236 tmp = 0;
1237 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1238 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1239 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1240
1241 tmp = 0;
1242 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1243 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1244 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1245
1246 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1247 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1248
1249 #if 0
1250 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1251
1252 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1253 #endif
1254 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1255 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1256
1257 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1258 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1259 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1260 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1261 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1262 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1263
1264 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1265 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1266 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1267 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1268
1269 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1270 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1271 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1272 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1273 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1274 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1275 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1276 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1277 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1278 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1279 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1280 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1281 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1282 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1283 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1284 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1285 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1286 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1287
1288 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1289 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1290 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1291 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1292 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1293 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1294 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1295 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1296 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1297 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1298 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1299 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1300 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1301 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1302 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1303 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1304 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1305 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1306 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1307 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1308 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1309 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1310 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1311 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1312 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1313 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1314 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1315 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1316 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1317 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1318 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1319 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1320
1321 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
1322
1323 r600_context_pipe_state_set(&rctx->ctx, rstate);
1324 }
1325
1326 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
1327 {
1328 struct r600_pipe_state state;
1329
1330 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
1331 state.nregs = 0;
1332 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1333 float offset_units = rctx->rasterizer->offset_units;
1334 unsigned offset_db_fmt_cntl = 0, depth;
1335
1336 switch (rctx->framebuffer.zsbuf->texture->format) {
1337 case PIPE_FORMAT_Z24X8_UNORM:
1338 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1339 depth = -24;
1340 offset_units *= 2.0f;
1341 break;
1342 case PIPE_FORMAT_Z32_FLOAT:
1343 depth = -23;
1344 offset_units *= 1.0f;
1345 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1346 break;
1347 case PIPE_FORMAT_Z16_UNORM:
1348 depth = -16;
1349 offset_units *= 4.0f;
1350 break;
1351 default:
1352 return;
1353 }
1354 /* FIXME some of those reg can be computed with cso */
1355 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1356 r600_pipe_state_add_reg(&state,
1357 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1358 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1359 r600_pipe_state_add_reg(&state,
1360 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1361 fui(offset_units), 0xFFFFFFFF, NULL);
1362 r600_pipe_state_add_reg(&state,
1363 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1364 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1365 r600_pipe_state_add_reg(&state,
1366 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1367 fui(offset_units), 0xFFFFFFFF, NULL);
1368 r600_pipe_state_add_reg(&state,
1369 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1370 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1371 r600_context_pipe_state_set(&rctx->ctx, &state);
1372 }
1373 }
1374
1375 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1376 {
1377 struct r600_pipe_state *rstate = &shader->rstate;
1378 struct r600_shader *rshader = &shader->shader;
1379 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
1380 int pos_index = -1, face_index = -1;
1381 int ninterp = 0;
1382 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1383 unsigned spi_baryc_cntl;
1384
1385 rstate->nregs = 0;
1386
1387 db_shader_control = 0;
1388 for (i = 0; i < rshader->ninput; i++) {
1389 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1390 POSITION goes via GPRs from the SC so isn't counted */
1391 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1392 pos_index = i;
1393 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1394 face_index = i;
1395 else {
1396 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
1397 rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1398 ninterp++;
1399 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1400 have_linear = TRUE;
1401 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1402 have_perspective = TRUE;
1403 if (rshader->input[i].centroid)
1404 have_centroid = TRUE;
1405 }
1406 }
1407 for (i = 0; i < rshader->noutput; i++) {
1408 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1409 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1410 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1411 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
1412 }
1413 if (rshader->uses_kill)
1414 db_shader_control |= S_02880C_KILL_ENABLE(1);
1415
1416 exports_ps = 0;
1417 num_cout = 0;
1418 for (i = 0; i < rshader->noutput; i++) {
1419 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1420 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1421 exports_ps |= 1;
1422 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1423 num_cout++;
1424 }
1425 }
1426 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1427 if (!exports_ps) {
1428 /* always at least export 1 component per pixel */
1429 exports_ps = 2;
1430 }
1431
1432 if (ninterp == 0) {
1433 ninterp = 1;
1434 have_perspective = TRUE;
1435 }
1436
1437 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
1438 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
1439 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
1440 spi_input_z = 0;
1441 if (pos_index != -1) {
1442 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
1443 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1444 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
1445 spi_input_z |= 1;
1446 }
1447
1448 spi_ps_in_control_1 = 0;
1449 if (face_index != -1) {
1450 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1451 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1452 }
1453
1454 spi_baryc_cntl = 0;
1455 if (have_perspective)
1456 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
1457 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
1458 if (have_linear)
1459 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
1460 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
1461
1462 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1463 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1464 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1465 spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1466 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
1467 0, 0xFFFFFFFF, NULL);
1468 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1469 r600_pipe_state_add_reg(rstate,
1470 R_0286E0_SPI_BARYC_CNTL,
1471 spi_baryc_cntl,
1472 0xFFFFFFFF, NULL);
1473
1474 r600_pipe_state_add_reg(rstate,
1475 R_028840_SQ_PGM_START_PS,
1476 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1477 r600_pipe_state_add_reg(rstate,
1478 R_028844_SQ_PGM_RESOURCES_PS,
1479 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1480 S_028844_PRIME_CACHE_ON_DRAW(1) |
1481 S_028844_STACK_SIZE(rshader->bc.nstack),
1482 0xFFFFFFFF, NULL);
1483 r600_pipe_state_add_reg(rstate,
1484 R_028848_SQ_PGM_RESOURCES_2_PS,
1485 0x0, 0xFFFFFFFF, NULL);
1486 r600_pipe_state_add_reg(rstate,
1487 R_02884C_SQ_PGM_EXPORTS_PS,
1488 exports_ps, 0xFFFFFFFF, NULL);
1489 /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */
1490 /* only set some bits here, the other bits are set in the dsa state */
1491 r600_pipe_state_add_reg(rstate,
1492 R_02880C_DB_SHADER_CONTROL,
1493 db_shader_control,
1494 S_02880C_Z_EXPORT_ENABLE(1) |
1495 S_02880C_STENCIL_EXPORT_ENABLE(1) |
1496 S_02880C_KILL_ENABLE(1),
1497 NULL);
1498 r600_pipe_state_add_reg(rstate,
1499 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
1500 0xFFFFFFFF, NULL);
1501 }
1502
1503 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1504 {
1505 struct r600_pipe_state *rstate = &shader->rstate;
1506 struct r600_shader *rshader = &shader->shader;
1507 unsigned spi_vs_out_id[10];
1508 unsigned i, tmp;
1509
1510 /* clear previous register */
1511 rstate->nregs = 0;
1512
1513 /* so far never got proper semantic id from tgsi */
1514 for (i = 0; i < 10; i++) {
1515 spi_vs_out_id[i] = 0;
1516 }
1517 for (i = 0; i < 32; i++) {
1518 tmp = i << ((i & 3) * 8);
1519 spi_vs_out_id[i / 4] |= tmp;
1520 }
1521 for (i = 0; i < 10; i++) {
1522 r600_pipe_state_add_reg(rstate,
1523 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1524 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1525 }
1526
1527 r600_pipe_state_add_reg(rstate,
1528 R_0286C4_SPI_VS_OUT_CONFIG,
1529 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1530 0xFFFFFFFF, NULL);
1531 r600_pipe_state_add_reg(rstate,
1532 R_028860_SQ_PGM_RESOURCES_VS,
1533 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1534 S_028860_STACK_SIZE(rshader->bc.nstack),
1535 0xFFFFFFFF, NULL);
1536 r600_pipe_state_add_reg(rstate,
1537 R_028864_SQ_PGM_RESOURCES_2_VS,
1538 0x0, 0xFFFFFFFF, NULL);
1539 r600_pipe_state_add_reg(rstate,
1540 R_02885C_SQ_PGM_START_VS,
1541 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1542
1543 r600_pipe_state_add_reg(rstate,
1544 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1545 0xFFFFFFFF, NULL);
1546 }
1547
1548 void evergreen_fetch_shader(struct r600_vertex_element *ve)
1549 {
1550 struct r600_pipe_state *rstate = &ve->rstate;
1551 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1552 rstate->nregs = 0;
1553 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
1554 0x00000000, 0xFFFFFFFF, NULL);
1555 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
1556 (r600_bo_offset(ve->fetch_shader)) >> 8,
1557 0xFFFFFFFF, ve->fetch_shader);
1558 }
1559
1560 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1561 {
1562 struct pipe_depth_stencil_alpha_state dsa;
1563 struct r600_pipe_state *rstate;
1564
1565 memset(&dsa, 0, sizeof(dsa));
1566
1567 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1568 r600_pipe_state_add_reg(rstate,
1569 R_02880C_DB_SHADER_CONTROL,
1570 0x0,
1571 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1572 r600_pipe_state_add_reg(rstate,
1573 R_028000_DB_RENDER_CONTROL,
1574 S_028000_DEPTH_COPY_ENABLE(1) |
1575 S_028000_STENCIL_COPY_ENABLE(1) |
1576 S_028000_COPY_CENTROID(1),
1577 S_028000_DEPTH_COPY_ENABLE(1) |
1578 S_028000_STENCIL_COPY_ENABLE(1) |
1579 S_028000_COPY_CENTROID(1), NULL);
1580 return rstate;
1581 }
1582
1583 void evergreen_pipe_set_buffer_resource(struct r600_pipe_context *rctx,
1584 struct r600_pipe_state *rstate,
1585 struct r600_resource *rbuffer,
1586 unsigned offset, unsigned stride)
1587 {
1588 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
1589 offset, 0xFFFFFFFF, rbuffer->bo);
1590 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
1591 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
1592 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
1593 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1594 S_030008_STRIDE(stride), 0xFFFFFFFF, NULL);
1595 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
1596 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1597 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1598 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1599 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W),
1600 0xFFFFFFFF, NULL);
1601 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
1602 0x00000000, 0xFFFFFFFF, NULL);
1603 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
1604 0x00000000, 0xFFFFFFFF, NULL);
1605 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
1606 0x00000000, 0xFFFFFFFF, NULL);
1607 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
1608 0xC0000000, 0xFFFFFFFF, NULL);
1609 }