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r600g: cleanup deprecated register tables
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static INLINE unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
39 break;
40 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
41 break;
42 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
43 default:
44 case RADEON_SURF_MODE_LINEAR: return V_028C70_ARRAY_LINEAR_GENERAL;
45 }
46 }
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
174 {
175 switch (dim) {
176 default:
177 case PIPE_TEXTURE_1D:
178 return V_030000_SQ_TEX_DIM_1D;
179 case PIPE_TEXTURE_1D_ARRAY:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY;
181 case PIPE_TEXTURE_2D:
182 case PIPE_TEXTURE_RECT:
183 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
184 V_030000_SQ_TEX_DIM_2D;
185 case PIPE_TEXTURE_2D_ARRAY:
186 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
187 V_030000_SQ_TEX_DIM_2D_ARRAY;
188 case PIPE_TEXTURE_3D:
189 return V_030000_SQ_TEX_DIM_3D;
190 case PIPE_TEXTURE_CUBE:
191 case PIPE_TEXTURE_CUBE_ARRAY:
192 return V_030000_SQ_TEX_DIM_CUBEMAP;
193 }
194 }
195
196 static uint32_t r600_translate_dbformat(enum pipe_format format)
197 {
198 switch (format) {
199 case PIPE_FORMAT_Z16_UNORM:
200 return V_028040_Z_16;
201 case PIPE_FORMAT_Z24X8_UNORM:
202 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
203 case PIPE_FORMAT_X8Z24_UNORM:
204 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
205 return V_028040_Z_24;
206 case PIPE_FORMAT_Z32_FLOAT:
207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
208 return V_028040_Z_32_FLOAT;
209 default:
210 return ~0U;
211 }
212 }
213
214 static uint32_t r600_translate_colorswap(enum pipe_format format)
215 {
216 switch (format) {
217 /* 8-bit buffers. */
218 case PIPE_FORMAT_L4A4_UNORM:
219 case PIPE_FORMAT_A4R4_UNORM:
220 return V_028C70_SWAP_ALT;
221
222 case PIPE_FORMAT_A8_UNORM:
223 case PIPE_FORMAT_A8_SNORM:
224 case PIPE_FORMAT_A8_UINT:
225 case PIPE_FORMAT_A8_SINT:
226 case PIPE_FORMAT_A16_UNORM:
227 case PIPE_FORMAT_A16_SNORM:
228 case PIPE_FORMAT_A16_UINT:
229 case PIPE_FORMAT_A16_SINT:
230 case PIPE_FORMAT_A16_FLOAT:
231 case PIPE_FORMAT_A32_UINT:
232 case PIPE_FORMAT_A32_SINT:
233 case PIPE_FORMAT_A32_FLOAT:
234 case PIPE_FORMAT_R4A4_UNORM:
235 return V_028C70_SWAP_ALT_REV;
236 case PIPE_FORMAT_I8_UNORM:
237 case PIPE_FORMAT_I8_SNORM:
238 case PIPE_FORMAT_I8_UINT:
239 case PIPE_FORMAT_I8_SINT:
240 case PIPE_FORMAT_I16_UNORM:
241 case PIPE_FORMAT_I16_SNORM:
242 case PIPE_FORMAT_I16_UINT:
243 case PIPE_FORMAT_I16_SINT:
244 case PIPE_FORMAT_I16_FLOAT:
245 case PIPE_FORMAT_I32_UINT:
246 case PIPE_FORMAT_I32_SINT:
247 case PIPE_FORMAT_I32_FLOAT:
248 case PIPE_FORMAT_L8_UNORM:
249 case PIPE_FORMAT_L8_SNORM:
250 case PIPE_FORMAT_L8_UINT:
251 case PIPE_FORMAT_L8_SINT:
252 case PIPE_FORMAT_L8_SRGB:
253 case PIPE_FORMAT_L16_UNORM:
254 case PIPE_FORMAT_L16_SNORM:
255 case PIPE_FORMAT_L16_UINT:
256 case PIPE_FORMAT_L16_SINT:
257 case PIPE_FORMAT_L16_FLOAT:
258 case PIPE_FORMAT_L32_UINT:
259 case PIPE_FORMAT_L32_SINT:
260 case PIPE_FORMAT_L32_FLOAT:
261 case PIPE_FORMAT_R8_UNORM:
262 case PIPE_FORMAT_R8_SNORM:
263 case PIPE_FORMAT_R8_UINT:
264 case PIPE_FORMAT_R8_SINT:
265 return V_028C70_SWAP_STD;
266
267 /* 16-bit buffers. */
268 case PIPE_FORMAT_B5G6R5_UNORM:
269 return V_028C70_SWAP_STD_REV;
270
271 case PIPE_FORMAT_B5G5R5A1_UNORM:
272 case PIPE_FORMAT_B5G5R5X1_UNORM:
273 return V_028C70_SWAP_ALT;
274
275 case PIPE_FORMAT_B4G4R4A4_UNORM:
276 case PIPE_FORMAT_B4G4R4X4_UNORM:
277 return V_028C70_SWAP_ALT;
278
279 case PIPE_FORMAT_Z16_UNORM:
280 return V_028C70_SWAP_STD;
281
282 case PIPE_FORMAT_L8A8_UNORM:
283 case PIPE_FORMAT_L8A8_SNORM:
284 case PIPE_FORMAT_L8A8_UINT:
285 case PIPE_FORMAT_L8A8_SINT:
286 case PIPE_FORMAT_L8A8_SRGB:
287 case PIPE_FORMAT_L16A16_UNORM:
288 case PIPE_FORMAT_L16A16_SNORM:
289 case PIPE_FORMAT_L16A16_UINT:
290 case PIPE_FORMAT_L16A16_SINT:
291 case PIPE_FORMAT_L16A16_FLOAT:
292 case PIPE_FORMAT_L32A32_UINT:
293 case PIPE_FORMAT_L32A32_SINT:
294 case PIPE_FORMAT_L32A32_FLOAT:
295 case PIPE_FORMAT_R8A8_UNORM:
296 case PIPE_FORMAT_R8A8_SNORM:
297 case PIPE_FORMAT_R8A8_UINT:
298 case PIPE_FORMAT_R8A8_SINT:
299 case PIPE_FORMAT_R16A16_UNORM:
300 case PIPE_FORMAT_R16A16_SNORM:
301 case PIPE_FORMAT_R16A16_UINT:
302 case PIPE_FORMAT_R16A16_SINT:
303 case PIPE_FORMAT_R16A16_FLOAT:
304 case PIPE_FORMAT_R32A32_UINT:
305 case PIPE_FORMAT_R32A32_SINT:
306 case PIPE_FORMAT_R32A32_FLOAT:
307 return V_028C70_SWAP_ALT;
308 case PIPE_FORMAT_R8G8_UNORM:
309 case PIPE_FORMAT_R8G8_SNORM:
310 case PIPE_FORMAT_R8G8_UINT:
311 case PIPE_FORMAT_R8G8_SINT:
312 return V_028C70_SWAP_STD;
313
314 case PIPE_FORMAT_R16_UNORM:
315 case PIPE_FORMAT_R16_SNORM:
316 case PIPE_FORMAT_R16_UINT:
317 case PIPE_FORMAT_R16_SINT:
318 case PIPE_FORMAT_R16_FLOAT:
319 return V_028C70_SWAP_STD;
320
321 /* 32-bit buffers. */
322 case PIPE_FORMAT_A8B8G8R8_SRGB:
323 return V_028C70_SWAP_STD_REV;
324 case PIPE_FORMAT_B8G8R8A8_SRGB:
325 return V_028C70_SWAP_ALT;
326
327 case PIPE_FORMAT_B8G8R8A8_UNORM:
328 case PIPE_FORMAT_B8G8R8X8_UNORM:
329 return V_028C70_SWAP_ALT;
330
331 case PIPE_FORMAT_A8R8G8B8_UNORM:
332 case PIPE_FORMAT_X8R8G8B8_UNORM:
333 return V_028C70_SWAP_ALT_REV;
334 case PIPE_FORMAT_R8G8B8A8_SNORM:
335 case PIPE_FORMAT_R8G8B8A8_UNORM:
336 case PIPE_FORMAT_R8G8B8A8_SINT:
337 case PIPE_FORMAT_R8G8B8A8_UINT:
338 case PIPE_FORMAT_R8G8B8X8_UNORM:
339 case PIPE_FORMAT_R8G8B8X8_SNORM:
340 case PIPE_FORMAT_R8G8B8X8_SRGB:
341 case PIPE_FORMAT_R8G8B8X8_UINT:
342 case PIPE_FORMAT_R8G8B8X8_SINT:
343 return V_028C70_SWAP_STD;
344
345 case PIPE_FORMAT_A8B8G8R8_UNORM:
346 case PIPE_FORMAT_X8B8G8R8_UNORM:
347 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
348 return V_028C70_SWAP_STD_REV;
349
350 case PIPE_FORMAT_Z24X8_UNORM:
351 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
352 return V_028C70_SWAP_STD;
353
354 case PIPE_FORMAT_X8Z24_UNORM:
355 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
356 return V_028C70_SWAP_STD_REV;
357
358 case PIPE_FORMAT_R10G10B10A2_UNORM:
359 case PIPE_FORMAT_R10G10B10X2_SNORM:
360 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
361 return V_028C70_SWAP_STD;
362
363 case PIPE_FORMAT_B10G10R10A2_UNORM:
364 case PIPE_FORMAT_B10G10R10A2_UINT:
365 case PIPE_FORMAT_B10G10R10X2_UNORM:
366 return V_028C70_SWAP_ALT;
367
368 case PIPE_FORMAT_R11G11B10_FLOAT:
369 case PIPE_FORMAT_R32_FLOAT:
370 case PIPE_FORMAT_R32_UINT:
371 case PIPE_FORMAT_R32_SINT:
372 case PIPE_FORMAT_Z32_FLOAT:
373 case PIPE_FORMAT_R16G16_FLOAT:
374 case PIPE_FORMAT_R16G16_UNORM:
375 case PIPE_FORMAT_R16G16_SNORM:
376 case PIPE_FORMAT_R16G16_UINT:
377 case PIPE_FORMAT_R16G16_SINT:
378 return V_028C70_SWAP_STD;
379
380 /* 64-bit buffers. */
381 case PIPE_FORMAT_R32G32_FLOAT:
382 case PIPE_FORMAT_R32G32_UINT:
383 case PIPE_FORMAT_R32G32_SINT:
384 case PIPE_FORMAT_R16G16B16A16_UNORM:
385 case PIPE_FORMAT_R16G16B16A16_SNORM:
386 case PIPE_FORMAT_R16G16B16A16_UINT:
387 case PIPE_FORMAT_R16G16B16A16_SINT:
388 case PIPE_FORMAT_R16G16B16A16_FLOAT:
389 case PIPE_FORMAT_R16G16B16X16_UNORM:
390 case PIPE_FORMAT_R16G16B16X16_SNORM:
391 case PIPE_FORMAT_R16G16B16X16_FLOAT:
392 case PIPE_FORMAT_R16G16B16X16_UINT:
393 case PIPE_FORMAT_R16G16B16X16_SINT:
394 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
395
396 /* 128-bit buffers. */
397 case PIPE_FORMAT_R32G32B32A32_FLOAT:
398 case PIPE_FORMAT_R32G32B32A32_SNORM:
399 case PIPE_FORMAT_R32G32B32A32_UNORM:
400 case PIPE_FORMAT_R32G32B32A32_SINT:
401 case PIPE_FORMAT_R32G32B32A32_UINT:
402 case PIPE_FORMAT_R32G32B32X32_FLOAT:
403 case PIPE_FORMAT_R32G32B32X32_UINT:
404 case PIPE_FORMAT_R32G32B32X32_SINT:
405 return V_028C70_SWAP_STD;
406 default:
407 R600_ERR("unsupported colorswap format %d\n", format);
408 return ~0U;
409 }
410 return ~0U;
411 }
412
413 static uint32_t r600_translate_colorformat(enum pipe_format format)
414 {
415 switch (format) {
416 /* 8-bit buffers. */
417 case PIPE_FORMAT_A8_UNORM:
418 case PIPE_FORMAT_A8_SNORM:
419 case PIPE_FORMAT_A8_UINT:
420 case PIPE_FORMAT_A8_SINT:
421 case PIPE_FORMAT_I8_UNORM:
422 case PIPE_FORMAT_I8_SNORM:
423 case PIPE_FORMAT_I8_UINT:
424 case PIPE_FORMAT_I8_SINT:
425 case PIPE_FORMAT_L8_UNORM:
426 case PIPE_FORMAT_L8_SNORM:
427 case PIPE_FORMAT_L8_UINT:
428 case PIPE_FORMAT_L8_SINT:
429 case PIPE_FORMAT_L8_SRGB:
430 case PIPE_FORMAT_R8_UNORM:
431 case PIPE_FORMAT_R8_SNORM:
432 case PIPE_FORMAT_R8_UINT:
433 case PIPE_FORMAT_R8_SINT:
434 return V_028C70_COLOR_8;
435
436 /* 16-bit buffers. */
437 case PIPE_FORMAT_B5G6R5_UNORM:
438 return V_028C70_COLOR_5_6_5;
439
440 case PIPE_FORMAT_B5G5R5A1_UNORM:
441 case PIPE_FORMAT_B5G5R5X1_UNORM:
442 return V_028C70_COLOR_1_5_5_5;
443
444 case PIPE_FORMAT_B4G4R4A4_UNORM:
445 case PIPE_FORMAT_B4G4R4X4_UNORM:
446 return V_028C70_COLOR_4_4_4_4;
447
448 case PIPE_FORMAT_Z16_UNORM:
449 return V_028C70_COLOR_16;
450
451 case PIPE_FORMAT_L8A8_UNORM:
452 case PIPE_FORMAT_L8A8_SNORM:
453 case PIPE_FORMAT_L8A8_UINT:
454 case PIPE_FORMAT_L8A8_SINT:
455 case PIPE_FORMAT_L8A8_SRGB:
456 case PIPE_FORMAT_R8G8_UNORM:
457 case PIPE_FORMAT_R8G8_SNORM:
458 case PIPE_FORMAT_R8G8_UINT:
459 case PIPE_FORMAT_R8G8_SINT:
460 case PIPE_FORMAT_R8A8_UNORM:
461 case PIPE_FORMAT_R8A8_SNORM:
462 case PIPE_FORMAT_R8A8_UINT:
463 case PIPE_FORMAT_R8A8_SINT:
464 return V_028C70_COLOR_8_8;
465
466 case PIPE_FORMAT_R16_UNORM:
467 case PIPE_FORMAT_R16_SNORM:
468 case PIPE_FORMAT_R16_UINT:
469 case PIPE_FORMAT_R16_SINT:
470 case PIPE_FORMAT_A16_UNORM:
471 case PIPE_FORMAT_A16_SNORM:
472 case PIPE_FORMAT_A16_UINT:
473 case PIPE_FORMAT_A16_SINT:
474 case PIPE_FORMAT_L16_UNORM:
475 case PIPE_FORMAT_L16_SNORM:
476 case PIPE_FORMAT_L16_UINT:
477 case PIPE_FORMAT_L16_SINT:
478 case PIPE_FORMAT_I16_UNORM:
479 case PIPE_FORMAT_I16_SNORM:
480 case PIPE_FORMAT_I16_UINT:
481 case PIPE_FORMAT_I16_SINT:
482 return V_028C70_COLOR_16;
483
484 case PIPE_FORMAT_R16_FLOAT:
485 case PIPE_FORMAT_A16_FLOAT:
486 case PIPE_FORMAT_L16_FLOAT:
487 case PIPE_FORMAT_I16_FLOAT:
488 return V_028C70_COLOR_16_FLOAT;
489
490 /* 32-bit buffers. */
491 case PIPE_FORMAT_A8B8G8R8_SRGB:
492 case PIPE_FORMAT_A8B8G8R8_UNORM:
493 case PIPE_FORMAT_A8R8G8B8_UNORM:
494 case PIPE_FORMAT_B8G8R8A8_SRGB:
495 case PIPE_FORMAT_B8G8R8A8_UNORM:
496 case PIPE_FORMAT_B8G8R8X8_UNORM:
497 case PIPE_FORMAT_R8G8B8A8_SNORM:
498 case PIPE_FORMAT_R8G8B8A8_UNORM:
499 case PIPE_FORMAT_R8G8B8X8_UNORM:
500 case PIPE_FORMAT_R8G8B8X8_SNORM:
501 case PIPE_FORMAT_R8G8B8X8_SRGB:
502 case PIPE_FORMAT_R8G8B8X8_UINT:
503 case PIPE_FORMAT_R8G8B8X8_SINT:
504 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
505 case PIPE_FORMAT_X8B8G8R8_UNORM:
506 case PIPE_FORMAT_X8R8G8B8_UNORM:
507 case PIPE_FORMAT_R8G8B8_UNORM:
508 case PIPE_FORMAT_R8G8B8A8_SINT:
509 case PIPE_FORMAT_R8G8B8A8_UINT:
510 return V_028C70_COLOR_8_8_8_8;
511
512 case PIPE_FORMAT_R10G10B10A2_UNORM:
513 case PIPE_FORMAT_R10G10B10X2_SNORM:
514 case PIPE_FORMAT_B10G10R10A2_UNORM:
515 case PIPE_FORMAT_B10G10R10A2_UINT:
516 case PIPE_FORMAT_B10G10R10X2_UNORM:
517 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
518 return V_028C70_COLOR_2_10_10_10;
519
520 case PIPE_FORMAT_Z24X8_UNORM:
521 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
522 return V_028C70_COLOR_8_24;
523
524 case PIPE_FORMAT_X8Z24_UNORM:
525 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
526 return V_028C70_COLOR_24_8;
527
528 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
529 return V_028C70_COLOR_X24_8_32_FLOAT;
530
531 case PIPE_FORMAT_R32_UINT:
532 case PIPE_FORMAT_R32_SINT:
533 case PIPE_FORMAT_A32_UINT:
534 case PIPE_FORMAT_A32_SINT:
535 case PIPE_FORMAT_L32_UINT:
536 case PIPE_FORMAT_L32_SINT:
537 case PIPE_FORMAT_I32_UINT:
538 case PIPE_FORMAT_I32_SINT:
539 return V_028C70_COLOR_32;
540
541 case PIPE_FORMAT_R32_FLOAT:
542 case PIPE_FORMAT_A32_FLOAT:
543 case PIPE_FORMAT_L32_FLOAT:
544 case PIPE_FORMAT_I32_FLOAT:
545 case PIPE_FORMAT_Z32_FLOAT:
546 return V_028C70_COLOR_32_FLOAT;
547
548 case PIPE_FORMAT_R16G16_FLOAT:
549 case PIPE_FORMAT_L16A16_FLOAT:
550 case PIPE_FORMAT_R16A16_FLOAT:
551 return V_028C70_COLOR_16_16_FLOAT;
552
553 case PIPE_FORMAT_R16G16_UNORM:
554 case PIPE_FORMAT_R16G16_SNORM:
555 case PIPE_FORMAT_R16G16_UINT:
556 case PIPE_FORMAT_R16G16_SINT:
557 case PIPE_FORMAT_L16A16_UNORM:
558 case PIPE_FORMAT_L16A16_SNORM:
559 case PIPE_FORMAT_L16A16_UINT:
560 case PIPE_FORMAT_L16A16_SINT:
561 case PIPE_FORMAT_R16A16_UNORM:
562 case PIPE_FORMAT_R16A16_SNORM:
563 case PIPE_FORMAT_R16A16_UINT:
564 case PIPE_FORMAT_R16A16_SINT:
565 return V_028C70_COLOR_16_16;
566
567 case PIPE_FORMAT_R11G11B10_FLOAT:
568 return V_028C70_COLOR_10_11_11_FLOAT;
569
570 /* 64-bit buffers. */
571 case PIPE_FORMAT_R16G16B16A16_UINT:
572 case PIPE_FORMAT_R16G16B16A16_SINT:
573 case PIPE_FORMAT_R16G16B16A16_UNORM:
574 case PIPE_FORMAT_R16G16B16A16_SNORM:
575 case PIPE_FORMAT_R16G16B16X16_UNORM:
576 case PIPE_FORMAT_R16G16B16X16_SNORM:
577 case PIPE_FORMAT_R16G16B16X16_UINT:
578 case PIPE_FORMAT_R16G16B16X16_SINT:
579 return V_028C70_COLOR_16_16_16_16;
580
581 case PIPE_FORMAT_R16G16B16A16_FLOAT:
582 case PIPE_FORMAT_R16G16B16X16_FLOAT:
583 return V_028C70_COLOR_16_16_16_16_FLOAT;
584
585 case PIPE_FORMAT_R32G32_FLOAT:
586 case PIPE_FORMAT_L32A32_FLOAT:
587 case PIPE_FORMAT_R32A32_FLOAT:
588 return V_028C70_COLOR_32_32_FLOAT;
589
590 case PIPE_FORMAT_R32G32_SINT:
591 case PIPE_FORMAT_R32G32_UINT:
592 case PIPE_FORMAT_L32A32_UINT:
593 case PIPE_FORMAT_L32A32_SINT:
594 return V_028C70_COLOR_32_32;
595
596 /* 128-bit buffers. */
597 case PIPE_FORMAT_R32G32B32A32_SNORM:
598 case PIPE_FORMAT_R32G32B32A32_UNORM:
599 case PIPE_FORMAT_R32G32B32A32_SINT:
600 case PIPE_FORMAT_R32G32B32A32_UINT:
601 case PIPE_FORMAT_R32G32B32X32_UINT:
602 case PIPE_FORMAT_R32G32B32X32_SINT:
603 return V_028C70_COLOR_32_32_32_32;
604 case PIPE_FORMAT_R32G32B32A32_FLOAT:
605 case PIPE_FORMAT_R32G32B32X32_FLOAT:
606 return V_028C70_COLOR_32_32_32_32_FLOAT;
607
608 /* YUV buffers. */
609 case PIPE_FORMAT_UYVY:
610 case PIPE_FORMAT_YUYV:
611 default:
612 return ~0U; /* Unsupported. */
613 }
614 }
615
616 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
617 {
618 if (R600_BIG_ENDIAN) {
619 switch(colorformat) {
620
621 /* 8-bit buffers. */
622 case V_028C70_COLOR_8:
623 return ENDIAN_NONE;
624
625 /* 16-bit buffers. */
626 case V_028C70_COLOR_5_6_5:
627 case V_028C70_COLOR_1_5_5_5:
628 case V_028C70_COLOR_4_4_4_4:
629 case V_028C70_COLOR_16:
630 case V_028C70_COLOR_8_8:
631 return ENDIAN_8IN16;
632
633 /* 32-bit buffers. */
634 case V_028C70_COLOR_8_8_8_8:
635 case V_028C70_COLOR_2_10_10_10:
636 case V_028C70_COLOR_8_24:
637 case V_028C70_COLOR_24_8:
638 case V_028C70_COLOR_32_FLOAT:
639 case V_028C70_COLOR_16_16_FLOAT:
640 case V_028C70_COLOR_16_16:
641 return ENDIAN_8IN32;
642
643 /* 64-bit buffers. */
644 case V_028C70_COLOR_16_16_16_16:
645 case V_028C70_COLOR_16_16_16_16_FLOAT:
646 return ENDIAN_8IN16;
647
648 case V_028C70_COLOR_32_32_FLOAT:
649 case V_028C70_COLOR_32_32:
650 case V_028C70_COLOR_X24_8_32_FLOAT:
651 return ENDIAN_8IN32;
652
653 /* 96-bit buffers. */
654 case V_028C70_COLOR_32_32_32_FLOAT:
655 /* 128-bit buffers. */
656 case V_028C70_COLOR_32_32_32_32_FLOAT:
657 case V_028C70_COLOR_32_32_32_32:
658 return ENDIAN_8IN32;
659 default:
660 return ENDIAN_NONE; /* Unsupported. */
661 }
662 } else {
663 return ENDIAN_NONE;
664 }
665 }
666
667 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
668 {
669 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
670 }
671
672 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
673 {
674 return r600_translate_colorformat(format) != ~0U &&
675 r600_translate_colorswap(format) != ~0U;
676 }
677
678 static bool r600_is_zs_format_supported(enum pipe_format format)
679 {
680 return r600_translate_dbformat(format) != ~0U;
681 }
682
683 boolean evergreen_is_format_supported(struct pipe_screen *screen,
684 enum pipe_format format,
685 enum pipe_texture_target target,
686 unsigned sample_count,
687 unsigned usage)
688 {
689 struct r600_screen *rscreen = (struct r600_screen*)screen;
690 unsigned retval = 0;
691
692 if (target >= PIPE_MAX_TEXTURE_TYPES) {
693 R600_ERR("r600: unsupported texture type %d\n", target);
694 return FALSE;
695 }
696
697 if (!util_format_is_supported(format, usage))
698 return FALSE;
699
700 if (sample_count > 1) {
701 if (!rscreen->has_msaa)
702 return FALSE;
703
704 switch (sample_count) {
705 case 2:
706 case 4:
707 case 8:
708 break;
709 default:
710 return FALSE;
711 }
712 }
713
714 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
715 r600_is_sampler_format_supported(screen, format)) {
716 retval |= PIPE_BIND_SAMPLER_VIEW;
717 }
718
719 if ((usage & (PIPE_BIND_RENDER_TARGET |
720 PIPE_BIND_DISPLAY_TARGET |
721 PIPE_BIND_SCANOUT |
722 PIPE_BIND_SHARED)) &&
723 r600_is_colorbuffer_format_supported(format)) {
724 retval |= usage &
725 (PIPE_BIND_RENDER_TARGET |
726 PIPE_BIND_DISPLAY_TARGET |
727 PIPE_BIND_SCANOUT |
728 PIPE_BIND_SHARED);
729 }
730
731 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
732 r600_is_zs_format_supported(format)) {
733 retval |= PIPE_BIND_DEPTH_STENCIL;
734 }
735
736 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
737 r600_is_vertex_format_supported(format)) {
738 retval |= PIPE_BIND_VERTEX_BUFFER;
739 }
740
741 if (usage & PIPE_BIND_TRANSFER_READ)
742 retval |= PIPE_BIND_TRANSFER_READ;
743 if (usage & PIPE_BIND_TRANSFER_WRITE)
744 retval |= PIPE_BIND_TRANSFER_WRITE;
745
746 return retval == usage;
747 }
748
749 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
750 const struct pipe_blend_state *state, int mode)
751 {
752 uint32_t color_control = 0, target_mask = 0;
753 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
754
755 if (!blend) {
756 return NULL;
757 }
758
759 r600_init_command_buffer(&blend->buffer, 20);
760 r600_init_command_buffer(&blend->buffer_no_blend, 20);
761
762 if (state->logicop_enable) {
763 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
764 } else {
765 color_control |= (0xcc << 16);
766 }
767 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
768 if (state->independent_blend_enable) {
769 for (int i = 0; i < 8; i++) {
770 target_mask |= (state->rt[i].colormask << (4 * i));
771 }
772 } else {
773 for (int i = 0; i < 8; i++) {
774 target_mask |= (state->rt[0].colormask << (4 * i));
775 }
776 }
777
778 /* only have dual source on MRT0 */
779 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
780 blend->cb_target_mask = target_mask;
781 blend->alpha_to_one = state->alpha_to_one;
782
783 if (target_mask)
784 color_control |= S_028808_MODE(mode);
785 else
786 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
787
788
789 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
790 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
791 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
792 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
793 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
794 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
795 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
796 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
797
798 /* Copy over the dwords set so far into buffer_no_blend.
799 * Only the CB_BLENDi_CONTROL registers must be set after this. */
800 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
801 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
802
803 for (int i = 0; i < 8; i++) {
804 /* state->rt entries > 0 only written if independent blending */
805 const int j = state->independent_blend_enable ? i : 0;
806
807 unsigned eqRGB = state->rt[j].rgb_func;
808 unsigned srcRGB = state->rt[j].rgb_src_factor;
809 unsigned dstRGB = state->rt[j].rgb_dst_factor;
810 unsigned eqA = state->rt[j].alpha_func;
811 unsigned srcA = state->rt[j].alpha_src_factor;
812 unsigned dstA = state->rt[j].alpha_dst_factor;
813 uint32_t bc = 0;
814
815 r600_store_value(&blend->buffer_no_blend, 0);
816
817 if (!state->rt[j].blend_enable) {
818 r600_store_value(&blend->buffer, 0);
819 continue;
820 }
821
822 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
823 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
824 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
825 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
826
827 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
828 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
829 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
830 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
831 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
832 }
833 r600_store_value(&blend->buffer, bc);
834 }
835 return blend;
836 }
837
838 static void *evergreen_create_blend_state(struct pipe_context *ctx,
839 const struct pipe_blend_state *state)
840 {
841
842 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
843 }
844
845 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
846 const struct pipe_depth_stencil_alpha_state *state)
847 {
848 unsigned db_depth_control, alpha_test_control, alpha_ref;
849 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
850
851 if (dsa == NULL) {
852 return NULL;
853 }
854
855 r600_init_command_buffer(&dsa->buffer, 3);
856
857 dsa->valuemask[0] = state->stencil[0].valuemask;
858 dsa->valuemask[1] = state->stencil[1].valuemask;
859 dsa->writemask[0] = state->stencil[0].writemask;
860 dsa->writemask[1] = state->stencil[1].writemask;
861 dsa->zwritemask = state->depth.writemask;
862
863 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
864 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
865 S_028800_ZFUNC(state->depth.func);
866
867 /* stencil */
868 if (state->stencil[0].enabled) {
869 db_depth_control |= S_028800_STENCIL_ENABLE(1);
870 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
871 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
872 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
873 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
874
875 if (state->stencil[1].enabled) {
876 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
877 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
878 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
879 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
880 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
881 }
882 }
883
884 /* alpha */
885 alpha_test_control = 0;
886 alpha_ref = 0;
887 if (state->alpha.enabled) {
888 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
889 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
890 alpha_ref = fui(state->alpha.ref_value);
891 }
892 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
893 dsa->alpha_ref = alpha_ref;
894
895 /* misc */
896 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
897 return dsa;
898 }
899
900 static void *evergreen_create_rs_state(struct pipe_context *ctx,
901 const struct pipe_rasterizer_state *state)
902 {
903 struct r600_context *rctx = (struct r600_context *)ctx;
904 unsigned tmp, spi_interp;
905 float psize_min, psize_max;
906 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
907
908 if (rs == NULL) {
909 return NULL;
910 }
911
912 r600_init_command_buffer(&rs->buffer, 30);
913
914 rs->flatshade = state->flatshade;
915 rs->sprite_coord_enable = state->sprite_coord_enable;
916 rs->two_side = state->light_twoside;
917 rs->clip_plane_enable = state->clip_plane_enable;
918 rs->pa_sc_line_stipple = state->line_stipple_enable ?
919 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
920 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
921 rs->pa_cl_clip_cntl =
922 S_028810_PS_UCP_MODE(3) |
923 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
924 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
925 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
926 rs->multisample_enable = state->multisample;
927
928 /* offset */
929 rs->offset_units = state->offset_units;
930 rs->offset_scale = state->offset_scale * 12.0f;
931 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
932
933 if (state->point_size_per_vertex) {
934 psize_min = util_get_min_point_size(state);
935 psize_max = 8192;
936 } else {
937 /* Force the point size to be as if the vertex output was disabled. */
938 psize_min = state->point_size;
939 psize_max = state->point_size;
940 }
941
942 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
943 if (state->sprite_coord_enable) {
944 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
945 S_0286D4_PNT_SPRITE_OVRD_X(2) |
946 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
947 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
948 S_0286D4_PNT_SPRITE_OVRD_W(1);
949 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
950 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
951 }
952 }
953
954 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
955 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
956 tmp = r600_pack_float_12p4(state->point_size/2);
957 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
958 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
959 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
960 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
961 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
962 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
963 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
964
965 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
966 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
967 S_028A48_MSAA_ENABLE(state->multisample) |
968 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
969 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
970
971 if (rctx->chip_class == CAYMAN) {
972 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
973 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
974 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
975 } else {
976 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
977 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
978 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
979 }
980
981 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
982 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
983 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
984 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
985 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
986 S_028814_FACE(!state->front_ccw) |
987 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
988 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
989 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
990 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
991 state->fill_back != PIPE_POLYGON_MODE_FILL) |
992 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
993 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
994 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
995 return rs;
996 }
997
998 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
999 const struct pipe_sampler_state *state)
1000 {
1001 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
1002 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
1003
1004 if (ss == NULL) {
1005 return NULL;
1006 }
1007
1008 ss->border_color_use = sampler_state_needs_border_color(state);
1009
1010 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
1011 ss->tex_sampler_words[0] =
1012 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1013 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1014 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1015 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1016 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1017 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1018 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1019 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1020 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
1021 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
1022 ss->tex_sampler_words[1] =
1023 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
1024 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
1025 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
1026 ss->tex_sampler_words[2] =
1027 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
1028 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
1029 S_03C008_TYPE(1);
1030
1031 if (ss->border_color_use) {
1032 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
1033 }
1034 return ss;
1035 }
1036
1037 static struct pipe_sampler_view *
1038 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
1039 unsigned width0, unsigned height0)
1040
1041 {
1042 struct pipe_context *ctx = view->base.context;
1043 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
1044 uint64_t va;
1045 int stride = util_format_get_blocksize(view->base.format);
1046 unsigned format, num_format, format_comp, endian;
1047 unsigned swizzle_res;
1048 unsigned char swizzle[4];
1049 const struct util_format_description *desc;
1050
1051 swizzle[0] = view->base.swizzle_r;
1052 swizzle[1] = view->base.swizzle_g;
1053 swizzle[2] = view->base.swizzle_b;
1054 swizzle[3] = view->base.swizzle_a;
1055
1056 r600_vertex_data_type(view->base.format,
1057 &format, &num_format, &format_comp,
1058 &endian);
1059
1060 desc = util_format_description(view->base.format);
1061
1062 swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
1063
1064 va = r600_resource_va(ctx->screen, view->base.texture);
1065 view->tex_resource = &tmp->resource;
1066
1067 view->skip_mip_address_reloc = true;
1068 view->tex_resource_words[0] = va;
1069 view->tex_resource_words[1] = width0 - 1;
1070 view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
1071 S_030008_STRIDE(stride) |
1072 S_030008_DATA_FORMAT(format) |
1073 S_030008_NUM_FORMAT_ALL(num_format) |
1074 S_030008_FORMAT_COMP_ALL(format_comp) |
1075 S_030008_SRF_MODE_ALL(1) |
1076 S_030008_ENDIAN_SWAP(endian);
1077 view->tex_resource_words[3] = swizzle_res;
1078 /*
1079 * in theory dword 4 is for number of elements, for use with resinfo,
1080 * but it seems to utterly fail to work, the amd gpu shader analyser
1081 * uses a const buffer to store the element sizes for buffer txq
1082 */
1083 view->tex_resource_words[4] = 0;
1084 view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
1085 view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
1086 return &view->base;
1087 }
1088
1089 struct pipe_sampler_view *
1090 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
1091 struct pipe_resource *texture,
1092 const struct pipe_sampler_view *state,
1093 unsigned width0, unsigned height0)
1094 {
1095 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
1096 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1097 struct r600_texture *tmp = (struct r600_texture*)texture;
1098 unsigned format, endian;
1099 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1100 unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
1101 unsigned height, depth, width;
1102 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1103 enum pipe_format pipe_format = state->format;
1104 struct radeon_surface_level *surflevel;
1105
1106 if (view == NULL)
1107 return NULL;
1108
1109 /* initialize base object */
1110 view->base = *state;
1111 view->base.texture = NULL;
1112 pipe_reference(NULL, &texture->reference);
1113 view->base.texture = texture;
1114 view->base.reference.count = 1;
1115 view->base.context = ctx;
1116
1117 if (texture->target == PIPE_BUFFER)
1118 return texture_buffer_sampler_view(view, width0, height0);
1119
1120 swizzle[0] = state->swizzle_r;
1121 swizzle[1] = state->swizzle_g;
1122 swizzle[2] = state->swizzle_b;
1123 swizzle[3] = state->swizzle_a;
1124
1125 tile_split = tmp->surface.tile_split;
1126 surflevel = tmp->surface.level;
1127
1128 /* Texturing with separate depth and stencil. */
1129 if (tmp->is_depth && !tmp->is_flushing_texture) {
1130 switch (pipe_format) {
1131 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1132 pipe_format = PIPE_FORMAT_Z32_FLOAT;
1133 break;
1134 case PIPE_FORMAT_X8Z24_UNORM:
1135 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1136 /* Z24 is always stored like this. */
1137 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
1138 break;
1139 case PIPE_FORMAT_X24S8_UINT:
1140 case PIPE_FORMAT_S8X24_UINT:
1141 case PIPE_FORMAT_X32_S8X24_UINT:
1142 pipe_format = PIPE_FORMAT_S8_UINT;
1143 tile_split = tmp->surface.stencil_tile_split;
1144 surflevel = tmp->surface.stencil_level;
1145 break;
1146 default:;
1147 }
1148 }
1149
1150 format = r600_translate_texformat(ctx->screen, pipe_format,
1151 swizzle,
1152 &word4, &yuv_format);
1153 assert(format != ~0);
1154 if (format == ~0) {
1155 FREE(view);
1156 return NULL;
1157 }
1158
1159 endian = r600_colorformat_endian_swap(format);
1160
1161 width = width0;
1162 height = height0;
1163 depth = texture->depth0;
1164 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
1165 non_disp_tiling = tmp->non_disp_tiling;
1166
1167 switch (surflevel[0].mode) {
1168 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1169 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1170 break;
1171 case RADEON_SURF_MODE_2D:
1172 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1173 break;
1174 case RADEON_SURF_MODE_1D:
1175 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1176 break;
1177 case RADEON_SURF_MODE_LINEAR:
1178 default:
1179 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1180 break;
1181 }
1182 macro_aspect = tmp->surface.mtilea;
1183 bankw = tmp->surface.bankw;
1184 bankh = tmp->surface.bankh;
1185 tile_split = eg_tile_split(tile_split);
1186 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1187 bankw = eg_bank_wh(bankw);
1188 bankh = eg_bank_wh(bankh);
1189
1190 /* 128 bit formats require tile type = 1 */
1191 if (rscreen->chip_class == CAYMAN) {
1192 if (util_format_get_blocksize(pipe_format) >= 16)
1193 non_disp_tiling = 1;
1194 }
1195 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1196
1197 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1198 height = 1;
1199 depth = texture->array_size;
1200 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1201 depth = texture->array_size;
1202 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
1203 depth = texture->array_size / 6;
1204
1205 view->tex_resource = &tmp->resource;
1206 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1207 S_030000_PITCH((pitch / 8) - 1) |
1208 S_030000_TEX_WIDTH(width - 1));
1209 if (rscreen->chip_class == CAYMAN)
1210 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
1211 else
1212 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
1213 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1214 S_030004_TEX_DEPTH(depth - 1) |
1215 S_030004_ARRAY_MODE(array_mode));
1216 view->tex_resource_words[2] = (surflevel[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1217
1218 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
1219 if (texture->nr_samples > 1 && rscreen->msaa_texture_support == MSAA_TEXTURE_COMPRESSED) {
1220 /* XXX the 2x and 4x cases are broken. */
1221 if (tmp->is_depth || tmp->resource.b.b.nr_samples != 8) {
1222 /* disable FMASK (0 = disabled) */
1223 view->tex_resource_words[3] = 0;
1224 view->skip_mip_address_reloc = true;
1225 } else {
1226 /* FMASK should be in MIP_ADDRESS for multisample textures */
1227 view->tex_resource_words[3] = (tmp->fmask_offset + r600_resource_va(ctx->screen, texture)) >> 8;
1228 }
1229 } else if (state->u.tex.last_level && texture->nr_samples <= 1) {
1230 view->tex_resource_words[3] = (surflevel[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1231 } else {
1232 view->tex_resource_words[3] = (surflevel[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1233 }
1234
1235 view->tex_resource_words[4] = (word4 |
1236 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1237 S_030010_ENDIAN_SWAP(endian));
1238 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1239 S_030014_LAST_ARRAY(state->u.tex.last_layer);
1240 if (texture->nr_samples > 1) {
1241 unsigned log_samples = util_logbase2(texture->nr_samples);
1242 if (rscreen->chip_class == CAYMAN) {
1243 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
1244 }
1245 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1246 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
1247 } else {
1248 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(state->u.tex.first_level);
1249 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(state->u.tex.last_level);
1250 }
1251 /* aniso max 16 samples */
1252 view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
1253 (S_030018_TILE_SPLIT(tile_split));
1254 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1255 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1256 S_03001C_BANK_WIDTH(bankw) |
1257 S_03001C_BANK_HEIGHT(bankh) |
1258 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1259 S_03001C_NUM_BANKS(nbanks) |
1260 S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
1261 return &view->base;
1262 }
1263
1264 static struct pipe_sampler_view *
1265 evergreen_create_sampler_view(struct pipe_context *ctx,
1266 struct pipe_resource *tex,
1267 const struct pipe_sampler_view *state)
1268 {
1269 return evergreen_create_sampler_view_custom(ctx, tex, state,
1270 tex->width0, tex->height0);
1271 }
1272
1273 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1274 {
1275 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1276 struct pipe_clip_state *state = &rctx->clip_state.state;
1277
1278 r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
1279 r600_write_array(cs, 6*4, (unsigned*)state);
1280 }
1281
1282 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1283 const struct pipe_poly_stipple *state)
1284 {
1285 }
1286
1287 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1288 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1289 uint32_t *tl, uint32_t *br)
1290 {
1291 /* EG hw workaround */
1292 if (br_x == 0)
1293 tl_x = 1;
1294 if (br_y == 0)
1295 tl_y = 1;
1296
1297 /* cayman hw workaround */
1298 if (rctx->chip_class == CAYMAN) {
1299 if (br_x == 1 && br_y == 1)
1300 br_x = 2;
1301 }
1302
1303 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1304 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1305 }
1306
1307 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1308 const struct pipe_scissor_state *state)
1309 {
1310 struct r600_context *rctx = (struct r600_context *)ctx;
1311
1312 rctx->scissor.scissor = *state;
1313 rctx->scissor.atom.dirty = true;
1314 }
1315
1316 static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
1317 {
1318 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1319 struct pipe_scissor_state *state = &rctx->scissor.scissor;
1320 uint32_t tl, br;
1321
1322 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1323
1324 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1325 r600_write_value(cs, tl);
1326 r600_write_value(cs, br);
1327 }
1328
1329 /**
1330 * This function intializes the CB* register values for RATs. It is meant
1331 * to be used for 1D aligned buffers that do not have an associated
1332 * radeon_surface.
1333 */
1334 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1335 struct r600_surface *surf)
1336 {
1337 struct pipe_resource *pipe_buffer = surf->base.texture;
1338 unsigned format = r600_translate_colorformat(surf->base.format);
1339 unsigned endian = r600_colorformat_endian_swap(format);
1340 unsigned swap = r600_translate_colorswap(surf->base.format);
1341 unsigned block_size =
1342 align(util_format_get_blocksize(pipe_buffer->format), 4);
1343 unsigned pitch_alignment =
1344 MAX2(64, rctx->screen->tiling_info.group_bytes / block_size);
1345 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
1346
1347 /* XXX: This is copied from evergreen_init_color_surface(). I don't
1348 * know why this is necessary.
1349 */
1350 if (pipe_buffer->usage == PIPE_USAGE_STAGING) {
1351 endian = ENDIAN_NONE;
1352 }
1353
1354 surf->cb_color_base =
1355 r600_resource_va(rctx->context.screen, pipe_buffer) >> 8;
1356
1357 surf->cb_color_pitch = (pitch / 8) - 1;
1358
1359 surf->cb_color_slice = 0;
1360
1361 surf->cb_color_view = 0;
1362
1363 surf->cb_color_info =
1364 S_028C70_ENDIAN(endian)
1365 | S_028C70_FORMAT(format)
1366 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
1367 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
1368 | S_028C70_COMP_SWAP(swap)
1369 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
1370 * are using NUMBER_UINT */
1371 | S_028C70_RAT(1)
1372 ;
1373
1374 surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1375
1376 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
1377 * elements. */
1378 surf->cb_color_dim = pipe_buffer->width0;
1379
1380 surf->cb_color_cmask = surf->cb_color_base;
1381 surf->cb_color_cmask_slice = 0;
1382 surf->cb_color_fmask = surf->cb_color_base;
1383 surf->cb_color_fmask_slice = 0;
1384 }
1385
1386 void evergreen_init_color_surface(struct r600_context *rctx,
1387 struct r600_surface *surf)
1388 {
1389 struct r600_screen *rscreen = rctx->screen;
1390 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1391 struct pipe_resource *pipe_tex = surf->base.texture;
1392 unsigned level = surf->base.u.tex.level;
1393 unsigned pitch, slice;
1394 unsigned color_info, color_attrib, color_dim = 0;
1395 unsigned format, swap, ntype, endian;
1396 uint64_t offset, base_offset;
1397 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1398 const struct util_format_description *desc;
1399 int i;
1400 bool blend_clamp = 0, blend_bypass = 0;
1401
1402 offset = rtex->surface.level[level].offset;
1403 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1404 offset += rtex->surface.level[level].slice_size *
1405 surf->base.u.tex.first_layer;
1406 }
1407 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1408 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1409 if (slice) {
1410 slice = slice - 1;
1411 }
1412 color_info = 0;
1413 switch (rtex->surface.level[level].mode) {
1414 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1415 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1416 non_disp_tiling = 1;
1417 break;
1418 case RADEON_SURF_MODE_1D:
1419 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1420 non_disp_tiling = rtex->non_disp_tiling;
1421 break;
1422 case RADEON_SURF_MODE_2D:
1423 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1424 non_disp_tiling = rtex->non_disp_tiling;
1425 break;
1426 case RADEON_SURF_MODE_LINEAR:
1427 default:
1428 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1429 non_disp_tiling = 1;
1430 break;
1431 }
1432 tile_split = rtex->surface.tile_split;
1433 macro_aspect = rtex->surface.mtilea;
1434 bankw = rtex->surface.bankw;
1435 bankh = rtex->surface.bankh;
1436 fmask_bankh = rtex->fmask_bank_height;
1437 tile_split = eg_tile_split(tile_split);
1438 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1439 bankw = eg_bank_wh(bankw);
1440 bankh = eg_bank_wh(bankh);
1441 fmask_bankh = eg_bank_wh(fmask_bankh);
1442
1443 /* 128 bit formats require tile type = 1 */
1444 if (rscreen->chip_class == CAYMAN) {
1445 if (util_format_get_blocksize(surf->base.format) >= 16)
1446 non_disp_tiling = 1;
1447 }
1448 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1449 desc = util_format_description(surf->base.format);
1450 for (i = 0; i < 4; i++) {
1451 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1452 break;
1453 }
1454 }
1455
1456 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1457 S_028C74_NUM_BANKS(nbanks) |
1458 S_028C74_BANK_WIDTH(bankw) |
1459 S_028C74_BANK_HEIGHT(bankh) |
1460 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1461 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1462 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1463
1464 if (rctx->chip_class == CAYMAN) {
1465 color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1466 UTIL_FORMAT_SWIZZLE_1);
1467
1468 if (rtex->resource.b.b.nr_samples > 1) {
1469 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1470 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1471 S_028C74_NUM_FRAGMENTS(log_samples);
1472 }
1473 }
1474
1475 ntype = V_028C70_NUMBER_UNORM;
1476 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1477 ntype = V_028C70_NUMBER_SRGB;
1478 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1479 if (desc->channel[i].normalized)
1480 ntype = V_028C70_NUMBER_SNORM;
1481 else if (desc->channel[i].pure_integer)
1482 ntype = V_028C70_NUMBER_SINT;
1483 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1484 if (desc->channel[i].normalized)
1485 ntype = V_028C70_NUMBER_UNORM;
1486 else if (desc->channel[i].pure_integer)
1487 ntype = V_028C70_NUMBER_UINT;
1488 }
1489
1490 format = r600_translate_colorformat(surf->base.format);
1491 assert(format != ~0);
1492
1493 swap = r600_translate_colorswap(surf->base.format);
1494 assert(swap != ~0);
1495
1496 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1497 endian = ENDIAN_NONE;
1498 } else {
1499 endian = r600_colorformat_endian_swap(format);
1500 }
1501
1502 /* blend clamp should be set for all NORM/SRGB types */
1503 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1504 ntype == V_028C70_NUMBER_SRGB)
1505 blend_clamp = 1;
1506
1507 /* set blend bypass according to docs if SINT/UINT or
1508 8/24 COLOR variants */
1509 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1510 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1511 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1512 blend_clamp = 0;
1513 blend_bypass = 1;
1514 }
1515
1516 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1517
1518 color_info |= S_028C70_FORMAT(format) |
1519 S_028C70_COMP_SWAP(swap) |
1520 S_028C70_BLEND_CLAMP(blend_clamp) |
1521 S_028C70_BLEND_BYPASS(blend_bypass) |
1522 S_028C70_NUMBER_TYPE(ntype) |
1523 S_028C70_ENDIAN(endian);
1524
1525 if (rtex->is_rat) {
1526 color_info |= S_028C70_RAT(1);
1527 color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0 & 0xffff)
1528 | S_028C78_HEIGHT_MAX((pipe_tex->width0 >> 16) & 0xffff);
1529 }
1530
1531 /* EXPORT_NORM is an optimzation that can be enabled for better
1532 * performance in certain cases.
1533 * EXPORT_NORM can be enabled if:
1534 * - 11-bit or smaller UNORM/SNORM/SRGB
1535 * - 16-bit or smaller FLOAT
1536 */
1537 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1538 ((desc->channel[i].size < 12 &&
1539 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1540 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1541 (desc->channel[i].size < 17 &&
1542 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1543 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1544 surf->export_16bpc = true;
1545 }
1546
1547 if (rtex->fmask_size && rtex->cmask_size) {
1548 color_info |= S_028C70_COMPRESSION(1) | S_028C70_FAST_CLEAR(1);
1549 }
1550
1551 base_offset = r600_resource_va(rctx->context.screen, pipe_tex);
1552
1553 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1554 surf->cb_color_base = (base_offset + offset) >> 8;
1555 surf->cb_color_dim = color_dim;
1556 surf->cb_color_info = color_info;
1557 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1558 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1559 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1560 surf->cb_color_view = 0;
1561 } else {
1562 surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1563 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1564 }
1565 surf->cb_color_attrib = color_attrib;
1566 if (rtex->fmask_size && rtex->cmask_size) {
1567 surf->cb_color_fmask = (base_offset + rtex->fmask_offset) >> 8;
1568 surf->cb_color_cmask = (base_offset + rtex->cmask_offset) >> 8;
1569 } else {
1570 surf->cb_color_fmask = surf->cb_color_base;
1571 surf->cb_color_cmask = surf->cb_color_base;
1572 }
1573 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1574 surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask_slice_tile_max);
1575
1576 surf->color_initialized = true;
1577 }
1578
1579 static void evergreen_init_depth_surface(struct r600_context *rctx,
1580 struct r600_surface *surf)
1581 {
1582 struct r600_screen *rscreen = rctx->screen;
1583 struct pipe_screen *screen = &rscreen->screen;
1584 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1585 uint64_t offset;
1586 unsigned level, pitch, slice, format, array_mode;
1587 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1588
1589 level = surf->base.u.tex.level;
1590 format = r600_translate_dbformat(surf->base.format);
1591 assert(format != ~0);
1592
1593 offset = r600_resource_va(screen, surf->base.texture);
1594 offset += rtex->surface.level[level].offset;
1595 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1596 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1597 if (slice) {
1598 slice = slice - 1;
1599 }
1600 switch (rtex->surface.level[level].mode) {
1601 case RADEON_SURF_MODE_2D:
1602 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1603 break;
1604 case RADEON_SURF_MODE_1D:
1605 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1606 case RADEON_SURF_MODE_LINEAR:
1607 default:
1608 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1609 break;
1610 }
1611 tile_split = rtex->surface.tile_split;
1612 macro_aspect = rtex->surface.mtilea;
1613 bankw = rtex->surface.bankw;
1614 bankh = rtex->surface.bankh;
1615 tile_split = eg_tile_split(tile_split);
1616 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1617 bankw = eg_bank_wh(bankw);
1618 bankh = eg_bank_wh(bankh);
1619 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1620 offset >>= 8;
1621
1622 surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1623 S_028040_FORMAT(format) |
1624 S_028040_TILE_SPLIT(tile_split)|
1625 S_028040_NUM_BANKS(nbanks) |
1626 S_028040_BANK_WIDTH(bankw) |
1627 S_028040_BANK_HEIGHT(bankh) |
1628 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1629 if (rscreen->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1630 surf->db_depth_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1631 }
1632 surf->db_depth_base = offset;
1633 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1634 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1635 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1636 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1637
1638 switch (surf->base.format) {
1639 case PIPE_FORMAT_Z24X8_UNORM:
1640 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1641 case PIPE_FORMAT_X8Z24_UNORM:
1642 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1643 surf->pa_su_poly_offset_db_fmt_cntl =
1644 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1645 break;
1646 case PIPE_FORMAT_Z32_FLOAT:
1647 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1648 surf->pa_su_poly_offset_db_fmt_cntl =
1649 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1650 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1651 break;
1652 case PIPE_FORMAT_Z16_UNORM:
1653 surf->pa_su_poly_offset_db_fmt_cntl =
1654 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1655 break;
1656 default:;
1657 }
1658
1659 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1660 uint64_t stencil_offset;
1661 unsigned stile_split = rtex->surface.stencil_tile_split;
1662
1663 stile_split = eg_tile_split(stile_split);
1664
1665 stencil_offset = rtex->surface.stencil_level[level].offset;
1666 stencil_offset += r600_resource_va(screen, surf->base.texture);
1667
1668 surf->db_stencil_base = stencil_offset >> 8;
1669 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1670 S_028044_TILE_SPLIT(stile_split);
1671 } else {
1672 surf->db_stencil_base = offset;
1673 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1674 * Older kernels are out of luck. */
1675 surf->db_stencil_info = rctx->screen->info.drm_minor >= 18 ?
1676 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1677 S_028044_FORMAT(V_028044_STENCIL_8);
1678 }
1679
1680 surf->htile_enabled = 0;
1681 /* use htile only for first level */
1682 if (rtex->htile && !level) {
1683 uint64_t va = r600_resource_va(&rctx->screen->screen, &rtex->htile->b.b);
1684 surf->htile_enabled = 1;
1685 surf->db_htile_data_base = va >> 8;
1686 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1687 S_028ABC_HTILE_HEIGHT(1) |
1688 S_028ABC_LINEAR(1);
1689 surf->db_depth_info |= S_028040_TILE_SURFACE_ENABLE(1);
1690 surf->db_preload_control = 0;
1691 }
1692
1693 surf->depth_initialized = true;
1694 }
1695
1696 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1697 const struct pipe_framebuffer_state *state)
1698 {
1699 struct r600_context *rctx = (struct r600_context *)ctx;
1700 struct r600_surface *surf;
1701 struct r600_texture *rtex;
1702 uint32_t i, log_samples;
1703
1704 if (rctx->framebuffer.state.nr_cbufs) {
1705 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1706
1707 if (rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1708 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1709 }
1710 }
1711 if (rctx->framebuffer.state.zsbuf) {
1712 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1713
1714 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1715 if (rtex->htile) {
1716 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1717 }
1718 }
1719
1720 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1721
1722 /* Colorbuffers. */
1723 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1724 rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1725 util_format_is_pure_integer(state->cbufs[0]->format);
1726 rctx->framebuffer.compressed_cb_mask = 0;
1727
1728 if (state->nr_cbufs)
1729 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1730 else if (state->zsbuf)
1731 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1732 else
1733 rctx->framebuffer.nr_samples = 0;
1734
1735 for (i = 0; i < state->nr_cbufs; i++) {
1736 surf = (struct r600_surface*)state->cbufs[i];
1737 rtex = (struct r600_texture*)surf->base.texture;
1738
1739 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1740
1741 if (!surf->color_initialized) {
1742 evergreen_init_color_surface(rctx, surf);
1743 }
1744
1745 if (!surf->export_16bpc) {
1746 rctx->framebuffer.export_16bpc = false;
1747 }
1748
1749 if (rtex->fmask_size && rtex->cmask_size) {
1750 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1751 }
1752 }
1753
1754 /* Update alpha-test state dependencies.
1755 * Alpha-test is done on the first colorbuffer only. */
1756 if (state->nr_cbufs) {
1757 surf = (struct r600_surface*)state->cbufs[0];
1758 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1759 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1760 rctx->alphatest_state.atom.dirty = true;
1761 }
1762 if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
1763 rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
1764 rctx->alphatest_state.atom.dirty = true;
1765 }
1766 }
1767
1768 /* ZS buffer. */
1769 if (state->zsbuf) {
1770 surf = (struct r600_surface*)state->zsbuf;
1771
1772 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1773
1774 if (!surf->depth_initialized) {
1775 evergreen_init_depth_surface(rctx, surf);
1776 }
1777
1778 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1779 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1780 rctx->poly_offset_state.atom.dirty = true;
1781 }
1782
1783 if (rctx->db_state.rsurf != surf) {
1784 rctx->db_state.rsurf = surf;
1785 rctx->db_state.atom.dirty = true;
1786 rctx->db_misc_state.atom.dirty = true;
1787 }
1788 } else if (rctx->db_state.rsurf) {
1789 rctx->db_state.rsurf = NULL;
1790 rctx->db_state.atom.dirty = true;
1791 rctx->db_misc_state.atom.dirty = true;
1792 }
1793
1794 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1795 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1796 rctx->cb_misc_state.atom.dirty = true;
1797 }
1798
1799 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1800 rctx->alphatest_state.bypass = false;
1801 rctx->alphatest_state.atom.dirty = true;
1802 }
1803
1804 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1805 if (rctx->chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) {
1806 rctx->db_misc_state.log_samples = log_samples;
1807 rctx->db_misc_state.atom.dirty = true;
1808 }
1809
1810 evergreen_update_db_shader_control(rctx);
1811
1812 /* Calculate the CS size. */
1813 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1814
1815 /* MSAA. */
1816 if (rctx->chip_class == EVERGREEN) {
1817 switch (rctx->framebuffer.nr_samples) {
1818 case 2:
1819 case 4:
1820 rctx->framebuffer.atom.num_dw += 6;
1821 break;
1822 case 8:
1823 rctx->framebuffer.atom.num_dw += 10;
1824 break;
1825 }
1826 rctx->framebuffer.atom.num_dw += 4;
1827 } else {
1828 switch (rctx->framebuffer.nr_samples) {
1829 case 2:
1830 case 4:
1831 rctx->framebuffer.atom.num_dw += 12;
1832 break;
1833 case 8:
1834 rctx->framebuffer.atom.num_dw += 16;
1835 break;
1836 case 16:
1837 rctx->framebuffer.atom.num_dw += 18;
1838 break;
1839 }
1840 rctx->framebuffer.atom.num_dw += 7;
1841 }
1842
1843 /* Colorbuffers. */
1844 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 21;
1845 if (rctx->keep_tiling_flags)
1846 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1847 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1848
1849 /* ZS buffer. */
1850 if (state->zsbuf) {
1851 rctx->framebuffer.atom.num_dw += 24;
1852 if (rctx->keep_tiling_flags)
1853 rctx->framebuffer.atom.num_dw += 2;
1854 } else if (rctx->screen->info.drm_minor >= 18) {
1855 rctx->framebuffer.atom.num_dw += 4;
1856 }
1857
1858 rctx->framebuffer.atom.dirty = true;
1859 }
1860
1861 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1862 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1863 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1864 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1865 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1866
1867 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1868 {
1869 /* 2xMSAA
1870 * There are two locations (-4, 4), (4, -4). */
1871 static uint32_t sample_locs_2x[] = {
1872 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1873 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1874 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1875 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1876 };
1877 static unsigned max_dist_2x = 4;
1878 /* 4xMSAA
1879 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1880 static uint32_t sample_locs_4x[] = {
1881 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1882 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1883 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1884 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1885 };
1886 static unsigned max_dist_4x = 6;
1887 /* 8xMSAA */
1888 static uint32_t sample_locs_8x[] = {
1889 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1890 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1891 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1892 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1893 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1894 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1895 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1896 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1897 };
1898 static unsigned max_dist_8x = 7;
1899
1900 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1901 unsigned max_dist = 0;
1902
1903 switch (nr_samples) {
1904 default:
1905 nr_samples = 0;
1906 break;
1907 case 2:
1908 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_2x));
1909 r600_write_array(cs, Elements(sample_locs_2x), sample_locs_2x);
1910 max_dist = max_dist_2x;
1911 break;
1912 case 4:
1913 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_4x));
1914 r600_write_array(cs, Elements(sample_locs_4x), sample_locs_4x);
1915 max_dist = max_dist_4x;
1916 break;
1917 case 8:
1918 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1919 r600_write_array(cs, Elements(sample_locs_8x), sample_locs_8x);
1920 max_dist = max_dist_8x;
1921 break;
1922 }
1923
1924 if (nr_samples > 1) {
1925 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1926 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1927 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1928 r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1929 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1930 } else {
1931 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1932 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1933 r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1934 }
1935 }
1936
1937 static void cayman_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1938 {
1939 /* 2xMSAA
1940 * There are two locations (-4, 4), (4, -4). */
1941 static uint32_t sample_locs_2x[] = {
1942 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1943 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1944 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1945 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1946 };
1947 static unsigned max_dist_2x = 4;
1948 /* 4xMSAA
1949 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1950 static uint32_t sample_locs_4x[] = {
1951 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1952 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1953 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1954 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1955 };
1956 static unsigned max_dist_4x = 6;
1957 /* 8xMSAA */
1958 static uint32_t sample_locs_8x[] = {
1959 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1960 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1961 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1962 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1963 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1964 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1965 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1966 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1967 };
1968 static unsigned max_dist_8x = 8;
1969 /* 16xMSAA */
1970 static uint32_t sample_locs_16x[] = {
1971 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1972 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1973 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1974 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1975 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1976 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1977 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1978 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1979 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1980 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1981 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1982 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1983 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1984 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1985 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1986 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1987 };
1988 static unsigned max_dist_16x = 8;
1989
1990 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1991 unsigned max_dist = 0;
1992
1993 switch (nr_samples) {
1994 default:
1995 nr_samples = 0;
1996 break;
1997 case 2:
1998 r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
1999 r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
2000 r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
2001 r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
2002 max_dist = max_dist_2x;
2003 break;
2004 case 4:
2005 r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
2006 r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
2007 r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
2008 r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
2009 max_dist = max_dist_4x;
2010 break;
2011 case 8:
2012 r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
2013 r600_write_value(cs, sample_locs_8x[0]);
2014 r600_write_value(cs, sample_locs_8x[4]);
2015 r600_write_value(cs, 0);
2016 r600_write_value(cs, 0);
2017 r600_write_value(cs, sample_locs_8x[1]);
2018 r600_write_value(cs, sample_locs_8x[5]);
2019 r600_write_value(cs, 0);
2020 r600_write_value(cs, 0);
2021 r600_write_value(cs, sample_locs_8x[2]);
2022 r600_write_value(cs, sample_locs_8x[6]);
2023 r600_write_value(cs, 0);
2024 r600_write_value(cs, 0);
2025 r600_write_value(cs, sample_locs_8x[3]);
2026 r600_write_value(cs, sample_locs_8x[7]);
2027 max_dist = max_dist_8x;
2028 break;
2029 case 16:
2030 r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
2031 r600_write_value(cs, sample_locs_16x[0]);
2032 r600_write_value(cs, sample_locs_16x[4]);
2033 r600_write_value(cs, sample_locs_16x[8]);
2034 r600_write_value(cs, sample_locs_16x[12]);
2035 r600_write_value(cs, sample_locs_16x[1]);
2036 r600_write_value(cs, sample_locs_16x[5]);
2037 r600_write_value(cs, sample_locs_16x[9]);
2038 r600_write_value(cs, sample_locs_16x[13]);
2039 r600_write_value(cs, sample_locs_16x[2]);
2040 r600_write_value(cs, sample_locs_16x[6]);
2041 r600_write_value(cs, sample_locs_16x[10]);
2042 r600_write_value(cs, sample_locs_16x[14]);
2043 r600_write_value(cs, sample_locs_16x[3]);
2044 r600_write_value(cs, sample_locs_16x[7]);
2045 r600_write_value(cs, sample_locs_16x[11]);
2046 r600_write_value(cs, sample_locs_16x[15]);
2047 max_dist = max_dist_16x;
2048 break;
2049 }
2050
2051 if (nr_samples > 1) {
2052 unsigned log_samples = util_logbase2(nr_samples);
2053
2054 r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
2055 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
2056 S_028C00_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2057 r600_write_value(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
2058 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
2059 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2060
2061 r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
2062 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2063 S_028804_PS_ITER_SAMPLES(log_samples) |
2064 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2065 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2066 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2067 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2068 } else {
2069 r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
2070 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2071 r600_write_value(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2072
2073 r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
2074 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2075 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2076 }
2077 }
2078
2079 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
2080 {
2081 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2082 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
2083 unsigned nr_cbufs = state->nr_cbufs;
2084 unsigned i, tl, br;
2085
2086 /* XXX support more colorbuffers once we need them */
2087 assert(nr_cbufs <= 8);
2088 if (nr_cbufs > 8)
2089 nr_cbufs = 8;
2090
2091 /* Colorbuffers. */
2092 for (i = 0; i < nr_cbufs; i++) {
2093 struct r600_surface *cb = (struct r600_surface*)state->cbufs[i];
2094 unsigned reloc = r600_context_bo_reloc(rctx,
2095 &rctx->rings.gfx,
2096 (struct r600_resource*)cb->base.texture,
2097 RADEON_USAGE_READWRITE);
2098
2099 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 11);
2100 r600_write_value(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2101 r600_write_value(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2102 r600_write_value(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2103 r600_write_value(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2104 r600_write_value(cs, cb->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2105 r600_write_value(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2106 r600_write_value(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
2107 r600_write_value(cs, cb->cb_color_cmask); /* R_028C7C_CB_COLOR0_CMASK */
2108 r600_write_value(cs, cb->cb_color_cmask_slice); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2109 r600_write_value(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2110 r600_write_value(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2111
2112 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
2113 r600_write_value(cs, reloc);
2114
2115 if (!rctx->keep_tiling_flags) {
2116 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
2117 r600_write_value(cs, reloc);
2118 }
2119
2120 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
2121 r600_write_value(cs, reloc);
2122
2123 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
2124 r600_write_value(cs, reloc);
2125
2126 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
2127 r600_write_value(cs, reloc);
2128 }
2129 /* set CB_COLOR1_INFO for possible dual-src blending */
2130 if (i == 1 && !((struct r600_texture*)state->cbufs[0]->texture)->is_rat) {
2131 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2132 ((struct r600_surface*)state->cbufs[0])->cb_color_info);
2133
2134 if (!rctx->keep_tiling_flags) {
2135 unsigned reloc = r600_context_bo_reloc(rctx,
2136 &rctx->rings.gfx,
2137 (struct r600_resource*)state->cbufs[0]->texture,
2138 RADEON_USAGE_READWRITE);
2139
2140 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
2141 r600_write_value(cs, reloc);
2142 }
2143 i++;
2144 }
2145 if (rctx->keep_tiling_flags) {
2146 for (; i < 8 ; i++) {
2147 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2148 }
2149 for (; i < 12; i++) {
2150 r600_write_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
2151 }
2152 }
2153
2154 /* ZS buffer. */
2155 if (state->zsbuf) {
2156 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2157 unsigned reloc = r600_context_bo_reloc(rctx,
2158 &rctx->rings.gfx,
2159 (struct r600_resource*)state->zsbuf->texture,
2160 RADEON_USAGE_READWRITE);
2161
2162 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2163 zb->pa_su_poly_offset_db_fmt_cntl);
2164 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2165
2166 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
2167 r600_write_value(cs, zb->db_depth_info); /* R_028040_DB_Z_INFO */
2168 r600_write_value(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2169 r600_write_value(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2170 r600_write_value(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2171 r600_write_value(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2172 r600_write_value(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2173 r600_write_value(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2174 r600_write_value(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2175
2176 if (!rctx->keep_tiling_flags) {
2177 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
2178 r600_write_value(cs, reloc);
2179 }
2180
2181 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
2182 r600_write_value(cs, reloc);
2183
2184 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
2185 r600_write_value(cs, reloc);
2186
2187 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
2188 r600_write_value(cs, reloc);
2189
2190 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
2191 r600_write_value(cs, reloc);
2192 } else if (rctx->screen->info.drm_minor >= 18) {
2193 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
2194 * Older kernels are out of luck. */
2195 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2196 r600_write_value(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2197 r600_write_value(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2198 }
2199
2200 /* Framebuffer dimensions. */
2201 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
2202
2203 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
2204 r600_write_value(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
2205 r600_write_value(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
2206
2207 if (rctx->chip_class == EVERGREEN) {
2208 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
2209 } else {
2210 cayman_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
2211 }
2212 }
2213
2214 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
2215 {
2216 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2217 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
2218 float offset_units = state->offset_units;
2219 float offset_scale = state->offset_scale;
2220
2221 switch (state->zs_format) {
2222 case PIPE_FORMAT_Z24X8_UNORM:
2223 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2224 case PIPE_FORMAT_X8Z24_UNORM:
2225 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2226 offset_units *= 2.0f;
2227 break;
2228 case PIPE_FORMAT_Z16_UNORM:
2229 offset_units *= 4.0f;
2230 break;
2231 default:;
2232 }
2233
2234 r600_write_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
2235 r600_write_value(cs, fui(offset_scale));
2236 r600_write_value(cs, fui(offset_units));
2237 r600_write_value(cs, fui(offset_scale));
2238 r600_write_value(cs, fui(offset_units));
2239 }
2240
2241 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2242 {
2243 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2244 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
2245 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
2246 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
2247
2248 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
2249 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
2250 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
2251 * will assure that the alpha-test will work even if there is
2252 * no colorbuffer bound. */
2253 r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
2254 }
2255
2256 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
2257 {
2258 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2259 struct r600_db_state *a = (struct r600_db_state*)atom;
2260
2261 if (a->rsurf && a->rsurf->htile_enabled) {
2262 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
2263 unsigned reloc_idx;
2264
2265 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear));
2266 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
2267 r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
2268 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
2269 reloc_idx = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rtex->htile, RADEON_USAGE_READWRITE);
2270 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
2271 cs->buf[cs->cdw++] = reloc_idx;
2272 } else {
2273 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
2274 r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
2275 }
2276 }
2277
2278 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2279 {
2280 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2281 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2282 unsigned db_render_control = 0;
2283 unsigned db_count_control = 0;
2284 unsigned db_render_override =
2285 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2286 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2287
2288 if (a->occlusion_query_enabled) {
2289 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
2290 if (rctx->chip_class == CAYMAN) {
2291 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
2292 }
2293 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
2294 }
2295 /* FIXME we should be able to use hyperz even if we are not writing to
2296 * zbuffer but somehow this trigger GPU lockup. See :
2297 *
2298 * https://bugs.freedesktop.org/show_bug.cgi?id=60848
2299 *
2300 * Disable hyperz for now if not writing to zbuffer.
2301 */
2302 if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled && rctx->zwritemask) {
2303 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
2304 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
2305 /* This is to fix a lockup when hyperz and alpha test are enabled at
2306 * the same time somehow GPU get confuse on which order to pick for
2307 * z test
2308 */
2309 if (rctx->alphatest_state.sx_alpha_test_control) {
2310 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
2311 }
2312 } else {
2313 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
2314 }
2315 if (a->flush_depthstencil_through_cb) {
2316 assert(a->copy_depth || a->copy_stencil);
2317
2318 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
2319 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
2320 S_028000_COPY_CENTROID(1) |
2321 S_028000_COPY_SAMPLE(a->copy_sample);
2322 } else if (a->flush_depthstencil_in_place) {
2323 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(1) |
2324 S_028000_STENCIL_COMPRESS_DISABLE(1);
2325 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2326 }
2327 if (a->htile_clear) {
2328 /* FIXME we might want to disable cliprect here */
2329 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
2330 }
2331
2332 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
2333 r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
2334 r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
2335 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2336 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2337 }
2338
2339 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
2340 struct r600_vertexbuf_state *state,
2341 unsigned resource_offset,
2342 unsigned pkt_flags)
2343 {
2344 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2345 uint32_t dirty_mask = state->dirty_mask;
2346
2347 while (dirty_mask) {
2348 struct pipe_vertex_buffer *vb;
2349 struct r600_resource *rbuffer;
2350 uint64_t va;
2351 unsigned buffer_index = u_bit_scan(&dirty_mask);
2352
2353 vb = &state->vb[buffer_index];
2354 rbuffer = (struct r600_resource*)vb->buffer;
2355 assert(rbuffer);
2356
2357 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
2358 va += vb->buffer_offset;
2359
2360 /* fetch resources start at index 992 */
2361 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2362 r600_write_value(cs, (resource_offset + buffer_index) * 8);
2363 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
2364 r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2365 r600_write_value(cs, /* RESOURCEi_WORD2 */
2366 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2367 S_030008_STRIDE(vb->stride) |
2368 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2369 r600_write_value(cs, /* RESOURCEi_WORD3 */
2370 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2371 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2372 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2373 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2374 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2375 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2376 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
2377 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2378
2379 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2380 r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
2381 }
2382 state->dirty_mask = 0;
2383 }
2384
2385 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2386 {
2387 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
2388 }
2389
2390 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2391 {
2392 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
2393 RADEON_CP_PACKET3_COMPUTE_MODE);
2394 }
2395
2396 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2397 struct r600_constbuf_state *state,
2398 unsigned buffer_id_base,
2399 unsigned reg_alu_constbuf_size,
2400 unsigned reg_alu_const_cache)
2401 {
2402 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2403 uint32_t dirty_mask = state->dirty_mask;
2404
2405 while (dirty_mask) {
2406 struct pipe_constant_buffer *cb;
2407 struct r600_resource *rbuffer;
2408 uint64_t va;
2409 unsigned buffer_index = ffs(dirty_mask) - 1;
2410
2411 cb = &state->cb[buffer_index];
2412 rbuffer = (struct r600_resource*)cb->buffer;
2413 assert(rbuffer);
2414
2415 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
2416 va += cb->buffer_offset;
2417
2418 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2419 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
2420 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
2421
2422 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2423 r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
2424
2425 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2426 r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
2427 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
2428 r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2429 r600_write_value(cs, /* RESOURCEi_WORD2 */
2430 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2431 S_030008_STRIDE(16) |
2432 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2433 r600_write_value(cs, /* RESOURCEi_WORD3 */
2434 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2435 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2436 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2437 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2438 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2439 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2440 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
2441 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2442
2443 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2444 r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
2445
2446 dirty_mask &= ~(1 << buffer_index);
2447 }
2448 state->dirty_mask = 0;
2449 }
2450
2451 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2452 {
2453 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 176,
2454 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2455 R_028980_ALU_CONST_CACHE_VS_0);
2456 }
2457
2458 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2459 {
2460 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
2461 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2462 R_0289C0_ALU_CONST_CACHE_GS_0);
2463 }
2464
2465 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2466 {
2467 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
2468 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2469 R_028940_ALU_CONST_CACHE_PS_0);
2470 }
2471
2472 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2473 struct r600_samplerview_state *state,
2474 unsigned resource_id_base)
2475 {
2476 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2477 uint32_t dirty_mask = state->dirty_mask;
2478
2479 while (dirty_mask) {
2480 struct r600_pipe_sampler_view *rview;
2481 unsigned resource_index = u_bit_scan(&dirty_mask);
2482 unsigned reloc;
2483
2484 rview = state->views[resource_index];
2485 assert(rview);
2486
2487 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2488 r600_write_value(cs, (resource_id_base + resource_index) * 8);
2489 r600_write_array(cs, 8, rview->tex_resource_words);
2490
2491 reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rview->tex_resource,
2492 RADEON_USAGE_READ);
2493 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2494 r600_write_value(cs, reloc);
2495
2496 if (!rview->skip_mip_address_reloc) {
2497 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2498 r600_write_value(cs, reloc);
2499 }
2500 }
2501 state->dirty_mask = 0;
2502 }
2503
2504 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2505 {
2506 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 176 + R600_MAX_CONST_BUFFERS);
2507 }
2508
2509 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2510 {
2511 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2512 }
2513
2514 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2515 {
2516 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2517 }
2518
2519 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2520 struct r600_textures_info *texinfo,
2521 unsigned resource_id_base,
2522 unsigned border_index_reg)
2523 {
2524 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2525 uint32_t dirty_mask = texinfo->states.dirty_mask;
2526
2527 while (dirty_mask) {
2528 struct r600_pipe_sampler_state *rstate;
2529 unsigned i = u_bit_scan(&dirty_mask);
2530
2531 rstate = texinfo->states.states[i];
2532 assert(rstate);
2533
2534 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2535 r600_write_value(cs, (resource_id_base + i) * 3);
2536 r600_write_array(cs, 3, rstate->tex_sampler_words);
2537
2538 if (rstate->border_color_use) {
2539 r600_write_config_reg_seq(cs, border_index_reg, 5);
2540 r600_write_value(cs, i);
2541 r600_write_array(cs, 4, rstate->border_color.ui);
2542 }
2543 }
2544 texinfo->states.dirty_mask = 0;
2545 }
2546
2547 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2548 {
2549 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
2550 }
2551
2552 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2553 {
2554 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX);
2555 }
2556
2557 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2558 {
2559 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
2560 }
2561
2562 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2563 {
2564 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2565 uint8_t mask = s->sample_mask;
2566
2567 r600_write_context_reg(rctx->rings.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2568 mask | (mask << 8) | (mask << 16) | (mask << 24));
2569 }
2570
2571 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2572 {
2573 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2574 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2575 uint16_t mask = s->sample_mask;
2576
2577 r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2578 r600_write_value(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2579 r600_write_value(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2580 }
2581
2582 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2583 {
2584 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2585 struct r600_cso_state *state = (struct r600_cso_state*)a;
2586 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2587
2588 r600_write_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2589 (r600_resource_va(rctx->context.screen, &shader->buffer->b.b) + shader->offset) >> 8);
2590 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2591 r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, shader->buffer, RADEON_USAGE_READ));
2592 }
2593
2594 void evergreen_init_state_functions(struct r600_context *rctx)
2595 {
2596 unsigned id = 4;
2597
2598 /* !!!
2599 * To avoid GPU lockup registers must be emited in a specific order
2600 * (no kidding ...). The order below is important and have been
2601 * partialy infered from analyzing fglrx command stream.
2602 *
2603 * Don't reorder atom without carefully checking the effect (GPU lockup
2604 * or piglit regression).
2605 * !!!
2606 */
2607
2608 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
2609 /* shader const */
2610 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
2611 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
2612 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
2613 /* shader program */
2614 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
2615 /* sampler */
2616 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
2617 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
2618 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
2619 /* resources */
2620 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
2621 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
2622 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
2623 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
2624 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
2625
2626 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 7);
2627
2628 if (rctx->chip_class == EVERGREEN) {
2629 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
2630 } else {
2631 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
2632 }
2633 rctx->sample_mask.sample_mask = ~0;
2634
2635 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2636 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2637 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
2638 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
2639 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
2640 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
2641 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
2642 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
2643 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
2644 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
2645 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
2646 r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 4);
2647 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2648 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2649 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
2650 r600_init_atom(rctx, &rctx->streamout.begin_atom, id++, r600_emit_streamout_begin, 0);
2651
2652 rctx->context.create_blend_state = evergreen_create_blend_state;
2653 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
2654 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
2655 rctx->context.create_sampler_state = evergreen_create_sampler_state;
2656 rctx->context.create_sampler_view = evergreen_create_sampler_view;
2657 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
2658 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
2659 rctx->context.set_scissor_state = evergreen_set_scissor_state;
2660 evergreen_init_compute_state_functions(rctx);
2661 }
2662
2663 void cayman_init_common_regs(struct r600_command_buffer *cb,
2664 enum chip_class ctx_chip_class,
2665 enum radeon_family ctx_family,
2666 int ctx_drm_minor)
2667 {
2668 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2669 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2670 /* always set the temp clauses */
2671 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2672
2673 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2674 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2675 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2676
2677 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2678
2679 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2680
2681 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2682
2683 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2684 }
2685
2686 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2687 {
2688 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2689
2690 r600_init_command_buffer(cb, 256);
2691
2692 /* This must be first. */
2693 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2694 r600_store_value(cb, 0x80000000);
2695 r600_store_value(cb, 0x80000000);
2696
2697 /* We're setting config registers here. */
2698 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2699 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2700
2701 cayman_init_common_regs(cb, rctx->chip_class,
2702 rctx->family, rctx->screen->info.drm_minor);
2703
2704 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2705 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2706
2707 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2708 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2709 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2710 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2711 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2712 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2713 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2714
2715 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2716 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2717 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2718 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2719 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2720
2721 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2722 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2723 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2724 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2725 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2726 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2727 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2728 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2729 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2730 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2731 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2732 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2733 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2734 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2735
2736 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2737 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2738 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2739
2740 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2741 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2742 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2743
2744 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2745
2746 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2747
2748 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2749 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2750 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2751
2752 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
2753 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2754 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2755
2756 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2757
2758 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2759 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2760 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2761
2762 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2763
2764 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2765
2766 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2767
2768 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2769 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2770 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2771 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2772
2773 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2774 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2775
2776 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2777 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2778 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2779
2780 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2781 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2782 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2783
2784 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2785 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2786 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2787 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2788 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2789
2790 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2791 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2792 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2793
2794 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2795 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2796 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2797
2798 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2799 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2800 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2801
2802 /* to avoid GPU doing any preloading of constant from random address */
2803 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2804 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2805 r600_store_value(cb, 0);
2806 r600_store_value(cb, 0);
2807 r600_store_value(cb, 0);
2808 r600_store_value(cb, 0);
2809 r600_store_value(cb, 0);
2810 r600_store_value(cb, 0);
2811 r600_store_value(cb, 0);
2812 r600_store_value(cb, 0);
2813 r600_store_value(cb, 0);
2814 r600_store_value(cb, 0);
2815 r600_store_value(cb, 0);
2816 r600_store_value(cb, 0);
2817 r600_store_value(cb, 0);
2818 r600_store_value(cb, 0);
2819 r600_store_value(cb, 0);
2820
2821 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2822 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2823 r600_store_value(cb, 0);
2824 r600_store_value(cb, 0);
2825 r600_store_value(cb, 0);
2826 r600_store_value(cb, 0);
2827 r600_store_value(cb, 0);
2828 r600_store_value(cb, 0);
2829 r600_store_value(cb, 0);
2830 r600_store_value(cb, 0);
2831 r600_store_value(cb, 0);
2832 r600_store_value(cb, 0);
2833 r600_store_value(cb, 0);
2834 r600_store_value(cb, 0);
2835 r600_store_value(cb, 0);
2836 r600_store_value(cb, 0);
2837 r600_store_value(cb, 0);
2838
2839 if (rctx->screen->has_streamout) {
2840 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2841 }
2842
2843 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2844 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2845 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2846 r600_store_context_reg(cb, R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0);
2847 r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
2848 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0);
2849
2850 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2851 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2852 }
2853
2854 void evergreen_init_common_regs(struct r600_command_buffer *cb,
2855 enum chip_class ctx_chip_class,
2856 enum radeon_family ctx_family,
2857 int ctx_drm_minor)
2858 {
2859 int ps_prio;
2860 int vs_prio;
2861 int gs_prio;
2862 int es_prio;
2863
2864 int hs_prio;
2865 int cs_prio;
2866 int ls_prio;
2867
2868 int num_ps_gprs;
2869 int num_vs_gprs;
2870 int num_gs_gprs;
2871 int num_es_gprs;
2872 int num_hs_gprs;
2873 int num_ls_gprs;
2874 int num_temp_gprs;
2875
2876 unsigned tmp;
2877
2878 ps_prio = 0;
2879 vs_prio = 1;
2880 gs_prio = 2;
2881 es_prio = 3;
2882 hs_prio = 0;
2883 ls_prio = 0;
2884 cs_prio = 0;
2885
2886 num_ps_gprs = 93;
2887 num_vs_gprs = 46;
2888 num_temp_gprs = 4;
2889 num_gs_gprs = 31;
2890 num_es_gprs = 31;
2891 num_hs_gprs = 23;
2892 num_ls_gprs = 23;
2893
2894 tmp = 0;
2895 switch (ctx_family) {
2896 case CHIP_CEDAR:
2897 case CHIP_PALM:
2898 case CHIP_SUMO:
2899 case CHIP_SUMO2:
2900 case CHIP_CAICOS:
2901 break;
2902 default:
2903 tmp |= S_008C00_VC_ENABLE(1);
2904 break;
2905 }
2906 tmp |= S_008C00_EXPORT_SRC_C(1);
2907 tmp |= S_008C00_CS_PRIO(cs_prio);
2908 tmp |= S_008C00_LS_PRIO(ls_prio);
2909 tmp |= S_008C00_HS_PRIO(hs_prio);
2910 tmp |= S_008C00_PS_PRIO(ps_prio);
2911 tmp |= S_008C00_VS_PRIO(vs_prio);
2912 tmp |= S_008C00_GS_PRIO(gs_prio);
2913 tmp |= S_008C00_ES_PRIO(es_prio);
2914
2915 /* enable dynamic GPR resource management */
2916 if (ctx_drm_minor >= 7) {
2917 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2918 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2919 /* always set temp clauses */
2920 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2921 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2922 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2923 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2924 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2925 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2926 S_028838_PS_GPRS(0x1e) |
2927 S_028838_VS_GPRS(0x1e) |
2928 S_028838_GS_GPRS(0x1e) |
2929 S_028838_ES_GPRS(0x1e) |
2930 S_028838_HS_GPRS(0x1e) |
2931 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2932 } else {
2933 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2934 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2935
2936 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2937 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2938 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2939 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2940
2941 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2942 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2943 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2944
2945 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2946 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2947 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2948 }
2949
2950 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2951 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2952
2953 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2954
2955 /* The cs checker requires this register to be set. */
2956 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2957
2958 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2959
2960 return;
2961 }
2962
2963 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2964 {
2965 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2966 int num_ps_threads;
2967 int num_vs_threads;
2968 int num_gs_threads;
2969 int num_es_threads;
2970 int num_hs_threads;
2971 int num_ls_threads;
2972
2973 int num_ps_stack_entries;
2974 int num_vs_stack_entries;
2975 int num_gs_stack_entries;
2976 int num_es_stack_entries;
2977 int num_hs_stack_entries;
2978 int num_ls_stack_entries;
2979 enum radeon_family family;
2980 unsigned tmp;
2981
2982 if (rctx->chip_class == CAYMAN) {
2983 cayman_init_atom_start_cs(rctx);
2984 return;
2985 }
2986
2987 r600_init_command_buffer(cb, 256);
2988
2989 /* This must be first. */
2990 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2991 r600_store_value(cb, 0x80000000);
2992 r600_store_value(cb, 0x80000000);
2993
2994 /* We're setting config registers here. */
2995 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2996 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2997
2998 evergreen_init_common_regs(cb, rctx->chip_class,
2999 rctx->family, rctx->screen->info.drm_minor);
3000
3001 family = rctx->family;
3002 switch (family) {
3003 case CHIP_CEDAR:
3004 default:
3005 num_ps_threads = 96;
3006 num_vs_threads = 16;
3007 num_gs_threads = 16;
3008 num_es_threads = 16;
3009 num_hs_threads = 16;
3010 num_ls_threads = 16;
3011 num_ps_stack_entries = 42;
3012 num_vs_stack_entries = 42;
3013 num_gs_stack_entries = 42;
3014 num_es_stack_entries = 42;
3015 num_hs_stack_entries = 42;
3016 num_ls_stack_entries = 42;
3017 break;
3018 case CHIP_REDWOOD:
3019 num_ps_threads = 128;
3020 num_vs_threads = 20;
3021 num_gs_threads = 20;
3022 num_es_threads = 20;
3023 num_hs_threads = 20;
3024 num_ls_threads = 20;
3025 num_ps_stack_entries = 42;
3026 num_vs_stack_entries = 42;
3027 num_gs_stack_entries = 42;
3028 num_es_stack_entries = 42;
3029 num_hs_stack_entries = 42;
3030 num_ls_stack_entries = 42;
3031 break;
3032 case CHIP_JUNIPER:
3033 num_ps_threads = 128;
3034 num_vs_threads = 20;
3035 num_gs_threads = 20;
3036 num_es_threads = 20;
3037 num_hs_threads = 20;
3038 num_ls_threads = 20;
3039 num_ps_stack_entries = 85;
3040 num_vs_stack_entries = 85;
3041 num_gs_stack_entries = 85;
3042 num_es_stack_entries = 85;
3043 num_hs_stack_entries = 85;
3044 num_ls_stack_entries = 85;
3045 break;
3046 case CHIP_CYPRESS:
3047 case CHIP_HEMLOCK:
3048 num_ps_threads = 128;
3049 num_vs_threads = 20;
3050 num_gs_threads = 20;
3051 num_es_threads = 20;
3052 num_hs_threads = 20;
3053 num_ls_threads = 20;
3054 num_ps_stack_entries = 85;
3055 num_vs_stack_entries = 85;
3056 num_gs_stack_entries = 85;
3057 num_es_stack_entries = 85;
3058 num_hs_stack_entries = 85;
3059 num_ls_stack_entries = 85;
3060 break;
3061 case CHIP_PALM:
3062 num_ps_threads = 96;
3063 num_vs_threads = 16;
3064 num_gs_threads = 16;
3065 num_es_threads = 16;
3066 num_hs_threads = 16;
3067 num_ls_threads = 16;
3068 num_ps_stack_entries = 42;
3069 num_vs_stack_entries = 42;
3070 num_gs_stack_entries = 42;
3071 num_es_stack_entries = 42;
3072 num_hs_stack_entries = 42;
3073 num_ls_stack_entries = 42;
3074 break;
3075 case CHIP_SUMO:
3076 num_ps_threads = 96;
3077 num_vs_threads = 25;
3078 num_gs_threads = 25;
3079 num_es_threads = 25;
3080 num_hs_threads = 25;
3081 num_ls_threads = 25;
3082 num_ps_stack_entries = 42;
3083 num_vs_stack_entries = 42;
3084 num_gs_stack_entries = 42;
3085 num_es_stack_entries = 42;
3086 num_hs_stack_entries = 42;
3087 num_ls_stack_entries = 42;
3088 break;
3089 case CHIP_SUMO2:
3090 num_ps_threads = 96;
3091 num_vs_threads = 25;
3092 num_gs_threads = 25;
3093 num_es_threads = 25;
3094 num_hs_threads = 25;
3095 num_ls_threads = 25;
3096 num_ps_stack_entries = 85;
3097 num_vs_stack_entries = 85;
3098 num_gs_stack_entries = 85;
3099 num_es_stack_entries = 85;
3100 num_hs_stack_entries = 85;
3101 num_ls_stack_entries = 85;
3102 break;
3103 case CHIP_BARTS:
3104 num_ps_threads = 128;
3105 num_vs_threads = 20;
3106 num_gs_threads = 20;
3107 num_es_threads = 20;
3108 num_hs_threads = 20;
3109 num_ls_threads = 20;
3110 num_ps_stack_entries = 85;
3111 num_vs_stack_entries = 85;
3112 num_gs_stack_entries = 85;
3113 num_es_stack_entries = 85;
3114 num_hs_stack_entries = 85;
3115 num_ls_stack_entries = 85;
3116 break;
3117 case CHIP_TURKS:
3118 num_ps_threads = 128;
3119 num_vs_threads = 20;
3120 num_gs_threads = 20;
3121 num_es_threads = 20;
3122 num_hs_threads = 20;
3123 num_ls_threads = 20;
3124 num_ps_stack_entries = 42;
3125 num_vs_stack_entries = 42;
3126 num_gs_stack_entries = 42;
3127 num_es_stack_entries = 42;
3128 num_hs_stack_entries = 42;
3129 num_ls_stack_entries = 42;
3130 break;
3131 case CHIP_CAICOS:
3132 num_ps_threads = 128;
3133 num_vs_threads = 10;
3134 num_gs_threads = 10;
3135 num_es_threads = 10;
3136 num_hs_threads = 10;
3137 num_ls_threads = 10;
3138 num_ps_stack_entries = 42;
3139 num_vs_stack_entries = 42;
3140 num_gs_stack_entries = 42;
3141 num_es_stack_entries = 42;
3142 num_hs_stack_entries = 42;
3143 num_ls_stack_entries = 42;
3144 break;
3145 }
3146
3147 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
3148 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
3149 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
3150 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
3151
3152 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
3153 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3154
3155 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
3156 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
3157 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3158
3159 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
3160 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
3161 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3162
3163 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
3164 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
3165 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3166
3167 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
3168 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
3169 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3170
3171 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
3172 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
3173
3174 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
3175 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3176 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3177 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3178 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3179 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3180 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3181
3182 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3183 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3184 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3185 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3186 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3187
3188 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
3189 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3190 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
3191 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3192 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3193 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3194 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3195 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3196 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
3197 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3198 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3199 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3200 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3201 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
3202
3203 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
3204 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
3205 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
3206
3207 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
3208
3209 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
3210
3211 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
3212 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3213 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
3214
3215 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
3216
3217 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
3218
3219 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
3220 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3221 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3222
3223 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
3224 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
3225 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
3226
3227 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
3228 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3229 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
3230
3231 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
3232 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3233 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3234 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3235
3236 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
3237 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
3238 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
3239 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
3240 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
3241
3242 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
3243 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3244 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3245
3246 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
3247 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3248 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3249
3250 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3251 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3252 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
3253
3254 /* to avoid GPU doing any preloading of constant from random address */
3255 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
3256 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
3257 r600_store_value(cb, 0);
3258 r600_store_value(cb, 0);
3259 r600_store_value(cb, 0);
3260 r600_store_value(cb, 0);
3261 r600_store_value(cb, 0);
3262 r600_store_value(cb, 0);
3263 r600_store_value(cb, 0);
3264 r600_store_value(cb, 0);
3265 r600_store_value(cb, 0);
3266 r600_store_value(cb, 0);
3267 r600_store_value(cb, 0);
3268 r600_store_value(cb, 0);
3269 r600_store_value(cb, 0);
3270 r600_store_value(cb, 0);
3271 r600_store_value(cb, 0);
3272
3273 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
3274 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
3275 r600_store_value(cb, 0);
3276 r600_store_value(cb, 0);
3277 r600_store_value(cb, 0);
3278 r600_store_value(cb, 0);
3279 r600_store_value(cb, 0);
3280 r600_store_value(cb, 0);
3281 r600_store_value(cb, 0);
3282 r600_store_value(cb, 0);
3283 r600_store_value(cb, 0);
3284 r600_store_value(cb, 0);
3285 r600_store_value(cb, 0);
3286 r600_store_value(cb, 0);
3287 r600_store_value(cb, 0);
3288 r600_store_value(cb, 0);
3289 r600_store_value(cb, 0);
3290
3291 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
3292 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
3293 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
3294
3295 if (rctx->screen->has_streamout) {
3296 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3297 }
3298
3299 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
3300 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3301 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
3302 r600_store_context_reg(cb, R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0);
3303 r600_store_context_reg(cb, R_0288EC_SQ_LDS_ALLOC_PS, 0);
3304 r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
3305
3306 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3307 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3308 }
3309
3310 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3311 {
3312 struct r600_context *rctx = (struct r600_context *)ctx;
3313 struct r600_pipe_state *rstate = &shader->rstate;
3314 struct r600_shader *rshader = &shader->shader;
3315 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
3316 int pos_index = -1, face_index = -1;
3317 int ninterp = 0;
3318 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
3319 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
3320 unsigned z_export = 0, stencil_export = 0;
3321 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3322
3323 rstate->nregs = 0;
3324
3325 for (i = 0; i < rshader->ninput; i++) {
3326 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3327 POSITION goes via GPRs from the SC so isn't counted */
3328 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3329 pos_index = i;
3330 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
3331 face_index = i;
3332 else {
3333 ninterp++;
3334 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
3335 have_linear = TRUE;
3336 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
3337 have_perspective = TRUE;
3338 if (rshader->input[i].centroid)
3339 have_centroid = TRUE;
3340 }
3341
3342 sid = rshader->input[i].spi_sid;
3343
3344 if (sid) {
3345
3346 tmp = S_028644_SEMANTIC(sid);
3347
3348 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3349 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3350 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3351 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3352 tmp |= S_028644_FLAT_SHADE(1);
3353 }
3354
3355 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3356 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3357 tmp |= S_028644_PT_SPRITE_TEX(1);
3358 }
3359
3360 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
3361 tmp);
3362
3363 idx++;
3364 }
3365 }
3366
3367 for (i = 0; i < rshader->noutput; i++) {
3368 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3369 z_export = 1;
3370 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3371 stencil_export = 1;
3372 }
3373 if (rshader->uses_kill)
3374 db_shader_control |= S_02880C_KILL_ENABLE(1);
3375
3376 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3377 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3378
3379 exports_ps = 0;
3380 for (i = 0; i < rshader->noutput; i++) {
3381 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3382 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3383 exports_ps |= 1;
3384 }
3385
3386 num_cout = rshader->nr_ps_color_exports;
3387
3388 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3389 if (!exports_ps) {
3390 /* always at least export 1 component per pixel */
3391 exports_ps = 2;
3392 }
3393 shader->nr_ps_color_outputs = num_cout;
3394 if (ninterp == 0) {
3395 ninterp = 1;
3396 have_perspective = TRUE;
3397 }
3398
3399 if (!have_perspective && !have_linear)
3400 have_perspective = TRUE;
3401
3402 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3403 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3404 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3405 spi_input_z = 0;
3406 if (pos_index != -1) {
3407 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3408 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
3409 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3410 spi_input_z |= 1;
3411 }
3412
3413 spi_ps_in_control_1 = 0;
3414 if (face_index != -1) {
3415 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3416 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3417 }
3418
3419 spi_baryc_cntl = 0;
3420 if (have_perspective)
3421 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
3422 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
3423 if (have_linear)
3424 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
3425 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
3426
3427 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
3428 spi_ps_in_control_0);
3429 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
3430 spi_ps_in_control_1);
3431 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
3432 0);
3433 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
3434 r600_pipe_state_add_reg(rstate,
3435 R_0286E0_SPI_BARYC_CNTL,
3436 spi_baryc_cntl);
3437
3438 r600_pipe_state_add_reg_bo(rstate,
3439 R_028840_SQ_PGM_START_PS,
3440 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3441 shader->bo, RADEON_USAGE_READ);
3442 r600_pipe_state_add_reg(rstate,
3443 R_028844_SQ_PGM_RESOURCES_PS,
3444 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3445 S_028844_PRIME_CACHE_ON_DRAW(1) |
3446 S_028844_STACK_SIZE(rshader->bc.nstack));
3447 r600_pipe_state_add_reg(rstate,
3448 R_02884C_SQ_PGM_EXPORTS_PS,
3449 exports_ps);
3450
3451 shader->db_shader_control = db_shader_control;
3452 shader->ps_depth_export = z_export | stencil_export;
3453
3454 shader->sprite_coord_enable = sprite_coord_enable;
3455 if (rctx->rasterizer)
3456 shader->flatshade = rctx->rasterizer->flatshade;
3457 }
3458
3459 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3460 {
3461 struct r600_context *rctx = (struct r600_context *)ctx;
3462 struct r600_pipe_state *rstate = &shader->rstate;
3463 struct r600_shader *rshader = &shader->shader;
3464 unsigned spi_vs_out_id[10] = {};
3465 unsigned i, tmp, nparams = 0;
3466
3467 /* clear previous register */
3468 rstate->nregs = 0;
3469
3470 for (i = 0; i < rshader->noutput; i++) {
3471 if (rshader->output[i].spi_sid) {
3472 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3473 spi_vs_out_id[nparams / 4] |= tmp;
3474 nparams++;
3475 }
3476 }
3477
3478 for (i = 0; i < 10; i++) {
3479 r600_pipe_state_add_reg(rstate,
3480 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
3481 spi_vs_out_id[i]);
3482 }
3483
3484 /* Certain attributes (position, psize, etc.) don't count as params.
3485 * VS is required to export at least one param and r600_shader_from_tgsi()
3486 * takes care of adding a dummy export.
3487 */
3488 if (nparams < 1)
3489 nparams = 1;
3490
3491 r600_pipe_state_add_reg(rstate,
3492 R_0286C4_SPI_VS_OUT_CONFIG,
3493 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3494 r600_pipe_state_add_reg(rstate,
3495 R_028860_SQ_PGM_RESOURCES_VS,
3496 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3497 S_028860_STACK_SIZE(rshader->bc.nstack));
3498 r600_pipe_state_add_reg_bo(rstate,
3499 R_02885C_SQ_PGM_START_VS,
3500 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3501 shader->bo, RADEON_USAGE_READ);
3502
3503 shader->pa_cl_vs_out_cntl =
3504 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3505 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3506 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3507 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
3508 }
3509
3510 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3511 {
3512 struct pipe_blend_state blend;
3513
3514 memset(&blend, 0, sizeof(blend));
3515 blend.independent_blend_enable = true;
3516 blend.rt[0].colormask = 0xf;
3517 return evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_RESOLVE);
3518 }
3519
3520 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3521 {
3522 struct pipe_blend_state blend;
3523
3524 memset(&blend, 0, sizeof(blend));
3525 blend.independent_blend_enable = true;
3526 blend.rt[0].colormask = 0xf;
3527 return evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_DECOMPRESS);
3528 }
3529
3530 void *evergreen_create_fmask_decompress_blend(struct r600_context *rctx)
3531 {
3532 struct pipe_blend_state blend;
3533
3534 memset(&blend, 0, sizeof(blend));
3535 blend.independent_blend_enable = true;
3536 blend.rt[0].colormask = 0xf;
3537 return evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_FMASK_DECOMPRESS);
3538 }
3539
3540 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3541 {
3542 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3543
3544 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
3545 }
3546
3547 void evergreen_update_db_shader_control(struct r600_context * rctx)
3548 {
3549 bool dual_export = rctx->framebuffer.export_16bpc &&
3550 !rctx->ps_shader->current->ps_depth_export;
3551
3552 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
3553 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3554 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3555 V_02880C_EXPORT_DB_FULL) |
3556 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3557
3558 /* When alpha test is enabled we can't trust the hw to make the proper
3559 * decision on the order in which ztest should be run related to fragment
3560 * shader execution.
3561 *
3562 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3563 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3564 * execution and thus after alpha test so if discarded by the alpha test
3565 * the z value is not written.
3566 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3567 * get a hang unless you flush the DB in between. For now just use
3568 * LATE_Z.
3569 */
3570 if (rctx->alphatest_state.sx_alpha_test_control) {
3571 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3572 } else {
3573 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3574 }
3575
3576 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3577 rctx->db_misc_state.db_shader_control = db_shader_control;
3578 rctx->db_misc_state.atom.dirty = true;
3579 }
3580 }
3581
3582 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3583 struct pipe_resource *dst,
3584 unsigned dst_level,
3585 unsigned dst_x,
3586 unsigned dst_y,
3587 unsigned dst_z,
3588 struct pipe_resource *src,
3589 unsigned src_level,
3590 unsigned src_x,
3591 unsigned src_y,
3592 unsigned src_z,
3593 unsigned copy_height,
3594 unsigned pitch,
3595 unsigned bpp)
3596 {
3597 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
3598 struct r600_texture *rsrc = (struct r600_texture*)src;
3599 struct r600_texture *rdst = (struct r600_texture*)dst;
3600 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3601 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3602 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split;
3603 uint64_t base, addr;
3604
3605 /* make sure that the dma ring is only one active */
3606 rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
3607
3608 dst_mode = rdst->surface.level[dst_level].mode;
3609 src_mode = rsrc->surface.level[src_level].mode;
3610 /* downcast linear aligned to linear to simplify test */
3611 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3612 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3613 assert(dst_mode != src_mode);
3614
3615 y = 0;
3616 sub_cmd = 0x8;
3617 lbpp = util_logbase2(bpp);
3618 pitch_tile_max = ((pitch / bpp) >> 3) - 1;
3619 nbanks = eg_num_banks(rctx->screen->tiling_info.num_banks);
3620
3621 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
3622 /* T2L */
3623 array_mode = evergreen_array_mode(src_mode);
3624 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) >> 6;
3625 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3626 /* linear height must be the same as the slice tile max height, it's ok even
3627 * if the linear destination/source have smaller heigh as the size of the
3628 * dma packet will be using the copy_height which is always smaller or equal
3629 * to the linear height
3630 */
3631 height = rsrc->surface.level[src_level].npix_y;
3632 detile = 1;
3633 x = src_x;
3634 y = src_y;
3635 z = src_z;
3636 base = rsrc->surface.level[src_level].offset;
3637 addr = rdst->surface.level[dst_level].offset;
3638 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3639 addr += dst_y * pitch + dst_x * bpp;
3640 bank_h = eg_bank_wh(rsrc->surface.bankh);
3641 bank_w = eg_bank_wh(rsrc->surface.bankw);
3642 mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
3643 tile_split = eg_tile_split(rsrc->surface.tile_split);
3644 base += r600_resource_va(&rctx->screen->screen, src);
3645 addr += r600_resource_va(&rctx->screen->screen, dst);
3646 } else {
3647 /* L2T */
3648 array_mode = evergreen_array_mode(dst_mode);
3649 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) >> 6;
3650 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3651 /* linear height must be the same as the slice tile max height, it's ok even
3652 * if the linear destination/source have smaller heigh as the size of the
3653 * dma packet will be using the copy_height which is always smaller or equal
3654 * to the linear height
3655 */
3656 height = rdst->surface.level[dst_level].npix_y;
3657 detile = 0;
3658 x = dst_x;
3659 y = dst_y;
3660 z = dst_z;
3661 base = rdst->surface.level[dst_level].offset;
3662 addr = rsrc->surface.level[src_level].offset;
3663 addr += rsrc->surface.level[src_level].slice_size * src_z;
3664 addr += src_y * pitch + src_x * bpp;
3665 bank_h = eg_bank_wh(rdst->surface.bankh);
3666 bank_w = eg_bank_wh(rdst->surface.bankw);
3667 mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
3668 tile_split = eg_tile_split(rdst->surface.tile_split);
3669 base += r600_resource_va(&rctx->screen->screen, dst);
3670 addr += r600_resource_va(&rctx->screen->screen, src);
3671 }
3672
3673 size = (copy_height * pitch) >> 2;
3674 ncopy = (size / 0x000fffff) + !!(size % 0x000fffff);
3675 r600_need_dma_space(rctx, ncopy * 9);
3676
3677 for (i = 0; i < ncopy; i++) {
3678 cheight = copy_height;
3679 if (((cheight * pitch) >> 2) > 0x000fffff) {
3680 cheight = (0x000fffff << 2) / pitch;
3681 }
3682 size = (cheight * pitch) >> 2;
3683 /* emit reloc before writting cs so that cs is always in consistent state */
3684 r600_context_bo_reloc(rctx, &rctx->rings.dma, &rsrc->resource, RADEON_USAGE_READ);
3685 r600_context_bo_reloc(rctx, &rctx->rings.dma, &rdst->resource, RADEON_USAGE_WRITE);
3686 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
3687 cs->buf[cs->cdw++] = base >> 8;
3688 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3689 (lbpp << 24) | (bank_h << 21) |
3690 (bank_w << 18) | (mt_aspect << 16);
3691 cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
3692 cs->buf[cs->cdw++] = (slice_tile_max << 0);
3693 cs->buf[cs->cdw++] = (x << 0) | (z << 18);
3694 cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25);
3695 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3696 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3697 copy_height -= cheight;
3698 addr += cheight * pitch;
3699 y += cheight;
3700 }
3701 }
3702
3703 boolean evergreen_dma_blit(struct pipe_context *ctx,
3704 struct pipe_resource *dst,
3705 unsigned dst_level,
3706 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3707 struct pipe_resource *src,
3708 unsigned src_level,
3709 const struct pipe_box *src_box)
3710 {
3711 struct r600_context *rctx = (struct r600_context *)ctx;
3712 struct r600_texture *rsrc = (struct r600_texture*)src;
3713 struct r600_texture *rdst = (struct r600_texture*)dst;
3714 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3715 unsigned src_w, dst_w;
3716
3717 if (rctx->rings.dma.cs == NULL) {
3718 return FALSE;
3719 }
3720 if (src->format != dst->format) {
3721 return FALSE;
3722 }
3723
3724 bpp = rdst->surface.bpe;
3725 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3726 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3727 src_w = rsrc->surface.level[src_level].npix_x;
3728 dst_w = rdst->surface.level[dst_level].npix_x;
3729 copy_height = src_box->height / rsrc->surface.blk_h;
3730
3731 dst_mode = rdst->surface.level[dst_level].mode;
3732 src_mode = rsrc->surface.level[src_level].mode;
3733 /* downcast linear aligned to linear to simplify test */
3734 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3735 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3736
3737 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3738 /* FIXME evergreen can do partial blit */
3739 return FALSE;
3740 }
3741 /* the x test here are currently useless (because we don't support partial blit)
3742 * but keep them around so we don't forget about those
3743 */
3744 if ((src_pitch & 0x7) || (src_box->x & 0x7) || (dst_x & 0x7) || (src_box->y & 0x7) || (dst_y & 0x7)) {
3745 return FALSE;
3746 }
3747
3748 if (src_mode == dst_mode) {
3749 uint64_t dst_offset, src_offset;
3750 /* simple dma blit would do NOTE code here assume :
3751 * src_box.x/y == 0
3752 * dst_x/y == 0
3753 * dst_pitch == src_pitch
3754 */
3755 src_offset= rsrc->surface.level[src_level].offset;
3756 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3757 src_offset += src_box->y * src_pitch + src_box->x * bpp;
3758 dst_offset = rdst->surface.level[dst_level].offset;
3759 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3760 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3761 evergreen_dma_copy(rctx, dst, src, dst_offset, src_offset,
3762 src_box->height * src_pitch);
3763 } else {
3764 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3765 src, src_level, src_box->x, src_box->y, src_box->z,
3766 copy_height, dst_pitch, bpp);
3767 }
3768 return TRUE;
3769 }