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r600g: flush FMASK and CMASK when changing colorbuffers on Evergreen
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "evergreend.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31 #include "evergreen_compute.h"
32
33 static uint32_t eg_num_banks(uint32_t nbanks)
34 {
35 switch (nbanks) {
36 case 2:
37 return 0;
38 case 4:
39 return 1;
40 case 8:
41 default:
42 return 2;
43 case 16:
44 return 3;
45 }
46 }
47
48
49 static unsigned eg_tile_split(unsigned tile_split)
50 {
51 switch (tile_split) {
52 case 64: tile_split = 0; break;
53 case 128: tile_split = 1; break;
54 case 256: tile_split = 2; break;
55 case 512: tile_split = 3; break;
56 default:
57 case 1024: tile_split = 4; break;
58 case 2048: tile_split = 5; break;
59 case 4096: tile_split = 6; break;
60 }
61 return tile_split;
62 }
63
64 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65 {
66 switch (macro_tile_aspect) {
67 default:
68 case 1: macro_tile_aspect = 0; break;
69 case 2: macro_tile_aspect = 1; break;
70 case 4: macro_tile_aspect = 2; break;
71 case 8: macro_tile_aspect = 3; break;
72 }
73 return macro_tile_aspect;
74 }
75
76 static unsigned eg_bank_wh(unsigned bankwh)
77 {
78 switch (bankwh) {
79 default:
80 case 1: bankwh = 0; break;
81 case 2: bankwh = 1; break;
82 case 4: bankwh = 2; break;
83 case 8: bankwh = 3; break;
84 }
85 return bankwh;
86 }
87
88 static uint32_t r600_translate_blend_function(int blend_func)
89 {
90 switch (blend_func) {
91 case PIPE_BLEND_ADD:
92 return V_028780_COMB_DST_PLUS_SRC;
93 case PIPE_BLEND_SUBTRACT:
94 return V_028780_COMB_SRC_MINUS_DST;
95 case PIPE_BLEND_REVERSE_SUBTRACT:
96 return V_028780_COMB_DST_MINUS_SRC;
97 case PIPE_BLEND_MIN:
98 return V_028780_COMB_MIN_DST_SRC;
99 case PIPE_BLEND_MAX:
100 return V_028780_COMB_MAX_DST_SRC;
101 default:
102 R600_ERR("Unknown blend function %d\n", blend_func);
103 assert(0);
104 break;
105 }
106 return 0;
107 }
108
109 static uint32_t r600_translate_blend_factor(int blend_fact)
110 {
111 switch (blend_fact) {
112 case PIPE_BLENDFACTOR_ONE:
113 return V_028780_BLEND_ONE;
114 case PIPE_BLENDFACTOR_SRC_COLOR:
115 return V_028780_BLEND_SRC_COLOR;
116 case PIPE_BLENDFACTOR_SRC_ALPHA:
117 return V_028780_BLEND_SRC_ALPHA;
118 case PIPE_BLENDFACTOR_DST_ALPHA:
119 return V_028780_BLEND_DST_ALPHA;
120 case PIPE_BLENDFACTOR_DST_COLOR:
121 return V_028780_BLEND_DST_COLOR;
122 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123 return V_028780_BLEND_SRC_ALPHA_SATURATE;
124 case PIPE_BLENDFACTOR_CONST_COLOR:
125 return V_028780_BLEND_CONST_COLOR;
126 case PIPE_BLENDFACTOR_CONST_ALPHA:
127 return V_028780_BLEND_CONST_ALPHA;
128 case PIPE_BLENDFACTOR_ZERO:
129 return V_028780_BLEND_ZERO;
130 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136 case PIPE_BLENDFACTOR_INV_DST_COLOR:
137 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_SRC1_COLOR:
143 return V_028780_BLEND_SRC1_COLOR;
144 case PIPE_BLENDFACTOR_SRC1_ALPHA:
145 return V_028780_BLEND_SRC1_ALPHA;
146 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147 return V_028780_BLEND_INV_SRC1_COLOR;
148 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149 return V_028780_BLEND_INV_SRC1_ALPHA;
150 default:
151 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152 assert(0);
153 break;
154 }
155 return 0;
156 }
157
158 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
159 {
160 switch (dim) {
161 default:
162 case PIPE_TEXTURE_1D:
163 return V_030000_SQ_TEX_DIM_1D;
164 case PIPE_TEXTURE_1D_ARRAY:
165 return V_030000_SQ_TEX_DIM_1D_ARRAY;
166 case PIPE_TEXTURE_2D:
167 case PIPE_TEXTURE_RECT:
168 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
169 V_030000_SQ_TEX_DIM_2D;
170 case PIPE_TEXTURE_2D_ARRAY:
171 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
172 V_030000_SQ_TEX_DIM_2D_ARRAY;
173 case PIPE_TEXTURE_3D:
174 return V_030000_SQ_TEX_DIM_3D;
175 case PIPE_TEXTURE_CUBE:
176 return V_030000_SQ_TEX_DIM_CUBEMAP;
177 }
178 }
179
180 static uint32_t r600_translate_dbformat(enum pipe_format format)
181 {
182 switch (format) {
183 case PIPE_FORMAT_Z16_UNORM:
184 return V_028040_Z_16;
185 case PIPE_FORMAT_Z24X8_UNORM:
186 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
187 return V_028040_Z_24;
188 case PIPE_FORMAT_Z32_FLOAT:
189 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
190 return V_028040_Z_32_FLOAT;
191 default:
192 return ~0U;
193 }
194 }
195
196 static uint32_t r600_translate_colorswap(enum pipe_format format)
197 {
198 switch (format) {
199 /* 8-bit buffers. */
200 case PIPE_FORMAT_L4A4_UNORM:
201 case PIPE_FORMAT_A4R4_UNORM:
202 return V_028C70_SWAP_ALT;
203
204 case PIPE_FORMAT_A8_UNORM:
205 case PIPE_FORMAT_A8_SNORM:
206 case PIPE_FORMAT_A8_UINT:
207 case PIPE_FORMAT_A8_SINT:
208 case PIPE_FORMAT_A16_UNORM:
209 case PIPE_FORMAT_A16_SNORM:
210 case PIPE_FORMAT_A16_UINT:
211 case PIPE_FORMAT_A16_SINT:
212 case PIPE_FORMAT_A16_FLOAT:
213 case PIPE_FORMAT_A32_UINT:
214 case PIPE_FORMAT_A32_SINT:
215 case PIPE_FORMAT_A32_FLOAT:
216 case PIPE_FORMAT_R4A4_UNORM:
217 return V_028C70_SWAP_ALT_REV;
218 case PIPE_FORMAT_I8_UNORM:
219 case PIPE_FORMAT_I8_SNORM:
220 case PIPE_FORMAT_I8_UINT:
221 case PIPE_FORMAT_I8_SINT:
222 case PIPE_FORMAT_I16_UNORM:
223 case PIPE_FORMAT_I16_SNORM:
224 case PIPE_FORMAT_I16_UINT:
225 case PIPE_FORMAT_I16_SINT:
226 case PIPE_FORMAT_I16_FLOAT:
227 case PIPE_FORMAT_I32_UINT:
228 case PIPE_FORMAT_I32_SINT:
229 case PIPE_FORMAT_I32_FLOAT:
230 case PIPE_FORMAT_L8_UNORM:
231 case PIPE_FORMAT_L8_SNORM:
232 case PIPE_FORMAT_L8_UINT:
233 case PIPE_FORMAT_L8_SINT:
234 case PIPE_FORMAT_L8_SRGB:
235 case PIPE_FORMAT_L16_UNORM:
236 case PIPE_FORMAT_L16_SNORM:
237 case PIPE_FORMAT_L16_UINT:
238 case PIPE_FORMAT_L16_SINT:
239 case PIPE_FORMAT_L16_FLOAT:
240 case PIPE_FORMAT_L32_UINT:
241 case PIPE_FORMAT_L32_SINT:
242 case PIPE_FORMAT_L32_FLOAT:
243 case PIPE_FORMAT_R8_UNORM:
244 case PIPE_FORMAT_R8_SNORM:
245 case PIPE_FORMAT_R8_UINT:
246 case PIPE_FORMAT_R8_SINT:
247 return V_028C70_SWAP_STD;
248
249 /* 16-bit buffers. */
250 case PIPE_FORMAT_B5G6R5_UNORM:
251 return V_028C70_SWAP_STD_REV;
252
253 case PIPE_FORMAT_B5G5R5A1_UNORM:
254 case PIPE_FORMAT_B5G5R5X1_UNORM:
255 return V_028C70_SWAP_ALT;
256
257 case PIPE_FORMAT_B4G4R4A4_UNORM:
258 case PIPE_FORMAT_B4G4R4X4_UNORM:
259 return V_028C70_SWAP_ALT;
260
261 case PIPE_FORMAT_Z16_UNORM:
262 return V_028C70_SWAP_STD;
263
264 case PIPE_FORMAT_L8A8_UNORM:
265 case PIPE_FORMAT_L8A8_SNORM:
266 case PIPE_FORMAT_L8A8_UINT:
267 case PIPE_FORMAT_L8A8_SINT:
268 case PIPE_FORMAT_L8A8_SRGB:
269 case PIPE_FORMAT_L16A16_UNORM:
270 case PIPE_FORMAT_L16A16_SNORM:
271 case PIPE_FORMAT_L16A16_UINT:
272 case PIPE_FORMAT_L16A16_SINT:
273 case PIPE_FORMAT_L16A16_FLOAT:
274 case PIPE_FORMAT_L32A32_UINT:
275 case PIPE_FORMAT_L32A32_SINT:
276 case PIPE_FORMAT_L32A32_FLOAT:
277 return V_028C70_SWAP_ALT;
278 case PIPE_FORMAT_R8G8_UNORM:
279 case PIPE_FORMAT_R8G8_SNORM:
280 case PIPE_FORMAT_R8G8_UINT:
281 case PIPE_FORMAT_R8G8_SINT:
282 return V_028C70_SWAP_STD;
283
284 case PIPE_FORMAT_R16_UNORM:
285 case PIPE_FORMAT_R16_SNORM:
286 case PIPE_FORMAT_R16_UINT:
287 case PIPE_FORMAT_R16_SINT:
288 case PIPE_FORMAT_R16_FLOAT:
289 return V_028C70_SWAP_STD;
290
291 /* 32-bit buffers. */
292 case PIPE_FORMAT_A8B8G8R8_SRGB:
293 return V_028C70_SWAP_STD_REV;
294 case PIPE_FORMAT_B8G8R8A8_SRGB:
295 return V_028C70_SWAP_ALT;
296
297 case PIPE_FORMAT_B8G8R8A8_UNORM:
298 case PIPE_FORMAT_B8G8R8X8_UNORM:
299 return V_028C70_SWAP_ALT;
300
301 case PIPE_FORMAT_A8R8G8B8_UNORM:
302 case PIPE_FORMAT_X8R8G8B8_UNORM:
303 return V_028C70_SWAP_ALT_REV;
304 case PIPE_FORMAT_R8G8B8A8_SNORM:
305 case PIPE_FORMAT_R8G8B8A8_UNORM:
306 case PIPE_FORMAT_R8G8B8A8_SINT:
307 case PIPE_FORMAT_R8G8B8A8_UINT:
308 case PIPE_FORMAT_R8G8B8X8_UNORM:
309 return V_028C70_SWAP_STD;
310
311 case PIPE_FORMAT_A8B8G8R8_UNORM:
312 case PIPE_FORMAT_X8B8G8R8_UNORM:
313 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
314 return V_028C70_SWAP_STD_REV;
315
316 case PIPE_FORMAT_Z24X8_UNORM:
317 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
318 return V_028C70_SWAP_STD;
319
320 case PIPE_FORMAT_X8Z24_UNORM:
321 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
322 return V_028C70_SWAP_STD;
323
324 case PIPE_FORMAT_R10G10B10A2_UNORM:
325 case PIPE_FORMAT_R10G10B10X2_SNORM:
326 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
327 return V_028C70_SWAP_STD;
328
329 case PIPE_FORMAT_B10G10R10A2_UNORM:
330 case PIPE_FORMAT_B10G10R10A2_UINT:
331 return V_028C70_SWAP_ALT;
332
333 case PIPE_FORMAT_R11G11B10_FLOAT:
334 case PIPE_FORMAT_R32_FLOAT:
335 case PIPE_FORMAT_R32_UINT:
336 case PIPE_FORMAT_R32_SINT:
337 case PIPE_FORMAT_Z32_FLOAT:
338 case PIPE_FORMAT_R16G16_FLOAT:
339 case PIPE_FORMAT_R16G16_UNORM:
340 case PIPE_FORMAT_R16G16_SNORM:
341 case PIPE_FORMAT_R16G16_UINT:
342 case PIPE_FORMAT_R16G16_SINT:
343 return V_028C70_SWAP_STD;
344
345 /* 64-bit buffers. */
346 case PIPE_FORMAT_R32G32_FLOAT:
347 case PIPE_FORMAT_R32G32_UINT:
348 case PIPE_FORMAT_R32G32_SINT:
349 case PIPE_FORMAT_R16G16B16A16_UNORM:
350 case PIPE_FORMAT_R16G16B16A16_SNORM:
351 case PIPE_FORMAT_R16G16B16A16_UINT:
352 case PIPE_FORMAT_R16G16B16A16_SINT:
353 case PIPE_FORMAT_R16G16B16A16_FLOAT:
354 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
355
356 /* 128-bit buffers. */
357 case PIPE_FORMAT_R32G32B32A32_FLOAT:
358 case PIPE_FORMAT_R32G32B32A32_SNORM:
359 case PIPE_FORMAT_R32G32B32A32_UNORM:
360 case PIPE_FORMAT_R32G32B32A32_SINT:
361 case PIPE_FORMAT_R32G32B32A32_UINT:
362 return V_028C70_SWAP_STD;
363 default:
364 R600_ERR("unsupported colorswap format %d\n", format);
365 return ~0U;
366 }
367 return ~0U;
368 }
369
370 static uint32_t r600_translate_colorformat(enum pipe_format format)
371 {
372 switch (format) {
373 /* 8-bit buffers. */
374 case PIPE_FORMAT_A8_UNORM:
375 case PIPE_FORMAT_A8_SNORM:
376 case PIPE_FORMAT_A8_UINT:
377 case PIPE_FORMAT_A8_SINT:
378 case PIPE_FORMAT_I8_UNORM:
379 case PIPE_FORMAT_I8_SNORM:
380 case PIPE_FORMAT_I8_UINT:
381 case PIPE_FORMAT_I8_SINT:
382 case PIPE_FORMAT_L8_UNORM:
383 case PIPE_FORMAT_L8_SNORM:
384 case PIPE_FORMAT_L8_UINT:
385 case PIPE_FORMAT_L8_SINT:
386 case PIPE_FORMAT_L8_SRGB:
387 case PIPE_FORMAT_R8_UNORM:
388 case PIPE_FORMAT_R8_SNORM:
389 case PIPE_FORMAT_R8_UINT:
390 case PIPE_FORMAT_R8_SINT:
391 return V_028C70_COLOR_8;
392
393 /* 16-bit buffers. */
394 case PIPE_FORMAT_B5G6R5_UNORM:
395 return V_028C70_COLOR_5_6_5;
396
397 case PIPE_FORMAT_B5G5R5A1_UNORM:
398 case PIPE_FORMAT_B5G5R5X1_UNORM:
399 return V_028C70_COLOR_1_5_5_5;
400
401 case PIPE_FORMAT_B4G4R4A4_UNORM:
402 case PIPE_FORMAT_B4G4R4X4_UNORM:
403 return V_028C70_COLOR_4_4_4_4;
404
405 case PIPE_FORMAT_Z16_UNORM:
406 return V_028C70_COLOR_16;
407
408 case PIPE_FORMAT_L8A8_UNORM:
409 case PIPE_FORMAT_L8A8_SNORM:
410 case PIPE_FORMAT_L8A8_UINT:
411 case PIPE_FORMAT_L8A8_SINT:
412 case PIPE_FORMAT_L8A8_SRGB:
413 case PIPE_FORMAT_R8G8_UNORM:
414 case PIPE_FORMAT_R8G8_SNORM:
415 case PIPE_FORMAT_R8G8_UINT:
416 case PIPE_FORMAT_R8G8_SINT:
417 return V_028C70_COLOR_8_8;
418
419 case PIPE_FORMAT_R16_UNORM:
420 case PIPE_FORMAT_R16_SNORM:
421 case PIPE_FORMAT_R16_UINT:
422 case PIPE_FORMAT_R16_SINT:
423 case PIPE_FORMAT_A16_UNORM:
424 case PIPE_FORMAT_A16_SNORM:
425 case PIPE_FORMAT_A16_UINT:
426 case PIPE_FORMAT_A16_SINT:
427 case PIPE_FORMAT_L16_UNORM:
428 case PIPE_FORMAT_L16_SNORM:
429 case PIPE_FORMAT_L16_UINT:
430 case PIPE_FORMAT_L16_SINT:
431 case PIPE_FORMAT_I16_UNORM:
432 case PIPE_FORMAT_I16_SNORM:
433 case PIPE_FORMAT_I16_UINT:
434 case PIPE_FORMAT_I16_SINT:
435 return V_028C70_COLOR_16;
436
437 case PIPE_FORMAT_R16_FLOAT:
438 case PIPE_FORMAT_A16_FLOAT:
439 case PIPE_FORMAT_L16_FLOAT:
440 case PIPE_FORMAT_I16_FLOAT:
441 return V_028C70_COLOR_16_FLOAT;
442
443 /* 32-bit buffers. */
444 case PIPE_FORMAT_A8B8G8R8_SRGB:
445 case PIPE_FORMAT_A8B8G8R8_UNORM:
446 case PIPE_FORMAT_A8R8G8B8_UNORM:
447 case PIPE_FORMAT_B8G8R8A8_SRGB:
448 case PIPE_FORMAT_B8G8R8A8_UNORM:
449 case PIPE_FORMAT_B8G8R8X8_UNORM:
450 case PIPE_FORMAT_R8G8B8A8_SNORM:
451 case PIPE_FORMAT_R8G8B8A8_UNORM:
452 case PIPE_FORMAT_R8G8B8X8_UNORM:
453 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
454 case PIPE_FORMAT_X8B8G8R8_UNORM:
455 case PIPE_FORMAT_X8R8G8B8_UNORM:
456 case PIPE_FORMAT_R8G8B8_UNORM:
457 case PIPE_FORMAT_R8G8B8A8_SINT:
458 case PIPE_FORMAT_R8G8B8A8_UINT:
459 return V_028C70_COLOR_8_8_8_8;
460
461 case PIPE_FORMAT_R10G10B10A2_UNORM:
462 case PIPE_FORMAT_R10G10B10X2_SNORM:
463 case PIPE_FORMAT_B10G10R10A2_UNORM:
464 case PIPE_FORMAT_B10G10R10A2_UINT:
465 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
466 return V_028C70_COLOR_2_10_10_10;
467
468 case PIPE_FORMAT_Z24X8_UNORM:
469 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
470 return V_028C70_COLOR_8_24;
471
472 case PIPE_FORMAT_X8Z24_UNORM:
473 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
474 return V_028C70_COLOR_24_8;
475
476 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
477 return V_028C70_COLOR_X24_8_32_FLOAT;
478
479 case PIPE_FORMAT_R32_UINT:
480 case PIPE_FORMAT_R32_SINT:
481 case PIPE_FORMAT_A32_UINT:
482 case PIPE_FORMAT_A32_SINT:
483 case PIPE_FORMAT_L32_UINT:
484 case PIPE_FORMAT_L32_SINT:
485 case PIPE_FORMAT_I32_UINT:
486 case PIPE_FORMAT_I32_SINT:
487 return V_028C70_COLOR_32;
488
489 case PIPE_FORMAT_R32_FLOAT:
490 case PIPE_FORMAT_A32_FLOAT:
491 case PIPE_FORMAT_L32_FLOAT:
492 case PIPE_FORMAT_I32_FLOAT:
493 case PIPE_FORMAT_Z32_FLOAT:
494 return V_028C70_COLOR_32_FLOAT;
495
496 case PIPE_FORMAT_R16G16_FLOAT:
497 case PIPE_FORMAT_L16A16_FLOAT:
498 return V_028C70_COLOR_16_16_FLOAT;
499
500 case PIPE_FORMAT_R16G16_UNORM:
501 case PIPE_FORMAT_R16G16_SNORM:
502 case PIPE_FORMAT_R16G16_UINT:
503 case PIPE_FORMAT_R16G16_SINT:
504 case PIPE_FORMAT_L16A16_UNORM:
505 case PIPE_FORMAT_L16A16_SNORM:
506 case PIPE_FORMAT_L16A16_UINT:
507 case PIPE_FORMAT_L16A16_SINT:
508 return V_028C70_COLOR_16_16;
509
510 case PIPE_FORMAT_R11G11B10_FLOAT:
511 return V_028C70_COLOR_10_11_11_FLOAT;
512
513 /* 64-bit buffers. */
514 case PIPE_FORMAT_R16G16B16A16_UINT:
515 case PIPE_FORMAT_R16G16B16A16_SINT:
516 case PIPE_FORMAT_R16G16B16A16_UNORM:
517 case PIPE_FORMAT_R16G16B16A16_SNORM:
518 return V_028C70_COLOR_16_16_16_16;
519
520 case PIPE_FORMAT_R16G16B16A16_FLOAT:
521 return V_028C70_COLOR_16_16_16_16_FLOAT;
522
523 case PIPE_FORMAT_R32G32_FLOAT:
524 case PIPE_FORMAT_L32A32_FLOAT:
525 return V_028C70_COLOR_32_32_FLOAT;
526
527 case PIPE_FORMAT_R32G32_SINT:
528 case PIPE_FORMAT_R32G32_UINT:
529 case PIPE_FORMAT_L32A32_UINT:
530 case PIPE_FORMAT_L32A32_SINT:
531 return V_028C70_COLOR_32_32;
532
533 /* 128-bit buffers. */
534 case PIPE_FORMAT_R32G32B32A32_SNORM:
535 case PIPE_FORMAT_R32G32B32A32_UNORM:
536 case PIPE_FORMAT_R32G32B32A32_SINT:
537 case PIPE_FORMAT_R32G32B32A32_UINT:
538 return V_028C70_COLOR_32_32_32_32;
539 case PIPE_FORMAT_R32G32B32A32_FLOAT:
540 return V_028C70_COLOR_32_32_32_32_FLOAT;
541
542 /* YUV buffers. */
543 case PIPE_FORMAT_UYVY:
544 case PIPE_FORMAT_YUYV:
545 default:
546 return ~0U; /* Unsupported. */
547 }
548 }
549
550 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
551 {
552 if (R600_BIG_ENDIAN) {
553 switch(colorformat) {
554
555 /* 8-bit buffers. */
556 case V_028C70_COLOR_8:
557 return ENDIAN_NONE;
558
559 /* 16-bit buffers. */
560 case V_028C70_COLOR_5_6_5:
561 case V_028C70_COLOR_1_5_5_5:
562 case V_028C70_COLOR_4_4_4_4:
563 case V_028C70_COLOR_16:
564 case V_028C70_COLOR_8_8:
565 return ENDIAN_8IN16;
566
567 /* 32-bit buffers. */
568 case V_028C70_COLOR_8_8_8_8:
569 case V_028C70_COLOR_2_10_10_10:
570 case V_028C70_COLOR_8_24:
571 case V_028C70_COLOR_24_8:
572 case V_028C70_COLOR_32_FLOAT:
573 case V_028C70_COLOR_16_16_FLOAT:
574 case V_028C70_COLOR_16_16:
575 return ENDIAN_8IN32;
576
577 /* 64-bit buffers. */
578 case V_028C70_COLOR_16_16_16_16:
579 case V_028C70_COLOR_16_16_16_16_FLOAT:
580 return ENDIAN_8IN16;
581
582 case V_028C70_COLOR_32_32_FLOAT:
583 case V_028C70_COLOR_32_32:
584 case V_028C70_COLOR_X24_8_32_FLOAT:
585 return ENDIAN_8IN32;
586
587 /* 96-bit buffers. */
588 case V_028C70_COLOR_32_32_32_FLOAT:
589 /* 128-bit buffers. */
590 case V_028C70_COLOR_32_32_32_32_FLOAT:
591 case V_028C70_COLOR_32_32_32_32:
592 return ENDIAN_8IN32;
593 default:
594 return ENDIAN_NONE; /* Unsupported. */
595 }
596 } else {
597 return ENDIAN_NONE;
598 }
599 }
600
601 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
602 {
603 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
604 }
605
606 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
607 {
608 return r600_translate_colorformat(format) != ~0U &&
609 r600_translate_colorswap(format) != ~0U;
610 }
611
612 static bool r600_is_zs_format_supported(enum pipe_format format)
613 {
614 return r600_translate_dbformat(format) != ~0U;
615 }
616
617 boolean evergreen_is_format_supported(struct pipe_screen *screen,
618 enum pipe_format format,
619 enum pipe_texture_target target,
620 unsigned sample_count,
621 unsigned usage)
622 {
623 struct r600_screen *rscreen = (struct r600_screen*)screen;
624 unsigned retval = 0;
625
626 if (target >= PIPE_MAX_TEXTURE_TYPES) {
627 R600_ERR("r600: unsupported texture type %d\n", target);
628 return FALSE;
629 }
630
631 if (!util_format_is_supported(format, usage))
632 return FALSE;
633
634 if (sample_count > 1) {
635 if (rscreen->info.drm_minor < 19)
636 return FALSE;
637
638 switch (sample_count) {
639 case 2:
640 case 4:
641 case 8:
642 break;
643 default:
644 return FALSE;
645 }
646 }
647
648 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
649 r600_is_sampler_format_supported(screen, format)) {
650 retval |= PIPE_BIND_SAMPLER_VIEW;
651 }
652
653 if ((usage & (PIPE_BIND_RENDER_TARGET |
654 PIPE_BIND_DISPLAY_TARGET |
655 PIPE_BIND_SCANOUT |
656 PIPE_BIND_SHARED)) &&
657 r600_is_colorbuffer_format_supported(format)) {
658 retval |= usage &
659 (PIPE_BIND_RENDER_TARGET |
660 PIPE_BIND_DISPLAY_TARGET |
661 PIPE_BIND_SCANOUT |
662 PIPE_BIND_SHARED);
663 }
664
665 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
666 r600_is_zs_format_supported(format)) {
667 retval |= PIPE_BIND_DEPTH_STENCIL;
668 }
669
670 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
671 r600_is_vertex_format_supported(format)) {
672 retval |= PIPE_BIND_VERTEX_BUFFER;
673 }
674
675 if (usage & PIPE_BIND_TRANSFER_READ)
676 retval |= PIPE_BIND_TRANSFER_READ;
677 if (usage & PIPE_BIND_TRANSFER_WRITE)
678 retval |= PIPE_BIND_TRANSFER_WRITE;
679
680 return retval == usage;
681 }
682
683 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
684 const struct pipe_blend_state *state, int mode)
685 {
686 struct r600_context *rctx = (struct r600_context *)ctx;
687 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
688 struct r600_pipe_state *rstate;
689 uint32_t color_control = 0, target_mask;
690 /* XXX there is more then 8 framebuffer */
691 unsigned blend_cntl[8];
692
693 if (blend == NULL) {
694 return NULL;
695 }
696
697 rstate = &blend->rstate;
698
699 rstate->id = R600_PIPE_STATE_BLEND;
700
701 target_mask = 0;
702 if (state->logicop_enable) {
703 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
704 } else {
705 color_control |= (0xcc << 16);
706 }
707 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
708 if (state->independent_blend_enable) {
709 for (int i = 0; i < 8; i++) {
710 target_mask |= (state->rt[i].colormask << (4 * i));
711 }
712 } else {
713 for (int i = 0; i < 8; i++) {
714 target_mask |= (state->rt[0].colormask << (4 * i));
715 }
716 }
717 blend->cb_target_mask = target_mask;
718
719 if (target_mask)
720 color_control |= S_028808_MODE(mode);
721 else
722 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
723
724 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
725 color_control);
726 /* only have dual source on MRT0 */
727 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
728 for (int i = 0; i < 8; i++) {
729 /* state->rt entries > 0 only written if independent blending */
730 const int j = state->independent_blend_enable ? i : 0;
731
732 unsigned eqRGB = state->rt[j].rgb_func;
733 unsigned srcRGB = state->rt[j].rgb_src_factor;
734 unsigned dstRGB = state->rt[j].rgb_dst_factor;
735 unsigned eqA = state->rt[j].alpha_func;
736 unsigned srcA = state->rt[j].alpha_src_factor;
737 unsigned dstA = state->rt[j].alpha_dst_factor;
738
739 blend_cntl[i] = 0;
740 if (!state->rt[j].blend_enable)
741 continue;
742
743 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
744 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
745 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
746 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
747
748 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
749 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
750 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
751 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
752 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
753 }
754 }
755 for (int i = 0; i < 8; i++) {
756 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
757 }
758
759 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK,
760 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
761 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
762 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
763 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
764 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
765
766 blend->alpha_to_one = state->alpha_to_one;
767 return rstate;
768 }
769
770 static void *evergreen_create_blend_state(struct pipe_context *ctx,
771 const struct pipe_blend_state *state)
772 {
773
774 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
775 }
776
777 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
778 const struct pipe_depth_stencil_alpha_state *state)
779 {
780 struct r600_context *rctx = (struct r600_context *)ctx;
781 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
782 unsigned db_depth_control, alpha_test_control, alpha_ref;
783 struct r600_pipe_state *rstate;
784
785 if (dsa == NULL) {
786 return NULL;
787 }
788
789 dsa->valuemask[0] = state->stencil[0].valuemask;
790 dsa->valuemask[1] = state->stencil[1].valuemask;
791 dsa->writemask[0] = state->stencil[0].writemask;
792 dsa->writemask[1] = state->stencil[1].writemask;
793
794 rstate = &dsa->rstate;
795
796 rstate->id = R600_PIPE_STATE_DSA;
797 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
798 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
799 S_028800_ZFUNC(state->depth.func);
800
801 /* stencil */
802 if (state->stencil[0].enabled) {
803 db_depth_control |= S_028800_STENCIL_ENABLE(1);
804 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
805 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
806 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
807 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
808
809 if (state->stencil[1].enabled) {
810 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
811 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
812 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
813 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
814 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
815 }
816 }
817
818 /* alpha */
819 alpha_test_control = 0;
820 alpha_ref = 0;
821 if (state->alpha.enabled) {
822 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
823 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
824 alpha_ref = fui(state->alpha.ref_value);
825 }
826 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
827 dsa->alpha_ref = alpha_ref;
828
829 /* misc */
830 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
831 return rstate;
832 }
833
834 static void *evergreen_create_rs_state(struct pipe_context *ctx,
835 const struct pipe_rasterizer_state *state)
836 {
837 struct r600_context *rctx = (struct r600_context *)ctx;
838 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
839 struct r600_pipe_state *rstate;
840 unsigned tmp;
841 unsigned prov_vtx = 1, polygon_dual_mode;
842 float psize_min, psize_max;
843
844 if (rs == NULL) {
845 return NULL;
846 }
847
848 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
849 state->fill_back != PIPE_POLYGON_MODE_FILL);
850
851 if (state->flatshade_first)
852 prov_vtx = 0;
853
854 rstate = &rs->rstate;
855 rs->flatshade = state->flatshade;
856 rs->sprite_coord_enable = state->sprite_coord_enable;
857 rs->two_side = state->light_twoside;
858 rs->clip_plane_enable = state->clip_plane_enable;
859 rs->pa_sc_line_stipple = state->line_stipple_enable ?
860 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
861 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
862 rs->pa_cl_clip_cntl =
863 S_028810_PS_UCP_MODE(3) |
864 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
865 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
866 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
867 rs->multisample_enable = state->multisample;
868
869 /* offset */
870 rs->offset_units = state->offset_units;
871 rs->offset_scale = state->offset_scale * 12.0f;
872
873 rstate->id = R600_PIPE_STATE_RASTERIZER;
874 tmp = S_0286D4_FLAT_SHADE_ENA(1);
875 if (state->sprite_coord_enable) {
876 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
877 S_0286D4_PNT_SPRITE_OVRD_X(2) |
878 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
879 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
880 S_0286D4_PNT_SPRITE_OVRD_W(1);
881 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
882 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
883 }
884 }
885 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
886
887 /* point size 12.4 fixed point */
888 tmp = (unsigned)(state->point_size * 8.0);
889 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
890
891 if (state->point_size_per_vertex) {
892 psize_min = util_get_min_point_size(state);
893 psize_max = 8192;
894 } else {
895 /* Force the point size to be as if the vertex output was disabled. */
896 psize_min = state->point_size;
897 psize_max = state->point_size;
898 }
899 /* Divide by two, because 0.5 = 1 pixel. */
900 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
901 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
902 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
903
904 tmp = (unsigned)state->line_width * 8;
905 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
906 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
907 S_028A48_MSAA_ENABLE(state->multisample) |
908 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
909 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
910
911 if (rctx->chip_class == CAYMAN) {
912 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
913 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
914 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
915 } else {
916 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
917 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
918 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
919 }
920 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
921 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
922 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
923 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
924 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
925 S_028814_FACE(!state->front_ccw) |
926 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
927 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
928 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
929 S_028814_POLY_MODE(polygon_dual_mode) |
930 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
931 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
932 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
933 return rstate;
934 }
935
936 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
937 const struct pipe_sampler_state *state)
938 {
939 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
940 union util_color uc;
941 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
942
943 if (ss == NULL) {
944 return NULL;
945 }
946
947 /* directly into sampler avoid r6xx code to emit useless reg */
948 ss->seamless_cube_map = false;
949 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
950 ss->border_color_use = false;
951 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
952 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
953 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
954 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
955 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
956 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
957 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
958 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
959 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
960 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
961 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
962 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
963 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
964 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
965 ss->tex_sampler_words[2] = S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
966 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
967 S_03C008_TYPE(1);
968 if (uc.ui) {
969 ss->border_color_use = true;
970 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
971 ss->border_color[0] = fui(state->border_color.f[0]);
972 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
973 ss->border_color[1] = fui(state->border_color.f[1]);
974 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
975 ss->border_color[2] = fui(state->border_color.f[2]);
976 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
977 ss->border_color[3] = fui(state->border_color.f[3]);
978 }
979 return ss;
980 }
981
982 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
983 struct pipe_resource *texture,
984 const struct pipe_sampler_view *state)
985 {
986 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
987 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
988 struct r600_texture *tmp = (struct r600_texture*)texture;
989 unsigned format, endian;
990 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
991 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
992 unsigned height, depth, width;
993 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
994
995 if (view == NULL)
996 return NULL;
997
998 /* initialize base object */
999 view->base = *state;
1000 view->base.texture = NULL;
1001 pipe_reference(NULL, &texture->reference);
1002 view->base.texture = texture;
1003 view->base.reference.count = 1;
1004 view->base.context = ctx;
1005
1006 swizzle[0] = state->swizzle_r;
1007 swizzle[1] = state->swizzle_g;
1008 swizzle[2] = state->swizzle_b;
1009 swizzle[3] = state->swizzle_a;
1010
1011 format = r600_translate_texformat(ctx->screen, state->format,
1012 swizzle,
1013 &word4, &yuv_format);
1014 assert(format != ~0);
1015 if (format == ~0) {
1016 FREE(view);
1017 return NULL;
1018 }
1019
1020 if (tmp->is_depth && !tmp->is_flushing_texture) {
1021 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1022 FREE(view);
1023 return NULL;
1024 }
1025 tmp = tmp->flushed_depth_texture;
1026 }
1027
1028 endian = r600_colorformat_endian_swap(format);
1029
1030 width = tmp->surface.level[0].npix_x;
1031 height = tmp->surface.level[0].npix_y;
1032 depth = tmp->surface.level[0].npix_z;
1033 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1034 tile_type = tmp->tile_type;
1035
1036 switch (tmp->surface.level[0].mode) {
1037 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1038 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1039 break;
1040 case RADEON_SURF_MODE_2D:
1041 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1042 break;
1043 case RADEON_SURF_MODE_1D:
1044 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1045 break;
1046 case RADEON_SURF_MODE_LINEAR:
1047 default:
1048 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1049 break;
1050 }
1051 tile_split = tmp->surface.tile_split;
1052 macro_aspect = tmp->surface.mtilea;
1053 bankw = tmp->surface.bankw;
1054 bankh = tmp->surface.bankh;
1055 tile_split = eg_tile_split(tile_split);
1056 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1057 bankw = eg_bank_wh(bankw);
1058 bankh = eg_bank_wh(bankh);
1059
1060 /* 128 bit formats require tile type = 1 */
1061 if (rscreen->chip_class == CAYMAN) {
1062 if (util_format_get_blocksize(state->format) >= 16)
1063 tile_type = 1;
1064 }
1065 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1066
1067 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1068 height = 1;
1069 depth = texture->array_size;
1070 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1071 depth = texture->array_size;
1072 }
1073
1074 view->tex_resource = &tmp->resource;
1075 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1076 S_030000_PITCH((pitch / 8) - 1) |
1077 S_030000_TEX_WIDTH(width - 1));
1078 if (rscreen->chip_class == CAYMAN)
1079 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1080 else
1081 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1082 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1083 S_030004_TEX_DEPTH(depth - 1) |
1084 S_030004_ARRAY_MODE(array_mode));
1085 view->tex_resource_words[2] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1086 if (state->u.tex.last_level && texture->nr_samples <= 1) {
1087 view->tex_resource_words[3] = (tmp->surface.level[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1088 } else {
1089 view->tex_resource_words[3] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1090 }
1091 view->tex_resource_words[4] = (word4 |
1092 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1093 S_030010_ENDIAN_SWAP(endian));
1094 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1095 S_030014_LAST_ARRAY(state->u.tex.last_layer);
1096 if (texture->nr_samples > 1) {
1097 unsigned log_samples = util_logbase2(texture->nr_samples);
1098 if (rscreen->chip_class == CAYMAN) {
1099 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
1100 }
1101 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1102 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
1103 } else {
1104 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(state->u.tex.first_level);
1105 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(state->u.tex.last_level);
1106 }
1107 /* aniso max 16 samples */
1108 view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
1109 (S_030018_TILE_SPLIT(tile_split));
1110 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1111 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1112 S_03001C_BANK_WIDTH(bankw) |
1113 S_03001C_BANK_HEIGHT(bankh) |
1114 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1115 S_03001C_NUM_BANKS(nbanks);
1116 return &view->base;
1117 }
1118
1119 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1120 {
1121 struct radeon_winsys_cs *cs = rctx->cs;
1122 struct pipe_clip_state *state = &rctx->clip_state.state;
1123
1124 r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
1125 r600_write_array(cs, 6*4, (unsigned*)state);
1126 }
1127
1128 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1129 const struct pipe_poly_stipple *state)
1130 {
1131 }
1132
1133 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1134 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1135 uint32_t *tl, uint32_t *br)
1136 {
1137 /* EG hw workaround */
1138 if (br_x == 0)
1139 tl_x = 1;
1140 if (br_y == 0)
1141 tl_y = 1;
1142
1143 /* cayman hw workaround */
1144 if (rctx->chip_class == CAYMAN) {
1145 if (br_x == 1 && br_y == 1)
1146 br_x = 2;
1147 }
1148
1149 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1150 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1151 }
1152
1153 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1154 const struct pipe_scissor_state *state)
1155 {
1156 struct r600_context *rctx = (struct r600_context *)ctx;
1157 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1158 uint32_t tl, br;
1159
1160 if (rstate == NULL)
1161 return;
1162
1163 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1164
1165 rstate->id = R600_PIPE_STATE_SCISSOR;
1166 r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1167 r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1168
1169 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1170 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1171 r600_context_pipe_state_set(rctx, rstate);
1172 }
1173
1174 void evergreen_init_color_surface(struct r600_context *rctx,
1175 struct r600_surface *surf)
1176 {
1177 struct r600_screen *rscreen = rctx->screen;
1178 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1179 struct pipe_resource *pipe_tex = surf->base.texture;
1180 unsigned level = surf->base.u.tex.level;
1181 unsigned pitch, slice;
1182 unsigned color_info, color_attrib, color_dim = 0;
1183 unsigned format, swap, ntype, endian;
1184 uint64_t offset, base_offset;
1185 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1186 const struct util_format_description *desc;
1187 int i;
1188 bool blend_clamp = 0, blend_bypass = 0;
1189
1190 if (rtex->is_depth && !rtex->is_flushing_texture) {
1191 r600_init_flushed_depth_texture(&rctx->context, pipe_tex, NULL);
1192 rtex = rtex->flushed_depth_texture;
1193 assert(rtex);
1194 }
1195
1196 offset = rtex->surface.level[level].offset;
1197 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1198 offset += rtex->surface.level[level].slice_size *
1199 surf->base.u.tex.first_layer;
1200 }
1201 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1202 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1203 if (slice) {
1204 slice = slice - 1;
1205 }
1206 color_info = 0;
1207 switch (rtex->surface.level[level].mode) {
1208 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1209 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1210 tile_type = 1;
1211 break;
1212 case RADEON_SURF_MODE_1D:
1213 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1214 tile_type = rtex->tile_type;
1215 break;
1216 case RADEON_SURF_MODE_2D:
1217 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1218 tile_type = rtex->tile_type;
1219 break;
1220 case RADEON_SURF_MODE_LINEAR:
1221 default:
1222 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1223 tile_type = 1;
1224 break;
1225 }
1226 tile_split = rtex->surface.tile_split;
1227 macro_aspect = rtex->surface.mtilea;
1228 bankw = rtex->surface.bankw;
1229 bankh = rtex->surface.bankh;
1230 fmask_bankh = rtex->fmask_bank_height;
1231 tile_split = eg_tile_split(tile_split);
1232 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1233 bankw = eg_bank_wh(bankw);
1234 bankh = eg_bank_wh(bankh);
1235 fmask_bankh = eg_bank_wh(fmask_bankh);
1236
1237 /* 128 bit formats require tile type = 1 */
1238 if (rscreen->chip_class == CAYMAN) {
1239 if (util_format_get_blocksize(surf->base.format) >= 16)
1240 tile_type = 1;
1241 }
1242 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1243 desc = util_format_description(surf->base.format);
1244 for (i = 0; i < 4; i++) {
1245 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1246 break;
1247 }
1248 }
1249
1250 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1251 S_028C74_NUM_BANKS(nbanks) |
1252 S_028C74_BANK_WIDTH(bankw) |
1253 S_028C74_BANK_HEIGHT(bankh) |
1254 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1255 S_028C74_NON_DISP_TILING_ORDER(tile_type) |
1256 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1257
1258 if (rctx->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1259 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1260 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1261 S_028C74_NUM_FRAGMENTS(log_samples);
1262 }
1263
1264 ntype = V_028C70_NUMBER_UNORM;
1265 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1266 ntype = V_028C70_NUMBER_SRGB;
1267 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1268 if (desc->channel[i].normalized)
1269 ntype = V_028C70_NUMBER_SNORM;
1270 else if (desc->channel[i].pure_integer)
1271 ntype = V_028C70_NUMBER_SINT;
1272 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1273 if (desc->channel[i].normalized)
1274 ntype = V_028C70_NUMBER_UNORM;
1275 else if (desc->channel[i].pure_integer)
1276 ntype = V_028C70_NUMBER_UINT;
1277 }
1278
1279 format = r600_translate_colorformat(surf->base.format);
1280 assert(format != ~0);
1281
1282 swap = r600_translate_colorswap(surf->base.format);
1283 assert(swap != ~0);
1284
1285 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1286 endian = ENDIAN_NONE;
1287 } else {
1288 endian = r600_colorformat_endian_swap(format);
1289 }
1290
1291 /* blend clamp should be set for all NORM/SRGB types */
1292 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1293 ntype == V_028C70_NUMBER_SRGB)
1294 blend_clamp = 1;
1295
1296 /* set blend bypass according to docs if SINT/UINT or
1297 8/24 COLOR variants */
1298 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1299 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1300 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1301 blend_clamp = 0;
1302 blend_bypass = 1;
1303 }
1304
1305 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1306
1307 color_info |= S_028C70_FORMAT(format) |
1308 S_028C70_COMP_SWAP(swap) |
1309 S_028C70_BLEND_CLAMP(blend_clamp) |
1310 S_028C70_BLEND_BYPASS(blend_bypass) |
1311 S_028C70_NUMBER_TYPE(ntype) |
1312 S_028C70_ENDIAN(endian);
1313
1314 if (rtex->is_rat) {
1315 color_info |= S_028C70_RAT(1);
1316 color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0 & 0xffff)
1317 | S_028C78_HEIGHT_MAX((pipe_tex->width0 >> 16) & 0xffff);
1318 }
1319
1320 /* EXPORT_NORM is an optimzation that can be enabled for better
1321 * performance in certain cases.
1322 * EXPORT_NORM can be enabled if:
1323 * - 11-bit or smaller UNORM/SNORM/SRGB
1324 * - 16-bit or smaller FLOAT
1325 */
1326 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1327 ((desc->channel[i].size < 12 &&
1328 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1329 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1330 (desc->channel[i].size < 17 &&
1331 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1332 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1333 surf->export_16bpc = true;
1334 }
1335
1336 if (rtex->fmask_size && rtex->cmask_size) {
1337 color_info |= S_028C70_COMPRESSION(1) | S_028C70_FAST_CLEAR(1);
1338 }
1339
1340 base_offset = r600_resource_va(rctx->context.screen, pipe_tex);
1341
1342 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1343 surf->cb_color_base = (base_offset + offset) >> 8;
1344 surf->cb_color_dim = color_dim;
1345 surf->cb_color_info = color_info;
1346 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1347 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1348 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1349 surf->cb_color_view = 0;
1350 } else {
1351 surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1352 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1353 }
1354 surf->cb_color_attrib = color_attrib;
1355 if (rtex->fmask_size && rtex->cmask_size) {
1356 surf->cb_color_fmask = (base_offset + rtex->fmask_offset) >> 8;
1357 surf->cb_color_cmask = (base_offset + rtex->cmask_offset) >> 8;
1358 } else {
1359 surf->cb_color_fmask = surf->cb_color_base;
1360 surf->cb_color_cmask = surf->cb_color_base;
1361 }
1362 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1363 surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask_slice_tile_max);
1364
1365 surf->color_initialized = true;
1366 }
1367
1368 static void evergreen_init_depth_surface(struct r600_context *rctx,
1369 struct r600_surface *surf)
1370 {
1371 struct r600_screen *rscreen = rctx->screen;
1372 struct pipe_screen *screen = &rscreen->screen;
1373 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1374 uint64_t offset;
1375 unsigned level, pitch, slice, format, array_mode;
1376 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1377
1378 level = surf->base.u.tex.level;
1379 format = r600_translate_dbformat(surf->base.format);
1380 assert(format != ~0);
1381
1382 offset = r600_resource_va(screen, surf->base.texture);
1383 offset += rtex->surface.level[level].offset;
1384 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1385 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1386 if (slice) {
1387 slice = slice - 1;
1388 }
1389 switch (rtex->surface.level[level].mode) {
1390 case RADEON_SURF_MODE_2D:
1391 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1392 break;
1393 case RADEON_SURF_MODE_1D:
1394 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1395 case RADEON_SURF_MODE_LINEAR:
1396 default:
1397 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1398 break;
1399 }
1400 tile_split = rtex->surface.tile_split;
1401 macro_aspect = rtex->surface.mtilea;
1402 bankw = rtex->surface.bankw;
1403 bankh = rtex->surface.bankh;
1404 tile_split = eg_tile_split(tile_split);
1405 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1406 bankw = eg_bank_wh(bankw);
1407 bankh = eg_bank_wh(bankh);
1408 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1409 offset >>= 8;
1410
1411 surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1412 S_028040_FORMAT(format) |
1413 S_028040_TILE_SPLIT(tile_split)|
1414 S_028040_NUM_BANKS(nbanks) |
1415 S_028040_BANK_WIDTH(bankw) |
1416 S_028040_BANK_HEIGHT(bankh) |
1417 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1418 if (rscreen->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1419 surf->db_depth_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1420 }
1421 surf->db_depth_base = offset;
1422 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1423 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1424 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1425 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1426
1427 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1428 uint64_t stencil_offset = rtex->surface.stencil_offset;
1429 unsigned stile_split = rtex->surface.stencil_tile_split;
1430
1431 stile_split = eg_tile_split(stile_split);
1432 stencil_offset += r600_resource_va(screen, surf->base.texture);
1433 stencil_offset += rtex->surface.level[level].offset / 4;
1434 stencil_offset >>= 8;
1435
1436 surf->db_stencil_base = stencil_offset;
1437 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1438 S_028044_TILE_SPLIT(stile_split);
1439 } else {
1440 surf->db_stencil_base = offset;
1441 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1442 * Older kernels are out of luck. */
1443 surf->db_stencil_info = rctx->screen->info.drm_minor >= 18 ?
1444 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1445 S_028044_FORMAT(V_028044_STENCIL_8);
1446 }
1447
1448 surf->depth_initialized = true;
1449 }
1450
1451 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1452 const struct pipe_framebuffer_state *state)
1453 {
1454 struct r600_context *rctx = (struct r600_context *)ctx;
1455 struct r600_surface *surf;
1456 struct r600_texture *rtex;
1457 uint32_t i, log_samples;
1458
1459 if (rctx->framebuffer.state.nr_cbufs) {
1460 rctx->flags |= R600_CONTEXT_CB_FLUSH;
1461
1462 if (rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1463 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1464 }
1465 }
1466 if (rctx->framebuffer.state.zsbuf) {
1467 rctx->flags |= R600_CONTEXT_DB_FLUSH;
1468 }
1469
1470 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1471
1472 /* Colorbuffers. */
1473 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1474 rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1475 util_format_is_pure_integer(state->cbufs[0]->format);
1476 rctx->framebuffer.compressed_cb_mask = 0;
1477
1478 if (state->nr_cbufs)
1479 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1480 else if (state->zsbuf)
1481 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1482 else
1483 rctx->framebuffer.nr_samples = 0;
1484
1485 for (i = 0; i < state->nr_cbufs; i++) {
1486 surf = (struct r600_surface*)state->cbufs[i];
1487 rtex = (struct r600_texture*)surf->base.texture;
1488
1489 if (!surf->color_initialized) {
1490 evergreen_init_color_surface(rctx, surf);
1491 }
1492
1493 if (!surf->export_16bpc) {
1494 rctx->framebuffer.export_16bpc = false;
1495 }
1496
1497 /* Cayman can fetch from a compressed MSAA colorbuffer,
1498 * so it's pointless to track them. */
1499 if (rctx->chip_class != CAYMAN && rtex->fmask_size && rtex->cmask_size) {
1500 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1501 }
1502 }
1503
1504 /* Update alpha-test state dependencies.
1505 * Alpha-test is done on the first colorbuffer only. */
1506 if (state->nr_cbufs) {
1507 surf = (struct r600_surface*)state->cbufs[0];
1508 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1509 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1510 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1511 }
1512 if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
1513 rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
1514 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1515 }
1516 }
1517
1518 /* ZS buffer. */
1519 if (state->zsbuf) {
1520 surf = (struct r600_surface*)state->zsbuf;
1521
1522 if (!surf->depth_initialized) {
1523 evergreen_init_depth_surface(rctx, surf);
1524 }
1525
1526 evergreen_polygon_offset_update(rctx);
1527 }
1528
1529 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1530 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1531 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1532 }
1533
1534 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1535 rctx->alphatest_state.bypass = false;
1536 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1537 }
1538
1539 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1540 if (rctx->chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) {
1541 rctx->db_misc_state.log_samples = log_samples;
1542 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1543 }
1544
1545 /* Calculate the CS size. */
1546 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1547
1548 /* MSAA. */
1549 if (rctx->chip_class == EVERGREEN) {
1550 switch (rctx->framebuffer.nr_samples) {
1551 case 2:
1552 case 4:
1553 rctx->framebuffer.atom.num_dw += 6;
1554 break;
1555 case 8:
1556 rctx->framebuffer.atom.num_dw += 10;
1557 break;
1558 }
1559 rctx->framebuffer.atom.num_dw += 4;
1560 } else {
1561 switch (rctx->framebuffer.nr_samples) {
1562 case 2:
1563 case 4:
1564 rctx->framebuffer.atom.num_dw += 12;
1565 break;
1566 case 8:
1567 rctx->framebuffer.atom.num_dw += 16;
1568 break;
1569 case 16:
1570 rctx->framebuffer.atom.num_dw += 18;
1571 break;
1572 }
1573 rctx->framebuffer.atom.num_dw += 7;
1574 }
1575
1576 /* Colorbuffers. */
1577 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 21;
1578 if (rctx->keep_tiling_flags)
1579 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1580 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1581
1582 /* ZS buffer. */
1583 if (state->zsbuf) {
1584 rctx->framebuffer.atom.num_dw += 21;
1585 if (rctx->keep_tiling_flags)
1586 rctx->framebuffer.atom.num_dw += 2;
1587 } else if (rctx->screen->info.drm_minor >= 18) {
1588 rctx->framebuffer.atom.num_dw += 4;
1589 }
1590
1591 r600_atom_dirty(rctx, &rctx->framebuffer.atom);
1592 }
1593
1594 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1595 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1596 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1597 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1598 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1599
1600 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1601 {
1602 /* 2xMSAA
1603 * There are two locations (-4, 4), (4, -4). */
1604 static uint32_t sample_locs_2x[] = {
1605 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1606 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1607 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1608 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1609 };
1610 static unsigned max_dist_2x = 4;
1611 /* 4xMSAA
1612 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1613 static uint32_t sample_locs_4x[] = {
1614 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1615 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1616 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1617 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1618 };
1619 static unsigned max_dist_4x = 6;
1620 /* 8xMSAA */
1621 static uint32_t sample_locs_8x[] = {
1622 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1623 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1624 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1625 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1626 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1627 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1628 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1629 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1630 };
1631 static unsigned max_dist_8x = 8;
1632
1633 struct radeon_winsys_cs *cs = rctx->cs;
1634 unsigned max_dist = 0;
1635
1636 switch (nr_samples) {
1637 default:
1638 nr_samples = 0;
1639 break;
1640 case 2:
1641 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_2x));
1642 r600_write_array(cs, Elements(sample_locs_2x), sample_locs_2x);
1643 max_dist = max_dist_2x;
1644 break;
1645 case 4:
1646 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_4x));
1647 r600_write_array(cs, Elements(sample_locs_4x), sample_locs_4x);
1648 max_dist = max_dist_4x;
1649 break;
1650 case 8:
1651 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1652 r600_write_array(cs, Elements(sample_locs_8x), sample_locs_8x);
1653 max_dist = max_dist_8x;
1654 break;
1655 }
1656
1657 if (nr_samples > 1) {
1658 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1659 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1660 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1661 r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1662 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1663 } else {
1664 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1665 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1666 r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1667 }
1668 }
1669
1670 static void cayman_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1671 {
1672 /* 2xMSAA
1673 * There are two locations (-4, 4), (4, -4). */
1674 static uint32_t sample_locs_2x[] = {
1675 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1676 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1677 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1678 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1679 };
1680 static unsigned max_dist_2x = 4;
1681 /* 4xMSAA
1682 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1683 static uint32_t sample_locs_4x[] = {
1684 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1685 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1686 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1687 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1688 };
1689 static unsigned max_dist_4x = 6;
1690 /* 8xMSAA */
1691 static uint32_t sample_locs_8x[] = {
1692 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1693 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1694 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1695 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1696 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1697 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1698 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1699 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1700 };
1701 static unsigned max_dist_8x = 8;
1702 /* 16xMSAA */
1703 static uint32_t sample_locs_16x[] = {
1704 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1705 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1706 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1707 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1708 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1709 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1710 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1711 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1712 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1713 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1714 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1715 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1716 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1717 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1718 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1719 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1720 };
1721 static unsigned max_dist_16x = 8;
1722
1723 struct radeon_winsys_cs *cs = rctx->cs;
1724 unsigned max_dist = 0;
1725
1726 switch (nr_samples) {
1727 default:
1728 nr_samples = 0;
1729 break;
1730 case 2:
1731 r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
1732 r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
1733 r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
1734 r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
1735 max_dist = max_dist_2x;
1736 break;
1737 case 4:
1738 r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
1739 r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
1740 r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
1741 r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
1742 max_dist = max_dist_4x;
1743 break;
1744 case 8:
1745 r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1746 r600_write_value(cs, sample_locs_8x[0]);
1747 r600_write_value(cs, sample_locs_8x[4]);
1748 r600_write_value(cs, 0);
1749 r600_write_value(cs, 0);
1750 r600_write_value(cs, sample_locs_8x[1]);
1751 r600_write_value(cs, sample_locs_8x[5]);
1752 r600_write_value(cs, 0);
1753 r600_write_value(cs, 0);
1754 r600_write_value(cs, sample_locs_8x[2]);
1755 r600_write_value(cs, sample_locs_8x[6]);
1756 r600_write_value(cs, 0);
1757 r600_write_value(cs, 0);
1758 r600_write_value(cs, sample_locs_8x[3]);
1759 r600_write_value(cs, sample_locs_8x[7]);
1760 max_dist = max_dist_8x;
1761 break;
1762 case 16:
1763 r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1764 r600_write_value(cs, sample_locs_16x[0]);
1765 r600_write_value(cs, sample_locs_16x[4]);
1766 r600_write_value(cs, sample_locs_16x[8]);
1767 r600_write_value(cs, sample_locs_16x[12]);
1768 r600_write_value(cs, sample_locs_16x[1]);
1769 r600_write_value(cs, sample_locs_16x[5]);
1770 r600_write_value(cs, sample_locs_16x[9]);
1771 r600_write_value(cs, sample_locs_16x[13]);
1772 r600_write_value(cs, sample_locs_16x[2]);
1773 r600_write_value(cs, sample_locs_16x[6]);
1774 r600_write_value(cs, sample_locs_16x[10]);
1775 r600_write_value(cs, sample_locs_16x[14]);
1776 r600_write_value(cs, sample_locs_16x[3]);
1777 r600_write_value(cs, sample_locs_16x[7]);
1778 r600_write_value(cs, sample_locs_16x[11]);
1779 r600_write_value(cs, sample_locs_16x[15]);
1780 max_dist = max_dist_16x;
1781 break;
1782 }
1783
1784 if (nr_samples > 1) {
1785 unsigned log_samples = util_logbase2(nr_samples);
1786
1787 r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
1788 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1789 S_028C00_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1790 r600_write_value(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1791 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
1792 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1793
1794 r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
1795 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1796 S_028804_PS_ITER_SAMPLES(log_samples) |
1797 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1798 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
1799 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1800 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1801 } else {
1802 r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
1803 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1804 r600_write_value(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1805
1806 r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
1807 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1808 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1809 }
1810 }
1811
1812 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1813 {
1814 struct radeon_winsys_cs *cs = rctx->cs;
1815 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1816 unsigned nr_cbufs = state->nr_cbufs;
1817 unsigned i, tl, br;
1818
1819 /* XXX support more colorbuffers once we need them */
1820 assert(nr_cbufs <= 8);
1821 if (nr_cbufs > 8)
1822 nr_cbufs = 8;
1823
1824 /* Colorbuffers. */
1825 for (i = 0; i < nr_cbufs; i++) {
1826 struct r600_surface *cb = (struct r600_surface*)state->cbufs[i];
1827 unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)cb->base.texture,
1828 RADEON_USAGE_READWRITE);
1829
1830 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 11);
1831 r600_write_value(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1832 r600_write_value(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1833 r600_write_value(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1834 r600_write_value(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1835 r600_write_value(cs, cb->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1836 r600_write_value(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1837 r600_write_value(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1838 r600_write_value(cs, cb->cb_color_cmask); /* R_028C7C_CB_COLOR0_CMASK */
1839 r600_write_value(cs, cb->cb_color_cmask_slice); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1840 r600_write_value(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1841 r600_write_value(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1842
1843 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1844 r600_write_value(cs, reloc);
1845
1846 if (!rctx->keep_tiling_flags) {
1847 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1848 r600_write_value(cs, reloc);
1849 }
1850
1851 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1852 r600_write_value(cs, reloc);
1853
1854 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1855 r600_write_value(cs, reloc);
1856
1857 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1858 r600_write_value(cs, reloc);
1859 }
1860 /* set CB_COLOR1_INFO for possible dual-src blending */
1861 if (i == 1 && !((struct r600_texture*)state->cbufs[0]->texture)->is_rat) {
1862 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1863 ((struct r600_surface*)state->cbufs[0])->cb_color_info);
1864
1865 if (!rctx->keep_tiling_flags) {
1866 unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)state->cbufs[0]->texture,
1867 RADEON_USAGE_READWRITE);
1868
1869 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1870 r600_write_value(cs, reloc);
1871 }
1872 i++;
1873 }
1874 if (rctx->keep_tiling_flags) {
1875 for (; i < 8 ; i++) {
1876 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1877 }
1878 for (; i < 12; i++) {
1879 r600_write_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1880 }
1881 }
1882
1883 /* ZS buffer. */
1884 if (state->zsbuf) {
1885 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1886 unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)state->zsbuf->texture,
1887 RADEON_USAGE_READWRITE);
1888
1889 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1890
1891 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1892 r600_write_value(cs, zb->db_depth_info); /* R_028040_DB_Z_INFO */
1893 r600_write_value(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1894 r600_write_value(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1895 r600_write_value(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1896 r600_write_value(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1897 r600_write_value(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1898 r600_write_value(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1899 r600_write_value(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1900
1901 if (!rctx->keep_tiling_flags) {
1902 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
1903 r600_write_value(cs, reloc);
1904 }
1905
1906 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1907 r600_write_value(cs, reloc);
1908
1909 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1910 r600_write_value(cs, reloc);
1911
1912 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1913 r600_write_value(cs, reloc);
1914
1915 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1916 r600_write_value(cs, reloc);
1917 } else if (rctx->screen->info.drm_minor >= 18) {
1918 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1919 * Older kernels are out of luck. */
1920 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1921 r600_write_value(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1922 r600_write_value(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1923 }
1924
1925 /* Framebuffer dimensions. */
1926 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1927
1928 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1929 r600_write_value(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1930 r600_write_value(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1931
1932 if (rctx->chip_class == EVERGREEN) {
1933 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1934 } else {
1935 cayman_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1936 }
1937 }
1938
1939 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1940 {
1941 struct radeon_winsys_cs *cs = rctx->cs;
1942 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1943 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1944 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1945
1946 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1947 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1948 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
1949 * will assure that the alpha-test will work even if there is
1950 * no colorbuffer bound. */
1951 r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1952 }
1953
1954 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1955 {
1956 struct radeon_winsys_cs *cs = rctx->cs;
1957 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1958 unsigned db_render_control = 0;
1959 unsigned db_count_control = 0;
1960 unsigned db_render_override =
1961 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1962 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1963 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1964
1965 if (a->occlusion_query_enabled) {
1966 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1967 if (rctx->chip_class == CAYMAN) {
1968 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1969 }
1970 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1971 }
1972
1973 if (a->flush_depthstencil_through_cb) {
1974 assert(a->copy_depth || a->copy_stencil);
1975
1976 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1977 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1978 S_028000_COPY_CENTROID(1) |
1979 S_028000_COPY_SAMPLE(a->copy_sample);
1980 }
1981
1982 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1983 r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1984 r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1985 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1986 }
1987
1988 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1989 struct r600_vertexbuf_state *state,
1990 unsigned resource_offset,
1991 unsigned pkt_flags)
1992 {
1993 struct radeon_winsys_cs *cs = rctx->cs;
1994 uint32_t dirty_mask = state->dirty_mask;
1995
1996 while (dirty_mask) {
1997 struct pipe_vertex_buffer *vb;
1998 struct r600_resource *rbuffer;
1999 uint64_t va;
2000 unsigned buffer_index = u_bit_scan(&dirty_mask);
2001
2002 vb = &state->vb[buffer_index];
2003 rbuffer = (struct r600_resource*)vb->buffer;
2004 assert(rbuffer);
2005
2006 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
2007 va += vb->buffer_offset;
2008
2009 /* fetch resources start at index 992 */
2010 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2011 r600_write_value(cs, (resource_offset + buffer_index) * 8);
2012 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
2013 r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2014 r600_write_value(cs, /* RESOURCEi_WORD2 */
2015 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2016 S_030008_STRIDE(vb->stride) |
2017 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2018 r600_write_value(cs, /* RESOURCEi_WORD3 */
2019 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2020 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2021 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2022 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2023 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2024 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2025 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
2026 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2027
2028 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2029 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2030 }
2031 state->dirty_mask = 0;
2032 }
2033
2034 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2035 {
2036 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
2037 }
2038
2039 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2040 {
2041 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
2042 RADEON_CP_PACKET3_COMPUTE_MODE);
2043 }
2044
2045 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2046 struct r600_constbuf_state *state,
2047 unsigned buffer_id_base,
2048 unsigned reg_alu_constbuf_size,
2049 unsigned reg_alu_const_cache)
2050 {
2051 struct radeon_winsys_cs *cs = rctx->cs;
2052 uint32_t dirty_mask = state->dirty_mask;
2053
2054 while (dirty_mask) {
2055 struct pipe_constant_buffer *cb;
2056 struct r600_resource *rbuffer;
2057 uint64_t va;
2058 unsigned buffer_index = ffs(dirty_mask) - 1;
2059
2060 cb = &state->cb[buffer_index];
2061 rbuffer = (struct r600_resource*)cb->buffer;
2062 assert(rbuffer);
2063
2064 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
2065 va += cb->buffer_offset;
2066
2067 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2068 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
2069 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
2070
2071 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2072 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2073
2074 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2075 r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
2076 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
2077 r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2078 r600_write_value(cs, /* RESOURCEi_WORD2 */
2079 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2080 S_030008_STRIDE(16) |
2081 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2082 r600_write_value(cs, /* RESOURCEi_WORD3 */
2083 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2084 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2085 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2086 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2087 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2088 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2089 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
2090 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2091
2092 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2093 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2094
2095 dirty_mask &= ~(1 << buffer_index);
2096 }
2097 state->dirty_mask = 0;
2098 }
2099
2100 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2101 {
2102 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 176,
2103 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2104 R_028980_ALU_CONST_CACHE_VS_0);
2105 }
2106
2107 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2108 {
2109 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
2110 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2111 R_0289C0_ALU_CONST_CACHE_GS_0);
2112 }
2113
2114 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2115 {
2116 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
2117 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2118 R_028940_ALU_CONST_CACHE_PS_0);
2119 }
2120
2121 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2122 struct r600_samplerview_state *state,
2123 unsigned resource_id_base)
2124 {
2125 struct radeon_winsys_cs *cs = rctx->cs;
2126 uint32_t dirty_mask = state->dirty_mask;
2127
2128 while (dirty_mask) {
2129 struct r600_pipe_sampler_view *rview;
2130 unsigned resource_index = u_bit_scan(&dirty_mask);
2131 unsigned reloc;
2132
2133 rview = state->views[resource_index];
2134 assert(rview);
2135
2136 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2137 r600_write_value(cs, (resource_id_base + resource_index) * 8);
2138 r600_write_array(cs, 8, rview->tex_resource_words);
2139
2140 /* XXX The kernel needs two relocations. This is stupid. */
2141 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
2142 RADEON_USAGE_READ);
2143 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2144 r600_write_value(cs, reloc);
2145 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2146 r600_write_value(cs, reloc);
2147 }
2148 state->dirty_mask = 0;
2149 }
2150
2151 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2152 {
2153 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 176 + R600_MAX_CONST_BUFFERS);
2154 }
2155
2156 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2157 {
2158 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2159 }
2160
2161 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2162 {
2163 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2164 }
2165
2166 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2167 struct r600_textures_info *texinfo,
2168 unsigned resource_id_base,
2169 unsigned border_index_reg)
2170 {
2171 struct radeon_winsys_cs *cs = rctx->cs;
2172 uint32_t dirty_mask = texinfo->states.dirty_mask;
2173
2174 while (dirty_mask) {
2175 struct r600_pipe_sampler_state *rstate;
2176 unsigned i = u_bit_scan(&dirty_mask);
2177
2178 rstate = texinfo->states.states[i];
2179 assert(rstate);
2180
2181 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2182 r600_write_value(cs, (resource_id_base + i) * 3);
2183 r600_write_array(cs, 3, rstate->tex_sampler_words);
2184
2185 if (rstate->border_color_use) {
2186 r600_write_config_reg_seq(cs, border_index_reg, 5);
2187 r600_write_value(cs, i);
2188 r600_write_array(cs, 4, rstate->border_color);
2189 }
2190 }
2191 texinfo->states.dirty_mask = 0;
2192 }
2193
2194 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2195 {
2196 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
2197 }
2198
2199 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2200 {
2201 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX);
2202 }
2203
2204 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2205 {
2206 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
2207 }
2208
2209 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2210 {
2211 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2212 uint8_t mask = s->sample_mask;
2213
2214 r600_write_context_reg(rctx->cs, R_028C3C_PA_SC_AA_MASK,
2215 mask | (mask << 8) | (mask << 16) | (mask << 24));
2216 }
2217
2218 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2219 {
2220 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2221 struct radeon_winsys_cs *cs = rctx->cs;
2222 uint16_t mask = s->sample_mask;
2223
2224 r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2225 r600_write_value(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2226 r600_write_value(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2227 }
2228
2229 void evergreen_init_state_functions(struct r600_context *rctx)
2230 {
2231 unsigned id = 4;
2232
2233 /* !!!
2234 * To avoid GPU lockup registers must be emited in a specific order
2235 * (no kidding ...). The order below is important and have been
2236 * partialy infered from analyzing fglrx command stream.
2237 *
2238 * Don't reorder atom without carefully checking the effect (GPU lockup
2239 * or piglit regression).
2240 * !!!
2241 */
2242
2243 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
2244 /* shader const */
2245 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
2246 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
2247 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
2248 /* shader program */
2249 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
2250 /* sampler */
2251 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
2252 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
2253 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
2254 /* resources */
2255 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
2256 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
2257 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
2258 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
2259 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
2260
2261 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
2262 r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
2263
2264 if (rctx->chip_class == EVERGREEN) {
2265 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
2266 } else {
2267 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
2268 }
2269 rctx->sample_mask.sample_mask = ~0;
2270
2271 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2272 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2273 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
2274 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
2275 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
2276 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 7);
2277 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2278 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2279
2280 rctx->context.create_blend_state = evergreen_create_blend_state;
2281 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
2282 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
2283 rctx->context.create_sampler_state = evergreen_create_sampler_state;
2284 rctx->context.create_sampler_view = evergreen_create_sampler_view;
2285 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
2286 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
2287 rctx->context.set_scissor_state = evergreen_set_scissor_state;
2288 evergreen_init_compute_state_functions(rctx);
2289 }
2290
2291 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2292 {
2293 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2294
2295 r600_init_command_buffer(rctx, cb, 0, 256);
2296
2297 /* This must be first. */
2298 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2299 r600_store_value(cb, 0x80000000);
2300 r600_store_value(cb, 0x80000000);
2301
2302 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2303 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2304 /* always set the temp clauses */
2305 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2306
2307 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2308 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2309 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2310
2311 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2312
2313 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2314
2315 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2316 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2317 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2318 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2319 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2320 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2321 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2322 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2323 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2324 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2325 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2326 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2327 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2328 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2329
2330 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2331 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2332 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2333
2334 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2335 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2336 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2337
2338 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2339
2340 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2341
2342 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2343 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2344 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2345
2346 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
2347 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2348 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2349
2350 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2351 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2352 r600_store_value(cb, 0);
2353 r600_store_value(cb, 0);
2354 r600_store_value(cb, 0);
2355 r600_store_value(cb, 0);
2356 r600_store_value(cb, 0);
2357 r600_store_value(cb, 0);
2358 r600_store_value(cb, 0);
2359 r600_store_value(cb, 0);
2360 r600_store_value(cb, 0);
2361 r600_store_value(cb, 0);
2362 r600_store_value(cb, 0);
2363 r600_store_value(cb, 0);
2364 r600_store_value(cb, 0);
2365 r600_store_value(cb, 0);
2366 r600_store_value(cb, 0);
2367 r600_store_value(cb, 0);
2368 r600_store_value(cb, 0);
2369 r600_store_value(cb, 0);
2370 r600_store_value(cb, 0);
2371 r600_store_value(cb, 0);
2372 r600_store_value(cb, 0);
2373 r600_store_value(cb, 0);
2374 r600_store_value(cb, 0);
2375 r600_store_value(cb, 0);
2376 r600_store_value(cb, 0);
2377 r600_store_value(cb, 0);
2378 r600_store_value(cb, 0);
2379 r600_store_value(cb, 0);
2380 r600_store_value(cb, 0);
2381 r600_store_value(cb, 0);
2382 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2383 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2384 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2385
2386 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2387
2388 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2389 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2390 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2391
2392 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2393
2394 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2395 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2396 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2397 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2398
2399 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2400 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2401
2402 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2403 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2404 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2405
2406 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2407 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2408 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2409
2410 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2411 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2412 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2413 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2414 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2415
2416 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2417 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2418 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2419
2420 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2421 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2422 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2423
2424 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2425 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2426 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2427
2428 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2429 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2430 if (rctx->screen->has_streamout) {
2431 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2432 }
2433
2434 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2435 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2436 }
2437
2438 void evergreen_init_common_regs(struct r600_command_buffer *cb,
2439 enum chip_class ctx_chip_class,
2440 enum radeon_family ctx_family,
2441 int ctx_drm_minor)
2442 {
2443 int ps_prio;
2444 int vs_prio;
2445 int gs_prio;
2446 int es_prio;
2447
2448 int hs_prio;
2449 int cs_prio;
2450 int ls_prio;
2451
2452 int num_ps_gprs;
2453 int num_vs_gprs;
2454 int num_gs_gprs;
2455 int num_es_gprs;
2456 int num_hs_gprs;
2457 int num_ls_gprs;
2458 int num_temp_gprs;
2459
2460 unsigned tmp;
2461
2462 ps_prio = 0;
2463 vs_prio = 1;
2464 gs_prio = 2;
2465 es_prio = 3;
2466 hs_prio = 0;
2467 ls_prio = 0;
2468 cs_prio = 0;
2469
2470 switch (ctx_family) {
2471 case CHIP_CEDAR:
2472 default:
2473 num_ps_gprs = 93;
2474 num_vs_gprs = 46;
2475 num_temp_gprs = 4;
2476 num_gs_gprs = 31;
2477 num_es_gprs = 31;
2478 num_hs_gprs = 23;
2479 num_ls_gprs = 23;
2480 break;
2481 case CHIP_REDWOOD:
2482 num_ps_gprs = 93;
2483 num_vs_gprs = 46;
2484 num_temp_gprs = 4;
2485 num_gs_gprs = 31;
2486 num_es_gprs = 31;
2487 num_hs_gprs = 23;
2488 num_ls_gprs = 23;
2489 break;
2490 case CHIP_JUNIPER:
2491 num_ps_gprs = 93;
2492 num_vs_gprs = 46;
2493 num_temp_gprs = 4;
2494 num_gs_gprs = 31;
2495 num_es_gprs = 31;
2496 num_hs_gprs = 23;
2497 num_ls_gprs = 23;
2498 break;
2499 case CHIP_CYPRESS:
2500 case CHIP_HEMLOCK:
2501 num_ps_gprs = 93;
2502 num_vs_gprs = 46;
2503 num_temp_gprs = 4;
2504 num_gs_gprs = 31;
2505 num_es_gprs = 31;
2506 num_hs_gprs = 23;
2507 num_ls_gprs = 23;
2508 break;
2509 case CHIP_PALM:
2510 num_ps_gprs = 93;
2511 num_vs_gprs = 46;
2512 num_temp_gprs = 4;
2513 num_gs_gprs = 31;
2514 num_es_gprs = 31;
2515 num_hs_gprs = 23;
2516 num_ls_gprs = 23;
2517 break;
2518 case CHIP_SUMO:
2519 num_ps_gprs = 93;
2520 num_vs_gprs = 46;
2521 num_temp_gprs = 4;
2522 num_gs_gprs = 31;
2523 num_es_gprs = 31;
2524 num_hs_gprs = 23;
2525 num_ls_gprs = 23;
2526 break;
2527 case CHIP_SUMO2:
2528 num_ps_gprs = 93;
2529 num_vs_gprs = 46;
2530 num_temp_gprs = 4;
2531 num_gs_gprs = 31;
2532 num_es_gprs = 31;
2533 num_hs_gprs = 23;
2534 num_ls_gprs = 23;
2535 break;
2536 case CHIP_BARTS:
2537 num_ps_gprs = 93;
2538 num_vs_gprs = 46;
2539 num_temp_gprs = 4;
2540 num_gs_gprs = 31;
2541 num_es_gprs = 31;
2542 num_hs_gprs = 23;
2543 num_ls_gprs = 23;
2544 break;
2545 case CHIP_TURKS:
2546 num_ps_gprs = 93;
2547 num_vs_gprs = 46;
2548 num_temp_gprs = 4;
2549 num_gs_gprs = 31;
2550 num_es_gprs = 31;
2551 num_hs_gprs = 23;
2552 num_ls_gprs = 23;
2553 break;
2554 case CHIP_CAICOS:
2555 num_ps_gprs = 93;
2556 num_vs_gprs = 46;
2557 num_temp_gprs = 4;
2558 num_gs_gprs = 31;
2559 num_es_gprs = 31;
2560 num_hs_gprs = 23;
2561 num_ls_gprs = 23;
2562 break;
2563 }
2564
2565 tmp = 0;
2566 switch (ctx_family) {
2567 case CHIP_CEDAR:
2568 case CHIP_PALM:
2569 case CHIP_SUMO:
2570 case CHIP_SUMO2:
2571 case CHIP_CAICOS:
2572 break;
2573 default:
2574 tmp |= S_008C00_VC_ENABLE(1);
2575 break;
2576 }
2577 tmp |= S_008C00_EXPORT_SRC_C(1);
2578 tmp |= S_008C00_CS_PRIO(cs_prio);
2579 tmp |= S_008C00_LS_PRIO(ls_prio);
2580 tmp |= S_008C00_HS_PRIO(hs_prio);
2581 tmp |= S_008C00_PS_PRIO(ps_prio);
2582 tmp |= S_008C00_VS_PRIO(vs_prio);
2583 tmp |= S_008C00_GS_PRIO(gs_prio);
2584 tmp |= S_008C00_ES_PRIO(es_prio);
2585
2586 /* enable dynamic GPR resource management */
2587 if (ctx_drm_minor >= 7) {
2588 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2589 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2590 /* always set temp clauses */
2591 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2592 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2593 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2594 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2595 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2596 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2597 S_028838_PS_GPRS(0x1e) |
2598 S_028838_VS_GPRS(0x1e) |
2599 S_028838_GS_GPRS(0x1e) |
2600 S_028838_ES_GPRS(0x1e) |
2601 S_028838_HS_GPRS(0x1e) |
2602 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2603 } else {
2604 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2605 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2606
2607 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2608 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2609 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2610 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2611
2612 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2613 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2614 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2615
2616 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2617 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2618 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2619 }
2620
2621 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2622 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2623
2624 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2625
2626 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2627 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2628 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2629
2630 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2631
2632 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2633 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2634 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2635
2636 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2637 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2638 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2639 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2640
2641 /* The cs checker requires this register to be set. */
2642 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2643
2644 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2645 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2646
2647 /* to avoid GPU doing any preloading of constant from random address */
2648 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2649 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2650 r600_store_value(cb, 0);
2651 r600_store_value(cb, 0);
2652 r600_store_value(cb, 0);
2653 r600_store_value(cb, 0);
2654 r600_store_value(cb, 0);
2655 r600_store_value(cb, 0);
2656 r600_store_value(cb, 0);
2657 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2658 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2659 r600_store_value(cb, 0);
2660 r600_store_value(cb, 0);
2661 r600_store_value(cb, 0);
2662 r600_store_value(cb, 0);
2663 r600_store_value(cb, 0);
2664 r600_store_value(cb, 0);
2665 r600_store_value(cb, 0);
2666
2667 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2668
2669 return;
2670 }
2671
2672 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2673 {
2674 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2675 int num_ps_threads;
2676 int num_vs_threads;
2677 int num_gs_threads;
2678 int num_es_threads;
2679 int num_hs_threads;
2680 int num_ls_threads;
2681
2682 int num_ps_stack_entries;
2683 int num_vs_stack_entries;
2684 int num_gs_stack_entries;
2685 int num_es_stack_entries;
2686 int num_hs_stack_entries;
2687 int num_ls_stack_entries;
2688 enum radeon_family family;
2689 unsigned tmp;
2690
2691 if (rctx->chip_class == CAYMAN) {
2692 cayman_init_atom_start_cs(rctx);
2693 return;
2694 }
2695
2696 r600_init_command_buffer(rctx, cb, 0, 256);
2697
2698 /* This must be first. */
2699 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2700 r600_store_value(cb, 0x80000000);
2701 r600_store_value(cb, 0x80000000);
2702
2703 evergreen_init_common_regs(cb, rctx->chip_class
2704 , rctx->family, rctx->screen->info.drm_minor);
2705
2706 family = rctx->family;
2707 switch (family) {
2708 case CHIP_CEDAR:
2709 default:
2710 num_ps_threads = 96;
2711 num_vs_threads = 16;
2712 num_gs_threads = 16;
2713 num_es_threads = 16;
2714 num_hs_threads = 16;
2715 num_ls_threads = 16;
2716 num_ps_stack_entries = 42;
2717 num_vs_stack_entries = 42;
2718 num_gs_stack_entries = 42;
2719 num_es_stack_entries = 42;
2720 num_hs_stack_entries = 42;
2721 num_ls_stack_entries = 42;
2722 break;
2723 case CHIP_REDWOOD:
2724 num_ps_threads = 128;
2725 num_vs_threads = 20;
2726 num_gs_threads = 20;
2727 num_es_threads = 20;
2728 num_hs_threads = 20;
2729 num_ls_threads = 20;
2730 num_ps_stack_entries = 42;
2731 num_vs_stack_entries = 42;
2732 num_gs_stack_entries = 42;
2733 num_es_stack_entries = 42;
2734 num_hs_stack_entries = 42;
2735 num_ls_stack_entries = 42;
2736 break;
2737 case CHIP_JUNIPER:
2738 num_ps_threads = 128;
2739 num_vs_threads = 20;
2740 num_gs_threads = 20;
2741 num_es_threads = 20;
2742 num_hs_threads = 20;
2743 num_ls_threads = 20;
2744 num_ps_stack_entries = 85;
2745 num_vs_stack_entries = 85;
2746 num_gs_stack_entries = 85;
2747 num_es_stack_entries = 85;
2748 num_hs_stack_entries = 85;
2749 num_ls_stack_entries = 85;
2750 break;
2751 case CHIP_CYPRESS:
2752 case CHIP_HEMLOCK:
2753 num_ps_threads = 128;
2754 num_vs_threads = 20;
2755 num_gs_threads = 20;
2756 num_es_threads = 20;
2757 num_hs_threads = 20;
2758 num_ls_threads = 20;
2759 num_ps_stack_entries = 85;
2760 num_vs_stack_entries = 85;
2761 num_gs_stack_entries = 85;
2762 num_es_stack_entries = 85;
2763 num_hs_stack_entries = 85;
2764 num_ls_stack_entries = 85;
2765 break;
2766 case CHIP_PALM:
2767 num_ps_threads = 96;
2768 num_vs_threads = 16;
2769 num_gs_threads = 16;
2770 num_es_threads = 16;
2771 num_hs_threads = 16;
2772 num_ls_threads = 16;
2773 num_ps_stack_entries = 42;
2774 num_vs_stack_entries = 42;
2775 num_gs_stack_entries = 42;
2776 num_es_stack_entries = 42;
2777 num_hs_stack_entries = 42;
2778 num_ls_stack_entries = 42;
2779 break;
2780 case CHIP_SUMO:
2781 num_ps_threads = 96;
2782 num_vs_threads = 25;
2783 num_gs_threads = 25;
2784 num_es_threads = 25;
2785 num_hs_threads = 25;
2786 num_ls_threads = 25;
2787 num_ps_stack_entries = 42;
2788 num_vs_stack_entries = 42;
2789 num_gs_stack_entries = 42;
2790 num_es_stack_entries = 42;
2791 num_hs_stack_entries = 42;
2792 num_ls_stack_entries = 42;
2793 break;
2794 case CHIP_SUMO2:
2795 num_ps_threads = 96;
2796 num_vs_threads = 25;
2797 num_gs_threads = 25;
2798 num_es_threads = 25;
2799 num_hs_threads = 25;
2800 num_ls_threads = 25;
2801 num_ps_stack_entries = 85;
2802 num_vs_stack_entries = 85;
2803 num_gs_stack_entries = 85;
2804 num_es_stack_entries = 85;
2805 num_hs_stack_entries = 85;
2806 num_ls_stack_entries = 85;
2807 break;
2808 case CHIP_BARTS:
2809 num_ps_threads = 128;
2810 num_vs_threads = 20;
2811 num_gs_threads = 20;
2812 num_es_threads = 20;
2813 num_hs_threads = 20;
2814 num_ls_threads = 20;
2815 num_ps_stack_entries = 85;
2816 num_vs_stack_entries = 85;
2817 num_gs_stack_entries = 85;
2818 num_es_stack_entries = 85;
2819 num_hs_stack_entries = 85;
2820 num_ls_stack_entries = 85;
2821 break;
2822 case CHIP_TURKS:
2823 num_ps_threads = 128;
2824 num_vs_threads = 20;
2825 num_gs_threads = 20;
2826 num_es_threads = 20;
2827 num_hs_threads = 20;
2828 num_ls_threads = 20;
2829 num_ps_stack_entries = 42;
2830 num_vs_stack_entries = 42;
2831 num_gs_stack_entries = 42;
2832 num_es_stack_entries = 42;
2833 num_hs_stack_entries = 42;
2834 num_ls_stack_entries = 42;
2835 break;
2836 case CHIP_CAICOS:
2837 num_ps_threads = 128;
2838 num_vs_threads = 10;
2839 num_gs_threads = 10;
2840 num_es_threads = 10;
2841 num_hs_threads = 10;
2842 num_ls_threads = 10;
2843 num_ps_stack_entries = 42;
2844 num_vs_stack_entries = 42;
2845 num_gs_stack_entries = 42;
2846 num_es_stack_entries = 42;
2847 num_hs_stack_entries = 42;
2848 num_ls_stack_entries = 42;
2849 break;
2850 }
2851
2852 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2853 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2854 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2855 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2856
2857 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2858 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2859
2860 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2861 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2862 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2863
2864 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2865 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2866 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2867
2868 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2869 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2870 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2871
2872 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2873 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2874 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2875
2876 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2877 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2878
2879 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2880 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2881 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2882 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2883 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2884 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2885 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2886
2887 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2888 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2889 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2890 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2891 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2892
2893 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2894 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2895 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2896 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2897 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2898 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2899 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2900 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2901 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2902 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2903 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2904 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2905 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2906 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2907
2908 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2909 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2910 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2911
2912 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2913
2914 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2915 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2916 r600_store_value(cb, 0);
2917 r600_store_value(cb, 0);
2918 r600_store_value(cb, 0);
2919 r600_store_value(cb, 0);
2920 r600_store_value(cb, 0);
2921 r600_store_value(cb, 0);
2922 r600_store_value(cb, 0);
2923 r600_store_value(cb, 0);
2924 r600_store_value(cb, 0);
2925 r600_store_value(cb, 0);
2926 r600_store_value(cb, 0);
2927 r600_store_value(cb, 0);
2928 r600_store_value(cb, 0);
2929 r600_store_value(cb, 0);
2930 r600_store_value(cb, 0);
2931 r600_store_value(cb, 0);
2932 r600_store_value(cb, 0);
2933 r600_store_value(cb, 0);
2934 r600_store_value(cb, 0);
2935 r600_store_value(cb, 0);
2936 r600_store_value(cb, 0);
2937 r600_store_value(cb, 0);
2938 r600_store_value(cb, 0);
2939 r600_store_value(cb, 0);
2940 r600_store_value(cb, 0);
2941 r600_store_value(cb, 0);
2942 r600_store_value(cb, 0);
2943 r600_store_value(cb, 0);
2944 r600_store_value(cb, 0);
2945 r600_store_value(cb, 0);
2946 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2947 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2948 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2949
2950 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2951
2952 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2953 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2954 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2955
2956 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2957 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2958
2959 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2960 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2961 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2962
2963 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2964 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2965 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2966 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2967
2968 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2969 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2970 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2971 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2972 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2973
2974 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2975 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2976 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2977
2978 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2979 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2980 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2981
2982 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2983
2984 if (rctx->screen->has_streamout) {
2985 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2986 }
2987
2988 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2989 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2990 }
2991
2992 void evergreen_polygon_offset_update(struct r600_context *rctx)
2993 {
2994 struct r600_pipe_state state;
2995
2996 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2997 state.nregs = 0;
2998 if (rctx->rasterizer && rctx->framebuffer.state.zsbuf) {
2999 float offset_units = rctx->rasterizer->offset_units;
3000 unsigned offset_db_fmt_cntl = 0, depth;
3001
3002 switch (rctx->framebuffer.state.zsbuf->format) {
3003 case PIPE_FORMAT_Z24X8_UNORM:
3004 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
3005 depth = -24;
3006 offset_units *= 2.0f;
3007 break;
3008 case PIPE_FORMAT_Z32_FLOAT:
3009 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3010 depth = -23;
3011 offset_units *= 1.0f;
3012 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3013 break;
3014 case PIPE_FORMAT_Z16_UNORM:
3015 depth = -16;
3016 offset_units *= 4.0f;
3017 break;
3018 default:
3019 return;
3020 }
3021 /* XXX some of those reg can be computed with cso */
3022 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
3023 r600_pipe_state_add_reg(&state,
3024 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
3025 fui(rctx->rasterizer->offset_scale));
3026 r600_pipe_state_add_reg(&state,
3027 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
3028 fui(offset_units));
3029 r600_pipe_state_add_reg(&state,
3030 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
3031 fui(rctx->rasterizer->offset_scale));
3032 r600_pipe_state_add_reg(&state,
3033 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
3034 fui(offset_units));
3035 r600_pipe_state_add_reg(&state,
3036 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
3037 offset_db_fmt_cntl);
3038 r600_context_pipe_state_set(rctx, &state);
3039 }
3040 }
3041
3042 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3043 {
3044 struct r600_context *rctx = (struct r600_context *)ctx;
3045 struct r600_pipe_state *rstate = &shader->rstate;
3046 struct r600_shader *rshader = &shader->shader;
3047 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
3048 int pos_index = -1, face_index = -1;
3049 int ninterp = 0;
3050 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
3051 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
3052 unsigned z_export = 0, stencil_export = 0;
3053
3054 rstate->nregs = 0;
3055
3056 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3057 for (i = 0; i < rshader->ninput; i++) {
3058 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3059 POSITION goes via GPRs from the SC so isn't counted */
3060 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3061 pos_index = i;
3062 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
3063 face_index = i;
3064 else {
3065 ninterp++;
3066 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
3067 have_linear = TRUE;
3068 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
3069 have_perspective = TRUE;
3070 if (rshader->input[i].centroid)
3071 have_centroid = TRUE;
3072 }
3073
3074 sid = rshader->input[i].spi_sid;
3075
3076 if (sid) {
3077
3078 tmp = S_028644_SEMANTIC(sid);
3079
3080 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3081 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3082 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3083 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3084 tmp |= S_028644_FLAT_SHADE(1);
3085 }
3086
3087 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3088 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
3089 tmp |= S_028644_PT_SPRITE_TEX(1);
3090 }
3091
3092 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
3093 tmp);
3094
3095 idx++;
3096 }
3097 }
3098
3099 for (i = 0; i < rshader->noutput; i++) {
3100 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3101 z_export = 1;
3102 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3103 stencil_export = 1;
3104 }
3105 if (rshader->uses_kill)
3106 db_shader_control |= S_02880C_KILL_ENABLE(1);
3107
3108 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3109 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3110
3111 exports_ps = 0;
3112 for (i = 0; i < rshader->noutput; i++) {
3113 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3114 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3115 exports_ps |= 1;
3116 }
3117
3118 num_cout = rshader->nr_ps_color_exports;
3119
3120 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3121 if (!exports_ps) {
3122 /* always at least export 1 component per pixel */
3123 exports_ps = 2;
3124 }
3125 shader->nr_ps_color_outputs = num_cout;
3126 if (ninterp == 0) {
3127 ninterp = 1;
3128 have_perspective = TRUE;
3129 }
3130
3131 if (!have_perspective && !have_linear)
3132 have_perspective = TRUE;
3133
3134 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3135 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3136 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3137 spi_input_z = 0;
3138 if (pos_index != -1) {
3139 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3140 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
3141 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3142 spi_input_z |= 1;
3143 }
3144
3145 spi_ps_in_control_1 = 0;
3146 if (face_index != -1) {
3147 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3148 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3149 }
3150
3151 spi_baryc_cntl = 0;
3152 if (have_perspective)
3153 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
3154 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
3155 if (have_linear)
3156 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
3157 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
3158
3159 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
3160 spi_ps_in_control_0);
3161 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
3162 spi_ps_in_control_1);
3163 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
3164 0);
3165 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
3166 r600_pipe_state_add_reg(rstate,
3167 R_0286E0_SPI_BARYC_CNTL,
3168 spi_baryc_cntl);
3169
3170 r600_pipe_state_add_reg_bo(rstate,
3171 R_028840_SQ_PGM_START_PS,
3172 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3173 shader->bo, RADEON_USAGE_READ);
3174 r600_pipe_state_add_reg(rstate,
3175 R_028844_SQ_PGM_RESOURCES_PS,
3176 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3177 S_028844_PRIME_CACHE_ON_DRAW(1) |
3178 S_028844_STACK_SIZE(rshader->bc.nstack));
3179 r600_pipe_state_add_reg(rstate,
3180 R_02884C_SQ_PGM_EXPORTS_PS,
3181 exports_ps);
3182
3183 shader->db_shader_control = db_shader_control;
3184 shader->ps_depth_export = z_export | stencil_export;
3185
3186 shader->sprite_coord_enable = rctx->sprite_coord_enable;
3187 if (rctx->rasterizer)
3188 shader->flatshade = rctx->rasterizer->flatshade;
3189 }
3190
3191 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3192 {
3193 struct r600_context *rctx = (struct r600_context *)ctx;
3194 struct r600_pipe_state *rstate = &shader->rstate;
3195 struct r600_shader *rshader = &shader->shader;
3196 unsigned spi_vs_out_id[10] = {};
3197 unsigned i, tmp, nparams = 0;
3198
3199 /* clear previous register */
3200 rstate->nregs = 0;
3201
3202 for (i = 0; i < rshader->noutput; i++) {
3203 if (rshader->output[i].spi_sid) {
3204 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3205 spi_vs_out_id[nparams / 4] |= tmp;
3206 nparams++;
3207 }
3208 }
3209
3210 for (i = 0; i < 10; i++) {
3211 r600_pipe_state_add_reg(rstate,
3212 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
3213 spi_vs_out_id[i]);
3214 }
3215
3216 /* Certain attributes (position, psize, etc.) don't count as params.
3217 * VS is required to export at least one param and r600_shader_from_tgsi()
3218 * takes care of adding a dummy export.
3219 */
3220 if (nparams < 1)
3221 nparams = 1;
3222
3223 r600_pipe_state_add_reg(rstate,
3224 R_0286C4_SPI_VS_OUT_CONFIG,
3225 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3226 r600_pipe_state_add_reg(rstate,
3227 R_028860_SQ_PGM_RESOURCES_VS,
3228 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3229 S_028860_STACK_SIZE(rshader->bc.nstack));
3230 r600_pipe_state_add_reg_bo(rstate,
3231 R_02885C_SQ_PGM_START_VS,
3232 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3233 shader->bo, RADEON_USAGE_READ);
3234
3235 shader->pa_cl_vs_out_cntl =
3236 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3237 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3238 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3239 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
3240 }
3241
3242 void evergreen_fetch_shader(struct pipe_context *ctx,
3243 struct r600_vertex_element *ve)
3244 {
3245 struct r600_context *rctx = (struct r600_context *)ctx;
3246 struct r600_pipe_state *rstate = &ve->rstate;
3247 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
3248 rstate->nregs = 0;
3249 r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
3250 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
3251 ve->fetch_shader, RADEON_USAGE_READ);
3252 }
3253
3254 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3255 {
3256 struct pipe_blend_state blend;
3257 struct r600_pipe_state *rstate;
3258
3259 memset(&blend, 0, sizeof(blend));
3260 blend.independent_blend_enable = true;
3261 blend.rt[0].colormask = 0xf;
3262 rstate = evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_RESOLVE);
3263 return rstate;
3264 }
3265
3266 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3267 {
3268 struct pipe_blend_state blend;
3269 struct r600_pipe_state *rstate;
3270
3271 memset(&blend, 0, sizeof(blend));
3272 blend.independent_blend_enable = true;
3273 blend.rt[0].colormask = 0xf;
3274 rstate = evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_DECOMPRESS);
3275 return rstate;
3276 }
3277
3278 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3279 {
3280 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3281
3282 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
3283 }
3284
3285 void evergreen_update_dual_export_state(struct r600_context * rctx)
3286 {
3287 bool dual_export = rctx->framebuffer.export_16bpc &&
3288 !rctx->ps_shader->current->ps_depth_export;
3289
3290 unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
3291 V_02880C_EXPORT_DB_FULL;
3292
3293 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
3294 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3295 S_02880C_DB_SOURCE_FORMAT(db_source_format) |
3296 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3297
3298 if (db_shader_control != rctx->db_shader_control) {
3299 struct r600_pipe_state rstate;
3300
3301 rctx->db_shader_control = db_shader_control;
3302
3303 rstate.nregs = 0;
3304 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
3305 r600_context_pipe_state_set(rctx, &rstate);
3306 }
3307 }