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r600g: sort variables in r600_context
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "evergreend.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31 #include "evergreen_compute.h"
32
33 static uint32_t eg_num_banks(uint32_t nbanks)
34 {
35 switch (nbanks) {
36 case 2:
37 return 0;
38 case 4:
39 return 1;
40 case 8:
41 default:
42 return 2;
43 case 16:
44 return 3;
45 }
46 }
47
48
49 static unsigned eg_tile_split(unsigned tile_split)
50 {
51 switch (tile_split) {
52 case 64: tile_split = 0; break;
53 case 128: tile_split = 1; break;
54 case 256: tile_split = 2; break;
55 case 512: tile_split = 3; break;
56 default:
57 case 1024: tile_split = 4; break;
58 case 2048: tile_split = 5; break;
59 case 4096: tile_split = 6; break;
60 }
61 return tile_split;
62 }
63
64 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65 {
66 switch (macro_tile_aspect) {
67 default:
68 case 1: macro_tile_aspect = 0; break;
69 case 2: macro_tile_aspect = 1; break;
70 case 4: macro_tile_aspect = 2; break;
71 case 8: macro_tile_aspect = 3; break;
72 }
73 return macro_tile_aspect;
74 }
75
76 static unsigned eg_bank_wh(unsigned bankwh)
77 {
78 switch (bankwh) {
79 default:
80 case 1: bankwh = 0; break;
81 case 2: bankwh = 1; break;
82 case 4: bankwh = 2; break;
83 case 8: bankwh = 3; break;
84 }
85 return bankwh;
86 }
87
88 static uint32_t r600_translate_blend_function(int blend_func)
89 {
90 switch (blend_func) {
91 case PIPE_BLEND_ADD:
92 return V_028780_COMB_DST_PLUS_SRC;
93 case PIPE_BLEND_SUBTRACT:
94 return V_028780_COMB_SRC_MINUS_DST;
95 case PIPE_BLEND_REVERSE_SUBTRACT:
96 return V_028780_COMB_DST_MINUS_SRC;
97 case PIPE_BLEND_MIN:
98 return V_028780_COMB_MIN_DST_SRC;
99 case PIPE_BLEND_MAX:
100 return V_028780_COMB_MAX_DST_SRC;
101 default:
102 R600_ERR("Unknown blend function %d\n", blend_func);
103 assert(0);
104 break;
105 }
106 return 0;
107 }
108
109 static uint32_t r600_translate_blend_factor(int blend_fact)
110 {
111 switch (blend_fact) {
112 case PIPE_BLENDFACTOR_ONE:
113 return V_028780_BLEND_ONE;
114 case PIPE_BLENDFACTOR_SRC_COLOR:
115 return V_028780_BLEND_SRC_COLOR;
116 case PIPE_BLENDFACTOR_SRC_ALPHA:
117 return V_028780_BLEND_SRC_ALPHA;
118 case PIPE_BLENDFACTOR_DST_ALPHA:
119 return V_028780_BLEND_DST_ALPHA;
120 case PIPE_BLENDFACTOR_DST_COLOR:
121 return V_028780_BLEND_DST_COLOR;
122 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123 return V_028780_BLEND_SRC_ALPHA_SATURATE;
124 case PIPE_BLENDFACTOR_CONST_COLOR:
125 return V_028780_BLEND_CONST_COLOR;
126 case PIPE_BLENDFACTOR_CONST_ALPHA:
127 return V_028780_BLEND_CONST_ALPHA;
128 case PIPE_BLENDFACTOR_ZERO:
129 return V_028780_BLEND_ZERO;
130 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136 case PIPE_BLENDFACTOR_INV_DST_COLOR:
137 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_SRC1_COLOR:
143 return V_028780_BLEND_SRC1_COLOR;
144 case PIPE_BLENDFACTOR_SRC1_ALPHA:
145 return V_028780_BLEND_SRC1_ALPHA;
146 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147 return V_028780_BLEND_INV_SRC1_COLOR;
148 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149 return V_028780_BLEND_INV_SRC1_ALPHA;
150 default:
151 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152 assert(0);
153 break;
154 }
155 return 0;
156 }
157
158 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
159 {
160 switch (dim) {
161 default:
162 case PIPE_TEXTURE_1D:
163 return V_030000_SQ_TEX_DIM_1D;
164 case PIPE_TEXTURE_1D_ARRAY:
165 return V_030000_SQ_TEX_DIM_1D_ARRAY;
166 case PIPE_TEXTURE_2D:
167 case PIPE_TEXTURE_RECT:
168 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
169 V_030000_SQ_TEX_DIM_2D;
170 case PIPE_TEXTURE_2D_ARRAY:
171 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
172 V_030000_SQ_TEX_DIM_2D_ARRAY;
173 case PIPE_TEXTURE_3D:
174 return V_030000_SQ_TEX_DIM_3D;
175 case PIPE_TEXTURE_CUBE:
176 return V_030000_SQ_TEX_DIM_CUBEMAP;
177 }
178 }
179
180 static uint32_t r600_translate_dbformat(enum pipe_format format)
181 {
182 switch (format) {
183 case PIPE_FORMAT_Z16_UNORM:
184 return V_028040_Z_16;
185 case PIPE_FORMAT_Z24X8_UNORM:
186 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
187 return V_028040_Z_24;
188 case PIPE_FORMAT_Z32_FLOAT:
189 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
190 return V_028040_Z_32_FLOAT;
191 default:
192 return ~0U;
193 }
194 }
195
196 static uint32_t r600_translate_colorswap(enum pipe_format format)
197 {
198 switch (format) {
199 /* 8-bit buffers. */
200 case PIPE_FORMAT_L4A4_UNORM:
201 case PIPE_FORMAT_A4R4_UNORM:
202 return V_028C70_SWAP_ALT;
203
204 case PIPE_FORMAT_A8_UNORM:
205 case PIPE_FORMAT_A8_SNORM:
206 case PIPE_FORMAT_A8_UINT:
207 case PIPE_FORMAT_A8_SINT:
208 case PIPE_FORMAT_A16_UNORM:
209 case PIPE_FORMAT_A16_SNORM:
210 case PIPE_FORMAT_A16_UINT:
211 case PIPE_FORMAT_A16_SINT:
212 case PIPE_FORMAT_A16_FLOAT:
213 case PIPE_FORMAT_A32_UINT:
214 case PIPE_FORMAT_A32_SINT:
215 case PIPE_FORMAT_A32_FLOAT:
216 case PIPE_FORMAT_R4A4_UNORM:
217 return V_028C70_SWAP_ALT_REV;
218 case PIPE_FORMAT_I8_UNORM:
219 case PIPE_FORMAT_I8_SNORM:
220 case PIPE_FORMAT_I8_UINT:
221 case PIPE_FORMAT_I8_SINT:
222 case PIPE_FORMAT_I16_UNORM:
223 case PIPE_FORMAT_I16_SNORM:
224 case PIPE_FORMAT_I16_UINT:
225 case PIPE_FORMAT_I16_SINT:
226 case PIPE_FORMAT_I16_FLOAT:
227 case PIPE_FORMAT_I32_UINT:
228 case PIPE_FORMAT_I32_SINT:
229 case PIPE_FORMAT_I32_FLOAT:
230 case PIPE_FORMAT_L8_UNORM:
231 case PIPE_FORMAT_L8_SNORM:
232 case PIPE_FORMAT_L8_UINT:
233 case PIPE_FORMAT_L8_SINT:
234 case PIPE_FORMAT_L8_SRGB:
235 case PIPE_FORMAT_L16_UNORM:
236 case PIPE_FORMAT_L16_SNORM:
237 case PIPE_FORMAT_L16_UINT:
238 case PIPE_FORMAT_L16_SINT:
239 case PIPE_FORMAT_L16_FLOAT:
240 case PIPE_FORMAT_L32_UINT:
241 case PIPE_FORMAT_L32_SINT:
242 case PIPE_FORMAT_L32_FLOAT:
243 case PIPE_FORMAT_R8_UNORM:
244 case PIPE_FORMAT_R8_SNORM:
245 case PIPE_FORMAT_R8_UINT:
246 case PIPE_FORMAT_R8_SINT:
247 return V_028C70_SWAP_STD;
248
249 /* 16-bit buffers. */
250 case PIPE_FORMAT_B5G6R5_UNORM:
251 return V_028C70_SWAP_STD_REV;
252
253 case PIPE_FORMAT_B5G5R5A1_UNORM:
254 case PIPE_FORMAT_B5G5R5X1_UNORM:
255 return V_028C70_SWAP_ALT;
256
257 case PIPE_FORMAT_B4G4R4A4_UNORM:
258 case PIPE_FORMAT_B4G4R4X4_UNORM:
259 return V_028C70_SWAP_ALT;
260
261 case PIPE_FORMAT_Z16_UNORM:
262 return V_028C70_SWAP_STD;
263
264 case PIPE_FORMAT_L8A8_UNORM:
265 case PIPE_FORMAT_L8A8_SNORM:
266 case PIPE_FORMAT_L8A8_UINT:
267 case PIPE_FORMAT_L8A8_SINT:
268 case PIPE_FORMAT_L8A8_SRGB:
269 case PIPE_FORMAT_L16A16_UNORM:
270 case PIPE_FORMAT_L16A16_SNORM:
271 case PIPE_FORMAT_L16A16_UINT:
272 case PIPE_FORMAT_L16A16_SINT:
273 case PIPE_FORMAT_L16A16_FLOAT:
274 case PIPE_FORMAT_L32A32_UINT:
275 case PIPE_FORMAT_L32A32_SINT:
276 case PIPE_FORMAT_L32A32_FLOAT:
277 return V_028C70_SWAP_ALT;
278 case PIPE_FORMAT_R8G8_UNORM:
279 case PIPE_FORMAT_R8G8_SNORM:
280 case PIPE_FORMAT_R8G8_UINT:
281 case PIPE_FORMAT_R8G8_SINT:
282 return V_028C70_SWAP_STD;
283
284 case PIPE_FORMAT_R16_UNORM:
285 case PIPE_FORMAT_R16_SNORM:
286 case PIPE_FORMAT_R16_UINT:
287 case PIPE_FORMAT_R16_SINT:
288 case PIPE_FORMAT_R16_FLOAT:
289 return V_028C70_SWAP_STD;
290
291 /* 32-bit buffers. */
292 case PIPE_FORMAT_A8B8G8R8_SRGB:
293 return V_028C70_SWAP_STD_REV;
294 case PIPE_FORMAT_B8G8R8A8_SRGB:
295 return V_028C70_SWAP_ALT;
296
297 case PIPE_FORMAT_B8G8R8A8_UNORM:
298 case PIPE_FORMAT_B8G8R8X8_UNORM:
299 return V_028C70_SWAP_ALT;
300
301 case PIPE_FORMAT_A8R8G8B8_UNORM:
302 case PIPE_FORMAT_X8R8G8B8_UNORM:
303 return V_028C70_SWAP_ALT_REV;
304 case PIPE_FORMAT_R8G8B8A8_SNORM:
305 case PIPE_FORMAT_R8G8B8A8_UNORM:
306 case PIPE_FORMAT_R8G8B8A8_SINT:
307 case PIPE_FORMAT_R8G8B8A8_UINT:
308 case PIPE_FORMAT_R8G8B8X8_UNORM:
309 return V_028C70_SWAP_STD;
310
311 case PIPE_FORMAT_A8B8G8R8_UNORM:
312 case PIPE_FORMAT_X8B8G8R8_UNORM:
313 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
314 return V_028C70_SWAP_STD_REV;
315
316 case PIPE_FORMAT_Z24X8_UNORM:
317 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
318 return V_028C70_SWAP_STD;
319
320 case PIPE_FORMAT_X8Z24_UNORM:
321 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
322 return V_028C70_SWAP_STD;
323
324 case PIPE_FORMAT_R10G10B10A2_UNORM:
325 case PIPE_FORMAT_R10G10B10X2_SNORM:
326 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
327 return V_028C70_SWAP_STD;
328
329 case PIPE_FORMAT_B10G10R10A2_UNORM:
330 case PIPE_FORMAT_B10G10R10A2_UINT:
331 return V_028C70_SWAP_ALT;
332
333 case PIPE_FORMAT_R11G11B10_FLOAT:
334 case PIPE_FORMAT_R32_FLOAT:
335 case PIPE_FORMAT_R32_UINT:
336 case PIPE_FORMAT_R32_SINT:
337 case PIPE_FORMAT_Z32_FLOAT:
338 case PIPE_FORMAT_R16G16_FLOAT:
339 case PIPE_FORMAT_R16G16_UNORM:
340 case PIPE_FORMAT_R16G16_SNORM:
341 case PIPE_FORMAT_R16G16_UINT:
342 case PIPE_FORMAT_R16G16_SINT:
343 return V_028C70_SWAP_STD;
344
345 /* 64-bit buffers. */
346 case PIPE_FORMAT_R32G32_FLOAT:
347 case PIPE_FORMAT_R32G32_UINT:
348 case PIPE_FORMAT_R32G32_SINT:
349 case PIPE_FORMAT_R16G16B16A16_UNORM:
350 case PIPE_FORMAT_R16G16B16A16_SNORM:
351 case PIPE_FORMAT_R16G16B16A16_UINT:
352 case PIPE_FORMAT_R16G16B16A16_SINT:
353 case PIPE_FORMAT_R16G16B16A16_FLOAT:
354 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
355
356 /* 128-bit buffers. */
357 case PIPE_FORMAT_R32G32B32A32_FLOAT:
358 case PIPE_FORMAT_R32G32B32A32_SNORM:
359 case PIPE_FORMAT_R32G32B32A32_UNORM:
360 case PIPE_FORMAT_R32G32B32A32_SINT:
361 case PIPE_FORMAT_R32G32B32A32_UINT:
362 return V_028C70_SWAP_STD;
363 default:
364 R600_ERR("unsupported colorswap format %d\n", format);
365 return ~0U;
366 }
367 return ~0U;
368 }
369
370 static uint32_t r600_translate_colorformat(enum pipe_format format)
371 {
372 switch (format) {
373 /* 8-bit buffers. */
374 case PIPE_FORMAT_A8_UNORM:
375 case PIPE_FORMAT_A8_SNORM:
376 case PIPE_FORMAT_A8_UINT:
377 case PIPE_FORMAT_A8_SINT:
378 case PIPE_FORMAT_I8_UNORM:
379 case PIPE_FORMAT_I8_SNORM:
380 case PIPE_FORMAT_I8_UINT:
381 case PIPE_FORMAT_I8_SINT:
382 case PIPE_FORMAT_L8_UNORM:
383 case PIPE_FORMAT_L8_SNORM:
384 case PIPE_FORMAT_L8_UINT:
385 case PIPE_FORMAT_L8_SINT:
386 case PIPE_FORMAT_L8_SRGB:
387 case PIPE_FORMAT_R8_UNORM:
388 case PIPE_FORMAT_R8_SNORM:
389 case PIPE_FORMAT_R8_UINT:
390 case PIPE_FORMAT_R8_SINT:
391 return V_028C70_COLOR_8;
392
393 /* 16-bit buffers. */
394 case PIPE_FORMAT_B5G6R5_UNORM:
395 return V_028C70_COLOR_5_6_5;
396
397 case PIPE_FORMAT_B5G5R5A1_UNORM:
398 case PIPE_FORMAT_B5G5R5X1_UNORM:
399 return V_028C70_COLOR_1_5_5_5;
400
401 case PIPE_FORMAT_B4G4R4A4_UNORM:
402 case PIPE_FORMAT_B4G4R4X4_UNORM:
403 return V_028C70_COLOR_4_4_4_4;
404
405 case PIPE_FORMAT_Z16_UNORM:
406 return V_028C70_COLOR_16;
407
408 case PIPE_FORMAT_L8A8_UNORM:
409 case PIPE_FORMAT_L8A8_SNORM:
410 case PIPE_FORMAT_L8A8_UINT:
411 case PIPE_FORMAT_L8A8_SINT:
412 case PIPE_FORMAT_L8A8_SRGB:
413 case PIPE_FORMAT_R8G8_UNORM:
414 case PIPE_FORMAT_R8G8_SNORM:
415 case PIPE_FORMAT_R8G8_UINT:
416 case PIPE_FORMAT_R8G8_SINT:
417 return V_028C70_COLOR_8_8;
418
419 case PIPE_FORMAT_R16_UNORM:
420 case PIPE_FORMAT_R16_SNORM:
421 case PIPE_FORMAT_R16_UINT:
422 case PIPE_FORMAT_R16_SINT:
423 case PIPE_FORMAT_A16_UNORM:
424 case PIPE_FORMAT_A16_SNORM:
425 case PIPE_FORMAT_A16_UINT:
426 case PIPE_FORMAT_A16_SINT:
427 case PIPE_FORMAT_L16_UNORM:
428 case PIPE_FORMAT_L16_SNORM:
429 case PIPE_FORMAT_L16_UINT:
430 case PIPE_FORMAT_L16_SINT:
431 case PIPE_FORMAT_I16_UNORM:
432 case PIPE_FORMAT_I16_SNORM:
433 case PIPE_FORMAT_I16_UINT:
434 case PIPE_FORMAT_I16_SINT:
435 return V_028C70_COLOR_16;
436
437 case PIPE_FORMAT_R16_FLOAT:
438 case PIPE_FORMAT_A16_FLOAT:
439 case PIPE_FORMAT_L16_FLOAT:
440 case PIPE_FORMAT_I16_FLOAT:
441 return V_028C70_COLOR_16_FLOAT;
442
443 /* 32-bit buffers. */
444 case PIPE_FORMAT_A8B8G8R8_SRGB:
445 case PIPE_FORMAT_A8B8G8R8_UNORM:
446 case PIPE_FORMAT_A8R8G8B8_UNORM:
447 case PIPE_FORMAT_B8G8R8A8_SRGB:
448 case PIPE_FORMAT_B8G8R8A8_UNORM:
449 case PIPE_FORMAT_B8G8R8X8_UNORM:
450 case PIPE_FORMAT_R8G8B8A8_SNORM:
451 case PIPE_FORMAT_R8G8B8A8_UNORM:
452 case PIPE_FORMAT_R8G8B8X8_UNORM:
453 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
454 case PIPE_FORMAT_X8B8G8R8_UNORM:
455 case PIPE_FORMAT_X8R8G8B8_UNORM:
456 case PIPE_FORMAT_R8G8B8_UNORM:
457 case PIPE_FORMAT_R8G8B8A8_SINT:
458 case PIPE_FORMAT_R8G8B8A8_UINT:
459 return V_028C70_COLOR_8_8_8_8;
460
461 case PIPE_FORMAT_R10G10B10A2_UNORM:
462 case PIPE_FORMAT_R10G10B10X2_SNORM:
463 case PIPE_FORMAT_B10G10R10A2_UNORM:
464 case PIPE_FORMAT_B10G10R10A2_UINT:
465 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
466 return V_028C70_COLOR_2_10_10_10;
467
468 case PIPE_FORMAT_Z24X8_UNORM:
469 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
470 return V_028C70_COLOR_8_24;
471
472 case PIPE_FORMAT_X8Z24_UNORM:
473 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
474 return V_028C70_COLOR_24_8;
475
476 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
477 return V_028C70_COLOR_X24_8_32_FLOAT;
478
479 case PIPE_FORMAT_R32_UINT:
480 case PIPE_FORMAT_R32_SINT:
481 case PIPE_FORMAT_A32_UINT:
482 case PIPE_FORMAT_A32_SINT:
483 case PIPE_FORMAT_L32_UINT:
484 case PIPE_FORMAT_L32_SINT:
485 case PIPE_FORMAT_I32_UINT:
486 case PIPE_FORMAT_I32_SINT:
487 return V_028C70_COLOR_32;
488
489 case PIPE_FORMAT_R32_FLOAT:
490 case PIPE_FORMAT_A32_FLOAT:
491 case PIPE_FORMAT_L32_FLOAT:
492 case PIPE_FORMAT_I32_FLOAT:
493 case PIPE_FORMAT_Z32_FLOAT:
494 return V_028C70_COLOR_32_FLOAT;
495
496 case PIPE_FORMAT_R16G16_FLOAT:
497 case PIPE_FORMAT_L16A16_FLOAT:
498 return V_028C70_COLOR_16_16_FLOAT;
499
500 case PIPE_FORMAT_R16G16_UNORM:
501 case PIPE_FORMAT_R16G16_SNORM:
502 case PIPE_FORMAT_R16G16_UINT:
503 case PIPE_FORMAT_R16G16_SINT:
504 case PIPE_FORMAT_L16A16_UNORM:
505 case PIPE_FORMAT_L16A16_SNORM:
506 case PIPE_FORMAT_L16A16_UINT:
507 case PIPE_FORMAT_L16A16_SINT:
508 return V_028C70_COLOR_16_16;
509
510 case PIPE_FORMAT_R11G11B10_FLOAT:
511 return V_028C70_COLOR_10_11_11_FLOAT;
512
513 /* 64-bit buffers. */
514 case PIPE_FORMAT_R16G16B16A16_UINT:
515 case PIPE_FORMAT_R16G16B16A16_SINT:
516 case PIPE_FORMAT_R16G16B16A16_UNORM:
517 case PIPE_FORMAT_R16G16B16A16_SNORM:
518 return V_028C70_COLOR_16_16_16_16;
519
520 case PIPE_FORMAT_R16G16B16A16_FLOAT:
521 return V_028C70_COLOR_16_16_16_16_FLOAT;
522
523 case PIPE_FORMAT_R32G32_FLOAT:
524 case PIPE_FORMAT_L32A32_FLOAT:
525 return V_028C70_COLOR_32_32_FLOAT;
526
527 case PIPE_FORMAT_R32G32_SINT:
528 case PIPE_FORMAT_R32G32_UINT:
529 case PIPE_FORMAT_L32A32_UINT:
530 case PIPE_FORMAT_L32A32_SINT:
531 return V_028C70_COLOR_32_32;
532
533 /* 128-bit buffers. */
534 case PIPE_FORMAT_R32G32B32A32_SNORM:
535 case PIPE_FORMAT_R32G32B32A32_UNORM:
536 case PIPE_FORMAT_R32G32B32A32_SINT:
537 case PIPE_FORMAT_R32G32B32A32_UINT:
538 return V_028C70_COLOR_32_32_32_32;
539 case PIPE_FORMAT_R32G32B32A32_FLOAT:
540 return V_028C70_COLOR_32_32_32_32_FLOAT;
541
542 /* YUV buffers. */
543 case PIPE_FORMAT_UYVY:
544 case PIPE_FORMAT_YUYV:
545 default:
546 return ~0U; /* Unsupported. */
547 }
548 }
549
550 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
551 {
552 if (R600_BIG_ENDIAN) {
553 switch(colorformat) {
554
555 /* 8-bit buffers. */
556 case V_028C70_COLOR_8:
557 return ENDIAN_NONE;
558
559 /* 16-bit buffers. */
560 case V_028C70_COLOR_5_6_5:
561 case V_028C70_COLOR_1_5_5_5:
562 case V_028C70_COLOR_4_4_4_4:
563 case V_028C70_COLOR_16:
564 case V_028C70_COLOR_8_8:
565 return ENDIAN_8IN16;
566
567 /* 32-bit buffers. */
568 case V_028C70_COLOR_8_8_8_8:
569 case V_028C70_COLOR_2_10_10_10:
570 case V_028C70_COLOR_8_24:
571 case V_028C70_COLOR_24_8:
572 case V_028C70_COLOR_32_FLOAT:
573 case V_028C70_COLOR_16_16_FLOAT:
574 case V_028C70_COLOR_16_16:
575 return ENDIAN_8IN32;
576
577 /* 64-bit buffers. */
578 case V_028C70_COLOR_16_16_16_16:
579 case V_028C70_COLOR_16_16_16_16_FLOAT:
580 return ENDIAN_8IN16;
581
582 case V_028C70_COLOR_32_32_FLOAT:
583 case V_028C70_COLOR_32_32:
584 case V_028C70_COLOR_X24_8_32_FLOAT:
585 return ENDIAN_8IN32;
586
587 /* 96-bit buffers. */
588 case V_028C70_COLOR_32_32_32_FLOAT:
589 /* 128-bit buffers. */
590 case V_028C70_COLOR_32_32_32_32_FLOAT:
591 case V_028C70_COLOR_32_32_32_32:
592 return ENDIAN_8IN32;
593 default:
594 return ENDIAN_NONE; /* Unsupported. */
595 }
596 } else {
597 return ENDIAN_NONE;
598 }
599 }
600
601 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
602 {
603 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
604 }
605
606 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
607 {
608 return r600_translate_colorformat(format) != ~0U &&
609 r600_translate_colorswap(format) != ~0U;
610 }
611
612 static bool r600_is_zs_format_supported(enum pipe_format format)
613 {
614 return r600_translate_dbformat(format) != ~0U;
615 }
616
617 boolean evergreen_is_format_supported(struct pipe_screen *screen,
618 enum pipe_format format,
619 enum pipe_texture_target target,
620 unsigned sample_count,
621 unsigned usage)
622 {
623 struct r600_screen *rscreen = (struct r600_screen*)screen;
624 unsigned retval = 0;
625
626 if (target >= PIPE_MAX_TEXTURE_TYPES) {
627 R600_ERR("r600: unsupported texture type %d\n", target);
628 return FALSE;
629 }
630
631 if (!util_format_is_supported(format, usage))
632 return FALSE;
633
634 if (sample_count > 1) {
635 if (rscreen->info.drm_minor < 19)
636 return FALSE;
637
638 switch (sample_count) {
639 case 2:
640 case 4:
641 case 8:
642 break;
643 default:
644 return FALSE;
645 }
646 }
647
648 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
649 r600_is_sampler_format_supported(screen, format)) {
650 retval |= PIPE_BIND_SAMPLER_VIEW;
651 }
652
653 if ((usage & (PIPE_BIND_RENDER_TARGET |
654 PIPE_BIND_DISPLAY_TARGET |
655 PIPE_BIND_SCANOUT |
656 PIPE_BIND_SHARED)) &&
657 r600_is_colorbuffer_format_supported(format)) {
658 retval |= usage &
659 (PIPE_BIND_RENDER_TARGET |
660 PIPE_BIND_DISPLAY_TARGET |
661 PIPE_BIND_SCANOUT |
662 PIPE_BIND_SHARED);
663 }
664
665 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
666 r600_is_zs_format_supported(format)) {
667 retval |= PIPE_BIND_DEPTH_STENCIL;
668 }
669
670 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
671 r600_is_vertex_format_supported(format)) {
672 retval |= PIPE_BIND_VERTEX_BUFFER;
673 }
674
675 if (usage & PIPE_BIND_TRANSFER_READ)
676 retval |= PIPE_BIND_TRANSFER_READ;
677 if (usage & PIPE_BIND_TRANSFER_WRITE)
678 retval |= PIPE_BIND_TRANSFER_WRITE;
679
680 return retval == usage;
681 }
682
683 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
684 const struct pipe_blend_state *state, int mode)
685 {
686 uint32_t color_control = 0, target_mask = 0;
687 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
688
689 if (!blend) {
690 return NULL;
691 }
692
693 r600_init_command_buffer(&blend->buffer, 20);
694 r600_init_command_buffer(&blend->buffer_no_blend, 20);
695
696 if (state->logicop_enable) {
697 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
698 } else {
699 color_control |= (0xcc << 16);
700 }
701 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
702 if (state->independent_blend_enable) {
703 for (int i = 0; i < 8; i++) {
704 target_mask |= (state->rt[i].colormask << (4 * i));
705 }
706 } else {
707 for (int i = 0; i < 8; i++) {
708 target_mask |= (state->rt[0].colormask << (4 * i));
709 }
710 }
711
712 /* only have dual source on MRT0 */
713 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
714 blend->cb_target_mask = target_mask;
715 blend->alpha_to_one = state->alpha_to_one;
716
717 if (target_mask)
718 color_control |= S_028808_MODE(mode);
719 else
720 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
721
722
723 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
724 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
725 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
726 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
727 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
728 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
729 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
730 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
731
732 /* Copy over the dwords set so far into buffer_no_blend.
733 * Only the CB_BLENDi_CONTROL registers must be set after this. */
734 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
735 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
736
737 for (int i = 0; i < 8; i++) {
738 /* state->rt entries > 0 only written if independent blending */
739 const int j = state->independent_blend_enable ? i : 0;
740
741 unsigned eqRGB = state->rt[j].rgb_func;
742 unsigned srcRGB = state->rt[j].rgb_src_factor;
743 unsigned dstRGB = state->rt[j].rgb_dst_factor;
744 unsigned eqA = state->rt[j].alpha_func;
745 unsigned srcA = state->rt[j].alpha_src_factor;
746 unsigned dstA = state->rt[j].alpha_dst_factor;
747 uint32_t bc = 0;
748
749 r600_store_value(&blend->buffer_no_blend, 0);
750
751 if (!state->rt[j].blend_enable) {
752 r600_store_value(&blend->buffer, 0);
753 continue;
754 }
755
756 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
757 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
758 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
759 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
760
761 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
762 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
763 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
764 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
765 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
766 }
767 r600_store_value(&blend->buffer, bc);
768 }
769 return blend;
770 }
771
772 static void *evergreen_create_blend_state(struct pipe_context *ctx,
773 const struct pipe_blend_state *state)
774 {
775
776 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
777 }
778
779 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
780 const struct pipe_depth_stencil_alpha_state *state)
781 {
782 struct r600_context *rctx = (struct r600_context *)ctx;
783 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
784 unsigned db_depth_control, alpha_test_control, alpha_ref;
785 struct r600_pipe_state *rstate;
786
787 if (dsa == NULL) {
788 return NULL;
789 }
790
791 dsa->valuemask[0] = state->stencil[0].valuemask;
792 dsa->valuemask[1] = state->stencil[1].valuemask;
793 dsa->writemask[0] = state->stencil[0].writemask;
794 dsa->writemask[1] = state->stencil[1].writemask;
795
796 rstate = &dsa->rstate;
797
798 rstate->id = R600_PIPE_STATE_DSA;
799 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
800 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
801 S_028800_ZFUNC(state->depth.func);
802
803 /* stencil */
804 if (state->stencil[0].enabled) {
805 db_depth_control |= S_028800_STENCIL_ENABLE(1);
806 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
807 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
808 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
809 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
810
811 if (state->stencil[1].enabled) {
812 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
813 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
814 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
815 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
816 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
817 }
818 }
819
820 /* alpha */
821 alpha_test_control = 0;
822 alpha_ref = 0;
823 if (state->alpha.enabled) {
824 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
825 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
826 alpha_ref = fui(state->alpha.ref_value);
827 }
828 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
829 dsa->alpha_ref = alpha_ref;
830
831 /* misc */
832 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
833 return rstate;
834 }
835
836 static void *evergreen_create_rs_state(struct pipe_context *ctx,
837 const struct pipe_rasterizer_state *state)
838 {
839 struct r600_context *rctx = (struct r600_context *)ctx;
840 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
841 struct r600_pipe_state *rstate;
842 unsigned tmp;
843 unsigned prov_vtx = 1, polygon_dual_mode;
844 float psize_min, psize_max;
845
846 if (rs == NULL) {
847 return NULL;
848 }
849
850 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
851 state->fill_back != PIPE_POLYGON_MODE_FILL);
852
853 if (state->flatshade_first)
854 prov_vtx = 0;
855
856 rstate = &rs->rstate;
857 rs->flatshade = state->flatshade;
858 rs->sprite_coord_enable = state->sprite_coord_enable;
859 rs->two_side = state->light_twoside;
860 rs->clip_plane_enable = state->clip_plane_enable;
861 rs->pa_sc_line_stipple = state->line_stipple_enable ?
862 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
863 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
864 rs->pa_cl_clip_cntl =
865 S_028810_PS_UCP_MODE(3) |
866 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
867 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
868 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
869 rs->multisample_enable = state->multisample;
870
871 /* offset */
872 rs->offset_units = state->offset_units;
873 rs->offset_scale = state->offset_scale * 12.0f;
874 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
875
876 rstate->id = R600_PIPE_STATE_RASTERIZER;
877 tmp = S_0286D4_FLAT_SHADE_ENA(1);
878 if (state->sprite_coord_enable) {
879 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
880 S_0286D4_PNT_SPRITE_OVRD_X(2) |
881 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
882 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
883 S_0286D4_PNT_SPRITE_OVRD_W(1);
884 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
885 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
886 }
887 }
888 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
889
890 /* point size 12.4 fixed point */
891 tmp = (unsigned)(state->point_size * 8.0);
892 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
893
894 if (state->point_size_per_vertex) {
895 psize_min = util_get_min_point_size(state);
896 psize_max = 8192;
897 } else {
898 /* Force the point size to be as if the vertex output was disabled. */
899 psize_min = state->point_size;
900 psize_max = state->point_size;
901 }
902 /* Divide by two, because 0.5 = 1 pixel. */
903 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
904 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
905 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
906
907 tmp = (unsigned)state->line_width * 8;
908 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
909 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
910 S_028A48_MSAA_ENABLE(state->multisample) |
911 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
912 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
913
914 if (rctx->chip_class == CAYMAN) {
915 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
916 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
917 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
918 } else {
919 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
920 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
921 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
922 }
923 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
924 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
925 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
926 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
927 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
928 S_028814_FACE(!state->front_ccw) |
929 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
930 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
931 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
932 S_028814_POLY_MODE(polygon_dual_mode) |
933 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
934 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
935 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
936 return rstate;
937 }
938
939 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
940 const struct pipe_sampler_state *state)
941 {
942 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
943 union util_color uc;
944 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
945
946 if (ss == NULL) {
947 return NULL;
948 }
949
950 /* directly into sampler avoid r6xx code to emit useless reg */
951 ss->seamless_cube_map = false;
952 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
953 ss->border_color_use = false;
954 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
955 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
956 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
957 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
958 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
959 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
960 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
961 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
962 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
963 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
964 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
965 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
966 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
967 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
968 ss->tex_sampler_words[2] = S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
969 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
970 S_03C008_TYPE(1);
971 if (uc.ui) {
972 ss->border_color_use = true;
973 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
974 ss->border_color[0] = fui(state->border_color.f[0]);
975 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
976 ss->border_color[1] = fui(state->border_color.f[1]);
977 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
978 ss->border_color[2] = fui(state->border_color.f[2]);
979 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
980 ss->border_color[3] = fui(state->border_color.f[3]);
981 }
982 return ss;
983 }
984
985 struct pipe_sampler_view *
986 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
987 struct pipe_resource *texture,
988 const struct pipe_sampler_view *state,
989 unsigned width0, unsigned height0)
990 {
991 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
992 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
993 struct r600_texture *tmp = (struct r600_texture*)texture;
994 unsigned format, endian;
995 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
996 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
997 unsigned height, depth, width;
998 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
999
1000 if (view == NULL)
1001 return NULL;
1002
1003 /* initialize base object */
1004 view->base = *state;
1005 view->base.texture = NULL;
1006 pipe_reference(NULL, &texture->reference);
1007 view->base.texture = texture;
1008 view->base.reference.count = 1;
1009 view->base.context = ctx;
1010
1011 swizzle[0] = state->swizzle_r;
1012 swizzle[1] = state->swizzle_g;
1013 swizzle[2] = state->swizzle_b;
1014 swizzle[3] = state->swizzle_a;
1015
1016 format = r600_translate_texformat(ctx->screen, state->format,
1017 swizzle,
1018 &word4, &yuv_format);
1019 assert(format != ~0);
1020 if (format == ~0) {
1021 FREE(view);
1022 return NULL;
1023 }
1024
1025 if (tmp->is_depth && !tmp->is_flushing_texture) {
1026 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1027 FREE(view);
1028 return NULL;
1029 }
1030 tmp = tmp->flushed_depth_texture;
1031 }
1032
1033 endian = r600_colorformat_endian_swap(format);
1034
1035 width = width0;
1036 height = height0;
1037 depth = tmp->surface.level[0].npix_z;
1038 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1039 tile_type = tmp->tile_type;
1040
1041 switch (tmp->surface.level[0].mode) {
1042 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1043 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1044 break;
1045 case RADEON_SURF_MODE_2D:
1046 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1047 break;
1048 case RADEON_SURF_MODE_1D:
1049 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1050 break;
1051 case RADEON_SURF_MODE_LINEAR:
1052 default:
1053 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1054 break;
1055 }
1056 tile_split = tmp->surface.tile_split;
1057 macro_aspect = tmp->surface.mtilea;
1058 bankw = tmp->surface.bankw;
1059 bankh = tmp->surface.bankh;
1060 tile_split = eg_tile_split(tile_split);
1061 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1062 bankw = eg_bank_wh(bankw);
1063 bankh = eg_bank_wh(bankh);
1064
1065 /* 128 bit formats require tile type = 1 */
1066 if (rscreen->chip_class == CAYMAN) {
1067 if (util_format_get_blocksize(state->format) >= 16)
1068 tile_type = 1;
1069 }
1070 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1071
1072 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1073 height = 1;
1074 depth = texture->array_size;
1075 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1076 depth = texture->array_size;
1077 }
1078
1079 view->tex_resource = &tmp->resource;
1080 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1081 S_030000_PITCH((pitch / 8) - 1) |
1082 S_030000_TEX_WIDTH(width - 1));
1083 if (rscreen->chip_class == CAYMAN)
1084 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1085 else
1086 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1087 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1088 S_030004_TEX_DEPTH(depth - 1) |
1089 S_030004_ARRAY_MODE(array_mode));
1090 view->tex_resource_words[2] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1091 if (state->u.tex.last_level && texture->nr_samples <= 1) {
1092 view->tex_resource_words[3] = (tmp->surface.level[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1093 } else {
1094 view->tex_resource_words[3] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1095 }
1096 view->tex_resource_words[4] = (word4 |
1097 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1098 S_030010_ENDIAN_SWAP(endian));
1099 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1100 S_030014_LAST_ARRAY(state->u.tex.last_layer);
1101 if (texture->nr_samples > 1) {
1102 unsigned log_samples = util_logbase2(texture->nr_samples);
1103 if (rscreen->chip_class == CAYMAN) {
1104 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
1105 }
1106 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1107 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
1108 } else {
1109 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(state->u.tex.first_level);
1110 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(state->u.tex.last_level);
1111 }
1112 /* aniso max 16 samples */
1113 view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
1114 (S_030018_TILE_SPLIT(tile_split));
1115 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1116 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1117 S_03001C_BANK_WIDTH(bankw) |
1118 S_03001C_BANK_HEIGHT(bankh) |
1119 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1120 S_03001C_NUM_BANKS(nbanks);
1121 return &view->base;
1122 }
1123
1124 static struct pipe_sampler_view *
1125 evergreen_create_sampler_view(struct pipe_context *ctx,
1126 struct pipe_resource *tex,
1127 const struct pipe_sampler_view *state)
1128 {
1129 return evergreen_create_sampler_view_custom(ctx, tex, state,
1130 tex->width0, tex->height0);
1131 }
1132
1133 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1134 {
1135 struct radeon_winsys_cs *cs = rctx->cs;
1136 struct pipe_clip_state *state = &rctx->clip_state.state;
1137
1138 r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
1139 r600_write_array(cs, 6*4, (unsigned*)state);
1140 }
1141
1142 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1143 const struct pipe_poly_stipple *state)
1144 {
1145 }
1146
1147 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1148 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1149 uint32_t *tl, uint32_t *br)
1150 {
1151 /* EG hw workaround */
1152 if (br_x == 0)
1153 tl_x = 1;
1154 if (br_y == 0)
1155 tl_y = 1;
1156
1157 /* cayman hw workaround */
1158 if (rctx->chip_class == CAYMAN) {
1159 if (br_x == 1 && br_y == 1)
1160 br_x = 2;
1161 }
1162
1163 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1164 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1165 }
1166
1167 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1168 const struct pipe_scissor_state *state)
1169 {
1170 struct r600_context *rctx = (struct r600_context *)ctx;
1171
1172 rctx->scissor.scissor = *state;
1173 rctx->scissor.atom.dirty = true;
1174 }
1175
1176 static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
1177 {
1178 struct radeon_winsys_cs *cs = rctx->cs;
1179 struct pipe_scissor_state *state = &rctx->scissor.scissor;
1180 uint32_t tl, br;
1181
1182 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1183
1184 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1185 r600_write_value(cs, tl);
1186 r600_write_value(cs, br);
1187 }
1188
1189 /**
1190 * This function intializes the CB* register values for RATs. It is meant
1191 * to be used for 1D aligned buffers that do not have an associated
1192 * radeon_surface.
1193 */
1194 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1195 struct r600_surface *surf)
1196 {
1197 struct pipe_resource *pipe_buffer = surf->base.texture;
1198 unsigned format = r600_translate_colorformat(surf->base.format);
1199 unsigned endian = r600_colorformat_endian_swap(format);
1200 unsigned swap = r600_translate_colorswap(surf->base.format);
1201 unsigned block_size =
1202 align(util_format_get_blocksize(pipe_buffer->format), 4);
1203 unsigned pitch_alignment =
1204 MAX2(64, rctx->screen->tiling_info.group_bytes / block_size);
1205 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
1206
1207 /* XXX: This is copied from evergreen_init_color_surface(). I don't
1208 * know why this is necessary.
1209 */
1210 if (pipe_buffer->usage == PIPE_USAGE_STAGING) {
1211 endian = ENDIAN_NONE;
1212 }
1213
1214 surf->cb_color_base =
1215 r600_resource_va(rctx->context.screen, pipe_buffer) >> 8;
1216
1217 surf->cb_color_pitch = (pitch / 8) - 1;
1218
1219 surf->cb_color_slice = 0;
1220
1221 surf->cb_color_view = 0;
1222
1223 surf->cb_color_info =
1224 S_028C70_ENDIAN(endian)
1225 | S_028C70_FORMAT(format)
1226 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
1227 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
1228 | S_028C70_COMP_SWAP(swap)
1229 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
1230 * are using NUMBER_UINT */
1231 | S_028C70_RAT(1)
1232 ;
1233
1234 surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1235
1236 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
1237 * elements. */
1238 surf->cb_color_dim = pipe_buffer->width0;
1239
1240 surf->cb_color_cmask = surf->cb_color_base;
1241 surf->cb_color_cmask_slice = 0;
1242 surf->cb_color_fmask = surf->cb_color_base;
1243 surf->cb_color_fmask_slice = 0;
1244 }
1245
1246 void evergreen_init_color_surface(struct r600_context *rctx,
1247 struct r600_surface *surf)
1248 {
1249 struct r600_screen *rscreen = rctx->screen;
1250 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1251 struct pipe_resource *pipe_tex = surf->base.texture;
1252 unsigned level = surf->base.u.tex.level;
1253 unsigned pitch, slice;
1254 unsigned color_info, color_attrib, color_dim = 0;
1255 unsigned format, swap, ntype, endian;
1256 uint64_t offset, base_offset;
1257 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1258 const struct util_format_description *desc;
1259 int i;
1260 bool blend_clamp = 0, blend_bypass = 0;
1261
1262 if (rtex->is_depth && !rtex->is_flushing_texture) {
1263 r600_init_flushed_depth_texture(&rctx->context, pipe_tex, NULL);
1264 rtex = rtex->flushed_depth_texture;
1265 assert(rtex);
1266 }
1267
1268 offset = rtex->surface.level[level].offset;
1269 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1270 offset += rtex->surface.level[level].slice_size *
1271 surf->base.u.tex.first_layer;
1272 }
1273 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1274 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1275 if (slice) {
1276 slice = slice - 1;
1277 }
1278 color_info = 0;
1279 switch (rtex->surface.level[level].mode) {
1280 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1281 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1282 tile_type = 1;
1283 break;
1284 case RADEON_SURF_MODE_1D:
1285 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1286 tile_type = rtex->tile_type;
1287 break;
1288 case RADEON_SURF_MODE_2D:
1289 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1290 tile_type = rtex->tile_type;
1291 break;
1292 case RADEON_SURF_MODE_LINEAR:
1293 default:
1294 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1295 tile_type = 1;
1296 break;
1297 }
1298 tile_split = rtex->surface.tile_split;
1299 macro_aspect = rtex->surface.mtilea;
1300 bankw = rtex->surface.bankw;
1301 bankh = rtex->surface.bankh;
1302 fmask_bankh = rtex->fmask_bank_height;
1303 tile_split = eg_tile_split(tile_split);
1304 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1305 bankw = eg_bank_wh(bankw);
1306 bankh = eg_bank_wh(bankh);
1307 fmask_bankh = eg_bank_wh(fmask_bankh);
1308
1309 /* 128 bit formats require tile type = 1 */
1310 if (rscreen->chip_class == CAYMAN) {
1311 if (util_format_get_blocksize(surf->base.format) >= 16)
1312 tile_type = 1;
1313 }
1314 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1315 desc = util_format_description(surf->base.format);
1316 for (i = 0; i < 4; i++) {
1317 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1318 break;
1319 }
1320 }
1321
1322 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1323 S_028C74_NUM_BANKS(nbanks) |
1324 S_028C74_BANK_WIDTH(bankw) |
1325 S_028C74_BANK_HEIGHT(bankh) |
1326 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1327 S_028C74_NON_DISP_TILING_ORDER(tile_type) |
1328 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1329
1330 if (rctx->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1331 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1332 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1333 S_028C74_NUM_FRAGMENTS(log_samples);
1334 }
1335
1336 ntype = V_028C70_NUMBER_UNORM;
1337 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1338 ntype = V_028C70_NUMBER_SRGB;
1339 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1340 if (desc->channel[i].normalized)
1341 ntype = V_028C70_NUMBER_SNORM;
1342 else if (desc->channel[i].pure_integer)
1343 ntype = V_028C70_NUMBER_SINT;
1344 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1345 if (desc->channel[i].normalized)
1346 ntype = V_028C70_NUMBER_UNORM;
1347 else if (desc->channel[i].pure_integer)
1348 ntype = V_028C70_NUMBER_UINT;
1349 }
1350
1351 format = r600_translate_colorformat(surf->base.format);
1352 assert(format != ~0);
1353
1354 swap = r600_translate_colorswap(surf->base.format);
1355 assert(swap != ~0);
1356
1357 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1358 endian = ENDIAN_NONE;
1359 } else {
1360 endian = r600_colorformat_endian_swap(format);
1361 }
1362
1363 /* blend clamp should be set for all NORM/SRGB types */
1364 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1365 ntype == V_028C70_NUMBER_SRGB)
1366 blend_clamp = 1;
1367
1368 /* set blend bypass according to docs if SINT/UINT or
1369 8/24 COLOR variants */
1370 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1371 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1372 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1373 blend_clamp = 0;
1374 blend_bypass = 1;
1375 }
1376
1377 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1378
1379 color_info |= S_028C70_FORMAT(format) |
1380 S_028C70_COMP_SWAP(swap) |
1381 S_028C70_BLEND_CLAMP(blend_clamp) |
1382 S_028C70_BLEND_BYPASS(blend_bypass) |
1383 S_028C70_NUMBER_TYPE(ntype) |
1384 S_028C70_ENDIAN(endian);
1385
1386 if (rtex->is_rat) {
1387 color_info |= S_028C70_RAT(1);
1388 color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0 & 0xffff)
1389 | S_028C78_HEIGHT_MAX((pipe_tex->width0 >> 16) & 0xffff);
1390 }
1391
1392 /* EXPORT_NORM is an optimzation that can be enabled for better
1393 * performance in certain cases.
1394 * EXPORT_NORM can be enabled if:
1395 * - 11-bit or smaller UNORM/SNORM/SRGB
1396 * - 16-bit or smaller FLOAT
1397 */
1398 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1399 ((desc->channel[i].size < 12 &&
1400 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1401 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1402 (desc->channel[i].size < 17 &&
1403 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1404 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1405 surf->export_16bpc = true;
1406 }
1407
1408 if (rtex->fmask_size && rtex->cmask_size) {
1409 color_info |= S_028C70_COMPRESSION(1) | S_028C70_FAST_CLEAR(1);
1410 }
1411
1412 base_offset = r600_resource_va(rctx->context.screen, pipe_tex);
1413
1414 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1415 surf->cb_color_base = (base_offset + offset) >> 8;
1416 surf->cb_color_dim = color_dim;
1417 surf->cb_color_info = color_info;
1418 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1419 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1420 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1421 surf->cb_color_view = 0;
1422 } else {
1423 surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1424 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1425 }
1426 surf->cb_color_attrib = color_attrib;
1427 if (rtex->fmask_size && rtex->cmask_size) {
1428 surf->cb_color_fmask = (base_offset + rtex->fmask_offset) >> 8;
1429 surf->cb_color_cmask = (base_offset + rtex->cmask_offset) >> 8;
1430 } else {
1431 surf->cb_color_fmask = surf->cb_color_base;
1432 surf->cb_color_cmask = surf->cb_color_base;
1433 }
1434 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1435 surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask_slice_tile_max);
1436
1437 surf->color_initialized = true;
1438 }
1439
1440 static void evergreen_init_depth_surface(struct r600_context *rctx,
1441 struct r600_surface *surf)
1442 {
1443 struct r600_screen *rscreen = rctx->screen;
1444 struct pipe_screen *screen = &rscreen->screen;
1445 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1446 uint64_t offset;
1447 unsigned level, pitch, slice, format, array_mode;
1448 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1449
1450 level = surf->base.u.tex.level;
1451 format = r600_translate_dbformat(surf->base.format);
1452 assert(format != ~0);
1453
1454 offset = r600_resource_va(screen, surf->base.texture);
1455 offset += rtex->surface.level[level].offset;
1456 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1457 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1458 if (slice) {
1459 slice = slice - 1;
1460 }
1461 switch (rtex->surface.level[level].mode) {
1462 case RADEON_SURF_MODE_2D:
1463 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1464 break;
1465 case RADEON_SURF_MODE_1D:
1466 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1467 case RADEON_SURF_MODE_LINEAR:
1468 default:
1469 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1470 break;
1471 }
1472 tile_split = rtex->surface.tile_split;
1473 macro_aspect = rtex->surface.mtilea;
1474 bankw = rtex->surface.bankw;
1475 bankh = rtex->surface.bankh;
1476 tile_split = eg_tile_split(tile_split);
1477 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1478 bankw = eg_bank_wh(bankw);
1479 bankh = eg_bank_wh(bankh);
1480 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1481 offset >>= 8;
1482
1483 surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1484 S_028040_FORMAT(format) |
1485 S_028040_TILE_SPLIT(tile_split)|
1486 S_028040_NUM_BANKS(nbanks) |
1487 S_028040_BANK_WIDTH(bankw) |
1488 S_028040_BANK_HEIGHT(bankh) |
1489 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1490 if (rscreen->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1491 surf->db_depth_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1492 }
1493 surf->db_depth_base = offset;
1494 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1495 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1496 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1497 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1498
1499 switch (surf->base.format) {
1500 case PIPE_FORMAT_Z24X8_UNORM:
1501 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1502 surf->pa_su_poly_offset_db_fmt_cntl =
1503 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1504 break;
1505 case PIPE_FORMAT_Z32_FLOAT:
1506 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1507 surf->pa_su_poly_offset_db_fmt_cntl =
1508 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1509 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1510 break;
1511 case PIPE_FORMAT_Z16_UNORM:
1512 surf->pa_su_poly_offset_db_fmt_cntl =
1513 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1514 break;
1515 default:;
1516 }
1517
1518 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1519 uint64_t stencil_offset = rtex->surface.stencil_offset;
1520 unsigned i, stile_split = rtex->surface.stencil_tile_split;
1521
1522 stile_split = eg_tile_split(stile_split);
1523 stencil_offset += r600_resource_va(screen, surf->base.texture);
1524 stencil_offset += rtex->surface.level[level].offset / 4;
1525 stencil_offset >>= 8;
1526
1527 /* We're guessing the stencil offset from the depth offset.
1528 * Make sure each mipmap level has a unique offset. */
1529 for (i = 1; i <= level; i++) {
1530 /* If two levels have the same address, add 256
1531 * to the offset of the smaller level. */
1532 if ((rtex->surface.level[i-1].offset / 4) >> 8 ==
1533 (rtex->surface.level[i].offset / 4) >> 8) {
1534 stencil_offset++;
1535 }
1536 }
1537
1538 surf->db_stencil_base = stencil_offset;
1539 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1540 S_028044_TILE_SPLIT(stile_split);
1541 } else {
1542 surf->db_stencil_base = offset;
1543 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1544 * Older kernels are out of luck. */
1545 surf->db_stencil_info = rctx->screen->info.drm_minor >= 18 ?
1546 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1547 S_028044_FORMAT(V_028044_STENCIL_8);
1548 }
1549
1550 surf->depth_initialized = true;
1551 }
1552
1553 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1554 const struct pipe_framebuffer_state *state)
1555 {
1556 struct r600_context *rctx = (struct r600_context *)ctx;
1557 struct r600_surface *surf;
1558 struct r600_texture *rtex;
1559 uint32_t i, log_samples;
1560
1561 if (rctx->framebuffer.state.nr_cbufs) {
1562 rctx->flags |= R600_CONTEXT_CB_FLUSH;
1563
1564 if (rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1565 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1566 }
1567 }
1568 if (rctx->framebuffer.state.zsbuf) {
1569 rctx->flags |= R600_CONTEXT_DB_FLUSH;
1570 }
1571
1572 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1573
1574 /* Colorbuffers. */
1575 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1576 rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1577 util_format_is_pure_integer(state->cbufs[0]->format);
1578 rctx->framebuffer.compressed_cb_mask = 0;
1579
1580 if (state->nr_cbufs)
1581 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1582 else if (state->zsbuf)
1583 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1584 else
1585 rctx->framebuffer.nr_samples = 0;
1586
1587 for (i = 0; i < state->nr_cbufs; i++) {
1588 surf = (struct r600_surface*)state->cbufs[i];
1589 rtex = (struct r600_texture*)surf->base.texture;
1590
1591 if (!surf->color_initialized) {
1592 evergreen_init_color_surface(rctx, surf);
1593 }
1594
1595 if (!surf->export_16bpc) {
1596 rctx->framebuffer.export_16bpc = false;
1597 }
1598
1599 /* Cayman can fetch from a compressed MSAA colorbuffer,
1600 * so it's pointless to track them. */
1601 if (rctx->chip_class != CAYMAN && rtex->fmask_size && rtex->cmask_size) {
1602 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1603 }
1604 }
1605
1606 /* Update alpha-test state dependencies.
1607 * Alpha-test is done on the first colorbuffer only. */
1608 if (state->nr_cbufs) {
1609 surf = (struct r600_surface*)state->cbufs[0];
1610 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1611 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1612 rctx->alphatest_state.atom.dirty = true;
1613 }
1614 if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
1615 rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
1616 rctx->alphatest_state.atom.dirty = true;
1617 }
1618 }
1619
1620 /* ZS buffer. */
1621 if (state->zsbuf) {
1622 surf = (struct r600_surface*)state->zsbuf;
1623
1624 if (!surf->depth_initialized) {
1625 evergreen_init_depth_surface(rctx, surf);
1626 }
1627
1628 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1629 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1630 rctx->poly_offset_state.atom.dirty = true;
1631 }
1632 }
1633
1634 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1635 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1636 rctx->cb_misc_state.atom.dirty = true;
1637 }
1638
1639 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1640 rctx->alphatest_state.bypass = false;
1641 rctx->alphatest_state.atom.dirty = true;
1642 }
1643
1644 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1645 if (rctx->chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) {
1646 rctx->db_misc_state.log_samples = log_samples;
1647 rctx->db_misc_state.atom.dirty = true;
1648 }
1649
1650 /* Calculate the CS size. */
1651 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1652
1653 /* MSAA. */
1654 if (rctx->chip_class == EVERGREEN) {
1655 switch (rctx->framebuffer.nr_samples) {
1656 case 2:
1657 case 4:
1658 rctx->framebuffer.atom.num_dw += 6;
1659 break;
1660 case 8:
1661 rctx->framebuffer.atom.num_dw += 10;
1662 break;
1663 }
1664 rctx->framebuffer.atom.num_dw += 4;
1665 } else {
1666 switch (rctx->framebuffer.nr_samples) {
1667 case 2:
1668 case 4:
1669 rctx->framebuffer.atom.num_dw += 12;
1670 break;
1671 case 8:
1672 rctx->framebuffer.atom.num_dw += 16;
1673 break;
1674 case 16:
1675 rctx->framebuffer.atom.num_dw += 18;
1676 break;
1677 }
1678 rctx->framebuffer.atom.num_dw += 7;
1679 }
1680
1681 /* Colorbuffers. */
1682 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 21;
1683 if (rctx->keep_tiling_flags)
1684 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1685 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1686
1687 /* ZS buffer. */
1688 if (state->zsbuf) {
1689 rctx->framebuffer.atom.num_dw += 24;
1690 if (rctx->keep_tiling_flags)
1691 rctx->framebuffer.atom.num_dw += 2;
1692 } else if (rctx->screen->info.drm_minor >= 18) {
1693 rctx->framebuffer.atom.num_dw += 4;
1694 }
1695
1696 rctx->framebuffer.atom.dirty = true;
1697 }
1698
1699 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1700 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1701 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1702 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1703 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1704
1705 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1706 {
1707 /* 2xMSAA
1708 * There are two locations (-4, 4), (4, -4). */
1709 static uint32_t sample_locs_2x[] = {
1710 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1711 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1712 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1713 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1714 };
1715 static unsigned max_dist_2x = 4;
1716 /* 4xMSAA
1717 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1718 static uint32_t sample_locs_4x[] = {
1719 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1720 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1721 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1722 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1723 };
1724 static unsigned max_dist_4x = 6;
1725 /* 8xMSAA */
1726 static uint32_t sample_locs_8x[] = {
1727 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1728 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1729 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1730 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1731 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1732 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1733 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1734 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1735 };
1736 static unsigned max_dist_8x = 8;
1737
1738 struct radeon_winsys_cs *cs = rctx->cs;
1739 unsigned max_dist = 0;
1740
1741 switch (nr_samples) {
1742 default:
1743 nr_samples = 0;
1744 break;
1745 case 2:
1746 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_2x));
1747 r600_write_array(cs, Elements(sample_locs_2x), sample_locs_2x);
1748 max_dist = max_dist_2x;
1749 break;
1750 case 4:
1751 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_4x));
1752 r600_write_array(cs, Elements(sample_locs_4x), sample_locs_4x);
1753 max_dist = max_dist_4x;
1754 break;
1755 case 8:
1756 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1757 r600_write_array(cs, Elements(sample_locs_8x), sample_locs_8x);
1758 max_dist = max_dist_8x;
1759 break;
1760 }
1761
1762 if (nr_samples > 1) {
1763 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1764 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1765 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1766 r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1767 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1768 } else {
1769 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1770 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1771 r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1772 }
1773 }
1774
1775 static void cayman_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1776 {
1777 /* 2xMSAA
1778 * There are two locations (-4, 4), (4, -4). */
1779 static uint32_t sample_locs_2x[] = {
1780 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1781 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1782 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1783 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1784 };
1785 static unsigned max_dist_2x = 4;
1786 /* 4xMSAA
1787 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1788 static uint32_t sample_locs_4x[] = {
1789 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1790 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1791 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1792 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1793 };
1794 static unsigned max_dist_4x = 6;
1795 /* 8xMSAA */
1796 static uint32_t sample_locs_8x[] = {
1797 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1798 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1799 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1800 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1801 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1802 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1803 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1804 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1805 };
1806 static unsigned max_dist_8x = 8;
1807 /* 16xMSAA */
1808 static uint32_t sample_locs_16x[] = {
1809 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1810 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1811 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1812 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1813 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1814 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1815 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1816 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1817 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1818 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1819 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1820 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1821 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1822 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1823 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1824 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1825 };
1826 static unsigned max_dist_16x = 8;
1827
1828 struct radeon_winsys_cs *cs = rctx->cs;
1829 unsigned max_dist = 0;
1830
1831 switch (nr_samples) {
1832 default:
1833 nr_samples = 0;
1834 break;
1835 case 2:
1836 r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
1837 r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
1838 r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
1839 r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
1840 max_dist = max_dist_2x;
1841 break;
1842 case 4:
1843 r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
1844 r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
1845 r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
1846 r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
1847 max_dist = max_dist_4x;
1848 break;
1849 case 8:
1850 r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1851 r600_write_value(cs, sample_locs_8x[0]);
1852 r600_write_value(cs, sample_locs_8x[4]);
1853 r600_write_value(cs, 0);
1854 r600_write_value(cs, 0);
1855 r600_write_value(cs, sample_locs_8x[1]);
1856 r600_write_value(cs, sample_locs_8x[5]);
1857 r600_write_value(cs, 0);
1858 r600_write_value(cs, 0);
1859 r600_write_value(cs, sample_locs_8x[2]);
1860 r600_write_value(cs, sample_locs_8x[6]);
1861 r600_write_value(cs, 0);
1862 r600_write_value(cs, 0);
1863 r600_write_value(cs, sample_locs_8x[3]);
1864 r600_write_value(cs, sample_locs_8x[7]);
1865 max_dist = max_dist_8x;
1866 break;
1867 case 16:
1868 r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1869 r600_write_value(cs, sample_locs_16x[0]);
1870 r600_write_value(cs, sample_locs_16x[4]);
1871 r600_write_value(cs, sample_locs_16x[8]);
1872 r600_write_value(cs, sample_locs_16x[12]);
1873 r600_write_value(cs, sample_locs_16x[1]);
1874 r600_write_value(cs, sample_locs_16x[5]);
1875 r600_write_value(cs, sample_locs_16x[9]);
1876 r600_write_value(cs, sample_locs_16x[13]);
1877 r600_write_value(cs, sample_locs_16x[2]);
1878 r600_write_value(cs, sample_locs_16x[6]);
1879 r600_write_value(cs, sample_locs_16x[10]);
1880 r600_write_value(cs, sample_locs_16x[14]);
1881 r600_write_value(cs, sample_locs_16x[3]);
1882 r600_write_value(cs, sample_locs_16x[7]);
1883 r600_write_value(cs, sample_locs_16x[11]);
1884 r600_write_value(cs, sample_locs_16x[15]);
1885 max_dist = max_dist_16x;
1886 break;
1887 }
1888
1889 if (nr_samples > 1) {
1890 unsigned log_samples = util_logbase2(nr_samples);
1891
1892 r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
1893 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1894 S_028C00_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1895 r600_write_value(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1896 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
1897 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1898
1899 r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
1900 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1901 S_028804_PS_ITER_SAMPLES(log_samples) |
1902 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1903 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
1904 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1905 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1906 } else {
1907 r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
1908 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1909 r600_write_value(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1910
1911 r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
1912 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1913 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1914 }
1915 }
1916
1917 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1918 {
1919 struct radeon_winsys_cs *cs = rctx->cs;
1920 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1921 unsigned nr_cbufs = state->nr_cbufs;
1922 unsigned i, tl, br;
1923
1924 /* XXX support more colorbuffers once we need them */
1925 assert(nr_cbufs <= 8);
1926 if (nr_cbufs > 8)
1927 nr_cbufs = 8;
1928
1929 /* Colorbuffers. */
1930 for (i = 0; i < nr_cbufs; i++) {
1931 struct r600_surface *cb = (struct r600_surface*)state->cbufs[i];
1932 unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)cb->base.texture,
1933 RADEON_USAGE_READWRITE);
1934
1935 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 11);
1936 r600_write_value(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1937 r600_write_value(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1938 r600_write_value(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1939 r600_write_value(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1940 r600_write_value(cs, cb->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1941 r600_write_value(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1942 r600_write_value(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1943 r600_write_value(cs, cb->cb_color_cmask); /* R_028C7C_CB_COLOR0_CMASK */
1944 r600_write_value(cs, cb->cb_color_cmask_slice); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1945 r600_write_value(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1946 r600_write_value(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1947
1948 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1949 r600_write_value(cs, reloc);
1950
1951 if (!rctx->keep_tiling_flags) {
1952 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1953 r600_write_value(cs, reloc);
1954 }
1955
1956 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1957 r600_write_value(cs, reloc);
1958
1959 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1960 r600_write_value(cs, reloc);
1961
1962 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1963 r600_write_value(cs, reloc);
1964 }
1965 /* set CB_COLOR1_INFO for possible dual-src blending */
1966 if (i == 1 && !((struct r600_texture*)state->cbufs[0]->texture)->is_rat) {
1967 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1968 ((struct r600_surface*)state->cbufs[0])->cb_color_info);
1969
1970 if (!rctx->keep_tiling_flags) {
1971 unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)state->cbufs[0]->texture,
1972 RADEON_USAGE_READWRITE);
1973
1974 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1975 r600_write_value(cs, reloc);
1976 }
1977 i++;
1978 }
1979 if (rctx->keep_tiling_flags) {
1980 for (; i < 8 ; i++) {
1981 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1982 }
1983 for (; i < 12; i++) {
1984 r600_write_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1985 }
1986 }
1987
1988 /* ZS buffer. */
1989 if (state->zsbuf) {
1990 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1991 unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)state->zsbuf->texture,
1992 RADEON_USAGE_READWRITE);
1993
1994 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1995 zb->pa_su_poly_offset_db_fmt_cntl);
1996 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1997
1998 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1999 r600_write_value(cs, zb->db_depth_info); /* R_028040_DB_Z_INFO */
2000 r600_write_value(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2001 r600_write_value(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2002 r600_write_value(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2003 r600_write_value(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2004 r600_write_value(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2005 r600_write_value(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2006 r600_write_value(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2007
2008 if (!rctx->keep_tiling_flags) {
2009 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
2010 r600_write_value(cs, reloc);
2011 }
2012
2013 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
2014 r600_write_value(cs, reloc);
2015
2016 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
2017 r600_write_value(cs, reloc);
2018
2019 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
2020 r600_write_value(cs, reloc);
2021
2022 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
2023 r600_write_value(cs, reloc);
2024 } else if (rctx->screen->info.drm_minor >= 18) {
2025 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
2026 * Older kernels are out of luck. */
2027 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2028 r600_write_value(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2029 r600_write_value(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2030 }
2031
2032 /* Framebuffer dimensions. */
2033 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
2034
2035 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
2036 r600_write_value(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
2037 r600_write_value(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
2038
2039 if (rctx->chip_class == EVERGREEN) {
2040 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
2041 } else {
2042 cayman_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
2043 }
2044 }
2045
2046 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
2047 {
2048 struct radeon_winsys_cs *cs = rctx->cs;
2049 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
2050 float offset_units = state->offset_units;
2051 float offset_scale = state->offset_scale;
2052
2053 switch (state->zs_format) {
2054 case PIPE_FORMAT_Z24X8_UNORM:
2055 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2056 offset_units *= 2.0f;
2057 break;
2058 case PIPE_FORMAT_Z16_UNORM:
2059 offset_units *= 4.0f;
2060 break;
2061 default:;
2062 }
2063
2064 r600_write_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
2065 r600_write_value(cs, fui(offset_scale));
2066 r600_write_value(cs, fui(offset_units));
2067 r600_write_value(cs, fui(offset_scale));
2068 r600_write_value(cs, fui(offset_units));
2069 }
2070
2071 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2072 {
2073 struct radeon_winsys_cs *cs = rctx->cs;
2074 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
2075 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
2076 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
2077
2078 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
2079 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
2080 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
2081 * will assure that the alpha-test will work even if there is
2082 * no colorbuffer bound. */
2083 r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
2084 }
2085
2086 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2087 {
2088 struct radeon_winsys_cs *cs = rctx->cs;
2089 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2090 unsigned db_render_control = 0;
2091 unsigned db_count_control = 0;
2092 unsigned db_render_override =
2093 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
2094 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2095 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2096
2097 if (a->occlusion_query_enabled) {
2098 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
2099 if (rctx->chip_class == CAYMAN) {
2100 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
2101 }
2102 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
2103 }
2104
2105 if (a->flush_depthstencil_through_cb) {
2106 assert(a->copy_depth || a->copy_stencil);
2107
2108 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
2109 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
2110 S_028000_COPY_CENTROID(1) |
2111 S_028000_COPY_SAMPLE(a->copy_sample);
2112 }
2113
2114 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
2115 r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
2116 r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
2117 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2118 }
2119
2120 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
2121 struct r600_vertexbuf_state *state,
2122 unsigned resource_offset,
2123 unsigned pkt_flags)
2124 {
2125 struct radeon_winsys_cs *cs = rctx->cs;
2126 uint32_t dirty_mask = state->dirty_mask;
2127
2128 while (dirty_mask) {
2129 struct pipe_vertex_buffer *vb;
2130 struct r600_resource *rbuffer;
2131 uint64_t va;
2132 unsigned buffer_index = u_bit_scan(&dirty_mask);
2133
2134 vb = &state->vb[buffer_index];
2135 rbuffer = (struct r600_resource*)vb->buffer;
2136 assert(rbuffer);
2137
2138 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
2139 va += vb->buffer_offset;
2140
2141 /* fetch resources start at index 992 */
2142 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2143 r600_write_value(cs, (resource_offset + buffer_index) * 8);
2144 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
2145 r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2146 r600_write_value(cs, /* RESOURCEi_WORD2 */
2147 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2148 S_030008_STRIDE(vb->stride) |
2149 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2150 r600_write_value(cs, /* RESOURCEi_WORD3 */
2151 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2152 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2153 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2154 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2155 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2156 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2157 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
2158 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2159
2160 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2161 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2162 }
2163 state->dirty_mask = 0;
2164 }
2165
2166 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2167 {
2168 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
2169 }
2170
2171 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2172 {
2173 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
2174 RADEON_CP_PACKET3_COMPUTE_MODE);
2175 }
2176
2177 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2178 struct r600_constbuf_state *state,
2179 unsigned buffer_id_base,
2180 unsigned reg_alu_constbuf_size,
2181 unsigned reg_alu_const_cache)
2182 {
2183 struct radeon_winsys_cs *cs = rctx->cs;
2184 uint32_t dirty_mask = state->dirty_mask;
2185
2186 while (dirty_mask) {
2187 struct pipe_constant_buffer *cb;
2188 struct r600_resource *rbuffer;
2189 uint64_t va;
2190 unsigned buffer_index = ffs(dirty_mask) - 1;
2191
2192 cb = &state->cb[buffer_index];
2193 rbuffer = (struct r600_resource*)cb->buffer;
2194 assert(rbuffer);
2195
2196 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
2197 va += cb->buffer_offset;
2198
2199 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2200 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
2201 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
2202
2203 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2204 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2205
2206 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2207 r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
2208 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
2209 r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2210 r600_write_value(cs, /* RESOURCEi_WORD2 */
2211 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2212 S_030008_STRIDE(16) |
2213 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2214 r600_write_value(cs, /* RESOURCEi_WORD3 */
2215 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2216 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2217 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2218 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2219 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2220 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2221 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
2222 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2223
2224 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2225 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2226
2227 dirty_mask &= ~(1 << buffer_index);
2228 }
2229 state->dirty_mask = 0;
2230 }
2231
2232 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2233 {
2234 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 176,
2235 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2236 R_028980_ALU_CONST_CACHE_VS_0);
2237 }
2238
2239 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2240 {
2241 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
2242 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2243 R_0289C0_ALU_CONST_CACHE_GS_0);
2244 }
2245
2246 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2247 {
2248 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
2249 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2250 R_028940_ALU_CONST_CACHE_PS_0);
2251 }
2252
2253 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2254 struct r600_samplerview_state *state,
2255 unsigned resource_id_base)
2256 {
2257 struct radeon_winsys_cs *cs = rctx->cs;
2258 uint32_t dirty_mask = state->dirty_mask;
2259
2260 while (dirty_mask) {
2261 struct r600_pipe_sampler_view *rview;
2262 unsigned resource_index = u_bit_scan(&dirty_mask);
2263 unsigned reloc;
2264
2265 rview = state->views[resource_index];
2266 assert(rview);
2267
2268 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2269 r600_write_value(cs, (resource_id_base + resource_index) * 8);
2270 r600_write_array(cs, 8, rview->tex_resource_words);
2271
2272 /* XXX The kernel needs two relocations. This is stupid. */
2273 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
2274 RADEON_USAGE_READ);
2275 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2276 r600_write_value(cs, reloc);
2277 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2278 r600_write_value(cs, reloc);
2279 }
2280 state->dirty_mask = 0;
2281 }
2282
2283 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2284 {
2285 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 176 + R600_MAX_CONST_BUFFERS);
2286 }
2287
2288 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2289 {
2290 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2291 }
2292
2293 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2294 {
2295 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2296 }
2297
2298 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2299 struct r600_textures_info *texinfo,
2300 unsigned resource_id_base,
2301 unsigned border_index_reg)
2302 {
2303 struct radeon_winsys_cs *cs = rctx->cs;
2304 uint32_t dirty_mask = texinfo->states.dirty_mask;
2305
2306 while (dirty_mask) {
2307 struct r600_pipe_sampler_state *rstate;
2308 unsigned i = u_bit_scan(&dirty_mask);
2309
2310 rstate = texinfo->states.states[i];
2311 assert(rstate);
2312
2313 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2314 r600_write_value(cs, (resource_id_base + i) * 3);
2315 r600_write_array(cs, 3, rstate->tex_sampler_words);
2316
2317 if (rstate->border_color_use) {
2318 r600_write_config_reg_seq(cs, border_index_reg, 5);
2319 r600_write_value(cs, i);
2320 r600_write_array(cs, 4, rstate->border_color);
2321 }
2322 }
2323 texinfo->states.dirty_mask = 0;
2324 }
2325
2326 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2327 {
2328 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
2329 }
2330
2331 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2332 {
2333 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX);
2334 }
2335
2336 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2337 {
2338 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
2339 }
2340
2341 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2342 {
2343 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2344 uint8_t mask = s->sample_mask;
2345
2346 r600_write_context_reg(rctx->cs, R_028C3C_PA_SC_AA_MASK,
2347 mask | (mask << 8) | (mask << 16) | (mask << 24));
2348 }
2349
2350 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2351 {
2352 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2353 struct radeon_winsys_cs *cs = rctx->cs;
2354 uint16_t mask = s->sample_mask;
2355
2356 r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2357 r600_write_value(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2358 r600_write_value(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2359 }
2360
2361 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2362 {
2363 struct radeon_winsys_cs *cs = rctx->cs;
2364 struct r600_cso_state *state = (struct r600_cso_state*)a;
2365 struct r600_resource *shader = (struct r600_resource*)state->cso;
2366
2367 r600_write_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2368 r600_resource_va(rctx->context.screen, &shader->b.b) >> 8);
2369 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2370 r600_write_value(cs, r600_context_bo_reloc(rctx, shader, RADEON_USAGE_READ));
2371 }
2372
2373 void evergreen_init_state_functions(struct r600_context *rctx)
2374 {
2375 unsigned id = 4;
2376
2377 /* !!!
2378 * To avoid GPU lockup registers must be emited in a specific order
2379 * (no kidding ...). The order below is important and have been
2380 * partialy infered from analyzing fglrx command stream.
2381 *
2382 * Don't reorder atom without carefully checking the effect (GPU lockup
2383 * or piglit regression).
2384 * !!!
2385 */
2386
2387 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
2388 /* shader const */
2389 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
2390 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
2391 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
2392 /* shader program */
2393 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
2394 /* sampler */
2395 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
2396 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
2397 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
2398 /* resources */
2399 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
2400 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
2401 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
2402 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
2403 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
2404
2405 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
2406 r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
2407
2408 if (rctx->chip_class == EVERGREEN) {
2409 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
2410 } else {
2411 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
2412 }
2413 rctx->sample_mask.sample_mask = ~0;
2414
2415 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2416 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2417 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
2418 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
2419 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
2420 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
2421 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 7);
2422 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
2423 r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 4);
2424 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2425 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2426 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
2427
2428 rctx->context.create_blend_state = evergreen_create_blend_state;
2429 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
2430 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
2431 rctx->context.create_sampler_state = evergreen_create_sampler_state;
2432 rctx->context.create_sampler_view = evergreen_create_sampler_view;
2433 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
2434 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
2435 rctx->context.set_scissor_state = evergreen_set_scissor_state;
2436 evergreen_init_compute_state_functions(rctx);
2437 }
2438
2439 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2440 {
2441 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2442
2443 r600_init_command_buffer(cb, 256);
2444
2445 /* This must be first. */
2446 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2447 r600_store_value(cb, 0x80000000);
2448 r600_store_value(cb, 0x80000000);
2449
2450 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2451 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2452 /* always set the temp clauses */
2453 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2454
2455 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2456 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2457 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2458
2459 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2460
2461 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2462
2463 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2464 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2465 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2466 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2467 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2468 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2469 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2470 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2471 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2472 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2473 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2474 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2475 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2476 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2477
2478 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2479 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2480 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2481
2482 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2483 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2484 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2485
2486 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2487
2488 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2489
2490 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2491 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2492 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2493
2494 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
2495 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2496 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2497
2498 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2499 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2500 r600_store_value(cb, 0);
2501 r600_store_value(cb, 0);
2502 r600_store_value(cb, 0);
2503 r600_store_value(cb, 0);
2504 r600_store_value(cb, 0);
2505 r600_store_value(cb, 0);
2506 r600_store_value(cb, 0);
2507 r600_store_value(cb, 0);
2508 r600_store_value(cb, 0);
2509 r600_store_value(cb, 0);
2510 r600_store_value(cb, 0);
2511 r600_store_value(cb, 0);
2512 r600_store_value(cb, 0);
2513 r600_store_value(cb, 0);
2514 r600_store_value(cb, 0);
2515 r600_store_value(cb, 0);
2516 r600_store_value(cb, 0);
2517 r600_store_value(cb, 0);
2518 r600_store_value(cb, 0);
2519 r600_store_value(cb, 0);
2520 r600_store_value(cb, 0);
2521 r600_store_value(cb, 0);
2522 r600_store_value(cb, 0);
2523 r600_store_value(cb, 0);
2524 r600_store_value(cb, 0);
2525 r600_store_value(cb, 0);
2526 r600_store_value(cb, 0);
2527 r600_store_value(cb, 0);
2528 r600_store_value(cb, 0);
2529 r600_store_value(cb, 0);
2530 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2531 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2532 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2533
2534 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2535
2536 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2537 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2538 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2539
2540 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2541
2542 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2543 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2544 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2545 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2546
2547 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2548 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2549
2550 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2551 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2552 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2553
2554 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2555 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2556 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2557
2558 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2559 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2560 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2561 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2562 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2563
2564 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2565 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2566 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2567
2568 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2569 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2570 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2571
2572 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2573 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2574 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2575
2576 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2577 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2578 if (rctx->screen->has_streamout) {
2579 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2580 }
2581
2582 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2583 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2584 }
2585
2586 void evergreen_init_common_regs(struct r600_command_buffer *cb,
2587 enum chip_class ctx_chip_class,
2588 enum radeon_family ctx_family,
2589 int ctx_drm_minor)
2590 {
2591 int ps_prio;
2592 int vs_prio;
2593 int gs_prio;
2594 int es_prio;
2595
2596 int hs_prio;
2597 int cs_prio;
2598 int ls_prio;
2599
2600 int num_ps_gprs;
2601 int num_vs_gprs;
2602 int num_gs_gprs;
2603 int num_es_gprs;
2604 int num_hs_gprs;
2605 int num_ls_gprs;
2606 int num_temp_gprs;
2607
2608 unsigned tmp;
2609
2610 ps_prio = 0;
2611 vs_prio = 1;
2612 gs_prio = 2;
2613 es_prio = 3;
2614 hs_prio = 0;
2615 ls_prio = 0;
2616 cs_prio = 0;
2617
2618 switch (ctx_family) {
2619 case CHIP_CEDAR:
2620 default:
2621 num_ps_gprs = 93;
2622 num_vs_gprs = 46;
2623 num_temp_gprs = 4;
2624 num_gs_gprs = 31;
2625 num_es_gprs = 31;
2626 num_hs_gprs = 23;
2627 num_ls_gprs = 23;
2628 break;
2629 case CHIP_REDWOOD:
2630 num_ps_gprs = 93;
2631 num_vs_gprs = 46;
2632 num_temp_gprs = 4;
2633 num_gs_gprs = 31;
2634 num_es_gprs = 31;
2635 num_hs_gprs = 23;
2636 num_ls_gprs = 23;
2637 break;
2638 case CHIP_JUNIPER:
2639 num_ps_gprs = 93;
2640 num_vs_gprs = 46;
2641 num_temp_gprs = 4;
2642 num_gs_gprs = 31;
2643 num_es_gprs = 31;
2644 num_hs_gprs = 23;
2645 num_ls_gprs = 23;
2646 break;
2647 case CHIP_CYPRESS:
2648 case CHIP_HEMLOCK:
2649 num_ps_gprs = 93;
2650 num_vs_gprs = 46;
2651 num_temp_gprs = 4;
2652 num_gs_gprs = 31;
2653 num_es_gprs = 31;
2654 num_hs_gprs = 23;
2655 num_ls_gprs = 23;
2656 break;
2657 case CHIP_PALM:
2658 num_ps_gprs = 93;
2659 num_vs_gprs = 46;
2660 num_temp_gprs = 4;
2661 num_gs_gprs = 31;
2662 num_es_gprs = 31;
2663 num_hs_gprs = 23;
2664 num_ls_gprs = 23;
2665 break;
2666 case CHIP_SUMO:
2667 num_ps_gprs = 93;
2668 num_vs_gprs = 46;
2669 num_temp_gprs = 4;
2670 num_gs_gprs = 31;
2671 num_es_gprs = 31;
2672 num_hs_gprs = 23;
2673 num_ls_gprs = 23;
2674 break;
2675 case CHIP_SUMO2:
2676 num_ps_gprs = 93;
2677 num_vs_gprs = 46;
2678 num_temp_gprs = 4;
2679 num_gs_gprs = 31;
2680 num_es_gprs = 31;
2681 num_hs_gprs = 23;
2682 num_ls_gprs = 23;
2683 break;
2684 case CHIP_BARTS:
2685 num_ps_gprs = 93;
2686 num_vs_gprs = 46;
2687 num_temp_gprs = 4;
2688 num_gs_gprs = 31;
2689 num_es_gprs = 31;
2690 num_hs_gprs = 23;
2691 num_ls_gprs = 23;
2692 break;
2693 case CHIP_TURKS:
2694 num_ps_gprs = 93;
2695 num_vs_gprs = 46;
2696 num_temp_gprs = 4;
2697 num_gs_gprs = 31;
2698 num_es_gprs = 31;
2699 num_hs_gprs = 23;
2700 num_ls_gprs = 23;
2701 break;
2702 case CHIP_CAICOS:
2703 num_ps_gprs = 93;
2704 num_vs_gprs = 46;
2705 num_temp_gprs = 4;
2706 num_gs_gprs = 31;
2707 num_es_gprs = 31;
2708 num_hs_gprs = 23;
2709 num_ls_gprs = 23;
2710 break;
2711 }
2712
2713 tmp = 0;
2714 switch (ctx_family) {
2715 case CHIP_CEDAR:
2716 case CHIP_PALM:
2717 case CHIP_SUMO:
2718 case CHIP_SUMO2:
2719 case CHIP_CAICOS:
2720 break;
2721 default:
2722 tmp |= S_008C00_VC_ENABLE(1);
2723 break;
2724 }
2725 tmp |= S_008C00_EXPORT_SRC_C(1);
2726 tmp |= S_008C00_CS_PRIO(cs_prio);
2727 tmp |= S_008C00_LS_PRIO(ls_prio);
2728 tmp |= S_008C00_HS_PRIO(hs_prio);
2729 tmp |= S_008C00_PS_PRIO(ps_prio);
2730 tmp |= S_008C00_VS_PRIO(vs_prio);
2731 tmp |= S_008C00_GS_PRIO(gs_prio);
2732 tmp |= S_008C00_ES_PRIO(es_prio);
2733
2734 /* enable dynamic GPR resource management */
2735 if (ctx_drm_minor >= 7) {
2736 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2737 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2738 /* always set temp clauses */
2739 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2740 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2741 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2742 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2743 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2744 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2745 S_028838_PS_GPRS(0x1e) |
2746 S_028838_VS_GPRS(0x1e) |
2747 S_028838_GS_GPRS(0x1e) |
2748 S_028838_ES_GPRS(0x1e) |
2749 S_028838_HS_GPRS(0x1e) |
2750 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2751 } else {
2752 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2753 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2754
2755 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2756 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2757 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2758 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2759
2760 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2761 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2762 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2763
2764 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2765 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2766 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2767 }
2768
2769 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2770 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2771
2772 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2773
2774 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2775 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2776 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2777
2778 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2779
2780 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2781 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2782 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2783
2784 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2785 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2786 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2787 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2788
2789 /* The cs checker requires this register to be set. */
2790 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2791
2792 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2793 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2794
2795 /* to avoid GPU doing any preloading of constant from random address */
2796 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2797 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2798 r600_store_value(cb, 0);
2799 r600_store_value(cb, 0);
2800 r600_store_value(cb, 0);
2801 r600_store_value(cb, 0);
2802 r600_store_value(cb, 0);
2803 r600_store_value(cb, 0);
2804 r600_store_value(cb, 0);
2805 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2806 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2807 r600_store_value(cb, 0);
2808 r600_store_value(cb, 0);
2809 r600_store_value(cb, 0);
2810 r600_store_value(cb, 0);
2811 r600_store_value(cb, 0);
2812 r600_store_value(cb, 0);
2813 r600_store_value(cb, 0);
2814
2815 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2816
2817 return;
2818 }
2819
2820 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2821 {
2822 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2823 int num_ps_threads;
2824 int num_vs_threads;
2825 int num_gs_threads;
2826 int num_es_threads;
2827 int num_hs_threads;
2828 int num_ls_threads;
2829
2830 int num_ps_stack_entries;
2831 int num_vs_stack_entries;
2832 int num_gs_stack_entries;
2833 int num_es_stack_entries;
2834 int num_hs_stack_entries;
2835 int num_ls_stack_entries;
2836 enum radeon_family family;
2837 unsigned tmp;
2838
2839 if (rctx->chip_class == CAYMAN) {
2840 cayman_init_atom_start_cs(rctx);
2841 return;
2842 }
2843
2844 r600_init_command_buffer(cb, 256);
2845
2846 /* This must be first. */
2847 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2848 r600_store_value(cb, 0x80000000);
2849 r600_store_value(cb, 0x80000000);
2850
2851 evergreen_init_common_regs(cb, rctx->chip_class
2852 , rctx->family, rctx->screen->info.drm_minor);
2853
2854 family = rctx->family;
2855 switch (family) {
2856 case CHIP_CEDAR:
2857 default:
2858 num_ps_threads = 96;
2859 num_vs_threads = 16;
2860 num_gs_threads = 16;
2861 num_es_threads = 16;
2862 num_hs_threads = 16;
2863 num_ls_threads = 16;
2864 num_ps_stack_entries = 42;
2865 num_vs_stack_entries = 42;
2866 num_gs_stack_entries = 42;
2867 num_es_stack_entries = 42;
2868 num_hs_stack_entries = 42;
2869 num_ls_stack_entries = 42;
2870 break;
2871 case CHIP_REDWOOD:
2872 num_ps_threads = 128;
2873 num_vs_threads = 20;
2874 num_gs_threads = 20;
2875 num_es_threads = 20;
2876 num_hs_threads = 20;
2877 num_ls_threads = 20;
2878 num_ps_stack_entries = 42;
2879 num_vs_stack_entries = 42;
2880 num_gs_stack_entries = 42;
2881 num_es_stack_entries = 42;
2882 num_hs_stack_entries = 42;
2883 num_ls_stack_entries = 42;
2884 break;
2885 case CHIP_JUNIPER:
2886 num_ps_threads = 128;
2887 num_vs_threads = 20;
2888 num_gs_threads = 20;
2889 num_es_threads = 20;
2890 num_hs_threads = 20;
2891 num_ls_threads = 20;
2892 num_ps_stack_entries = 85;
2893 num_vs_stack_entries = 85;
2894 num_gs_stack_entries = 85;
2895 num_es_stack_entries = 85;
2896 num_hs_stack_entries = 85;
2897 num_ls_stack_entries = 85;
2898 break;
2899 case CHIP_CYPRESS:
2900 case CHIP_HEMLOCK:
2901 num_ps_threads = 128;
2902 num_vs_threads = 20;
2903 num_gs_threads = 20;
2904 num_es_threads = 20;
2905 num_hs_threads = 20;
2906 num_ls_threads = 20;
2907 num_ps_stack_entries = 85;
2908 num_vs_stack_entries = 85;
2909 num_gs_stack_entries = 85;
2910 num_es_stack_entries = 85;
2911 num_hs_stack_entries = 85;
2912 num_ls_stack_entries = 85;
2913 break;
2914 case CHIP_PALM:
2915 num_ps_threads = 96;
2916 num_vs_threads = 16;
2917 num_gs_threads = 16;
2918 num_es_threads = 16;
2919 num_hs_threads = 16;
2920 num_ls_threads = 16;
2921 num_ps_stack_entries = 42;
2922 num_vs_stack_entries = 42;
2923 num_gs_stack_entries = 42;
2924 num_es_stack_entries = 42;
2925 num_hs_stack_entries = 42;
2926 num_ls_stack_entries = 42;
2927 break;
2928 case CHIP_SUMO:
2929 num_ps_threads = 96;
2930 num_vs_threads = 25;
2931 num_gs_threads = 25;
2932 num_es_threads = 25;
2933 num_hs_threads = 25;
2934 num_ls_threads = 25;
2935 num_ps_stack_entries = 42;
2936 num_vs_stack_entries = 42;
2937 num_gs_stack_entries = 42;
2938 num_es_stack_entries = 42;
2939 num_hs_stack_entries = 42;
2940 num_ls_stack_entries = 42;
2941 break;
2942 case CHIP_SUMO2:
2943 num_ps_threads = 96;
2944 num_vs_threads = 25;
2945 num_gs_threads = 25;
2946 num_es_threads = 25;
2947 num_hs_threads = 25;
2948 num_ls_threads = 25;
2949 num_ps_stack_entries = 85;
2950 num_vs_stack_entries = 85;
2951 num_gs_stack_entries = 85;
2952 num_es_stack_entries = 85;
2953 num_hs_stack_entries = 85;
2954 num_ls_stack_entries = 85;
2955 break;
2956 case CHIP_BARTS:
2957 num_ps_threads = 128;
2958 num_vs_threads = 20;
2959 num_gs_threads = 20;
2960 num_es_threads = 20;
2961 num_hs_threads = 20;
2962 num_ls_threads = 20;
2963 num_ps_stack_entries = 85;
2964 num_vs_stack_entries = 85;
2965 num_gs_stack_entries = 85;
2966 num_es_stack_entries = 85;
2967 num_hs_stack_entries = 85;
2968 num_ls_stack_entries = 85;
2969 break;
2970 case CHIP_TURKS:
2971 num_ps_threads = 128;
2972 num_vs_threads = 20;
2973 num_gs_threads = 20;
2974 num_es_threads = 20;
2975 num_hs_threads = 20;
2976 num_ls_threads = 20;
2977 num_ps_stack_entries = 42;
2978 num_vs_stack_entries = 42;
2979 num_gs_stack_entries = 42;
2980 num_es_stack_entries = 42;
2981 num_hs_stack_entries = 42;
2982 num_ls_stack_entries = 42;
2983 break;
2984 case CHIP_CAICOS:
2985 num_ps_threads = 128;
2986 num_vs_threads = 10;
2987 num_gs_threads = 10;
2988 num_es_threads = 10;
2989 num_hs_threads = 10;
2990 num_ls_threads = 10;
2991 num_ps_stack_entries = 42;
2992 num_vs_stack_entries = 42;
2993 num_gs_stack_entries = 42;
2994 num_es_stack_entries = 42;
2995 num_hs_stack_entries = 42;
2996 num_ls_stack_entries = 42;
2997 break;
2998 }
2999
3000 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
3001 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
3002 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
3003 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
3004
3005 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
3006 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3007
3008 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
3009 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
3010 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3011
3012 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
3013 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
3014 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3015
3016 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
3017 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
3018 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3019
3020 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
3021 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
3022 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3023
3024 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
3025 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
3026
3027 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
3028 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3029 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3030 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3031 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3032 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3033 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3034
3035 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3036 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3037 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3038 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3039 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3040
3041 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
3042 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3043 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
3044 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3045 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3046 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3047 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3048 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3049 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
3050 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3051 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3052 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3053 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3054 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
3055
3056 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
3057 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
3058 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
3059
3060 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
3061
3062 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
3063 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
3064 r600_store_value(cb, 0);
3065 r600_store_value(cb, 0);
3066 r600_store_value(cb, 0);
3067 r600_store_value(cb, 0);
3068 r600_store_value(cb, 0);
3069 r600_store_value(cb, 0);
3070 r600_store_value(cb, 0);
3071 r600_store_value(cb, 0);
3072 r600_store_value(cb, 0);
3073 r600_store_value(cb, 0);
3074 r600_store_value(cb, 0);
3075 r600_store_value(cb, 0);
3076 r600_store_value(cb, 0);
3077 r600_store_value(cb, 0);
3078 r600_store_value(cb, 0);
3079 r600_store_value(cb, 0);
3080 r600_store_value(cb, 0);
3081 r600_store_value(cb, 0);
3082 r600_store_value(cb, 0);
3083 r600_store_value(cb, 0);
3084 r600_store_value(cb, 0);
3085 r600_store_value(cb, 0);
3086 r600_store_value(cb, 0);
3087 r600_store_value(cb, 0);
3088 r600_store_value(cb, 0);
3089 r600_store_value(cb, 0);
3090 r600_store_value(cb, 0);
3091 r600_store_value(cb, 0);
3092 r600_store_value(cb, 0);
3093 r600_store_value(cb, 0);
3094 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
3095 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3096 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
3097
3098 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
3099
3100 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
3101 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
3102 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
3103
3104 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
3105 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3106
3107 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
3108 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3109 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
3110
3111 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
3112 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3113 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3114 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3115
3116 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
3117 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
3118 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
3119 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
3120 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
3121
3122 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
3123 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3124 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3125
3126 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
3127 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3128 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3129
3130 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
3131
3132 if (rctx->screen->has_streamout) {
3133 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3134 }
3135
3136 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3137 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3138 }
3139
3140 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3141 {
3142 struct r600_context *rctx = (struct r600_context *)ctx;
3143 struct r600_pipe_state *rstate = &shader->rstate;
3144 struct r600_shader *rshader = &shader->shader;
3145 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
3146 int pos_index = -1, face_index = -1;
3147 int ninterp = 0;
3148 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
3149 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
3150 unsigned z_export = 0, stencil_export = 0;
3151 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3152
3153 rstate->nregs = 0;
3154
3155 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3156 for (i = 0; i < rshader->ninput; i++) {
3157 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3158 POSITION goes via GPRs from the SC so isn't counted */
3159 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3160 pos_index = i;
3161 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
3162 face_index = i;
3163 else {
3164 ninterp++;
3165 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
3166 have_linear = TRUE;
3167 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
3168 have_perspective = TRUE;
3169 if (rshader->input[i].centroid)
3170 have_centroid = TRUE;
3171 }
3172
3173 sid = rshader->input[i].spi_sid;
3174
3175 if (sid) {
3176
3177 tmp = S_028644_SEMANTIC(sid);
3178
3179 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3180 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3181 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3182 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3183 tmp |= S_028644_FLAT_SHADE(1);
3184 }
3185
3186 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3187 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3188 tmp |= S_028644_PT_SPRITE_TEX(1);
3189 }
3190
3191 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
3192 tmp);
3193
3194 idx++;
3195 }
3196 }
3197
3198 for (i = 0; i < rshader->noutput; i++) {
3199 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3200 z_export = 1;
3201 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3202 stencil_export = 1;
3203 }
3204 if (rshader->uses_kill)
3205 db_shader_control |= S_02880C_KILL_ENABLE(1);
3206
3207 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3208 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3209
3210 exports_ps = 0;
3211 for (i = 0; i < rshader->noutput; i++) {
3212 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3213 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3214 exports_ps |= 1;
3215 }
3216
3217 num_cout = rshader->nr_ps_color_exports;
3218
3219 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3220 if (!exports_ps) {
3221 /* always at least export 1 component per pixel */
3222 exports_ps = 2;
3223 }
3224 shader->nr_ps_color_outputs = num_cout;
3225 if (ninterp == 0) {
3226 ninterp = 1;
3227 have_perspective = TRUE;
3228 }
3229
3230 if (!have_perspective && !have_linear)
3231 have_perspective = TRUE;
3232
3233 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3234 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3235 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3236 spi_input_z = 0;
3237 if (pos_index != -1) {
3238 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3239 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
3240 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3241 spi_input_z |= 1;
3242 }
3243
3244 spi_ps_in_control_1 = 0;
3245 if (face_index != -1) {
3246 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3247 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3248 }
3249
3250 spi_baryc_cntl = 0;
3251 if (have_perspective)
3252 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
3253 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
3254 if (have_linear)
3255 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
3256 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
3257
3258 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
3259 spi_ps_in_control_0);
3260 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
3261 spi_ps_in_control_1);
3262 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
3263 0);
3264 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
3265 r600_pipe_state_add_reg(rstate,
3266 R_0286E0_SPI_BARYC_CNTL,
3267 spi_baryc_cntl);
3268
3269 r600_pipe_state_add_reg_bo(rstate,
3270 R_028840_SQ_PGM_START_PS,
3271 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3272 shader->bo, RADEON_USAGE_READ);
3273 r600_pipe_state_add_reg(rstate,
3274 R_028844_SQ_PGM_RESOURCES_PS,
3275 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3276 S_028844_PRIME_CACHE_ON_DRAW(1) |
3277 S_028844_STACK_SIZE(rshader->bc.nstack));
3278 r600_pipe_state_add_reg(rstate,
3279 R_02884C_SQ_PGM_EXPORTS_PS,
3280 exports_ps);
3281
3282 shader->db_shader_control = db_shader_control;
3283 shader->ps_depth_export = z_export | stencil_export;
3284
3285 shader->sprite_coord_enable = sprite_coord_enable;
3286 if (rctx->rasterizer)
3287 shader->flatshade = rctx->rasterizer->flatshade;
3288 }
3289
3290 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3291 {
3292 struct r600_context *rctx = (struct r600_context *)ctx;
3293 struct r600_pipe_state *rstate = &shader->rstate;
3294 struct r600_shader *rshader = &shader->shader;
3295 unsigned spi_vs_out_id[10] = {};
3296 unsigned i, tmp, nparams = 0;
3297
3298 /* clear previous register */
3299 rstate->nregs = 0;
3300
3301 for (i = 0; i < rshader->noutput; i++) {
3302 if (rshader->output[i].spi_sid) {
3303 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3304 spi_vs_out_id[nparams / 4] |= tmp;
3305 nparams++;
3306 }
3307 }
3308
3309 for (i = 0; i < 10; i++) {
3310 r600_pipe_state_add_reg(rstate,
3311 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
3312 spi_vs_out_id[i]);
3313 }
3314
3315 /* Certain attributes (position, psize, etc.) don't count as params.
3316 * VS is required to export at least one param and r600_shader_from_tgsi()
3317 * takes care of adding a dummy export.
3318 */
3319 if (nparams < 1)
3320 nparams = 1;
3321
3322 r600_pipe_state_add_reg(rstate,
3323 R_0286C4_SPI_VS_OUT_CONFIG,
3324 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3325 r600_pipe_state_add_reg(rstate,
3326 R_028860_SQ_PGM_RESOURCES_VS,
3327 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3328 S_028860_STACK_SIZE(rshader->bc.nstack));
3329 r600_pipe_state_add_reg_bo(rstate,
3330 R_02885C_SQ_PGM_START_VS,
3331 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3332 shader->bo, RADEON_USAGE_READ);
3333
3334 shader->pa_cl_vs_out_cntl =
3335 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3336 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3337 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3338 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
3339 }
3340
3341 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3342 {
3343 struct pipe_blend_state blend;
3344
3345 memset(&blend, 0, sizeof(blend));
3346 blend.independent_blend_enable = true;
3347 blend.rt[0].colormask = 0xf;
3348 return evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_RESOLVE);
3349 }
3350
3351 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3352 {
3353 struct pipe_blend_state blend;
3354
3355 memset(&blend, 0, sizeof(blend));
3356 blend.independent_blend_enable = true;
3357 blend.rt[0].colormask = 0xf;
3358 return evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_DECOMPRESS);
3359 }
3360
3361 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3362 {
3363 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3364
3365 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
3366 }
3367
3368 void evergreen_update_dual_export_state(struct r600_context * rctx)
3369 {
3370 bool dual_export = rctx->framebuffer.export_16bpc &&
3371 !rctx->ps_shader->current->ps_depth_export;
3372
3373 unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
3374 V_02880C_EXPORT_DB_FULL;
3375
3376 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
3377 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3378 S_02880C_DB_SOURCE_FORMAT(db_source_format) |
3379 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3380
3381 if (db_shader_control != rctx->db_shader_control) {
3382 struct r600_pipe_state rstate;
3383
3384 rctx->db_shader_control = db_shader_control;
3385
3386 rstate.nregs = 0;
3387 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
3388 r600_context_pipe_state_set(rctx, &rstate);
3389 }
3390 }