2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * - fix mask for depth control & cull for query
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "eg_state_inlines.h"
51 static void evergreen_set_blend_color(struct pipe_context
*ctx
,
52 const struct pipe_blend_color
*state
)
54 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
55 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
60 rstate
->id
= R600_PIPE_STATE_BLEND_COLOR
;
61 r600_pipe_state_add_reg(rstate
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]), 0xFFFFFFFF, NULL
);
62 r600_pipe_state_add_reg(rstate
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]), 0xFFFFFFFF, NULL
);
63 r600_pipe_state_add_reg(rstate
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]), 0xFFFFFFFF, NULL
);
64 r600_pipe_state_add_reg(rstate
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]), 0xFFFFFFFF, NULL
);
66 free(rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
]);
67 rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
] = rstate
;
68 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
71 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
72 const struct pipe_blend_state
*state
)
74 struct r600_pipe_blend
*blend
= CALLOC_STRUCT(r600_pipe_blend
);
75 struct r600_pipe_state
*rstate
;
76 u32 color_control
, target_mask
;
77 /* FIXME there is more then 8 framebuffer */
78 unsigned blend_cntl
[8];
83 rstate
= &blend
->rstate
;
85 rstate
->id
= R600_PIPE_STATE_BLEND
;
88 color_control
= S_028808_MODE(1);
89 if (state
->logicop_enable
) {
90 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
92 color_control
|= (0xcc << 16);
94 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
95 if (state
->independent_blend_enable
) {
96 for (int i
= 0; i
< 8; i
++) {
97 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
100 for (int i
= 0; i
< 8; i
++) {
101 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
104 blend
->cb_target_mask
= target_mask
;
105 r600_pipe_state_add_reg(rstate
, R_028808_CB_COLOR_CONTROL
,
106 color_control
, 0xFFFFFFFF, NULL
);
107 r600_pipe_state_add_reg(rstate
, R_028C3C_PA_SC_AA_MASK
, 0xFFFFFFFF, 0xFFFFFFFF, NULL
);
109 for (int i
= 0; i
< 8; i
++) {
110 unsigned eqRGB
= state
->rt
[i
].rgb_func
;
111 unsigned srcRGB
= state
->rt
[i
].rgb_src_factor
;
112 unsigned dstRGB
= state
->rt
[i
].rgb_dst_factor
;
113 unsigned eqA
= state
->rt
[i
].alpha_func
;
114 unsigned srcA
= state
->rt
[i
].alpha_src_factor
;
115 unsigned dstA
= state
->rt
[i
].alpha_dst_factor
;
118 if (!state
->rt
[i
].blend_enable
)
121 blend_cntl
[i
] |= S_028780_BLEND_CONTROL_ENABLE(1);
122 blend_cntl
[i
] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
123 blend_cntl
[i
] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
124 blend_cntl
[i
] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
126 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
127 blend_cntl
[i
] |= S_028780_SEPARATE_ALPHA_BLEND(1);
128 blend_cntl
[i
] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
129 blend_cntl
[i
] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
130 blend_cntl
[i
] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
133 for (int i
= 0; i
< 8; i
++) {
134 r600_pipe_state_add_reg(rstate
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
[i
], 0xFFFFFFFF, NULL
);
140 static void evergreen_bind_blend_state(struct pipe_context
*ctx
, void *state
)
142 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
143 struct r600_pipe_blend
*blend
= (struct r600_pipe_blend
*)state
;
144 struct r600_pipe_state
*rstate
;
148 rstate
= &blend
->rstate
;
149 rctx
->states
[rstate
->id
] = rstate
;
150 rctx
->cb_target_mask
= blend
->cb_target_mask
;
151 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
154 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
155 const struct pipe_depth_stencil_alpha_state
*state
)
157 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
158 unsigned db_depth_control
, alpha_test_control
, alpha_ref
, db_shader_control
;
159 unsigned stencil_ref_mask
, stencil_ref_mask_bf
, db_render_override
, db_render_control
;
161 if (rstate
== NULL
) {
165 rstate
->id
= R600_PIPE_STATE_DSA
;
166 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
167 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
168 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
169 * be set if shader use texkill instruction
171 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
172 stencil_ref_mask
= 0;
173 stencil_ref_mask_bf
= 0;
174 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
175 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
176 S_028800_ZFUNC(state
->depth
.func
);
179 if (state
->stencil
[0].enabled
) {
180 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
181 db_depth_control
|= S_028800_STENCILFUNC(r600_translate_ds_func(state
->stencil
[0].func
));
182 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
183 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
184 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
187 stencil_ref_mask
= S_028430_STENCILMASK(state
->stencil
[0].valuemask
) |
188 S_028430_STENCILWRITEMASK(state
->stencil
[0].writemask
);
189 if (state
->stencil
[1].enabled
) {
190 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
191 db_depth_control
|= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state
->stencil
[1].func
));
192 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
193 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
194 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
195 stencil_ref_mask_bf
= S_028434_STENCILMASK_BF(state
->stencil
[1].valuemask
) |
196 S_028434_STENCILWRITEMASK_BF(state
->stencil
[1].writemask
);
201 alpha_test_control
= 0;
203 if (state
->alpha
.enabled
) {
204 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
205 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
206 alpha_ref
= fui(state
->alpha
.ref_value
);
210 db_render_control
= 0;
211 db_render_override
= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
) |
212 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
213 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
214 /* TODO db_render_override depends on query */
215 r600_pipe_state_add_reg(rstate
, R_028028_DB_STENCIL_CLEAR
, 0x00000000, 0xFFFFFFFF, NULL
);
216 r600_pipe_state_add_reg(rstate
, R_02802C_DB_DEPTH_CLEAR
, 0x3F800000, 0xFFFFFFFF, NULL
);
217 r600_pipe_state_add_reg(rstate
, R_028410_SX_ALPHA_TEST_CONTROL
, alpha_test_control
, 0xFFFFFFFF, NULL
);
218 r600_pipe_state_add_reg(rstate
,
219 R_028430_DB_STENCILREFMASK
, stencil_ref_mask
,
220 0xFFFFFFFF & C_028430_STENCILREF
, NULL
);
221 r600_pipe_state_add_reg(rstate
,
222 R_028434_DB_STENCILREFMASK_BF
, stencil_ref_mask_bf
,
223 0xFFFFFFFF & C_028434_STENCILREF_BF
, NULL
);
224 r600_pipe_state_add_reg(rstate
, R_028438_SX_ALPHA_REF
, alpha_ref
, 0xFFFFFFFF, NULL
);
225 r600_pipe_state_add_reg(rstate
, R_0286DC_SPI_FOG_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
226 r600_pipe_state_add_reg(rstate
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
, 0xFFFFFFFF, NULL
);
227 r600_pipe_state_add_reg(rstate
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
, 0xFFFFFFBE, NULL
);
228 r600_pipe_state_add_reg(rstate
, R_028000_DB_RENDER_CONTROL
, db_render_control
, 0xFFFFFFFF, NULL
);
229 r600_pipe_state_add_reg(rstate
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
, 0xFFFFFFFF, NULL
);
230 r600_pipe_state_add_reg(rstate
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0, 0xFFFFFFFF, NULL
);
231 r600_pipe_state_add_reg(rstate
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0, 0xFFFFFFFF, NULL
);
232 r600_pipe_state_add_reg(rstate
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0, 0xFFFFFFFF, NULL
);
233 r600_pipe_state_add_reg(rstate
, R_028B70_DB_ALPHA_TO_MASK
, 0x0000AA00, 0xFFFFFFFF, NULL
);
238 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
239 const struct pipe_rasterizer_state
*state
)
241 struct r600_pipe_rasterizer
*rs
= CALLOC_STRUCT(r600_pipe_rasterizer
);
242 struct r600_pipe_state
*rstate
;
244 unsigned prov_vtx
= 1, polygon_dual_mode
;
251 rstate
= &rs
->rstate
;
252 rs
->flatshade
= state
->flatshade
;
253 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
255 clip_rule
= state
->scissor
? 0xAAAA : 0xFFFF;
258 rs
->offset_units
= state
->offset_units
;
259 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
261 rstate
->id
= R600_PIPE_STATE_RASTERIZER
;
262 if (state
->flatshade_first
)
265 if (state
->sprite_coord_enable
) {
266 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
267 S_0286D4_PNT_SPRITE_OVRD_X(2) |
268 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
269 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
270 S_0286D4_PNT_SPRITE_OVRD_W(1);
271 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
272 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
275 r600_pipe_state_add_reg(rstate
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
, 0xFFFFFFFF, NULL
);
277 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
278 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
279 r600_pipe_state_add_reg(rstate
, R_028814_PA_SU_SC_MODE_CNTL
,
280 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
281 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
282 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
283 S_028814_FACE(!state
->front_ccw
) |
284 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
285 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
286 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
287 S_028814_POLY_MODE(polygon_dual_mode
) |
288 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
289 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)), 0xFFFFFFFF, NULL
);
290 r600_pipe_state_add_reg(rstate
, R_02881C_PA_CL_VS_OUT_CNTL
,
291 S_02881C_USE_VTX_POINT_SIZE(state
->point_size_per_vertex
) |
292 S_02881C_VS_OUT_MISC_VEC_ENA(state
->point_size_per_vertex
), 0xFFFFFFFF, NULL
);
293 r600_pipe_state_add_reg(rstate
, R_028820_PA_CL_NANINF_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
294 /* point size 12.4 fixed point */
295 tmp
= (unsigned)(state
->point_size
* 8.0);
296 r600_pipe_state_add_reg(rstate
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
), 0xFFFFFFFF, NULL
);
297 r600_pipe_state_add_reg(rstate
, R_028A04_PA_SU_POINT_MINMAX
, 0x80000000, 0xFFFFFFFF, NULL
);
298 r600_pipe_state_add_reg(rstate
, R_028A08_PA_SU_LINE_CNTL
, 0x00000008, 0xFFFFFFFF, NULL
);
299 r600_pipe_state_add_reg(rstate
, R_028C00_PA_SC_LINE_CNTL
, 0x00000400, 0xFFFFFFFF, NULL
);
300 r600_pipe_state_add_reg(rstate
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
301 r600_pipe_state_add_reg(rstate
, R_028C10_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
302 r600_pipe_state_add_reg(rstate
, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
303 r600_pipe_state_add_reg(rstate
, R_028C18_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
304 r600_pipe_state_add_reg(rstate
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 0x0, 0xFFFFFFFF, NULL
);
305 r600_pipe_state_add_reg(rstate
, R_028C08_PA_SU_VTX_CNTL
, 0x00000005, 0xFFFFFFFF, NULL
);
306 r600_pipe_state_add_reg(rstate
, R_02820C_PA_SC_CLIPRECT_RULE
, clip_rule
, 0xFFFFFFFF, NULL
);
310 static void evergreen_bind_rs_state(struct pipe_context
*ctx
, void *state
)
312 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
313 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
318 rctx
->flatshade
= rs
->flatshade
;
319 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
320 rctx
->rasterizer
= rs
;
322 rctx
->states
[rs
->rstate
.id
] = &rs
->rstate
;
323 r600_context_pipe_state_set(&rctx
->ctx
, &rs
->rstate
);
326 static void evergreen_delete_rs_state(struct pipe_context
*ctx
, void *state
)
328 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
329 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
331 if (rctx
->rasterizer
== rs
) {
332 rctx
->rasterizer
= NULL
;
334 if (rctx
->states
[rs
->rstate
.id
] == &rs
->rstate
) {
335 rctx
->states
[rs
->rstate
.id
] = NULL
;
340 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
341 const struct pipe_sampler_state
*state
)
343 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
346 if (rstate
== NULL
) {
350 rstate
->id
= R600_PIPE_STATE_SAMPLER
;
351 util_pack_color(state
->border_color
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
352 r600_pipe_state_add_reg(rstate
, R_03C000_SQ_TEX_SAMPLER_WORD0_0
,
353 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
354 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
355 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
356 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
)) |
357 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
)) |
358 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
359 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
360 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0), 0xFFFFFFFF, NULL
);
361 /* FIXME LOD it depends on texture base level ... */
362 r600_pipe_state_add_reg(rstate
, R_03C004_SQ_TEX_SAMPLER_WORD1_0
,
363 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
364 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)),
366 r600_pipe_state_add_reg(rstate
, R_03C008_SQ_TEX_SAMPLER_WORD2_0
,
367 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6)) |
372 r600_pipe_state_add_reg(rstate
, R_00A404_TD_PS_SAMPLER0_BORDER_RED
, fui(state
->border_color
[0]), 0xFFFFFFFF, NULL
);
373 r600_pipe_state_add_reg(rstate
, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN
, fui(state
->border_color
[1]), 0xFFFFFFFF, NULL
);
374 r600_pipe_state_add_reg(rstate
, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE
, fui(state
->border_color
[2]), 0xFFFFFFFF, NULL
);
375 r600_pipe_state_add_reg(rstate
, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA
, fui(state
->border_color
[3]), 0xFFFFFFFF, NULL
);
380 static void evergreen_sampler_view_destroy(struct pipe_context
*ctx
,
381 struct pipe_sampler_view
*state
)
383 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
385 pipe_resource_reference(&state
->texture
, NULL
);
389 static struct pipe_sampler_view
*evergreen_create_sampler_view(struct pipe_context
*ctx
,
390 struct pipe_resource
*texture
,
391 const struct pipe_sampler_view
*state
)
393 struct r600_pipe_sampler_view
*resource
= CALLOC_STRUCT(r600_pipe_sampler_view
);
394 struct r600_pipe_state
*rstate
;
395 const struct util_format_description
*desc
;
396 struct r600_resource_texture
*tmp
;
397 struct r600_resource
*rbuffer
;
399 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
400 unsigned char swizzle
[4];
401 struct r600_bo
*bo
[2];
403 if (resource
== NULL
)
405 rstate
= &resource
->state
;
407 /* initialize base object */
408 resource
->base
= *state
;
409 resource
->base
.texture
= NULL
;
410 pipe_reference(NULL
, &texture
->reference
);
411 resource
->base
.texture
= texture
;
412 resource
->base
.reference
.count
= 1;
413 resource
->base
.context
= ctx
;
415 swizzle
[0] = state
->swizzle_r
;
416 swizzle
[1] = state
->swizzle_g
;
417 swizzle
[2] = state
->swizzle_b
;
418 swizzle
[3] = state
->swizzle_a
;
419 format
= r600_translate_texformat(state
->format
,
421 &word4
, &yuv_format
);
425 desc
= util_format_description(state
->format
);
427 R600_ERR("unknow format %d\n", state
->format
);
429 tmp
= (struct r600_resource_texture
*)texture
;
430 rbuffer
= &tmp
->resource
;
433 /* FIXME depth texture decompression */
435 r600_texture_depth_flush(ctx
, texture
);
436 tmp
= (struct r600_resource_texture
*)texture
;
437 rbuffer
= &tmp
->flushed_depth_texture
->resource
;
441 pitch
= align(tmp
->pitch_in_pixels
[0], 8);
443 /* FIXME properly handle first level != 0 */
444 r600_pipe_state_add_reg(rstate
, R_030000_RESOURCE0_WORD0
,
445 S_030000_DIM(r600_tex_dim(texture
->target
)) |
446 S_030000_PITCH((pitch
/ 8) - 1) |
447 S_030000_TEX_WIDTH(texture
->width0
- 1), 0xFFFFFFFF, NULL
);
448 r600_pipe_state_add_reg(rstate
, R_030004_RESOURCE0_WORD1
,
449 S_030004_TEX_HEIGHT(texture
->height0
- 1) |
450 S_030004_TEX_DEPTH(texture
->depth0
- 1),
452 r600_pipe_state_add_reg(rstate
, R_030008_RESOURCE0_WORD2
,
453 (tmp
->offset
[0] + r600_bo_offset(bo
[0])) >> 8, 0xFFFFFFFF, bo
[0]);
454 r600_pipe_state_add_reg(rstate
, R_03000C_RESOURCE0_WORD3
,
455 (tmp
->offset
[1] + r600_bo_offset(bo
[1])) >> 8, 0xFFFFFFFF, bo
[1]);
456 r600_pipe_state_add_reg(rstate
, R_030010_RESOURCE0_WORD4
,
457 word4
| S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM
) |
458 S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO
) |
459 S_030010_BASE_LEVEL(state
->first_level
), 0xFFFFFFFF, NULL
);
460 r600_pipe_state_add_reg(rstate
, R_030014_RESOURCE0_WORD5
,
461 S_030014_LAST_LEVEL(state
->last_level
) |
462 S_030014_BASE_ARRAY(0) |
463 S_030014_LAST_ARRAY(0), 0xffffffff, NULL
);
464 r600_pipe_state_add_reg(rstate
, R_030018_RESOURCE0_WORD6
, 0x0, 0xFFFFFFFF, NULL
);
465 r600_pipe_state_add_reg(rstate
, R_03001C_RESOURCE0_WORD7
,
466 S_03001C_DATA_FORMAT(format
) |
467 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
), 0xFFFFFFFF, NULL
);
469 return &resource
->base
;
472 static void evergreen_set_vs_sampler_view(struct pipe_context
*ctx
, unsigned count
,
473 struct pipe_sampler_view
**views
)
475 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
476 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
478 for (int i
= 0; i
< count
; i
++) {
480 evergreen_context_pipe_state_set_vs_resource(&rctx
->ctx
, &resource
[i
]->state
, i
+ PIPE_MAX_ATTRIBS
);
485 static void evergreen_set_ps_sampler_view(struct pipe_context
*ctx
, unsigned count
,
486 struct pipe_sampler_view
**views
)
488 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
489 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
492 for (i
= 0; i
< count
; i
++) {
493 if (&rctx
->ps_samplers
.views
[i
]->base
!= views
[i
]) {
495 evergreen_context_pipe_state_set_ps_resource(&rctx
->ctx
, &resource
[i
]->state
, i
);
497 evergreen_context_pipe_state_set_ps_resource(&rctx
->ctx
, NULL
, i
);
499 pipe_sampler_view_reference(
500 (struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
],
504 for (i
= count
; i
< NUM_TEX_UNITS
; i
++) {
505 if (rctx
->ps_samplers
.views
[i
]) {
506 evergreen_context_pipe_state_set_ps_resource(&rctx
->ctx
, NULL
, i
);
507 pipe_sampler_view_reference((struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
], NULL
);
510 rctx
->ps_samplers
.n_views
= count
;
513 static void evergreen_bind_state(struct pipe_context
*ctx
, void *state
)
515 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
516 struct r600_pipe_state
*rstate
= (struct r600_pipe_state
*)state
;
520 rctx
->states
[rstate
->id
] = rstate
;
521 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
524 static void evergreen_bind_ps_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
526 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
527 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
530 memcpy(rctx
->ps_samplers
.samplers
, states
, sizeof(void*) * count
);
531 rctx
->ps_samplers
.n_samplers
= count
;
533 for (int i
= 0; i
< count
; i
++) {
534 evergreen_context_pipe_state_set_ps_sampler(&rctx
->ctx
, rstates
[i
], i
);
538 static void evergreen_bind_vs_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
540 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
541 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
543 for (int i
= 0; i
< count
; i
++) {
544 evergreen_context_pipe_state_set_vs_sampler(&rctx
->ctx
, rstates
[i
], i
);
548 static void evergreen_delete_state(struct pipe_context
*ctx
, void *state
)
550 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
551 struct r600_pipe_state
*rstate
= (struct r600_pipe_state
*)state
;
553 if (rctx
->states
[rstate
->id
] == rstate
) {
554 rctx
->states
[rstate
->id
] = NULL
;
556 for (int i
= 0; i
< rstate
->nregs
; i
++) {
557 r600_bo_reference(rctx
->radeon
, &rstate
->regs
[i
].bo
, NULL
);
562 static void evergreen_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
564 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
568 if (rctx
->vertex_elements
== state
)
569 rctx
->vertex_elements
= NULL
;
572 static void evergreen_set_clip_state(struct pipe_context
*ctx
,
573 const struct pipe_clip_state
*state
)
575 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
576 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
582 rstate
->id
= R600_PIPE_STATE_CLIP
;
583 for (int i
= 0; i
< state
->nr
; i
++) {
584 r600_pipe_state_add_reg(rstate
,
585 R_0285BC_PA_CL_UCP0_X
+ i
* 4,
586 fui(state
->ucp
[i
][0]), 0xFFFFFFFF, NULL
);
587 r600_pipe_state_add_reg(rstate
,
588 R_0285C0_PA_CL_UCP0_Y
+ i
* 4,
589 fui(state
->ucp
[i
][1]) , 0xFFFFFFFF, NULL
);
590 r600_pipe_state_add_reg(rstate
,
591 R_0285C4_PA_CL_UCP0_Z
+ i
* 4,
592 fui(state
->ucp
[i
][2]), 0xFFFFFFFF, NULL
);
593 r600_pipe_state_add_reg(rstate
,
594 R_0285C8_PA_CL_UCP0_W
+ i
* 4,
595 fui(state
->ucp
[i
][3]), 0xFFFFFFFF, NULL
);
597 r600_pipe_state_add_reg(rstate
, R_028810_PA_CL_CLIP_CNTL
,
598 S_028810_PS_UCP_MODE(3) | ((1 << state
->nr
) - 1) |
599 S_028810_ZCLIP_NEAR_DISABLE(state
->depth_clamp
) |
600 S_028810_ZCLIP_FAR_DISABLE(state
->depth_clamp
), 0xFFFFFFFF, NULL
);
602 free(rctx
->states
[R600_PIPE_STATE_CLIP
]);
603 rctx
->states
[R600_PIPE_STATE_CLIP
] = rstate
;
604 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
607 static void evergreen_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
609 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
610 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
612 rctx
->vertex_elements
= v
;
614 // rctx->vs_rebuild = TRUE;
618 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
619 const struct pipe_poly_stipple
*state
)
623 static void evergreen_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
627 static void evergreen_set_scissor_state(struct pipe_context
*ctx
,
628 const struct pipe_scissor_state
*state
)
630 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
631 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
637 rstate
->id
= R600_PIPE_STATE_SCISSOR
;
638 tl
= S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
);
639 br
= S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
);
640 r600_pipe_state_add_reg(rstate
,
641 R_028210_PA_SC_CLIPRECT_0_TL
, tl
,
643 r600_pipe_state_add_reg(rstate
,
644 R_028214_PA_SC_CLIPRECT_0_BR
, br
,
646 r600_pipe_state_add_reg(rstate
,
647 R_028218_PA_SC_CLIPRECT_1_TL
, tl
,
649 r600_pipe_state_add_reg(rstate
,
650 R_02821C_PA_SC_CLIPRECT_1_BR
, br
,
652 r600_pipe_state_add_reg(rstate
,
653 R_028220_PA_SC_CLIPRECT_2_TL
, tl
,
655 r600_pipe_state_add_reg(rstate
,
656 R_028224_PA_SC_CLIPRECT_2_BR
, br
,
658 r600_pipe_state_add_reg(rstate
,
659 R_028228_PA_SC_CLIPRECT_3_TL
, tl
,
661 r600_pipe_state_add_reg(rstate
,
662 R_02822C_PA_SC_CLIPRECT_3_BR
, br
,
665 free(rctx
->states
[R600_PIPE_STATE_SCISSOR
]);
666 rctx
->states
[R600_PIPE_STATE_SCISSOR
] = rstate
;
667 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
670 static void evergreen_set_stencil_ref(struct pipe_context
*ctx
,
671 const struct pipe_stencil_ref
*state
)
673 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
674 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
680 rctx
->stencil_ref
= *state
;
681 rstate
->id
= R600_PIPE_STATE_STENCIL_REF
;
682 tmp
= S_028430_STENCILREF(state
->ref_value
[0]);
683 r600_pipe_state_add_reg(rstate
,
684 R_028430_DB_STENCILREFMASK
, tmp
,
685 ~C_028430_STENCILREF
, NULL
);
686 tmp
= S_028434_STENCILREF_BF(state
->ref_value
[1]);
687 r600_pipe_state_add_reg(rstate
,
688 R_028434_DB_STENCILREFMASK_BF
, tmp
,
689 ~C_028434_STENCILREF_BF
, NULL
);
691 free(rctx
->states
[R600_PIPE_STATE_STENCIL_REF
]);
692 rctx
->states
[R600_PIPE_STATE_STENCIL_REF
] = rstate
;
693 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
696 static void evergreen_set_viewport_state(struct pipe_context
*ctx
,
697 const struct pipe_viewport_state
*state
)
699 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
700 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
705 rctx
->viewport
= *state
;
706 rstate
->id
= R600_PIPE_STATE_VIEWPORT
;
707 r600_pipe_state_add_reg(rstate
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 0x00000000, 0xFFFFFFFF, NULL
);
708 r600_pipe_state_add_reg(rstate
, R_0282D4_PA_SC_VPORT_ZMAX_0
, 0x3F800000, 0xFFFFFFFF, NULL
);
709 r600_pipe_state_add_reg(rstate
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]), 0xFFFFFFFF, NULL
);
710 r600_pipe_state_add_reg(rstate
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]), 0xFFFFFFFF, NULL
);
711 r600_pipe_state_add_reg(rstate
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]), 0xFFFFFFFF, NULL
);
712 r600_pipe_state_add_reg(rstate
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]), 0xFFFFFFFF, NULL
);
713 r600_pipe_state_add_reg(rstate
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]), 0xFFFFFFFF, NULL
);
714 r600_pipe_state_add_reg(rstate
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]), 0xFFFFFFFF, NULL
);
715 r600_pipe_state_add_reg(rstate
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F, 0xFFFFFFFF, NULL
);
717 free(rctx
->states
[R600_PIPE_STATE_VIEWPORT
]);
718 rctx
->states
[R600_PIPE_STATE_VIEWPORT
] = rstate
;
719 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
722 static void evergreen_cb(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
723 const struct pipe_framebuffer_state
*state
, int cb
)
725 struct r600_resource_texture
*rtex
;
726 struct r600_resource
*rbuffer
;
727 struct r600_surface
*surf
;
728 unsigned level
= state
->cbufs
[cb
]->level
;
729 unsigned pitch
, slice
;
731 unsigned format
, swap
, ntype
;
732 const struct util_format_description
*desc
;
733 struct r600_bo
*bo
[3];
735 surf
= (struct r600_surface
*)state
->cbufs
[cb
];
736 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
737 rbuffer
= &rtex
->resource
;
742 pitch
= rtex
->pitch_in_pixels
[level
] / 8 - 1;
743 slice
= rtex
->pitch_in_pixels
[level
] * surf
->aligned_height
/ 64 - 1;
745 desc
= util_format_description(rtex
->resource
.base
.b
.format
);
746 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
747 ntype
= V_028C70_NUMBER_SRGB
;
749 format
= r600_translate_colorformat(rtex
->resource
.base
.b
.format
);
750 swap
= r600_translate_colorswap(rtex
->resource
.base
.b
.format
);
751 color_info
= S_028C70_FORMAT(format
) |
752 S_028C70_COMP_SWAP(swap
) |
753 S_028C70_BLEND_CLAMP(1) |
754 S_028C70_NUMBER_TYPE(ntype
);
755 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
756 color_info
|= S_028C70_SOURCE_FORMAT(1);
758 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
759 r600_pipe_state_add_reg(rstate
,
760 R_028C60_CB_COLOR0_BASE
+ cb
* 0x3C,
761 (state
->cbufs
[cb
]->offset
+ r600_bo_offset(bo
[0])) >> 8, 0xFFFFFFFF, bo
[0]);
762 r600_pipe_state_add_reg(rstate
,
763 R_028C78_CB_COLOR0_DIM
+ cb
* 0x3C,
764 0x0, 0xFFFFFFFF, NULL
);
765 r600_pipe_state_add_reg(rstate
,
766 R_028C70_CB_COLOR0_INFO
+ cb
* 0x3C,
767 color_info
, 0xFFFFFFFF, bo
[0]);
768 r600_pipe_state_add_reg(rstate
,
769 R_028C64_CB_COLOR0_PITCH
+ cb
* 0x3C,
770 S_028C64_PITCH_TILE_MAX(pitch
),
772 r600_pipe_state_add_reg(rstate
,
773 R_028C68_CB_COLOR0_SLICE
+ cb
* 0x3C,
774 S_028C68_SLICE_TILE_MAX(slice
),
776 r600_pipe_state_add_reg(rstate
,
777 R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C,
778 0x00000000, 0xFFFFFFFF, NULL
);
779 r600_pipe_state_add_reg(rstate
,
780 R_028C74_CB_COLOR0_ATTRIB
+ cb
* 0x3C,
781 S_028C74_NON_DISP_TILING_ORDER(1),
785 static void evergreen_db(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
786 const struct pipe_framebuffer_state
*state
)
788 struct r600_resource_texture
*rtex
;
789 struct r600_resource
*rbuffer
;
790 struct r600_surface
*surf
;
792 unsigned pitch
, slice
, format
, stencil_format
;
794 if (state
->zsbuf
== NULL
)
797 level
= state
->zsbuf
->level
;
799 surf
= (struct r600_surface
*)state
->zsbuf
;
800 rtex
= (struct r600_resource_texture
*)state
->zsbuf
->texture
;
802 rtex
->array_mode
[level
] = 2;
805 rbuffer
= &rtex
->resource
;
807 pitch
= rtex
->pitch_in_pixels
[level
] / 8 - 1;
808 slice
= rtex
->pitch_in_pixels
[level
] * surf
->aligned_height
/ 64 - 1;
809 format
= r600_translate_dbformat(state
->zsbuf
->texture
->format
);
810 stencil_format
= r600_translate_stencilformat(state
->zsbuf
->texture
->format
);
812 r600_pipe_state_add_reg(rstate
, R_028048_DB_Z_READ_BASE
,
813 (state
->zsbuf
->offset
+ r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
814 r600_pipe_state_add_reg(rstate
, R_028050_DB_Z_WRITE_BASE
,
815 (state
->zsbuf
->offset
+ r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
817 if (stencil_format
) {
818 uint32_t stencil_offset
;
820 stencil_offset
= ((surf
->aligned_height
* rtex
->pitch_in_bytes
[level
]) + 255) & ~255;
821 r600_pipe_state_add_reg(rstate
, R_02804C_DB_STENCIL_READ_BASE
,
822 (state
->zsbuf
->offset
+ stencil_offset
+ r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
823 r600_pipe_state_add_reg(rstate
, R_028054_DB_STENCIL_WRITE_BASE
,
824 (state
->zsbuf
->offset
+ stencil_offset
+ r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
827 r600_pipe_state_add_reg(rstate
, R_028008_DB_DEPTH_VIEW
, 0x00000000, 0xFFFFFFFF, NULL
);
828 r600_pipe_state_add_reg(rstate
, R_028044_DB_STENCIL_INFO
,
829 S_028044_FORMAT(stencil_format
), 0xFFFFFFFF, rbuffer
->bo
);
831 r600_pipe_state_add_reg(rstate
, R_028040_DB_Z_INFO
,
832 S_028040_ARRAY_MODE(rtex
->array_mode
[level
]) | S_028040_FORMAT(format
),
833 0xFFFFFFFF, rbuffer
->bo
);
834 r600_pipe_state_add_reg(rstate
, R_028058_DB_DEPTH_SIZE
,
835 S_028058_PITCH_TILE_MAX(pitch
),
837 r600_pipe_state_add_reg(rstate
, R_02805C_DB_DEPTH_SLICE
,
838 S_02805C_SLICE_TILE_MAX(slice
),
842 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
843 const struct pipe_framebuffer_state
*state
)
845 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
846 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
847 u32 shader_mask
, tl
, br
, target_mask
;
852 /* unreference old buffer and reference new one */
853 rstate
->id
= R600_PIPE_STATE_FRAMEBUFFER
;
855 util_copy_framebuffer_state(&rctx
->framebuffer
, state
);
857 rctx
->pframebuffer
= &rctx
->framebuffer
;
860 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
861 evergreen_cb(rctx
, rstate
, state
, i
);
864 evergreen_db(rctx
, rstate
, state
);
867 target_mask
= 0x00000000;
868 target_mask
= 0xFFFFFFFF;
870 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
871 target_mask
^= 0xf << (i
* 4);
872 shader_mask
|= 0xf << (i
* 4);
874 tl
= S_028240_TL_X(0) | S_028240_TL_Y(0);
875 br
= S_028244_BR_X(state
->width
) | S_028244_BR_Y(state
->height
);
877 r600_pipe_state_add_reg(rstate
,
878 R_028240_PA_SC_GENERIC_SCISSOR_TL
, tl
,
880 r600_pipe_state_add_reg(rstate
,
881 R_028244_PA_SC_GENERIC_SCISSOR_BR
, br
,
883 r600_pipe_state_add_reg(rstate
,
884 R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
,
886 r600_pipe_state_add_reg(rstate
,
887 R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
,
889 r600_pipe_state_add_reg(rstate
,
890 R_028030_PA_SC_SCREEN_SCISSOR_TL
, tl
,
892 r600_pipe_state_add_reg(rstate
,
893 R_028034_PA_SC_SCREEN_SCISSOR_BR
, br
,
895 r600_pipe_state_add_reg(rstate
,
896 R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
,
898 r600_pipe_state_add_reg(rstate
,
899 R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
,
901 r600_pipe_state_add_reg(rstate
,
902 R_028200_PA_SC_WINDOW_OFFSET
, 0x00000000,
904 r600_pipe_state_add_reg(rstate
,
905 R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA,
908 r600_pipe_state_add_reg(rstate
, R_028238_CB_TARGET_MASK
,
909 0x00000000, target_mask
, NULL
);
910 r600_pipe_state_add_reg(rstate
, R_02823C_CB_SHADER_MASK
,
911 shader_mask
, 0xFFFFFFFF, NULL
);
912 r600_pipe_state_add_reg(rstate
, R_028C04_PA_SC_AA_CONFIG
,
913 0x00000000, 0xFFFFFFFF, NULL
);
914 r600_pipe_state_add_reg(rstate
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
,
915 0x00000000, 0xFFFFFFFF, NULL
);
917 free(rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
]);
918 rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
] = rstate
;
919 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
922 static void evergreen_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
923 struct pipe_resource
*buffer
)
925 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
926 struct r600_resource
*rbuffer
= (struct r600_resource
*)buffer
;
929 case PIPE_SHADER_VERTEX
:
930 rctx
->vs_const_buffer
.nregs
= 0;
931 r600_pipe_state_add_reg(&rctx
->vs_const_buffer
,
932 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
933 ALIGN_DIVUP(buffer
->width0
>> 4, 16),
935 r600_pipe_state_add_reg(&rctx
->vs_const_buffer
,
936 R_028980_ALU_CONST_CACHE_VS_0
,
937 (r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
938 r600_context_pipe_state_set(&rctx
->ctx
, &rctx
->vs_const_buffer
);
940 case PIPE_SHADER_FRAGMENT
:
941 rctx
->ps_const_buffer
.nregs
= 0;
942 r600_pipe_state_add_reg(&rctx
->ps_const_buffer
,
943 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
944 ALIGN_DIVUP(buffer
->width0
>> 4, 16),
946 r600_pipe_state_add_reg(&rctx
->ps_const_buffer
,
947 R_028940_ALU_CONST_CACHE_PS_0
,
948 (r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
949 r600_context_pipe_state_set(&rctx
->ctx
, &rctx
->ps_const_buffer
);
952 R600_ERR("unsupported %d\n", shader
);
957 static void *evergreen_create_shader_state(struct pipe_context
*ctx
,
958 const struct pipe_shader_state
*state
)
960 struct r600_pipe_shader
*shader
= CALLOC_STRUCT(r600_pipe_shader
);
963 r
= r600_pipe_shader_create(ctx
, shader
, state
->tokens
);
970 static void evergreen_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
972 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
974 /* TODO delete old shader */
975 rctx
->ps_shader
= (struct r600_pipe_shader
*)state
;
978 static void evergreen_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
980 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
982 /* TODO delete old shader */
983 rctx
->vs_shader
= (struct r600_pipe_shader
*)state
;
986 static void evergreen_delete_ps_shader(struct pipe_context
*ctx
, void *state
)
988 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
989 struct r600_pipe_shader
*shader
= (struct r600_pipe_shader
*)state
;
991 if (rctx
->ps_shader
== shader
) {
992 rctx
->ps_shader
= NULL
;
994 /* TODO proper delete */
998 static void evergreen_delete_vs_shader(struct pipe_context
*ctx
, void *state
)
1000 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1001 struct r600_pipe_shader
*shader
= (struct r600_pipe_shader
*)state
;
1003 if (rctx
->vs_shader
== shader
) {
1004 rctx
->vs_shader
= NULL
;
1006 /* TODO proper delete */
1010 void evergreen_init_state_functions(struct r600_pipe_context
*rctx
)
1012 rctx
->context
.create_blend_state
= evergreen_create_blend_state
;
1013 rctx
->context
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
1014 rctx
->context
.create_fs_state
= evergreen_create_shader_state
;
1015 rctx
->context
.create_rasterizer_state
= evergreen_create_rs_state
;
1016 rctx
->context
.create_sampler_state
= evergreen_create_sampler_state
;
1017 rctx
->context
.create_sampler_view
= evergreen_create_sampler_view
;
1018 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
1019 rctx
->context
.create_vs_state
= evergreen_create_shader_state
;
1020 rctx
->context
.bind_blend_state
= evergreen_bind_blend_state
;
1021 rctx
->context
.bind_depth_stencil_alpha_state
= evergreen_bind_state
;
1022 rctx
->context
.bind_fragment_sampler_states
= evergreen_bind_ps_sampler
;
1023 rctx
->context
.bind_fs_state
= evergreen_bind_ps_shader
;
1024 rctx
->context
.bind_rasterizer_state
= evergreen_bind_rs_state
;
1025 rctx
->context
.bind_vertex_elements_state
= evergreen_bind_vertex_elements
;
1026 rctx
->context
.bind_vertex_sampler_states
= evergreen_bind_vs_sampler
;
1027 rctx
->context
.bind_vs_state
= evergreen_bind_vs_shader
;
1028 rctx
->context
.delete_blend_state
= evergreen_delete_state
;
1029 rctx
->context
.delete_depth_stencil_alpha_state
= evergreen_delete_state
;
1030 rctx
->context
.delete_fs_state
= evergreen_delete_ps_shader
;
1031 rctx
->context
.delete_rasterizer_state
= evergreen_delete_rs_state
;
1032 rctx
->context
.delete_sampler_state
= evergreen_delete_state
;
1033 rctx
->context
.delete_vertex_elements_state
= evergreen_delete_vertex_element
;
1034 rctx
->context
.delete_vs_state
= evergreen_delete_vs_shader
;
1035 rctx
->context
.set_blend_color
= evergreen_set_blend_color
;
1036 rctx
->context
.set_clip_state
= evergreen_set_clip_state
;
1037 rctx
->context
.set_constant_buffer
= evergreen_set_constant_buffer
;
1038 rctx
->context
.set_fragment_sampler_views
= evergreen_set_ps_sampler_view
;
1039 rctx
->context
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
1040 rctx
->context
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
1041 rctx
->context
.set_sample_mask
= evergreen_set_sample_mask
;
1042 rctx
->context
.set_scissor_state
= evergreen_set_scissor_state
;
1043 rctx
->context
.set_stencil_ref
= evergreen_set_stencil_ref
;
1044 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1045 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1046 rctx
->context
.set_vertex_sampler_views
= evergreen_set_vs_sampler_view
;
1047 rctx
->context
.set_viewport_state
= evergreen_set_viewport_state
;
1048 rctx
->context
.sampler_view_destroy
= evergreen_sampler_view_destroy
;
1051 void evergreen_init_config(struct r600_pipe_context
*rctx
)
1053 struct r600_pipe_state
*rstate
= &rctx
->config
;
1058 int hs_prio
, cs_prio
, ls_prio
;
1072 int num_ps_stack_entries
;
1073 int num_vs_stack_entries
;
1074 int num_gs_stack_entries
;
1075 int num_es_stack_entries
;
1076 int num_hs_stack_entries
;
1077 int num_ls_stack_entries
;
1078 enum radeon_family family
;
1081 family
= r600_get_family(rctx
->radeon
);
1100 num_ps_threads
= 96;
1101 num_vs_threads
= 16;
1102 num_gs_threads
= 16;
1103 num_es_threads
= 16;
1104 num_hs_threads
= 16;
1105 num_ls_threads
= 16;
1106 num_ps_stack_entries
= 42;
1107 num_vs_stack_entries
= 42;
1108 num_gs_stack_entries
= 42;
1109 num_es_stack_entries
= 42;
1110 num_hs_stack_entries
= 42;
1111 num_ls_stack_entries
= 42;
1121 num_ps_threads
= 128;
1122 num_vs_threads
= 20;
1123 num_gs_threads
= 20;
1124 num_es_threads
= 20;
1125 num_hs_threads
= 20;
1126 num_ls_threads
= 20;
1127 num_ps_stack_entries
= 42;
1128 num_vs_stack_entries
= 42;
1129 num_gs_stack_entries
= 42;
1130 num_es_stack_entries
= 42;
1131 num_hs_stack_entries
= 42;
1132 num_ls_stack_entries
= 42;
1142 num_ps_threads
= 128;
1143 num_vs_threads
= 20;
1144 num_gs_threads
= 20;
1145 num_es_threads
= 20;
1146 num_hs_threads
= 20;
1147 num_ls_threads
= 20;
1148 num_ps_stack_entries
= 85;
1149 num_vs_stack_entries
= 85;
1150 num_gs_stack_entries
= 85;
1151 num_es_stack_entries
= 85;
1152 num_hs_stack_entries
= 85;
1153 num_ls_stack_entries
= 85;
1164 num_ps_threads
= 128;
1165 num_vs_threads
= 20;
1166 num_gs_threads
= 20;
1167 num_es_threads
= 20;
1168 num_hs_threads
= 20;
1169 num_ls_threads
= 20;
1170 num_ps_stack_entries
= 85;
1171 num_vs_stack_entries
= 85;
1172 num_gs_stack_entries
= 85;
1173 num_es_stack_entries
= 85;
1174 num_hs_stack_entries
= 85;
1175 num_ls_stack_entries
= 85;
1184 tmp
|= S_008C00_VC_ENABLE(1);
1187 tmp
|= S_008C00_EXPORT_SRC_C(1);
1188 tmp
|= S_008C00_CS_PRIO(cs_prio
);
1189 tmp
|= S_008C00_LS_PRIO(ls_prio
);
1190 tmp
|= S_008C00_HS_PRIO(hs_prio
);
1191 tmp
|= S_008C00_PS_PRIO(ps_prio
);
1192 tmp
|= S_008C00_VS_PRIO(vs_prio
);
1193 tmp
|= S_008C00_GS_PRIO(gs_prio
);
1194 tmp
|= S_008C00_ES_PRIO(es_prio
);
1195 r600_pipe_state_add_reg(rstate
, R_008C00_SQ_CONFIG
, tmp
, 0xFFFFFFFF, NULL
);
1198 tmp
|= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
1199 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
1200 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
1201 r600_pipe_state_add_reg(rstate
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
);
1204 tmp
|= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
1205 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
1206 r600_pipe_state_add_reg(rstate
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
);
1209 tmp
|= S_008C0C_NUM_HS_GPRS(num_hs_gprs
);
1210 tmp
|= S_008C0C_NUM_LS_GPRS(num_ls_gprs
);
1211 r600_pipe_state_add_reg(rstate
, R_008C0C_SQ_GPR_RESOURCE_MGMT_3
, tmp
, 0xFFFFFFFF, NULL
);
1214 tmp
|= S_008C18_NUM_PS_THREADS(num_ps_threads
);
1215 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
1216 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
1217 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
1218 r600_pipe_state_add_reg(rstate
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
);
1221 tmp
|= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
1222 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
1223 r600_pipe_state_add_reg(rstate
, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
);
1226 tmp
|= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
1227 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
1228 r600_pipe_state_add_reg(rstate
, R_008C20_SQ_STACK_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
);
1231 tmp
|= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
1232 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
1233 r600_pipe_state_add_reg(rstate
, R_008C24_SQ_STACK_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
);
1236 tmp
|= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
1237 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
1238 r600_pipe_state_add_reg(rstate
, R_008C28_SQ_STACK_RESOURCE_MGMT_3
, tmp
, 0xFFFFFFFF, NULL
);
1240 r600_pipe_state_add_reg(rstate
, R_009100_SPI_CONFIG_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1241 r600_pipe_state_add_reg(rstate
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL
);
1243 // r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1245 // r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1246 r600_pipe_state_add_reg(rstate
, R_028A48_PA_SC_MODE_CNTL_0
, 0x0, 0xFFFFFFFF, NULL
);
1247 r600_pipe_state_add_reg(rstate
, R_028A4C_PA_SC_MODE_CNTL_1
, 0x0, 0xFFFFFFFF, NULL
);
1249 r600_pipe_state_add_reg(rstate
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1250 r600_pipe_state_add_reg(rstate
, R_028904_SQ_GSVS_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1251 r600_pipe_state_add_reg(rstate
, R_028908_SQ_ESTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1252 r600_pipe_state_add_reg(rstate
, R_02890C_SQ_GSTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1253 r600_pipe_state_add_reg(rstate
, R_028910_SQ_VSTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1254 r600_pipe_state_add_reg(rstate
, R_028914_SQ_PSTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1256 r600_pipe_state_add_reg(rstate
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1257 r600_pipe_state_add_reg(rstate
, R_028920_SQ_GS_VERT_ITEMSIZE_1
, 0x0, 0xFFFFFFFF, NULL
);
1258 r600_pipe_state_add_reg(rstate
, R_028924_SQ_GS_VERT_ITEMSIZE_2
, 0x0, 0xFFFFFFFF, NULL
);
1259 r600_pipe_state_add_reg(rstate
, R_028928_SQ_GS_VERT_ITEMSIZE_3
, 0x0, 0xFFFFFFFF, NULL
);
1261 r600_pipe_state_add_reg(rstate
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1262 r600_pipe_state_add_reg(rstate
, R_028A14_VGT_HOS_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1263 r600_pipe_state_add_reg(rstate
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x0, 0xFFFFFFFF, NULL
);
1264 r600_pipe_state_add_reg(rstate
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x0, 0xFFFFFFFF, NULL
);
1265 r600_pipe_state_add_reg(rstate
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x0, 0xFFFFFFFF, NULL
);
1266 r600_pipe_state_add_reg(rstate
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x0, 0xFFFFFFFF, NULL
);
1267 r600_pipe_state_add_reg(rstate
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x0, 0xFFFFFFFF, NULL
);
1268 r600_pipe_state_add_reg(rstate
, R_028A2C_VGT_GROUP_DECR
, 0x0, 0xFFFFFFFF, NULL
);
1269 r600_pipe_state_add_reg(rstate
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1270 r600_pipe_state_add_reg(rstate
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1271 r600_pipe_state_add_reg(rstate
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1272 r600_pipe_state_add_reg(rstate
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1273 r600_pipe_state_add_reg(rstate
, R_028A40_VGT_GS_MODE
, 0x0, 0xFFFFFFFF, NULL
);
1274 r600_pipe_state_add_reg(rstate
, R_028B94_VGT_STRMOUT_CONFIG
, 0x0, 0xFFFFFFFF, NULL
);
1275 r600_pipe_state_add_reg(rstate
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0, 0xFFFFFFFF, NULL
);
1276 r600_pipe_state_add_reg(rstate
, R_028AB4_VGT_REUSE_OFF
, 0x00000000, 0xFFFFFFFF, NULL
);
1277 r600_pipe_state_add_reg(rstate
, R_028AB8_VGT_VTX_CNT_EN
, 0x0, 0xFFFFFFFF, NULL
);
1278 r600_pipe_state_add_reg(rstate
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1, 0xFFFFFFFF, NULL
);
1280 r600_pipe_state_add_reg(rstate
, R_028380_SQ_VTX_SEMANTIC_0
, 0x0, 0xFFFFFFFF, NULL
);
1281 r600_pipe_state_add_reg(rstate
, R_028384_SQ_VTX_SEMANTIC_1
, 0x0, 0xFFFFFFFF, NULL
);
1282 r600_pipe_state_add_reg(rstate
, R_028388_SQ_VTX_SEMANTIC_2
, 0x0, 0xFFFFFFFF, NULL
);
1283 r600_pipe_state_add_reg(rstate
, R_02838C_SQ_VTX_SEMANTIC_3
, 0x0, 0xFFFFFFFF, NULL
);
1284 r600_pipe_state_add_reg(rstate
, R_028390_SQ_VTX_SEMANTIC_4
, 0x0, 0xFFFFFFFF, NULL
);
1285 r600_pipe_state_add_reg(rstate
, R_028394_SQ_VTX_SEMANTIC_5
, 0x0, 0xFFFFFFFF, NULL
);
1286 r600_pipe_state_add_reg(rstate
, R_028398_SQ_VTX_SEMANTIC_6
, 0x0, 0xFFFFFFFF, NULL
);
1287 r600_pipe_state_add_reg(rstate
, R_02839C_SQ_VTX_SEMANTIC_7
, 0x0, 0xFFFFFFFF, NULL
);
1288 r600_pipe_state_add_reg(rstate
, R_0283A0_SQ_VTX_SEMANTIC_8
, 0x0, 0xFFFFFFFF, NULL
);
1289 r600_pipe_state_add_reg(rstate
, R_0283A4_SQ_VTX_SEMANTIC_9
, 0x0, 0xFFFFFFFF, NULL
);
1290 r600_pipe_state_add_reg(rstate
, R_0283A8_SQ_VTX_SEMANTIC_10
, 0x0, 0xFFFFFFFF, NULL
);
1291 r600_pipe_state_add_reg(rstate
, R_0283AC_SQ_VTX_SEMANTIC_11
, 0x0, 0xFFFFFFFF, NULL
);
1292 r600_pipe_state_add_reg(rstate
, R_0283B0_SQ_VTX_SEMANTIC_12
, 0x0, 0xFFFFFFFF, NULL
);
1293 r600_pipe_state_add_reg(rstate
, R_0283B4_SQ_VTX_SEMANTIC_13
, 0x0, 0xFFFFFFFF, NULL
);
1294 r600_pipe_state_add_reg(rstate
, R_0283B8_SQ_VTX_SEMANTIC_14
, 0x0, 0xFFFFFFFF, NULL
);
1295 r600_pipe_state_add_reg(rstate
, R_0283BC_SQ_VTX_SEMANTIC_15
, 0x0, 0xFFFFFFFF, NULL
);
1296 r600_pipe_state_add_reg(rstate
, R_0283C0_SQ_VTX_SEMANTIC_16
, 0x0, 0xFFFFFFFF, NULL
);
1297 r600_pipe_state_add_reg(rstate
, R_0283C4_SQ_VTX_SEMANTIC_17
, 0x0, 0xFFFFFFFF, NULL
);
1298 r600_pipe_state_add_reg(rstate
, R_0283C8_SQ_VTX_SEMANTIC_18
, 0x0, 0xFFFFFFFF, NULL
);
1299 r600_pipe_state_add_reg(rstate
, R_0283CC_SQ_VTX_SEMANTIC_19
, 0x0, 0xFFFFFFFF, NULL
);
1300 r600_pipe_state_add_reg(rstate
, R_0283D0_SQ_VTX_SEMANTIC_20
, 0x0, 0xFFFFFFFF, NULL
);
1301 r600_pipe_state_add_reg(rstate
, R_0283D4_SQ_VTX_SEMANTIC_21
, 0x0, 0xFFFFFFFF, NULL
);
1302 r600_pipe_state_add_reg(rstate
, R_0283D8_SQ_VTX_SEMANTIC_22
, 0x0, 0xFFFFFFFF, NULL
);
1303 r600_pipe_state_add_reg(rstate
, R_0283DC_SQ_VTX_SEMANTIC_23
, 0x0, 0xFFFFFFFF, NULL
);
1304 r600_pipe_state_add_reg(rstate
, R_0283E0_SQ_VTX_SEMANTIC_24
, 0x0, 0xFFFFFFFF, NULL
);
1305 r600_pipe_state_add_reg(rstate
, R_0283E4_SQ_VTX_SEMANTIC_25
, 0x0, 0xFFFFFFFF, NULL
);
1306 r600_pipe_state_add_reg(rstate
, R_0283E8_SQ_VTX_SEMANTIC_26
, 0x0, 0xFFFFFFFF, NULL
);
1307 r600_pipe_state_add_reg(rstate
, R_0283EC_SQ_VTX_SEMANTIC_27
, 0x0, 0xFFFFFFFF, NULL
);
1308 r600_pipe_state_add_reg(rstate
, R_0283F0_SQ_VTX_SEMANTIC_28
, 0x0, 0xFFFFFFFF, NULL
);
1309 r600_pipe_state_add_reg(rstate
, R_0283F4_SQ_VTX_SEMANTIC_29
, 0x0, 0xFFFFFFFF, NULL
);
1310 r600_pipe_state_add_reg(rstate
, R_0283F8_SQ_VTX_SEMANTIC_30
, 0x0, 0xFFFFFFFF, NULL
);
1311 r600_pipe_state_add_reg(rstate
, R_0283FC_SQ_VTX_SEMANTIC_31
, 0x0, 0xFFFFFFFF, NULL
);
1313 r600_pipe_state_add_reg(rstate
, R_028810_PA_CL_CLIP_CNTL
,
1314 0x0, 0xFFFFFFFF, NULL
);
1316 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1319 int r600_conv_pipe_prim(unsigned pprim
, unsigned *prim
);
1320 void evergreen_draw(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
1322 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1323 struct r600_pipe_state
*rstate
;
1324 struct r600_resource
*rbuffer
;
1325 unsigned i
, j
, offset
, prim
;
1326 u32 vgt_dma_index_type
, vgt_draw_initiator
, mask
;
1327 struct pipe_vertex_buffer
*vertex_buffer
;
1328 struct r600_draw rdraw
;
1329 struct r600_pipe_state vgt
;
1330 struct r600_drawl draw
;
1331 boolean translate
= FALSE
;
1333 if (rctx
->vertex_elements
->incompatible_layout
) {
1334 r600_begin_vertex_translate(rctx
);
1338 if (rctx
->any_user_vbs
) {
1339 r600_upload_user_buffers(rctx
);
1340 rctx
->any_user_vbs
= FALSE
;
1343 memset(&draw
, 0, sizeof(struct r600_drawl
));
1345 draw
.mode
= info
->mode
;
1346 draw
.start
= info
->start
;
1347 draw
.count
= info
->count
;
1348 if (info
->indexed
&& rctx
->index_buffer
.buffer
) {
1349 draw
.start
+= rctx
->index_buffer
.offset
/ rctx
->index_buffer
.index_size
;
1350 draw
.min_index
= info
->min_index
;
1351 draw
.max_index
= info
->max_index
;
1352 draw
.index_bias
= info
->index_bias
;
1354 r600_translate_index_buffer(rctx
, &rctx
->index_buffer
.buffer
,
1355 &rctx
->index_buffer
.index_size
,
1359 draw
.index_size
= rctx
->index_buffer
.index_size
;
1360 pipe_resource_reference(&draw
.index_buffer
, rctx
->index_buffer
.buffer
);
1361 draw
.index_buffer_offset
= draw
.start
* draw
.index_size
;
1363 r600_upload_index_buffer(rctx
, &draw
);
1365 draw
.index_size
= 0;
1366 draw
.index_buffer
= NULL
;
1367 draw
.min_index
= info
->min_index
;
1368 draw
.max_index
= info
->max_index
;
1369 draw
.index_bias
= info
->start
;
1372 switch (draw
.index_size
) {
1374 vgt_draw_initiator
= 0;
1375 vgt_dma_index_type
= 0;
1378 vgt_draw_initiator
= 0;
1379 vgt_dma_index_type
= 1;
1382 vgt_draw_initiator
= 2;
1383 vgt_dma_index_type
= 0;
1386 R600_ERR("unsupported index size %d\n", draw
.index_size
);
1389 if (r600_conv_pipe_prim(draw
.mode
, &prim
))
1392 /* rebuild vertex shader if input format changed */
1393 if (r600_pipe_shader_update(&rctx
->context
, rctx
->vs_shader
))
1395 if (r600_pipe_shader_update(&rctx
->context
, rctx
->ps_shader
))
1398 for (i
= 0 ; i
< rctx
->vertex_elements
->count
; i
++) {
1399 uint32_t word3
, word2
;
1401 rstate
= &rctx
->vs_resource
[i
];
1403 rstate
->id
= R600_PIPE_STATE_RESOURCE
;
1406 j
= rctx
->vertex_elements
->elements
[i
].vertex_buffer_index
;
1407 vertex_buffer
= &rctx
->vertex_buffer
[j
];
1408 rbuffer
= (struct r600_resource
*)vertex_buffer
->buffer
;
1409 offset
= rctx
->vertex_elements
->elements
[i
].src_offset
+
1410 vertex_buffer
->buffer_offset
+
1411 r600_bo_offset(rbuffer
->bo
);
1413 format
= r600_translate_vertex_data_type(rctx
->vertex_elements
->hw_format
[i
]);
1415 word2
= format
| S_030008_STRIDE(vertex_buffer
->stride
);
1417 word3
= r600_translate_vertex_data_swizzle(rctx
->vertex_elements
->hw_format
[i
]);
1419 r600_pipe_state_add_reg(rstate
, R_030000_RESOURCE0_WORD0
, offset
, 0xFFFFFFFF, rbuffer
->bo
);
1420 r600_pipe_state_add_reg(rstate
, R_030004_RESOURCE0_WORD1
, rbuffer
->size
- offset
- 1, 0xFFFFFFFF, NULL
);
1421 r600_pipe_state_add_reg(rstate
, R_030008_RESOURCE0_WORD2
, word2
, 0xFFFFFFFF, NULL
);
1422 r600_pipe_state_add_reg(rstate
, R_03000C_RESOURCE0_WORD3
, word3
, 0xFFFFFFFF, NULL
);
1423 r600_pipe_state_add_reg(rstate
, R_030010_RESOURCE0_WORD4
, 0x00000000, 0xFFFFFFFF, NULL
);
1424 r600_pipe_state_add_reg(rstate
, R_030014_RESOURCE0_WORD5
, 0x00000000, 0xFFFFFFFF, NULL
);
1425 r600_pipe_state_add_reg(rstate
, R_030018_RESOURCE0_WORD6
, 0x00000000, 0xFFFFFFFF, NULL
);
1426 r600_pipe_state_add_reg(rstate
, R_03001C_RESOURCE0_WORD7
, 0xC0000000, 0xFFFFFFFF, NULL
);
1427 evergreen_vs_resource_set(&rctx
->ctx
, rstate
, i
);
1431 for (int i
= 0; i
< rctx
->framebuffer
.nr_cbufs
; i
++) {
1432 mask
|= (0xF << (i
* 4));
1435 vgt
.id
= R600_PIPE_STATE_VGT
;
1437 r600_pipe_state_add_reg(&vgt
, R_008958_VGT_PRIMITIVE_TYPE
, prim
, 0xFFFFFFFF, NULL
);
1438 r600_pipe_state_add_reg(&vgt
, R_028408_VGT_INDX_OFFSET
, draw
.index_bias
, 0xFFFFFFFF, NULL
);
1439 r600_pipe_state_add_reg(&vgt
, R_028238_CB_TARGET_MASK
, rctx
->cb_target_mask
& mask
, 0xFFFFFFFF, NULL
);
1440 r600_pipe_state_add_reg(&vgt
, R_028400_VGT_MAX_VTX_INDX
, draw
.max_index
, 0xFFFFFFFF, NULL
);
1441 r600_pipe_state_add_reg(&vgt
, R_028404_VGT_MIN_VTX_INDX
, draw
.min_index
, 0xFFFFFFFF, NULL
);
1442 r600_pipe_state_add_reg(&vgt
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0, 0xFFFFFFFF, NULL
);
1443 r600_pipe_state_add_reg(&vgt
, R_03CFF4_SQ_VTX_START_INST_LOC
, 0, 0xFFFFFFFF, NULL
);
1445 if (rctx
->rasterizer
&& rctx
->framebuffer
.zsbuf
) {
1446 float offset_units
= rctx
->rasterizer
->offset_units
;
1447 unsigned offset_db_fmt_cntl
= 0, depth
;
1449 switch (rctx
->framebuffer
.zsbuf
->texture
->format
) {
1450 case PIPE_FORMAT_Z24X8_UNORM
:
1451 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
1453 offset_units
*= 2.0f
;
1455 case PIPE_FORMAT_Z32_FLOAT
:
1457 offset_units
*= 1.0f
;
1458 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1460 case PIPE_FORMAT_Z16_UNORM
:
1462 offset_units
*= 4.0f
;
1467 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
1468 r600_pipe_state_add_reg(&vgt
,
1469 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
1470 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
);
1471 r600_pipe_state_add_reg(&vgt
,
1472 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
1473 fui(offset_units
), 0xFFFFFFFF, NULL
);
1474 r600_pipe_state_add_reg(&vgt
,
1475 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
1476 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
);
1477 r600_pipe_state_add_reg(&vgt
,
1478 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
1479 fui(offset_units
), 0xFFFFFFFF, NULL
);
1480 r600_pipe_state_add_reg(&vgt
,
1481 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1482 offset_db_fmt_cntl
, 0xFFFFFFFF, NULL
);
1484 r600_context_pipe_state_set(&rctx
->ctx
, &vgt
);
1486 rdraw
.vgt_num_indices
= draw
.count
;
1487 rdraw
.vgt_num_instances
= 1;
1488 rdraw
.vgt_index_type
= vgt_dma_index_type
;
1489 rdraw
.vgt_draw_initiator
= vgt_draw_initiator
;
1490 rdraw
.indices
= NULL
;
1491 if (draw
.index_buffer
) {
1492 rbuffer
= (struct r600_resource
*)draw
.index_buffer
;
1493 rdraw
.indices
= rbuffer
->bo
;
1494 rdraw
.indices_bo_offset
= draw
.index_buffer_offset
;
1496 evergreen_context_draw(&rctx
->ctx
, &rdraw
);
1499 r600_end_vertex_translate(rctx
);
1501 pipe_resource_reference(&draw
.index_buffer
, NULL
);
1504 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
1506 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1507 struct r600_pipe_state
*rstate
= &shader
->rstate
;
1508 struct r600_shader
*rshader
= &shader
->shader
;
1509 unsigned i
, tmp
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
;
1510 int pos_index
= -1, face_index
= -1;
1512 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
1513 unsigned spi_baryc_cntl
;
1515 /* clear previous register */
1518 for (i
= 0; i
< rshader
->ninput
; i
++) {
1519 tmp
= S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx
->vs_shader
->shader
, rshader
, i
));
1520 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1521 POSITION goes via GPRs from the SC so isn't counted */
1522 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
1524 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
1527 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
||
1528 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
1530 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
1532 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
1533 have_perspective
= TRUE
;
1534 if (rshader
->input
[i
].centroid
)
1535 have_centroid
= TRUE
;
1537 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
||
1538 rshader
->input
[i
].name
== TGSI_SEMANTIC_BCOLOR
||
1539 rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
) {
1540 tmp
|= S_028644_FLAT_SHADE(rshader
->flat_shade
);
1542 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
1543 rctx
->sprite_coord_enable
& (1 << rshader
->input
[i
].sid
)) {
1544 tmp
|= S_028644_PT_SPRITE_TEX(1);
1546 r600_pipe_state_add_reg(rstate
, R_028644_SPI_PS_INPUT_CNTL_0
+ i
* 4, tmp
, 0xFFFFFFFF, NULL
);
1548 for (i
= 0; i
< rshader
->noutput
; i
++) {
1549 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
1550 r600_pipe_state_add_reg(rstate
,
1551 R_02880C_DB_SHADER_CONTROL
,
1552 S_02880C_Z_EXPORT_ENABLE(1),
1553 S_02880C_Z_EXPORT_ENABLE(1), NULL
);
1554 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
1555 r600_pipe_state_add_reg(rstate
,
1556 R_02880C_DB_SHADER_CONTROL
,
1557 S_02880C_STENCIL_EXPORT_ENABLE(1),
1558 S_02880C_STENCIL_EXPORT_ENABLE(1), NULL
);
1563 for (i
= 0; i
< rshader
->noutput
; i
++) {
1564 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
1565 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
1567 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
1571 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
1573 /* always at least export 1 component per pixel */
1579 have_perspective
= TRUE
;
1582 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
1583 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
1584 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
1586 if (pos_index
!= -1) {
1587 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
1588 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
1589 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
1593 spi_ps_in_control_1
= 0;
1594 if (face_index
!= -1) {
1595 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
1596 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
1600 if (have_perspective
)
1601 spi_baryc_cntl
|= S_0286E0_PERSP_CENTER_ENA(1) |
1602 S_0286E0_PERSP_CENTROID_ENA(have_centroid
);
1604 spi_baryc_cntl
|= S_0286E0_LINEAR_CENTER_ENA(1) |
1605 S_0286E0_LINEAR_CENTROID_ENA(have_centroid
);
1607 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
,
1608 spi_ps_in_control_0
, 0xFFFFFFFF, NULL
);
1609 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
,
1610 spi_ps_in_control_1
, 0xFFFFFFFF, NULL
);
1611 r600_pipe_state_add_reg(rstate
, R_0286E4_SPI_PS_IN_CONTROL_2
,
1612 0, 0xFFFFFFFF, NULL
);
1613 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
, 0xFFFFFFFF, NULL
);
1614 r600_pipe_state_add_reg(rstate
,
1615 R_0286E0_SPI_BARYC_CNTL
,
1619 r600_pipe_state_add_reg(rstate
,
1620 R_028840_SQ_PGM_START_PS
,
1621 (r600_bo_offset(shader
->bo
)) >> 8, 0xFFFFFFFF, shader
->bo
);
1622 r600_pipe_state_add_reg(rstate
,
1623 R_028844_SQ_PGM_RESOURCES_PS
,
1624 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
1625 S_028844_PRIME_CACHE_ON_DRAW(1) |
1626 S_028844_STACK_SIZE(rshader
->bc
.nstack
),
1628 r600_pipe_state_add_reg(rstate
,
1629 R_028848_SQ_PGM_RESOURCES_2_PS
,
1630 0x0, 0xFFFFFFFF, NULL
);
1631 r600_pipe_state_add_reg(rstate
,
1632 R_02884C_SQ_PGM_EXPORTS_PS
,
1633 exports_ps
, 0xFFFFFFFF, NULL
);
1635 if (rshader
->uses_kill
) {
1636 /* only set some bits here, the other bits are set in the dsa state */
1637 r600_pipe_state_add_reg(rstate
,
1638 R_02880C_DB_SHADER_CONTROL
,
1639 S_02880C_KILL_ENABLE(1),
1640 S_02880C_KILL_ENABLE(1), NULL
);
1643 r600_pipe_state_add_reg(rstate
,
1644 R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF,
1648 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
1650 struct r600_pipe_state
*rstate
= &shader
->rstate
;
1651 struct r600_shader
*rshader
= &shader
->shader
;
1652 unsigned spi_vs_out_id
[10];
1655 /* clear previous register */
1658 /* so far never got proper semantic id from tgsi */
1659 for (i
= 0; i
< 10; i
++) {
1660 spi_vs_out_id
[i
] = 0;
1662 for (i
= 0; i
< 32; i
++) {
1663 tmp
= i
<< ((i
& 3) * 8);
1664 spi_vs_out_id
[i
/ 4] |= tmp
;
1666 for (i
= 0; i
< 10; i
++) {
1667 r600_pipe_state_add_reg(rstate
,
1668 R_02861C_SPI_VS_OUT_ID_0
+ i
* 4,
1669 spi_vs_out_id
[i
], 0xFFFFFFFF, NULL
);
1672 r600_pipe_state_add_reg(rstate
,
1673 R_0286C4_SPI_VS_OUT_CONFIG
,
1674 S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2),
1676 r600_pipe_state_add_reg(rstate
,
1677 R_028860_SQ_PGM_RESOURCES_VS
,
1678 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
1679 S_028860_STACK_SIZE(rshader
->bc
.nstack
),
1681 r600_pipe_state_add_reg(rstate
,
1682 R_028864_SQ_PGM_RESOURCES_2_VS
,
1683 0x0, 0xFFFFFFFF, NULL
);
1684 r600_pipe_state_add_reg(rstate
,
1685 R_0288A8_SQ_PGM_RESOURCES_FS
,
1686 0x00000000, 0xFFFFFFFF, NULL
);
1687 r600_pipe_state_add_reg(rstate
,
1688 R_02885C_SQ_PGM_START_VS
,
1689 (r600_bo_offset(shader
->bo
)) >> 8, 0xFFFFFFFF, shader
->bo
);
1690 r600_pipe_state_add_reg(rstate
,
1691 R_0288A4_SQ_PGM_START_FS
,
1692 (r600_bo_offset(shader
->bo
)) >> 8, 0xFFFFFFFF, shader
->bo
);
1694 r600_pipe_state_add_reg(rstate
,
1695 R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF,
1699 void *evergreen_create_db_flush_dsa(struct r600_pipe_context
*rctx
)
1701 struct pipe_depth_stencil_alpha_state dsa
;
1702 struct r600_pipe_state
*rstate
;
1704 memset(&dsa
, 0, sizeof(dsa
));
1706 rstate
= rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
1707 r600_pipe_state_add_reg(rstate
,
1708 R_02880C_DB_SHADER_CONTROL
,
1710 S_02880C_DUAL_EXPORT_ENABLE(1), NULL
);
1711 r600_pipe_state_add_reg(rstate
,
1712 R_028000_DB_RENDER_CONTROL
,
1713 S_028000_DEPTH_COPY_ENABLE(1) |
1714 S_028000_STENCIL_COPY_ENABLE(1) |
1715 S_028000_COPY_CENTROID(1),
1716 S_028000_DEPTH_COPY_ENABLE(1) |
1717 S_028000_STENCIL_COPY_ENABLE(1) |
1718 S_028000_COPY_CENTROID(1), NULL
);